From: Luo Jie <quic_luoj@quicinc.com>
To: <andrew@lunn.ch>, <davem@davemloft.net>, <edumazet@google.com>,
<kuba@kernel.org>, <pabeni@redhat.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
<hkallweit1@gmail.com>, <linux@armlinux.org.uk>, <corbet@lwn.net>
Cc: <netdev@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-doc@vger.kernel.org>
Subject: [PATCH v3 5/6] net: phy: at803x: Add qca8084_config_init function
Date: Wed, 15 Nov 2023 22:06:29 +0800 [thread overview]
Message-ID: <20231115140630.10858-6-quic_luoj@quicinc.com> (raw)
In-Reply-To: <20231115140630.10858-1-quic_luoj@quicinc.com>
Configure MSE detect threshold and ADC clock edge invert.
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
drivers/net/phy/at803x.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index f56202f5944d..06a068ca5539 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -280,6 +280,15 @@
#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072
#define QCA8081_PHY_FIFO_RSTN BIT(11)
+/* QCA8084 ADC clock edge */
+#define QCA8084_ADC_CLK_SEL 0x8b80
+#define QCA8084_ADC_CLK_SEL_ACLK GENMASK(7, 4)
+#define QCA8084_ADC_CLK_SEL_ACLK_FALL 0xf
+#define QCA8084_ADC_CLK_SEL_ACLK_RISE 0x0
+
+#define QCA8084_MSE_THRESHOLD 0x800a
+#define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6
+
MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
MODULE_AUTHOR("Matus Ujhelyi");
MODULE_LICENSE("GPL");
@@ -2083,6 +2092,23 @@ static void qca808x_link_change_notify(struct phy_device *phydev)
QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
}
+static int qca8084_config_init(struct phy_device *phydev)
+{
+ int ret;
+
+ /* Invert ADC clock edge */
+ ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL,
+ QCA8084_ADC_CLK_SEL_ACLK,
+ FIELD_PREP(QCA8084_ADC_CLK_SEL_ACLK,
+ QCA8084_ADC_CLK_SEL_ACLK_FALL));
+ if (ret < 0)
+ return ret;
+
+ /* Adjust MSE threshold value to avoid link issue with some link partner */
+ return phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
+ QCA8084_MSE_THRESHOLD, QCA8084_MSE_THRESHOLD_2P5G_VAL);
+}
+
static struct phy_driver at803x_driver[] = {
{
/* Qualcomm Atheros AR8035 */
@@ -2280,6 +2306,7 @@ static struct phy_driver at803x_driver[] = {
.soft_reset = qca808x_soft_reset,
.cable_test_start = qca808x_cable_test_start,
.cable_test_get_status = qca808x_cable_test_get_status,
+ .config_init = qca8084_config_init,
}, };
module_phy_driver(at803x_driver);
--
2.42.0
next prev parent reply other threads:[~2023-11-15 14:09 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-15 14:06 [PATCH v3 0/6] add qca8084 ethernet phy driver Luo Jie
2023-11-15 14:06 ` [PATCH v3 1/6] net: phylink: move phylink_pcs_neg_mode() to phylink.c Luo Jie
2023-11-15 14:14 ` Russell King (Oracle)
2023-11-16 7:32 ` Jie Luo
2023-11-15 14:06 ` [PATCH v3 2/6] net: phy: introduce core support for phy-mode = "10g-qxgmii" Luo Jie
2023-11-15 14:31 ` Conor Dooley
2023-11-16 7:35 ` Jie Luo
2023-11-15 14:06 ` [PATCH v3 3/6] net: phy: at803x: add QCA8084 ethernet phy support Luo Jie
2023-11-15 14:06 ` [PATCH v3 4/6] net: phy: at803x: add the function phydev_id_is_qca808x Luo Jie
2023-11-15 14:06 ` Luo Jie [this message]
2023-11-15 14:06 ` [PATCH v3 6/6] net: phy: qca8084: add qca8084_link_change_notify Luo Jie
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