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([240d:1a:3a7:a400:9a57:aa11:487a:b54f]) by smtp.gmail.com with ESMTPSA id y5-20020a655a05000000b005b3a91e8a94sm765500pgs.76.2023.11.17.00.10.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Nov 2023 00:10:06 -0800 (PST) From: Ryosuke Saito To: jaswinder.singh@linaro.org, ilias.apalodimas@linaro.org, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, masahisa.kojima@linaro.org Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] net: netsec: replace cpu_relax() with timeout handling for register checks Date: Fri, 17 Nov 2023 17:10:02 +0900 Message-ID: <20231117081002.60107-1-ryosuke.saito@linaro.org> X-Mailer: git-send-email 2.41.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The cpu_relax() loops have the potential to hang if the specified register bits are not met on condition. The patch replaces it with usleep_range() and netsec_wait_while_busy() which includes timeout logic. Additionally, if the error condition is met during interrupting DMA transfer, there's no recovery mechanism available. In that case, any frames being sent or received will be discarded, which leads to potential frame loss as indicated in the comments. Signed-off-by: Ryosuke Saito --- drivers/net/ethernet/socionext/netsec.c | 35 ++++++++++++++++--------- 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/socionext/netsec.c b/drivers/net/ethernet/socionext/netsec.c index 0dcd6a568b06..6f9127d30a9a 100644 --- a/drivers/net/ethernet/socionext/netsec.c +++ b/drivers/net/ethernet/socionext/netsec.c @@ -1410,21 +1410,28 @@ static int netsec_reset_hardware(struct netsec_priv *priv, netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, NETSEC_DMA_CTRL_REG_STOP); - while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) & - NETSEC_DMA_CTRL_REG_STOP) - cpu_relax(); - - while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) & - NETSEC_DMA_CTRL_REG_STOP) - cpu_relax(); + if (netsec_wait_while_busy(priv, NETSEC_REG_DMA_HM_CTRL, + NETSEC_DMA_CTRL_REG_STOP) || + netsec_wait_while_busy(priv, NETSEC_REG_DMA_MH_CTRL, + NETSEC_DMA_CTRL_REG_STOP)) { + dev_warn(priv->dev, + "%s: DMA transfer cannot be stopped.\n", + __func__); + /* There is no recovery mechanism in place if this + * error occurs. Frames may be lost. + */ + } } netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET); netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN); netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL); - while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0) - cpu_relax(); + if (netsec_wait_while_busy(priv, NETSEC_REG_COM_INIT, 1)) { + dev_err(priv->dev, + "%s: failed to reset NETSEC.\n", __func__); + return -ETIMEDOUT; + } /* set desc_start addr */ netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP, @@ -1476,9 +1483,13 @@ static int netsec_reset_hardware(struct netsec_priv *priv, netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS); netsec_write(priv, NETSEC_REG_PKT_CTRL, value); - while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) & - NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) - cpu_relax(); + usleep_range(100000, 120000); + + if ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) & + NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) { + dev_warn(priv->dev, + "%s: trans comp timeout.\n", __func__); + } /* clear any pending EMPTY/ERR irq status */ netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0); -- 2.34.1