From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BDF7328C9; Mon, 20 Nov 2023 18:51:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rNbB3zQe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 78D3EC433C8; Mon, 20 Nov 2023 18:51:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1700506310; bh=W2rRlTlnaz7y/dAe1I9YW0SDSX4YDJ+JQ3JUeJOiE0w=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=rNbB3zQeaasobMgO2bQs8/WPmiPXJbIDkO1FZ0gDFmszp9kZh9fbi93mFAZk5KlBd aQ/HZB1Wvnbt+upxuRvZIOsq8nMjK2X2djatxv59SNRwN0GZhzsPHrwnm9Fz+Z21v+ 5sB9bLtKXVL5JM10/YqtRfJH0rXWG2td1ME7SSqFfGLJ30Uc5o2I9DEowX8gvYXuHL PsT0QQvjlMIR78QjEmfipugjDOnyepK7FbfOEuEIfKEIQ/WgBXWBHPWtE1g/bcSgYd wIaDWgZxt1nw3dGOyO8be3NpJWV8nsMSt5HYtzpk0/q57sQba9DWI6UlWYrJs8xbKU DkJx+TKPlcsLg== Date: Mon, 20 Nov 2023 10:51:48 -0800 From: Jakub Kicinski To: Andrew Lunn Cc: Vladimir Oltean , =?UTF-8?B?S8O2cnk=?= Maincent , Florian Fainelli , Broadcom internal kernel review list , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Paolo Abeni , Richard Cochran , Radu Pirea , Jay Vosburgh , Andy Gospodarek , Nicolas Ferre , Claudiu Beznea , Willem de Bruijn , Jonathan Corbet , Horatiu Vultur , UNGLinuxDriver@microchip.com, Simon Horman , Thomas Petazzoni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Maxime Chevallier Subject: Re: [PATCH net-next v7 15/16] net: ethtool: ts: Let the active time stamping layer be selectable Message-ID: <20231120105148.064dc4bd@kernel.org> In-Reply-To: <157c68b0-687e-4333-9d59-fad3f5032345@lunn.ch> References: <20231114-feature_ptp_netnext-v7-0-472e77951e40@bootlin.com> <20231114-feature_ptp_netnext-v7-15-472e77951e40@bootlin.com> <20231118183433.30ca1d1a@kernel.org> <20231120104439.15bfdd09@kmaincent-XPS-13-7390> <20231120105255.cgbart5amkg4efaz@skbuf> <20231120121440.3274d44c@kmaincent-XPS-13-7390> <20231120120601.ondrhbkqpnaozl2q@skbuf> <20231120144929.3375317e@kmaincent-XPS-13-7390> <20231120142316.d2emoaqeej2pg4s3@skbuf> <20231120093723.4d88fb2a@kernel.org> <157c68b0-687e-4333-9d59-fad3f5032345@lunn.ch> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Mon, 20 Nov 2023 19:39:35 +0100 Andrew Lunn wrote: > > What about my use case of having a NIC which can stamp at a low rate > > at the PHY (for PTP) and high rate at the DMA block (for congestion > > control)? Both stamp points have the same PHC index. > > How theoretical is that? To me, it seems more likely you have two PHC. Very practical. mlx5 does this today, based on guessing and private ethtool flags. > The PHY stamping tends to be slow because of the MDIO bus. If the MAC > has fast access to the PHC, it means its not on the MDIO bus. It > probably means you have the PHY integrated into the MAC/SoC, so the > MAC can access it. But if its integrated like this, i don't see why > PHY stamping should be particularly slow. So you can probably use it > for congestion control. And then you don't need DMA stamping. Tx stamps are harder to carry back to the host all the way from the PHY than from the DMA block when DMA completion is signaled. Rx stamps seem much easier to carry down the pipeline but apparently some vendors are incapable of doing that as well. > Do you know of real hardware with a MAC and a PHY sharing a PHC? mlx5 for sure, but other designs, too. PHY, NIC pipeline and PCIe PTM may all need to time stamp from a single time counter.