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Date: Thu, 30 Nov 2023 18:16:11 +0000
From: Simon Horman <horms@kernel.org>
To: Leon Romanovsky <leon@kernel.org>
Cc: Jason Gunthorpe <jgg@nvidia.com>, Shun Hao <shunh@nvidia.com>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, linux-rdma@vger.kernel.org,
	netdev@vger.kernel.org, Paolo Abeni <pabeni@redhat.com>,
	Saeed Mahameed <saeedm@nvidia.com>
Subject: Re: [PATCH mlx5-next 2/5] net/mlx5: Manage ICM type of SW encap
Message-ID: <20231130181611.GL32077@kernel.org>
References: <cover.1701172481.git.leon@kernel.org>
 <37dc4fd78dfa3374ff53aa602f038a2ec76eb069.1701172481.git.leon@kernel.org>
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In-Reply-To: <37dc4fd78dfa3374ff53aa602f038a2ec76eb069.1701172481.git.leon@kernel.org>

On Tue, Nov 28, 2023 at 02:29:46PM +0200, Leon Romanovsky wrote:
> From: Shun Hao <shunh@nvidia.com>
> 
> Support allocate/deallocate the new SW encap ICM type memory.
> The new ICM type is used for encap context allocation managed by SW,
> instead FW. It can increase encap context maximum number and allocation
> speed
> 
> Signed-off-by: Shun Hao <shunh@nvidia.com>
> Signed-off-by: Leon Romanovsky <leonro@nvidia.com>

...

> @@ -164,6 +188,13 @@ int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
>  						log_header_modify_pattern_sw_icm_size);
>  		block_map = dm->header_modify_pattern_sw_icm_alloc_blocks;
>  		break;
> +	case MLX5_SW_ICM_TYPE_SW_ENCAP:
> +		icm_start_addr = MLX5_CAP64_DEV_MEM(dev,
> +						    indirect_encap_sw_icm_start_address);
> +		log_icm_size = MLX5_CAP_DEV_MEM(dev,
> +						log_indirect_encap_sw_icm_size);
> +		block_map = dm->header_encap_sw_icm_alloc_blocks;
> +		break;
>  	default:
>  		return -EINVAL;
>  	}
> @@ -242,6 +273,11 @@ int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type
>  						    header_modify_pattern_sw_icm_start_address);
>  		block_map = dm->header_modify_pattern_sw_icm_alloc_blocks;
>  		break;
> +	case MLX5_SW_ICM_TYPE_SW_ENCAP:
> +		icm_start_addr = MLX5_CAP64_DEV_MEM(dev,
> +						    indirect_encap_sw_icm_start_address);
> +		block_map = dm->header_encap_sw_icm_alloc_blocks;
> +		break;
>  	default:
>  		return -EINVAL;
>  	}

Hi Leon and Shun,

a minor nit from my side: this patch uses MLX5_SW_ICM_TYPE_SW_ENCAP,
but that enum value isn't present until the following patch.