From: Leon Romanovsky <leon@kernel.org>
To: Simon Horman <horms@kernel.org>
Cc: Jason Gunthorpe <jgg@nvidia.com>, Shun Hao <shunh@nvidia.com>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
Paolo Abeni <pabeni@redhat.com>,
Saeed Mahameed <saeedm@nvidia.com>
Subject: Re: [PATCH mlx5-next 2/5] net/mlx5: Manage ICM type of SW encap
Date: Fri, 1 Dec 2023 19:15:00 +0200 [thread overview]
Message-ID: <20231201171500.GD6535@unreal> (raw)
In-Reply-To: <20231130181611.GL32077@kernel.org>
On Thu, Nov 30, 2023 at 06:16:11PM +0000, Simon Horman wrote:
> On Tue, Nov 28, 2023 at 02:29:46PM +0200, Leon Romanovsky wrote:
> > From: Shun Hao <shunh@nvidia.com>
> >
> > Support allocate/deallocate the new SW encap ICM type memory.
> > The new ICM type is used for encap context allocation managed by SW,
> > instead FW. It can increase encap context maximum number and allocation
> > speed
> >
> > Signed-off-by: Shun Hao <shunh@nvidia.com>
> > Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
>
> ...
>
> > @@ -164,6 +188,13 @@ int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
> > log_header_modify_pattern_sw_icm_size);
> > block_map = dm->header_modify_pattern_sw_icm_alloc_blocks;
> > break;
> > + case MLX5_SW_ICM_TYPE_SW_ENCAP:
> > + icm_start_addr = MLX5_CAP64_DEV_MEM(dev,
> > + indirect_encap_sw_icm_start_address);
> > + log_icm_size = MLX5_CAP_DEV_MEM(dev,
> > + log_indirect_encap_sw_icm_size);
> > + block_map = dm->header_encap_sw_icm_alloc_blocks;
> > + break;
> > default:
> > return -EINVAL;
> > }
> > @@ -242,6 +273,11 @@ int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type
> > header_modify_pattern_sw_icm_start_address);
> > block_map = dm->header_modify_pattern_sw_icm_alloc_blocks;
> > break;
> > + case MLX5_SW_ICM_TYPE_SW_ENCAP:
> > + icm_start_addr = MLX5_CAP64_DEV_MEM(dev,
> > + indirect_encap_sw_icm_start_address);
> > + block_map = dm->header_encap_sw_icm_alloc_blocks;
> > + break;
> > default:
> > return -EINVAL;
> > }
>
> Hi Leon and Shun,
>
> a minor nit from my side: this patch uses MLX5_SW_ICM_TYPE_SW_ENCAP,
> but that enum value isn't present until the following patch.
Thanks, it was my mistake to reorder patches, will change to right order
and resubmit.
next prev parent reply other threads:[~2023-12-01 17:15 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-28 12:29 [PATCH mlx5-next 0/5] Expose c0 and SW encap ICM for RDMA Leon Romanovsky
2023-11-28 12:29 ` [PATCH mlx5-next 1/5] net/mlx5: Introduce indirect-sw-encap icm properties Leon Romanovsky
2023-11-28 12:29 ` [PATCH mlx5-next 2/5] net/mlx5: Manage ICM type of SW encap Leon Romanovsky
2023-11-30 18:16 ` Simon Horman
2023-12-01 17:15 ` Leon Romanovsky [this message]
2023-11-28 12:29 ` [PATCH mlx5-next 3/5] RDMA/mlx5: Support handling of SW encap ICM area Leon Romanovsky
2023-11-28 12:29 ` [PATCH mlx5-next 4/5] net/mlx5: E-Switch, expose eswitch manager vport Leon Romanovsky
2023-11-28 12:29 ` [PATCH mlx5-next 5/5] RDMA/mlx5: Expose register c0 for RDMA device Leon Romanovsky
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