From: Jakub Kicinski <kuba@kernel.org>
To: Min Li <lnimi@hotmail.com>
Cc: richardcochran@gmail.com, lee@kernel.org,
linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
Min Li <min.li.xe@renesas.com>
Subject: Re: [PATCH net-next v6 3/6] ptp: clockmatrix: Fix u8 -> u16, DPLL_WF_TIMER and DPLL_WP_TIMER are 2-byte registers
Date: Mon, 4 Dec 2023 18:44:06 -0800 [thread overview]
Message-ID: <20231204184406.4c154e28@kernel.org> (raw)
In-Reply-To: <PH7PR03MB70643CB46D5BA34397181500A082A@PH7PR03MB7064.namprd03.prod.outlook.com>
On Thu, 30 Nov 2023 13:46:31 -0500 Min Li wrote:
> Subject: [PATCH net-next v6 3/6] ptp: clockmatrix: Fix u8 -> u16, DPLL_WF_TIMER and DPLL_WP_TIMER are 2-byte registers
> From: Min Li <min.li.xe@renesas.com>
Thanks for the changes, much easier to review now.
This patch, however, should be squashed with the previous one.
next prev parent reply other threads:[~2023-12-05 2:44 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20231130184634.22577-1-lnimi@hotmail.com>
2023-11-30 18:46 ` [PATCH net-next v6 2/6] ptp: clockmatrix: set write phase timer to 0 when not in PCW mode Min Li
2023-11-30 18:46 ` [PATCH net-next v6 3/6] ptp: clockmatrix: Fix u8 -> u16, DPLL_WF_TIMER and DPLL_WP_TIMER are 2-byte registers Min Li
2023-12-05 2:44 ` Jakub Kicinski [this message]
2023-11-30 18:46 ` [PATCH net-next v6 4/6] ptp: clockmatrix: dco input-to-output delay is 20 FOD cycles + 8ns Min Li
2023-12-05 2:44 ` Jakub Kicinski
2023-11-30 18:46 ` [PATCH net-next v6 5/6] ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO] Min Li
2023-11-30 18:46 ` [PATCH net-next v6 6/6] ptp: clockmatrix: move register and firmware related definition to idt8a340_reg.h Min Li
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