From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8D4A41766 for ; Thu, 7 Dec 2023 14:29:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uXBkyx03" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06ACEC433A9; Thu, 7 Dec 2023 14:29:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701959348; bh=TqlKfFKOLLV8/pff7AZHnAMNzvKwpCh5nT2X8mByeJk=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=uXBkyx03W4Uuv9404zBCC/K1KLScFaO4qf3eWS4PQNfQfe4mrafoBjEt1pGH74/+G 2pOWvzS/4lCCj46zVXsrM78Emf3o+4xWuGYZEwfiYJ1Co1ptYNOaQ1FWMSVD32tdXr sdhS9gXAEZMhYQn93jmEDMaZw90Az24dFJsV9asJmmVR/Ka1pIGXWrRVGVqDCcxUyx fkKS7HJ304ESaPXUtKPJ19zblqOneEbehpEx0gfxHqHuobLIZFIAXMrl5RNcIsrhDi 7pX48TbcOJZY0aP4ZJppFrF8uIh23mculrE5n48KJdyfc/7DkDRuYTZNl5hwbVsMwj v1X91WTWd4oUQ== Date: Thu, 7 Dec 2023 14:29:04 +0000 From: Lee Jones To: Min Li Cc: richardcochran@gmail.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Min Li Subject: Re: [PATCH net-next v2 2/2] ptp: add FemtoClock3 Wireless as ptp hardware clock Message-ID: <20231207142904.GE8867@google.com> References: <20231129204806.14539-1-lnimi@hotmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, 29 Nov 2023, Min Li wrote: > From: Min Li > > The RENESAS FemtoClock3 Wireless is a high-performance jitter attenuator, > frequency translator, and clock synthesizer. The device is comprised of 3 > digital PLLs (DPLL) to track CLKIN inputs and three independent low phase > noise fractional output dividers (FOD) that output low phase noise clocks. > > FemtoClock3 supports one Time Synchronization (Time Sync) channel to enable > an external processor to control the phase and frequency of the Time Sync > channel and to take phase measurements using the TDC. Intended applications > are synchronization using the precision time protocol (PTP) and > synchronization with 0.5 Hz and 1 Hz signals from GNSS. > > Signed-off-by: Min Li > --- > drivers/ptp/Kconfig | 12 + > drivers/ptp/Makefile | 1 + > drivers/ptp/ptp_fc3.c | 1036 ++++++++++++++++++++++++++++ > drivers/ptp/ptp_fc3.h | 45 ++ > include/linux/mfd/idtRC38xxx_reg.h | 273 ++++++++ Acked-by: Lee Jones > 5 files changed, 1367 insertions(+) > create mode 100644 drivers/ptp/ptp_fc3.c > create mode 100644 drivers/ptp/ptp_fc3.h > create mode 100644 include/linux/mfd/idtRC38xxx_reg.h -- Lee Jones [李琼斯]