From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64BFC32C7A; Fri, 8 Dec 2023 16:59:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VV9pLQrd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BC84DC433C8; Fri, 8 Dec 2023 16:58:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1702054742; bh=h0JkAKzYF1eCC3VCUFet/wUloQePgRqJtpyUOwrwHs8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=VV9pLQrduCHZxqG1gp2gsdESd89zqUJ8T/ztaw9WJVw7s21G8m8muHVlDot3+Gf40 65myTt3MriTs13uBBjQtrCxREZctMcuNBTs7qnGtm24UGeLP0ZZIHk1cDe2BqhGoG5 6n9im+9fMvwh7N5TggcZFvP6o6io3PyaZcgCS1iYmLOW+edW4FBFuzCKI3FXRVqssq gBwKneVYebD7Q/ruS5A6bejC3WL/NZroDaT74VKIptNNKVPIXywOlsdC0uq209XkCP And+nEwHTfPBhvawAtMy7NfdJGgiRcPQgMJR+qF0p4bLHgxxd7/yjMuh2w1hz5BSiS rFmD07v7UUqtw== Date: Fri, 8 Dec 2023 16:58:55 +0000 From: Simon Horman To: Raphael Gallais-Pou Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Richard Cochran , devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, netdev@vger.kernel.org Subject: Re: [PATCH v2 3/4] drm/stm: dsi: expose DSI PHY internal clock Message-ID: <20231208165855.GA8459@kernel.org> References: <20231204101113.276368-1-raphael.gallais-pou@foss.st.com> <20231204101113.276368-4-raphael.gallais-pou@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231204101113.276368-4-raphael.gallais-pou@foss.st.com> On Mon, Dec 04, 2023 at 11:11:12AM +0100, Raphael Gallais-Pou wrote: ... > @@ -514,18 +675,40 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev) > dsi->lane_max_kbps *= 2; > } > > - dw_mipi_dsi_stm_plat_data.base = dsi->base; > - dw_mipi_dsi_stm_plat_data.priv_data = dsi; > + dsi->pdata = *pdata; > + dsi->pdata.base = dsi->base; > + dsi->pdata.priv_data = dsi; > + > + dsi->pdata.max_data_lanes = 2; > + dsi->pdata.phy_ops = &dw_mipi_dsi_stm_phy_ops; > > platform_set_drvdata(pdev, dsi); > > - dsi->dsi = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data); > + dsi->dsi = dw_mipi_dsi_probe(pdev, &dsi->pdata); > if (IS_ERR(dsi->dsi)) { > ret = PTR_ERR(dsi->dsi); > dev_err_probe(dev, ret, "Failed to initialize mipi dsi host\n"); > goto err_dsi_probe; > } > > + /* > + * We need to wait for the generic bridge to probe before enabling and > + * register the internal pixel clock. > + */ > + ret = clk_prepare_enable(dsi->pclk); > + if (ret) { > + DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__); > + goto err_dsi_probe; > + } > + > + ret = dw_mipi_dsi_clk_register(dsi, dev); > + if (ret) { > + DRM_ERROR("Failed to register DSI pixel clock: %d\n", ret); Hi Raphael, Does clk_disable_unprepare(dsi->pclk) need to be added to this unwind chain? Flagged by Smatch. > + goto err_dsi_probe; > + } > + > + clk_disable_unprepare(dsi->pclk); > + > return 0; > > err_dsi_probe: ...