RE: [EXT] Re: [net v3 PATCH 1/1] net: mvpp2: clear BM pool before initialization

Jenishkumar Patel [C]
2024-01-19T03:58:32Z

-----Original Message-----
From: Maxime Chevallier <maxime.chevallier@bootlin.com>
Sent: Thursday, January 18, 2024 8:21 PM
To: Jenishkumar Patel [C] <jpatel2@marvell.com>
Cc: marcin.s.wojtas@gmail.com; linux@armlinux.org.uk; davem@davemloft.net; edumazet@google.com; kuba@kernel.org; pabeni@redhat.com; netdev@vger.kernel.org; linux-kernel@vger.kernel.org; Antoine Tenart <atenart@kernel.org>
Subject: [EXT] Re: [net v3 PATCH 1/1] net: mvpp2: clear BM pool before initialization

External Email

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Hello,

On Thu, 18 Jan 2024 00:14:47 -0800
Jenishkumar Maheshbhai Patel <jpatel2@marvell.com> wrote:

> Register value persist after booting the kernel using kexec which
> results in kernel panic. Thus clear the BM pool registers before
> initialisation to fix the issue.

[...]

> +/* Cleanup pool before actual initialization in the OS */ static void
> +mvpp2_bm_pool_cleanup(struct mvpp2 *priv, int pool_id) {
> + u32 val;
> + int i;
> + unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());

Please sort these lines with the longest line at the top, following the reverse christmas-tree style.
Thank you for the input will make the changes in v4
> +
> + /* Drain the BM from all possible residues left by firmware */
> + for (i = 0; i < MVPP2_BM_POOL_SIZE_MAX; i++)
> + mvpp2_thread_read(priv, thread, MVPP2_BM_PHY_ALLOC_REG(pool_id));

Since you don't need to use the thread-based accessors after this, you can call put_cpu() right now to avoid keeping preemption disabled unnecessarily for too long.
Thank you for the input will make the changes in v4
> + /* Stop the BM pool */
> + val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(pool_id));
> + val |= MVPP2_BM_STOP_MASK;
> + mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(pool_id), val);
> +
> + /* Mask BM all interrupts */
> + mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(pool_id), 0);
> +
> + /* Clear BM cause register */
> + mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(pool_id), 0);

These two registers dealing with interrupt masking and cause are already cleared in mvpp2_bm_init(), not shown in the diff context, so either you can remove these or the ones in mvpp2_bm_init().
Thank you for the input will make the changes in v4
> + put_cpu();
> +}
> +
> static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv) {
> enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
> int i, err, poolnum = MVPP2_BM_POOLS_NUM;
> struct mvpp2_port *port;
>
> + if (priv->percpu_pools)
> + poolnum = mvpp2_get_nrxqs(priv) * 2;
> +
> + /* Clean up the pool state in case it contains stale state */
> + for (i = 0; i < poolnum; i++)
> + mvpp2_bm_pool_cleanup(priv, i);
> +
> if (priv->percpu_pools) {
> for (i = 0; i < priv->port_count; i++) {
> port = priv->port_list[i];
> @@ -629,7 +661,6 @@ static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
> }
> }
>
> - poolnum = mvpp2_get_nrxqs(priv) * 2;
> for (i = 0; i < poolnum; i++) {
> /* the pool in use */
> int pn = i / (poolnum / 2);

Thanks,

Maxime