[PATCH v5 net-next 0/5] amd-xgbe: add support for AMD Crater

[PATCH v5 net-next 0/5] amd-xgbe: add support for AMD Crater

[Raju Rangoju]

Add support for a new AMD Ethernet device called "Crater". It has a new
PCI ID, add this to the current list of supported devices in the
amd-xgbe devices. Also, the BAR1 addresses cannot be used to access the
PCS registers on Crater platform, use the indirect addressing via SMN
instead.

Changes since v4:
- split the patches as per Simon's suggestion
 
Changes since v3:
- Club patches 2 and 3 to avoid bisect issues.
- Modified license in xgbe-smn.h to match the license in all the other files.
- Modified the function get_pcs_index_and_offset() to reflect the name.

Raju Rangoju (5):
  amd-xgbe: reorganize the code of XPCS access
  amd-xgbe: reorganize the xgbe_pci_probe() code path
  amd-xgbe: add support for new XPCS routines
  amd-xgbe: Add XGBE_XPCS_ACCESS_V3 support to xgbe_pci_probe()
  amd-xgbe: add support for new pci device id 0x1641

 drivers/net/ethernet/amd/xgbe/xgbe-common.h |   5 +
 drivers/net/ethernet/amd/xgbe/xgbe-dev.c    | 124 ++++++++++++-----
 drivers/net/ethernet/amd/xgbe/xgbe-pci.c    |  83 +++++++++---
 drivers/net/ethernet/amd/xgbe/xgbe-smn.h    | 139 ++++++++++++++++++++
 drivers/net/ethernet/amd/xgbe/xgbe.h        |  11 ++
 5 files changed, 305 insertions(+), 57 deletions(-)
 create mode 100644 drivers/net/ethernet/amd/xgbe/xgbe-smn.h

-- 
2.34.1

[PATCH v5 net-next 1/5] amd-xgbe: reorganize the code of XPCS access

[Raju Rangoju]

The xgbe_{read/write}_mmd_regs_v* functions have common code which can
be moved to helper functions. Add new helper functions to calculate the
mmd_address for v1/v2 of xpcs access.

Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
 drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 63 ++++++++++--------------
 1 file changed, 27 insertions(+), 36 deletions(-)

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
index f393228d41c7..197da2993471 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
@@ -1150,18 +1150,17 @@ static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
 	return 0;
 }
 
-static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
-				 int mmd_reg)
+static unsigned int get_mmd_address(struct xgbe_prv_data *pdata, int mmd_reg)
 {
-	unsigned long flags;
-	unsigned int mmd_address, index, offset;
-	int mmd_data;
-
-	if (mmd_reg & XGBE_ADDR_C45)
-		mmd_address = mmd_reg & ~XGBE_ADDR_C45;
-	else
-		mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
+	return (mmd_reg & XGBE_ADDR_C45) ?
+		mmd_reg & ~XGBE_ADDR_C45 :
+		(pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
+}
 
+static void get_pcs_index_and_offset(struct xgbe_prv_data *pdata,
+				     unsigned int mmd_address,
+				     unsigned int *index, unsigned int *offset)
+{
 	/* The PCS registers are accessed using mmio. The underlying
 	 * management interface uses indirect addressing to access the MMD
 	 * register sets. This requires accessing of the PCS register in two
@@ -1172,8 +1171,20 @@ static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
 	 * offset 1 bit and reading 16 bits of data.
 	 */
 	mmd_address <<= 1;
-	index = mmd_address & ~pdata->xpcs_window_mask;
-	offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
+	*index = mmd_address & ~pdata->xpcs_window_mask;
+	*offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
+}
+
+static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
+				 int mmd_reg)
+{
+	unsigned long flags;
+	unsigned int mmd_address, index, offset;
+	int mmd_data;
+
+	mmd_address = get_mmd_address(pdata, mmd_reg);
+
+	get_pcs_index_and_offset(pdata, mmd_address, &index, &offset);
 
 	spin_lock_irqsave(&pdata->xpcs_lock, flags);
 	XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index);
@@ -1189,23 +1200,9 @@ static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
 	unsigned long flags;
 	unsigned int mmd_address, index, offset;
 
-	if (mmd_reg & XGBE_ADDR_C45)
-		mmd_address = mmd_reg & ~XGBE_ADDR_C45;
-	else
-		mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
+	mmd_address = get_mmd_address(pdata, mmd_reg);
 
-	/* The PCS registers are accessed using mmio. The underlying
-	 * management interface uses indirect addressing to access the MMD
-	 * register sets. This requires accessing of the PCS register in two
-	 * phases, an address phase and a data phase.
-	 *
-	 * The mmio interface is based on 16-bit offsets and values. All
-	 * register offsets must therefore be adjusted by left shifting the
-	 * offset 1 bit and writing 16 bits of data.
-	 */
-	mmd_address <<= 1;
-	index = mmd_address & ~pdata->xpcs_window_mask;
-	offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
+	get_pcs_index_and_offset(pdata, mmd_address, &index, &offset);
 
 	spin_lock_irqsave(&pdata->xpcs_lock, flags);
 	XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index);
@@ -1220,10 +1217,7 @@ static int xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad,
 	unsigned int mmd_address;
 	int mmd_data;
 
-	if (mmd_reg & XGBE_ADDR_C45)
-		mmd_address = mmd_reg & ~XGBE_ADDR_C45;
-	else
-		mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
+	mmd_address = get_mmd_address(pdata, mmd_reg);
 
 	/* The PCS registers are accessed using mmio. The underlying APB3
 	 * management interface uses indirect addressing to access the MMD
@@ -1248,10 +1242,7 @@ static void xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad,
 	unsigned int mmd_address;
 	unsigned long flags;
 
-	if (mmd_reg & XGBE_ADDR_C45)
-		mmd_address = mmd_reg & ~XGBE_ADDR_C45;
-	else
-		mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
+	mmd_address = get_mmd_address(pdata, mmd_reg);
 
 	/* The PCS registers are accessed using mmio. The underlying APB3
 	 * management interface uses indirect addressing to access the MMD
-- 
2.34.1

[PATCH v5 net-next 2/5] amd-xgbe: reorganize the xgbe_pci_probe() code path

[Raju Rangoju]

Reorganize the xgbe_pci_probe() code path to convert if/else statements
to switch case to help add future code. This helps code look cleaner.

Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
 drivers/net/ethernet/amd/xgbe/xgbe-pci.c | 35 ++++++++++++++----------
 drivers/net/ethernet/amd/xgbe/xgbe.h     |  4 +++
 2 files changed, 25 insertions(+), 14 deletions(-)

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
index f409d7bd1f1e..18d1cc16c919 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
@@ -274,20 +274,27 @@ static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 
 	/* Set the PCS indirect addressing definition registers */
 	rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
-	if (rdev &&
-	    (rdev->vendor == PCI_VENDOR_ID_AMD) && (rdev->device == 0x15d0)) {
-		pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
-		pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
-	} else if (rdev && (rdev->vendor == PCI_VENDOR_ID_AMD) &&
-		   (rdev->device == 0x14b5)) {
-		pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF;
-		pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT;
-
-		/* Yellow Carp devices do not need cdr workaround */
-		pdata->vdata->an_cdr_workaround = 0;
-
-		/* Yellow Carp devices do not need rrc */
-		pdata->vdata->enable_rrc = 0;
+	if (rdev && rdev->vendor == PCI_VENDOR_ID_AMD) {
+		switch (rdev->device) {
+		case XGBE_RV_PCI_DEVICE_ID:
+			pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
+			pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
+			break;
+		case XGBE_YC_PCI_DEVICE_ID:
+			pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF;
+			pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT;
+
+			/* Yellow Carp devices do not need cdr workaround */
+			pdata->vdata->an_cdr_workaround = 0;
+
+			/* Yellow Carp devices do not need rrc */
+			pdata->vdata->enable_rrc = 0;
+			break;
+		default:
+			pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
+			pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
+			break;
+		}
 	} else {
 		pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
 		pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index f01a1e566da6..eda909235d48 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -347,6 +347,10 @@
 		    (_src)->link_modes._sname,		\
 		    __ETHTOOL_LINK_MODE_MASK_NBITS)
 
+/* XGBE PCI device id */
+#define XGBE_RV_PCI_DEVICE_ID	0x15d0
+#define XGBE_YC_PCI_DEVICE_ID	0x14b5
+
 struct xgbe_prv_data;
 
 struct xgbe_packet_data {
-- 
2.34.1

[PATCH v5 net-next 3/5] amd-xgbe: add support for new XPCS routines

[Raju Rangoju]

Add the necessary support to enable Crater ethernet device. Since the
BAR1 address cannot be used to access the XPCS registers on Crater, use
the smn functions.

Some of the ethernet add-in-cards have dual PHY but share a single MDIO
line (between the ports). In such cases, link inconsistencies are
noticed during the heavy traffic and during reboot stress tests. Using
smn calls helps avoid such race conditions.

Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
 drivers/net/ethernet/amd/xgbe/xgbe-dev.c |  61 ++++++++++
 drivers/net/ethernet/amd/xgbe/xgbe-smn.h | 139 +++++++++++++++++++++++
 drivers/net/ethernet/amd/xgbe/xgbe.h     |   6 +
 3 files changed, 206 insertions(+)
 create mode 100644 drivers/net/ethernet/amd/xgbe/xgbe-smn.h

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
index 197da2993471..0c7ef15860a9 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
@@ -123,6 +123,7 @@
 
 #include "xgbe.h"
 #include "xgbe-common.h"
+#include "xgbe-smn.h"
 
 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata)
 {
@@ -1175,6 +1176,60 @@ static void get_pcs_index_and_offset(struct xgbe_prv_data *pdata,
 	*offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
 }
 
+static int xgbe_read_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
+				 int mmd_reg)
+{
+	unsigned int mmd_address, index, offset;
+	unsigned long flags;
+	int mmd_data;
+
+	mmd_address = get_mmd_address(pdata, mmd_reg);
+
+	get_pcs_index_and_offset(pdata, mmd_address, &index, &offset);
+
+	spin_lock_irqsave(&pdata->xpcs_lock, flags);
+	amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), index);
+	amd_smn_read(0, pdata->smn_base + offset, &mmd_data);
+	mmd_data = (offset % 4) ? FIELD_GET(XGBE_GEN_HI_MASK, mmd_data) :
+				  FIELD_GET(XGBE_GEN_LO_MASK, mmd_data);
+
+	spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
+
+	return mmd_data;
+}
+
+static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
+				   int mmd_reg, int mmd_data)
+{
+	unsigned int pci_mmd_data, hi_mask, lo_mask;
+	unsigned int mmd_address, index, offset;
+	unsigned long flags;
+
+	mmd_address = get_mmd_address(pdata, mmd_reg);
+
+	get_pcs_index_and_offset(pdata, mmd_address, &index, &offset);
+
+	spin_lock_irqsave(&pdata->xpcs_lock, flags);
+	amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), index);
+	amd_smn_read(0, pdata->smn_base + offset, &pci_mmd_data);
+
+	if (offset % 4) {
+		hi_mask = FIELD_PREP(XGBE_GEN_HI_MASK, mmd_data);
+		lo_mask = FIELD_GET(XGBE_GEN_LO_MASK, pci_mmd_data);
+	} else {
+		hi_mask = FIELD_PREP(XGBE_GEN_HI_MASK,
+				     FIELD_GET(XGBE_GEN_HI_MASK, pci_mmd_data));
+		lo_mask = FIELD_GET(XGBE_GEN_LO_MASK, mmd_data);
+	}
+
+	pci_mmd_data = hi_mask | lo_mask;
+
+	amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), index);
+	amd_smn_write(0, (pdata->smn_base + offset), pci_mmd_data);
+
+	spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
+}
+
 static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
 				 int mmd_reg)
 {
@@ -1269,6 +1324,9 @@ static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
 	case XGBE_XPCS_ACCESS_V2:
 	default:
 		return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg);
+
+	case XGBE_XPCS_ACCESS_V3:
+		return xgbe_read_mmd_regs_v3(pdata, prtad, mmd_reg);
 	}
 }
 
@@ -1282,6 +1340,9 @@ static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
 	case XGBE_XPCS_ACCESS_V2:
 	default:
 		return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data);
+
+	case XGBE_XPCS_ACCESS_V3:
+		return xgbe_write_mmd_regs_v3(pdata, prtad, mmd_reg, mmd_data);
 	}
 }
 
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-smn.h b/drivers/net/ethernet/amd/xgbe/xgbe-smn.h
new file mode 100644
index 000000000000..a1fb499b8637
--- /dev/null
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-smn.h
@@ -0,0 +1,139 @@
+/*
+ * AMD 10Gb Ethernet driver
+ *
+ * This file is available to you under your choice of the following two
+ * licenses:
+ *
+ * License 1: GPLv2
+ *
+ * Copyright (c) 2024 Advanced Micro Devices, Inc.
+ *
+ * This file is free software; you may copy, redistribute and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
+ *     and you.
+ *
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
+ *     under any End User Software License Agreement or Agreement for Licensed
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
+ *     granted, free of charge, to any person obtaining a copy of this software
+ *     annotated with this license and the Software, to deal in the Software
+ *     without restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ *     of the Software, and to permit persons to whom the Software is furnished
+ *     to do so, subject to the following conditions:
+ *
+ *     The above copyright notice and this permission notice shall be included
+ *     in all copies or substantial portions of the Software.
+ *
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *     THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * License 2: Modified BSD
+ *
+ * Copyright (c) 2024 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
+ *     and you.
+ *
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
+ *     under any End User Software License Agreement or Agreement for Licensed
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
+ *     granted, free of charge, to any person obtaining a copy of this software
+ *     annotated with this license and the Software, to deal in the Software
+ *     without restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ *     of the Software, and to permit persons to whom the Software is furnished
+ *     to do so, subject to the following conditions:
+ *
+ *     The above copyright notice and this permission notice shall be included
+ *     in all copies or substantial portions of the Software.
+ *
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *     THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *     Author: Raju Rangoju <Raju.Rangoju@amd.com>
+ */
+
+#ifndef __SMN_H__
+#define __SMN_H__
+
+#ifdef CONFIG_AMD_NB
+
+#include <asm/amd_nb.h>
+
+#else
+
+static inline int amd_smn_write(u16 node, u32 address, u32 value)
+{
+	return -ENODEV;
+}
+
+static inline int amd_smn_read(u16 node, u32 address, u32 *value)
+{
+	return -ENODEV;
+}
+
+#endif
+#endif
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index eda909235d48..60882a46fe50 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -351,6 +351,10 @@
 #define XGBE_RV_PCI_DEVICE_ID	0x15d0
 #define XGBE_YC_PCI_DEVICE_ID	0x14b5
 
+ /* Generic low and high masks */
+#define XGBE_GEN_HI_MASK	GENMASK(31, 16)
+#define XGBE_GEN_LO_MASK	GENMASK(15, 0)
+
 struct xgbe_prv_data;
 
 struct xgbe_packet_data {
@@ -569,6 +573,7 @@ enum xgbe_speed {
 enum xgbe_xpcs_access {
 	XGBE_XPCS_ACCESS_V1 = 0,
 	XGBE_XPCS_ACCESS_V2,
+	XGBE_XPCS_ACCESS_V3,
 };
 
 enum xgbe_an_mode {
@@ -1060,6 +1065,7 @@ struct xgbe_prv_data {
 	struct device *dev;
 	struct platform_device *phy_platdev;
 	struct device *phy_dev;
+	unsigned int smn_base;
 
 	/* Version related data */
 	struct xgbe_version_data *vdata;
-- 
2.34.1

Re: [PATCH v5 net-next 3/5] amd-xgbe: add support for new XPCS routines

[Jacob Keller]

On 2/14/2024 7:48 AM, Raju Rangoju wrote:
> +/*
> + * AMD 10Gb Ethernet driver
> + *
> + * This file is available to you under your choice of the following two
> + * licenses:
> + *
> + * License 1: GPLv2

<snip>

> + * License 2: Modified BSD
> + *

<snip>

> + *
> + *     Author: Raju Rangoju <Raju.Rangoju@amd.com>
> + */
I'm not sure if its a strict policy but I thought Linux kernel switched
to using SPDX headers instead of fully copying license information
within each file...

See: Documentation/process/license-rules.rst:

> An alternative to boilerplate text is the use of Software Package Data
> Exchange (SPDX) license identifiers in each source file.  SPDX license
> identifiers are machine parsable and precise shorthands for the license
> under which the content of the file is contributed.  SPDX license
> identifiers are managed by the SPDX Workgroup at the Linux Foundation and
> have been agreed on by partners throughout the industry, tool vendors, and
> legal teams.  For further information see https://spdx.org/
> 
> The Linux kernel requires the precise SPDX identifier in all source files.
> The valid identifiers used in the kernel are explained in the section
> `License identifiers`_ and have been retrieved from the official SPDX
> license list at https://spdx.org/licenses/ along with the license texts.

This implies to me that we should prefer SPDX license identifiers,
rather than including the boilerplate here.

Re: [PATCH v5 net-next 3/5] amd-xgbe: add support for new XPCS routines

[Jakub Kicinski]

Hi Greg!

Would you be able to give us your "no" vs "whatever" on the license
shenanigans below? First time I'm spotting this sort of a thing,
although it looks like we already have copies of this exact text
in the tree :(

On Wed, 14 Feb 2024 21:18:40 +0530 Raju Rangoju wrote:
> + * AMD 10Gb Ethernet driver
> + *
> + * This file is available to you under your choice of the following two
> + * licenses:
> + *
> + * License 1: GPLv2
> + *
> + * Copyright (c) 2024 Advanced Micro Devices, Inc.
> + *
> + * This file is free software; you may copy, redistribute and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or (at
> + * your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + * This file incorporates work covered by the following copyright and
> + * permission notice:
> + *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
> + *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
> + *     Inc. unless otherwise expressly agreed to in writing between Synopsys
> + *     and you.
> + *
> + *     The Software IS NOT an item of Licensed Software or Licensed Product
> + *     under any End User Software License Agreement or Agreement for Licensed
> + *     Product with Synopsys or any supplement thereto.  Permission is hereby
> + *     granted, free of charge, to any person obtaining a copy of this software
> + *     annotated with this license and the Software, to deal in the Software
> + *     without restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
> + *     of the Software, and to permit persons to whom the Software is furnished
> + *     to do so, subject to the following conditions:
> + *
> + *     The above copyright notice and this permission notice shall be included
> + *     in all copies or substantial portions of the Software.
> + *
> + *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
> + *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
> + *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
> + *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
> + *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
> + *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
> + *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
> + *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
> + *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
> + *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
> + *     THE POSSIBILITY OF SUCH DAMAGE.
> + *
> + *
> + * License 2: Modified BSD
> + *
> + * Copyright (c) 2024 Advanced Micro Devices, Inc.
> + * All rights reserved.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions are met:
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above copyright
> + *       notice, this list of conditions and the following disclaimer in the
> + *       documentation and/or other materials provided with the distribution.
> + *     * Neither the name of Advanced Micro Devices, Inc. nor the
> + *       names of its contributors may be used to endorse or promote products
> + *       derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
> + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + *
> + * This file incorporates work covered by the following copyright and
> + * permission notice:
> + *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
> + *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
> + *     Inc. unless otherwise expressly agreed to in writing between Synopsys
> + *     and you.
> + *
> + *     The Software IS NOT an item of Licensed Software or Licensed Product
> + *     under any End User Software License Agreement or Agreement for Licensed
> + *     Product with Synopsys or any supplement thereto.  Permission is hereby
> + *     granted, free of charge, to any person obtaining a copy of this software
> + *     annotated with this license and the Software, to deal in the Software
> + *     without restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
> + *     of the Software, and to permit persons to whom the Software is furnished
> + *     to do so, subject to the following conditions:
> + *
> + *     The above copyright notice and this permission notice shall be included
> + *     in all copies or substantial portions of the Software.
> + *
> + *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
> + *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
> + *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
> + *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
> + *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
> + *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
> + *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
> + *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
> + *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
> + *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
> + *     THE POSSIBILITY OF SUCH DAMAGE.

Re: [PATCH v5 net-next 3/5] amd-xgbe: add support for new XPCS routines

[Greg Kroah-Hartman]

On Wed, Feb 14, 2024 at 05:27:30PM -0800, Jakub Kicinski wrote:
> Hi Greg!
> 
> Would you be able to give us your "no" vs "whatever" on the license
> shenanigans below? First time I'm spotting this sort of a thing,
> although it looks like we already have copies of this exact text
> in the tree :(

Ugh, that's a mess:

> 
> On Wed, 14 Feb 2024 21:18:40 +0530 Raju Rangoju wrote:
> > + * AMD 10Gb Ethernet driver

First off, checkpatch should have complained about no SPDX line on this
file, so that's a big NACK from me for this patch to start with.  Just
don't do that.

second, this whole thing can be distilled down to a single "GPLv2-only"
spdx line.  Don't create special, custom, licenses like "modified BSD"
if you expect a file to be able to be merged into the kernel tree,
that's not ok.

AMD developers, please work with your lawyers to clean this all up, and
remove ALL of that boilerplate license text, all you need is one simple
SPDX line that describes the license.

Also, I will push back hard and say "no dual license files, UNLESS you
have a lawyer sign-off on the patch" as the issues involved in doing
that are non-trivial, and require work on the legal side of your company
to ensure that they work properly.  That is work your lawyer is signing
up to do, so they need to be responsible for it.

thanks,

greg k-h

Re: [PATCH v5 net-next 3/5] amd-xgbe: add support for new XPCS routines

[Raju Rangoju]

On 2/15/2024 1:15 PM, Greg Kroah-Hartman wrote:
> On Wed, Feb 14, 2024 at 05:27:30PM -0800, Jakub Kicinski wrote:
>> Hi Greg!
>>
>> Would you be able to give us your "no" vs "whatever" on the license
>> shenanigans below? First time I'm spotting this sort of a thing,
>> although it looks like we already have copies of this exact text
>> in the tree :(
> 
> Ugh, that's a mess:
> 
>>
>> On Wed, 14 Feb 2024 21:18:40 +0530 Raju Rangoju wrote:
>>> + * AMD 10Gb Ethernet driver
> 
> First off, checkpatch should have complained about no SPDX line on this
> file, so that's a big NACK from me for this patch to start with.  Just
> don't do that.
> 
> second, this whole thing can be distilled down to a single "GPLv2-only"
> spdx line.  Don't create special, custom, licenses like "modified BSD"
> if you expect a file to be able to be merged into the kernel tree,
> that's not ok.
> 
> AMD developers, please work with your lawyers to clean this all up, and
> remove ALL of that boilerplate license text, all you need is one simple
> SPDX line that describes the license.
>

Hi Greg,

Thanks for your inputs on this. We will work with our legal team to see 
if we can use GPLv2 instead of dual license.

Thanks,
Raju

> Also, I will push back hard and say "no dual license files, UNLESS you
> have a lawyer sign-off on the patch" as the issues involved in doing
> that are non-trivial, and require work on the legal side of your company
> to ensure that they work properly.  That is work your lawyer is signing
> up to do, so they need to be responsible for it.
> 
> thanks,
> 
> greg k-h

Re: [PATCH v5 net-next 3/5] amd-xgbe: add support for new XPCS routines

[Andrew Lunn]

> Hi Greg,
> 
> Thanks for your inputs on this. We will work with our legal team to see if
> we can use GPLv2 instead of dual license.

Another option would be to throw away all this code and just use
phylink, which already has a driver for XPCS. Might be cheaper than
talking to lawyers :-)

	 Andrew

[PATCH v5 net-next 4/5] amd-xgbe: Add XGBE_XPCS_ACCESS_V3 support to xgbe_pci_probe()

[Raju Rangoju]

A new version of XPCS access routines have been introduced, add the
support to xgbe_pci_probe() to use these routines.

Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
 drivers/net/ethernet/amd/xgbe/xgbe-common.h |  5 ++++
 drivers/net/ethernet/amd/xgbe/xgbe-pci.c    | 30 ++++++++++++++++-----
 drivers/net/ethernet/amd/xgbe/xgbe.h        |  1 +
 3 files changed, 29 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
index 3b70f6737633..33ed361ff018 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
@@ -900,6 +900,11 @@
 #define PCS_V2_RV_WINDOW_SELECT		0x1064
 #define PCS_V2_YC_WINDOW_DEF		0x18060
 #define PCS_V2_YC_WINDOW_SELECT		0x18064
+#define PCS_V3_RN_WINDOW_DEF		0xf8078
+#define PCS_V3_RN_WINDOW_SELECT		0xf807c
+
+#define PCS_RN_SMN_BASE_ADDR		0x11e00000
+#define PCS_RN_PORT_ADDR_SIZE		0x100000
 
 /* PCS register entry bit positions and sizes */
 #define PCS_V2_WINDOW_DEF_OFFSET_INDEX	6
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
index 18d1cc16c919..340a7f16c0cc 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
@@ -118,6 +118,7 @@
 #include <linux/device.h>
 #include <linux/pci.h>
 #include <linux/log2.h>
+#include "xgbe-smn.h"
 
 #include "xgbe.h"
 #include "xgbe-common.h"
@@ -207,14 +208,14 @@ static int xgbe_config_irqs(struct xgbe_prv_data *pdata)
 
 static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
-	struct xgbe_prv_data *pdata;
-	struct device *dev = &pdev->dev;
 	void __iomem * const *iomap_table;
-	struct pci_dev *rdev;
+	unsigned int port_addr_size, reg;
+	struct device *dev = &pdev->dev;
+	struct xgbe_prv_data *pdata;
 	unsigned int ma_lo, ma_hi;
-	unsigned int reg;
-	int bar_mask;
-	int ret;
+	struct pci_dev *rdev;
+	int bar_mask, ret;
+	u32 address;
 
 	pdata = xgbe_alloc_pdata(dev);
 	if (IS_ERR(pdata)) {
@@ -290,6 +291,10 @@ static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 			/* Yellow Carp devices do not need rrc */
 			pdata->vdata->enable_rrc = 0;
 			break;
+		case XGBE_RN_PCI_DEVICE_ID:
+			pdata->xpcs_window_def_reg = PCS_V3_RN_WINDOW_DEF;
+			pdata->xpcs_window_sel_reg = PCS_V3_RN_WINDOW_SELECT;
+			break;
 		default:
 			pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
 			pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
@@ -302,7 +307,18 @@ static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	pci_dev_put(rdev);
 
 	/* Configure the PCS indirect addressing support */
-	reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
+	if (pdata->vdata->xpcs_access == XGBE_XPCS_ACCESS_V3) {
+		port_addr_size = PCS_RN_PORT_ADDR_SIZE *
+				 XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
+		pdata->smn_base = PCS_RN_SMN_BASE_ADDR + port_addr_size;
+
+		address = pdata->smn_base + (pdata->xpcs_window_def_reg);
+		reg = XP_IOREAD(pdata, XP_PROP_0);
+		amd_smn_read(0, address, &reg);
+	} else {
+		reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
+	}
+
 	pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
 	pdata->xpcs_window <<= 6;
 	pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index 60882a46fe50..12c074efa872 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -350,6 +350,7 @@
 /* XGBE PCI device id */
 #define XGBE_RV_PCI_DEVICE_ID	0x15d0
 #define XGBE_YC_PCI_DEVICE_ID	0x14b5
+#define XGBE_RN_PCI_DEVICE_ID	0x1630
 
  /* Generic low and high masks */
 #define XGBE_GEN_HI_MASK	GENMASK(31, 16)
-- 
2.34.1

Re: [PATCH v5 net-next 4/5] amd-xgbe: Add XGBE_XPCS_ACCESS_V3 support to xgbe_pci_probe()

[Jacob Keller]

On 2/14/2024 7:48 AM, Raju Rangoju wrote:
> A new version of XPCS access routines have been introduced, add the
> support to xgbe_pci_probe() to use these routines.
> 
> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
> ---

Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>

Re: [PATCH v5 net-next 4/5] amd-xgbe: Add XGBE_XPCS_ACCESS_V3 support to xgbe_pci_probe()

[kernel test robot]

Hi Raju,

kernel test robot noticed the following build warnings:

[auto build test WARNING on net-next/main]

url:    https://github.com/intel-lab-lkp/linux/commits/Raju-Rangoju/amd-xgbe-reorganize-the-code-of-XPCS-access/20240215-000248
base:   net-next/main
patch link:    https://lore.kernel.org/r/20240214154842.3577628-5-Raju.Rangoju%40amd.com
patch subject: [PATCH v5 net-next 4/5] amd-xgbe: Add XGBE_XPCS_ACCESS_V3 support to xgbe_pci_probe()
config: s390-allmodconfig (https://download.01.org/0day-ci/archive/20240216/202402160711.PlBR8NLf-lkp@intel.com/config)
compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project 1c10821022f1799452065fb57474e894e2562b7f)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240216/202402160711.PlBR8NLf-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202402160711.PlBR8NLf-lkp@intel.com/

All warnings (new ones prefixed by >>):

   In file included from drivers/net/ethernet/amd/xgbe/xgbe-pci.c:119:
   In file included from include/linux/pci.h:39:
   In file included from include/linux/io.h:13:
   In file included from arch/s390/include/asm/io.h:78:
   include/asm-generic/io.h:547:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     547 |         val = __raw_readb(PCI_IOBASE + addr);
         |                           ~~~~~~~~~~ ^
   include/asm-generic/io.h:560:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     560 |         val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
         |                                                         ~~~~~~~~~~ ^
   include/uapi/linux/byteorder/big_endian.h:37:59: note: expanded from macro '__le16_to_cpu'
      37 | #define __le16_to_cpu(x) __swab16((__force __u16)(__le16)(x))
         |                                                           ^
   include/uapi/linux/swab.h:102:54: note: expanded from macro '__swab16'
     102 | #define __swab16(x) (__u16)__builtin_bswap16((__u16)(x))
         |                                                      ^
   In file included from drivers/net/ethernet/amd/xgbe/xgbe-pci.c:119:
   In file included from include/linux/pci.h:39:
   In file included from include/linux/io.h:13:
   In file included from arch/s390/include/asm/io.h:78:
   include/asm-generic/io.h:573:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     573 |         val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
         |                                                         ~~~~~~~~~~ ^
   include/uapi/linux/byteorder/big_endian.h:35:59: note: expanded from macro '__le32_to_cpu'
      35 | #define __le32_to_cpu(x) __swab32((__force __u32)(__le32)(x))
         |                                                           ^
   include/uapi/linux/swab.h:115:54: note: expanded from macro '__swab32'
     115 | #define __swab32(x) (__u32)__builtin_bswap32((__u32)(x))
         |                                                      ^
   In file included from drivers/net/ethernet/amd/xgbe/xgbe-pci.c:119:
   In file included from include/linux/pci.h:39:
   In file included from include/linux/io.h:13:
   In file included from arch/s390/include/asm/io.h:78:
   include/asm-generic/io.h:584:33: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     584 |         __raw_writeb(value, PCI_IOBASE + addr);
         |                             ~~~~~~~~~~ ^
   include/asm-generic/io.h:594:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     594 |         __raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
         |                                                       ~~~~~~~~~~ ^
   include/asm-generic/io.h:604:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     604 |         __raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
         |                                                       ~~~~~~~~~~ ^
   include/asm-generic/io.h:692:20: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     692 |         readsb(PCI_IOBASE + addr, buffer, count);
         |                ~~~~~~~~~~ ^
   include/asm-generic/io.h:700:20: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     700 |         readsw(PCI_IOBASE + addr, buffer, count);
         |                ~~~~~~~~~~ ^
   include/asm-generic/io.h:708:20: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     708 |         readsl(PCI_IOBASE + addr, buffer, count);
         |                ~~~~~~~~~~ ^
   include/asm-generic/io.h:717:21: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     717 |         writesb(PCI_IOBASE + addr, buffer, count);
         |                 ~~~~~~~~~~ ^
   include/asm-generic/io.h:726:21: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     726 |         writesw(PCI_IOBASE + addr, buffer, count);
         |                 ~~~~~~~~~~ ^
   include/asm-generic/io.h:735:21: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     735 |         writesl(PCI_IOBASE + addr, buffer, count);
         |                 ~~~~~~~~~~ ^
>> drivers/net/ethernet/amd/xgbe/xgbe-pci.c:312:18: warning: variable 'reg' is uninitialized when used here [-Wuninitialized]
     312 |                                  XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
         |                                              ^~~
   drivers/net/ethernet/amd/xgbe/xgbe-common.h:1682:12: note: expanded from macro 'XP_GET_BITS'
    1682 |         GET_BITS((_var),                                                \
         |                   ^~~~
   drivers/net/ethernet/amd/xgbe/xgbe-common.h:1454:5: note: expanded from macro 'GET_BITS'
    1454 |         (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
         |            ^~~~
   drivers/net/ethernet/amd/xgbe/xgbe-pci.c:212:34: note: initialize the variable 'reg' to silence this warning
     212 |         unsigned int port_addr_size, reg;
         |                                         ^
         |                                          = 0
   13 warnings generated.


vim +/reg +312 drivers/net/ethernet/amd/xgbe/xgbe-pci.c

   208	
   209	static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
   210	{
   211		void __iomem * const *iomap_table;
   212		unsigned int port_addr_size, reg;
   213		struct device *dev = &pdev->dev;
   214		struct xgbe_prv_data *pdata;
   215		unsigned int ma_lo, ma_hi;
   216		struct pci_dev *rdev;
   217		int bar_mask, ret;
   218		u32 address;
   219	
   220		pdata = xgbe_alloc_pdata(dev);
   221		if (IS_ERR(pdata)) {
   222			ret = PTR_ERR(pdata);
   223			goto err_alloc;
   224		}
   225	
   226		pdata->pcidev = pdev;
   227		pci_set_drvdata(pdev, pdata);
   228	
   229		/* Get the version data */
   230		pdata->vdata = (struct xgbe_version_data *)id->driver_data;
   231	
   232		ret = pcim_enable_device(pdev);
   233		if (ret) {
   234			dev_err(dev, "pcim_enable_device failed\n");
   235			goto err_pci_enable;
   236		}
   237	
   238		/* Obtain the mmio areas for the device */
   239		bar_mask = pci_select_bars(pdev, IORESOURCE_MEM);
   240		ret = pcim_iomap_regions(pdev, bar_mask, XGBE_DRV_NAME);
   241		if (ret) {
   242			dev_err(dev, "pcim_iomap_regions failed\n");
   243			goto err_pci_enable;
   244		}
   245	
   246		iomap_table = pcim_iomap_table(pdev);
   247		if (!iomap_table) {
   248			dev_err(dev, "pcim_iomap_table failed\n");
   249			ret = -ENOMEM;
   250			goto err_pci_enable;
   251		}
   252	
   253		pdata->xgmac_regs = iomap_table[XGBE_XGMAC_BAR];
   254		if (!pdata->xgmac_regs) {
   255			dev_err(dev, "xgmac ioremap failed\n");
   256			ret = -ENOMEM;
   257			goto err_pci_enable;
   258		}
   259		pdata->xprop_regs = pdata->xgmac_regs + XGBE_MAC_PROP_OFFSET;
   260		pdata->xi2c_regs = pdata->xgmac_regs + XGBE_I2C_CTRL_OFFSET;
   261		if (netif_msg_probe(pdata)) {
   262			dev_dbg(dev, "xgmac_regs = %p\n", pdata->xgmac_regs);
   263			dev_dbg(dev, "xprop_regs = %p\n", pdata->xprop_regs);
   264			dev_dbg(dev, "xi2c_regs  = %p\n", pdata->xi2c_regs);
   265		}
   266	
   267		pdata->xpcs_regs = iomap_table[XGBE_XPCS_BAR];
   268		if (!pdata->xpcs_regs) {
   269			dev_err(dev, "xpcs ioremap failed\n");
   270			ret = -ENOMEM;
   271			goto err_pci_enable;
   272		}
   273		if (netif_msg_probe(pdata))
   274			dev_dbg(dev, "xpcs_regs  = %p\n", pdata->xpcs_regs);
   275	
   276		/* Set the PCS indirect addressing definition registers */
   277		rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
   278		if (rdev && rdev->vendor == PCI_VENDOR_ID_AMD) {
   279			switch (rdev->device) {
   280			case XGBE_RV_PCI_DEVICE_ID:
   281				pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
   282				pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
   283				break;
   284			case XGBE_YC_PCI_DEVICE_ID:
   285				pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF;
   286				pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT;
   287	
   288				/* Yellow Carp devices do not need cdr workaround */
   289				pdata->vdata->an_cdr_workaround = 0;
   290	
   291				/* Yellow Carp devices do not need rrc */
   292				pdata->vdata->enable_rrc = 0;
   293				break;
   294			case XGBE_RN_PCI_DEVICE_ID:
   295				pdata->xpcs_window_def_reg = PCS_V3_RN_WINDOW_DEF;
   296				pdata->xpcs_window_sel_reg = PCS_V3_RN_WINDOW_SELECT;
   297				break;
   298			default:
   299				pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
   300				pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
   301				break;
   302			}
   303		} else {
   304			pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
   305			pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
   306		}
   307		pci_dev_put(rdev);
   308	
   309		/* Configure the PCS indirect addressing support */
   310		if (pdata->vdata->xpcs_access == XGBE_XPCS_ACCESS_V3) {
   311			port_addr_size = PCS_RN_PORT_ADDR_SIZE *
 > 312					 XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
   313			pdata->smn_base = PCS_RN_SMN_BASE_ADDR + port_addr_size;
   314	
   315			address = pdata->smn_base + (pdata->xpcs_window_def_reg);
   316			reg = XP_IOREAD(pdata, XP_PROP_0);
   317			amd_smn_read(0, address, &reg);
   318		} else {
   319			reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
   320		}
   321	
   322		pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
   323		pdata->xpcs_window <<= 6;
   324		pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
   325		pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
   326		pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
   327		if (netif_msg_probe(pdata)) {
   328			dev_dbg(dev, "xpcs window def  = %#010x\n",
   329				pdata->xpcs_window_def_reg);
   330			dev_dbg(dev, "xpcs window sel  = %#010x\n",
   331				pdata->xpcs_window_sel_reg);
   332			dev_dbg(dev, "xpcs window      = %#010x\n",
   333				pdata->xpcs_window);
   334			dev_dbg(dev, "xpcs window size = %#010x\n",
   335				pdata->xpcs_window_size);
   336			dev_dbg(dev, "xpcs window mask = %#010x\n",
   337				pdata->xpcs_window_mask);
   338		}
   339	
   340		pci_set_master(pdev);
   341	
   342		/* Enable all interrupts in the hardware */
   343		XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
   344	
   345		/* Retrieve the MAC address */
   346		ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
   347		ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
   348		pdata->mac_addr[0] = ma_lo & 0xff;
   349		pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
   350		pdata->mac_addr[2] = (ma_lo >> 16) & 0xff;
   351		pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
   352		pdata->mac_addr[4] = ma_hi & 0xff;
   353		pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
   354		if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID) ||
   355		    !is_valid_ether_addr(pdata->mac_addr)) {
   356			dev_err(dev, "invalid mac address\n");
   357			ret = -EINVAL;
   358			goto err_pci_enable;
   359		}
   360	
   361		/* Clock settings */
   362		pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
   363		pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
   364	
   365		/* Set the DMA coherency values */
   366		pdata->coherent = 1;
   367		pdata->arcr = XGBE_DMA_PCI_ARCR;
   368		pdata->awcr = XGBE_DMA_PCI_AWCR;
   369		pdata->awarcr = XGBE_DMA_PCI_AWARCR;
   370	
   371		/* Read the port property registers */
   372		pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
   373		pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
   374		pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
   375		pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
   376		pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
   377		if (netif_msg_probe(pdata)) {
   378			dev_dbg(dev, "port property 0 = %#010x\n", pdata->pp0);
   379			dev_dbg(dev, "port property 1 = %#010x\n", pdata->pp1);
   380			dev_dbg(dev, "port property 2 = %#010x\n", pdata->pp2);
   381			dev_dbg(dev, "port property 3 = %#010x\n", pdata->pp3);
   382			dev_dbg(dev, "port property 4 = %#010x\n", pdata->pp4);
   383		}
   384	
   385		/* Set the maximum channels and queues */
   386		pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
   387							  MAX_TX_DMA);
   388		pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
   389							  MAX_RX_DMA);
   390		pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
   391						    MAX_TX_QUEUES);
   392		pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
   393						    MAX_RX_QUEUES);
   394		if (netif_msg_probe(pdata)) {
   395			dev_dbg(dev, "max tx/rx channel count = %u/%u\n",
   396				pdata->tx_max_channel_count,
   397				pdata->rx_max_channel_count);
   398			dev_dbg(dev, "max tx/rx hw queue count = %u/%u\n",
   399				pdata->tx_max_q_count, pdata->rx_max_q_count);
   400		}
   401	
   402		/* Set the hardware channel and queue counts */
   403		xgbe_set_counts(pdata);
   404	
   405		/* Set the maximum fifo amounts */
   406		pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
   407						      TX_FIFO_SIZE);
   408		pdata->tx_max_fifo_size *= 16384;
   409		pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
   410					      pdata->vdata->tx_max_fifo_size);
   411		pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
   412						      RX_FIFO_SIZE);
   413		pdata->rx_max_fifo_size *= 16384;
   414		pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
   415					      pdata->vdata->rx_max_fifo_size);
   416		if (netif_msg_probe(pdata))
   417			dev_dbg(dev, "max tx/rx max fifo size = %u/%u\n",
   418				pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
   419	
   420		/* Configure interrupt support */
   421		ret = xgbe_config_irqs(pdata);
   422		if (ret)
   423			goto err_pci_enable;
   424	
   425		/* Configure the netdev resource */
   426		ret = xgbe_config_netdev(pdata);
   427		if (ret)
   428			goto err_irq_vectors;
   429	
   430		netdev_notice(pdata->netdev, "net device enabled\n");
   431	
   432		return 0;
   433	
   434	err_irq_vectors:
   435		pci_free_irq_vectors(pdata->pcidev);
   436	
   437	err_pci_enable:
   438		xgbe_free_pdata(pdata);
   439	
   440	err_alloc:
   441		dev_notice(dev, "net device not enabled\n");
   442	
   443		return ret;
   444	}
   445	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v5 net-next 4/5] amd-xgbe: Add XGBE_XPCS_ACCESS_V3 support to xgbe_pci_probe()

[Dan Carpenter]

Hi Raju,

kernel test robot noticed the following build warnings:

url:    https://github.com/intel-lab-lkp/linux/commits/Raju-Rangoju/amd-xgbe-reorganize-the-code-of-XPCS-access/20240215-000248
base:   net-next/main
patch link:    https://lore.kernel.org/r/20240214154842.3577628-5-Raju.Rangoju%40amd.com
patch subject: [PATCH v5 net-next 4/5] amd-xgbe: Add XGBE_XPCS_ACCESS_V3 support to xgbe_pci_probe()
config: openrisc-randconfig-r071-20240215 (https://download.01.org/0day-ci/archive/20240218/202402180755.pdt7twL2-lkp@intel.com/config)
compiler: or1k-linux-gcc (GCC) 13.2.0

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202402180755.pdt7twL2-lkp@intel.com/

smatch warnings:
drivers/net/ethernet/amd/xgbe/xgbe-pci.c:312 xgbe_pci_probe() error: uninitialized symbol 'reg'.

vim +/reg +312 drivers/net/ethernet/amd/xgbe/xgbe-pci.c

47f164deab22a0 Lendacky, Thomas 2016-11-10  209  static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
47f164deab22a0 Lendacky, Thomas 2016-11-10  210  {
47f164deab22a0 Lendacky, Thomas 2016-11-10  211  	void __iomem * const *iomap_table;
eec387ef1b0556 Raju Rangoju     2024-02-14  212  	unsigned int port_addr_size, reg;
eec387ef1b0556 Raju Rangoju     2024-02-14  213  	struct device *dev = &pdev->dev;
eec387ef1b0556 Raju Rangoju     2024-02-14  214  	struct xgbe_prv_data *pdata;
47f164deab22a0 Lendacky, Thomas 2016-11-10  215  	unsigned int ma_lo, ma_hi;
eec387ef1b0556 Raju Rangoju     2024-02-14  216  	struct pci_dev *rdev;
eec387ef1b0556 Raju Rangoju     2024-02-14  217  	int bar_mask, ret;
eec387ef1b0556 Raju Rangoju     2024-02-14  218  	u32 address;
47f164deab22a0 Lendacky, Thomas 2016-11-10  219  
47f164deab22a0 Lendacky, Thomas 2016-11-10  220  	pdata = xgbe_alloc_pdata(dev);
47f164deab22a0 Lendacky, Thomas 2016-11-10  221  	if (IS_ERR(pdata)) {
47f164deab22a0 Lendacky, Thomas 2016-11-10  222  		ret = PTR_ERR(pdata);
47f164deab22a0 Lendacky, Thomas 2016-11-10  223  		goto err_alloc;
47f164deab22a0 Lendacky, Thomas 2016-11-10  224  	}
47f164deab22a0 Lendacky, Thomas 2016-11-10  225  
47f164deab22a0 Lendacky, Thomas 2016-11-10  226  	pdata->pcidev = pdev;
47f164deab22a0 Lendacky, Thomas 2016-11-10  227  	pci_set_drvdata(pdev, pdata);
47f164deab22a0 Lendacky, Thomas 2016-11-10  228  
47f164deab22a0 Lendacky, Thomas 2016-11-10  229  	/* Get the version data */
47f164deab22a0 Lendacky, Thomas 2016-11-10  230  	pdata->vdata = (struct xgbe_version_data *)id->driver_data;
47f164deab22a0 Lendacky, Thomas 2016-11-10  231  
47f164deab22a0 Lendacky, Thomas 2016-11-10  232  	ret = pcim_enable_device(pdev);
47f164deab22a0 Lendacky, Thomas 2016-11-10  233  	if (ret) {
47f164deab22a0 Lendacky, Thomas 2016-11-10  234  		dev_err(dev, "pcim_enable_device failed\n");
47f164deab22a0 Lendacky, Thomas 2016-11-10  235  		goto err_pci_enable;
47f164deab22a0 Lendacky, Thomas 2016-11-10  236  	}
47f164deab22a0 Lendacky, Thomas 2016-11-10  237  
47f164deab22a0 Lendacky, Thomas 2016-11-10  238  	/* Obtain the mmio areas for the device */
47f164deab22a0 Lendacky, Thomas 2016-11-10  239  	bar_mask = pci_select_bars(pdev, IORESOURCE_MEM);
47f164deab22a0 Lendacky, Thomas 2016-11-10  240  	ret = pcim_iomap_regions(pdev, bar_mask, XGBE_DRV_NAME);
47f164deab22a0 Lendacky, Thomas 2016-11-10  241  	if (ret) {
47f164deab22a0 Lendacky, Thomas 2016-11-10  242  		dev_err(dev, "pcim_iomap_regions failed\n");
47f164deab22a0 Lendacky, Thomas 2016-11-10  243  		goto err_pci_enable;
47f164deab22a0 Lendacky, Thomas 2016-11-10  244  	}
47f164deab22a0 Lendacky, Thomas 2016-11-10  245  
47f164deab22a0 Lendacky, Thomas 2016-11-10  246  	iomap_table = pcim_iomap_table(pdev);
47f164deab22a0 Lendacky, Thomas 2016-11-10  247  	if (!iomap_table) {
47f164deab22a0 Lendacky, Thomas 2016-11-10  248  		dev_err(dev, "pcim_iomap_table failed\n");
47f164deab22a0 Lendacky, Thomas 2016-11-10  249  		ret = -ENOMEM;
47f164deab22a0 Lendacky, Thomas 2016-11-10  250  		goto err_pci_enable;
47f164deab22a0 Lendacky, Thomas 2016-11-10  251  	}
47f164deab22a0 Lendacky, Thomas 2016-11-10  252  
47f164deab22a0 Lendacky, Thomas 2016-11-10  253  	pdata->xgmac_regs = iomap_table[XGBE_XGMAC_BAR];
47f164deab22a0 Lendacky, Thomas 2016-11-10  254  	if (!pdata->xgmac_regs) {
47f164deab22a0 Lendacky, Thomas 2016-11-10  255  		dev_err(dev, "xgmac ioremap failed\n");
47f164deab22a0 Lendacky, Thomas 2016-11-10  256  		ret = -ENOMEM;
47f164deab22a0 Lendacky, Thomas 2016-11-10  257  		goto err_pci_enable;
47f164deab22a0 Lendacky, Thomas 2016-11-10  258  	}
47f164deab22a0 Lendacky, Thomas 2016-11-10  259  	pdata->xprop_regs = pdata->xgmac_regs + XGBE_MAC_PROP_OFFSET;
47f164deab22a0 Lendacky, Thomas 2016-11-10  260  	pdata->xi2c_regs = pdata->xgmac_regs + XGBE_I2C_CTRL_OFFSET;
47f164deab22a0 Lendacky, Thomas 2016-11-10  261  	if (netif_msg_probe(pdata)) {
47f164deab22a0 Lendacky, Thomas 2016-11-10  262  		dev_dbg(dev, "xgmac_regs = %p\n", pdata->xgmac_regs);
47f164deab22a0 Lendacky, Thomas 2016-11-10  263  		dev_dbg(dev, "xprop_regs = %p\n", pdata->xprop_regs);
47f164deab22a0 Lendacky, Thomas 2016-11-10  264  		dev_dbg(dev, "xi2c_regs  = %p\n", pdata->xi2c_regs);
47f164deab22a0 Lendacky, Thomas 2016-11-10  265  	}
47f164deab22a0 Lendacky, Thomas 2016-11-10  266  
47f164deab22a0 Lendacky, Thomas 2016-11-10  267  	pdata->xpcs_regs = iomap_table[XGBE_XPCS_BAR];
47f164deab22a0 Lendacky, Thomas 2016-11-10  268  	if (!pdata->xpcs_regs) {
47f164deab22a0 Lendacky, Thomas 2016-11-10  269  		dev_err(dev, "xpcs ioremap failed\n");
47f164deab22a0 Lendacky, Thomas 2016-11-10  270  		ret = -ENOMEM;
47f164deab22a0 Lendacky, Thomas 2016-11-10  271  		goto err_pci_enable;
47f164deab22a0 Lendacky, Thomas 2016-11-10  272  	}
47f164deab22a0 Lendacky, Thomas 2016-11-10  273  	if (netif_msg_probe(pdata))
47f164deab22a0 Lendacky, Thomas 2016-11-10  274  		dev_dbg(dev, "xpcs_regs  = %p\n", pdata->xpcs_regs);
47f164deab22a0 Lendacky, Thomas 2016-11-10  275  
4eccbfc3618692 Lendacky, Thomas 2017-01-20  276  	/* Set the PCS indirect addressing definition registers */
4eccbfc3618692 Lendacky, Thomas 2017-01-20  277  	rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
597d9659e35b7d Raju Rangoju     2024-02-14  278  	if (rdev && rdev->vendor == PCI_VENDOR_ID_AMD) {
597d9659e35b7d Raju Rangoju     2024-02-14  279  		switch (rdev->device) {
597d9659e35b7d Raju Rangoju     2024-02-14  280  		case XGBE_RV_PCI_DEVICE_ID:
4eccbfc3618692 Lendacky, Thomas 2017-01-20  281  			pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
4eccbfc3618692 Lendacky, Thomas 2017-01-20  282  			pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
597d9659e35b7d Raju Rangoju     2024-02-14  283  			break;
597d9659e35b7d Raju Rangoju     2024-02-14  284  		case XGBE_YC_PCI_DEVICE_ID:
dbb6c58b5a61d0 Raju Rangoju     2021-12-20  285  			pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF;
dbb6c58b5a61d0 Raju Rangoju     2021-12-20  286  			pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT;
6f60ecf233f9a8 Raju Rangoju     2021-12-20  287  
6f60ecf233f9a8 Raju Rangoju     2021-12-20  288  			/* Yellow Carp devices do not need cdr workaround */
6f60ecf233f9a8 Raju Rangoju     2021-12-20  289  			pdata->vdata->an_cdr_workaround = 0;
f97fc7ef414603 Raju Rangoju     2022-10-20  290  
f97fc7ef414603 Raju Rangoju     2022-10-20  291  			/* Yellow Carp devices do not need rrc */
f97fc7ef414603 Raju Rangoju     2022-10-20  292  			pdata->vdata->enable_rrc = 0;
597d9659e35b7d Raju Rangoju     2024-02-14  293  			break;
eec387ef1b0556 Raju Rangoju     2024-02-14  294  		case XGBE_RN_PCI_DEVICE_ID:
eec387ef1b0556 Raju Rangoju     2024-02-14  295  			pdata->xpcs_window_def_reg = PCS_V3_RN_WINDOW_DEF;
eec387ef1b0556 Raju Rangoju     2024-02-14  296  			pdata->xpcs_window_sel_reg = PCS_V3_RN_WINDOW_SELECT;
eec387ef1b0556 Raju Rangoju     2024-02-14  297  			break;
597d9659e35b7d Raju Rangoju     2024-02-14  298  		default:
597d9659e35b7d Raju Rangoju     2024-02-14  299  			pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
597d9659e35b7d Raju Rangoju     2024-02-14  300  			pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
597d9659e35b7d Raju Rangoju     2024-02-14  301  			break;
597d9659e35b7d Raju Rangoju     2024-02-14  302  		}
4eccbfc3618692 Lendacky, Thomas 2017-01-20  303  	} else {
4eccbfc3618692 Lendacky, Thomas 2017-01-20  304  		pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
4eccbfc3618692 Lendacky, Thomas 2017-01-20  305  		pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
4eccbfc3618692 Lendacky, Thomas 2017-01-20  306  	}
4eccbfc3618692 Lendacky, Thomas 2017-01-20  307  	pci_dev_put(rdev);
4eccbfc3618692 Lendacky, Thomas 2017-01-20  308  
47f164deab22a0 Lendacky, Thomas 2016-11-10  309  	/* Configure the PCS indirect addressing support */
eec387ef1b0556 Raju Rangoju     2024-02-14  310  	if (pdata->vdata->xpcs_access == XGBE_XPCS_ACCESS_V3) {
eec387ef1b0556 Raju Rangoju     2024-02-14  311  		port_addr_size = PCS_RN_PORT_ADDR_SIZE *
eec387ef1b0556 Raju Rangoju     2024-02-14 @312  				 XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
                                                                                             ^^^
reg isn't initalized until 2 lines below.

eec387ef1b0556 Raju Rangoju     2024-02-14  313  		pdata->smn_base = PCS_RN_SMN_BASE_ADDR + port_addr_size;
eec387ef1b0556 Raju Rangoju     2024-02-14  314  
eec387ef1b0556 Raju Rangoju     2024-02-14  315  		address = pdata->smn_base + (pdata->xpcs_window_def_reg);
eec387ef1b0556 Raju Rangoju     2024-02-14  316  		reg = XP_IOREAD(pdata, XP_PROP_0);
eec387ef1b0556 Raju Rangoju     2024-02-14  317  		amd_smn_read(0, address, &reg);
eec387ef1b0556 Raju Rangoju     2024-02-14  318  	} else {
4eccbfc3618692 Lendacky, Thomas 2017-01-20  319  		reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
eec387ef1b0556 Raju Rangoju     2024-02-14  320  	}
eec387ef1b0556 Raju Rangoju     2024-02-14  321  
47f164deab22a0 Lendacky, Thomas 2016-11-10  322  	pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
47f164deab22a0 Lendacky, Thomas 2016-11-10  323  	pdata->xpcs_window <<= 6;
47f164deab22a0 Lendacky, Thomas 2016-11-10  324  	pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
47f164deab22a0 Lendacky, Thomas 2016-11-10  325  	pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
47f164deab22a0 Lendacky, Thomas 2016-11-10  326  	pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
47f164deab22a0 Lendacky, Thomas 2016-11-10  327  	if (netif_msg_probe(pdata)) {
40452f0ec84a3b Lendacky, Thomas 2017-08-18  328  		dev_dbg(dev, "xpcs window def  = %#010x\n",

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[PATCH v5 net-next 5/5] amd-xgbe: add support for new pci device id 0x1641

[Raju Rangoju]

Add support for new pci device id 0x1641 to register
Crater device with PCIe.

Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
 drivers/net/ethernet/amd/xgbe/xgbe-pci.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
index 340a7f16c0cc..179dcff907fb 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
@@ -496,6 +496,22 @@ static int __maybe_unused xgbe_pci_resume(struct device *dev)
 	return ret;
 }
 
+static struct xgbe_version_data xgbe_v3 = {
+	.init_function_ptrs_phy_impl	= xgbe_init_function_ptrs_phy_v2,
+	.xpcs_access			= XGBE_XPCS_ACCESS_V3,
+	.mmc_64bit			= 1,
+	.tx_max_fifo_size		= 65536,
+	.rx_max_fifo_size		= 65536,
+	.tx_tstamp_workaround		= 1,
+	.ecc_support			= 1,
+	.i2c_support			= 1,
+	.irq_reissue_support		= 1,
+	.tx_desc_prefetch		= 5,
+	.rx_desc_prefetch		= 5,
+	.an_cdr_workaround		= 0,
+	.enable_rrc			= 0,
+};
+
 static struct xgbe_version_data xgbe_v2a = {
 	.init_function_ptrs_phy_impl	= xgbe_init_function_ptrs_phy_v2,
 	.xpcs_access			= XGBE_XPCS_ACCESS_V2,
@@ -533,6 +549,8 @@ static const struct pci_device_id xgbe_pci_table[] = {
 	  .driver_data = (kernel_ulong_t)&xgbe_v2a },
 	{ PCI_VDEVICE(AMD, 0x1459),
 	  .driver_data = (kernel_ulong_t)&xgbe_v2b },
+	{ PCI_VDEVICE(AMD, 0x1641),
+	  .driver_data = (kernel_ulong_t)&xgbe_v3 },
 	/* Last entry must be zero */
 	{ 0, }
 };
-- 
2.34.1

Re: [PATCH v5 net-next 5/5] amd-xgbe: add support for new pci device id 0x1641

[Jacob Keller]

On 2/14/2024 7:48 AM, Raju Rangoju wrote:
> Add support for new pci device id 0x1641 to register
> Crater device with PCIe.
> 
> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
> ---

Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>