From: Michael Chan <michael.chan@broadcom.com>
To: davem@davemloft.net
Cc: netdev@vger.kernel.org, edumazet@google.com, kuba@kernel.org,
pabeni@redhat.com, pavan.chebbi@broadcom.com,
andrew.gospodarek@broadcom.com,
Ajit Khaparde <ajit.khaparde@broadcom.com>
Subject: [PATCH net-next 02/10] bnxt_en: Explicitly specify P5 completion rings to reserve
Date: Tue, 20 Feb 2024 15:03:09 -0800 [thread overview]
Message-ID: <20240220230317.96341-3-michael.chan@broadcom.com> (raw)
In-Reply-To: <20240220230317.96341-1-michael.chan@broadcom.com>
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The current code assumes that every RX ring group and every TX ring
requires a completion ring on P5_PLUS chips. Now that we have the
bnxt_hw_rings structure, add the cp_p5 field so that it can
be explicitly specified. This makes the logic more clear.
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Pavan Chebbi <pavan.chebbi@broadcom.com>
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
---
drivers/net/ethernet/broadcom/bnxt/bnxt.c | 19 ++++++++++++-------
drivers/net/ethernet/broadcom/bnxt/bnxt.h | 1 +
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
index 4a30eff0791b..4f3d2b1c9989 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
@@ -7114,7 +7114,7 @@ __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct bnxt_hw_rings *hwr)
enables |= hwr->stat ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
enables |= hwr->cp ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
- enables |= hwr->tx + hwr->grp ?
+ enables |= hwr->cp_p5 ?
FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
enables |= hwr->rx ?
FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
@@ -7131,7 +7131,7 @@ __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct bnxt_hw_rings *hwr)
if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
u16 rss_ctx = bnxt_get_nr_rss_ctxs(bp, hwr->grp);
- req->num_cmpl_rings = cpu_to_le16(hwr->tx + hwr->grp);
+ req->num_cmpl_rings = cpu_to_le16(hwr->cp_p5);
req->num_msix = cpu_to_le16(hwr->cp);
req->num_rsscos_ctxs = cpu_to_le16(rss_ctx);
} else {
@@ -7164,7 +7164,7 @@ __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, struct bnxt_hw_rings *hwr)
FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
enables |= hwr->stat ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
- enables |= hwr->tx + hwr->grp ?
+ enables |= hwr->cp_p5 ?
FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
} else {
enables |= hwr->cp ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
@@ -7180,7 +7180,7 @@ __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, struct bnxt_hw_rings *hwr)
if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
u16 rss_ctx = bnxt_get_nr_rss_ctxs(bp, hwr->grp);
- req->num_cmpl_rings = cpu_to_le16(hwr->tx + hwr->grp);
+ req->num_cmpl_rings = cpu_to_le16(hwr->cp_p5);
req->num_rsscos_ctxs = cpu_to_le16(rss_ctx);
} else {
req->num_cmpl_rings = cpu_to_le16(hwr->cp);
@@ -7350,6 +7350,8 @@ static void bnxt_copy_reserved_rings(struct bnxt *bp, struct bnxt_hw_rings *hwr)
if (BNXT_NEW_RM(bp)) {
hwr->rx = hw_resc->resv_rx_rings;
hwr->cp = hw_resc->resv_irqs;
+ if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
+ hwr->cp_p5 = hw_resc->resv_cp_rings;
hwr->grp = hw_resc->resv_hw_ring_grps;
hwr->vnic = hw_resc->resv_vnics;
hwr->stat = hw_resc->resv_stat_ctxs;
@@ -7359,7 +7361,7 @@ static void bnxt_copy_reserved_rings(struct bnxt *bp, struct bnxt_hw_rings *hwr)
static bool bnxt_rings_ok(struct bnxt *bp, struct bnxt_hw_rings *hwr)
{
return hwr->tx && hwr->rx && hwr->cp && hwr->grp && hwr->vnic &&
- hwr->stat;
+ hwr->stat && (hwr->cp_p5 || !(bp->flags & BNXT_FLAG_CHIP_P5_PLUS));
}
static int __bnxt_reserve_rings(struct bnxt *bp)
@@ -7378,8 +7380,9 @@ static int __bnxt_reserve_rings(struct bnxt *bp)
hwr.vnic = 1;
if (bp->flags & BNXT_FLAG_SHARED_RINGS)
sh = true;
- if ((bp->flags & BNXT_FLAG_RFS) &&
- !(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
+ if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
+ hwr.cp_p5 = hwr.rx + hwr.tx;
+ else if (bp->flags & BNXT_FLAG_RFS)
hwr.vnic = hwr.rx + 1;
if (bp->flags & BNXT_FLAG_AGG_RINGS)
hwr.rx <<= 1;
@@ -13326,6 +13329,8 @@ int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
hwr.cp += bnxt_get_ulp_msix_num(bp);
hwr.stat += bnxt_get_ulp_stat_ctxs(bp);
}
+ if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
+ hwr.cp_p5 = hwr.tx + rx;
return bnxt_hwrm_check_rings(bp, &hwr);
}
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.h b/drivers/net/ethernet/broadcom/bnxt/bnxt.h
index bb3b31f8d02f..681a579afcc2 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.h
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.h
@@ -1259,6 +1259,7 @@ struct bnxt_hw_rings {
int rx;
int grp;
int cp;
+ int cp_p5;
int stat;
int vnic;
};
--
2.30.1
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next prev parent reply other threads:[~2024-02-20 23:03 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-20 23:03 [PATCH net-next 00/10] bnxt_en: Ntuple filter improvements Michael Chan
2024-02-20 23:03 ` [PATCH net-next 01/10] bnxt_en: Refactor ring reservation functions Michael Chan
2024-02-20 23:03 ` Michael Chan [this message]
2024-02-20 23:03 ` [PATCH net-next 03/10] bnxt_en: Improve RSS context reservation infrastructure Michael Chan
2024-02-20 23:03 ` [PATCH net-next 04/10] bnxt_en: Check additional resources in bnxt_check_rings() Michael Chan
2024-02-20 23:03 ` [PATCH net-next 05/10] bnxt_en: Add bnxt_get_total_vnics() to calculate number of VNICs Michael Chan
2024-02-20 23:03 ` [PATCH net-next 06/10] bnxt_en: Refactor bnxt_set_features() Michael Chan
2024-02-20 23:03 ` [PATCH net-next 07/10] bnxt_en: Define BNXT_VNIC_DEFAULT for the default vnic index Michael Chan
2024-02-20 23:03 ` [PATCH net-next 08/10] bnxt_en: Provision for an additional VNIC for ntuple filters Michael Chan
2024-02-20 23:03 ` [PATCH net-next 09/10] bnxt_en: Create and setup the additional VNIC for adding " Michael Chan
2024-02-20 23:03 ` [PATCH net-next 10/10] bnxt_en: Use the new VNIC to create " Michael Chan
2024-02-22 14:40 ` [PATCH net-next 00/10] bnxt_en: Ntuple filter improvements patchwork-bot+netdevbpf
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