From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACEA77EEE1; Tue, 5 Mar 2024 07:51:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709625072; cv=none; b=WfqgWWF9Tl/hxd/gmiWLpkS70VthdxX9nGFMCpvdvUsq/ImFxrefD0RhAI9EfpgeY9bvfeEER1nR7NQOW5qnWOoDwGmaPBThBW5JZjcUM6MKRzPps59MNY/96m3qUYwYzPpVQFVTXYD6QK3p/v/Ddn4nLN0BCCOvJKH+7tFdIOQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709625072; c=relaxed/simple; bh=Mv+wjnpaqjDPxpuudt6hmB75f7eiz4A9FMh4nOvAHfM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VNKU0qnDcc+9MKrSUrS+WWO5+PgAEAcvDUMecQVubn7bl/9YJSrneOQE4HaIiQKXWRKl9/rOcX3Vva5b89qO7lB+KK7BU3J/5ZOnZTw2QWtSS7y56XMFz29HLwiHc49eVEnr/whW3M7FXUvY3YGKOyOzAvCmnlFxhZc8KQ0U+gg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DkQ1Exn2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DkQ1Exn2" Received: by smtp.kernel.org (Postfix) with ESMTPS id 65E9AC43141; Tue, 5 Mar 2024 07:51:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1709625072; bh=Mv+wjnpaqjDPxpuudt6hmB75f7eiz4A9FMh4nOvAHfM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DkQ1Exn2ph24kwJKEFuSXiYt8NAtOo6jMFJ4V3RhGQI1BFnWpc/M1XdyRXTeSyq5X 1/+Gcr/9CodU/adj2q7UaowF+dTp/5GRMIV8wz5celFq/1RVEkdithERcMYjRbh3tw ycH4r1vQYkMO4kxkataFIWuBVi4azcLyyngl7csrbpshttNx/iZ/kw8XoQGkX8dv55 k3jgYuWeRWdghX4GFDxe12pkacUeg/KfinFw6aviHs0Vt1hCGPQkeiFKIsi+4I3I0i svkEx4VmVX+1omCt05qlhX+TNYs+Z1Wtl8nCofAtAQt4L6w43cSV1PRm/3x69AExYC 4wDfLcB0Wo/iQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C3C6C54E5C; Tue, 5 Mar 2024 07:51:12 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Tue, 05 Mar 2024 15:51:13 +0800 Subject: [PATCH net-next v8 4/9] dt-bindings: net: convert hisi-femac.txt to YAML Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240305-net-v8-4-166aaeea2107@outlook.com> References: <20240305-net-v8-0-166aaeea2107@outlook.com> In-Reply-To: <20240305-net-v8-0-166aaeea2107@outlook.com> To: Yisen Zhuang , Salil Mehta , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1709625070; l=5303; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=Y31W+EBTMTCB+g3jeFUiVgLCSMs5MTAdgXmolrXBmrQ=; b=Aug3S6YnjDFnp7BTPJCvSRokxnH2+7b4NbmaQAIOQ3Bk9h2Py39VAmu2/07QSeXI+bIEvJ2ei QlvRVFG/7XMAFTZQTUMtT68HYeXyjgdO5m1i+ULdcE0GAiDmyadd1EX X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: From: Yang Xiwen Convert the old text binding to new YAML. While at it, make some changes to the binding: - The version numbers are not documented publicly. The version also does not change programming interface. Remove it until it's really needed. - A few clocks are missing in old binding file. Add them to match the real hardware. Signed-off-by: Yang Xiwen --- .../bindings/net/hisilicon,hisi-femac.yaml | 89 ++++++++++++++++++++++ .../devicetree/bindings/net/hisilicon-femac.txt | 41 ---------- 2 files changed, 89 insertions(+), 41 deletions(-) diff --git a/Documentation/devicetree/bindings/net/hisilicon,hisi-femac.yaml b/Documentation/devicetree/bindings/net/hisilicon,hisi-femac.yaml new file mode 100644 index 000000000000..ba207f2c9ae4 --- /dev/null +++ b/Documentation/devicetree/bindings/net/hisilicon,hisi-femac.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/hisilicon,hisi-femac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Fast Ethernet MAC controller + +maintainers: + - Yang Xiwen + +allOf: + - $ref: ethernet-controller.yaml + +properties: + compatible: + items: + - enum: + - hisilicon,hi3516cv300-femac + - const: hisilicon,hisi-femac + + reg: + items: + - description: The first region is the MAC core register base and size. + - description: The second region is the global MAC control register. + + interrupts: + maxItems: 1 + + clocks: + items: + - description: MAC main clock + - description: MAC bus interface clock + - description: PHY clock + + clock-names: + items: + - const: mac + - const: macif + - const: phy + + resets: + items: + - description: MAC reset signal + - description: PHY reset signal + + reset-names: + items: + - const: mac + - const: phy + + hisilicon,phy-reset-delays-us: + description: PHY reset timing requirement (in micro seconds). + The integrated PHY usually have a special reset timing sequence and must + interact with MAC controller to accomplish the entire reset procedure. So + these properties belong to MAC controller, not PHY. + items: + - description: pre-reset delay for PHY + - description: reset pulse for PHY + - description: post-reset delay for PHY + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - reset-names + - phy-mode + - phy-handle + - hisilicon,phy-reset-delays-us + +unevaluatedProperties: false + +examples: + - | + ethernet@10090000 { + compatible = "hisilicon,hi3516cv300-femac", "hisilicon,hisi-femac"; + reg = <0x10090000 0x1000>, <0x10091300 0x200>; + interrupts = <12>; + clocks = <&clk_femac>, <&clk_femacif>, <&clk_fephy>; + clock-names = "mac", "macif", "phy"; + resets = <&crg 0xec 0>, <&crg 0xec 3>; + reset-names = "mac", "phy"; + mac-address = [00 00 00 00 00 00]; + phy-mode = "mii"; + phy-handle = <&fephy>; + hisilicon,phy-reset-delays-us = <10000 20000 20000>; + }; diff --git a/Documentation/devicetree/bindings/net/hisilicon-femac.txt b/Documentation/devicetree/bindings/net/hisilicon-femac.txt deleted file mode 100644 index 5f96976f3cea..000000000000 --- a/Documentation/devicetree/bindings/net/hisilicon-femac.txt +++ /dev/null @@ -1,41 +0,0 @@ -Hisilicon Fast Ethernet MAC controller - -Required properties: -- compatible: should contain one of the following version strings: - * "hisilicon,hisi-femac-v1" - * "hisilicon,hisi-femac-v2" - and the soc string "hisilicon,hi3516cv300-femac". -- reg: specifies base physical address(s) and size of the device registers. - The first region is the MAC core register base and size. - The second region is the global MAC control register. -- interrupts: should contain the MAC interrupt. -- clocks: A phandle to the MAC main clock. -- resets: should contain the phandle to the MAC reset signal(required) and - the PHY reset signal(optional). -- reset-names: should contain the reset signal name "mac"(required) - and "phy"(optional). -- phy-mode: see ethernet.txt [1]. -- phy-handle: see ethernet.txt [1]. -- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given. - The 1st cell is reset pre-delay in micro seconds. - The 2nd cell is reset pulse in micro seconds. - The 3rd cell is reset post-delay in micro seconds. - -The MAC address will be determined using the optional properties -defined in ethernet.txt[1]. - -[1] Documentation/devicetree/bindings/net/ethernet.txt - -Example: - hisi_femac: ethernet@10090000 { - compatible = "hisilicon,hi3516cv300-femac","hisilicon,hisi-femac-v2"; - reg = <0x10090000 0x1000>,<0x10091300 0x200>; - interrupts = <12>; - clocks = <&crg HI3518EV200_ETH_CLK>; - resets = <&crg 0xec 0>,<&crg 0xec 3>; - reset-names = "mac","phy"; - mac-address = [00 00 00 00 00 00]; - phy-mode = "mii"; - phy-handle = <&phy0>; - hisilicon,phy-reset-delays-us = <10000 20000 20000>; - }; -- 2.43.0