Re: [PATCH] octeontx2-af: Increase maximum BPID channels

[Simon Horman <horms@kernel.org>]

On Wed, Mar 06, 2024 at 01:38:06PM -0800, Radha Mohan Chintakuntla wrote:
> Any NIX interface type can have maximum 256 channels. So increased the
> backpressure ID count to 256 so that it can cover cn9k and cn10k SoCs that
> have different NIX interface types with varied maximum channels.
> 
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> ---
>  drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
> index d5c4f810da61..223a2e39172c 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
> @@ -1207,10 +1207,8 @@ struct nix_bp_cfg_req {
>  	/* bpid_per_chan = 1 assigns separate bp id for each channel */
>  };
>  
> -/* PF can be mapped to either CGX or LBK interface,
> - * so maximum 64 channels are possible.
> - */
> -#define NIX_MAX_BPID_CHAN	64
> +/* Maximum channels any single NIX interface can have */
> +#define NIX_MAX_BPID_CHAN	256
>  struct nix_bp_cfg_rsp {
>  	struct mbox_msghdr hdr;
>  	u16	chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */

Hi Radha,

looking over this, I am curious to know how out-of bounds access
to chan_bpid is prevented. The bounds seems to be the
the number of PF or VF rings. Which I assume is derived from
the HW. But if so, what if the HW reports more than NIX_MAX_BPID_CHAN
rings?

On a different note, struct includes the following field:

	u16 bpid[NIX_MAX_BPID_CHAN];

But here the index used seems to be

1. VLAN priority (which has maximum value of 8) if DCB is used
2. 0 otherwise

So perhaps fewer elements are needed?

Apologies in advance if I'm on the wrong track here.