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From: Saeed Mahameed <saeed@kernel.org>
To: "David S. Miller" <davem@davemloft.net>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Eric Dumazet <edumazet@google.com>
Cc: Saeed Mahameed <saeedm@nvidia.com>,
	netdev@vger.kernel.org, Tariq Toukan <tariqt@nvidia.com>,
	Gal Pressman <gal@nvidia.com>,
	Leon Romanovsky <leonro@nvidia.com>,
	Michael Liang <mliang@purestorage.com>,
	Mohamed Khalfella <mkhalfella@purestorage.com>,
	Yuanyuan Zhong <yzhong@purestorage.com>,
	Shay Drory <shayd@nvidia.com>
Subject: [net 03/10] net/mlx5: offset comp irq index in name by one
Date: Tue, 26 Mar 2024 07:46:39 -0700	[thread overview]
Message-ID: <20240326144646.2078893-4-saeed@kernel.org> (raw)
In-Reply-To: <20240326144646.2078893-1-saeed@kernel.org>

From: Michael Liang <mliang@purestorage.com>

The mlx5 comp irq name scheme is changed a little bit between
commit 3663ad34bc70 ("net/mlx5: Shift control IRQ to the last index")
and commit 3354822cde5a ("net/mlx5: Use dynamic msix vectors allocation").
The index in the comp irq name used to start from 0 but now it starts
from 1. There is nothing critical here, but it's harmless to change
back to the old behavior, a.k.a starting from 0.

Fixes: 3354822cde5a ("net/mlx5: Use dynamic msix vectors allocation")
Reviewed-by: Mohamed Khalfella <mkhalfella@purestorage.com>
Reviewed-by: Yuanyuan Zhong <yzhong@purestorage.com>
Signed-off-by: Michael Liang <mliang@purestorage.com>
Reviewed-by: Shay Drory <shayd@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c
index 4dcf995cb1a2..6bac8ad70ba6 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c
@@ -19,6 +19,7 @@
 #define MLX5_IRQ_CTRL_SF_MAX 8
 /* min num of vectors for SFs to be enabled */
 #define MLX5_IRQ_VEC_COMP_BASE_SF 2
+#define MLX5_IRQ_VEC_COMP_BASE 1
 
 #define MLX5_EQ_SHARE_IRQ_MAX_COMP (8)
 #define MLX5_EQ_SHARE_IRQ_MAX_CTRL (UINT_MAX)
@@ -246,6 +247,7 @@ static void irq_set_name(struct mlx5_irq_pool *pool, char *name, int vecidx)
 		return;
 	}
 
+	vecidx -= MLX5_IRQ_VEC_COMP_BASE;
 	snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", vecidx);
 }
 
@@ -585,7 +587,7 @@ struct mlx5_irq *mlx5_irq_request_vector(struct mlx5_core_dev *dev, u16 cpu,
 	struct mlx5_irq_table *table = mlx5_irq_table_get(dev);
 	struct mlx5_irq_pool *pool = table->pcif_pool;
 	struct irq_affinity_desc af_desc;
-	int offset = 1;
+	int offset = MLX5_IRQ_VEC_COMP_BASE;
 
 	if (!pool->xa_num_irqs.max)
 		offset = 0;
-- 
2.44.0


  parent reply	other threads:[~2024-03-26 14:46 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-26 14:46 [pull request][net 00/10] mlx5 fixes 2024-03-26 Saeed Mahameed
2024-03-26 14:46 ` [net 01/10] net/mlx5: E-switch, store eswitch pointer before registering devlink_param Saeed Mahameed
2024-03-26 14:46 ` [net 02/10] net/mlx5: Register devlink first under devlink lock Saeed Mahameed
2024-03-26 14:46 ` Saeed Mahameed [this message]
2024-03-26 14:46 ` [net 04/10] net/mlx5: Properly link new fs rules into the tree Saeed Mahameed
2024-03-26 14:46 ` [net 05/10] net/mlx5: Correctly compare pkt reformat ids Saeed Mahameed
2024-03-26 14:46 ` [net 06/10] net/mlx5: RSS, Block changing channels number when RXFH is configured Saeed Mahameed
2024-03-29  5:31   ` Jakub Kicinski
2024-04-01  6:54     ` Tariq Toukan
2024-04-01 14:34       ` Jakub Kicinski
2024-03-26 14:46 ` [net 07/10] net/mlx5e: Fix mlx5e_priv_init() cleanup flow Saeed Mahameed
2024-03-26 14:46 ` [net 08/10] net/mlx5e: HTB, Fix inconsistencies with QoS SQs number Saeed Mahameed
2024-03-26 14:46 ` [net 09/10] net/mlx5e: Do not produce metadata freelist entries in Tx port ts WQE xmit Saeed Mahameed
2024-03-26 14:46 ` [net 10/10] net/mlx5e: RSS, Block XOR hash with over 128 channels Saeed Mahameed

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