Re: [PATCH bpf-next 2/5] riscv, bpf: Relax restrictions on Zbb instructions

Björn Töpel
2024-04-02T14:18:06Z

Conor Dooley <conor.dooley@microchip.com> writes:

> On Thu, Mar 28, 2024 at 10:07:23PM +0000, Conor Dooley wrote:
>
>> As I said on IRC to you earlier, I think the Kconfig options here are in
>> need of a bit of a spring cleaning - they should be modified to explain
>> their individual purposes, be that enabling optimisations in the kernel
>> or being required for userspace. I'll try to send a patch for that if
>> I remember tomorrow.
>
> Something like this:
>
> -- >8 --
> commit 5125504beaedd669b082bf74b02003a77360670f
> Author: Conor Dooley <conor.dooley@microchip.com>
> Date: Fri Mar 29 11:13:22 2024 +0000
>
> RISC-V: clarify what some RISCV_ISA* config options do
>
> During some discussion on IRC yesterday and on Pu's bpf patch [1]
> I noticed that these RISCV_ISA* Kconfig options are not really clear
> about their implications. Many of these options have no impact on what
> userspace is allowed to do, for example an application can use Zbb
> regardless of whether or not the kernel does. Change the help text to
> try and clarify whether or not an option affects just the kernel, or
> also userspace. None of these options actually control whether or not an
> extension is detected dynamically as that's done regardless of Kconfig
> options, so drop any text that implies the option is required for
> dynamic detection, rewording them as "do x when y is detected".
>
> Link: https://lore.kernel.org/linux-riscv/20240328-ferocity-repose-c554f75a676c@spud/ [1]
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> I did this based on top of Samuel's changes dropping the MMU
> requurements just in case, but I don't think there's a conflict:
> https://lore.kernel.org/linux-riscv/20240227003630.3634533-4-samuel.holland@sifive.com/
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index d8a777f59402..f327a8ac648f 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -501,8 +501,8 @@ config RISCV_ISA_SVNAPOT
> depends on RISCV_ALTERNATIVE
> default y
> help
> - Allow kernel to detect the Svnapot ISA-extension dynamically at boot
> - time and enable its usage.
> + Add support for the Svnapot ISA-extension when it is detected by
> + the kernel at boot.
>
> The Svnapot extension is used to mark contiguous PTEs as a range
> of contiguous virtual-to-physical translations for a naturally
> @@ -520,9 +520,9 @@ config RISCV_ISA_SVPBMT
> depends on RISCV_ALTERNATIVE
> default y
> help
> - Adds support to dynamically detect the presence of the Svpbmt
> - ISA-extension (Supervisor-mode: page-based memory types) and
> - enable its usage.
> + Add support for the Svpbmt ISA-extension (Supervisor-mode:
> + page-based memory types) when it is detected by the kernel at
> + boot.
>
> The memory type for a page contains a combination of attributes
> that indicate the cacheability, idempotency, and ordering
> @@ -541,14 +541,15 @@ config TOOLCHAIN_HAS_V
> depends on AS_HAS_OPTION_ARCH
>
> config RISCV_ISA_V
> - bool "VECTOR extension support"
> + bool "Vector extension support"
> depends on TOOLCHAIN_HAS_V
> depends on FPU
> select DYNAMIC_SIGFRAME
> default y
> help
> Say N here if you want to disable all vector related procedure
> - in the kernel.
> + in the kernel. Without this option enabled, neither the kernel nor
> + userspace may use vector.
>
> If you don't know what to do here, say Y.
>
> @@ -606,8 +607,8 @@ config RISCV_ISA_ZBB
> depends on RISCV_ALTERNATIVE
> default y
> help
> - Adds support to dynamically detect the presence of the ZBB
> - extension (basic bit manipulation) and enable its usage.
> + Add support for enabling optimisations in the kernel when the

I don't care much, but "optimizations" here -- for consistency reasons!
[1] ;-)

Nice change!

Reviewed-by: Björn Töpel <bjorn@rivosinc.com>

[1] https://lwn.net/Articles/636286/