[PATCH v4 00/11] Series to deliver Ethernet for STM32MP13

[PATCH v4 00/11] Series to deliver Ethernet for STM32MP13

[Christophe Roullier]

STM32MP13 is STM32 SOC with 2 GMACs instances
    GMAC IP version is SNPS 4.20.
    GMAC IP configure with 1 RX and 1 TX queue.
    DMA HW capability register supported
    RX Checksum Offload Engine supported
    TX Checksum insertion supported
    Wake-Up On Lan supported
    TSO supported
Rework dwmac glue to simplify management for next stm32 (integrate RFC from Marek)

V2: - Remark from Rob Herring (add Krzysztof's ack in patch 02/11, update in yaml)
      Remark from Serge Semin (upate commits msg)
V3: - Remove PHY regulator patch and Ethernet2 DT because need to clarify how to
      manage PHY regulator (in glue or PHY side)
    - Integrate RFC from Marek
    - Remark from Rob Herring in YAML documentation
V4: - Remark from Marek (remove max-speed, extra space in DT, update commit msg)
    - Remark from Rasmus (add sign-off, add base-commit)
    - Remark from Sai Krishna Gajula

Christophe Roullier (6):
  dt-bindings: net: add STM32MP13 compatible in documentation for stm32
  net: ethernet: stmmac: add management of stm32mp13 for stm32
  ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13
  ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board
  ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board
  ARM: multi_v7_defconfig: Add MCP23S08 pinctrl support

Marek Vasut (5):
  net: stmmac: dwmac-stm32: Separate out external clock rate validation
  net: stmmac: dwmac-stm32: Separate out external clock selector
  net: stmmac: dwmac-stm32: Extract PMCR configuration
  net: stmmac: dwmac-stm32: Clean up the debug prints
  net: stmmac: dwmac-stm32: Fix Mhz to MHz

 .../devicetree/bindings/net/stm32-dwmac.yaml  |  41 ++++-
 arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi   |  71 ++++++++
 arch/arm/boot/dts/st/stm32mp131.dtsi          |  38 ++++
 arch/arm/boot/dts/st/stm32mp133.dtsi          |  31 ++++
 arch/arm/boot/dts/st/stm32mp135f-dk.dts       |  23 +++
 arch/arm/configs/multi_v7_defconfig           |   1 +
 .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 172 ++++++++++++++----
 7 files changed, 330 insertions(+), 47 deletions(-)


base-commit: cd0057ad75116bacf16fea82e48c1db642971136
-- 
2.25.1

[PATCH v4 01/11] dt-bindings: net: add STM32MP13 compatible in documentation for stm32

[Christophe Roullier]

New STM32 SOC have 2 GMACs instances.
GMAC IP version is SNPS 4.20.

Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
 .../devicetree/bindings/net/stm32-dwmac.yaml  | 41 +++++++++++++++----
 1 file changed, 34 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
index 7ccf75676b6d5..ecbed9a7aaf6d 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
@@ -22,18 +22,17 @@ select:
         enum:
           - st,stm32-dwmac
           - st,stm32mp1-dwmac
+          - st,stm32mp13-dwmac
   required:
     - compatible
 
-allOf:
-  - $ref: snps,dwmac.yaml#
-
 properties:
   compatible:
     oneOf:
       - items:
           - enum:
               - st,stm32mp1-dwmac
+              - st,stm32mp13-dwmac
           - const: snps,dwmac-4.20a
       - items:
           - enum:
@@ -75,12 +74,15 @@ properties:
   st,syscon:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     items:
-      - items:
+      - minItems: 2
+        items:
           - description: phandle to the syscon node which encompases the glue register
           - description: offset of the control register
+          - description: field to set mask in register
     description:
       Should be phandle/offset pair. The phandle to the syscon node which
-      encompases the glue register, and the offset of the control register
+      encompases the glue register, the offset of the control register and
+      the mask to set bitfield in control register
 
   st,ext-phyclk:
     description:
@@ -112,12 +114,37 @@ required:
 
 unevaluatedProperties: false
 
+allOf:
+  - $ref: snps,dwmac.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - st,stm32mp1-dwmac
+              - st,stm32-dwmac
+    then:
+      properties:
+        st,syscon:
+          items:
+            maxItems: 2
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - st,stm32mp13-dwmac
+    then:
+      properties:
+        st,syscon:
+          items:
+            minItems: 3
+
 examples:
   - |
     #include <dt-bindings/interrupt-controller/arm-gic.h>
     #include <dt-bindings/clock/stm32mp1-clks.h>
-    #include <dt-bindings/reset/stm32mp1-resets.h>
-    #include <dt-bindings/mfd/stm32h7-rcc.h>
     //Example 1
      ethernet0: ethernet@5800a000 {
            compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
-- 
2.25.1

[PATCH v4 02/11] net: stmmac: dwmac-stm32: Separate out external clock rate validation

[Christophe Roullier]

From: Marek Vasut <marex@denx.de>

Pull the external clock frequency validation into a separate function,
to avoid conflating it with external clock DT property decoding and
clock mux register configuration. This should make the code easier to
read and understand.

This does change the code behavior slightly. The clock mux PMCR register
setting now depends solely on the DT properties which configure the clock
mux between external clock and internal RCC generated clock. The mux PMCR
register settings no longer depend on the supplied clock frequency, that
supplied clock frequency is now only validated, and if the clock frequency
is invalid for a mode, it is rejected.

Previously, the code would switch the PMCR register clock mux to internal
RCC generated clock if external clock couldn't provide suitable frequency,
without checking whether the RCC generated clock frequency is correct. Such
behavior is risky at best, user should have configured their clock correctly
in the first place, so this behavior is removed here.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
 .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 51 +++++++++++++++----
 1 file changed, 41 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index c92dfc4ecf570..2fd2620ebed69 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -157,25 +157,54 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat, bool resume)
 	return stm32_dwmac_clk_enable(dwmac, resume);
 }
 
+static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat)
+{
+	struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
+	const u32 clk_rate = clk_get_rate(dwmac->clk_eth_ck);
+
+	switch (plat_dat->mac_interface) {
+	case PHY_INTERFACE_MODE_MII:
+	case PHY_INTERFACE_MODE_GMII:
+		if (clk_rate == ETH_CK_F_25M)
+			return 0;
+		break;
+	case PHY_INTERFACE_MODE_RMII:
+		if (clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M)
+			return 0;
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		if (clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M)
+			return 0;
+		break;
+	default:
+		break;
+	}
+
+	dev_err(dwmac->dev, "Mode %s does not match eth-ck frequency %d Hz",
+		phy_modes(plat_dat->mac_interface), clk_rate);
+	return -EINVAL;
+}
+
 static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
 {
 	struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
-	u32 reg = dwmac->mode_reg, clk_rate;
-	int val;
+	u32 reg = dwmac->mode_reg;
+	int val, ret;
 
-	clk_rate = clk_get_rate(dwmac->clk_eth_ck);
 	dwmac->enable_eth_ck = false;
 	switch (plat_dat->mac_interface) {
 	case PHY_INTERFACE_MODE_MII:
-		if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk)
+		if (dwmac->ext_phyclk)
 			dwmac->enable_eth_ck = true;
 		val = SYSCFG_PMCR_ETH_SEL_MII;
 		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
 		break;
 	case PHY_INTERFACE_MODE_GMII:
 		val = SYSCFG_PMCR_ETH_SEL_GMII;
-		if (clk_rate == ETH_CK_F_25M &&
-		    (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
+		if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) {
 			dwmac->enable_eth_ck = true;
 			val |= SYSCFG_PMCR_ETH_CLK_SEL;
 		}
@@ -183,8 +212,7 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
 		break;
 	case PHY_INTERFACE_MODE_RMII:
 		val = SYSCFG_PMCR_ETH_SEL_RMII;
-		if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) &&
-		    (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) {
+		if (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk) {
 			dwmac->enable_eth_ck = true;
 			val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
 		}
@@ -195,8 +223,7 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
 	case PHY_INTERFACE_MODE_RGMII_RXID:
 	case PHY_INTERFACE_MODE_RGMII_TXID:
 		val = SYSCFG_PMCR_ETH_SEL_RGMII;
-		if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) &&
-		    (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
+		if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) {
 			dwmac->enable_eth_ck = true;
 			val |= SYSCFG_PMCR_ETH_CLK_SEL;
 		}
@@ -209,6 +236,10 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
 		return -EINVAL;
 	}
 
+	ret = stm32mp1_validate_ethck_rate(plat_dat);
+	if (ret)
+		return ret;
+
 	/* Need to update PMCCLRR (clear register) */
 	regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
 		     dwmac->ops->syscfg_eth_mask);
-- 
2.25.1

[PATCH v4 03/11] net: stmmac: dwmac-stm32: Separate out external clock selector

[Christophe Roullier]

From: Marek Vasut <marex@denx.de>

Pull the external clock selector into a separate function, to avoid
conflating it with external clock rate validation and clock mux
register configuration. This should make the code easier to read and
understand.

The dwmac->enable_eth_ck variable in the end indicates whether the MAC
clock are supplied by external oscillator (true) or internal RCC clock
IP (false). The dwmac->enable_eth_ck value is set based on multiple DT
properties, some of them deprecated, some of them specific to bus mode.

The following DT properties and variables are taken into account. In
each case, if the property is present or true, MAC clock is supplied
by external oscillator.
- "st,ext-phyclk", assigned to variable dwmac->ext_phyclk
  - Used in any mode (MII/RMII/GMII/RGMII)
  - The only non-deprecated DT property of the three
- "st,eth-clk-sel", assigned to variable dwmac->eth_clk_sel_reg
  - Valid only in GMII/RGMII mode
  - Deprecated property, backward compatibility only
- "st,eth-ref-clk-sel", assigned to variable dwmac->eth_ref_clk_sel_reg
  - Valid only in RMII mode
  - Deprecated property, backward compatibility only

The stm32mp1_select_ethck_external() function handles the aforementioned
DT properties and sets dwmac->enable_eth_ck accordingly.

The stm32mp1_set_mode() is adjusted to call stm32mp1_select_ethck_external()
first and then only use dwmac->enable_eth_ck to determine hardware clock mux
settings.

No functional change intended.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
 .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 50 ++++++++++++++-----
 1 file changed, 38 insertions(+), 12 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 2fd2620ebed69..767994061ea82 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -157,6 +157,37 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat, bool resume)
 	return stm32_dwmac_clk_enable(dwmac, resume);
 }
 
+static int stm32mp1_select_ethck_external(struct plat_stmmacenet_data *plat_dat)
+{
+	struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
+
+	switch (plat_dat->mac_interface) {
+	case PHY_INTERFACE_MODE_MII:
+		dwmac->enable_eth_ck = dwmac->ext_phyclk;
+		return 0;
+	case PHY_INTERFACE_MODE_GMII:
+		dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg ||
+				       dwmac->ext_phyclk;
+		return 0;
+	case PHY_INTERFACE_MODE_RMII:
+		dwmac->enable_eth_ck = dwmac->eth_ref_clk_sel_reg ||
+				       dwmac->ext_phyclk;
+		return 0;
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg ||
+				       dwmac->ext_phyclk;
+		return 0;
+	default:
+		dwmac->enable_eth_ck = false;
+		dev_err(dwmac->dev, "Mode %s not supported",
+			phy_modes(plat_dat->mac_interface));
+		return -EINVAL;
+	}
+}
+
 static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat)
 {
 	struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
@@ -194,28 +225,25 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
 	u32 reg = dwmac->mode_reg;
 	int val, ret;
 
-	dwmac->enable_eth_ck = false;
+	ret = stm32mp1_select_ethck_external(plat_dat);
+	if (ret)
+		return ret;
+
 	switch (plat_dat->mac_interface) {
 	case PHY_INTERFACE_MODE_MII:
-		if (dwmac->ext_phyclk)
-			dwmac->enable_eth_ck = true;
 		val = SYSCFG_PMCR_ETH_SEL_MII;
 		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
 		break;
 	case PHY_INTERFACE_MODE_GMII:
 		val = SYSCFG_PMCR_ETH_SEL_GMII;
-		if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) {
-			dwmac->enable_eth_ck = true;
+		if (dwmac->enable_eth_ck)
 			val |= SYSCFG_PMCR_ETH_CLK_SEL;
-		}
 		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
 		break;
 	case PHY_INTERFACE_MODE_RMII:
 		val = SYSCFG_PMCR_ETH_SEL_RMII;
-		if (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk) {
-			dwmac->enable_eth_ck = true;
+		if (dwmac->enable_eth_ck)
 			val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
-		}
 		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
 		break;
 	case PHY_INTERFACE_MODE_RGMII:
@@ -223,10 +251,8 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
 	case PHY_INTERFACE_MODE_RGMII_RXID:
 	case PHY_INTERFACE_MODE_RGMII_TXID:
 		val = SYSCFG_PMCR_ETH_SEL_RGMII;
-		if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) {
-			dwmac->enable_eth_ck = true;
+		if (dwmac->enable_eth_ck)
 			val |= SYSCFG_PMCR_ETH_CLK_SEL;
-		}
 		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
 		break;
 	default:
-- 
2.25.1

[PATCH v4 04/11] net: stmmac: dwmac-stm32: Extract PMCR configuration

[Christophe Roullier]

From: Marek Vasut <marex@denx.de>

Pull the PMCR clock mux configuration into a separate function. This is
the final change of three, which moves external clock rate validation,
external clock selector decoding, and clock mux configuration into
separate functions. This should make the code easier to undrestand.
No functional change intended.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
 .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 27 ++++++++++++-------
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 767994061ea82..aa413edd1ef71 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -219,15 +219,11 @@ static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat)
 	return -EINVAL;
 }
 
-static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
+static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
 {
 	struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
 	u32 reg = dwmac->mode_reg;
-	int val, ret;
-
-	ret = stm32mp1_select_ethck_external(plat_dat);
-	if (ret)
-		return ret;
+	int val;
 
 	switch (plat_dat->mac_interface) {
 	case PHY_INTERFACE_MODE_MII:
@@ -262,10 +258,6 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
 		return -EINVAL;
 	}
 
-	ret = stm32mp1_validate_ethck_rate(plat_dat);
-	if (ret)
-		return ret;
-
 	/* Need to update PMCCLRR (clear register) */
 	regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
 		     dwmac->ops->syscfg_eth_mask);
@@ -275,6 +267,21 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
 				 dwmac->ops->syscfg_eth_mask, val);
 }
 
+static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
+{
+	int ret;
+
+	ret = stm32mp1_select_ethck_external(plat_dat);
+	if (ret)
+		return ret;
+
+	ret = stm32mp1_validate_ethck_rate(plat_dat);
+	if (ret)
+		return ret;
+
+	return stm32mp1_configure_pmcr(plat_dat);
+}
+
 static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
 {
 	struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
-- 
2.25.1

[PATCH v4 05/11] net: stmmac: dwmac-stm32: Clean up the debug prints

[Christophe Roullier]

From: Marek Vasut <marex@denx.de>

Use dev_err()/dev_dbg() and phy_modes() to print PHY mode instead of
pr_debug() and hand-written PHY mode decoding. This way, each debug
print has associated device with it and duplicated mode decoding is
removed.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
 .../net/ethernet/stmicro/stmmac/dwmac-stm32.c  | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index aa413edd1ef71..75981ac2cbb56 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -228,19 +228,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
 	switch (plat_dat->mac_interface) {
 	case PHY_INTERFACE_MODE_MII:
 		val = SYSCFG_PMCR_ETH_SEL_MII;
-		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
 		break;
 	case PHY_INTERFACE_MODE_GMII:
 		val = SYSCFG_PMCR_ETH_SEL_GMII;
 		if (dwmac->enable_eth_ck)
 			val |= SYSCFG_PMCR_ETH_CLK_SEL;
-		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
 		break;
 	case PHY_INTERFACE_MODE_RMII:
 		val = SYSCFG_PMCR_ETH_SEL_RMII;
 		if (dwmac->enable_eth_ck)
 			val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
-		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
 		break;
 	case PHY_INTERFACE_MODE_RGMII:
 	case PHY_INTERFACE_MODE_RGMII_ID:
@@ -249,15 +246,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
 		val = SYSCFG_PMCR_ETH_SEL_RGMII;
 		if (dwmac->enable_eth_ck)
 			val |= SYSCFG_PMCR_ETH_CLK_SEL;
-		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
 		break;
 	default:
-		pr_debug("SYSCFG init :  Do not manage %d interface\n",
-			 plat_dat->mac_interface);
+		dev_err(dwmac->dev, "Mode %s not supported",
+			phy_modes(plat_dat->mac_interface));
 		/* Do not manage others interfaces */
 		return -EINVAL;
 	}
 
+	dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
+
 	/* Need to update PMCCLRR (clear register) */
 	regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
 		     dwmac->ops->syscfg_eth_mask);
@@ -291,19 +289,19 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
 	switch (plat_dat->mac_interface) {
 	case PHY_INTERFACE_MODE_MII:
 		val = SYSCFG_MCU_ETH_SEL_MII;
-		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
 		break;
 	case PHY_INTERFACE_MODE_RMII:
 		val = SYSCFG_MCU_ETH_SEL_RMII;
-		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
 		break;
 	default:
-		pr_debug("SYSCFG init :  Do not manage %d interface\n",
-			 plat_dat->mac_interface);
+		dev_err(dwmac->dev, "Mode %s not supported",
+			phy_modes(plat_dat->mac_interface));
 		/* Do not manage others interfaces */
 		return -EINVAL;
 	}
 
+	dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
+
 	return regmap_update_bits(dwmac->regmap, reg,
 				 dwmac->ops->syscfg_eth_mask, val << 23);
 }
-- 
2.25.1

[PATCH v4 06/11] net: stmmac: dwmac-stm32: Fix Mhz to MHz

[Christophe Roullier]

From: Marek Vasut <marex@denx.de>

Trivial, fix up the comments using 'Mhz' to 'MHz'.
No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 75981ac2cbb56..bed2be129b2d2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -58,7 +58,7 @@
  * Below table summarizes the clock requirement and clock sources for
  * supported phy interface modes.
  * __________________________________________________________________________
- *|PHY_MODE | Normal | PHY wo crystal|   PHY wo crystal   |No 125Mhz from PHY|
+ *|PHY_MODE | Normal | PHY wo crystal|   PHY wo crystal   |No 125MHz from PHY|
  *|         |        |      25MHz    |        50MHz       |                  |
  * ---------------------------------------------------------------------------
  *|  MII    |	 -   |     eth-ck    |	      n/a	  |	  n/a        |
@@ -367,7 +367,7 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
 	/* Gigabit Ethernet 125MHz clock selection. */
 	dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel");
 
-	/* Ethernet 50Mhz RMII clock selection */
+	/* Ethernet 50MHz RMII clock selection */
 	dwmac->eth_ref_clk_sel_reg =
 		of_property_read_bool(np, "st,eth-ref-clk-sel");
 
-- 
2.25.1

[PATCH v4 07/11] net: ethernet: stmmac: add management of stm32mp13 for stm32

[Christophe Roullier]

Add Ethernet support for STM32MP13.
STM32MP13 is STM32 SOC with 2 GMACs instances.
GMAC IP version is SNPS 4.20.
GMAC IP configure with 1 RX and 1 TX queue.
DMA HW capability register supported
RX Checksum Offload Engine supported
TX Checksum insertion supported
Wake-Up On Lan supported
TSO supported

Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
 .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 50 +++++++++++++++----
 1 file changed, 40 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index bed2be129b2d2..e59f8a845e01e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -84,12 +84,14 @@ struct stm32_dwmac {
 	struct clk *clk_eth_ck;
 	struct clk *clk_ethstp;
 	struct clk *syscfg_clk;
+	bool is_mp13;
 	int ext_phyclk;
 	int enable_eth_ck;
 	int eth_clk_sel_reg;
 	int eth_ref_clk_sel_reg;
 	int irq_pwr_wakeup;
 	u32 mode_reg;		 /* MAC glue-logic mode register */
+	u32 mode_mask;
 	struct regmap *regmap;
 	u32 speed;
 	const struct stm32_ops *ops;
@@ -102,8 +104,8 @@ struct stm32_ops {
 	void (*resume)(struct stm32_dwmac *dwmac);
 	int (*parse_data)(struct stm32_dwmac *dwmac,
 			  struct device *dev);
-	u32 syscfg_eth_mask;
 	bool clk_rx_enable_in_suspend;
+	u32 syscfg_clr_off;
 };
 
 static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac, bool resume)
@@ -227,7 +229,14 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
 
 	switch (plat_dat->mac_interface) {
 	case PHY_INTERFACE_MODE_MII:
-		val = SYSCFG_PMCR_ETH_SEL_MII;
+		/*
+		 * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
+		 * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
+		 * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx
+		 * supports only MII, ETH_SELMII is not present.
+		 */
+		if (!dwmac->is_mp13)	/* Select MII mode on STM32MP15xx */
+			val |= SYSCFG_PMCR_ETH_SEL_MII;
 		break;
 	case PHY_INTERFACE_MODE_GMII:
 		val = SYSCFG_PMCR_ETH_SEL_GMII;
@@ -256,13 +265,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
 
 	dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
 
+	/* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
+	val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);
+
 	/* Need to update PMCCLRR (clear register) */
-	regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
-		     dwmac->ops->syscfg_eth_mask);
+	regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off,
+		     dwmac->mode_mask);
 
 	/* Update PMCSETR (set register) */
 	return regmap_update_bits(dwmac->regmap, reg,
-				 dwmac->ops->syscfg_eth_mask, val);
+				 dwmac->mode_mask, val);
 }
 
 static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
@@ -303,7 +315,7 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
 	dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
 
 	return regmap_update_bits(dwmac->regmap, reg,
-				 dwmac->ops->syscfg_eth_mask, val << 23);
+				 SYSCFG_MCU_ETH_MASK, val << 23);
 }
 
 static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac, bool suspend)
@@ -348,8 +360,15 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
 		return PTR_ERR(dwmac->regmap);
 
 	err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg);
-	if (err)
+	if (err) {
 		dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err);
+		return err;
+	}
+
+	dwmac->mode_mask = SYSCFG_MP1_ETH_MASK;
+	err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask);
+	if (err)
+		pr_debug("Warning sysconfig register mask not set\n");
 
 	return err;
 }
@@ -361,6 +380,8 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
 	struct device_node *np = dev->of_node;
 	int err = 0;
 
+	dwmac->is_mp13 = of_device_is_compatible(np, "st,stm32mp13-dwmac");
+
 	/* Ethernet PHY have no crystal */
 	dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
 
@@ -540,8 +561,7 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
 	stm32_dwmac_suspend, stm32_dwmac_resume);
 
 static struct stm32_ops stm32mcu_dwmac_data = {
-	.set_mode = stm32mcu_set_mode,
-	.syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
+	.set_mode = stm32mcu_set_mode
 };
 
 static struct stm32_ops stm32mp1_dwmac_data = {
@@ -549,13 +569,23 @@ static struct stm32_ops stm32mp1_dwmac_data = {
 	.suspend = stm32mp1_suspend,
 	.resume = stm32mp1_resume,
 	.parse_data = stm32mp1_parse_data,
-	.syscfg_eth_mask = SYSCFG_MP1_ETH_MASK,
+	.syscfg_clr_off = 0x44,
+	.clk_rx_enable_in_suspend = true
+};
+
+static struct stm32_ops stm32mp13_dwmac_data = {
+	.set_mode = stm32mp1_set_mode,
+	.suspend = stm32mp1_suspend,
+	.resume = stm32mp1_resume,
+	.parse_data = stm32mp1_parse_data,
+	.syscfg_clr_off = 0x08,
 	.clk_rx_enable_in_suspend = true
 };
 
 static const struct of_device_id stm32_dwmac_match[] = {
 	{ .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
 	{ .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},
+	{ .compatible = "st,stm32mp13-dwmac", .data = &stm32mp13_dwmac_data},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, stm32_dwmac_match);
-- 
2.25.1

[PATCH v4 08/11] ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13

[Christophe Roullier]

Both instances ethernet based on GMAC SNPS IP on stm32mp13.
GMAC IP version is SNPS 4.20.

Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
 arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++++++++++++++++++++++++++
 arch/arm/boot/dts/st/stm32mp133.dtsi | 31 +++++++++++++++++++++++
 2 files changed, 69 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
index 6704ceef284d3..9d05853ececf7 100644
--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
@@ -979,6 +979,12 @@ ts_cal1: calib@5c {
 			ts_cal2: calib@5e {
 				reg = <0x5e 0x2>;
 			};
+			ethernet_mac1_address: mac1@e4 {
+				reg = <0xe4 0x6>;
+			};
+			ethernet_mac2_address: mac2@ea {
+				reg = <0xea 0x6>;
+			};
 		};
 
 		etzpc: bus@5c007000 {
@@ -1505,6 +1511,38 @@ sdmmc2: mmc@58007000 {
 				status = "disabled";
 			};
 
+			ethernet1: ethernet@5800a000 {
+				compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
+				reg = <0x5800a000 0x2000>;
+				reg-names = "stmmaceth";
+				interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+						      <&exti 68 1>;
+				interrupt-names = "macirq", "eth_wake_irq";
+				clock-names = "stmmaceth",
+					      "mac-clk-tx",
+					      "mac-clk-rx",
+					      "ethstp",
+					      "eth-ck";
+				clocks = <&rcc ETH1MAC>,
+					 <&rcc ETH1TX>,
+					 <&rcc ETH1RX>,
+					 <&rcc ETH1STP>,
+					 <&rcc ETH1CK_K>;
+				st,syscon = <&syscfg 0x4 0xff0000>;
+				snps,mixed-burst;
+				snps,pbl = <2>;
+				snps,axi-config = <&stmmac_axi_config_1>;
+				snps,tso;
+				access-controllers = <&etzpc 48>;
+				status = "disabled";
+
+				stmmac_axi_config_1: stmmac-axi-config {
+					snps,wr_osr_lmt = <0x7>;
+					snps,rd_osr_lmt = <0x7>;
+					snps,blen = <0 0 0 0 16 8 4>;
+				};
+			};
+
 			usbphyc: usbphyc@5a006000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi
index 3e394c8e58b92..09c7da1a2eda8 100644
--- a/arch/arm/boot/dts/st/stm32mp133.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp133.dtsi
@@ -67,5 +67,36 @@ channel@18 {
 				label = "vrefint";
 			};
 		};
+
+		ethernet2: ethernet@5800e000 {
+			compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
+			reg = <0x5800e000 0x2000>;
+			reg-names = "stmmaceth";
+			interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clock-names = "stmmaceth",
+				      "mac-clk-tx",
+				      "mac-clk-rx",
+				      "ethstp",
+				      "eth-ck";
+			clocks = <&rcc ETH2MAC>,
+				 <&rcc ETH2TX>,
+				 <&rcc ETH2RX>,
+				 <&rcc ETH2STP>,
+				 <&rcc ETH2CK_K>;
+			st,syscon = <&syscfg 0x4 0xff000000>;
+			snps,mixed-burst;
+			snps,pbl = <2>;
+			snps,axi-config = <&stmmac_axi_config_2>;
+			snps,tso;
+			access-controllers = <&etzpc 49>;
+			status = "disabled";
+
+			stmmac_axi_config_2: stmmac-axi-config {
+				snps,wr_osr_lmt = <0x7>;
+				snps,rd_osr_lmt = <0x7>;
+				snps,blen = <0 0 0 0 16 8 4>;
+			};
+		};
 	};
 };
-- 
2.25.1

[PATCH v4 09/11] ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board

[Christophe Roullier]

Those pins are used for Ethernet 1 and 2 on STM32MP13F-DK board.
ethernet1: RMII with crystal.
ethernet2: RMII without crystal.
Add analog gpio pin configuration ("sleep") to manage power mode on
stm32mp13.

Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
 arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 71 +++++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
index 32c5d8a1e06ac..7f72c62da0a64 100644
--- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
@@ -13,6 +13,77 @@ pins {
 		};
 	};
 
+	eth1_rmii_pins_a: eth1-rmii-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RMII_TXD0 */
+				 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RMII_TXD1 */
+				 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RMII_TX_EN */
+				 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
+				 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+				 <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <1>;
+		};
+
+		pins2 {
+			pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
+				 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RMII_RXD1 */
+				 <STM32_PINMUX('C', 1, AF10)>; /* ETH_RMII_CRS_DV */
+			bias-disable;
+		};
+
+	};
+
+	eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RMII_TXD0 */
+				 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RMII_TXD1 */
+				 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RMII_TX_EN */
+				 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RMII_REF_CLK */
+				 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+				 <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
+				 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RMII_RXD0 */
+				 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RMII_RXD1 */
+				 <STM32_PINMUX('C', 1, ANALOG)>; /* ETH_RMII_CRS_DV */
+		};
+	};
+
+	eth2_rmii_pins_a: eth2-rmii-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RMII_TXD0 */
+				 <STM32_PINMUX('G', 11, AF10)>, /* ETH_RMII_TXD1 */
+				 <STM32_PINMUX('G', 8, AF13)>, /* ETH_RMII_ETHCK */
+				 <STM32_PINMUX('F', 6, AF11)>, /* ETH_RMII_TX_EN */
+				 <STM32_PINMUX('B', 2, AF11)>, /* ETH_MDIO */
+				 <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <1>;
+		};
+
+		pins2 {
+			pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RMII_RXD0 */
+				 <STM32_PINMUX('E', 2, AF10)>, /* ETH_RMII_RXD1 */
+				 <STM32_PINMUX('A', 12, AF11)>; /* ETH_RMII_CRS_DV */
+			bias-disable;
+		};
+	};
+
+	eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RMII_TXD0 */
+				 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RMII_TXD1 */
+				 <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RMII_ETHCK */
+				 <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RMII_TX_EN */
+				 <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
+				 <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
+				 <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RMII_RXD0 */
+				 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RMII_RXD1 */
+				 <STM32_PINMUX('A', 12, ANALOG)>; /* ETH_RMII_CRS_DV */
+		};
+	};
+
 	i2c1_pins_a: i2c1-0 {
 		pins {
 			pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
-- 
2.25.1

[PATCH v4 10/11] ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board

[Christophe Roullier]

Ethernet1: RMII with crystal
PHY used is SMSC (LAN8742A)

Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
 arch/arm/boot/dts/st/stm32mp135f-dk.dts | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
index 567e53ad285fa..16e91b9d812d8 100644
--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
@@ -19,6 +19,7 @@ / {
 	compatible = "st,stm32mp135f-dk", "st,stm32mp135";
 
 	aliases {
+		ethernet0 = &ethernet1;
 		serial0 = &uart4;
 		serial1 = &usart1;
 		serial2 = &uart8;
@@ -141,6 +142,28 @@ &cryp {
 	status = "okay";
 };
 
+&ethernet1 {
+	status = "okay";
+	pinctrl-0 = <&eth1_rmii_pins_a>;
+	pinctrl-1 = <&eth1_rmii_sleep_pins_a>;
+	pinctrl-names = "default", "sleep";
+	phy-mode = "rmii";
+	phy-handle = <&phy0_eth1>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+
+		phy0_eth1: ethernet-phy@0 {
+			compatible = "ethernet-phy-id0007.c131";
+			reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>;
+			reg = <0>;
+			wakeup-source;
+		};
+	};
+};
+
 &i2c1 {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&i2c1_pins_a>;
-- 
2.25.1

[PATCH v4 11/11] ARM: multi_v7_defconfig: Add MCP23S08 pinctrl support

[Christophe Roullier]

Need to enable MCP23S08 I/O expanders to manage Ethernet PHY
reset in STM32MP135F-DK board.
Put this config in built-in like STMMAC to avoid huge of Ethernet
messages during boot (deferred)

Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 86bf057ac3663..9758f3d41ad70 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -469,6 +469,7 @@ CONFIG_SPI_XILINX=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_SPMI=y
 CONFIG_PINCTRL_AS3722=y
+CONFIG_PINCTRL_MCP23S08=y
 CONFIG_PINCTRL_MICROCHIP_SGPIO=y
 CONFIG_PINCTRL_OCELOT=y
 CONFIG_PINCTRL_PALMAS=y
-- 
2.25.1

Re: [PATCH v4 00/11] Series to deliver Ethernet for STM32MP13

[Rob Herring (Arm)]

On Tue, 04 Jun 2024 16:34:51 +0200, Christophe Roullier wrote:
> STM32MP13 is STM32 SOC with 2 GMACs instances
>     GMAC IP version is SNPS 4.20.
>     GMAC IP configure with 1 RX and 1 TX queue.
>     DMA HW capability register supported
>     RX Checksum Offload Engine supported
>     TX Checksum insertion supported
>     Wake-Up On Lan supported
>     TSO supported
> Rework dwmac glue to simplify management for next stm32 (integrate RFC from Marek)
> 
> V2: - Remark from Rob Herring (add Krzysztof's ack in patch 02/11, update in yaml)
>       Remark from Serge Semin (upate commits msg)
> V3: - Remove PHY regulator patch and Ethernet2 DT because need to clarify how to
>       manage PHY regulator (in glue or PHY side)
>     - Integrate RFC from Marek
>     - Remark from Rob Herring in YAML documentation
> V4: - Remark from Marek (remove max-speed, extra space in DT, update commit msg)
>     - Remark from Rasmus (add sign-off, add base-commit)
>     - Remark from Sai Krishna Gajula
> 
> Christophe Roullier (6):
>   dt-bindings: net: add STM32MP13 compatible in documentation for stm32
>   net: ethernet: stmmac: add management of stm32mp13 for stm32
>   ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13
>   ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board
>   ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board
>   ARM: multi_v7_defconfig: Add MCP23S08 pinctrl support
> 
> Marek Vasut (5):
>   net: stmmac: dwmac-stm32: Separate out external clock rate validation
>   net: stmmac: dwmac-stm32: Separate out external clock selector
>   net: stmmac: dwmac-stm32: Extract PMCR configuration
>   net: stmmac: dwmac-stm32: Clean up the debug prints
>   net: stmmac: dwmac-stm32: Fix Mhz to MHz
> 
>  .../devicetree/bindings/net/stm32-dwmac.yaml  |  41 ++++-
>  arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi   |  71 ++++++++
>  arch/arm/boot/dts/st/stm32mp131.dtsi          |  38 ++++
>  arch/arm/boot/dts/st/stm32mp133.dtsi          |  31 ++++
>  arch/arm/boot/dts/st/stm32mp135f-dk.dts       |  23 +++
>  arch/arm/configs/multi_v7_defconfig           |   1 +
>  .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 172 ++++++++++++++----
>  7 files changed, 330 insertions(+), 47 deletions(-)
> 
> 
> base-commit: cd0057ad75116bacf16fea82e48c1db642971136
> --
> 2.25.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y st/stm32mp135f-dk.dtb' for 20240604143502.154463-1-christophe.roullier@foss.st.com:

arch/arm/boot/dts/st/stm32mp135f-dk.dtb: adc@48003000: 'ethernet@5800e000' does not match any of the regexes: '^adc@[0-9]+$', 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#

Re: [PATCH v4 00/11] Series to deliver Ethernet for STM32MP13

[Christophe ROULLIER]

On 6/4/24 17:29, Rob Herring (Arm) wrote:
> On Tue, 04 Jun 2024 16:34:51 +0200, Christophe Roullier wrote:
>> STM32MP13 is STM32 SOC with 2 GMACs instances
>>      GMAC IP version is SNPS 4.20.
>>      GMAC IP configure with 1 RX and 1 TX queue.
>>      DMA HW capability register supported
>>      RX Checksum Offload Engine supported
>>      TX Checksum insertion supported
>>      Wake-Up On Lan supported
>>      TSO supported
>> Rework dwmac glue to simplify management for next stm32 (integrate RFC from Marek)
>>
>> V2: - Remark from Rob Herring (add Krzysztof's ack in patch 02/11, update in yaml)
>>        Remark from Serge Semin (upate commits msg)
>> V3: - Remove PHY regulator patch and Ethernet2 DT because need to clarify how to
>>        manage PHY regulator (in glue or PHY side)
>>      - Integrate RFC from Marek
>>      - Remark from Rob Herring in YAML documentation
>> V4: - Remark from Marek (remove max-speed, extra space in DT, update commit msg)
>>      - Remark from Rasmus (add sign-off, add base-commit)
>>      - Remark from Sai Krishna Gajula
>>
>> Christophe Roullier (6):
>>    dt-bindings: net: add STM32MP13 compatible in documentation for stm32
>>    net: ethernet: stmmac: add management of stm32mp13 for stm32
>>    ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13
>>    ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board
>>    ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board
>>    ARM: multi_v7_defconfig: Add MCP23S08 pinctrl support
>>
>> Marek Vasut (5):
>>    net: stmmac: dwmac-stm32: Separate out external clock rate validation
>>    net: stmmac: dwmac-stm32: Separate out external clock selector
>>    net: stmmac: dwmac-stm32: Extract PMCR configuration
>>    net: stmmac: dwmac-stm32: Clean up the debug prints
>>    net: stmmac: dwmac-stm32: Fix Mhz to MHz
>>
>>   .../devicetree/bindings/net/stm32-dwmac.yaml  |  41 ++++-
>>   arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi   |  71 ++++++++
>>   arch/arm/boot/dts/st/stm32mp131.dtsi          |  38 ++++
>>   arch/arm/boot/dts/st/stm32mp133.dtsi          |  31 ++++
>>   arch/arm/boot/dts/st/stm32mp135f-dk.dts       |  23 +++
>>   arch/arm/configs/multi_v7_defconfig           |   1 +
>>   .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 172 ++++++++++++++----
>>   7 files changed, 330 insertions(+), 47 deletions(-)
>>
>>
>> base-commit: cd0057ad75116bacf16fea82e48c1db642971136
>> --
>> 2.25.1
>>
>>
>>
>
> My bot found new DTB warnings on the .dts files added or changed in this
> series.
>
> Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
> are fixed by another series. Ultimately, it is up to the platform
> maintainer whether these warnings are acceptable or not. No need to reply
> unless the platform maintainer has comments.
>
> If you already ran DT checks and didn't see these error(s), then
> make sure dt-schema is up to date:
>
>    pip3 install dtschema --upgrade
>
>
> New warnings running 'make CHECK_DTBS=y st/stm32mp135f-dk.dtb' for 20240604143502.154463-1-christophe.roullier@foss.st.com:
>
> arch/arm/boot/dts/st/stm32mp135f-dk.dtb: adc@48003000: 'ethernet@5800e000' does not match any of the regexes: '^adc@[0-9]+$', 'pinctrl-[0-9]+'
> 	from schema $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
>
Hi Rob,

I will provide v5 to fix it.

Thanks

>
>
>

Re: [PATCH v4 08/11] ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13

[Marek Vasut]

On 6/4/24 4:34 PM, Christophe Roullier wrote:
> Both instances ethernet based on GMAC SNPS IP on stm32mp13.
> GMAC IP version is SNPS 4.20.
> 
> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
> ---
>   arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++++++++++++++++++++++++++
>   arch/arm/boot/dts/st/stm32mp133.dtsi | 31 +++++++++++++++++++++++
>   2 files changed, 69 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
> index 6704ceef284d3..9d05853ececf7 100644
> --- a/arch/arm/boot/dts/st/stm32mp131.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
> @@ -979,6 +979,12 @@ ts_cal1: calib@5c {
>   			ts_cal2: calib@5e {
>   				reg = <0x5e 0x2>;
>   			};
> +			ethernet_mac1_address: mac1@e4 {
> +				reg = <0xe4 0x6>;
> +			};
> +			ethernet_mac2_address: mac2@ea {
> +				reg = <0xea 0x6>;
> +			};
>   		};
>   
>   		etzpc: bus@5c007000 {
> @@ -1505,6 +1511,38 @@ sdmmc2: mmc@58007000 {
>   				status = "disabled";
>   			};
>   
> +			ethernet1: ethernet@5800a000 {
> +				compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
> +				reg = <0x5800a000 0x2000>;
> +				reg-names = "stmmaceth";
> +				interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> +						      <&exti 68 1>;
> +				interrupt-names = "macirq", "eth_wake_irq";
> +				clock-names = "stmmaceth",
> +					      "mac-clk-tx",
> +					      "mac-clk-rx",
> +					      "ethstp",
> +					      "eth-ck";
> +				clocks = <&rcc ETH1MAC>,
> +					 <&rcc ETH1TX>,
> +					 <&rcc ETH1RX>,
> +					 <&rcc ETH1STP>,
> +					 <&rcc ETH1CK_K>;
> +				st,syscon = <&syscfg 0x4 0xff0000>;
> +				snps,mixed-burst;
> +				snps,pbl = <2>;
> +				snps,axi-config = <&stmmac_axi_config_1>;
> +				snps,tso;
> +				access-controllers = <&etzpc 48>;

Please keep the list of properties sorted.

> +				status = "disabled";
> +
> +				stmmac_axi_config_1: stmmac-axi-config {
> +					snps,wr_osr_lmt = <0x7>;
> +					snps,rd_osr_lmt = <0x7>;
> +					snps,blen = <0 0 0 0 16 8 4>;

Sort here too.

> +				};
> +			};
> +
>   			usbphyc: usbphyc@5a006000 {
>   				#address-cells = <1>;
>   				#size-cells = <0>;
> diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi
> index 3e394c8e58b92..09c7da1a2eda8 100644
> --- a/arch/arm/boot/dts/st/stm32mp133.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi
> @@ -67,5 +67,36 @@ channel@18 {
>   				label = "vrefint";
>   			};
>   		};
> +
> +		ethernet2: ethernet@5800e000 {
> +			compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
> +			reg = <0x5800e000 0x2000>;
> +			reg-names = "stmmaceth";
> +			interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "macirq";
> +			clock-names = "stmmaceth",
> +				      "mac-clk-tx",
> +				      "mac-clk-rx",
> +				      "ethstp",
> +				      "eth-ck";
> +			clocks = <&rcc ETH2MAC>,
> +				 <&rcc ETH2TX>,
> +				 <&rcc ETH2RX>,
> +				 <&rcc ETH2STP>,
> +				 <&rcc ETH2CK_K>;
> +			st,syscon = <&syscfg 0x4 0xff000000>;
> +			snps,mixed-burst;
> +			snps,pbl = <2>;
> +			snps,axi-config = <&stmmac_axi_config_2>;
> +			snps,tso;
> +			access-controllers = <&etzpc 49>;

Sort here too.

> +			status = "disabled";
> +
> +			stmmac_axi_config_2: stmmac-axi-config {
> +				snps,wr_osr_lmt = <0x7>;
> +				snps,rd_osr_lmt = <0x7>;
> +				snps,blen = <0 0 0 0 16 8 4>;

Sort here too.

[...]

Re: [PATCH v4 10/11] ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board

[Marek Vasut]

On 6/4/24 4:35 PM, Christophe Roullier wrote:
> Ethernet1: RMII with crystal
> PHY used is SMSC (LAN8742A)

Doesn't the STM32MP135F-DK come with two ethernet ports ?
Why not enable both ?

Re: [PATCH v4 11/11] ARM: multi_v7_defconfig: Add MCP23S08 pinctrl support

[Marek Vasut]

On 6/4/24 4:35 PM, Christophe Roullier wrote:
> Need to enable MCP23S08 I/O expanders to manage Ethernet PHY
> reset in STM32MP135F-DK board.
> Put this config in built-in like STMMAC to avoid huge of Ethernet
> messages during boot (deferred)

You're not avoiding any error/defer/messages here, you simply need to 
enable the MCP23S08 GPIO controller driver, so the kernel can use the 
GPIO provided by that driver instance to release the ethernet PHY from 
reset on STM32MP135F-DK, that's all.

Re: [PATCH v4 07/11] net: ethernet: stmmac: add management of stm32mp13 for stm32

[Marek Vasut]

On 6/4/24 4:34 PM, Christophe Roullier wrote:
> Add Ethernet support for STM32MP13.
> STM32MP13 is STM32 SOC with 2 GMACs instances.
> GMAC IP version is SNPS 4.20.
> GMAC IP configure with 1 RX and 1 TX queue.
> DMA HW capability register supported
> RX Checksum Offload Engine supported
> TX Checksum insertion supported
> Wake-Up On Lan supported
> TSO supported
> 
> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
> ---
>   .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 50 +++++++++++++++----
>   1 file changed, 40 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> index bed2be129b2d2..e59f8a845e01e 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> @@ -84,12 +84,14 @@ struct stm32_dwmac {
>   	struct clk *clk_eth_ck;
>   	struct clk *clk_ethstp;
>   	struct clk *syscfg_clk;
> +	bool is_mp13;
>   	int ext_phyclk;
>   	int enable_eth_ck;
>   	int eth_clk_sel_reg;
>   	int eth_ref_clk_sel_reg;
>   	int irq_pwr_wakeup;
>   	u32 mode_reg;		 /* MAC glue-logic mode register */
> +	u32 mode_mask;
>   	struct regmap *regmap;
>   	u32 speed;
>   	const struct stm32_ops *ops;
> @@ -102,8 +104,8 @@ struct stm32_ops {
>   	void (*resume)(struct stm32_dwmac *dwmac);
>   	int (*parse_data)(struct stm32_dwmac *dwmac,
>   			  struct device *dev);
> -	u32 syscfg_eth_mask;
>   	bool clk_rx_enable_in_suspend;
> +	u32 syscfg_clr_off;
>   };
>   
>   static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac, bool resume)
> @@ -227,7 +229,14 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
>   
>   	switch (plat_dat->mac_interface) {
>   	case PHY_INTERFACE_MODE_MII:
> -		val = SYSCFG_PMCR_ETH_SEL_MII;
> +		/*
> +		 * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
> +		 * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
> +		 * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx
> +		 * supports only MII, ETH_SELMII is not present.
> +		 */
> +		if (!dwmac->is_mp13)	/* Select MII mode on STM32MP15xx */
> +			val |= SYSCFG_PMCR_ETH_SEL_MII;
>   		break;
>   	case PHY_INTERFACE_MODE_GMII:
>   		val = SYSCFG_PMCR_ETH_SEL_GMII;
> @@ -256,13 +265,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
>   
>   	dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
>   
> +	/* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
> +	val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);
> +
>   	/* Need to update PMCCLRR (clear register) */
> -	regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
> -		     dwmac->ops->syscfg_eth_mask);
> +	regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off,
> +		     dwmac->mode_mask);
>   
>   	/* Update PMCSETR (set register) */
>   	return regmap_update_bits(dwmac->regmap, reg,
> -				 dwmac->ops->syscfg_eth_mask, val);
> +				 dwmac->mode_mask, val);
>   }
>   
>   static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
> @@ -303,7 +315,7 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
>   	dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
>   
>   	return regmap_update_bits(dwmac->regmap, reg,
> -				 dwmac->ops->syscfg_eth_mask, val << 23);
> +				 SYSCFG_MCU_ETH_MASK, val << 23);
>   }
>   
>   static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac, bool suspend)
> @@ -348,8 +360,15 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
>   		return PTR_ERR(dwmac->regmap);
>   
>   	err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg);
> -	if (err)
> +	if (err) {
>   		dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err);
> +		return err;
> +	}
> +
> +	dwmac->mode_mask = SYSCFG_MP1_ETH_MASK;
> +	err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask);
> +	if (err)
> +		pr_debug("Warning sysconfig register mask not set\n");

I _think_ you need to left-shift the mode mask by 8 for STM32MP13xx 
second GMAC somewhere in here, right ?

>   	return err;
>   }
> @@ -361,6 +380,8 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
>   	struct device_node *np = dev->of_node;
>   	int err = 0;
>   
> +	dwmac->is_mp13 = of_device_is_compatible(np, "st,stm32mp13-dwmac");

You could make is_mp13 part of struct stm32_ops {} just like 
syscfg_clr_off is part of struct stm32_ops {} .

>   	/* Ethernet PHY have no crystal */
>   	dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
>   
> @@ -540,8 +561,7 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
>   	stm32_dwmac_suspend, stm32_dwmac_resume);
>   
>   static struct stm32_ops stm32mcu_dwmac_data = {
> -	.set_mode = stm32mcu_set_mode,
> -	.syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
> +	.set_mode = stm32mcu_set_mode

It is not necessary to remove the trailing comma ','

>   };
>   
>   static struct stm32_ops stm32mp1_dwmac_data = {
> @@ -549,13 +569,23 @@ static struct stm32_ops stm32mp1_dwmac_data = {
>   	.suspend = stm32mp1_suspend,
>   	.resume = stm32mp1_resume,
>   	.parse_data = stm32mp1_parse_data,
> -	.syscfg_eth_mask = SYSCFG_MP1_ETH_MASK,
> +	.syscfg_clr_off = 0x44,
> +	.clk_rx_enable_in_suspend = true
> +};
> +
> +static struct stm32_ops stm32mp13_dwmac_data = {
> +	.set_mode = stm32mp1_set_mode,
> +	.suspend = stm32mp1_suspend,
> +	.resume = stm32mp1_resume,
> +	.parse_data = stm32mp1_parse_data,
> +	.syscfg_clr_off = 0x08,
>   	.clk_rx_enable_in_suspend = true
>   };
>   
>   static const struct of_device_id stm32_dwmac_match[] = {
>   	{ .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
>   	{ .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},
> +	{ .compatible = "st,stm32mp13-dwmac", .data = &stm32mp13_dwmac_data},
>   	{ }
>   };
>   MODULE_DEVICE_TABLE(of, stm32_dwmac_match);

This patch definitely looks MUCH better than what this series started 
with, it is much easier to grasp the MP13 specific changes.

You could possibly improve this further and split the 
dwmac->ops->syscfg_eth_mask to dwmac->mode_mask conversion into separate 
preparatory patch (as a 6.5/11 in context of this series), and then add 
the few MP13 changes on top (as 7/11 patch).

Re: [PATCH v4 07/11] net: ethernet: stmmac: add management of stm32mp13 for stm32

[kernel test robot]

Hi Christophe,

kernel test robot noticed the following build warnings:

[auto build test WARNING on cd0057ad75116bacf16fea82e48c1db642971136]

url:    https://github.com/intel-lab-lkp/linux/commits/Christophe-Roullier/dt-bindings-net-add-STM32MP13-compatible-in-documentation-for-stm32/20240604-224324
base:   cd0057ad75116bacf16fea82e48c1db642971136
patch link:    https://lore.kernel.org/r/20240604143502.154463-8-christophe.roullier%40foss.st.com
patch subject: [PATCH v4 07/11] net: ethernet: stmmac: add management of stm32mp13 for stm32
config: arm-defconfig (https://download.01.org/0day-ci/archive/20240605/202406050248.rGgTkevY-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240605/202406050248.rGgTkevY-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202406050248.rGgTkevY-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c:239:4: warning: variable 'val' is uninitialized when used here [-Wuninitialized]
                           val |= SYSCFG_PMCR_ETH_SEL_MII;
                           ^~~
   drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c:228:9: note: initialize the variable 'val' to silence this warning
           int val;
                  ^
                   = 0
   1 warning generated.


vim +/val +239 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c

   223	
   224	static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
   225	{
   226		struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
   227		u32 reg = dwmac->mode_reg;
   228		int val;
   229	
   230		switch (plat_dat->mac_interface) {
   231		case PHY_INTERFACE_MODE_MII:
   232			/*
   233			 * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
   234			 * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
   235			 * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx
   236			 * supports only MII, ETH_SELMII is not present.
   237			 */
   238			if (!dwmac->is_mp13)	/* Select MII mode on STM32MP15xx */
 > 239				val |= SYSCFG_PMCR_ETH_SEL_MII;
   240			break;
   241		case PHY_INTERFACE_MODE_GMII:
   242			val = SYSCFG_PMCR_ETH_SEL_GMII;
   243			if (dwmac->enable_eth_ck)
   244				val |= SYSCFG_PMCR_ETH_CLK_SEL;
   245			break;
   246		case PHY_INTERFACE_MODE_RMII:
   247			val = SYSCFG_PMCR_ETH_SEL_RMII;
   248			if (dwmac->enable_eth_ck)
   249				val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
   250			break;
   251		case PHY_INTERFACE_MODE_RGMII:
   252		case PHY_INTERFACE_MODE_RGMII_ID:
   253		case PHY_INTERFACE_MODE_RGMII_RXID:
   254		case PHY_INTERFACE_MODE_RGMII_TXID:
   255			val = SYSCFG_PMCR_ETH_SEL_RGMII;
   256			if (dwmac->enable_eth_ck)
   257				val |= SYSCFG_PMCR_ETH_CLK_SEL;
   258			break;
   259		default:
   260			dev_err(dwmac->dev, "Mode %s not supported",
   261				phy_modes(plat_dat->mac_interface));
   262			/* Do not manage others interfaces */
   263			return -EINVAL;
   264		}
   265	
   266		dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
   267	
   268		/* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
   269		val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);
   270	
   271		/* Need to update PMCCLRR (clear register) */
   272		regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off,
   273			     dwmac->mode_mask);
   274	
   275		/* Update PMCSETR (set register) */
   276		return regmap_update_bits(dwmac->regmap, reg,
   277					 dwmac->mode_mask, val);
   278	}
   279	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v4 10/11] ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board

[Christophe ROULLIER]

On 6/4/24 18:52, Marek Vasut wrote:
> On 6/4/24 4:35 PM, Christophe Roullier wrote:
>> Ethernet1: RMII with crystal
>> PHY used is SMSC (LAN8742A)
>
> Doesn't the STM32MP135F-DK come with two ethernet ports ?
> Why not enable both ?

Hi Marek,

As already discussed in V2, second ethernet have no cristal and need 
"phy-supply" property to work, today this property is managed by 
Ethernet glue, but

should be present and managed in PHY node (as explained by Rob). So I 
will push second Ethernet in next step ;-)

Re: [PATCH v4 01/11] dt-bindings: net: add STM32MP13 compatible in documentation for stm32

[Krzysztof Kozlowski]

On 04/06/2024 16:34, Christophe Roullier wrote:
> New STM32 SOC have 2 GMACs instances.
> GMAC IP version is SNPS 4.20.
> 
> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
> ---
>  .../devicetree/bindings/net/stm32-dwmac.yaml  | 41 +++++++++++++++----
>  1 file changed, 34 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
> index 7ccf75676b6d5..ecbed9a7aaf6d 100644
> --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
> @@ -22,18 +22,17 @@ select:
>          enum:
>            - st,stm32-dwmac
>            - st,stm32mp1-dwmac
> +          - st,stm32mp13-dwmac
>    required:
>      - compatible
>  
> -allOf:
> -  - $ref: snps,dwmac.yaml#
> -
>  properties:
>    compatible:
>      oneOf:
>        - items:
>            - enum:
>                - st,stm32mp1-dwmac
> +              - st,stm32mp13-dwmac
>            - const: snps,dwmac-4.20a
>        - items:
>            - enum:
> @@ -75,12 +74,15 @@ properties:
>    st,syscon:
>      $ref: /schemas/types.yaml#/definitions/phandle-array
>      items:
> -      - items:
> +      - minItems: 2
> +        items:
>            - description: phandle to the syscon node which encompases the glue register
>            - description: offset of the control register
> +          - description: field to set mask in register
>      description:
>        Should be phandle/offset pair. The phandle to the syscon node which
> -      encompases the glue register, and the offset of the control register
> +      encompases the glue register, the offset of the control register and
> +      the mask to set bitfield in control register
>  
>    st,ext-phyclk:
>      description:
> @@ -112,12 +114,37 @@ required:
>  
>  unevaluatedProperties: false
>  
> +allOf:
> +  - $ref: snps,dwmac.yaml#
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - st,stm32mp1-dwmac
> +              - st,stm32-dwmac
> +    then:
> +      properties:
> +        st,syscon:
> +          items:
> +            maxItems: 2
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - st,stm32mp13-dwmac
> +    then:
> +      properties:
> +        st,syscon:
> +          items:
> +            minItems: 3

I don't think this works. You now constrain the first dimension which
had only one item before.

Make your example complete and test it.

Best regards,
Krzysztof

Re: [PATCH v4 01/11] dt-bindings: net: add STM32MP13 compatible in documentation for stm32

[Christophe ROULLIER]

On 6/5/24 10:14, Krzysztof Kozlowski wrote:
> On 04/06/2024 16:34, Christophe Roullier wrote:
>> New STM32 SOC have 2 GMACs instances.
>> GMAC IP version is SNPS 4.20.
>>
>> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
>> ---
>>   .../devicetree/bindings/net/stm32-dwmac.yaml  | 41 +++++++++++++++----
>>   1 file changed, 34 insertions(+), 7 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
>> index 7ccf75676b6d5..ecbed9a7aaf6d 100644
>> --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
>> +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
>> @@ -22,18 +22,17 @@ select:
>>           enum:
>>             - st,stm32-dwmac
>>             - st,stm32mp1-dwmac
>> +          - st,stm32mp13-dwmac
>>     required:
>>       - compatible
>>   
>> -allOf:
>> -  - $ref: snps,dwmac.yaml#
>> -
>>   properties:
>>     compatible:
>>       oneOf:
>>         - items:
>>             - enum:
>>                 - st,stm32mp1-dwmac
>> +              - st,stm32mp13-dwmac
>>             - const: snps,dwmac-4.20a
>>         - items:
>>             - enum:
>> @@ -75,12 +74,15 @@ properties:
>>     st,syscon:
>>       $ref: /schemas/types.yaml#/definitions/phandle-array
>>       items:
>> -      - items:
>> +      - minItems: 2
>> +        items:
>>             - description: phandle to the syscon node which encompases the glue register
>>             - description: offset of the control register
>> +          - description: field to set mask in register
>>       description:
>>         Should be phandle/offset pair. The phandle to the syscon node which
>> -      encompases the glue register, and the offset of the control register
>> +      encompases the glue register, the offset of the control register and
>> +      the mask to set bitfield in control register
>>   
>>     st,ext-phyclk:
>>       description:
>> @@ -112,12 +114,37 @@ required:
>>   
>>   unevaluatedProperties: false
>>   
>> +allOf:
>> +  - $ref: snps,dwmac.yaml#
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            enum:
>> +              - st,stm32mp1-dwmac
>> +              - st,stm32-dwmac
>> +    then:
>> +      properties:
>> +        st,syscon:
>> +          items:
>> +            maxItems: 2
>> +
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            enum:
>> +              - st,stm32mp13-dwmac
>> +    then:
>> +      properties:
>> +        st,syscon:
>> +          items:
>> +            minItems: 3
> I don't think this works. You now constrain the first dimension which
> had only one item before.
>
> Make your example complete and test it.
>
> Best regards,
> Krzysztof

Hi Krzysztof,

"Official" bindings for MP15: st,syscon = <&syscfg 0x4>;
"Official" bindings for MP13: st,syscon = <&syscfg 0x4 0xff0000>; or 
st,syscon = <&syscfg 0x4 0xff000000>;

If I execute make dt_binding_check 
DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/stm32-dwmac.yaml with:

    For MP15: st,syscon = <&syscfg>; 
=>bindings/net/stm32-dwmac.example.dtb: ethernet@40027000: st,syscon:0: 
[4294967295] is too short

    For MP15: st,syscon = <&syscfg 0x4 0xff0000>; 
=>devicetree/bindings/net/stm32-dwmac.example.dtb: ethernet@40027000: 
st,syscon:0: [4294967295, 4, 16711680] is too long

    For MP13: st,syscon = <&syscfg 0x4>; => 
devicetree/bindings/net/stm32-dwmac.example.dtb: ethernet@5800a000: 
st,syscon:0: [4294967295, 4] is too short

    For MP13: st,syscon = <&syscfg 0x4 0xff0000 0xff>; => 
devicetree/bindings/net/stm32-dwmac.example.dtb: ethernet@5800a000: 
st,syscon:0: [4294967295, 4, 16711680, 255] is too long

So it is seems good :-)

>

Re: [PATCH v4 10/11] ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board

[Marek Vasut]

On 6/5/24 8:00 AM, Christophe ROULLIER wrote:
> 
> On 6/4/24 18:52, Marek Vasut wrote:
>> On 6/4/24 4:35 PM, Christophe Roullier wrote:
>>> Ethernet1: RMII with crystal
>>> PHY used is SMSC (LAN8742A)
>>
>> Doesn't the STM32MP135F-DK come with two ethernet ports ?
>> Why not enable both ?
> 
> Hi Marek,
> 
> As already discussed in V2, second ethernet have no cristal and need 
> "phy-supply" property to work, today this property is managed by 
> Ethernet glue, but
> 
> should be present and managed in PHY node (as explained by Rob). So I 
> will push second Ethernet in next step ;-)

Please add that ^ information into the commit message.

Re: [PATCH v4 01/11] dt-bindings: net: add STM32MP13 compatible in documentation for stm32

[Krzysztof Kozlowski]

On 05/06/2024 11:55, Christophe ROULLIER wrote:
> 
> On 6/5/24 10:14, Krzysztof Kozlowski wrote:
>> On 04/06/2024 16:34, Christophe Roullier wrote:
>>> New STM32 SOC have 2 GMACs instances.
>>> GMAC IP version is SNPS 4.20.
>>>
>>> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
>>> ---
>>>   .../devicetree/bindings/net/stm32-dwmac.yaml  | 41 +++++++++++++++----
>>>   1 file changed, 34 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
>>> index 7ccf75676b6d5..ecbed9a7aaf6d 100644
>>> --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
>>> +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
>>> @@ -22,18 +22,17 @@ select:
>>>           enum:
>>>             - st,stm32-dwmac
>>>             - st,stm32mp1-dwmac
>>> +          - st,stm32mp13-dwmac
>>>     required:
>>>       - compatible
>>>   
>>> -allOf:
>>> -  - $ref: snps,dwmac.yaml#
>>> -
>>>   properties:
>>>     compatible:
>>>       oneOf:
>>>         - items:
>>>             - enum:
>>>                 - st,stm32mp1-dwmac
>>> +              - st,stm32mp13-dwmac
>>>             - const: snps,dwmac-4.20a
>>>         - items:
>>>             - enum:
>>> @@ -75,12 +74,15 @@ properties:
>>>     st,syscon:
>>>       $ref: /schemas/types.yaml#/definitions/phandle-array
>>>       items:
>>> -      - items:
>>> +      - minItems: 2
>>> +        items:
>>>             - description: phandle to the syscon node which encompases the glue register
>>>             - description: offset of the control register
>>> +          - description: field to set mask in register
>>>       description:
>>>         Should be phandle/offset pair. The phandle to the syscon node which
>>> -      encompases the glue register, and the offset of the control register
>>> +      encompases the glue register, the offset of the control register and
>>> +      the mask to set bitfield in control register
>>>   
>>>     st,ext-phyclk:
>>>       description:
>>> @@ -112,12 +114,37 @@ required:
>>>   
>>>   unevaluatedProperties: false
>>>   
>>> +allOf:
>>> +  - $ref: snps,dwmac.yaml#
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            enum:
>>> +              - st,stm32mp1-dwmac
>>> +              - st,stm32-dwmac
>>> +    then:
>>> +      properties:
>>> +        st,syscon:
>>> +          items:
>>> +            maxItems: 2
>>> +
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            enum:
>>> +              - st,stm32mp13-dwmac
>>> +    then:
>>> +      properties:
>>> +        st,syscon:
>>> +          items:
>>> +            minItems: 3
>> I don't think this works. You now constrain the first dimension which
>> had only one item before.
>>
>> Make your example complete and test it.
>>
>> Best regards,
>> Krzysztof
> 
> Hi Krzysztof,
> 
> "Official" bindings for MP15: st,syscon = <&syscfg 0x4>;
> "Official" bindings for MP13: st,syscon = <&syscfg 0x4 0xff0000>; or 
> st,syscon = <&syscfg 0x4 0xff000000>;
> 
> If I execute make dt_binding_check 
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/stm32-dwmac.yaml with:
> 
>     For MP15: st,syscon = <&syscfg>; 
> =>bindings/net/stm32-dwmac.example.dtb: ethernet@40027000: st,syscon:0: 
> [4294967295] is too short
> 
>     For MP15: st,syscon = <&syscfg 0x4 0xff0000>; 
> =>devicetree/bindings/net/stm32-dwmac.example.dtb: ethernet@40027000: 
> st,syscon:0: [4294967295, 4, 16711680] is too long
> 
>     For MP13: st,syscon = <&syscfg 0x4>; => 
> devicetree/bindings/net/stm32-dwmac.example.dtb: ethernet@5800a000: 
> st,syscon:0: [4294967295, 4] is too short
> 
>     For MP13: st,syscon = <&syscfg 0x4 0xff0000 0xff>; => 
> devicetree/bindings/net/stm32-dwmac.example.dtb: ethernet@5800a000: 
> st,syscon:0: [4294967295, 4, 16711680, 255] is too long
> 
> So it is seems good :-)

Code is still incorrect, although will work because of how schema parses
matrix. But even by looking it is not symmetrical between allOf:if:then
and properties:. Make it symmetric - apply the number of items on the
second dimension.

Best regards,
Krzysztof

net: ethernet: stmmac: add management of stm32mp13 for stm32

[Amit Singh Tomar]

> Add Ethernet support for STM32MP13.
> STM32MP13 is STM32 SOC with 2 GMACs instances.
> GMAC IP version is SNPS 4.20.
> GMAC IP configure with 1 RX and 1 TX queue.
> DMA HW capability register supported
> RX Checksum Offload Engine supported
> TX Checksum insertion supported
> Wake-Up On Lan supported
> TSO supported
> 
> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
> ---
>   .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 50 +++++++++++++++----
>   1 file changed, 40 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> index bed2be129b2d2..e59f8a845e01e 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> @@ -84,12 +84,14 @@ struct stm32_dwmac {
>   	struct clk *clk_eth_ck;
>   	struct clk *clk_ethstp;
>   	struct clk *syscfg_clk;
> +	bool is_mp13;
>   	int ext_phyclk;
>   	int enable_eth_ck;
>   	int eth_clk_sel_reg;
>   	int eth_ref_clk_sel_reg;
>   	int irq_pwr_wakeup;
>   	u32 mode_reg;		 /* MAC glue-logic mode register */
> +	u32 mode_mask;
>   	struct regmap *regmap;
>   	u32 speed;
>   	const struct stm32_ops *ops;
> @@ -102,8 +104,8 @@ struct stm32_ops {
>   	void (*resume)(struct stm32_dwmac *dwmac);
>   	int (*parse_data)(struct stm32_dwmac *dwmac,
>   			  struct device *dev);
> -	u32 syscfg_eth_mask;
>   	bool clk_rx_enable_in_suspend;
> +	u32 syscfg_clr_off;
>   };
>   
>   static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac, bool resume)
> @@ -227,7 +229,14 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
>   
>   	switch (plat_dat->mac_interface) {
>   	case PHY_INTERFACE_MODE_MII:
> -		val = SYSCFG_PMCR_ETH_SEL_MII;
> +		/*
> +		 * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
> +		 * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
> +		 * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx
> +		 * supports only MII, ETH_SELMII is not present.
> +		 */
> +		if (!dwmac->is_mp13)	/* Select MII mode on STM32MP15xx */
> +			val |= SYSCFG_PMCR_ETH_SEL_MII;
>   		break;
>   	case PHY_INTERFACE_MODE_GMII:
>   		val = SYSCFG_PMCR_ETH_SEL_GMII;
> @@ -256,13 +265,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
>   
>   	dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
>   
> +	/* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
> +	val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);
> +
>   	/* Need to update PMCCLRR (clear register) */
> -	regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
> -		     dwmac->ops->syscfg_eth_mask);
> +	regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off,
> +		     dwmac->mode_mask);
>   
>   	/* Update PMCSETR (set register) */
>   	return regmap_update_bits(dwmac->regmap, reg,
> -				 dwmac->ops->syscfg_eth_mask, val);
> +				 dwmac->mode_mask, val);
>   }
>   
>   static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
> @@ -303,7 +315,7 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
>   	dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
>   
>   	return regmap_update_bits(dwmac->regmap, reg,
> -				 dwmac->ops->syscfg_eth_mask, val << 23);
> +				 SYSCFG_MCU_ETH_MASK, val << 23);
>   }
>   
>   static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac, bool suspend)
> @@ -348,8 +360,15 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
>   		return PTR_ERR(dwmac->regmap);
>   
>   	err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg);
> -	if (err)
> +	if (err) {
>   		dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err);

Shouldn't we decrement the refcount of np (‎of_node_put‎) before 
returning from this point?

> +		return err;
> +	}
> +
> +	dwmac->mode_mask = SYSCFG_MP1_ETH_MASK;
> +	err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask);
> +	if (err)
> +		pr_debug("Warning sysconfig register mask not set\n");
>   
>   	return err;
>   }
> @@ -361,6 +380,8 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
>   	struct device_node *np = dev->of_node;
>   	int err = 0;
>   
> +	dwmac->is_mp13 = of_device_is_compatible(np, "st,stm32mp13-dwmac");
> +
>   	/* Ethernet PHY have no crystal */
>   	dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
>   
> @@ -540,8 +561,7 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
>   	stm32_dwmac_suspend, stm32_dwmac_resume);
>   
>   static struct stm32_ops stm32mcu_dwmac_data = {
> -	.set_mode = stm32mcu_set_mode,
> -	.syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
> +	.set_mode = stm32mcu_set_mode
>   };
>   
>   static struct stm32_ops stm32mp1_dwmac_data = {
> @@ -549,13 +569,23 @@ static struct stm32_ops stm32mp1_dwmac_data = {
>   	.suspend = stm32mp1_suspend,
>   	.resume = stm32mp1_resume,
>   	.parse_data = stm32mp1_parse_data,
> -	.syscfg_eth_mask = SYSCFG_MP1_ETH_MASK,
> +	.syscfg_clr_off = 0x44,
> +	.clk_rx_enable_in_suspend = true
> +};
> +
> +static struct stm32_ops stm32mp13_dwmac_data = {
> +	.set_mode = stm32mp1_set_mode,
> +	.suspend = stm32mp1_suspend,
> +	.resume = stm32mp1_resume,
> +	.parse_data = stm32mp1_parse_data,
> +	.syscfg_clr_off = 0x08,
>   	.clk_rx_enable_in_suspend = true
>   };
>   
>   static const struct of_device_id stm32_dwmac_match[] = {
>   	{ .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
>   	{ .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},
> +	{ .compatible = "st,stm32mp13-dwmac", .data = &stm32mp13_dwmac_data},
>   	{ }
>   };
>   MODULE_DEVICE_TABLE(of, stm32_dwmac_match);

Re: [PATCH v4 01/11] dt-bindings: net: add STM32MP13 compatible in documentation for stm32

[Rob Herring]

On Wed, Jun 05, 2024 at 01:46:33PM +0200, Krzysztof Kozlowski wrote:
> On 05/06/2024 11:55, Christophe ROULLIER wrote:
> > 
> > On 6/5/24 10:14, Krzysztof Kozlowski wrote:
> >> On 04/06/2024 16:34, Christophe Roullier wrote:
> >>> New STM32 SOC have 2 GMACs instances.
> >>> GMAC IP version is SNPS 4.20.
> >>>
> >>> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
> >>> ---
> >>>   .../devicetree/bindings/net/stm32-dwmac.yaml  | 41 +++++++++++++++----
> >>>   1 file changed, 34 insertions(+), 7 deletions(-)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
> >>> index 7ccf75676b6d5..ecbed9a7aaf6d 100644
> >>> --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
> >>> +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
> >>> @@ -22,18 +22,17 @@ select:
> >>>           enum:
> >>>             - st,stm32-dwmac
> >>>             - st,stm32mp1-dwmac
> >>> +          - st,stm32mp13-dwmac
> >>>     required:
> >>>       - compatible
> >>>   
> >>> -allOf:
> >>> -  - $ref: snps,dwmac.yaml#
> >>> -
> >>>   properties:
> >>>     compatible:
> >>>       oneOf:
> >>>         - items:
> >>>             - enum:
> >>>                 - st,stm32mp1-dwmac
> >>> +              - st,stm32mp13-dwmac
> >>>             - const: snps,dwmac-4.20a
> >>>         - items:
> >>>             - enum:
> >>> @@ -75,12 +74,15 @@ properties:
> >>>     st,syscon:
> >>>       $ref: /schemas/types.yaml#/definitions/phandle-array
> >>>       items:
> >>> -      - items:
> >>> +      - minItems: 2
> >>> +        items:
> >>>             - description: phandle to the syscon node which encompases the glue register
> >>>             - description: offset of the control register
> >>> +          - description: field to set mask in register
> >>>       description:
> >>>         Should be phandle/offset pair. The phandle to the syscon node which
> >>> -      encompases the glue register, and the offset of the control register
> >>> +      encompases the glue register, the offset of the control register and
> >>> +      the mask to set bitfield in control register
> >>>   
> >>>     st,ext-phyclk:
> >>>       description:
> >>> @@ -112,12 +114,37 @@ required:
> >>>   
> >>>   unevaluatedProperties: false
> >>>   
> >>> +allOf:
> >>> +  - $ref: snps,dwmac.yaml#
> >>> +  - if:
> >>> +      properties:
> >>> +        compatible:
> >>> +          contains:
> >>> +            enum:
> >>> +              - st,stm32mp1-dwmac
> >>> +              - st,stm32-dwmac
> >>> +    then:
> >>> +      properties:
> >>> +        st,syscon:
> >>> +          items:
> >>> +            maxItems: 2
> >>> +
> >>> +  - if:
> >>> +      properties:
> >>> +        compatible:
> >>> +          contains:
> >>> +            enum:
> >>> +              - st,stm32mp13-dwmac
> >>> +    then:
> >>> +      properties:
> >>> +        st,syscon:
> >>> +          items:
> >>> +            minItems: 3
> >> I don't think this works. You now constrain the first dimension which
> >> had only one item before.
> >>
> >> Make your example complete and test it.
> >>
> >> Best regards,
> >> Krzysztof
> > 
> > Hi Krzysztof,
> > 
> > "Official" bindings for MP15: st,syscon = <&syscfg 0x4>;
> > "Official" bindings for MP13: st,syscon = <&syscfg 0x4 0xff0000>; or 
> > st,syscon = <&syscfg 0x4 0xff000000>;
> > 
> > If I execute make dt_binding_check 
> > DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/stm32-dwmac.yaml with:
> > 
> >     For MP15: st,syscon = <&syscfg>; 
> > =>bindings/net/stm32-dwmac.example.dtb: ethernet@40027000: st,syscon:0: 
> > [4294967295] is too short
> > 
> >     For MP15: st,syscon = <&syscfg 0x4 0xff0000>; 
> > =>devicetree/bindings/net/stm32-dwmac.example.dtb: ethernet@40027000: 
> > st,syscon:0: [4294967295, 4, 16711680] is too long
> > 
> >     For MP13: st,syscon = <&syscfg 0x4>; => 
> > devicetree/bindings/net/stm32-dwmac.example.dtb: ethernet@5800a000: 
> > st,syscon:0: [4294967295, 4] is too short
> > 
> >     For MP13: st,syscon = <&syscfg 0x4 0xff0000 0xff>; => 
> > devicetree/bindings/net/stm32-dwmac.example.dtb: ethernet@5800a000: 
> > st,syscon:0: [4294967295, 4, 16711680, 255] is too long
> > 
> > So it is seems good :-)
> 
> Code is still incorrect, although will work because of how schema parses
> matrix. But even by looking it is not symmetrical between allOf:if:then
> and properties:. Make it symmetric - apply the number of items on the
> second dimension.

It looks correct to me. But it could also be like this:

st,syscon:
  items:
    - minItems: 3

Either way works. Is that what you are asking for? I'm just happy when 
folks can write a working schema.

Rob

Re: [PATCH v4 07/11] net: ethernet: stmmac: add management of stm32mp13 for stm32

[Christophe ROULLIER]

On 6/4/24 19:05, Marek Vasut wrote:
> On 6/4/24 4:34 PM, Christophe Roullier wrote:
>> Add Ethernet support for STM32MP13.
>> STM32MP13 is STM32 SOC with 2 GMACs instances.
>> GMAC IP version is SNPS 4.20.
>> GMAC IP configure with 1 RX and 1 TX queue.
>> DMA HW capability register supported
>> RX Checksum Offload Engine supported
>> TX Checksum insertion supported
>> Wake-Up On Lan supported
>> TSO supported
>>
>> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
>> ---
>>   .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 50 +++++++++++++++----
>>   1 file changed, 40 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c 
>> b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
>> index bed2be129b2d2..e59f8a845e01e 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
>> @@ -84,12 +84,14 @@ struct stm32_dwmac {
>>       struct clk *clk_eth_ck;
>>       struct clk *clk_ethstp;
>>       struct clk *syscfg_clk;
>> +    bool is_mp13;
>>       int ext_phyclk;
>>       int enable_eth_ck;
>>       int eth_clk_sel_reg;
>>       int eth_ref_clk_sel_reg;
>>       int irq_pwr_wakeup;
>>       u32 mode_reg;         /* MAC glue-logic mode register */
>> +    u32 mode_mask;
>>       struct regmap *regmap;
>>       u32 speed;
>>       const struct stm32_ops *ops;
>> @@ -102,8 +104,8 @@ struct stm32_ops {
>>       void (*resume)(struct stm32_dwmac *dwmac);
>>       int (*parse_data)(struct stm32_dwmac *dwmac,
>>                 struct device *dev);
>> -    u32 syscfg_eth_mask;
>>       bool clk_rx_enable_in_suspend;
>> +    u32 syscfg_clr_off;
>>   };
>>     static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac, bool 
>> resume)
>> @@ -227,7 +229,14 @@ static int stm32mp1_configure_pmcr(struct 
>> plat_stmmacenet_data *plat_dat)
>>         switch (plat_dat->mac_interface) {
>>       case PHY_INTERFACE_MODE_MII:
>> -        val = SYSCFG_PMCR_ETH_SEL_MII;
>> +        /*
>> +         * STM32MP15xx supports both MII and GMII, STM32MP13xx MII 
>> only.
>> +         * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
>> +         * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx
>> +         * supports only MII, ETH_SELMII is not present.
>> +         */
>> +        if (!dwmac->is_mp13)    /* Select MII mode on STM32MP15xx */
>> +            val |= SYSCFG_PMCR_ETH_SEL_MII;
>>           break;
>>       case PHY_INTERFACE_MODE_GMII:
>>           val = SYSCFG_PMCR_ETH_SEL_GMII;
>> @@ -256,13 +265,16 @@ static int stm32mp1_configure_pmcr(struct 
>> plat_stmmacenet_data *plat_dat)
>>         dev_dbg(dwmac->dev, "Mode %s", 
>> phy_modes(plat_dat->mac_interface));
>>   +    /* Shift value at correct ethernet MAC offset in 
>> SYSCFG_PMCSETR */
>> +    val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);
>> +
>>       /* Need to update PMCCLRR (clear register) */
>> -    regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
>> -             dwmac->ops->syscfg_eth_mask);
>> +    regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off,
>> +             dwmac->mode_mask);
>>         /* Update PMCSETR (set register) */
>>       return regmap_update_bits(dwmac->regmap, reg,
>> -                 dwmac->ops->syscfg_eth_mask, val);
>> +                 dwmac->mode_mask, val);
>>   }
>>     static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
>> @@ -303,7 +315,7 @@ static int stm32mcu_set_mode(struct 
>> plat_stmmacenet_data *plat_dat)
>>       dev_dbg(dwmac->dev, "Mode %s", 
>> phy_modes(plat_dat->mac_interface));
>>         return regmap_update_bits(dwmac->regmap, reg,
>> -                 dwmac->ops->syscfg_eth_mask, val << 23);
>> +                 SYSCFG_MCU_ETH_MASK, val << 23);
>>   }
>>     static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac, 
>> bool suspend)
>> @@ -348,8 +360,15 @@ static int stm32_dwmac_parse_data(struct 
>> stm32_dwmac *dwmac,
>>           return PTR_ERR(dwmac->regmap);
>>         err = of_property_read_u32_index(np, "st,syscon", 1, 
>> &dwmac->mode_reg);
>> -    if (err)
>> +    if (err) {
>>           dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err);
>> +        return err;
>> +    }
>> +
>> +    dwmac->mode_mask = SYSCFG_MP1_ETH_MASK;
>> +    err = of_property_read_u32_index(np, "st,syscon", 2, 
>> &dwmac->mode_mask);
>> +    if (err)
>> +        pr_debug("Warning sysconfig register mask not set\n");
>
> I _think_ you need to left-shift the mode mask by 8 for STM32MP13xx 
> second GMAC somewhere in here, right ?
>
The shift is performed in function stm32mp1_configure_pmcr:

     /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
     val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);

In case of MP13 Ethernet1 or MP15, shift equal 0

In case of MP13 Ethernet2 , shift equal 8  ;-)

>>       return err;
>>   }
>> @@ -361,6 +380,8 @@ static int stm32mp1_parse_data(struct stm32_dwmac 
>> *dwmac,
>>       struct device_node *np = dev->of_node;
>>       int err = 0;
>>   +    dwmac->is_mp13 = of_device_is_compatible(np, 
>> "st,stm32mp13-dwmac");
>
> You could make is_mp13 part of struct stm32_ops {} just like 
> syscfg_clr_off is part of struct stm32_ops {} .
ok
>
>>       /* Ethernet PHY have no crystal */
>>       dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
>>   @@ -540,8 +561,7 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
>>       stm32_dwmac_suspend, stm32_dwmac_resume);
>>     static struct stm32_ops stm32mcu_dwmac_data = {
>> -    .set_mode = stm32mcu_set_mode,
>> -    .syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
>> +    .set_mode = stm32mcu_set_mode
>
> It is not necessary to remove the trailing comma ','
ok
>
>>   };
>>     static struct stm32_ops stm32mp1_dwmac_data = {
>> @@ -549,13 +569,23 @@ static struct stm32_ops stm32mp1_dwmac_data = {
>>       .suspend = stm32mp1_suspend,
>>       .resume = stm32mp1_resume,
>>       .parse_data = stm32mp1_parse_data,
>> -    .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK,
>> +    .syscfg_clr_off = 0x44,
>> +    .clk_rx_enable_in_suspend = true
>> +};
>> +
>> +static struct stm32_ops stm32mp13_dwmac_data = {
>> +    .set_mode = stm32mp1_set_mode,
>> +    .suspend = stm32mp1_suspend,
>> +    .resume = stm32mp1_resume,
>> +    .parse_data = stm32mp1_parse_data,
>> +    .syscfg_clr_off = 0x08,
>>       .clk_rx_enable_in_suspend = true
>>   };
>>     static const struct of_device_id stm32_dwmac_match[] = {
>>       { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
>>       { .compatible = "st,stm32mp1-dwmac", .data = 
>> &stm32mp1_dwmac_data},
>> +    { .compatible = "st,stm32mp13-dwmac", .data = 
>> &stm32mp13_dwmac_data},
>>       { }
>>   };
>>   MODULE_DEVICE_TABLE(of, stm32_dwmac_match);
>
> This patch definitely looks MUCH better than what this series started 
> with, it is much easier to grasp the MP13 specific changes.
>
> You could possibly improve this further and split the 
> dwmac->ops->syscfg_eth_mask to dwmac->mode_mask conversion into 
> separate preparatory patch (as a 6.5/11 in context of this series), 
> and then add the few MP13 changes on top (as 7/11 patch).
ok

Re: [PATCH v4 07/11] net: ethernet: stmmac: add management of stm32mp13 for stm32

[Marek Vasut]

On 6/6/24 4:19 PM, Christophe ROULLIER wrote:

Hi,

>>> @@ -348,8 +360,15 @@ static int stm32_dwmac_parse_data(struct 
>>> stm32_dwmac *dwmac,
>>>           return PTR_ERR(dwmac->regmap);
>>>         err = of_property_read_u32_index(np, "st,syscon", 1, 
>>> &dwmac->mode_reg);
>>> -    if (err)
>>> +    if (err) {
>>>           dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err);
>>> +        return err;
>>> +    }
>>> +
>>> +    dwmac->mode_mask = SYSCFG_MP1_ETH_MASK;
>>> +    err = of_property_read_u32_index(np, "st,syscon", 2, 
>>> &dwmac->mode_mask);
>>> +    if (err)
>>> +        pr_debug("Warning sysconfig register mask not set\n");
>>
>> I _think_ you need to left-shift the mode mask by 8 for STM32MP13xx 
>> second GMAC somewhere in here, right ?
>>
> The shift is performed in function stm32mp1_configure_pmcr:
> 
>      /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
>      val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);
> 
> In case of MP13 Ethernet1 or MP15, shift equal 0
> 
> In case of MP13 Ethernet2 , shift equal 8  ;-)

Oh, good, thanks !

Re: [PATCH v4 08/11] ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13

[Christophe ROULLIER]

Hi

On 6/4/24 18:49, Marek Vasut wrote:
> On 6/4/24 4:34 PM, Christophe Roullier wrote:
>> Both instances ethernet based on GMAC SNPS IP on stm32mp13.
>> GMAC IP version is SNPS 4.20.
>>
>> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
>> ---
>>   arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++++++++++++++++++++++++++
>>   arch/arm/boot/dts/st/stm32mp133.dtsi | 31 +++++++++++++++++++++++
>>   2 files changed, 69 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi 
>> b/arch/arm/boot/dts/st/stm32mp131.dtsi
>> index 6704ceef284d3..9d05853ececf7 100644
>> --- a/arch/arm/boot/dts/st/stm32mp131.dtsi
>> +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
>> @@ -979,6 +979,12 @@ ts_cal1: calib@5c {
>>               ts_cal2: calib@5e {
>>                   reg = <0x5e 0x2>;
>>               };
>> +            ethernet_mac1_address: mac1@e4 {
>> +                reg = <0xe4 0x6>;
>> +            };
>> +            ethernet_mac2_address: mac2@ea {
>> +                reg = <0xea 0x6>;
>> +            };
>>           };
>>             etzpc: bus@5c007000 {
>> @@ -1505,6 +1511,38 @@ sdmmc2: mmc@58007000 {
>>                   status = "disabled";
>>               };
>>   +            ethernet1: ethernet@5800a000 {
>> +                compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
>> +                reg = <0x5800a000 0x2000>;
>> +                reg-names = "stmmaceth";
>> +                interrupts-extended = <&intc GIC_SPI 62 
>> IRQ_TYPE_LEVEL_HIGH>,
>> +                              <&exti 68 1>;
>> +                interrupt-names = "macirq", "eth_wake_irq";
>> +                clock-names = "stmmaceth",
>> +                          "mac-clk-tx",
>> +                          "mac-clk-rx",
>> +                          "ethstp",
>> +                          "eth-ck";
>> +                clocks = <&rcc ETH1MAC>,
>> +                     <&rcc ETH1TX>,
>> +                     <&rcc ETH1RX>,
>> +                     <&rcc ETH1STP>,
>> +                     <&rcc ETH1CK_K>;
>> +                st,syscon = <&syscfg 0x4 0xff0000>;
>> +                snps,mixed-burst;
>> +                snps,pbl = <2>;
>> +                snps,axi-config = <&stmmac_axi_config_1>;
>> +                snps,tso;
>> +                access-controllers = <&etzpc 48>;
>
> Please keep the list of properties sorted.
>
To be coherent with all other IP, I will keep "access-controllers" 
property just before "status" property.
>> +                status = "disabled";
>> +
>> +                stmmac_axi_config_1: stmmac-axi-config {
>> +                    snps,wr_osr_lmt = <0x7>;
>> +                    snps,rd_osr_lmt = <0x7>;
>> +                    snps,blen = <0 0 0 0 16 8 4>;
>
> Sort here too.
ok
>
>> +                };
>> +            };
>> +
>>               usbphyc: usbphyc@5a006000 {
>>                   #address-cells = <1>;
>>                   #size-cells = <0>;
>> diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi 
>> b/arch/arm/boot/dts/st/stm32mp133.dtsi
>> index 3e394c8e58b92..09c7da1a2eda8 100644
>> --- a/arch/arm/boot/dts/st/stm32mp133.dtsi
>> +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi
>> @@ -67,5 +67,36 @@ channel@18 {
>>                   label = "vrefint";
>>               };
>>           };
>> +
>> +        ethernet2: ethernet@5800e000 {
>> +            compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
>> +            reg = <0x5800e000 0x2000>;
>> +            reg-names = "stmmaceth";
>> +            interrupts-extended = <&intc GIC_SPI 97 
>> IRQ_TYPE_LEVEL_HIGH>;
>> +            interrupt-names = "macirq";
>> +            clock-names = "stmmaceth",
>> +                      "mac-clk-tx",
>> +                      "mac-clk-rx",
>> +                      "ethstp",
>> +                      "eth-ck";
>> +            clocks = <&rcc ETH2MAC>,
>> +                 <&rcc ETH2TX>,
>> +                 <&rcc ETH2RX>,
>> +                 <&rcc ETH2STP>,
>> +                 <&rcc ETH2CK_K>;
>> +            st,syscon = <&syscfg 0x4 0xff000000>;
>> +            snps,mixed-burst;
>> +            snps,pbl = <2>;
>> +            snps,axi-config = <&stmmac_axi_config_2>;
>> +            snps,tso;
>> +            access-controllers = <&etzpc 49>;
>
> Sort here too.
>
>> +            status = "disabled";
>> +
>> +            stmmac_axi_config_2: stmmac-axi-config {
>> +                snps,wr_osr_lmt = <0x7>;
>> +                snps,rd_osr_lmt = <0x7>;
>> +                snps,blen = <0 0 0 0 16 8 4>;
>
> Sort here too.
>
> [...]