From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 038BE1990D0; Fri, 7 Jun 2024 15:56:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717775820; cv=none; b=t0/C2ByX04vB/upcauDUXdFPGdBPH54IiST/wR/PjjyBZYR5XZ6oiUX+s+MG+zNnbEnBOf2HMMNh9VidxCeOhmNmK6WctpjGrP5QXD+BKi/cwxhBiLsyqbZ32TyCy3Hphepdi3Odg1BLT6POwjyMAAZA/2eCCRtCSaARmeYHQ44= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717775820; c=relaxed/simple; bh=AvfwU2peuip8Rxw2RQR7kZaaaxxe71BZQ8M6oVTESCo=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=U39M26V8kTx6kJ4I317YQm9/qerNkCTkqX/n9HHPW3ZANCWc7P/oqVHwbzS8BtzCSRUfkXMeC9m6/UNDyrla7Tmc0Pm3GZvg6UEm9dcf0W0ooBbaIn12QeXRU7nShZLTh5bFe/ZvzPmoZlluABqDYH7GSjjSvCgGZkJHpwMv7fo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=Huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=Huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Vwm4r0W1zz6D94q; Fri, 7 Jun 2024 23:55:40 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (unknown [7.191.163.240]) by mail.maildlp.com (Postfix) with ESMTPS id 2BF87140A70; Fri, 7 Jun 2024 23:56:54 +0800 (CST) Received: from localhost (10.202.227.76) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 7 Jun 2024 16:56:53 +0100 Date: Fri, 7 Jun 2024 16:56:51 +0100 From: Jonathan Cameron To: Wei Huang CC: , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH V2 1/9] PCI: Introduce PCIe TPH support framework Message-ID: <20240607165651.00006554@Huawei.com> In-Reply-To: <20240531213841.3246055-2-wei.huang2@amd.com> References: <20240531213841.3246055-1-wei.huang2@amd.com> <20240531213841.3246055-2-wei.huang2@amd.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml500004.china.huawei.com (7.191.163.9) To lhrpeml500005.china.huawei.com (7.191.163.240) On Fri, 31 May 2024 16:38:33 -0500 Wei Huang wrote: > This patch implements the framework for PCIe TPH support. It introduces > tph.c source file, along with CONFIG_PCIE_TPH, to Linux PCIe subsystem. > A new member, named tph_cap, is also introduced in pci_dev to cache TPH > capability offset. > > Co-developed-by: Eric Van Tassell > Signed-off-by: Eric Van Tassell > Signed-off-by: Wei Huang > Reviewed-by: Ajit Khaparde > Reviewed-by: Somnath Kotur > Reviewed-by: Andy Gospodarek One trivial comment inline. With that fixed. Reviewed-by: Jonathan Cameron > diff --git a/drivers/pci/pcie/tph.c b/drivers/pci/pcie/tph.c > new file mode 100644 > index 000000000000..5f0cc06b74bb > --- /dev/null > +++ b/drivers/pci/pcie/tph.c > @@ -0,0 +1,28 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * TPH (TLP Processing Hints) support > + * > + * Copyright (C) 2024 Advanced Micro Devices, Inc. > + * Eric Van Tassell > + * Wei Huang > + */ > + > +#define pr_fmt(fmt) "TPH: " fmt > +#define dev_fmt pr_fmt > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include Introduce headers as you first use them. That way we can more easily see if there are unused ones in this list. > + > +#include "../pci.h" > + > +void pcie_tph_init(struct pci_dev *dev) > +{ > + dev->tph_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_TPH); > +} > + > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > index 15168881ec94..1f1ae55a5f83 100644 > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c > @@ -2484,6 +2484,7 @@ static void pci_init_capabilities(struct pci_dev *dev) > pci_dpc_init(dev); /* Downstream Port Containment */ > pci_rcec_init(dev); /* Root Complex Event Collector */ > pci_doe_init(dev); /* Data Object Exchange */ > + pcie_tph_init(dev); /* TLP Processing Hints */ > > pcie_report_downtraining(dev); > pci_init_reset_methods(dev); > diff --git a/include/linux/pci.h b/include/linux/pci.h > index 5bece7fd11f8..d75a88ec5136 100644 > --- a/include/linux/pci.h > +++ b/include/linux/pci.h > @@ -530,6 +530,10 @@ struct pci_dev { > > /* These methods index pci_reset_fn_methods[] */ > u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ > + > +#ifdef CONFIG_PCIE_TPH > + u16 tph_cap; /* TPH capability offset */ > +#endif > }; > > static inline struct pci_dev *pci_physfn(struct pci_dev *dev)