* [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
@ 2024-06-13 8:21 ` Omer Shpigelman
2024-06-13 13:01 ` Przemek Kitszel
` (2 more replies)
2024-06-13 8:21 ` [PATCH 02/15] net: hbl_cn: memory manager component Omer Shpigelman
` (15 subsequent siblings)
16 siblings, 3 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:21 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
Add the hbl_cn driver which will serve both Ethernet and InfiniBand
drivers.
hbl_cn is the layer which is used by the satellite drivers for many shared
operations that are needed by both EN and IB subsystems like QPs, CQs etc.
The CN driver is initialized via auxiliary bus by the habanalabs driver.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
.../device_drivers/ethernet/index.rst | 1 +
.../device_drivers/ethernet/intel/hbl.rst | 82 +
MAINTAINERS | 11 +
drivers/net/ethernet/intel/Kconfig | 20 +
drivers/net/ethernet/intel/Makefile | 1 +
drivers/net/ethernet/intel/hbl_cn/Makefile | 9 +
.../net/ethernet/intel/hbl_cn/common/Makefile | 3 +
.../net/ethernet/intel/hbl_cn/common/hbl_cn.c | 5954 +++++++++++++++++
.../net/ethernet/intel/hbl_cn/common/hbl_cn.h | 1627 +++++
.../ethernet/intel/hbl_cn/common/hbl_cn_drv.c | 220 +
.../intel/hbl_cn/common/hbl_cn_memory.c | 40 +
.../ethernet/intel/hbl_cn/common/hbl_cn_phy.c | 33 +
.../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 13 +
include/linux/habanalabs/cpucp_if.h | 125 +-
include/linux/habanalabs/hl_boot_if.h | 9 +-
include/linux/net/intel/cn.h | 474 ++
include/linux/net/intel/cn_aux.h | 298 +
include/linux/net/intel/cni.h | 636 ++
18 files changed, 9545 insertions(+), 11 deletions(-)
create mode 100644 Documentation/networking/device_drivers/ethernet/intel/hbl.rst
create mode 100644 drivers/net/ethernet/intel/hbl_cn/Makefile
create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/Makefile
create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_drv.c
create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_memory.c
create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_phy.c
create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
create mode 100644 include/linux/net/intel/cn.h
create mode 100644 include/linux/net/intel/cn_aux.h
create mode 100644 include/linux/net/intel/cni.h
diff --git a/Documentation/networking/device_drivers/ethernet/index.rst b/Documentation/networking/device_drivers/ethernet/index.rst
index 6932d8c043c2..2fe975aae7b1 100644
--- a/Documentation/networking/device_drivers/ethernet/index.rst
+++ b/Documentation/networking/device_drivers/ethernet/index.rst
@@ -40,6 +40,7 @@ Contents:
intel/i40e
intel/iavf
intel/ice
+ intel/hbl
marvell/octeontx2
marvell/octeon_ep
marvell/octeon_ep_vf
diff --git a/Documentation/networking/device_drivers/ethernet/intel/hbl.rst b/Documentation/networking/device_drivers/ethernet/intel/hbl.rst
new file mode 100644
index 000000000000..ebf436d0da7c
--- /dev/null
+++ b/Documentation/networking/device_drivers/ethernet/intel/hbl.rst
@@ -0,0 +1,82 @@
+.. SPDX-License-Identifier: GPL-2.0
+======================================================================
+Linux kernel drivers for HabanaLabs (an Intel company) Network
+======================================================================
+
+Copyright 2020-2024 HabanaLabs, Ltd.
+Copyright(c) 2023-2024 Intel Corporation.
+
+Contents
+========
+
+- Overview
+- Identifying Your Adapter
+- Important Notes
+- Support
+- Trademarks
+
+Overview
+========
+
+These drivers enables the infrastructure for network functionality which is part
+of the GAUDI ASIC family of AI Accelerators.
+
+The network interfaces are mainly used for scaling the training of AI neural
+networks through ROCEv2 protocol.
+
+Driver's information can be obtained using lspci.
+
+For questions related to hardware requirements, refer to the documentation
+supplied with your HabanaLabs adapter. All hardware requirements listed apply to
+use with Linux.
+
+The included network drivers are Core Network, Ethernet and InfiniBand which are
+all based on the habanalabs driver which serves as the compute driver and the
+general platform.
+This is the drivers scheme:
+
++------------+ | +-----+ | +-------+
+| INFINIBAND | | | NET | | | ACCEL |
++------------+ | +-----+ | +-------+
+ | |
+ +----+ | +----+ +----+ | +------------+
+ | IB | | | EN <---| CN | | | HABANALABS |
+ +-^--+ | +----+ +---^+ | +------------+
+ | | | |
+ +-----------------------+ +--------------+
+
+The parent driver is at the arrow base and the son is at the arrow head.
+The CN driver is both a parent and a son driver.
+
+Identifying Your Adapter
+========================
+For information on how to identify your adapter, and for the latest Intel
+network drivers, refer to the Intel Support website:
+https://www.intel.com/support
+
+Important Notes
+===============
+
+hbl_cn main goal is to provide core functionalities that are shared between the
+Ethernet (hbl_en) and the InfiniBand (hbl) drivers.
+It contains all core logic that is needed to operate the satellite drivers while
+keeping them as minimal as possible. Only pure Ethernet/InfiniBand code should
+reside in the satellite drivers.
+This code structure ensures a single and common infrastructure layer for both
+functionalities which makes it easier to modify and maintain.
+
+Support
+=======
+For general information, go to the Intel support website at:
+https://www.intel.com/support/
+
+If an issue is identified with the released source code on a supported kernel
+with a supported adapter, email the specific information related to the issue
+to intel-wired-lan@lists.osuosl.org.
+
+Trademarks
+==========
+Intel is a trademark or registered trademark of Intel Corporation or its
+subsidiaries in the United States and/or other countries.
+
+* Other names and brands may be claimed as the property of others.
diff --git a/MAINTAINERS b/MAINTAINERS
index 8754ac2c259d..e948e33e990d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9604,6 +9604,17 @@ F: include/linux/habanalabs/
F: include/trace/events/habanalabs.h
F: include/uapi/drm/habanalabs_accel.h
+HABANALABS CORE NETWORK DRIVER
+M: Omer Shpigelman <oshpigelman@habana.ai>
+L: netdev@vger.kernel.org
+L: linux-rdma@vger.kernel.org
+S: Supported
+W: https://www.habana.ai
+F: Documentation/networking/device_drivers/ethernet/intel/hbl.rst
+F: drivers/net/ethernet/intel/hbl_cn/
+F: include/linux/habanalabs/
+F: include/linux/net/intel/cn*
+
HACKRF MEDIA DRIVER
L: linux-media@vger.kernel.org
S: Orphan
diff --git a/drivers/net/ethernet/intel/Kconfig b/drivers/net/ethernet/intel/Kconfig
index e0287fbd501d..0d1b8a2bae99 100644
--- a/drivers/net/ethernet/intel/Kconfig
+++ b/drivers/net/ethernet/intel/Kconfig
@@ -397,4 +397,24 @@ config IDPF
To compile this driver as a module, choose M here. The module
will be called idpf.
+config HABANA_CN
+ tristate "HabanaLabs (an Intel Company) Core Network driver"
+ depends on X86_64
+ depends on PCI
+ select AUXILIARY_BUS
+ default n
+ help
+ This driver enables the infrastructure for network functionality that
+ is part of the GAUDI ASIC family of AI Accelerators.
+ For more information on how to identify your adapter, go to the
+ Adapter & Driver ID Guide that can be located at:
+
+ <http://support.intel.com>
+
+ More specific information on configuring the driver is in
+ <file:Documentation/networking/device_drivers/ethernet/intel/hbl.rst>.
+
+ To compile this driver as a module, choose M here. The module
+ will be called habanalabs_cn.
+
endif # NET_VENDOR_INTEL
diff --git a/drivers/net/ethernet/intel/Makefile b/drivers/net/ethernet/intel/Makefile
index 04c844ef4964..10049a28e336 100644
--- a/drivers/net/ethernet/intel/Makefile
+++ b/drivers/net/ethernet/intel/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_IAVF) += iavf/
obj-$(CONFIG_FM10K) += fm10k/
obj-$(CONFIG_ICE) += ice/
obj-$(CONFIG_IDPF) += idpf/
+obj-$(CONFIG_HABANA_CN) += hbl_cn/
diff --git a/drivers/net/ethernet/intel/hbl_cn/Makefile b/drivers/net/ethernet/intel/hbl_cn/Makefile
new file mode 100644
index 000000000000..84ee2a6d7c3b
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Makefile for HabanaLabs (an Intel Company) core network driver
+#
+
+obj-$(CONFIG_HABANA_CN) := habanalabs_cn.o
+
+include $(src)/common/Makefile
+habanalabs_cn-y += $(HBL_CN_COMMON_FILES)
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/Makefile b/drivers/net/ethernet/intel/hbl_cn/common/Makefile
new file mode 100644
index 000000000000..c8cf092db786
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/common/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+HBL_CN_COMMON_FILES := common/hbl_cn_drv.o common/hbl_cn.o \
+ common/hbl_cn_phy.o common/hbl_cn_qp.o common/hbl_cn_memory.o
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
new file mode 100644
index 000000000000..946b11bfa61b
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
@@ -0,0 +1,5954 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "hbl_cn.h"
+
+#include <linux/file.h>
+#include <linux/module.h>
+#include <linux/overflow.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+
+#define NIC_MIN_WQS_PER_PORT 2
+
+#define NIC_SEQ_RESETS_TIMEOUT_MS 15000 /* 15 seconds */
+#define NIC_MAX_SEQ_RESETS 3
+
+#define HBL_CN_IPV4_PROTOCOL_UDP 17
+
+/* SOB mask is not expected to change across ASIC. Hence common defines. */
+#define NIC_SOB_INC_MASK 0x80000000
+#define NIC_SOB_VAL_MASK 0x7fff
+
+#define NIC_DUMP_QP_SZ SZ_4K
+
+#define HBL_AUX2NIC(aux_dev) \
+ ({ \
+ struct hbl_aux_dev *__aux_dev = (aux_dev); \
+ ((__aux_dev)->type == HBL_AUX_DEV_ETH) ? \
+ container_of(__aux_dev, struct hbl_cn_device, en_aux_dev) : \
+ container_of(__aux_dev, struct hbl_cn_device, ib_aux_dev); \
+ })
+
+#define RAND_STAT_CNT(cnt) \
+ do { \
+ u32 __cnt = get_random_u32(); \
+ (cnt) = __cnt; \
+ dev_info(hdev->dev, "port %d, %s: %u\n", port, #cnt, __cnt); \
+ } while (0)
+
+struct hbl_cn_stat hbl_cn_mac_fec_stats[] = {
+ {"correctable_errors", 0x2, 0x3},
+ {"uncorrectable_errors", 0x4, 0x5}
+};
+
+struct hbl_cn_stat hbl_cn_mac_stats_rx[] = {
+ {"Octets", 0x0},
+ {"OctetsReceivedOK", 0x4},
+ {"aAlignmentErrors", 0x8},
+ {"aPAUSEMACCtrlFramesReceived", 0xC},
+ {"aFrameTooLongErrors", 0x10},
+ {"aInRangeLengthErrors", 0x14},
+ {"aFramesReceivedOK", 0x18},
+ {"aFrameCheckSequenceErrors", 0x1C},
+ {"VLANReceivedOK", 0x20},
+ {"ifInErrors", 0x24},
+ {"ifInUcastPkts", 0x28},
+ {"ifInMulticastPkts", 0x2C},
+ {"ifInBroadcastPkts", 0x30},
+ {"DropEvents", 0x34},
+ {"Pkts", 0x38},
+ {"UndersizePkts", 0x3C},
+ {"Pkts64Octets", 0x40},
+ {"Pkts65to127Octets", 0x44},
+ {"Pkts128to255Octets", 0x48},
+ {"Pkts256to511Octets", 0x4C},
+ {"Pkts512to1023Octets", 0x50},
+ {"Pkts1024to1518Octets", 0x54},
+ {"Pkts1519toMaxOctets", 0x58},
+ {"OversizePkts", 0x5C},
+ {"Jabbers", 0x60},
+ {"Fragments", 0x64},
+ {"aCBFCPAUSERx0", 0x68},
+ {"aCBFCPAUSERx1", 0x6C},
+ {"aCBFCPAUSERx2", 0x70},
+ {"aCBFCPAUSERx3", 0x74},
+ {"aCBFCPAUSERx4", 0x78},
+ {"aCBFCPAUSERx5", 0x7C},
+ {"aCBFCPAUSERx6", 0x80},
+ {"aCBFCPAUSERx7", 0x84},
+ {"aMACControlFramesReceived", 0x88}
+};
+
+struct hbl_cn_stat hbl_cn_mac_stats_tx[] = {
+ {"Octets", 0x0},
+ {"OctetsTransmittedOK", 0x4},
+ {"aPAUSEMACCtrlFramesTransmitted", 0x8},
+ {"aFramesTransmittedOK", 0xC},
+ {"VLANTransmittedOK", 0x10},
+ {"ifOutErrors", 0x14},
+ {"ifOutUcastPkts", 0x18},
+ {"ifOutMulticastPkts", 0x1C},
+ {"ifOutBroadcastPkts", 0x20},
+ {"Pkts64Octets", 0x24},
+ {"Pkts65to127Octets", 0x28},
+ {"Pkts128to255Octets", 0x2C},
+ {"Pkts256to511Octets", 0x30},
+ {"Pkts512to1023Octets", 0x34},
+ {"Pkts1024to1518Octets", 0x38},
+ {"Pkts1519toMaxOctets", 0x3C},
+ {"aCBFCPAUSETx0", 0x40},
+ {"aCBFCPAUSETx1", 0x44},
+ {"aCBFCPAUSETx2", 0x48},
+ {"aCBFCPAUSETx3", 0x4C},
+ {"aCBFCPAUSETx4", 0x50},
+ {"aCBFCPAUSETx5", 0x54},
+ {"aCBFCPAUSETx6", 0x58},
+ {"aCBFCPAUSETx7", 0x5C},
+ {"aMACControlFramesTx", 0x60},
+ {"Pkts", 0x64}
+};
+
+static const char pcs_counters_str[][ETH_GSTRING_LEN] = {
+ {"pcs_local_faults"},
+ {"pcs_remote_faults"},
+ {"pcs_remote_fault_reconfig"},
+ {"pcs_link_restores"},
+ {"pcs_link_toggles"},
+};
+
+static size_t pcs_counters_str_len = ARRAY_SIZE(pcs_counters_str);
+size_t hbl_cn_mac_fec_stats_len = ARRAY_SIZE(hbl_cn_mac_fec_stats);
+size_t hbl_cn_mac_stats_rx_len = ARRAY_SIZE(hbl_cn_mac_stats_rx);
+size_t hbl_cn_mac_stats_tx_len = ARRAY_SIZE(hbl_cn_mac_stats_tx);
+
+static void qps_stop(struct hbl_cn_device *hdev);
+static void qp_destroy_work(struct work_struct *work);
+static int __user_wq_arr_unset(struct hbl_cn_ctx *ctx, struct hbl_cn_port *cn_port, u32 type);
+static void user_cq_destroy(struct kref *kref);
+static void set_app_params_clear(struct hbl_cn_device *hdev);
+static int hbl_cn_ib_cmd_ctrl(struct hbl_aux_dev *aux_dev, void *cn_ib_ctx, u32 op, void *input,
+ void *output);
+static int hbl_cn_ib_query_mem_handle(struct hbl_aux_dev *ib_aux_dev, u64 mem_handle,
+ struct hbl_ib_mem_info *info);
+
+static void hbl_cn_reset_stats_counters_port(struct hbl_cn_device *hdev, u32 port);
+static void hbl_cn_late_init(struct hbl_cn_device *hdev);
+static void hbl_cn_late_fini(struct hbl_cn_device *hdev);
+static int hbl_cn_sw_init(struct hbl_cn_device *hdev);
+static void hbl_cn_sw_fini(struct hbl_cn_device *hdev);
+static void hbl_cn_spmu_init(struct hbl_cn_port *cn_port, bool full);
+static int hbl_cn_cmd_port_check(struct hbl_cn_device *hdev, u32 port, u32 flags);
+static void hbl_cn_qps_stop(struct hbl_cn_port *cn_port);
+
+static int hbl_cn_request_irqs(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+
+ return asic_funcs->request_irqs(hdev);
+}
+
+static void hbl_cn_free_irqs(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+
+ asic_funcs->free_irqs(hdev);
+}
+
+static void hbl_cn_synchronize_irqs(struct hbl_aux_dev *cn_aux_dev)
+{
+ struct hbl_cn_device *hdev = cn_aux_dev->priv;
+ struct hbl_cn_asic_funcs *asic_funcs;
+
+ asic_funcs = hdev->asic_funcs;
+
+ asic_funcs->synchronize_irqs(hdev);
+}
+
+void hbl_cn_get_frac_info(u64 numerator, u64 denominator, u64 *integer, u64 *exp)
+{
+ u64 high_digit_n, high_digit_d, integer_tmp, exp_tmp;
+ u8 num_digits_n, num_digits_d;
+ int i;
+
+ num_digits_d = hbl_cn_get_num_of_digits(denominator);
+ high_digit_d = denominator;
+ for (i = 0; i < num_digits_d - 1; i++)
+ high_digit_d /= 10;
+
+ integer_tmp = 0;
+ exp_tmp = 0;
+
+ if (numerator) {
+ num_digits_n = hbl_cn_get_num_of_digits(numerator);
+ high_digit_n = numerator;
+ for (i = 0; i < num_digits_n - 1; i++)
+ high_digit_n /= 10;
+
+ exp_tmp = num_digits_d - num_digits_n;
+
+ if (high_digit_n < high_digit_d) {
+ high_digit_n *= 10;
+ exp_tmp++;
+ }
+
+ integer_tmp = div_u64(high_digit_n, high_digit_d);
+ }
+
+ *integer = integer_tmp;
+ *exp = exp_tmp;
+}
+
+int hbl_cn_read_spmu_counters(struct hbl_cn_port *cn_port, u64 out_data[], u32 *num_out_data)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_stat *ignore;
+ int rc;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ port_funcs->spmu_get_stats_info(cn_port, &ignore, num_out_data);
+
+ /* this function can be called from ethtool, get_statistics ioctl and FW status thread */
+ mutex_lock(&cn_port->cnt_lock);
+ rc = port_funcs->spmu_sample(cn_port, *num_out_data, out_data);
+ mutex_unlock(&cn_port->cnt_lock);
+
+ return rc;
+}
+
+static u32 hbl_cn_get_port_toggle_cnt(struct hbl_cn_port *cn_port)
+{
+ /* We should not count the first toggle, as it marks that port was brought up for
+ * the first time. In case port connection wasn't established, the counter should be 0.
+ */
+ return cn_port->port_toggle_cnt ? cn_port->port_toggle_cnt - 1 : 0;
+}
+
+static int __hbl_cn_get_cnts_num(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+
+ return pcs_counters_str_len +
+ hdev->asic_funcs->port_funcs->get_cnts_num(cn_port);
+}
+
+static void __hbl_cn_get_cnts_names(struct hbl_cn_port *cn_port, u8 *data, bool ext)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ int i, len;
+
+ len = ext ? HBL_IB_CNT_NAME_LEN : ETH_GSTRING_LEN;
+
+ for (i = 0; i < pcs_counters_str_len; i++)
+ memcpy(data + i * len, pcs_counters_str[i], ETH_GSTRING_LEN);
+ data += i * len;
+
+ hdev->asic_funcs->port_funcs->get_cnts_names(cn_port, data, ext);
+}
+
+static void __hbl_cn_get_cnts_values(struct hbl_cn_port *cn_port, u64 *data)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+
+ data[0] = cn_port->pcs_local_fault_cnt;
+ data[1] = cn_port->pcs_remote_fault_cnt;
+ data[2] = cn_port->pcs_remote_fault_reconfig_cnt;
+ data[3] = cn_port->pcs_link_restore_cnt;
+ data[4] = hbl_cn_get_port_toggle_cnt(cn_port);
+
+ data += pcs_counters_str_len;
+
+ hdev->asic_funcs->port_funcs->get_cnts_values(cn_port, data);
+}
+
+static int __hbl_cn_port_hw_init(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+
+ if (cn_port->disabled) {
+ dev_err(hdev->dev, "Port %u is disabled\n", cn_port->port);
+ return -EPERM;
+ }
+
+ hbl_cn_reset_stats_counters_port(hdev, cn_port->port);
+
+ return hdev->asic_funcs->port_funcs->port_hw_init(cn_port);
+}
+
+static void __hbl_cn_port_hw_fini(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_funcs *asic_funcs;
+
+ asic_funcs = hdev->asic_funcs;
+
+ /* in hard reset the QPs were stopped by hbl_cn_stop called from halt engines */
+ if (hdev->operational)
+ hbl_cn_qps_stop(cn_port);
+
+ asic_funcs->port_funcs->port_hw_fini(cn_port);
+}
+
+bool hbl_cn_comp_device_operational(struct hbl_cn_device *hdev)
+{
+ struct hbl_aux_dev *aux_dev = hdev->cn_aux_dev;
+ struct hbl_cn_aux_ops *aux_ops;
+
+ aux_ops = aux_dev->aux_ops;
+
+ return aux_ops->device_operational(aux_dev);
+}
+
+void hbl_cn_spmu_get_stats_info(struct hbl_cn_port *cn_port, struct hbl_cn_stat **stats,
+ u32 *n_stats)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+
+ hdev->asic_funcs->port_funcs->spmu_get_stats_info(cn_port, stats, n_stats);
+}
+
+int hbl_cn_reserve_dva_block(struct hbl_cn_ctx *ctx, u64 size, u64 *dva)
+{
+ struct hbl_cn_device *hdev = ctx->hdev;
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ return aux_ops->vm_reserve_dva_block(aux_dev, ctx->driver_vm_info.vm_handle, size, dva);
+}
+
+void hbl_cn_unreserve_dva_block(struct hbl_cn_ctx *ctx, u64 dva, u64 size)
+{
+ struct hbl_cn_device *hdev = ctx->hdev;
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ aux_ops->vm_unreserve_dva_block(aux_dev, ctx->driver_vm_info.vm_handle, dva, size);
+}
+
+int hbl_cn_get_hw_block_handle(struct hbl_cn_device *hdev, u64 address, u64 *handle)
+{
+ return hdev->asic_funcs->get_hw_block_handle(hdev, address, handle);
+}
+
+static int hbl_cn_get_hw_block_addr(struct hbl_cn_device *hdev, u64 handle, u64 *addr, u64 *size)
+{
+ return hdev->asic_funcs->get_hw_block_addr(hdev, handle, addr, size);
+}
+
+int hbl_cn_send_cpucp_packet(struct hbl_cn_device *hdev, u32 port, enum cpucp_packet_id pkt_id,
+ int val)
+{
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ return hdev->asic_funcs->port_funcs->send_cpucp_packet(cn_port, pkt_id, val);
+}
+
+static bool hbl_cn_device_operational(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+
+ return hdev->operational;
+}
+
+static void hbl_cn_hw_access_lock(struct hbl_aux_dev *aux_dev)
+ __acquires(&hdev->hw_access_lock)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+
+ mutex_lock(&hdev->hw_access_lock);
+}
+
+static void hbl_cn_hw_access_unlock(struct hbl_aux_dev *aux_dev)
+ __releases(&hdev->hw_access_lock)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+
+ mutex_unlock(&hdev->hw_access_lock);
+}
+
+static bool hbl_cn_is_eth_lpbk(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+
+ return hdev->eth_loopback;
+}
+
+static int hbl_cn_port_hw_init(struct hbl_aux_dev *aux_dev, u32 port)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ return __hbl_cn_port_hw_init(cn_port);
+}
+
+static void hbl_cn_port_hw_fini(struct hbl_aux_dev *aux_dev, u32 port)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ __hbl_cn_port_hw_fini(cn_port);
+}
+
+static int hbl_cn_phy_port_init(struct hbl_aux_dev *aux_dev, u32 port)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ return hdev->asic_funcs->port_funcs->phy_port_init(cn_port);
+}
+
+static void hbl_cn_phy_port_fini(struct hbl_aux_dev *aux_dev, u32 port)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ hdev->asic_funcs->port_funcs->phy_port_fini(cn_port);
+}
+
+static int hbl_cn_set_pfc(struct hbl_aux_dev *aux_dev, u32 port, bool enable)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ cn_port->pfc_enable = enable;
+
+ return hdev->asic_funcs->port_funcs->set_pfc(cn_port);
+}
+
+static int hbl_cn_get_cnts_num(struct hbl_aux_dev *aux_dev, u32 port)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ return __hbl_cn_get_cnts_num(cn_port);
+}
+
+static void hbl_cn_get_cnts_names(struct hbl_aux_dev *aux_dev, u32 port, u8 *data)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ __hbl_cn_get_cnts_names(cn_port, data, false);
+}
+
+static void hbl_cn_get_cnts_values(struct hbl_aux_dev *aux_dev, u32 port, u64 *data)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ __hbl_cn_get_cnts_values(cn_port, data);
+}
+
+static bool hbl_cn_get_mac_lpbk(struct hbl_aux_dev *aux_dev, u32 port)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ return cn_port->mac_loopback;
+}
+
+static int hbl_cn_set_mac_lpbk(struct hbl_aux_dev *aux_dev, u32 port, bool enable)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ if (atomic_read(&cn_port->num_of_allocated_qps)) {
+ dev_dbg(hdev->dev,
+ "There are active QPs under this port - Can't %s mac loopback\n",
+ enable ? "enable" : "disable");
+ return -EBUSY;
+ }
+
+ cn_port->mac_loopback = enable;
+
+ if (enable)
+ hdev->mac_loopback |= BIT(port);
+ else
+ hdev->mac_loopback &= ~BIT(port);
+
+ return 0;
+}
+
+static int hbl_cn_update_mtu(struct hbl_aux_dev *aux_dev, u32 port, u32 mtu)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_port *cn_port;
+ unsigned long qp_id = 0;
+ struct hbl_cn_qp *qp;
+ int rc = 0;
+
+ cn_port = &hdev->cn_ports[port];
+ port_funcs = hdev->asic_funcs->port_funcs;
+ mtu += HBL_EN_MAX_HEADERS_SZ;
+
+ port_funcs->cfg_lock(cn_port);
+ xa_for_each(&cn_port->qp_ids, qp_id, qp) {
+ if (qp->mtu_type == MTU_FROM_NETDEV && qp->mtu != mtu) {
+ rc = port_funcs->update_qp_mtu(cn_port, qp, mtu);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to update MTU, port: %d, qpn: %ld, %d\n",
+ port, qp_id, rc);
+ break;
+ }
+ }
+ }
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static int hbl_cn_qpc_write(struct hbl_aux_dev *aux_dev, u32 port, void *qpc,
+ struct qpc_mask *qpc_mask, u32 qpn, bool is_req)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_port *cn_port;
+ int rc;
+
+ cn_port = &hdev->cn_ports[port];
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ port_funcs->cfg_lock(cn_port);
+ rc = port_funcs->qpc_write(cn_port, qpc, qpc_mask, qpn, is_req);
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static void hbl_cn_ctrl_lock(struct hbl_aux_dev *aux_dev, u32 port)
+ __acquires(&cn_port->control_lock)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ mutex_lock(&cn_port->control_lock);
+}
+
+static void hbl_cn_ctrl_unlock(struct hbl_aux_dev *aux_dev, u32 port)
+ __releases(&cn_port->control_lock)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ mutex_unlock(&cn_port->control_lock);
+}
+
+static int hbl_cn_dispatcher_register_qp(struct hbl_aux_dev *aux_dev, u32 port, u32 asid, u32 qp_id)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ return hbl_cn_eq_dispatcher_register_qp(cn_port, asid, qp_id);
+}
+
+static int hbl_cn_dispatcher_unregister_qp(struct hbl_aux_dev *aux_dev, u32 port, u32 qp_id)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ return hbl_cn_eq_dispatcher_unregister_qp(cn_port, qp_id);
+}
+
+static u32 hbl_cn_get_speed(struct hbl_aux_dev *aux_dev, u32 port)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ return cn_port->speed;
+}
+
+static void hbl_cn_track_ext_port_reset(struct hbl_aux_dev *aux_dev, u32 port, u32 syndrome)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ hbl_cn_track_port_reset(cn_port, syndrome);
+}
+
+static void hbl_cn_port_toggle_count(struct hbl_aux_dev *aux_dev, u32 port)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ cn_port->port_toggle_cnt++;
+}
+
+/* Check for initialized hbl IB device. */
+bool hbl_cn_is_ibdev(struct hbl_cn_device *hdev)
+{
+ return !!hdev->ib_aux_dev.priv;
+}
+
+/* Check for opened hbl IB device. */
+static bool hbl_cn_is_ibdev_opened(struct hbl_cn_device *hdev)
+{
+ return hdev->ib_aux_dev.priv && hdev->ib_device_opened;
+}
+
+static int hbl_cn_ib_alloc_ucontext(struct hbl_aux_dev *ib_aux_dev, int user_fd, void **cn_ib_ctx)
+{
+ struct hbl_cn_comp_vm_info *user_vm_info, *driver_vm_info;
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(ib_aux_dev);
+ struct hbl_aux_dev *aux_dev = hdev->cn_aux_dev;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_cn_ctx *ctx;
+ int rc;
+
+ asic_funcs = hdev->asic_funcs;
+ aux_ops = aux_dev->aux_ops;
+
+ if (!hdev->multi_ctx_support && hdev->ctx) {
+ dev_err(hdev->dev, "There is already an active user context\n");
+ return -EBUSY;
+ }
+
+ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ ctx->hdev = hdev;
+ mutex_init(&ctx->lock);
+
+ user_vm_info = &ctx->user_vm_info;
+ driver_vm_info = &ctx->driver_vm_info;
+
+ rc = aux_ops->register_cn_user_context(aux_dev, user_fd, ctx, &ctx->comp_handle,
+ &user_vm_info->vm_handle);
+ if (rc) {
+ dev_dbg(hdev->dev, "Failed to register user context with FD %d\n", user_fd);
+ goto release_ctx;
+ }
+
+ if (user_vm_info->vm_handle != ctx->comp_handle) {
+ rc = aux_ops->get_vm_info(aux_dev, user_vm_info->vm_handle, &user_vm_info->vm_info);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to get user VM info for handle 0x%llx\n",
+ user_vm_info->vm_handle);
+ goto deregister_ctx;
+ }
+
+ if (user_vm_info->vm_info.mmu_mode == HBL_CN_MMU_MODE_NETWORK_TLB)
+ ctx->user_asid = user_vm_info->vm_info.net_tlb.pasid;
+ else
+ ctx->user_asid = user_vm_info->vm_info.ext_mmu.work_id;
+ } else {
+ /* No data transfer in this mode */
+ ctx->user_asid = -1;
+ }
+
+ rc = aux_ops->vm_create(aux_dev, ctx->comp_handle, 0, &driver_vm_info->vm_handle);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to create driver VM for vompute handle 0x%llx\n",
+ ctx->comp_handle);
+ goto deregister_ctx;
+ }
+
+ rc = aux_ops->get_vm_info(aux_dev, driver_vm_info->vm_handle, &driver_vm_info->vm_info);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to get driver VM info for handle 0x%llx\n",
+ driver_vm_info->vm_handle);
+ goto destroy_driver_vm;
+ }
+
+ if (driver_vm_info->vm_info.mmu_mode == HBL_CN_MMU_MODE_NETWORK_TLB)
+ ctx->asid = driver_vm_info->vm_info.net_tlb.pasid;
+ else
+ ctx->asid = driver_vm_info->vm_info.ext_mmu.work_id;
+
+ /* must be called before calling create_mem_ctx */
+ rc = asic_funcs->ctx_init(ctx);
+ if (rc) {
+ dev_err(hdev->dev, "failed to init user context with ASID %d\n", ctx->asid);
+ goto destroy_driver_vm;
+ }
+
+ if (ctx->user_asid != -1 && user_vm_info->vm_info.mmu_mode == HBL_CN_MMU_MODE_NETWORK_TLB) {
+ rc = asic_funcs->create_mem_ctx(ctx, user_vm_info->vm_info.net_tlb.pasid,
+ user_vm_info->vm_info.net_tlb.page_tbl_addr);
+ if (rc) {
+ dev_err(hdev->dev,
+ "failed to create HW memory context for user VM, FD %d\n", user_fd);
+ goto ctx_cleanup;
+ }
+ }
+
+ if (driver_vm_info->vm_info.mmu_mode == HBL_CN_MMU_MODE_NETWORK_TLB) {
+ rc = asic_funcs->create_mem_ctx(ctx, driver_vm_info->vm_info.net_tlb.pasid,
+ driver_vm_info->vm_info.net_tlb.page_tbl_addr);
+ if (rc) {
+ dev_err(hdev->dev,
+ "failed to create HW memory context for driver VM, FD %d\n",
+ user_fd);
+ goto user_vm_ctx_cleanup;
+ }
+ }
+
+ *cn_ib_ctx = ctx;
+ hdev->ib_device_opened = true;
+ hdev->ctx = ctx;
+
+ return 0;
+
+user_vm_ctx_cleanup:
+ if (ctx->user_asid != -1 && user_vm_info->vm_info.mmu_mode == HBL_CN_MMU_MODE_NETWORK_TLB)
+ asic_funcs->destroy_mem_ctx(ctx, user_vm_info->vm_info.net_tlb.pasid,
+ user_vm_info->vm_info.net_tlb.page_tbl_addr);
+ctx_cleanup:
+ asic_funcs->ctx_fini(ctx);
+destroy_driver_vm:
+ aux_ops->vm_destroy(aux_dev, driver_vm_info->vm_handle);
+deregister_ctx:
+ aux_ops->deregister_cn_user_context(aux_dev, user_vm_info->vm_handle);
+release_ctx:
+ mutex_destroy(&ctx->lock);
+ kfree(ctx);
+
+ return rc;
+}
+
+static void hbl_cn_ib_dealloc_ucontext(struct hbl_aux_dev *ib_aux_dev, void *cn_ib_ctx)
+{
+ struct hbl_cn_comp_vm_info *user_vm_info, *driver_vm_info;
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(ib_aux_dev);
+ struct hbl_aux_dev *aux_dev = hdev->cn_aux_dev;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct hbl_cn_ctx *ctx = cn_ib_ctx;
+ struct hbl_cn_aux_ops *aux_ops;
+
+ aux_ops = aux_dev->aux_ops;
+ asic_funcs = hdev->asic_funcs;
+ user_vm_info = &ctx->user_vm_info;
+ driver_vm_info = &ctx->driver_vm_info;
+
+ dev_dbg(hdev->dev, "IB context dealloc\n");
+
+ if (driver_vm_info->vm_info.mmu_mode == HBL_CN_MMU_MODE_NETWORK_TLB)
+ asic_funcs->destroy_mem_ctx(ctx, driver_vm_info->vm_info.net_tlb.pasid,
+ driver_vm_info->vm_info.net_tlb.page_tbl_addr);
+
+ if (ctx->user_asid != -1 && user_vm_info->vm_info.mmu_mode == HBL_CN_MMU_MODE_NETWORK_TLB)
+ asic_funcs->destroy_mem_ctx(ctx, user_vm_info->vm_info.net_tlb.pasid,
+ user_vm_info->vm_info.net_tlb.page_tbl_addr);
+
+ hbl_cn_ctx_resources_destroy(hdev, ctx);
+ hdev->asic_funcs->ctx_fini(ctx);
+
+ aux_ops->vm_destroy(aux_dev, driver_vm_info->vm_handle);
+ aux_ops->deregister_cn_user_context(aux_dev, user_vm_info->vm_handle);
+
+ hdev->ctx = NULL;
+ mutex_destroy(&ctx->lock);
+ kfree(ctx);
+
+ hdev->ib_device_opened = false;
+}
+
+static void hbl_cn_ib_query_port(struct hbl_aux_dev *aux_dev, u32 port,
+ struct hbl_ib_port_attr *port_attr)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct hbl_cn_port *cn_port;
+
+ asic_funcs = hdev->asic_funcs;
+ cn_port = &hdev->cn_ports[port];
+
+ port_attr->open = hbl_cn_is_port_open(cn_port);
+ port_attr->link_up = cn_port->pcs_link;
+ port_attr->speed = cn_port->speed;
+ port_attr->max_msg_sz = asic_funcs->get_max_msg_sz(hdev);
+ port_attr->num_lanes = hdev->lanes_per_port;
+ port_attr->max_mtu = SZ_8K;
+}
+
+static inline void parse_fw_ver(struct hbl_cn_device *hdev, char *str, u32 *maj, u16 *min, u16 *sub)
+{
+ char *ver = strstr(str, "fw-");
+ int ret;
+
+ if (!ver)
+ goto failure;
+
+ ret = sscanf(ver, "fw-%d.%hu.%hu", maj, min, sub);
+ if (ret < 3) {
+failure:
+ dev_dbg(hdev->dev, "Failed to read version string\n");
+ *maj = *min = *sub = 0;
+ }
+}
+
+static void hbl_cn_ib_query_device(struct hbl_aux_dev *aux_dev, struct hbl_ib_device_attr *dev_attr)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_properties *cn_props;
+ struct hbl_ib_aux_data *aux_data;
+ u16 minor, sub_ver;
+ u32 major;
+
+ aux_data = aux_dev->aux_data;
+ cn_props = &hdev->cn_props;
+
+ if (hdev->cpucp_fw) {
+ parse_fw_ver(hdev, hdev->fw_ver, &major, &minor, &sub_ver);
+ dev_attr->fw_ver = ((u64)major << 32) | ((u64)minor << 16) | sub_ver;
+ }
+
+ dev_attr->max_mr_size = aux_data->dram_size;
+
+ dev_attr->page_size_cap = PAGE_SIZE;
+
+ dev_attr->vendor_id = hdev->pdev->vendor;
+ dev_attr->vendor_part_id = hdev->pdev->device;
+ dev_attr->hw_ver = hdev->pdev->subsystem_device;
+
+ dev_attr->max_qp = cn_props->max_qps_num;
+
+ dev_attr->max_qp_wr = aux_data->max_num_of_wqes;
+ dev_attr->max_cqe = cn_props->user_cq_max_entries;
+
+ dev_attr->cqe_size = cn_props->cqe_size;
+ dev_attr->min_cq_entries = cn_props->user_cq_min_entries;
+}
+
+static void hbl_cn_ib_set_ip_addr_encap(struct hbl_aux_dev *aux_dev, u32 ip_addr, u32 port)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct hbl_cn_port *cn_port;
+ u32 encap_id;
+
+ asic_funcs = hdev->asic_funcs;
+ cn_port = &hdev->cn_ports[port];
+
+ asic_funcs->port_funcs->set_ip_addr_encap(cn_port, &encap_id, ip_addr);
+}
+
+static char *hbl_cn_ib_qp_syndrome_to_str(struct hbl_aux_dev *aux_dev, u32 syndrome)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_asic_funcs *asic_funcs;
+
+ asic_funcs = hdev->asic_funcs;
+
+ return asic_funcs->qp_syndrome_to_str(syndrome);
+}
+
+static int hbl_cn_ib_verify_qp_id(struct hbl_aux_dev *aux_dev, u32 qp_id, u32 port)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_port *cn_port;
+ struct hbl_cn_device *hdev;
+ struct hbl_cn_qp *qp;
+ int rc = 0;
+
+ hdev = HBL_AUX2NIC(aux_dev);
+ port_funcs = hdev->asic_funcs->port_funcs;
+ cn_port = &hdev->cn_ports[port];
+
+ port_funcs->cfg_lock(cn_port);
+ qp = xa_load(&cn_port->qp_ids, qp_id);
+
+ if (IS_ERR_OR_NULL(qp)) {
+ dev_dbg(hdev->dev, "Failed to find matching QP for handle %d, port %d\n", qp_id,
+ port);
+ rc = -EINVAL;
+ goto cfg_unlock;
+ }
+
+ /* sanity test the port IDs */
+ if (qp->port != port) {
+ dev_dbg(hdev->dev, "QP port %d does not match requested port %d\n", qp->port, port);
+ rc = -EINVAL;
+ goto cfg_unlock;
+ }
+
+cfg_unlock:
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static int hbl_cn_ib_dump_qp(struct hbl_aux_dev *aux_dev, struct hbl_ib_dump_qp_attr *attr,
+ char *buf, size_t size)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct hbl_cn_qp_info qp_info = {};
+ int rc;
+
+ asic_funcs = hdev->asic_funcs;
+
+ qp_info.port = attr->port;
+ qp_info.qpn = attr->qpn;
+ qp_info.req = attr->req;
+ qp_info.full_print = attr->full;
+ qp_info.force_read = attr->force;
+
+ rc = asic_funcs->qp_read(hdev, &qp_info, buf, size);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to read QP %u, port %u\n", attr->qpn, attr->port);
+ return rc;
+ }
+
+ return 0;
+}
+
+static int hbl_cn_en_aux_data_init(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+ struct hbl_en_aux_data *en_aux_data;
+ struct hbl_cn_properties *cn_props;
+ struct hbl_en_aux_ops *en_aux_ops;
+ struct hbl_aux_dev *en_aux_dev;
+ char **mac_addr;
+ int i;
+
+ en_aux_dev = &hdev->en_aux_dev;
+ en_aux_dev->type = HBL_AUX_DEV_ETH;
+ en_aux_data = en_aux_dev->aux_data;
+ en_aux_ops = en_aux_dev->aux_ops;
+ cn_props = &hdev->cn_props;
+
+ en_aux_data->pdev = hdev->pdev;
+ en_aux_data->dev = hdev->dev;
+ en_aux_data->ports_mask = hdev->ext_ports_mask;
+ en_aux_data->auto_neg_mask = hdev->auto_neg_mask;
+ en_aux_data->id = hdev->id;
+ en_aux_data->fw_ver = hdev->fw_ver;
+ en_aux_data->qsfp_eeprom = hdev->cpucp_info->qsfp_eeprom;
+ en_aux_data->pending_reset_long_timeout = hdev->pending_reset_long_timeout;
+ en_aux_data->max_frm_len = cn_props->max_frm_len;
+ en_aux_data->raw_elem_size = cn_props->raw_elem_size;
+ en_aux_data->max_raw_mtu = cn_props->max_raw_mtu;
+ en_aux_data->min_raw_mtu = cn_props->min_raw_mtu;
+ en_aux_data->max_num_of_ports = hdev->cn_props.max_num_of_ports;
+ en_aux_data->has_eq = hdev->has_eq;
+ en_aux_data->asic_type = hdev->asic_type;
+
+ mac_addr = kcalloc(hdev->cn_props.max_num_of_ports, sizeof(*mac_addr), GFP_KERNEL);
+ if (!mac_addr)
+ return -ENOMEM;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(en_aux_data->ports_mask & BIT(i)))
+ continue;
+
+ mac_addr[i] = hdev->cpucp_info->mac_addrs[i].mac_addr;
+ }
+
+ en_aux_data->mac_addr = mac_addr;
+
+ /* set en -> cn ops */
+ /* device functions */
+ en_aux_ops->device_operational = hbl_cn_device_operational;
+ en_aux_ops->hw_access_lock = hbl_cn_hw_access_lock;
+ en_aux_ops->hw_access_unlock = hbl_cn_hw_access_unlock;
+ en_aux_ops->is_eth_lpbk = hbl_cn_is_eth_lpbk;
+ /* port functions */
+ en_aux_ops->port_hw_init = hbl_cn_port_hw_init;
+ en_aux_ops->port_hw_fini = hbl_cn_port_hw_fini;
+ en_aux_ops->phy_init = hbl_cn_phy_port_init;
+ en_aux_ops->phy_fini = hbl_cn_phy_port_fini;
+ en_aux_ops->set_pfc = hbl_cn_set_pfc;
+ en_aux_ops->get_cnts_num = hbl_cn_get_cnts_num;
+ en_aux_ops->get_cnts_names = hbl_cn_get_cnts_names;
+ en_aux_ops->get_cnts_values = hbl_cn_get_cnts_values;
+ en_aux_ops->get_mac_lpbk = hbl_cn_get_mac_lpbk;
+ en_aux_ops->set_mac_lpbk = hbl_cn_set_mac_lpbk;
+ en_aux_ops->update_mtu = hbl_cn_update_mtu;
+ en_aux_ops->qpc_write = hbl_cn_qpc_write;
+ en_aux_ops->ctrl_lock = hbl_cn_ctrl_lock;
+ en_aux_ops->ctrl_unlock = hbl_cn_ctrl_unlock;
+ en_aux_ops->eq_dispatcher_register_qp = hbl_cn_dispatcher_register_qp;
+ en_aux_ops->eq_dispatcher_unregister_qp = hbl_cn_dispatcher_unregister_qp;
+ en_aux_ops->get_speed = hbl_cn_get_speed;
+ en_aux_ops->track_ext_port_reset = hbl_cn_track_ext_port_reset;
+ en_aux_ops->port_toggle_count = hbl_cn_port_toggle_count;
+
+ asic_funcs->set_en_data(hdev);
+
+ return 0;
+}
+
+static void hbl_cn_en_aux_data_fini(struct hbl_cn_device *hdev)
+{
+ struct hbl_aux_dev *aux_dev = &hdev->en_aux_dev;
+ struct hbl_en_aux_data *aux_data;
+
+ aux_data = aux_dev->aux_data;
+
+ kfree(aux_data->mac_addr);
+ aux_data->mac_addr = NULL;
+}
+
+static int hbl_cn_ib_aux_data_init(struct hbl_cn_device *hdev)
+{
+ struct hbl_ib_port_cnts_data *cnts_data;
+ struct hbl_ib_aux_data *ib_aux_data;
+ struct hbl_ib_aux_ops *ib_aux_ops;
+ struct hbl_aux_dev *ib_aux_dev;
+ struct hbl_cn_port *cn_port;
+ int rc, i;
+
+ ib_aux_dev = &hdev->ib_aux_dev;
+ ib_aux_dev->type = HBL_AUX_DEV_IB;
+ ib_aux_data = ib_aux_dev->aux_data;
+ ib_aux_ops = ib_aux_dev->aux_ops;
+
+ ib_aux_data->pdev = hdev->pdev;
+ ib_aux_data->dev = hdev->dev;
+ ib_aux_data->ports_mask = hdev->ports_mask;
+ ib_aux_data->ext_ports_mask = hdev->ext_ports_mask;
+ ib_aux_data->max_num_of_wqes = hdev->cn_props.max_hw_user_wqs_num;
+ ib_aux_data->max_num_of_ports = hdev->cn_props.max_num_of_ports;
+ ib_aux_data->pending_reset_long_timeout = hdev->pending_reset_long_timeout;
+ ib_aux_data->id = hdev->id;
+ ib_aux_data->dram_size = hdev->dram_size;
+ ib_aux_data->mixed_qp_wq_types = hdev->mixed_qp_wq_types;
+ ib_aux_data->umr_support = hdev->umr_support;
+ ib_aux_data->cc_support = hdev->cc_support;
+
+ ib_aux_data->cnts_data = kcalloc(hdev->cn_props.max_num_of_ports,
+ sizeof(*ib_aux_data->cnts_data), GFP_KERNEL);
+ if (!ib_aux_data->cnts_data)
+ return -ENOMEM;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(ib_aux_data->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+ cnts_data = &ib_aux_data->cnts_data[i];
+
+ cnts_data->num = __hbl_cn_get_cnts_num(cn_port);
+
+ cnts_data->names = kcalloc(cnts_data->num, HBL_IB_CNT_NAME_LEN, GFP_KERNEL);
+ if (!cnts_data->names) {
+ rc = -ENOMEM;
+ goto free_cnts_data;
+ }
+
+ __hbl_cn_get_cnts_names(cn_port, cnts_data->names, true);
+ }
+
+ /* set ib -> cn ops */
+ /* the following functions are used even if the IB verbs API is disabled */
+ ib_aux_ops->device_operational = hbl_cn_device_operational;
+ ib_aux_ops->hw_access_lock = hbl_cn_hw_access_lock;
+ ib_aux_ops->hw_access_unlock = hbl_cn_hw_access_unlock;
+ ib_aux_ops->alloc_ucontext = hbl_cn_ib_alloc_ucontext;
+ ib_aux_ops->dealloc_ucontext = hbl_cn_ib_dealloc_ucontext;
+ ib_aux_ops->query_port = hbl_cn_ib_query_port;
+ ib_aux_ops->query_device = hbl_cn_ib_query_device;
+ ib_aux_ops->set_ip_addr_encap = hbl_cn_ib_set_ip_addr_encap;
+ ib_aux_ops->qp_syndrome_to_str = hbl_cn_ib_qp_syndrome_to_str;
+ ib_aux_ops->verify_qp_id = hbl_cn_ib_verify_qp_id;
+ ib_aux_ops->get_cnts_values = hbl_cn_get_cnts_values;
+ ib_aux_ops->dump_qp = hbl_cn_ib_dump_qp;
+
+ /* these functions are used only if the IB verbs API is enabled */
+ ib_aux_ops->cmd_ctrl = hbl_cn_ib_cmd_ctrl;
+ ib_aux_ops->query_mem_handle = hbl_cn_ib_query_mem_handle;
+
+ return 0;
+
+free_cnts_data:
+ for (--i; i >= 0; i--) {
+ if (!(ib_aux_data->ports_mask & BIT(i)))
+ continue;
+
+ kfree(ib_aux_data->cnts_data[i].names);
+ }
+ kfree(ib_aux_data->cnts_data);
+
+ return rc;
+}
+
+static void hbl_cn_ib_aux_data_fini(struct hbl_cn_device *hdev)
+{
+ struct hbl_ib_aux_data *aux_data;
+ struct hbl_aux_dev *aux_dev;
+ int i;
+
+ aux_dev = &hdev->ib_aux_dev;
+ aux_data = aux_dev->aux_data;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(aux_data->ports_mask & BIT(i)))
+ continue;
+
+ kfree(aux_data->cnts_data[i].names);
+ }
+ kfree(aux_data->cnts_data);
+}
+
+static void eth_adev_release(struct device *dev)
+{
+ struct hbl_aux_dev *aux_dev = container_of(dev, struct hbl_aux_dev, adev.dev);
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+
+ hdev->is_eth_aux_dev_initialized = false;
+}
+
+static int hbl_cn_en_aux_drv_init(struct hbl_cn_device *hdev)
+{
+ struct hbl_aux_dev *aux_dev = &hdev->en_aux_dev;
+ struct auxiliary_device *adev;
+ int rc;
+
+ rc = hbl_cn_en_aux_data_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "eth aux data init failed\n");
+ return rc;
+ }
+
+ adev = &aux_dev->adev;
+ adev->id = hdev->id;
+ adev->name = "en";
+ adev->dev.parent = hdev->dev;
+ adev->dev.release = eth_adev_release;
+
+ rc = auxiliary_device_init(adev);
+ if (rc) {
+ dev_err(hdev->dev, "eth auxiliary_device_init failed\n");
+ goto aux_data_free;
+ }
+
+ rc = auxiliary_device_add(adev);
+ if (rc) {
+ dev_err(hdev->dev, "eth auxiliary_device_add failed\n");
+ goto uninit_adev;
+ }
+
+ hdev->is_eth_aux_dev_initialized = true;
+
+ return 0;
+
+uninit_adev:
+ auxiliary_device_uninit(adev);
+aux_data_free:
+ hbl_cn_en_aux_data_fini(hdev);
+
+ return rc;
+}
+
+static void hbl_cn_en_aux_drv_fini(struct hbl_cn_device *hdev)
+{
+ struct auxiliary_device *adev;
+
+ if (!hdev->is_eth_aux_dev_initialized)
+ return;
+
+ adev = &hdev->en_aux_dev.adev;
+
+ auxiliary_device_delete(adev);
+ auxiliary_device_uninit(adev);
+
+ hbl_cn_en_aux_data_fini(hdev);
+}
+
+static void ib_adev_release(struct device *dev)
+{
+ struct hbl_aux_dev *aux_dev = container_of(dev, struct hbl_aux_dev, adev.dev);
+ struct hbl_cn_device *hdev;
+
+ hdev = container_of(aux_dev, struct hbl_cn_device, ib_aux_dev);
+
+ hdev->is_ib_aux_dev_initialized = false;
+}
+
+static int hbl_cn_ib_aux_drv_init(struct hbl_cn_device *hdev)
+{
+ struct hbl_aux_dev *aux_dev = &hdev->ib_aux_dev;
+ struct auxiliary_device *adev;
+ int rc;
+
+ if (!hdev->ib_support)
+ return 0;
+
+ rc = hbl_cn_ib_aux_data_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "IB aux data init failed\n");
+ return rc;
+ }
+
+ adev = &aux_dev->adev;
+ adev->id = hdev->id;
+ adev->name = "ib";
+ adev->dev.parent = hdev->dev;
+ adev->dev.release = ib_adev_release;
+
+ rc = auxiliary_device_init(adev);
+ if (rc) {
+ dev_err(hdev->dev, "ib auxiliary_device_init failed\n");
+ goto aux_data_free;
+ }
+
+ rc = auxiliary_device_add(adev);
+ if (rc) {
+ dev_err(hdev->dev, "ib auxiliary_device_add failed\n");
+ goto uninit_adev;
+ }
+
+ hdev->is_ib_aux_dev_initialized = true;
+
+ return 0;
+
+uninit_adev:
+ auxiliary_device_uninit(adev);
+aux_data_free:
+ hbl_cn_ib_aux_data_fini(hdev);
+
+ return rc;
+}
+
+static void hbl_cn_ib_aux_drv_fini(struct hbl_cn_device *hdev)
+{
+ struct auxiliary_device *adev;
+
+ if (!hdev->ib_support || !hdev->is_ib_aux_dev_initialized)
+ return;
+
+ adev = &hdev->ib_aux_dev.adev;
+
+ auxiliary_device_delete(adev);
+ auxiliary_device_uninit(adev);
+
+ hbl_cn_ib_aux_data_fini(hdev);
+}
+
+void hbl_cn_internal_port_fini_locked(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_funcs *asic_funcs;
+
+ asic_funcs = hdev->asic_funcs;
+
+ if (!cn_port->port_open)
+ return;
+
+ cn_port->port_open = false;
+
+ /* verify that the port is marked as closed before continuing */
+ mb();
+
+ asic_funcs->port_funcs->phy_port_fini(cn_port);
+
+ __hbl_cn_port_hw_fini(cn_port);
+}
+
+static void hbl_cn_internal_ports_fini(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_port *cn_port;
+ int i;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)) || (hdev->ext_ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ mutex_lock(&cn_port->control_lock);
+
+ hbl_cn_internal_port_fini_locked(cn_port);
+
+ mutex_unlock(&cn_port->control_lock);
+ }
+}
+
+void hbl_cn_ports_cancel_status_work(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_port *cn_port;
+ int i;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ cancel_delayed_work_sync(&cn_port->fw_status_work);
+ }
+}
+
+int hbl_cn_internal_port_init_locked(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ u32 port = cn_port->port;
+ int rc;
+
+ asic_funcs = hdev->asic_funcs;
+
+ rc = __hbl_cn_port_hw_init(cn_port);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to configure the HW, port: %d, %d", port, rc);
+ return rc;
+ }
+
+ rc = asic_funcs->port_funcs->phy_port_init(cn_port);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to configure the HW, port: %d, %d", port, rc);
+ goto phy_fail;
+ }
+
+ cn_port->port_open = true;
+
+ return 0;
+
+phy_fail:
+ __hbl_cn_port_hw_fini(cn_port);
+
+ return rc;
+}
+
+static int hbl_cn_internal_ports_init(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_port *cn_port;
+ u32 port;
+ int rc, i;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)) || (hdev->ext_ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+ port = cn_port->port;
+
+ mutex_lock(&cn_port->control_lock);
+
+ rc = hbl_cn_internal_port_init_locked(cn_port);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to configure the HW, port: %d, %d", port, rc);
+ mutex_unlock(&cn_port->control_lock);
+ goto port_init_fail;
+ }
+
+ mutex_unlock(&cn_port->control_lock);
+ }
+
+ return 0;
+
+port_init_fail:
+ hbl_cn_internal_ports_fini(hdev);
+
+ return rc;
+}
+
+static int hbl_cn_kernel_ctx_init(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+
+ return asic_funcs->kernel_ctx_init(hdev, hdev->kernel_asid);
+}
+
+static void hbl_cn_kernel_ctx_fini(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+
+ asic_funcs->kernel_ctx_fini(hdev, hdev->kernel_asid);
+}
+
+static void hbl_cn_mac_loopback_init(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port = cn_port->port;
+ bool enable;
+
+ aux_dev = &hdev->en_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ enable = !!(hdev->mac_loopback & BIT(port));
+ cn_port->mac_loopback = enable;
+
+ if (cn_port->eth_enable && aux_ops->set_dev_lpbk)
+ aux_ops->set_dev_lpbk(aux_dev, port, enable);
+}
+
+static int hbl_cn_core_init(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+ struct hbl_cn_macro *cn_macro;
+ struct hbl_cn_port *cn_port;
+ int rc, i, port_cnt = 0;
+ u32 port;
+
+ /* RX packet drop config is not preserved across hard reset. */
+ hdev->rx_drop_percent = 0;
+
+ if (hdev->load_phy_fw) {
+ if (hdev->cn_props.is_phy_fw_binary) {
+ rc = hbl_cn_phy_has_binary_fw(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "F/W file was not found\n");
+ return rc;
+ }
+ }
+
+ rc = asic_funcs->phy_fw_load_all(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "F/W load for all failed\n");
+ return rc;
+ }
+ }
+
+ if (hdev->phy_config_fw)
+ dev_dbg(hdev->dev, "F/W CRC: 0x%x\n", asic_funcs->phy_get_crc(hdev));
+
+ for (i = 0; i < hdev->cn_props.num_of_macros; i++) {
+ hdev->cn_macros[i].phy_macro_needs_reset = true;
+ hdev->cn_macros[i].rec_link_sts = 0;
+ }
+
+ memset(hdev->phy_ber_info, 0,
+ hdev->cn_props.max_num_of_lanes * sizeof(struct hbl_cn_ber_info));
+
+ rc = asic_funcs->core_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "core init failed\n");
+ return rc;
+ }
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++, port_cnt++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+ cn_macro = cn_port->cn_macro;
+ port = cn_port->port;
+
+ /* In case this port got disabled, enable it back here */
+ cn_port->disabled = false;
+ /* Port toggle count should be reinitialized for each port upond hard reset only */
+ cn_port->port_toggle_cnt = 0;
+ cn_port->port_toggle_cnt_prev = 0;
+
+ /* Reset the macro PHY once on boot.
+ * This function resets all the 4 lanes in the PHY macro, therefore only one of the
+ * two ports of the macro should call it.
+ */
+ if (hdev->phy_config_fw && cn_macro->phy_macro_needs_reset) {
+ rc = asic_funcs->phy_reset_macro(cn_macro);
+ if (rc) {
+ dev_err(hdev->dev, "PHY reset macro failed for port %d\n", port);
+ goto err;
+ }
+
+ cn_macro->phy_macro_needs_reset = false;
+ }
+
+ hbl_cn_spmu_init(cn_port, false);
+
+ cn_port->auto_neg_enable = !!(hdev->auto_neg_mask & BIT(port));
+
+ if (!hdev->in_reset)
+ cn_port->eth_enable = !!(BIT(port) & hdev->ext_ports_mask);
+
+ /* This function must be called after setting cn_port->eth_enable */
+ hbl_cn_mac_loopback_init(cn_port);
+ }
+
+ return 0;
+
+err:
+ asic_funcs->core_fini(hdev);
+
+ return rc;
+}
+
+static void hbl_cn_core_fini(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+
+ asic_funcs->core_fini(hdev);
+}
+
+static void wq_arrays_pool_destroy(struct hbl_cn_device *hdev)
+{
+ if (!hdev->wq_arrays_pool_enable)
+ return;
+
+ gen_pool_destroy(hdev->wq_arrays_pool);
+}
+
+static int wq_arrays_pool_alloc(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_properties *cn_props;
+ int rc;
+
+ if (!hdev->wq_arrays_pool_enable)
+ return 0;
+
+ cn_props = &hdev->cn_props;
+
+ hdev->wq_arrays_pool = gen_pool_create(ilog2(hdev->cache_line_size), -1);
+ if (!hdev->wq_arrays_pool) {
+ dev_err(hdev->dev, "Failed to create a pool to manage WQ arrays on HBM\n");
+ rc = -ENOMEM;
+ goto gen_pool_create_fail;
+ }
+
+ gen_pool_set_algo(hdev->wq_arrays_pool, gen_pool_best_fit, NULL);
+
+ rc = gen_pool_add(hdev->wq_arrays_pool, cn_props->wq_base_addr, cn_props->wq_base_size,
+ -1);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to add memory to the WQ arrays pool\n");
+ goto gen_pool_add_fail;
+ }
+
+ return 0;
+
+gen_pool_add_fail:
+ gen_pool_destroy(hdev->wq_arrays_pool);
+gen_pool_create_fail:
+ return rc;
+}
+
+int __hbl_cn_ports_reopen(struct hbl_cn_device *hdev)
+{
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *en_aux_dev;
+ int rc;
+
+ en_aux_dev = &hdev->en_aux_dev;
+ aux_ops = en_aux_dev->aux_ops;
+
+ rc = hbl_cn_kernel_ctx_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init kernel context\n");
+ return rc;
+ }
+
+ rc = hbl_cn_core_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init core\n");
+ goto core_init_fail;
+ }
+
+ rc = hbl_cn_internal_ports_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init internal ports\n");
+ goto internal_ports_fail;
+ }
+
+ hdev->in_reset = false;
+ hdev->fw_reset = false;
+ hdev->operational = true;
+
+ if (aux_ops->ports_reopen) {
+ rc = aux_ops->ports_reopen(en_aux_dev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to reopen en ports\n");
+ goto en_ports_reopen_fail;
+ }
+ }
+
+ return 0;
+
+en_ports_reopen_fail:
+ hdev->operational = false;
+ hbl_cn_internal_ports_fini(hdev);
+internal_ports_fail:
+ hbl_cn_core_fini(hdev);
+core_init_fail:
+ hbl_cn_kernel_ctx_fini(hdev);
+
+ return rc;
+}
+
+void __hbl_cn_stop(struct hbl_cn_device *hdev)
+{
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *en_aux_dev;
+
+ en_aux_dev = &hdev->en_aux_dev;
+ aux_ops = en_aux_dev->aux_ops;
+
+ /* Cancelling all outstanding works for all ports should be done first when stopping */
+ hdev->asic_funcs->ports_cancel_status_work(hdev);
+
+ qps_stop(hdev);
+
+ if (aux_ops->ports_stop)
+ aux_ops->ports_stop(en_aux_dev);
+
+ hbl_cn_internal_ports_fini(hdev);
+ hbl_cn_core_fini(hdev);
+ hbl_cn_kernel_ctx_fini(hdev);
+}
+
+void __hbl_cn_hard_reset_prepare(struct hbl_cn_device *hdev, bool fw_reset, bool in_teardown)
+{
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *en_aux_dev;
+
+ en_aux_dev = &hdev->en_aux_dev;
+ aux_ops = en_aux_dev->aux_ops;
+
+ hdev->in_reset = true;
+ hdev->fw_reset = fw_reset;
+ hdev->in_teardown = in_teardown;
+ hdev->operational = false;
+
+ mutex_lock(&hdev->hw_access_lock);
+ mutex_unlock(&hdev->hw_access_lock);
+
+ if (aux_ops->ports_stop_prepare)
+ aux_ops->ports_stop_prepare(en_aux_dev);
+}
+
+void hbl_cn_hard_reset_prepare(struct hbl_aux_dev *cn_aux_dev, bool fw_reset, bool in_teardown)
+{
+ struct hbl_cn_device *hdev = cn_aux_dev->priv;
+
+ __hbl_cn_hard_reset_prepare(hdev, fw_reset, in_teardown);
+}
+
+int hbl_cn_send_port_cpucp_status(struct hbl_aux_dev *aux_dev, u32 port, u8 cmd, u8 period)
+{
+ struct hbl_cn_device *hdev = aux_dev->priv;
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ if (cmd > HBL_CN_STATUS_PERIODIC_STOP) {
+ dev_err(hdev->dev, "Received invalid CN status cmd (%d) from F/W, port %d", cmd,
+ port);
+ return -EINVAL;
+ }
+
+ hdev->status_cmd = cmd;
+ hdev->status_period = (cmd == HBL_CN_STATUS_PERIODIC_START) ? period : 0;
+
+ if (cmd == HBL_CN_STATUS_PERIODIC_STOP)
+ cancel_delayed_work_sync(&cn_port->fw_status_work);
+ else
+ queue_delayed_work(cn_port->wq, &cn_port->fw_status_work, 0);
+
+ return 0;
+}
+
+static void hbl_cn_get_cpucp_info(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ aux_ops->get_cpucp_info(aux_dev, hdev->cpucp_info);
+}
+
+static int hbl_cn_ports_reopen(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_cn_device *hdev = aux_dev->priv;
+ int rc;
+
+ /* update CPUCP info after device reset */
+ hbl_cn_get_cpucp_info(hdev);
+
+ rc = hbl_cn_request_irqs(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to request IRQs\n");
+ return rc;
+ }
+
+ rc = __hbl_cn_ports_reopen(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to reopen ports\n");
+ goto free_irqs;
+ }
+
+ return 0;
+
+free_irqs:
+ hbl_cn_free_irqs(hdev);
+
+ return rc;
+}
+
+static void hbl_cn_stop(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_cn_device *hdev = aux_dev->priv;
+
+ __hbl_cn_stop(hdev);
+
+ hbl_cn_synchronize_irqs(aux_dev);
+ hbl_cn_free_irqs(hdev);
+}
+
+static int hbl_cn_set_static_properties(struct hbl_cn_device *hdev)
+{
+ return hdev->asic_funcs->set_static_properties(hdev);
+}
+
+static int hbl_cn_set_dram_properties(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+
+ return asic_funcs->set_dram_properties(hdev);
+}
+
+static int hbl_cn_set_asic_funcs(struct hbl_cn_device *hdev)
+{
+ switch (hdev->asic_type) {
+ case HBL_ASIC_GAUDI2:
+ default:
+ dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int hbl_cn_dev_init(struct hbl_cn_device *hdev)
+{
+ int rc;
+
+ if (!hdev->ports_mask) {
+ dev_err(hdev->dev, "All ports are disabled\n");
+ return -EINVAL;
+ }
+
+ /* must be called first to init the ASIC funcs */
+ rc = hbl_cn_set_asic_funcs(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "failed to set ASIC aux ops\n");
+ return rc;
+ }
+
+ /* get CPUCP info before initializing the device */
+ hbl_cn_get_cpucp_info(hdev);
+
+ /* init static cn properties */
+ rc = hbl_cn_set_static_properties(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to set static properties\n");
+ return rc;
+ }
+
+ /* init DRAM cn properties */
+ rc = hbl_cn_set_dram_properties(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "failed to set DRAM properties\n");
+ return rc;
+ }
+
+ rc = hbl_cn_sw_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "SW init failed\n");
+ return rc;
+ }
+
+ rc = hbl_cn_request_irqs(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to request IRQs\n");
+ goto request_irqs_fail;
+ }
+
+ rc = hbl_cn_kernel_ctx_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init kernel context\n");
+ goto kernel_ctx_init_fail;
+ }
+
+ rc = hbl_cn_core_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init core\n");
+ goto core_init_fail;
+ }
+
+ rc = hbl_cn_internal_ports_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init internal ports\n");
+ goto internal_ports_init_fail;
+ }
+
+ rc = wq_arrays_pool_alloc(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init WQ arrays pool\n");
+ goto wq_arrays_pool_alloc_fail;
+ }
+
+ hbl_cn_mem_init(hdev);
+
+ hdev->operational = true;
+
+ rc = hbl_cn_en_aux_drv_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init Ethernet driver\n");
+ goto en_aux_drv_fail;
+ }
+
+ rc = hbl_cn_ib_aux_drv_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init IB driver\n");
+ goto ib_aux_drv_fail;
+ }
+
+ hbl_cn_late_init(hdev);
+
+ hdev->is_initialized = true;
+
+ return 0;
+
+ib_aux_drv_fail:
+ hbl_cn_en_aux_drv_fini(hdev);
+en_aux_drv_fail:
+ hdev->operational = false;
+ hbl_cn_mem_fini(hdev);
+ wq_arrays_pool_destroy(hdev);
+wq_arrays_pool_alloc_fail:
+ hbl_cn_internal_ports_fini(hdev);
+internal_ports_init_fail:
+ hbl_cn_core_fini(hdev);
+core_init_fail:
+ hbl_cn_kernel_ctx_fini(hdev);
+kernel_ctx_init_fail:
+ hbl_cn_free_irqs(hdev);
+request_irqs_fail:
+ hbl_cn_sw_fini(hdev);
+
+ return rc;
+}
+
+void hbl_cn_dev_fini(struct hbl_cn_device *hdev)
+{
+ if (!hdev->is_initialized)
+ return;
+
+ hdev->is_initialized = false;
+
+ if (hdev->hw_stop_during_teardown) {
+ hbl_cn_hard_reset_prepare(hdev->cn_aux_dev, false, true);
+ hbl_cn_stop(hdev->cn_aux_dev);
+ }
+
+ hbl_cn_late_fini(hdev);
+
+ hbl_cn_ib_aux_drv_fini(hdev);
+ /* must be called after MSI was disabled */
+ hbl_cn_en_aux_drv_fini(hdev);
+ hbl_cn_mem_fini(hdev);
+ wq_arrays_pool_destroy(hdev);
+ hbl_cn_sw_fini(hdev);
+}
+
+static int hbl_cn_cmd_port_check(struct hbl_cn_device *hdev, u32 port, u32 flags)
+{
+ bool check_open = flags & NIC_PORT_CHECK_OPEN,
+ check_enable = (flags & NIC_PORT_CHECK_ENABLE) || check_open,
+ print_on_err = flags & NIC_PORT_PRINT_ON_ERR;
+ struct hbl_cn_port *cn_port;
+
+ if (port >= hdev->cn_props.max_num_of_ports) {
+ if (print_on_err)
+ dev_dbg(hdev->dev, "Invalid port %d\n", port);
+ return -EINVAL;
+ }
+
+ if (check_enable && !(hdev->ports_mask & BIT(port))) {
+ if (print_on_err)
+ dev_dbg(hdev->dev, "Port %d is disabled\n", port);
+ return -ENODEV;
+ }
+
+ cn_port = &hdev->cn_ports[port];
+
+ if (check_open && !hbl_cn_is_port_open(cn_port)) {
+ if (print_on_err)
+ dev_dbg(hdev->dev, "Port %d is closed\n", port);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static void hbl_cn_get_qp_id_range(struct hbl_cn_port *cn_port, u32 *min_id, u32 *max_id)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_funcs *asic_funcs;
+
+ asic_funcs = hdev->asic_funcs;
+
+ asic_funcs->port_funcs->get_qp_id_range(cn_port, min_id, max_id);
+
+ /* Take the minimum between the max id supported by the port and the max id supported by
+ * the WQs number the user asked to allocate.
+ */
+ *max_id = min(cn_port->qp_idx_offset + cn_port->num_of_wqs - 1, *max_id);
+}
+
+static void hbl_cn_qp_do_release(struct hbl_cn_qp *qp)
+{
+ struct hbl_cn_qpc_drain_attr drain_attr = { .wait_for_idle = false, };
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_port *cn_port;
+
+ if (IS_ERR_OR_NULL(qp))
+ return;
+
+ cn_port = qp->cn_port;
+ port_funcs = cn_port->hdev->asic_funcs->port_funcs;
+
+ cancel_delayed_work(&qp->adaptive_tmr_reset);
+
+ port_funcs->qp_pre_destroy(qp);
+
+ /* QP was found before, hence use xa_store to replace the pointer but don't release index.
+ * xa_store should not fail in such scenario.
+ */
+ xa_store(&qp->cn_port->qp_ids, qp->qp_id, NULL, GFP_KERNEL);
+
+ /* drain the Req QP now in order to make sure that accesses to the WQ will not
+ * be performed from this point on.
+ * Waiting for the WQ to drain is performed in the reset work
+ */
+ hbl_cn_qp_modify(cn_port, qp, CN_QP_STATE_SQD, &drain_attr);
+
+ queue_work(cn_port->qp_wq, &qp->async_work);
+}
+
+static void qp_adaptive_tmr_reset(struct work_struct *work)
+{
+ struct hbl_cn_qp *qp = container_of(work, struct hbl_cn_qp, adaptive_tmr_reset.work);
+ struct hbl_cn_port *cn_port = qp->cn_port;
+ struct hbl_cn_device *hdev;
+
+ hdev = cn_port->hdev;
+
+ hdev->asic_funcs->port_funcs->adaptive_tmr_reset(qp);
+}
+
+static int alloc_qp(struct hbl_cn_device *hdev, struct hbl_cn_ctx *ctx,
+ struct hbl_cni_alloc_conn_in *in, struct hbl_cni_alloc_conn_out *out)
+{
+ struct hbl_cn_wq_array_properties *swq_arr_props, *rwq_arr_props;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_port *cn_port;
+ struct xa_limit id_limit;
+ u32 min_id, max_id, port;
+ struct hbl_cn_qp *qp;
+ int id, rc;
+
+ port = in->port;
+
+ rc = hbl_cn_cmd_port_check(hdev, port, NIC_PORT_CHECK_OPEN | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ qp = kzalloc(sizeof(*qp), GFP_KERNEL);
+ if (!qp)
+ return -ENOMEM;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ cn_port = &hdev->cn_ports[port];
+ qp->cn_port = cn_port;
+ qp->port = port;
+ qp->ctx = ctx;
+ qp->curr_state = CN_QP_STATE_RESET;
+ INIT_WORK(&qp->async_work, qp_destroy_work);
+ INIT_DELAYED_WORK(&qp->adaptive_tmr_reset, qp_adaptive_tmr_reset);
+
+ hbl_cn_get_qp_id_range(cn_port, &min_id, &max_id);
+
+ port_funcs->cfg_lock(cn_port);
+
+ if (!cn_port->set_app_params) {
+ dev_dbg(hdev->dev,
+ "Failed to allocate QP, set_app_params wasn't called yet, port %d\n", port);
+ rc = -EPERM;
+ goto error_exit;
+ }
+
+ swq_arr_props = &cn_port->wq_arr_props[HBL_CNI_USER_WQ_SEND];
+ rwq_arr_props = &cn_port->wq_arr_props[HBL_CNI_USER_WQ_RECV];
+
+ if (!swq_arr_props->enabled || !rwq_arr_props->enabled) {
+ dev_dbg(hdev->dev, "Failed to allocate QP as WQs are not configured, port %d\n",
+ port);
+ rc = -EPERM;
+ goto error_exit;
+ }
+
+ if (swq_arr_props->under_unset || rwq_arr_props->under_unset) {
+ dev_dbg(hdev->dev, "Failed to allocate QP as WQs are under unset, port %d\n", port);
+ rc = -EPERM;
+ goto error_exit;
+ }
+
+ id_limit = XA_LIMIT(min_id, max_id);
+ rc = xa_alloc(&cn_port->qp_ids, &id, qp, id_limit, GFP_KERNEL);
+ if (rc) {
+ dev_dbg(hdev->dev, "Failed allocate QP IDR entry, port %d", port);
+ goto error_exit;
+ }
+
+ qp->qp_id = id;
+
+ rc = port_funcs->register_qp(cn_port, id, ctx->asid);
+ if (rc) {
+ dev_dbg(hdev->dev, "Failed to register QP %d, port %d\n", id, port);
+ goto qp_register_error;
+ }
+
+ atomic_inc(&cn_port->num_of_allocated_qps);
+
+ port_funcs->cfg_unlock(cn_port);
+
+ out->conn_id = id;
+
+ return 0;
+
+qp_register_error:
+ xa_erase(&qp->cn_port->qp_ids, qp->qp_id);
+error_exit:
+ port_funcs->cfg_unlock(cn_port);
+ kfree(qp);
+ return rc;
+}
+
+u32 hbl_cn_get_wq_array_type(bool is_send)
+{
+ return is_send ? HBL_CNI_USER_WQ_SEND : HBL_CNI_USER_WQ_RECV;
+}
+
+static int alloc_and_map_wq(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp, u32 n_wq,
+ bool is_swq)
+{
+ u32 wq_arr_type, wqe_size, qp_idx_offset, wq_idx;
+ struct hbl_cn_wq_array_properties *wq_arr_props;
+ struct hbl_cn_mem_data mem_data = {};
+ struct hbl_cn_properties *cn_props;
+ struct hbl_cn_device *hdev;
+ struct hbl_cn_mem_buf *buf;
+ u64 wq_arr_size, wq_size;
+ int rc;
+
+ hdev = cn_port->hdev;
+ cn_props = &hdev->cn_props;
+ qp_idx_offset = cn_port->qp_idx_offset;
+ wq_idx = qp->qp_id - qp_idx_offset;
+
+ wq_arr_type = hbl_cn_get_wq_array_type(is_swq);
+ wq_arr_props = &cn_port->wq_arr_props[wq_arr_type];
+ wqe_size = is_swq ? cn_port->swqe_size : cn_props->rwqe_size;
+
+ if (wq_arr_props->dva_base) {
+ mem_data.mem_id = HBL_CN_DRV_MEM_HOST_VIRTUAL;
+ mem_data.size = PAGE_ALIGN(n_wq * wqe_size);
+
+ /* Get offset into device VA block pre-allocated for SWQ.
+ *
+ * Note: HW indexes into SWQ array using qp_id.
+ * In general, it's HW requirement to leave holes in a WQ array if corresponding QP
+ * indexes are allocated on another WQ array.
+ */
+ mem_data.device_va = wq_arr_props->dva_base + wq_arr_props->offset +
+ wq_arr_props->wq_size * wq_idx;
+
+ /* Check for out of range. */
+ if (mem_data.device_va + mem_data.size >
+ wq_arr_props->dva_base + wq_arr_props->dva_size) {
+ dev_dbg(hdev->dev,
+ "Out of range device VA. device_va 0x%llx, size 0x%llx\n",
+ mem_data.device_va, mem_data.size);
+ return -EINVAL;
+ }
+ } else {
+ /* DMA coherent allocate case. Memory for WQ array is already allocated in
+ * user_wq_arr_set(). Here we use the allocated base addresses and QP id to
+ * calculate the CPU & bus addresses of the WQ for current QP and return that
+ * handle to the user. User may mmap() this handle returned by set_req_qp_ctx()
+ * to write WQEs.
+ */
+ mem_data.mem_id = HBL_CN_DRV_MEM_HOST_MAP_ONLY;
+
+ buf = hbl_cn_mem_buf_get(hdev, wq_arr_props->handle);
+ if (!buf) {
+ dev_err(hdev->dev, "Failed to retrieve WQ arr handle for port %d\n",
+ cn_port->port);
+ return -EINVAL;
+ }
+
+ /* Actual size to allocate. Page aligned since we mmap to user. */
+ mem_data.size = PAGE_ALIGN(n_wq * wqe_size);
+ wq_size = wq_arr_props->wq_size;
+ wq_arr_size = buf->mappable_size;
+
+ /* Get offset into kernel buffer block pre-allocated for SWQ. */
+ mem_data.in.host_map_data.kernel_address = buf->kernel_address +
+ wq_arr_props->offset + wq_size * wq_idx;
+
+ mem_data.in.host_map_data.bus_address = buf->bus_address + wq_arr_props->offset +
+ wq_size * wq_idx;
+
+ /* Check for out of range. */
+ if ((u64)mem_data.in.host_map_data.kernel_address + mem_data.size >
+ (u64)buf->kernel_address + wq_arr_size) {
+ dev_dbg(hdev->dev,
+ "Out of range kernel addr. kernel addr 0x%p, size 0x%llx\n",
+ mem_data.in.host_map_data.kernel_address, mem_data.size);
+ return -EINVAL;
+ }
+ }
+
+ /* Allocate host vmalloc memory and map its physical pages to PMMU. */
+ rc = hbl_cn_mem_alloc(qp->ctx, &mem_data);
+ if (rc) {
+ dev_dbg(hdev->dev, "Failed to allocate %s. Port %d, QP %d\n",
+ is_swq ? "SWQ" : "RWQ", cn_port->port, qp->qp_id);
+ return rc;
+ }
+
+ /* Retrieve mmap handle. */
+ if (is_swq) {
+ qp->swq_handle = mem_data.handle;
+ qp->swq_size = mem_data.size;
+ } else {
+ qp->rwq_handle = mem_data.handle;
+ qp->rwq_size = mem_data.size;
+ }
+
+ return 0;
+}
+
+static int set_req_qp_ctx(struct hbl_cn_device *hdev, struct hbl_cni_req_conn_ctx_in *in,
+ struct hbl_cni_req_conn_ctx_out *out)
+{
+ struct hbl_cn_wq_array_properties *swq_arr_props, *rwq_arr_props;
+ struct hbl_cn_encap_xarray_pdata *encap_data;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ u32 wq_size, port, max_wq_size;
+ struct hbl_cn_port *cn_port;
+ struct hbl_cn_qp *qp;
+ int rc;
+
+ port = in->port;
+
+ rc = hbl_cn_cmd_port_check(hdev, port, NIC_PORT_CHECK_OPEN | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ asic_funcs = hdev->asic_funcs;
+ port_funcs = asic_funcs->port_funcs;
+ cn_port = &hdev->cn_ports[port];
+
+ if (in->timer_granularity > NIC_TMR_TIMEOUT_MAX_GRAN) {
+ dev_err(hdev->dev,
+ "timer granularity %d is not supported\n", in->timer_granularity);
+ return -EINVAL;
+ }
+
+ if (!in->timer_granularity && !hbl_cn_is_ibdev_opened(hdev))
+ in->timer_granularity = NIC_TMR_TIMEOUT_DEFAULT_GRAN;
+
+ port_funcs->cfg_lock(cn_port);
+ qp = xa_load(&cn_port->qp_ids, in->conn_id);
+
+ if (IS_ERR_OR_NULL(qp)) {
+ dev_dbg(hdev->dev, "Failed to find matching QP for handle %d, port %d\n",
+ in->conn_id, port);
+ rc = -EINVAL;
+ goto cfg_unlock;
+ }
+
+ /* sanity test the port IDs */
+ if (qp->port != port) {
+ dev_dbg(hdev->dev, "QP port %d does not match requested port %d\n", qp->port, port);
+ rc = -EINVAL;
+ goto cfg_unlock;
+ }
+
+ if (in->encap_en) {
+ encap_data = xa_load(&cn_port->encap_ids, in->encap_id);
+ if (!encap_data) {
+ dev_dbg_ratelimited(hdev->dev,
+ "Encapsulation ID %d not found, ignoring\n",
+ in->encap_id);
+ in->encap_en = 0;
+ in->encap_id = 0;
+ }
+ }
+
+ if (qp->is_req) {
+ dev_dbg(hdev->dev, "Port %d, QP %d - Requester QP is already set\n", port,
+ qp->qp_id);
+ rc = -EINVAL;
+ goto cfg_unlock;
+ }
+
+ wq_size = in->wq_size;
+
+ /* verify that size does not exceed wq_array size */
+ max_wq_size = cn_port->num_of_wq_entries;
+
+ if (wq_size > max_wq_size) {
+ dev_dbg(hdev->dev,
+ "Port %d, Requester QP %d - requested size (%d) > max size (%d)\n", port,
+ qp->qp_id, wq_size, max_wq_size);
+ rc = -EINVAL;
+ goto cfg_unlock;
+ }
+
+ swq_arr_props = &cn_port->wq_arr_props[HBL_CNI_USER_WQ_SEND];
+ rwq_arr_props = &cn_port->wq_arr_props[HBL_CNI_USER_WQ_RECV];
+
+ if (!swq_arr_props->on_device_mem) {
+ rc = alloc_and_map_wq(cn_port, qp, wq_size, true);
+ if (rc)
+ goto cfg_unlock;
+
+ out->swq_mem_handle = qp->swq_handle;
+ out->swq_mem_size = qp->swq_size;
+ }
+
+ if (!rwq_arr_props->on_device_mem) {
+ rc = alloc_and_map_wq(cn_port, qp, wq_size, false);
+ if (rc)
+ goto err_free_swq;
+
+ out->rwq_mem_handle = qp->rwq_handle;
+ out->rwq_mem_size = qp->rwq_size;
+ }
+
+ qp->remote_key = in->remote_key;
+
+ rc = hbl_cn_qp_modify(cn_port, qp, CN_QP_STATE_RTS, in);
+ if (rc)
+ goto err_free_rwq;
+
+ port_funcs->cfg_unlock(cn_port);
+
+ return 0;
+
+err_free_rwq:
+ if (qp->rwq_handle) {
+ hbl_cn_mem_destroy(hdev, qp->rwq_handle);
+ qp->rwq_handle = 0;
+ out->rwq_mem_handle = qp->rwq_handle;
+ if (!rwq_arr_props->dva_base) {
+ int ret;
+
+ ret = hbl_cn_mem_buf_put_handle(hdev, rwq_arr_props->handle);
+ if (ret == 1)
+ rwq_arr_props->handle = 0;
+ }
+ }
+err_free_swq:
+ if (qp->swq_handle) {
+ hbl_cn_mem_destroy(hdev, qp->swq_handle);
+ qp->swq_handle = 0;
+ out->swq_mem_handle = qp->swq_handle;
+ if (!swq_arr_props->dva_base) {
+ int ret;
+
+ ret = hbl_cn_mem_buf_put_handle(hdev, swq_arr_props->handle);
+ if (ret == 1)
+ swq_arr_props->handle = 0;
+ }
+ }
+cfg_unlock:
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static int set_res_qp_ctx(struct hbl_cn_device *hdev, struct hbl_cni_res_conn_ctx_in *in)
+{
+ struct hbl_cn_encap_xarray_pdata *encap_data;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct hbl_cn_port *cn_port;
+ struct hbl_cn_qp *qp;
+ u32 port;
+ int rc;
+
+ port = in->port;
+
+ rc = hbl_cn_cmd_port_check(hdev, port, NIC_PORT_CHECK_OPEN | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ asic_funcs = hdev->asic_funcs;
+ port_funcs = asic_funcs->port_funcs;
+ cn_port = &hdev->cn_ports[port];
+
+ port_funcs->cfg_lock(cn_port);
+ qp = xa_load(&cn_port->qp_ids, in->conn_id);
+
+ if (IS_ERR_OR_NULL(qp)) {
+ dev_dbg(hdev->dev, "Failed to find matching QP for handle %d, port %d\n",
+ in->conn_id, port);
+ rc = -EINVAL;
+ goto unlock_cfg;
+ }
+
+ if (in->encap_en) {
+ encap_data = xa_load(&cn_port->encap_ids, in->encap_id);
+ if (!encap_data) {
+ dev_dbg_ratelimited(hdev->dev,
+ "Encapsulation ID %d not found, ignoring\n",
+ in->encap_id);
+ in->encap_en = 0;
+ in->encap_id = 0;
+ }
+ }
+
+ if (qp->is_res) {
+ dev_dbg(hdev->dev, "Port %d, QP %d - Responder QP is already set\n", port,
+ qp->qp_id);
+ rc = -EINVAL;
+ goto unlock_cfg;
+ }
+
+ /* sanity test the port IDs */
+ if (qp->port != port) {
+ dev_dbg(hdev->dev, "QP port %d does not match requested port %d\n", qp->port, port);
+ rc = -EINVAL;
+ goto unlock_cfg;
+ }
+
+ qp->local_key = in->local_key;
+
+ if (qp->curr_state == CN_QP_STATE_RESET) {
+ rc = hbl_cn_qp_modify(cn_port, qp, CN_QP_STATE_INIT, NULL);
+ if (rc)
+ goto unlock_cfg;
+ }
+
+ /* all is well, we are ready to receive */
+ rc = hbl_cn_qp_modify(cn_port, qp, CN_QP_STATE_RTR, in);
+
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+
+unlock_cfg:
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+/* must be called under the port cfg lock */
+u32 hbl_cn_get_max_qp_id(struct hbl_cn_port *cn_port)
+{
+ int max_qp_id = cn_port->qp_idx_offset;
+ unsigned long qp_id = 0;
+ struct hbl_cn_qp *qp;
+
+ xa_for_each(&cn_port->qp_ids, qp_id, qp)
+ if (qp->qp_id > max_qp_id)
+ max_qp_id = qp->qp_id;
+
+ return max_qp_id;
+}
+
+static void qp_destroy_work(struct work_struct *work)
+{
+ struct hbl_cn_qp *qp = container_of(work, struct hbl_cn_qp, async_work);
+ struct hbl_cn_wq_array_properties *swq_arr_props, *rwq_arr_props;
+ struct hbl_cn_port *cn_port = qp->cn_port;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_qpc_drain_attr drain_attr;
+ struct hbl_cn_qpc_reset_attr rst_attr;
+ struct hbl_cn_ctx *ctx = qp->ctx;
+ struct hbl_cn_device *hdev;
+ int rc;
+
+ hdev = cn_port->hdev;
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ if (!hdev->operational) {
+ drain_attr.wait_for_idle = false;
+ rst_attr.reset_mode = hdev->qp_reset_mode;
+ } else {
+ drain_attr.wait_for_idle = true;
+ rst_attr.reset_mode = CN_QP_RESET_MODE_GRACEFUL;
+ }
+
+ /* Complete the wait for SQ to drain. To allow parallel QPs destruction, don't take the cfg
+ * lock here. This is safe because SQD->SQD QP transition is a simple wait to drain the QP
+ * without any access to the HW.
+ */
+ if (qp->curr_state == CN_QP_STATE_SQD)
+ hbl_cn_qp_modify(cn_port, qp, CN_QP_STATE_SQD, &drain_attr);
+
+ port_funcs->cfg_lock(cn_port);
+
+ hbl_cn_qp_modify(cn_port, qp, CN_QP_STATE_RESET, &rst_attr);
+
+ port_funcs->unregister_qp(cn_port, qp->qp_id);
+
+ swq_arr_props = &cn_port->wq_arr_props[HBL_CNI_USER_WQ_SEND];
+ rwq_arr_props = &cn_port->wq_arr_props[HBL_CNI_USER_WQ_RECV];
+
+ if (qp->swq_handle) {
+ hbl_cn_mem_destroy(hdev, qp->swq_handle);
+ qp->swq_handle = 0;
+ if (!swq_arr_props->dva_base) {
+ rc = hbl_cn_mem_buf_put_handle(hdev, swq_arr_props->handle);
+ if (rc == 1)
+ swq_arr_props->handle = 0;
+ }
+ }
+
+ if (qp->rwq_handle) {
+ hbl_cn_mem_destroy(hdev, qp->rwq_handle);
+ qp->rwq_handle = 0;
+ if (!rwq_arr_props->dva_base) {
+ rc = hbl_cn_mem_buf_put_handle(hdev, rwq_arr_props->handle);
+ if (rc == 1)
+ rwq_arr_props->handle = 0;
+ }
+ }
+
+ xa_erase(&cn_port->qp_ids, qp->qp_id);
+
+ if (atomic_dec_and_test(&cn_port->num_of_allocated_qps)) {
+ if (swq_arr_props->under_unset)
+ __user_wq_arr_unset(ctx, cn_port, HBL_CNI_USER_WQ_SEND);
+
+ if (rwq_arr_props->under_unset)
+ __user_wq_arr_unset(ctx, cn_port, HBL_CNI_USER_WQ_RECV);
+ }
+
+ if (qp->req_user_cq)
+ hbl_cn_user_cq_put(qp->req_user_cq);
+
+ if (qp->res_user_cq)
+ hbl_cn_user_cq_put(qp->res_user_cq);
+
+ port_funcs->qp_post_destroy(qp);
+
+ /* hbl_cn_mem_destroy should be included inside lock not due to protection.
+ * The handles (swq_handle and rwq_handle) are created based on QP id.
+ * Lock is to avoid concurrent memory access from a new handle created before freeing
+ * memory.
+ */
+ port_funcs->cfg_unlock(cn_port);
+
+ kfree(qp);
+}
+
+static void qps_drain_async_work(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_port *cn_port;
+ int i, num_gen_qps;
+
+ /* wait for the workers to complete */
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ drain_workqueue(cn_port->qp_wq);
+
+ num_gen_qps = atomic_read(&cn_port->num_of_allocated_qps);
+ if (num_gen_qps)
+ dev_warn(hdev->dev, "Port %d still has %d QPs alive\n", i, num_gen_qps);
+ }
+}
+
+static inline int __must_check PTR_ERR_OR_EINVAL(__force const void *ptr)
+{
+ if (IS_ERR(ptr))
+ return PTR_ERR(ptr);
+ else
+ return -EINVAL;
+}
+
+static int destroy_qp(struct hbl_cn_device *hdev, struct hbl_cni_destroy_conn_in *in)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct hbl_cn_port *cn_port;
+ struct hbl_cn_qp *qp;
+ u32 port, flags;
+ int rc;
+
+ port = in->port;
+
+ if (port >= hdev->cn_props.max_num_of_ports) {
+ dev_dbg(hdev->dev, "Invalid port %d\n", port);
+ return -EINVAL;
+ }
+
+ cn_port = &hdev->cn_ports[port];
+
+ /* in case of destroying QPs of external ports, the port may be already closed by a user
+ * issuing "ip link set down" command so we only check if the port is enabled in these
+ * ports.
+ */
+ flags = cn_port->eth_enable ? NIC_PORT_CHECK_ENABLE : NIC_PORT_CHECK_OPEN;
+ flags |= NIC_PORT_PRINT_ON_ERR;
+ rc = hbl_cn_cmd_port_check(hdev, port, flags);
+ if (rc)
+ return rc;
+
+ asic_funcs = hdev->asic_funcs;
+ port_funcs = asic_funcs->port_funcs;
+
+ /* prevent reentrancy by locking the whole process of destroy_qp */
+ port_funcs->cfg_lock(cn_port);
+ qp = xa_load(&cn_port->qp_ids, in->conn_id);
+
+ if (IS_ERR_OR_NULL(qp)) {
+ rc = PTR_ERR_OR_EINVAL(qp);
+ goto out_err;
+ }
+
+ hbl_cn_qp_do_release(qp);
+
+ port_funcs->cfg_unlock(cn_port);
+
+ return 0;
+
+out_err:
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static void hbl_cn_qps_stop(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs = cn_port->hdev->asic_funcs->port_funcs;
+ struct hbl_cn_qpc_drain_attr drain = { .wait_for_idle = false, };
+ unsigned long qp_id = 0;
+ struct hbl_cn_qp *qp;
+
+ port_funcs->cfg_lock(cn_port);
+
+ xa_for_each(&cn_port->qp_ids, qp_id, qp) {
+ if (IS_ERR_OR_NULL(qp))
+ continue;
+
+ hbl_cn_qp_modify(cn_port, qp, CN_QP_STATE_QPD, (void *)&drain);
+ }
+
+ port_funcs->cfg_unlock(cn_port);
+}
+
+static void qps_stop(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_port *cn_port;
+ int i;
+
+ /* stop the QPs */
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ hbl_cn_qps_stop(cn_port);
+ }
+}
+
+static int user_wq_arr_set(struct hbl_cn_device *hdev, struct hbl_cni_user_wq_arr_set_in *in,
+ struct hbl_cni_user_wq_arr_set_out *out, struct hbl_cn_ctx *ctx)
+{
+ u32 port, type, num_of_wqs, num_of_wq_entries, min_wqs_per_port, mem_id;
+ struct hbl_cn_wq_array_properties *wq_arr_props;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_properties *cn_props;
+ struct hbl_cn_port *cn_port;
+ char *type_str;
+ int rc;
+
+ if (in->swq_granularity > HBL_CNI_SWQE_GRAN_64B) {
+ dev_dbg(hdev->dev, "Invalid send WQE granularity %d\n", in->swq_granularity);
+ return -EINVAL;
+ }
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+ cn_props = &hdev->cn_props;
+
+ type = in->type;
+
+ if (type > cn_props->max_wq_arr_type) {
+ dev_dbg(hdev->dev, "invalid type %d, can't set user WQ\n", type);
+ return -EINVAL;
+ }
+
+ mem_id = in->mem_id;
+
+ if (mem_id != HBL_CNI_MEM_HOST && mem_id != HBL_CNI_MEM_DEVICE) {
+ dev_dbg(hdev->dev, "invalid memory type %d for user WQ\n", mem_id);
+ return -EINVAL;
+ }
+
+ port = in->port;
+ rc = hbl_cn_cmd_port_check(hdev, port, NIC_PORT_CHECK_OPEN | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ cn_port = &hdev->cn_ports[port];
+
+ wq_arr_props = &cn_port->wq_arr_props[type];
+ type_str = wq_arr_props->type_str;
+
+ /* For generic WQs minimum number of wqs required is 2, one for raw eth and one for rdma */
+ min_wqs_per_port = NIC_MIN_WQS_PER_PORT;
+ if (in->num_of_wqs < min_wqs_per_port) {
+ dev_dbg(hdev->dev, "number of %s WQs must be minimum %d, port %d\n", type_str,
+ min_wqs_per_port, port);
+ return -EINVAL;
+ }
+
+ /* H/W limitation */
+ if (in->num_of_wqs > cn_props->max_hw_qps_num) {
+ dev_dbg(hdev->dev, "number of %s WQs (0x%x) can't be bigger than 0x%x, port %d\n",
+ type_str, in->num_of_wqs, cn_props->max_hw_qps_num, port);
+ return -EINVAL;
+ }
+
+ if (!is_power_of_2(in->num_of_wq_entries)) {
+ dev_dbg(hdev->dev,
+ "number of %s WQ entries (0x%x) must be a power of 2, port %d\n", type_str,
+ in->num_of_wq_entries, port);
+ return -EINVAL;
+ }
+
+ /* H/W limitation */
+ if (in->num_of_wq_entries < cn_props->min_hw_user_wqs_num) {
+ dev_dbg(hdev->dev,
+ "number of %s WQ entries (0x%x) must be at least %d, port %d\n", type_str,
+ in->num_of_wq_entries, cn_props->min_hw_user_wqs_num, port);
+ return -EINVAL;
+ }
+
+ /* H/W limitation */
+ if (in->num_of_wq_entries > cn_props->max_hw_user_wqs_num) {
+ dev_dbg(hdev->dev,
+ "number of %s WQ entries (0x%x) can't be bigger than 0x%x, port %d\n",
+ type_str, in->num_of_wq_entries, cn_props->max_hw_user_wqs_num, port);
+ return -EINVAL;
+ }
+
+ port_funcs->cfg_lock(cn_port);
+
+ if (!cn_port->set_app_params) {
+ dev_dbg(hdev->dev,
+ "Failed to set %s WQ array, set_app_params wasn't called yet, port %d\n",
+ type_str, port);
+ rc = -EPERM;
+ goto out;
+ }
+
+ /* we first check the wq_under_unset condition since a prev WQ unset (async) operation may
+ * still be in progress, and since in such cases we would like to return -EAGAIN to the
+ * caller and not -EINVAL
+ */
+ if (wq_arr_props->enabled && wq_arr_props->under_unset) {
+ dev_dbg_ratelimited(hdev->dev,
+ "Retry to set %s WQ array as it is under unset, port %d\n",
+ type_str, port);
+ rc = -EAGAIN;
+ goto out;
+ }
+
+ if (wq_arr_props->enabled) {
+ dev_dbg(hdev->dev, "%s WQ array is already enabled, port %d\n", type_str, port);
+ rc = -EINVAL;
+ goto out;
+ }
+
+ if (wq_arr_props->under_unset) {
+ dev_dbg(hdev->dev,
+ "Failed to set %s WQ array as it is not enabled and under unset, port %d\n",
+ type_str, port);
+ rc = -EPERM;
+ goto out;
+ }
+
+ num_of_wq_entries = cn_port->num_of_wq_entries;
+ num_of_wqs = cn_port->num_of_wqs;
+
+ if (num_of_wq_entries && num_of_wq_entries != in->num_of_wq_entries) {
+ dev_dbg(hdev->dev, "%s WQ number of entries (0x%x) should be 0x%x, port %d\n",
+ type_str, in->num_of_wq_entries, num_of_wq_entries, port);
+ rc = -EINVAL;
+ goto out;
+ }
+
+ if (num_of_wqs && num_of_wqs != in->num_of_wqs) {
+ dev_dbg(hdev->dev, "%s WQs number (0x%x) should be 0x%x, port %d\n",
+ type_str, in->num_of_wqs, num_of_wqs, port);
+ rc = -EINVAL;
+ goto out;
+ }
+
+ rc = hdev->asic_funcs->user_wq_arr_set(hdev, in, out, ctx);
+ if (rc) {
+ dev_err(hdev->dev, "%s WQ array set failed, port %d, err %d\n", type_str, port, rc);
+ goto out;
+ }
+
+ cn_port->num_of_wq_entries = in->num_of_wq_entries;
+ cn_port->num_of_wqs = in->num_of_wqs;
+
+ wq_arr_props->enabled = true;
+
+out:
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static int __user_wq_arr_unset(struct hbl_cn_ctx *ctx, struct hbl_cn_port *cn_port, u32 type)
+{
+ struct hbl_cn_wq_array_properties *wq_arr_props;
+ struct hbl_cn_device *hdev;
+ char *type_str;
+ u32 port;
+ int rc;
+
+ hdev = ctx->hdev;
+ wq_arr_props = &cn_port->wq_arr_props[type];
+ type_str = wq_arr_props->type_str;
+ port = cn_port->port;
+
+ rc = hdev->asic_funcs->port_funcs->user_wq_arr_unset(ctx, cn_port, type);
+ if (rc)
+ dev_err(hdev->dev, "%s WQ array unset failed, port %d, err %d\n", type_str, port,
+ rc);
+
+ wq_arr_props->enabled = false;
+ wq_arr_props->under_unset = false;
+
+ if (!cn_port->wq_arr_props[HBL_CNI_USER_WQ_SEND].enabled &&
+ !cn_port->wq_arr_props[HBL_CNI_USER_WQ_RECV].enabled) {
+ cn_port->num_of_wq_entries = 0;
+ cn_port->num_of_wqs = 0;
+ }
+
+ return rc;
+}
+
+static int user_wq_arr_unset(struct hbl_cn_device *hdev, struct hbl_cni_user_wq_arr_unset_in *in,
+ struct hbl_cn_ctx *ctx)
+{
+ struct hbl_cn_wq_array_properties *wq_arr_props;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_properties *cn_props;
+ struct hbl_cn_port *cn_port;
+ u32 port, type;
+ char *type_str;
+ int rc;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+ cn_props = &hdev->cn_props;
+
+ type = in->type;
+
+ if (type > cn_props->max_wq_arr_type) {
+ dev_dbg(hdev->dev, "invalid type %d, can't unset user WQ\n", type);
+ return -EINVAL;
+ }
+
+ port = in->port;
+
+ /* No need to check if the port is open because internal ports are always open and external
+ * ports might be closed by a user command e.g. "ip link set down" after a WQ was
+ * configured, but we still want to unset it.
+ */
+ rc = hbl_cn_cmd_port_check(hdev, port, NIC_PORT_CHECK_ENABLE | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ cn_port = &hdev->cn_ports[port];
+
+ wq_arr_props = &cn_port->wq_arr_props[type];
+ type_str = wq_arr_props->type_str;
+
+ port_funcs->cfg_lock(cn_port);
+
+ if (!wq_arr_props->enabled) {
+ dev_dbg(hdev->dev, "%s WQ array is disabled, port %d\n", type_str, port);
+ rc = -EINVAL;
+ goto out;
+ }
+
+ if (wq_arr_props->under_unset) {
+ dev_dbg(hdev->dev, "%s WQ array is already under unset, port %d\n", type_str, port);
+ rc = -EPERM;
+ goto out;
+ }
+
+ /* Allocated QPs might still use the WQ, hence unset the WQ once they are destroyed */
+ if (atomic_read(&cn_port->num_of_allocated_qps)) {
+ wq_arr_props->under_unset = true;
+ rc = 0;
+ goto out;
+ }
+
+ rc = __user_wq_arr_unset(ctx, cn_port, type);
+out:
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static int alloc_user_cq_id(struct hbl_cn_device *hdev, struct hbl_cni_alloc_user_cq_id_in *in,
+ struct hbl_cni_alloc_user_cq_id_out *out, struct hbl_cn_ctx *ctx)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs = hdev->asic_funcs->port_funcs;
+ struct hbl_cn_properties *cn_props = &hdev->cn_props;
+ u32 min_id, max_id, port, flags;
+ struct hbl_cn_user_cq *user_cq;
+ struct hbl_cn_port *cn_port;
+ struct xa_limit id_limit;
+ int id, rc;
+
+ port = in->port;
+ flags = NIC_PORT_PRINT_ON_ERR;
+
+ if (!cn_props->force_cq)
+ flags |= NIC_PORT_CHECK_OPEN;
+
+ rc = hbl_cn_cmd_port_check(hdev, port, flags);
+ if (rc)
+ return rc;
+
+ cn_port = &hdev->cn_ports[port];
+
+ user_cq = kzalloc(sizeof(*user_cq), GFP_KERNEL);
+ if (!user_cq)
+ return -ENOMEM;
+
+ user_cq->state = USER_CQ_STATE_ALLOC;
+ user_cq->ctx = ctx;
+ user_cq->cn_port = cn_port;
+ kref_init(&user_cq->refcount);
+
+ port_funcs->get_cq_id_range(cn_port, &min_id, &max_id);
+
+ port_funcs->cfg_lock(cn_port);
+
+ if (!cn_port->set_app_params) {
+ dev_dbg(hdev->dev,
+ "Failed to allocate a CQ ID, set_app_params wasn't called yet, port %d\n",
+ port);
+ rc = -EPERM;
+ goto cfg_unlock;
+ }
+
+ id_limit = XA_LIMIT(min_id, max_id);
+ rc = xa_alloc(&cn_port->cq_ids, &id, user_cq, id_limit, GFP_KERNEL);
+ if (rc) {
+ dev_err(hdev->dev, "No available user CQ, port %d\n", port);
+ goto cfg_unlock;
+ }
+
+ user_cq->id = id;
+
+ mutex_init(&user_cq->overrun_lock);
+
+ port_funcs->cfg_unlock(cn_port);
+
+ dev_dbg(hdev->dev, "Allocating CQ id %d in port %d", id, port);
+
+ out->id = id;
+
+ return 0;
+
+cfg_unlock:
+ port_funcs->cfg_unlock(cn_port);
+ kfree(user_cq);
+
+ return rc;
+}
+
+static bool validate_cq_id_range(struct hbl_cn_port *cn_port, u32 cq_id)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ u32 min_id, max_id;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ port_funcs->get_cq_id_range(cn_port, &min_id, &max_id);
+
+ return (cq_id >= min_id) && (cq_id <= max_id);
+}
+
+static int __user_cq_set(struct hbl_cn_device *hdev, struct hbl_cni_user_cq_set_in_params *in,
+ struct hbl_cni_user_cq_set_out_params *out)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs = hdev->asic_funcs->port_funcs;
+ struct hbl_cn_properties *cn_props = &hdev->cn_props;
+ struct hbl_cn_user_cq *user_cq;
+ struct hbl_cn_port *cn_port;
+ u32 port, flags, id;
+ int rc;
+
+ id = in->id;
+ port = in->port;
+
+ flags = NIC_PORT_PRINT_ON_ERR;
+
+ if (!cn_props->force_cq)
+ flags |= NIC_PORT_CHECK_OPEN;
+
+ rc = hbl_cn_cmd_port_check(hdev, port, flags);
+ if (rc)
+ return rc;
+
+ cn_port = &hdev->cn_ports[port];
+
+ if (!validate_cq_id_range(cn_port, id)) {
+ dev_dbg(hdev->dev, "user CQ %d is invalid, port %d\n", id, port);
+ return -EINVAL;
+ }
+
+ if (in->num_of_cqes < cn_props->user_cq_min_entries) {
+ dev_dbg(hdev->dev,
+ "user CQ %d buffer length must be at least 0x%x entries, port %d\n",
+ id, cn_props->user_cq_min_entries, port);
+ return -EINVAL;
+ }
+
+ if (!is_power_of_2(in->num_of_cqes)) {
+ dev_dbg(hdev->dev, "user CQ %d buffer length must be at power of 2, port %d\n",
+ id, port);
+ return -EINVAL;
+ }
+
+ if (in->num_of_cqes > cn_props->user_cq_max_entries) {
+ dev_dbg(hdev->dev,
+ "user CQ %d buffer length must not be more than 0x%x entries, port %d\n",
+ id, cn_props->user_cq_max_entries, port);
+ return -EINVAL;
+ }
+
+ port_funcs->cfg_lock(cn_port);
+
+ /* Validate if user CQ is allocated. */
+ user_cq = xa_load(&cn_port->cq_ids, id);
+ if (!user_cq) {
+ dev_dbg(hdev->dev, "user CQ %d wasn't allocated, port %d\n", id, port);
+ rc = -EINVAL;
+ goto out;
+ }
+
+ /* Validate that user CQ is in ALLOC state. */
+ if (user_cq->state != USER_CQ_STATE_ALLOC) {
+ dev_dbg(hdev->dev, "user CQ %d set failed, current state %d, port %d\n",
+ id, user_cq->state, port);
+ rc = -EINVAL;
+ goto out;
+ }
+
+ rc = port_funcs->user_cq_set(user_cq, in, out);
+ if (rc) {
+ dev_dbg(hdev->dev, "user CQ %d set failed, port %d\n", id, port);
+ goto out;
+ }
+
+ user_cq->state = USER_CQ_STATE_SET;
+out:
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static int user_cq_id_set(struct hbl_cn_device *hdev, struct hbl_cni_user_cq_id_set_in *in,
+ struct hbl_cni_user_cq_id_set_out *out)
+{
+ struct hbl_cni_user_cq_set_out_params out2 = {};
+ struct hbl_cni_user_cq_set_in_params in2 = {};
+ int rc;
+
+ in2.port = in->port;
+ in2.num_of_cqes = in->num_of_cqes;
+ in2.id = in->id;
+
+ rc = __user_cq_set(hdev, &in2, &out2);
+ if (rc)
+ return rc;
+
+ out->mem_handle = out2.mem_handle;
+ out->pi_handle = out2.pi_handle;
+ out->regs_handle = out2.regs_handle;
+ out->regs_offset = out2.regs_offset;
+
+ return 0;
+}
+
+static void user_cq_destroy(struct kref *kref)
+{
+ struct hbl_cn_user_cq *user_cq = container_of(kref, struct hbl_cn_user_cq, refcount);
+ struct hbl_cn_port *cn_port = user_cq->cn_port;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ /* Destroy the remaining resources allocated during SET state. The below callback needs to
+ * be called only if the CQ moved to unset from set state. This is because, this resource
+ * was created only during set state. If the CQ moved directly to unset from alloc then we
+ * shouldn't be trying to clear the resource.
+ */
+ if (user_cq->state == USER_CQ_STATE_SET_TO_UNSET)
+ port_funcs->user_cq_destroy(user_cq);
+
+ mutex_destroy(&user_cq->overrun_lock);
+ xa_erase(&cn_port->cq_ids, user_cq->id);
+ kfree(user_cq);
+}
+
+struct hbl_cn_user_cq *hbl_cn_user_cq_get(struct hbl_cn_port *cn_port, u8 cq_id)
+{
+ struct hbl_cn_user_cq *user_cq;
+
+ user_cq = xa_load(&cn_port->cq_ids, cq_id);
+ if (!user_cq || user_cq->state != USER_CQ_STATE_SET)
+ return NULL;
+
+ kref_get(&user_cq->refcount);
+
+ return user_cq;
+}
+
+int hbl_cn_user_cq_put(struct hbl_cn_user_cq *user_cq)
+{
+ return kref_put(&user_cq->refcount, user_cq_destroy);
+}
+
+static int user_cq_unset_locked(struct hbl_cn_user_cq *user_cq, bool warn_if_alive)
+{
+ struct hbl_cn_port *cn_port = user_cq->cn_port;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port, id = user_cq->id;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ int rc = 0, ret;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ /* Call unset only if the CQ has already been SET */
+ if (user_cq->state == USER_CQ_STATE_SET) {
+ rc = port_funcs->user_cq_unset(user_cq);
+ if (rc)
+ dev_dbg(hdev->dev, "user CQ %d unset failed, port %d\n", id, port);
+
+ user_cq->state = USER_CQ_STATE_SET_TO_UNSET;
+ } else {
+ user_cq->state = USER_CQ_STATE_ALLOC_TO_UNSET;
+ }
+
+ /* we'd like to destroy even if the unset callback returned error */
+ ret = hbl_cn_user_cq_put(user_cq);
+
+ if (warn_if_alive && ret != 1)
+ dev_warn(hdev->dev, "user CQ %d was not destroyed, port %d\n", id, port);
+
+ return rc;
+}
+
+static int __user_cq_unset(struct hbl_cn_device *hdev, struct hbl_cni_user_cq_unset_in_params *in)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs = hdev->asic_funcs->port_funcs;
+ struct hbl_cn_properties *cn_props = &hdev->cn_props;
+ struct hbl_cn_user_cq *user_cq;
+ struct hbl_cn_port *cn_port;
+ u32 port, flags, id;
+ int rc;
+
+ port = in->port;
+ id = in->id;
+
+ if (port >= cn_props->max_num_of_ports) {
+ dev_dbg(hdev->dev, "Invalid port %d\n", port);
+ return -EINVAL;
+ }
+
+ cn_port = &hdev->cn_ports[port];
+
+ flags = NIC_PORT_PRINT_ON_ERR;
+
+ /* Unless force_cq flag in enabled, in case of user CQ unset of external ports, the port
+ * may be already closed by the user, so we only check if the port is enabled.
+ */
+ if (!cn_props->force_cq)
+ flags |= cn_port->eth_enable ? NIC_PORT_CHECK_ENABLE : NIC_PORT_CHECK_OPEN;
+
+ rc = hbl_cn_cmd_port_check(hdev, port, flags);
+ if (rc)
+ return rc;
+
+ if (!validate_cq_id_range(cn_port, id)) {
+ dev_dbg(hdev->dev, "user CQ %d is invalid, port %d\n", id, port);
+ return -EINVAL;
+ }
+
+ port_funcs->cfg_lock(cn_port);
+
+ /* Validate if user CQ is allocated. */
+ user_cq = xa_load(&cn_port->cq_ids, id);
+ if (!user_cq) {
+ dev_dbg(hdev->dev, "user CQ %d wasn't allocated, port %d\n", id, port);
+ rc = -EINVAL;
+ goto out;
+ }
+
+ rc = user_cq_unset_locked(user_cq, false);
+out:
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static int user_cq_id_unset(struct hbl_cn_device *hdev, struct hbl_cni_user_cq_id_unset_in *in)
+{
+ struct hbl_cni_user_cq_unset_in_params in2 = {};
+
+ in2.port = in->port;
+ in2.id = in->id;
+
+ return __user_cq_unset(hdev, &in2);
+}
+
+static int user_set_app_params(struct hbl_cn_device *hdev,
+ struct hbl_cni_set_user_app_params_in *in, struct hbl_cn_ctx *ctx)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_port *cn_port;
+ bool modify_wqe_checkers;
+ u32 port;
+ int rc;
+
+ port_funcs = asic_funcs->port_funcs;
+
+ port = in->port;
+
+ rc = hbl_cn_cmd_port_check(hdev, port, NIC_PORT_CHECK_OPEN | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ cn_port = &hdev->cn_ports[port];
+
+ /* We must take rtnl_lock here prior to taking cfg_lock, as we may land into flow that
+ * extracts the IP port and that can cause a deadlock in case an operation from the
+ * net subsystem that requires the cfg_lock is executed at the same time. As such operation
+ * will first obtain rtnl_lock and then will try to take a cfg_lock, hence a deadlock.
+ */
+ rtnl_lock();
+ port_funcs->cfg_lock(cn_port);
+
+ rc = asic_funcs->user_set_app_params(hdev, in, &modify_wqe_checkers, ctx);
+ if (rc)
+ goto out;
+
+ if (modify_wqe_checkers) {
+ rc = hdev->asic_funcs->port_funcs->disable_wqe_index_checker(cn_port);
+ if (rc) {
+ dev_err(hdev->dev, "Failed disable wqe index checker, port %d rc %d\n",
+ port, rc);
+ goto out;
+ }
+ }
+
+ cn_port->set_app_params = true;
+
+out:
+ port_funcs->cfg_unlock(cn_port);
+ rtnl_unlock();
+
+ return rc;
+}
+
+static int user_get_app_params(struct hbl_cn_device *hdev,
+ struct hbl_cni_get_user_app_params_in *in,
+ struct hbl_cni_get_user_app_params_out *out)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_port *cn_port;
+ u32 port;
+ int rc;
+
+ port_funcs = asic_funcs->port_funcs;
+
+ port = in->port;
+
+ rc = hbl_cn_cmd_port_check(hdev, port, NIC_PORT_CHECK_OPEN | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ cn_port = &hdev->cn_ports[port];
+
+ port_funcs->cfg_lock(cn_port);
+ asic_funcs->user_get_app_params(hdev, in, out);
+ port_funcs->cfg_unlock(cn_port);
+
+ return 0;
+}
+
+static int eq_poll(struct hbl_cn_device *hdev, struct hbl_cn_ctx *ctx,
+ struct hbl_cni_eq_poll_in *in, struct hbl_cni_eq_poll_out *out)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+ struct hbl_cn_port *cn_port;
+ u32 port;
+ int rc;
+
+ port = in->port;
+ rc = hbl_cn_cmd_port_check(hdev, port, NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ cn_port = &hdev->cn_ports[port];
+ rc = asic_funcs->port_funcs->eq_poll(cn_port, ctx->asid, out);
+ switch (rc) {
+ case 0:
+ out->status = HBL_CNI_EQ_POLL_STATUS_SUCCESS;
+ break;
+ case -EOPNOTSUPP:
+ out->status = HBL_CNI_EQ_POLL_STATUS_ERR_UNSUPPORTED_OP;
+ break;
+ case -EINVAL:
+ out->status = HBL_CNI_EQ_POLL_STATUS_ERR_NO_SUCH_PORT;
+ break;
+ case -ENXIO:
+ out->status = HBL_CNI_EQ_POLL_STATUS_ERR_PORT_DISABLED;
+ break;
+ case -ENODATA:
+ out->status = HBL_CNI_EQ_POLL_STATUS_EQ_EMPTY;
+ break;
+ case -ESRCH:
+ out->status = HBL_CNI_EQ_POLL_STATUS_ERR_NO_SUCH_EQ;
+ break;
+ default:
+ out->status = HBL_CNI_EQ_POLL_STATUS_ERR_UNDEF;
+ break;
+ }
+
+ return 0;
+}
+
+static void get_user_db_fifo_id_range(struct hbl_cn_port *cn_port, u32 *min_id, u32 *max_id,
+ u32 id_hint)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs;
+
+ port_funcs = cn_port->hdev->asic_funcs->port_funcs;
+
+ /* id_hint comes from user. Driver enforces allocation of the requested
+ * db fifo HW resource. i.e. driver fails if requested resource is not
+ * available. Reason, user stack has hard coded user fifo resource IDs.
+ */
+ if (id_hint) {
+ *min_id = id_hint;
+ *max_id = id_hint;
+ } else {
+ port_funcs->get_db_fifo_id_range(cn_port, min_id, max_id);
+ }
+}
+
+static int alloc_user_db_fifo(struct hbl_cn_device *hdev, struct hbl_cn_ctx *ctx,
+ struct hbl_cni_alloc_user_db_fifo_in *in,
+ struct hbl_cni_alloc_user_db_fifo_out *out)
+{
+ struct hbl_cn_db_fifo_xarray_pdata *xa_pdata;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_port *cn_port;
+ struct xa_limit id_limit;
+ u32 min_id, max_id;
+ int rc, id;
+ u32 port;
+
+ port = in->port;
+ rc = hbl_cn_cmd_port_check(hdev, port, NIC_PORT_CHECK_OPEN | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ cn_port = &hdev->cn_ports[port];
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ get_user_db_fifo_id_range(cn_port, &min_id, &max_id, in->id_hint);
+
+ /* IDR private data. */
+ xa_pdata = kzalloc(sizeof(*xa_pdata), GFP_KERNEL);
+ if (!xa_pdata)
+ return -ENOMEM;
+
+ xa_pdata->asid = ctx->asid;
+ xa_pdata->state = DB_FIFO_STATE_ALLOC;
+ xa_pdata->port = port;
+
+ port_funcs->cfg_lock(cn_port);
+
+ if (!cn_port->set_app_params) {
+ dev_dbg(hdev->dev,
+ "Failed to allocate DB FIFO, set_app_params wasn't called yet, port %d\n",
+ port);
+ rc = -EPERM;
+ goto cfg_unlock;
+ }
+
+ id_limit = XA_LIMIT(min_id, max_id);
+ rc = xa_alloc(&cn_port->db_fifo_ids, &id, xa_pdata, id_limit, GFP_KERNEL);
+ if (rc) {
+ dev_dbg_ratelimited(hdev->dev, "DB FIFO ID allocation failed, port %d\n", port);
+ goto cfg_unlock;
+ }
+
+ xa_pdata->id = id;
+
+ port_funcs->cfg_unlock(cn_port);
+
+ out->id = id;
+
+ return 0;
+
+cfg_unlock:
+ port_funcs->cfg_unlock(cn_port);
+ kfree(xa_pdata);
+ return rc;
+}
+
+static int validate_db_fifo_id_range(struct hbl_cn_port *cn_port, u32 db_fifo_id)
+{
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct hbl_cn_device *hdev;
+ u32 min_id, max_id;
+
+ hdev = cn_port->hdev;
+ asic_funcs = hdev->asic_funcs;
+
+ asic_funcs->port_funcs->get_db_fifo_id_range(cn_port, &min_id, &max_id);
+
+ if (db_fifo_id < min_id || db_fifo_id > max_id) {
+ dev_dbg_ratelimited(hdev->dev, "Invalid db fifo ID, %d, port: %d\n", db_fifo_id,
+ cn_port->port);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int validate_db_fifo_mode(struct hbl_cn_port *cn_port, u8 fifo_mode)
+{
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct hbl_cn_device *hdev;
+ u32 modes_mask;
+
+ hdev = cn_port->hdev;
+ asic_funcs = hdev->asic_funcs;
+
+ asic_funcs->port_funcs->get_db_fifo_modes_mask(cn_port, &modes_mask);
+
+ if (!(BIT(fifo_mode) & modes_mask)) {
+ dev_dbg_ratelimited(hdev->dev, "Invalid db fifo mode, %d, port: %d\n", fifo_mode,
+ cn_port->port);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int validate_db_fifo_ioctl(struct hbl_cn_port *cn_port, u32 db_fifo_id)
+{
+ return validate_db_fifo_id_range(cn_port, db_fifo_id);
+}
+
+static int user_db_fifo_unset_and_free(struct hbl_cn_port *cn_port,
+ struct hbl_cn_db_fifo_xarray_pdata *xa_pdata)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ int rc = 0;
+
+ asic_funcs = hdev->asic_funcs;
+
+ asic_funcs->port_funcs->db_fifo_unset(cn_port, xa_pdata->id, xa_pdata);
+
+ /* Destroy CI buffer if we allocated one.
+ * Note: Not all DB fifo modes need CI memory buffer.
+ * Track CI via sync objects.
+ * If there is an issue in destroying the CI memory, then we might exit this function
+ * without freeing the db_fifo_pool. This would cause a kernel assertion when we try to do
+ * rmmod as the gen_alloc_destroy for db_fifo_pool would fail as there are allocations
+ * still left in the pool. So, the db_fifo_pool needs to be freed irrespective of the ci
+ * memory being destroyed or not.
+ */
+ if (xa_pdata->ci_mmap_handle)
+ rc = hbl_cn_mem_destroy(hdev, xa_pdata->ci_mmap_handle);
+
+ asic_funcs->port_funcs->db_fifo_free(cn_port, xa_pdata->db_pool_addr, xa_pdata->fifo_size);
+
+ return rc;
+}
+
+static int user_db_fifo_set(struct hbl_cn_device *hdev, struct hbl_cn_ctx *ctx,
+ struct hbl_cni_user_db_fifo_set_in *in,
+ struct hbl_cni_user_db_fifo_set_out *out)
+{
+ u64 umr_block_addr, umr_mmap_handle, ci_mmap_handle = 0, ci_device_handle;
+ struct hbl_cn_db_fifo_xarray_pdata *xa_pdata;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_mem_data mem_data = {};
+ struct hbl_cn_port *cn_port;
+ u32 umr_db_offset, port, id;
+ int rc;
+
+ port = in->port;
+ rc = hbl_cn_cmd_port_check(hdev, port, NIC_PORT_CHECK_OPEN | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ cn_port = &hdev->cn_ports[port];
+ port_funcs = hdev->asic_funcs->port_funcs;
+ id = in->id;
+
+ rc = validate_db_fifo_ioctl(cn_port, id);
+ if (rc)
+ return rc;
+
+ /* Get allocated ID private data. Having meta data associated with IDR also helps validate
+ * that user do not trick kernel into configuring db fifo HW for an unallocated ID.
+ */
+ port_funcs->cfg_lock(cn_port);
+ xa_pdata = xa_load(&cn_port->db_fifo_ids, id);
+ if (!xa_pdata) {
+ dev_dbg_ratelimited(hdev->dev, "DB FIFO ID %d is not allocated, port: %d\n", id,
+ port);
+ rc = -EINVAL;
+ goto cfg_unlock;
+ }
+
+ rc = validate_db_fifo_mode(cn_port, in->mode);
+ if (rc)
+ goto cfg_unlock;
+
+ xa_pdata->fifo_mode = in->mode;
+
+ /* User may call db_fifo_set multiple times post db_fifo_alloc. So, before doing any
+ * further register changes, make sure to unset the previous settings for this id
+ */
+ if (xa_pdata->state == DB_FIFO_STATE_SET) {
+ rc = user_db_fifo_unset_and_free(cn_port, xa_pdata);
+ if (rc) {
+ dev_dbg(hdev->dev, "Fail to unset DB FIFO %d before set, port %d\n", id,
+ port);
+ goto cfg_unlock;
+ }
+ }
+
+ rc = port_funcs->db_fifo_allocate(cn_port, xa_pdata);
+ if (rc) {
+ dev_dbg(hdev->dev, "DB FIFO %d allocation failed, port %d, mode %d\n", id, port,
+ in->mode);
+ goto cfg_unlock;
+ }
+
+ /* Get the user mapped register(UMR) block address and
+ * db fifo offset associated with the ID.
+ */
+ port_funcs->get_db_fifo_umr(cn_port, id, &umr_block_addr, &umr_db_offset);
+
+ /* Get mmap handle for UMR block. */
+ rc = hbl_cn_get_hw_block_handle(hdev, umr_block_addr, &umr_mmap_handle);
+ if (rc) {
+ dev_dbg_ratelimited(hdev->dev,
+ "Failed to get UMR mmap handle of DB FIFO %d, port %d\n", id,
+ port);
+ goto free_db_fifo;
+ }
+
+ /* Allocate a consumer-index(CI) buffer in host kernel.
+ * HW updates CI when it pops a db fifo. User mmaps CI buffer and may poll to read current
+ * CI.
+ * Allocate page size, else we risk exposing kernel data to userspace inadvertently.
+ */
+ mem_data.mem_id = HBL_CN_DRV_MEM_HOST_DMA_COHERENT;
+ mem_data.size = PAGE_SIZE;
+ rc = hbl_cn_mem_alloc(ctx, &mem_data);
+ if (rc) {
+ dev_dbg_ratelimited(hdev->dev,
+ "DB FIFO id %d, CI buffer allocation failed, port %d\n",
+ id, port);
+ goto free_db_fifo;
+ }
+
+ ci_mmap_handle = mem_data.handle;
+ ci_device_handle = mem_data.addr;
+
+ rc = port_funcs->db_fifo_set(cn_port, ctx, id, ci_device_handle, xa_pdata);
+ if (rc) {
+ dev_dbg_ratelimited(hdev->dev, "DB FIFO id %d, HW config failed, port %d\n", id,
+ port);
+ goto free_ci;
+ }
+
+ /* Cache IDR metadata and init IOCTL out. */
+ out->ci_handle = ci_mmap_handle;
+ out->regs_handle = umr_mmap_handle;
+ out->regs_offset = umr_db_offset;
+
+ xa_pdata->ci_mmap_handle = out->ci_handle;
+ xa_pdata->umr_mmap_handle = out->regs_handle;
+ xa_pdata->umr_db_offset = out->regs_offset;
+ xa_pdata->state = DB_FIFO_STATE_SET;
+
+ out->fifo_size = xa_pdata->fifo_size;
+ out->fifo_bp_thresh = xa_pdata->fifo_size / 2;
+
+ port_funcs->cfg_unlock(cn_port);
+
+ return 0;
+
+free_ci:
+ if (ci_mmap_handle)
+ hbl_cn_mem_destroy(hdev, ci_mmap_handle);
+free_db_fifo:
+ port_funcs->db_fifo_free(cn_port, xa_pdata->db_pool_addr, xa_pdata->fifo_size);
+cfg_unlock:
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static int __user_db_fifo_unset(struct hbl_cn_port *cn_port,
+ struct hbl_cn_db_fifo_xarray_pdata *xa_pdata)
+{
+ u32 id = xa_pdata->id;
+ int rc = 0;
+
+ /* User may call unset or the context may be destroyed while a db fifo is still in
+ * allocated state. When we call alloc_user_db_fifo next time, we would skip that
+ * particular id. This way, the id is blocked indefinitely until a full reset is done.
+ * So to fix this issue, we maintain the state of the idr. Perform unset only if set had
+ * been previously done for the idr.
+ */
+ if (xa_pdata->state == DB_FIFO_STATE_SET)
+ rc = user_db_fifo_unset_and_free(cn_port, xa_pdata);
+
+ kfree(xa_pdata);
+ xa_erase(&cn_port->db_fifo_ids, id);
+
+ return rc;
+}
+
+static int user_db_fifo_unset(struct hbl_cn_device *hdev, struct hbl_cni_user_db_fifo_unset_in *in)
+{
+ struct hbl_cn_db_fifo_xarray_pdata *xa_pdata;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_port *cn_port;
+ int rc;
+ u32 id;
+
+ rc = hbl_cn_cmd_port_check(hdev, in->port, NIC_PORT_CHECK_OPEN | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ cn_port = &hdev->cn_ports[in->port];
+ port_funcs = hdev->asic_funcs->port_funcs;
+ id = in->id;
+
+ rc = validate_db_fifo_ioctl(cn_port, id);
+ if (rc)
+ return rc;
+
+ port_funcs->cfg_lock(cn_port);
+
+ xa_pdata = xa_load(&cn_port->db_fifo_ids, id);
+ if (!xa_pdata) {
+ dev_dbg_ratelimited(hdev->dev, "DB fifo ID %d is not allocated, port: %d\n", id,
+ in->port);
+ rc = -EINVAL;
+ goto out;
+ }
+
+ rc = __user_db_fifo_unset(cn_port, xa_pdata);
+out:
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static int user_encap_alloc(struct hbl_cn_device *hdev, struct hbl_cni_user_encap_alloc_in *in,
+ struct hbl_cni_user_encap_alloc_out *out)
+{
+ struct hbl_cn_encap_xarray_pdata *xa_pdata;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_port *cn_port;
+ struct xa_limit id_limit;
+ u32 min_id, max_id;
+ int rc, id;
+ u32 port;
+
+ port = in->port;
+ rc = hbl_cn_cmd_port_check(hdev, port, NIC_PORT_CHECK_OPEN | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ cn_port = &hdev->cn_ports[port];
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ port_funcs->get_encap_id_range(cn_port, &min_id, &max_id);
+
+ /* IDR private data. */
+ xa_pdata = kzalloc(sizeof(*xa_pdata), GFP_KERNEL);
+ if (!xa_pdata)
+ return -ENOMEM;
+
+ xa_pdata->port = port;
+
+ port_funcs->cfg_lock(cn_port);
+
+ if (!cn_port->set_app_params) {
+ dev_dbg(hdev->dev,
+ "Failed to allocate encapsulation ID, set_app_params wasn't called yet, port %d\n",
+ port);
+ rc = -EPERM;
+ goto cfg_unlock;
+ }
+
+ id_limit = XA_LIMIT(min_id, max_id);
+ rc = xa_alloc(&cn_port->encap_ids, &id, xa_pdata, id_limit, GFP_KERNEL);
+ if (rc) {
+ dev_dbg_ratelimited(hdev->dev, "Encapsulation ID allocation failed, port %d\n",
+ port);
+ goto cfg_unlock;
+ }
+
+ xa_pdata->id = id;
+ port_funcs->cfg_unlock(cn_port);
+
+ out->id = id;
+
+ return 0;
+
+cfg_unlock:
+ port_funcs->cfg_unlock(cn_port);
+ kfree(xa_pdata);
+
+ return rc;
+}
+
+static int validate_encap_id_range(struct hbl_cn_port *cn_port, u32 encap_id)
+{
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct hbl_cn_device *hdev;
+ u32 min_id, max_id;
+
+ hdev = cn_port->hdev;
+ asic_funcs = hdev->asic_funcs;
+
+ asic_funcs->port_funcs->get_encap_id_range(cn_port, &min_id, &max_id);
+
+ if (encap_id < min_id || encap_id > max_id) {
+ dev_dbg_ratelimited(hdev->dev, "Invalid encapsulation ID, %d\n", encap_id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int validate_encap_ioctl(struct hbl_cn_port *cn_port, u32 encap_id)
+{
+ return validate_encap_id_range(cn_port, encap_id);
+}
+
+static bool is_encap_supported(struct hbl_cn_device *hdev, struct hbl_cni_user_encap_set_in *in)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+
+ return asic_funcs->is_encap_supported(hdev, in);
+}
+
+static int user_encap_set(struct hbl_cn_device *hdev, struct hbl_cni_user_encap_set_in *in)
+{
+ struct hbl_cn_encap_xarray_pdata *xa_pdata;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_port *cn_port;
+ u32 id, encap_type_data = 0;
+ void *encap_header = NULL;
+ int rc;
+
+ /* Check if the user request for encap set is supported */
+ if (!is_encap_supported(hdev, in))
+ return -EOPNOTSUPP;
+
+ rc = hbl_cn_cmd_port_check(hdev, in->port, NIC_PORT_CHECK_OPEN | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ cn_port = &hdev->cn_ports[in->port];
+ port_funcs = hdev->asic_funcs->port_funcs;
+ id = in->id;
+
+ rc = validate_encap_ioctl(cn_port, id);
+ if (rc)
+ return rc;
+
+ switch (in->encap_type) {
+ case HBL_CNI_ENCAP_OVER_IPV4:
+ encap_type_data = in->ip_proto;
+ break;
+ case HBL_CNI_ENCAP_OVER_UDP:
+ encap_type_data = in->udp_dst_port;
+ break;
+ case HBL_CNI_ENCAP_NONE:
+ /* No encapsulation/tunneling mode. Just set
+ * source IPv4 address and UDP protocol.
+ */
+ encap_type_data = HBL_CN_IPV4_PROTOCOL_UDP;
+ break;
+ default:
+ dev_dbg_ratelimited(hdev->dev, "Invalid encapsulation type, %d\n", in->encap_type);
+ return -EINVAL;
+ }
+
+ port_funcs->cfg_lock(cn_port);
+
+ xa_pdata = xa_load(&cn_port->encap_ids, id);
+ if (!xa_pdata) {
+ dev_dbg_ratelimited(hdev->dev, "Encapsulation ID %d is not allocated\n", id);
+ rc = -EINVAL;
+ goto cfg_unlock;
+ }
+
+ /* There could be a use case wherein the user allocates a encap ID and then calls encap_set
+ * with IPv4 encap. Now, without doing a unset, the user can call the encap_set with UDP
+ * encap or encap_none. In this case, we should be clearing the existing settings as well
+ * as freeing any allocated buffer. So, call unset API to clear the settings
+ */
+ port_funcs->encap_unset(cn_port, id, xa_pdata);
+
+ if (xa_pdata->encap_type != HBL_CNI_ENCAP_NONE)
+ kfree(xa_pdata->encap_header);
+
+ if (in->encap_type != HBL_CNI_ENCAP_NONE) {
+ if (in->tnl_hdr_size > NIC_MAX_TNL_HDR_SIZE) {
+ dev_dbg_ratelimited(hdev->dev, "Invalid tunnel header size, %d\n",
+ in->tnl_hdr_size);
+ rc = -EINVAL;
+ goto cfg_unlock;
+ }
+
+ /* Align encapsulation header to 32bit register fields. */
+ encap_header = kzalloc(ALIGN(in->tnl_hdr_size, 4), GFP_KERNEL);
+ if (!encap_header) {
+ rc = -ENOMEM;
+ goto cfg_unlock;
+ }
+
+ rc = copy_from_user(encap_header, u64_to_user_ptr(in->tnl_hdr_ptr),
+ in->tnl_hdr_size);
+ if (rc) {
+ dev_dbg_ratelimited(hdev->dev,
+ "Copy encapsulation header data failed, %d\n", rc);
+ rc = -EFAULT;
+ goto free_header;
+ }
+
+ xa_pdata->encap_header = encap_header;
+ xa_pdata->encap_header_size = in->tnl_hdr_size;
+ }
+
+ xa_pdata->encap_type = in->encap_type;
+ xa_pdata->encap_type_data = encap_type_data;
+ xa_pdata->src_ip = in->ipv4_addr;
+ xa_pdata->is_set = true;
+
+ rc = port_funcs->encap_set(cn_port, id, xa_pdata);
+ if (rc)
+ goto free_header;
+
+ port_funcs->cfg_unlock(cn_port);
+
+ return 0;
+
+free_header:
+ if (in->encap_type != HBL_CNI_ENCAP_NONE)
+ kfree(encap_header);
+cfg_unlock:
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static int user_encap_unset(struct hbl_cn_device *hdev, struct hbl_cni_user_encap_unset_in *in)
+{
+ struct hbl_cn_encap_xarray_pdata *xa_pdata;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_port *cn_port;
+ int rc;
+ u32 id;
+
+ rc = hbl_cn_cmd_port_check(hdev, in->port, NIC_PORT_CHECK_OPEN | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ cn_port = &hdev->cn_ports[in->port];
+ port_funcs = hdev->asic_funcs->port_funcs;
+ id = in->id;
+
+ rc = validate_encap_ioctl(cn_port, id);
+ if (rc)
+ return rc;
+
+ port_funcs->cfg_lock(cn_port);
+
+ xa_pdata = xa_load(&cn_port->encap_ids, id);
+ if (!xa_pdata) {
+ dev_dbg_ratelimited(hdev->dev, "Encapsulation ID %d is not allocated\n", id);
+ rc = -EINVAL;
+ goto out;
+ }
+
+ if (xa_pdata->is_set) {
+ port_funcs->encap_unset(cn_port, id, xa_pdata);
+
+ if (xa_pdata->encap_type != HBL_CNI_ENCAP_NONE)
+ kfree(xa_pdata->encap_header);
+ }
+
+ xa_erase(&cn_port->encap_ids, id);
+ kfree(xa_pdata);
+
+out:
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static int user_ccq_set(struct hbl_cn_device *hdev, struct hbl_cni_user_ccq_set_in *in,
+ struct hbl_cni_user_ccq_set_out *out, struct hbl_cn_ctx *ctx)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs = hdev->asic_funcs->port_funcs;
+ u64 ccq_mmap_handle, ccq_device_addr, pi_mmap_handle, pi_device_addr;
+ struct hbl_cn_mem_data mem_data = {};
+ struct hbl_cn_port *cn_port;
+ u32 port, ccqn;
+ int rc;
+
+ rc = hbl_cn_cmd_port_check(hdev, in->port, NIC_PORT_CHECK_OPEN | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ port = in->port;
+
+ if (!hdev->mmu_bypass) {
+ dev_dbg(hdev->dev, "Allocation of non physical dma-mem is not supported, port %d\n",
+ port);
+ return -EOPNOTSUPP;
+ }
+
+ if (!is_power_of_2(in->num_of_entries)) {
+ dev_dbg(hdev->dev, "user CCQ buffer length must be at power of 2, port %d\n",
+ port);
+ return -EINVAL;
+ }
+
+ if (in->num_of_entries > USER_CCQ_MAX_ENTRIES ||
+ in->num_of_entries < USER_CCQ_MIN_ENTRIES) {
+ dev_dbg(hdev->dev, "CCQ buffer length invalid 0x%x, port %d\n", in->num_of_entries,
+ port);
+ return -EINVAL;
+ }
+
+ cn_port = &hdev->cn_ports[port];
+
+ port_funcs->cfg_lock(cn_port);
+
+ if (!cn_port->set_app_params) {
+ dev_dbg(hdev->dev,
+ "Failed to set CCQ handler, set_app_params wasn't called yet, port %d\n",
+ port);
+ rc = -EPERM;
+ goto cfg_unlock;
+ }
+
+ if (cn_port->ccq_enable) {
+ dev_dbg(hdev->dev, "Failed setting CCQ handler - it is already set, port %d\n",
+ port);
+ rc = -EBUSY;
+ goto cfg_unlock;
+ }
+
+ /* Allocate the queue memory buffer in host kernel */
+ mem_data.mem_id = HBL_CN_DRV_MEM_HOST_DMA_COHERENT;
+ mem_data.size = in->num_of_entries * CC_CQE_SIZE;
+ rc = hbl_cn_mem_alloc(ctx, &mem_data);
+ if (rc) {
+ dev_err(hdev->dev, "CCQ memory buffer allocation failed, port %d\n", port);
+ goto cfg_unlock;
+ }
+
+ ccq_mmap_handle = mem_data.handle;
+ ccq_device_addr = mem_data.addr;
+
+ /* Allocate a producer-index (PI) buffer in host kernel */
+ memset(&mem_data, 0, sizeof(mem_data));
+ mem_data.mem_id = HBL_CN_DRV_MEM_HOST_DMA_COHERENT;
+ mem_data.size = PAGE_SIZE;
+ rc = hbl_cn_mem_alloc(ctx, &mem_data);
+ if (rc) {
+ dev_err(hdev->dev, "CCQ PI buffer allocation failed, port %d\n", port);
+ goto free_ccq;
+ }
+
+ pi_mmap_handle = mem_data.handle;
+ pi_device_addr = mem_data.addr;
+
+ port_funcs->user_ccq_set(cn_port, ccq_device_addr, pi_device_addr, in->num_of_entries,
+ &ccqn);
+
+ rc = hbl_cn_eq_dispatcher_register_ccq(cn_port, ctx->asid, ccqn);
+ if (rc) {
+ dev_err(hdev->dev, "failed to register CCQ EQ handler, port %u, asid %u\n", port,
+ ctx->asid);
+ goto free_pi;
+ }
+
+ cn_port->ccq_handle = ccq_mmap_handle;
+ cn_port->ccq_pi_handle = pi_mmap_handle;
+
+ out->mem_handle = cn_port->ccq_handle;
+ out->pi_handle = cn_port->ccq_pi_handle;
+ out->id = ccqn;
+
+ cn_port->ccq_enable = true;
+
+ port_funcs->cfg_unlock(cn_port);
+
+ return 0;
+
+free_pi:
+ hbl_cn_mem_destroy(hdev, pi_mmap_handle);
+free_ccq:
+ hbl_cn_mem_destroy(hdev, ccq_mmap_handle);
+cfg_unlock:
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static int __user_ccq_unset(struct hbl_cn_device *hdev, struct hbl_cn_ctx *ctx, u32 port)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_port *cn_port;
+ bool has_errors = false;
+ u32 ccqn;
+ int rc;
+
+ cn_port = &hdev->cn_ports[port];
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+ port_funcs->user_ccq_unset(cn_port, &ccqn);
+
+ rc = hbl_cn_mem_destroy(hdev, cn_port->ccq_pi_handle);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to free CCQ PI memory, port %d\n", port);
+ has_errors = true;
+ }
+
+ rc = hbl_cn_mem_destroy(hdev, cn_port->ccq_handle);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to free CCQ memory, port %d\n", port);
+ has_errors = true;
+ }
+
+ rc = hbl_cn_eq_dispatcher_unregister_ccq(cn_port, ctx->asid, ccqn);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to unregister CCQ EQ handler, port %u, asid %u\n", port,
+ ctx->asid);
+ has_errors = true;
+ }
+
+ if (has_errors)
+ return -EIO;
+
+ cn_port->ccq_enable = false;
+
+ return 0;
+}
+
+static int user_ccq_unset(struct hbl_cn_device *hdev, struct hbl_cni_user_ccq_unset_in *in,
+ struct hbl_cn_ctx *ctx)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs = hdev->asic_funcs->port_funcs;
+ struct hbl_cn_port *cn_port;
+ u32 port;
+ int rc;
+
+ port = in->port;
+
+ rc = hbl_cn_cmd_port_check(hdev, port, NIC_PORT_CHECK_ENABLE | NIC_PORT_PRINT_ON_ERR);
+ if (rc)
+ return rc;
+
+ cn_port = &hdev->cn_ports[port];
+
+ port_funcs->cfg_lock(cn_port);
+
+ if (!cn_port->ccq_enable) {
+ dev_dbg(hdev->dev, "Failed unsetting CCQ handler - it is already unset, port %u\n",
+ port);
+ rc = -ENXIO;
+ goto out;
+ }
+
+ rc = __user_ccq_unset(hdev, ctx, in->port);
+out:
+ port_funcs->cfg_unlock(cn_port);
+
+ return rc;
+}
+
+static int dump_qp(struct hbl_cn_device *hdev, struct hbl_cni_dump_qp_in *in)
+{
+ struct hbl_cn_qp_info qp_info = {};
+ u32 buf_size;
+ char *buf;
+ int rc;
+
+ buf_size = in->user_buf_size;
+
+ if (!buf_size || buf_size > NIC_DUMP_QP_SZ) {
+ dev_err(hdev->dev, "Invalid buffer size %u\n", buf_size);
+ return -EINVAL;
+ }
+
+ buf = kzalloc(buf_size, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ qp_info.port = in->port;
+ qp_info.qpn = in->qpn;
+ qp_info.req = in->req;
+ qp_info.full_print = true;
+ qp_info.force_read = true;
+
+ rc = hdev->asic_funcs->qp_read(hdev, &qp_info, buf, buf_size);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to read QP %u, port %u\n", in->qpn, in->port);
+ goto out;
+ }
+
+ if (copy_to_user((void __user *)(uintptr_t)in->user_buf, buf, buf_size)) {
+ dev_err(hdev->dev, "copy to user failed in debug ioctl\n");
+ rc = -EFAULT;
+ goto out;
+ }
+
+out:
+ kfree(buf);
+ return rc;
+}
+
+static int __hbl_cn_control(struct hbl_cn_device *hdev, u32 op, void *input, void *output,
+ struct hbl_cn_ctx *ctx)
+{
+ int rc;
+
+ if (!(hdev->ctrl_op_mask & BIT(op))) {
+ dev_dbg(hdev->dev, "CN control request %d is not supported on this device\n", op);
+ return -EOPNOTSUPP;
+ }
+
+ switch (op) {
+ case HBL_CNI_OP_ALLOC_CONN:
+ rc = alloc_qp(hdev, ctx, input, output);
+ break;
+ case HBL_CNI_OP_SET_REQ_CONN_CTX:
+ rc = set_req_qp_ctx(hdev, input, output);
+ break;
+ case HBL_CNI_OP_SET_RES_CONN_CTX:
+ rc = set_res_qp_ctx(hdev, input);
+ break;
+ case HBL_CNI_OP_DESTROY_CONN:
+ rc = destroy_qp(hdev, input);
+ break;
+ case HBL_CNI_OP_USER_WQ_SET:
+ rc = user_wq_arr_set(hdev, input, output, ctx);
+ break;
+ case HBL_CNI_OP_USER_WQ_UNSET:
+ rc = user_wq_arr_unset(hdev, input, ctx);
+ break;
+ case HBL_CNI_OP_ALLOC_USER_CQ_ID:
+ rc = alloc_user_cq_id(hdev, input, output, ctx);
+ break;
+ case HBL_CNI_OP_SET_USER_APP_PARAMS:
+ rc = user_set_app_params(hdev, input, ctx);
+ break;
+ case HBL_CNI_OP_GET_USER_APP_PARAMS:
+ rc = user_get_app_params(hdev, input, output);
+ break;
+ case HBL_CNI_OP_EQ_POLL:
+ rc = eq_poll(hdev, ctx, input, output);
+ break;
+ case HBL_CNI_OP_ALLOC_USER_DB_FIFO:
+ rc = alloc_user_db_fifo(hdev, ctx, input, output);
+ break;
+ case HBL_CNI_OP_USER_DB_FIFO_SET:
+ rc = user_db_fifo_set(hdev, ctx, input, output);
+ break;
+ case HBL_CNI_OP_USER_DB_FIFO_UNSET:
+ rc = user_db_fifo_unset(hdev, input);
+ break;
+ case HBL_CNI_OP_USER_ENCAP_ALLOC:
+ rc = user_encap_alloc(hdev, input, output);
+ break;
+ case HBL_CNI_OP_USER_ENCAP_SET:
+ rc = user_encap_set(hdev, input);
+ break;
+ case HBL_CNI_OP_USER_ENCAP_UNSET:
+ rc = user_encap_unset(hdev, input);
+ break;
+ case HBL_CNI_OP_USER_CCQ_SET:
+ rc = user_ccq_set(hdev, input, output, ctx);
+ break;
+ case HBL_CNI_OP_USER_CCQ_UNSET:
+ rc = user_ccq_unset(hdev, input, ctx);
+ break;
+ case HBL_CNI_OP_USER_CQ_ID_SET:
+ rc = user_cq_id_set(hdev, input, output);
+ break;
+ case HBL_CNI_OP_USER_CQ_ID_UNSET:
+ rc = user_cq_id_unset(hdev, input);
+ break;
+ case HBL_CNI_OP_DUMP_QP:
+ rc = dump_qp(hdev, input);
+ break;
+ default:
+ /* we shouldn't get here as we check the opcode mask before */
+ dev_dbg(hdev->dev, "Invalid CN control request %d\n", op);
+ return -EINVAL;
+ }
+
+ return rc;
+}
+
+static int hbl_cn_ib_cmd_ctrl(struct hbl_aux_dev *aux_dev, void *cn_ib_ctx, u32 op, void *input,
+ void *output)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(aux_dev);
+ struct hbl_cn_ctx *ctx = cn_ib_ctx;
+ int rc;
+
+ mutex_lock(&ctx->lock);
+
+ do
+ rc = __hbl_cn_control(hdev, op, input, output, ctx);
+ while (rc == -EAGAIN);
+
+ mutex_unlock(&ctx->lock);
+
+ return rc;
+}
+
+static enum hbl_ib_mem_type mem_id_to_mem_type(enum hbl_cn_drv_mem_id id)
+{
+ switch (id) {
+ case HBL_CN_DRV_MEM_HOST_DMA_COHERENT:
+ return HBL_IB_MEM_HOST_DMA_COHERENT;
+ case HBL_CN_DRV_MEM_HOST_VIRTUAL:
+ return HBL_IB_MEM_HOST_VIRTUAL;
+ case HBL_CN_DRV_MEM_DEVICE:
+ return HBL_IB_MEM_DEVICE;
+ case HBL_CN_DRV_MEM_HOST_MAP_ONLY:
+ return HBL_IB_MEM_HOST_MAP_ONLY;
+ case HBL_CN_DRV_MEM_INVALID:
+ default:
+ return HBL_IB_MEM_INVALID;
+ }
+}
+
+static int hbl_cn_ib_query_mem_handle(struct hbl_aux_dev *ib_aux_dev, u64 mem_handle,
+ struct hbl_ib_mem_info *info)
+{
+ struct hbl_cn_device *hdev = HBL_AUX2NIC(ib_aux_dev);
+ struct hbl_cn_mem_buf *buf;
+ u64 mem_type;
+
+ mem_type = (mem_handle >> PAGE_SHIFT) & HBL_CN_MMAP_TYPE_MASK;
+
+ memset(info, 0, sizeof(*info));
+ info->mem_handle = mem_handle;
+
+ switch (mem_type) {
+ case HBL_CN_MMAP_TYPE_BLOCK:
+ info->mtype = HBL_IB_MEM_HW_BLOCK;
+ if (!hbl_cn_get_hw_block_addr(hdev, mem_handle, &info->bus_addr, &info->size))
+ return 0;
+
+ dev_err(hdev->dev, "NIC: No hw block address for handle %#llx\n", mem_handle);
+ break;
+ case HBL_CN_MMAP_TYPE_CN_MEM:
+ buf = hbl_cn_mem_buf_get(hdev, mem_handle);
+ if (!buf) {
+ dev_err(hdev->dev, "NIC: No buffer for handle %#llx\n", mem_handle);
+ break;
+ }
+
+ info->cpu_addr = buf->kernel_address;
+ info->bus_addr = buf->bus_address;
+ info->size = buf->mappable_size;
+ info->vmalloc = false;
+ info->mtype = mem_id_to_mem_type(buf->mem_id);
+
+ hbl_cn_mem_buf_put(buf);
+ return 0;
+ default:
+ dev_err(hdev->dev, "NIC: Invalid handle %#llx\n", mem_handle);
+ break;
+ }
+ return -EINVAL;
+}
+
+static void qps_destroy(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs = hdev->asic_funcs->port_funcs;
+ struct hbl_cn_port *cn_port;
+ unsigned long qp_id = 0;
+ struct hbl_cn_qp *qp;
+ int i;
+
+ /* destroy the QPs */
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ /* protect against destroy_qp occurring in parallel */
+ port_funcs->cfg_lock(cn_port);
+
+ xa_for_each(&cn_port->qp_ids, qp_id, qp) {
+ if (IS_ERR_OR_NULL(qp))
+ continue;
+
+ hbl_cn_qp_do_release(qp);
+ }
+
+ port_funcs->cfg_unlock(cn_port);
+ }
+
+ /* wait for the workers to complete */
+ qps_drain_async_work(hdev);
+
+ /* Verify the lists are empty */
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ port_funcs->cfg_lock(cn_port);
+
+ xa_for_each(&cn_port->qp_ids, qp_id, qp)
+ dev_err_ratelimited(hdev->dev, "Port %d QP %ld is still alive\n",
+ cn_port->port, qp_id);
+
+ port_funcs->cfg_unlock(cn_port);
+ }
+}
+
+static void user_cqs_destroy(struct hbl_cn_ctx *ctx)
+{
+ struct hbl_cn_device *hdev = ctx->hdev;
+ struct hbl_cn_properties *cn_props;
+ struct hbl_cn_user_cq *user_cq;
+ struct hbl_cn_port *cn_port;
+ unsigned long id;
+ int i;
+
+ cn_props = &hdev->cn_props;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!cn_props->force_cq && !(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ xa_for_each(&cn_port->cq_ids, id, user_cq) {
+ if (user_cq->state == USER_CQ_STATE_ALLOC)
+ hbl_cn_user_cq_put(user_cq);
+ else if (user_cq->state == USER_CQ_STATE_SET)
+ user_cq_unset_locked(user_cq, true);
+ }
+ }
+}
+
+static void wq_arrs_destroy(struct hbl_cn_ctx *ctx)
+{
+ struct hbl_cn_wq_array_properties *wq_arr_props;
+ struct hbl_cn_device *hdev = ctx->hdev;
+ struct hbl_cn_port *cn_port;
+ u32 type;
+ int i;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ wq_arr_props = cn_port->wq_arr_props;
+
+ for (type = 0; type < HBL_CNI_USER_WQ_TYPE_MAX; type++) {
+ if (wq_arr_props[type].enabled)
+ __user_wq_arr_unset(ctx, cn_port, type);
+ }
+ }
+}
+
+static void ccqs_destroy(struct hbl_cn_ctx *ctx)
+{
+ struct hbl_cn_device *hdev = ctx->hdev;
+ struct hbl_cn_port *cn_port;
+ int port;
+
+ for (port = 0; port < hdev->cn_props.max_num_of_ports; port++) {
+ if (!(hdev->ports_mask & BIT(port)))
+ continue;
+
+ cn_port = &hdev->cn_ports[port];
+ if (cn_port->ccq_enable)
+ __user_ccq_unset(hdev, ctx, port);
+ }
+}
+
+static void user_db_fifos_destroy(struct hbl_cn_ctx *ctx)
+{
+ struct hbl_cn_db_fifo_xarray_pdata *xa_pdata;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_port *cn_port;
+ struct hbl_cn_device *hdev;
+ unsigned long id;
+ int i;
+
+ hdev = ctx->hdev;
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ port_funcs->cfg_lock(cn_port);
+
+ xa_for_each(&cn_port->db_fifo_ids, id, xa_pdata)
+ if (xa_pdata->asid == ctx->asid)
+ __user_db_fifo_unset(cn_port, xa_pdata);
+
+ port_funcs->cfg_unlock(cn_port);
+ }
+}
+
+static void encap_ids_destroy(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs = hdev->asic_funcs->port_funcs;
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+ struct hbl_cn_encap_xarray_pdata *xa_pdata;
+ struct hbl_cn_port *cn_port;
+ unsigned long encap_id;
+ int i;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ port_funcs->cfg_lock(cn_port);
+
+ xa_for_each(&cn_port->encap_ids, encap_id, xa_pdata) {
+ asic_funcs->port_funcs->encap_unset(cn_port, encap_id, xa_pdata);
+
+ if (xa_pdata->encap_type != HBL_CNI_ENCAP_NONE)
+ kfree(xa_pdata->encap_header);
+
+ kfree(xa_pdata);
+ xa_erase(&cn_port->encap_ids, encap_id);
+ }
+
+ port_funcs->cfg_unlock(cn_port);
+ }
+}
+
+static void set_app_params_clear(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct hbl_cn_port *cn_port;
+ u32 max_num_of_ports, port;
+
+ asic_funcs = hdev->asic_funcs;
+ max_num_of_ports = hdev->cn_props.max_num_of_ports;
+
+ asic_funcs->app_params_clear(hdev);
+
+ for (port = 0; port < max_num_of_ports; port++) {
+ if (!(hdev->ports_mask & BIT(port)))
+ continue;
+
+ cn_port = &hdev->cn_ports[port];
+ cn_port->set_app_params = false;
+ }
+}
+
+void hbl_cn_ctx_resources_destroy(struct hbl_cn_device *hdev, struct hbl_cn_ctx *ctx)
+{
+ qps_destroy(hdev);
+ user_cqs_destroy(ctx);
+ wq_arrs_destroy(ctx);
+ ccqs_destroy(ctx);
+ user_db_fifos_destroy(ctx);
+ encap_ids_destroy(hdev);
+ set_app_params_clear(hdev);
+}
+
+int hbl_cn_alloc_ring(struct hbl_cn_device *hdev, struct hbl_cn_ring *ring, int elem_size,
+ int count)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+ int rc;
+
+ ring->count = count;
+ ring->elem_size = elem_size;
+ ring->asid = hdev->kernel_asid;
+
+ RING_BUF_SIZE(ring) = elem_size * count;
+ RING_BUF_ADDRESS(ring) = hbl_cn_dma_alloc_coherent(hdev, RING_BUF_SIZE(ring),
+ &RING_BUF_DMA_ADDRESS(ring), GFP_KERNEL);
+ if (!RING_BUF_ADDRESS(ring))
+ return -ENOMEM;
+
+ /* ring's idx_ptr shall point on pi/ci address */
+ RING_PI_SIZE(ring) = sizeof(u64);
+ RING_PI_ADDRESS(ring) = hbl_cn_dma_pool_zalloc(hdev, RING_PI_SIZE(ring),
+ GFP_KERNEL | __GFP_ZERO,
+ &RING_PI_DMA_ADDRESS(ring));
+ if (!RING_PI_ADDRESS(ring)) {
+ rc = -ENOMEM;
+ goto pi_alloc_fail;
+ }
+
+ return 0;
+
+pi_alloc_fail:
+ asic_funcs->dma_free_coherent(hdev, RING_BUF_SIZE(ring), RING_BUF_ADDRESS(ring),
+ RING_BUF_DMA_ADDRESS(ring));
+
+ return rc;
+}
+
+void hbl_cn_free_ring(struct hbl_cn_device *hdev, struct hbl_cn_ring *ring)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+
+ asic_funcs->dma_pool_free(hdev, RING_PI_ADDRESS(ring), RING_PI_DMA_ADDRESS(ring));
+
+ asic_funcs->dma_free_coherent(hdev, RING_BUF_SIZE(ring), RING_BUF_ADDRESS(ring),
+ RING_BUF_DMA_ADDRESS(ring));
+}
+
+static void hbl_cn_randomize_status_cnts(struct hbl_cn_port *cn_port,
+ struct hbl_cn_cpucp_status *status)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+
+ RAND_STAT_CNT(status->high_ber_reinit);
+ RAND_STAT_CNT(status->correctable_err_cnt);
+ RAND_STAT_CNT(status->uncorrectable_err_cnt);
+ RAND_STAT_CNT(status->bad_format_cnt);
+ RAND_STAT_CNT(status->responder_out_of_sequence_psn_cnt);
+}
+
+static void hbl_cn_get_status(struct hbl_cn_port *cn_port, struct hbl_cn_cpucp_status *status)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+
+ /* Port toggle counter should always be filled regardless of the logical state of the
+ * port.
+ */
+ status->port_toggle_cnt = hbl_cn_get_port_toggle_cnt(cn_port);
+
+ status->port = port;
+ status->up = hbl_cn_is_port_open(cn_port);
+
+ if (!status->up)
+ return;
+
+ status->pcs_link = cn_port->pcs_link;
+ status->phy_ready = cn_port->phy_fw_tuned;
+ status->auto_neg = cn_port->auto_neg_enable;
+
+ if (hdev->rand_status) {
+ hbl_cn_randomize_status_cnts(cn_port, status);
+ return;
+ }
+
+ status->high_ber_reinit = cn_port->pcs_remote_fault_reconfig_cnt;
+
+ /* Each ASIC will fill the rest of the statistics */
+ hdev->asic_funcs->port_funcs->get_status(cn_port, status);
+}
+
+static void hbl_cn_convert_cpucp_status(struct cpucp_nic_status *to,
+ struct hbl_cn_cpucp_status *from)
+{
+ to->port = cpu_to_le32(from->port);
+ to->bad_format_cnt = cpu_to_le32(from->bad_format_cnt);
+ to->responder_out_of_sequence_psn_cnt =
+ cpu_to_le32(from->responder_out_of_sequence_psn_cnt);
+ to->high_ber_reinit = cpu_to_le32(from->high_ber_reinit);
+ to->correctable_err_cnt = cpu_to_le32(from->correctable_err_cnt);
+ to->uncorrectable_err_cnt = cpu_to_le32(from->uncorrectable_err_cnt);
+ to->retraining_cnt = cpu_to_le32(from->retraining_cnt);
+ to->up = from->up;
+ to->pcs_link = from->pcs_link;
+ to->phy_ready = from->phy_ready;
+ to->auto_neg = from->auto_neg;
+ to->timeout_retransmission_cnt = cpu_to_le32(from->timeout_retransmission_cnt);
+ to->high_ber_cnt = cpu_to_le32(from->high_ber_cnt);
+ to->pre_fec_ser.integer = cpu_to_le16(from->pre_fec_ser.integer);
+ to->pre_fec_ser.exp = cpu_to_le16(from->pre_fec_ser.exp);
+ to->post_fec_ser.integer = cpu_to_le16(from->post_fec_ser.integer);
+ to->post_fec_ser.exp = cpu_to_le16(from->post_fec_ser.exp);
+ to->bandwidth.integer = cpu_to_le16(from->bandwidth.integer);
+ to->bandwidth.frac = cpu_to_le16(from->bandwidth.frac);
+ to->lat.integer = cpu_to_le16(from->lat.integer);
+ to->lat.frac = cpu_to_le16(from->lat.frac);
+ to->port_toggle_cnt = cpu_to_le32(from->port_toggle_cnt);
+}
+
+static int hbl_cn_send_cpucp_status(struct hbl_cn_device *hdev, u32 port,
+ struct hbl_cn_cpucp_status *cn_status)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct cpucp_nic_status_packet *pkt;
+ struct cpucp_nic_status status = {};
+ struct hbl_cn_properties *cn_props;
+ size_t total_pkt_size, data_size;
+ struct hbl_cn_port *cn_port;
+ u64 result;
+ int rc;
+
+ cn_props = &hdev->cn_props;
+ data_size = cn_props->status_packet_size;
+ asic_funcs = hdev->asic_funcs;
+ port_funcs = asic_funcs->port_funcs;
+ cn_port = &hdev->cn_ports[port];
+
+ total_pkt_size = sizeof(struct cpucp_nic_status_packet) + data_size;
+
+ /* data should be aligned to 8 bytes in order to CPU-CP to copy it */
+ total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
+
+ /* total_pkt_size is casted to u16 later on */
+ if (total_pkt_size > USHRT_MAX) {
+ dev_err(hdev->dev, "NIC status data is too big\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ pkt = kzalloc(total_pkt_size, GFP_KERNEL);
+ if (!pkt) {
+ rc = -ENOMEM;
+ goto out;
+ }
+
+ hbl_cn_convert_cpucp_status(&status, cn_status);
+
+ pkt->length = cpu_to_le32(data_size / sizeof(u32));
+ memcpy(&pkt->data, &status, data_size);
+
+ pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_NIC_STATUS << CPUCP_PKT_CTL_OPCODE_SHIFT);
+
+ rc = asic_funcs->send_cpu_message(hdev, (u32 *)pkt, total_pkt_size, 0, &result);
+ if (rc)
+ dev_err(hdev->dev, "failed to send NIC status, port %d\n", port);
+
+ kfree(pkt);
+out:
+ port_funcs->post_send_status(cn_port);
+
+ return rc;
+}
+
+void hbl_cn_fw_status_work(struct work_struct *work)
+{
+ struct hbl_cn_port *cn_port = container_of(work, struct hbl_cn_port, fw_status_work.work);
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_cpucp_status status = {};
+ u32 port = cn_port->port;
+ int rc;
+
+ hbl_cn_get_status(cn_port, &status);
+
+ rc = hbl_cn_send_cpucp_status(hdev, port, &status);
+ if (rc)
+ return;
+
+ if (hdev->status_cmd == HBL_CN_STATUS_PERIODIC_START)
+ queue_delayed_work(cn_port->wq, &cn_port->fw_status_work,
+ msecs_to_jiffies(hdev->status_period * 1000));
+}
+
+static void cn_port_sw_fini(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = cn_port->hdev->asic_funcs;
+
+ if (!cn_port->sw_initialized)
+ return;
+
+ cn_port->sw_initialized = false;
+
+ asic_funcs->port_funcs->port_sw_fini(cn_port);
+
+ xa_destroy(&cn_port->cq_ids);
+ xa_destroy(&cn_port->encap_ids);
+ xa_destroy(&cn_port->db_fifo_ids);
+ xa_destroy(&cn_port->qp_ids);
+
+ mutex_destroy(&cn_port->cnt_lock);
+ mutex_destroy(&cn_port->control_lock);
+
+ kfree(cn_port->reset_tracker);
+
+ destroy_workqueue(cn_port->qp_wq);
+ destroy_workqueue(cn_port->wq);
+}
+
+static void cn_wq_arr_props_init(struct hbl_cn_wq_array_properties *wq_arr_props)
+{
+ wq_arr_props[HBL_CNI_USER_WQ_SEND].type_str = "send";
+ wq_arr_props[HBL_CNI_USER_WQ_SEND].is_send = true;
+
+ wq_arr_props[HBL_CNI_USER_WQ_RECV].type_str = "recv";
+ wq_arr_props[HBL_CNI_USER_WQ_RECV].is_send = false;
+}
+
+static int cn_port_sw_init(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_wq_array_properties *wq_arr_props;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_reset_tracker *reset_tracker;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ u32 port, max_qp_error_syndromes;
+ char wq_name[32] = {0};
+ int rc;
+
+ port = cn_port->port;
+ asic_funcs = hdev->asic_funcs;
+ port_funcs = asic_funcs->port_funcs;
+ wq_arr_props = cn_port->wq_arr_props;
+ reset_tracker = NULL;
+
+ snprintf(wq_name, sizeof(wq_name) - 1, "hbl%u-cn%d-wq", hdev->id, port);
+ cn_port->wq = alloc_workqueue(wq_name, 0, 0);
+ if (!cn_port->wq) {
+ dev_err(hdev->dev, "Failed to create WQ, port: %d\n", port);
+ return -ENOMEM;
+ }
+
+ snprintf(wq_name, sizeof(wq_name) - 1, "hbl%u-cn%d-qp-wq", hdev->id, port);
+ cn_port->qp_wq = alloc_workqueue(wq_name, WQ_UNBOUND, 0);
+ if (!cn_port->qp_wq) {
+ dev_err(hdev->dev, "Failed to create QP WQ, port: %d\n", port);
+ rc = -ENOMEM;
+ goto qp_wq_err;
+ }
+
+ max_qp_error_syndromes = hdev->cn_props.max_qp_error_syndromes;
+ if (max_qp_error_syndromes) {
+ reset_tracker = kcalloc(max_qp_error_syndromes, sizeof(*reset_tracker), GFP_KERNEL);
+ if (!reset_tracker) {
+ rc = -ENOMEM;
+ goto reset_tracker_err;
+ }
+
+ cn_port->reset_tracker = reset_tracker;
+ }
+
+ mutex_init(&cn_port->control_lock);
+ mutex_init(&cn_port->cnt_lock);
+
+ xa_init_flags(&cn_port->qp_ids, XA_FLAGS_ALLOC);
+ xa_init_flags(&cn_port->db_fifo_ids, XA_FLAGS_ALLOC);
+ xa_init_flags(&cn_port->encap_ids, XA_FLAGS_ALLOC);
+ xa_init_flags(&cn_port->cq_ids, XA_FLAGS_ALLOC);
+
+ INIT_DELAYED_WORK(&cn_port->link_status_work, port_funcs->phy_link_status_work);
+
+ cn_port->speed = asic_funcs->get_default_port_speed(hdev);
+ cn_port->pfc_enable = true;
+ cn_port->pflags = PFLAGS_PCS_LINK_CHECK | PFLAGS_PHY_AUTO_NEG_LPBK;
+
+ cn_wq_arr_props_init(wq_arr_props);
+
+ rc = port_funcs->port_sw_init(cn_port);
+ if (rc)
+ goto sw_init_err;
+
+ cn_port->sw_initialized = true;
+
+ return 0;
+
+sw_init_err:
+ xa_destroy(&cn_port->cq_ids);
+ xa_destroy(&cn_port->encap_ids);
+ xa_destroy(&cn_port->db_fifo_ids);
+ xa_destroy(&cn_port->qp_ids);
+
+ mutex_destroy(&cn_port->cnt_lock);
+ mutex_destroy(&cn_port->control_lock);
+
+ if (max_qp_error_syndromes)
+ kfree(reset_tracker);
+reset_tracker_err:
+ destroy_workqueue(cn_port->qp_wq);
+qp_wq_err:
+ destroy_workqueue(cn_port->wq);
+
+ return rc;
+}
+
+static int cn_macro_sw_init(struct hbl_cn_macro *cn_macro)
+{
+ struct hbl_cn_asic_funcs *asic_funcs;
+
+ asic_funcs = cn_macro->hdev->asic_funcs;
+
+ return asic_funcs->macro_sw_init(cn_macro);
+}
+
+static void cn_macro_sw_fini(struct hbl_cn_macro *cn_macro)
+{
+ struct hbl_cn_asic_funcs *asic_funcs;
+
+ asic_funcs = cn_macro->hdev->asic_funcs;
+
+ asic_funcs->macro_sw_fini(cn_macro);
+}
+
+static void hbl_cn_sw_fini(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+ int i;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++)
+ cn_port_sw_fini(&hdev->cn_ports[i]);
+
+ for (i = 0; i < hdev->cn_props.num_of_macros; i++)
+ cn_macro_sw_fini(&hdev->cn_macros[i]);
+
+ asic_funcs->sw_fini(hdev);
+
+ kfree(hdev->ib_aux_dev.aux_data);
+ kfree(hdev->ib_aux_dev.aux_ops);
+ kfree(hdev->en_aux_dev.aux_data);
+ kfree(hdev->en_aux_dev.aux_ops);
+ kfree(hdev->mac_lane_remap);
+ kfree(hdev->phy_ber_info);
+ kfree(hdev->phy_tx_taps);
+ kfree(hdev->cn_macros);
+ kfree(hdev->cn_ports);
+}
+
+static int hbl_cn_sw_init(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+ struct hbl_cn_macro *cn_macro, *cn_macros;
+ int rc, i, macro_cnt = 0, port_cnt = 0;
+ struct hbl_cn_port *cn_port, *cn_ports;
+ struct hbl_en_aux_data *en_aux_data;
+ struct hbl_ib_aux_data *ib_aux_data;
+ struct hbl_en_aux_ops *en_aux_ops;
+ struct hbl_ib_aux_ops *ib_aux_ops;
+ struct hbl_cn_ber_info *ber_info;
+ struct hbl_cn_tx_taps *tx_taps;
+ u32 *mac_lane_remap;
+
+ asic_funcs->pre_sw_init(hdev);
+
+ /* Allocate per port common structure array */
+ cn_ports = kcalloc(hdev->cn_props.max_num_of_ports, sizeof(*cn_ports), GFP_KERNEL);
+ if (!cn_ports)
+ return -ENOMEM;
+
+ /* Allocate per macro common structure array */
+ cn_macros = kcalloc(hdev->cn_props.num_of_macros, sizeof(*cn_macros), GFP_KERNEL);
+ if (!cn_macros) {
+ rc = -ENOMEM;
+ goto macro_alloc_fail;
+ }
+
+ tx_taps = kcalloc(hdev->cn_props.max_num_of_lanes, sizeof(*tx_taps), GFP_KERNEL);
+ if (!tx_taps) {
+ rc = -ENOMEM;
+ goto taps_alloc_fail;
+ }
+
+ ber_info = kcalloc(hdev->cn_props.max_num_of_lanes, sizeof(*ber_info), GFP_KERNEL);
+ if (!ber_info) {
+ rc = -ENOMEM;
+ goto ber_info_alloc_fail;
+ }
+
+ mac_lane_remap = kcalloc(hdev->cn_props.num_of_macros, sizeof(*mac_lane_remap),
+ GFP_KERNEL);
+ if (!mac_lane_remap) {
+ rc = -ENOMEM;
+ goto mac_remap_alloc_fail;
+ }
+
+ en_aux_data = kzalloc(sizeof(*en_aux_data), GFP_KERNEL);
+ if (!en_aux_data) {
+ rc = -ENOMEM;
+ goto en_aux_data_alloc_fail;
+ }
+
+ en_aux_ops = kzalloc(sizeof(*en_aux_ops), GFP_KERNEL);
+ if (!en_aux_ops) {
+ rc = -ENOMEM;
+ goto en_aux_ops_alloc_fail;
+ }
+
+ ib_aux_data = kzalloc(sizeof(*ib_aux_data), GFP_KERNEL);
+ if (!ib_aux_data) {
+ rc = -ENOMEM;
+ goto ib_aux_data_alloc_fail;
+ }
+
+ ib_aux_ops = kzalloc(sizeof(*ib_aux_ops), GFP_KERNEL);
+ if (!ib_aux_ops) {
+ rc = -ENOMEM;
+ goto ib_aux_ops_alloc_fail;
+ }
+
+ hdev->en_aux_dev.aux_data = en_aux_data;
+ hdev->en_aux_dev.aux_ops = en_aux_ops;
+ hdev->ib_aux_dev.aux_data = ib_aux_data;
+ hdev->ib_aux_dev.aux_ops = ib_aux_ops;
+
+ hdev->phy_tx_taps = tx_taps;
+ hdev->phy_ber_info = ber_info;
+ hdev->mac_lane_remap = mac_lane_remap;
+ hdev->phy_config_fw = !hdev->pldm && !hdev->skip_phy_init;
+ hdev->mmu_bypass = true;
+ hdev->phy_calc_ber_wait_sec = 30;
+
+ rc = asic_funcs->sw_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "ASIC SW init failed\n");
+ goto sw_init_fail;
+ }
+
+ hdev->cn_ports = cn_ports;
+ hdev->cn_macros = cn_macros;
+ for (i = 0; i < hdev->cn_props.num_of_macros; i++, macro_cnt++) {
+ cn_macro = &hdev->cn_macros[i];
+
+ cn_macro->hdev = hdev;
+ cn_macro->idx = i;
+
+ rc = cn_macro_sw_init(cn_macro);
+ if (rc) {
+ dev_err(hdev->dev, "Macro %d SW init failed\n", i);
+ goto macro_init_fail;
+ }
+ }
+
+ /* At this stage, we don't know how many ports we have, so we must
+ * allocate for the maximum number of ports (and also free all of them
+ * in sw_fini)
+ */
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++, port_cnt++) {
+ cn_port = &hdev->cn_ports[i];
+ cn_port->hdev = hdev;
+ cn_port->port = i;
+ atomic_set(&cn_port->num_of_allocated_qps, 0);
+ rc = cn_port_sw_init(cn_port);
+ if (rc) {
+ dev_err(hdev->dev, "S/W init failed, port %d\n", i);
+ goto port_init_fail;
+ }
+ }
+
+ return 0;
+
+port_init_fail:
+ for (i = 0; i < port_cnt; i++)
+ cn_port_sw_fini(&hdev->cn_ports[i]);
+
+macro_init_fail:
+ for (i = 0; i < macro_cnt; i++)
+ cn_macro_sw_fini(&hdev->cn_macros[i]);
+
+ asic_funcs->sw_fini(hdev);
+sw_init_fail:
+ kfree(ib_aux_ops);
+ib_aux_ops_alloc_fail:
+ kfree(ib_aux_data);
+ib_aux_data_alloc_fail:
+ kfree(en_aux_ops);
+en_aux_ops_alloc_fail:
+ kfree(en_aux_data);
+en_aux_data_alloc_fail:
+ kfree(mac_lane_remap);
+mac_remap_alloc_fail:
+ kfree(ber_info);
+ber_info_alloc_fail:
+ kfree(tx_taps);
+taps_alloc_fail:
+ kfree(cn_macros);
+macro_alloc_fail:
+ kfree(cn_ports);
+
+ return rc;
+}
+
+static void hbl_cn_late_init(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ /* compute2cn */
+ aux_ops->ports_reopen = hbl_cn_ports_reopen;
+ aux_ops->ports_stop_prepare = hbl_cn_hard_reset_prepare;
+ aux_ops->ports_stop = hbl_cn_stop;
+ aux_ops->synchronize_irqs = hbl_cn_synchronize_irqs;
+
+ hdev->asic_funcs->late_init(hdev);
+}
+
+static void hbl_cn_late_fini(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ /* compute2cn */
+ aux_ops->ports_reopen = NULL;
+ aux_ops->ports_stop_prepare = NULL;
+ aux_ops->ports_stop = NULL;
+ aux_ops->synchronize_irqs = NULL;
+
+ hdev->asic_funcs->late_fini(hdev);
+}
+
+bool hbl_cn_is_port_open(struct hbl_cn_port *cn_port)
+{
+ struct hbl_aux_dev *aux_dev = &cn_port->hdev->en_aux_dev;
+ struct hbl_en_aux_ops *aux_ops = aux_dev->aux_ops;
+ u32 port = cn_port->port;
+
+ if (cn_port->eth_enable && aux_ops->is_port_open)
+ return aux_ops->is_port_open(aux_dev, port);
+
+ return cn_port->port_open;
+}
+
+u32 hbl_cn_get_pflags(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port = cn_port->port;
+
+ aux_dev = &hdev->en_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ if (cn_port->eth_enable && aux_ops->get_pflags)
+ return aux_ops->get_pflags(aux_dev, port);
+
+ return cn_port->pflags;
+}
+
+u8 hbl_cn_get_num_of_digits(u64 num)
+{
+ u8 n_digits = 0;
+
+ while (num) {
+ n_digits++;
+ num /= 10;
+ }
+
+ return n_digits;
+}
+
+static void hbl_cn_spmu_init(struct hbl_cn_port *cn_port, bool full)
+{
+ u32 spmu_events[NIC_SPMU_STATS_LEN_MAX], num_event_types, port = cn_port->port;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_stat *event_types;
+ int rc, i;
+
+ if (!hdev->supports_coresight)
+ return;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ port_funcs->spmu_get_stats_info(cn_port, &event_types, &num_event_types);
+ num_event_types = min_t(u32, num_event_types, NIC_SPMU_STATS_LEN_MAX);
+
+ for (i = 0; i < num_event_types; i++)
+ spmu_events[i] = event_types[i].lo_offset;
+
+ if (full) {
+ rc = port_funcs->spmu_config(cn_port, num_event_types, spmu_events, false);
+ if (rc)
+ dev_err(hdev->dev, "Failed to disable spmu for port %d\n", port);
+ }
+
+ rc = port_funcs->spmu_config(cn_port, num_event_types, spmu_events, true);
+ if (rc)
+ dev_err(hdev->dev, "Failed to enable spmu for port %d\n", port);
+}
+
+static void hbl_cn_reset_stats_counters_port(struct hbl_cn_device *hdev, u32 port)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_cn_port *cn_port;
+ struct hbl_aux_dev *aux_dev;
+
+ cn_port = &hdev->cn_ports[port];
+ aux_dev = &hdev->en_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ /* Ethernet */
+ if (cn_port->eth_enable && aux_ops->reset_stats)
+ aux_ops->reset_stats(aux_dev, port);
+
+ /* MAC */
+ port_funcs->reset_mac_stats(cn_port);
+
+ /* SPMU */
+ hbl_cn_spmu_init(cn_port, true);
+
+ /* XPCS91 */
+ cn_port->correctable_errors_cnt = 0;
+ cn_port->uncorrectable_errors_cnt = 0;
+
+ /* PCS */
+ cn_port->pcs_local_fault_cnt = 0;
+ cn_port->pcs_remote_fault_cnt = 0;
+ cn_port->pcs_remote_fault_reconfig_cnt = 0;
+ cn_port->pcs_link_restore_cnt = 0;
+
+ /* Congestion Queue */
+ cn_port->cong_q_err_cnt = 0;
+}
+
+void hbl_cn_reset_stats_counters(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_port *cn_port;
+ u32 port;
+ int i;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ if (!hbl_cn_is_port_open(cn_port))
+ continue;
+
+ port = cn_port->port;
+
+ hbl_cn_reset_stats_counters_port(hdev, port);
+ }
+}
+
+void hbl_cn_reset_ports_toggle_counters(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_port *cn_port;
+ int i;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ cn_port->port_toggle_cnt = 0;
+ cn_port->port_toggle_cnt_prev = 0;
+ }
+}
+
+/* The following implements the events dispatcher
+ * Each application registering with the device is assigned a unique ASID
+ * by the driver, it is also being associated with a SW-EQ by the dispatcher
+ * (The Eth driver is handled by the kernel associated with ASID 0).
+ * during the lifetime of the app/ASID, each resource allocated to it
+ * that can generate events (such as QP and CQ) is being associated by the
+ * dispatcher the appropriate ASID.
+ * During the course of work of the NIC, the HW EQ is accessed
+ * (by poling or interrupt), and for each event found in it
+ * - The resource ID which generated the event is retrieved from it (CQ# or QP#)
+ * - The ASID it retrieved from the ASID-resource association lists,
+ * - The event is inserted to the ASID-specific SW-EQ to be retrieved later on
+ * by the app. An exception is the Eth driver which as for today is tightly
+ * coupled with the EQ so the dispatcher calls the Eth event handling routine
+ * (if registered) immediately after dispatching the events to the SW-EQs.
+ * Note: The Link events which are always handled by the Eth driver (ASID 0).
+ */
+
+struct hbl_cn_ev_dq *hbl_cn_cqn_to_dq(struct hbl_cn_ev_dqs *ev_dqs, u32 cqn,
+ struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_properties *cn_prop = &hdev->cn_props;
+ struct hbl_cn_ev_dq *dq;
+
+ if (cqn >= cn_prop->max_cqs)
+ return NULL;
+
+ dq = ev_dqs->cq_dq[cqn];
+ if (!dq || !dq->associated)
+ return NULL;
+
+ return dq;
+}
+
+struct hbl_cn_ev_dq *hbl_cn_ccqn_to_dq(struct hbl_cn_ev_dqs *ev_dqs, u32 ccqn,
+ struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_properties *cn_prop = &hdev->cn_props;
+ struct hbl_cn_ev_dq *dq;
+
+ if (ccqn >= cn_prop->max_ccqs)
+ return NULL;
+
+ dq = ev_dqs->ccq_dq[ccqn];
+ if (!dq || !dq->associated)
+ return NULL;
+
+ return dq;
+}
+
+struct hbl_cn_dq_qp_info *hbl_cn_get_qp_info(struct hbl_cn_ev_dqs *ev_dqs, u32 qpn)
+{
+ struct hbl_cn_dq_qp_info *qp_info = NULL;
+
+ hash_for_each_possible(ev_dqs->qps, qp_info, node, qpn)
+ if (qpn == qp_info->qpn)
+ return qp_info;
+
+ return NULL;
+}
+
+struct hbl_cn_ev_dq *hbl_cn_qpn_to_dq(struct hbl_cn_ev_dqs *ev_dqs, u32 qpn)
+{
+ struct hbl_cn_dq_qp_info *qp_info = hbl_cn_get_qp_info(ev_dqs, qpn);
+
+ if (qp_info)
+ return qp_info->dq;
+
+ return NULL;
+}
+
+struct hbl_cn_ev_dq *hbl_cn_dbn_to_dq(struct hbl_cn_ev_dqs *ev_dqs, u32 dbn,
+ struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_properties *cn_prop = &hdev->cn_props;
+ struct hbl_cn_ev_dq *dq;
+
+ if (dbn >= cn_prop->max_db_fifos)
+ return NULL;
+
+ dq = ev_dqs->db_dq[dbn];
+ if (!dq || !dq->associated)
+ return NULL;
+
+ return dq;
+}
+
+struct hbl_cn_ev_dq *hbl_cn_asid_to_dq(struct hbl_cn_ev_dqs *ev_dqs, u32 asid)
+{
+ struct hbl_cn_ev_dq *dq;
+ int i;
+
+ for (i = 0; i < NIC_NUM_CONCUR_ASIDS; i++) {
+ dq = &ev_dqs->edq[i];
+ if (dq->associated && dq->asid == asid)
+ return dq;
+ }
+
+ return NULL;
+}
+
+static void hbl_cn_dq_reset(struct hbl_cn_ev_dq *dq)
+{
+ struct hbl_cn_eq_raw_buf *buf = &dq->buf;
+
+ dq->overflow = 0;
+ buf->tail = 0;
+ buf->head = buf->tail;
+ buf->events_count = 0;
+ memset(buf->events, 0, sizeof(buf->events));
+}
+
+bool hbl_cn_eq_dispatcher_is_empty(struct hbl_cn_ev_dq *dq)
+{
+ return (dq->buf.events_count == 0);
+}
+
+bool hbl_cn_eq_dispatcher_is_full(struct hbl_cn_ev_dq *dq)
+{
+ return (dq->buf.events_count == (NIC_EQ_INFO_BUF_SIZE - 1));
+}
+
+void hbl_cn_eq_dispatcher_init(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ int i;
+
+ hash_init(ev_dqs->qps);
+ mutex_init(&ev_dqs->lock);
+
+ hbl_cn_dq_reset(&ev_dqs->default_edq);
+
+ for (i = 0; i < NIC_NUM_CONCUR_ASIDS; i++)
+ hbl_cn_dq_reset(&ev_dqs->edq[i]);
+
+ for (i = 0; i < NIC_DRV_MAX_CQS_NUM; i++)
+ ev_dqs->cq_dq[i] = NULL;
+
+ for (i = 0; i < NIC_DRV_NUM_DB_FIFOS; i++)
+ ev_dqs->db_dq[i] = NULL;
+}
+
+void hbl_cn_eq_dispatcher_fini(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_ev_dqs *edqs = ev_dqs;
+ struct hbl_cn_dq_qp_info *qp_info;
+ u32 port = cn_port->port;
+ struct hlist_node *tmp;
+ int i;
+
+ if (!hash_empty(edqs->qps))
+ dev_err(hdev->dev, "port %d dispatcher is closed while there are QPs in use\n",
+ port);
+
+ hash_for_each_safe(edqs->qps, i, tmp, qp_info, node) {
+ dev_err_ratelimited(hdev->dev, "port %d QP %d was not destroyed\n", port,
+ qp_info->qpn);
+ hash_del(&qp_info->node);
+ kfree(qp_info);
+ }
+
+ mutex_destroy(&ev_dqs->lock);
+}
+
+void hbl_cn_eq_dispatcher_reset(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ struct hbl_cn_ev_dqs *edqs = ev_dqs;
+ int i;
+
+ mutex_lock(&edqs->lock);
+
+ hbl_cn_dq_reset(&edqs->default_edq);
+
+ for (i = 0; i < NIC_NUM_CONCUR_ASIDS; i++)
+ hbl_cn_dq_reset(&edqs->edq[i]);
+
+ mutex_unlock(&edqs->lock);
+}
+
+int hbl_cn_eq_dispatcher_associate_dq(struct hbl_cn_port *cn_port, u32 asid)
+{
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ struct hbl_cn_ev_dq *dq;
+ int i, rc = -ENOSPC;
+
+ mutex_lock(&ev_dqs->lock);
+
+ dq = hbl_cn_asid_to_dq(ev_dqs, asid);
+ if (dq) {
+ rc = 0;
+ goto exit;
+ }
+
+ for (i = 0; i < NIC_NUM_CONCUR_ASIDS; i++) {
+ dq = &ev_dqs->edq[i];
+ if (!dq->associated) {
+ dq->associated = true;
+ dq->asid = asid;
+ rc = 0;
+ break;
+ }
+ }
+
+exit:
+ mutex_unlock(&ev_dqs->lock);
+
+ return rc;
+}
+
+int hbl_cn_eq_dispatcher_dissociate_dq(struct hbl_cn_port *cn_port, u32 asid)
+{
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ struct hbl_cn_ev_dq *dq;
+
+ mutex_lock(&ev_dqs->lock);
+
+ dq = hbl_cn_asid_to_dq(ev_dqs, asid);
+ if (!dq)
+ goto exit;
+
+ hbl_cn_dq_reset(dq);
+ dq->associated = false;
+ dq->asid = U32_MAX;
+
+exit:
+ mutex_unlock(&ev_dqs->lock);
+
+ return 0;
+}
+
+int hbl_cn_eq_dispatcher_register_qp(struct hbl_cn_port *cn_port, u32 asid, u32 qp_id)
+{
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ struct hbl_cn_dq_qp_info *qp_info;
+ struct hbl_cn_ev_dq *dq;
+ int rc = 0;
+
+ mutex_lock(&ev_dqs->lock);
+
+ /* check if such qp is already registered and if with the same asid */
+ dq = hbl_cn_qpn_to_dq(ev_dqs, qp_id);
+ if (dq) {
+ if (dq->asid != asid)
+ rc = -EINVAL;
+
+ goto exit;
+ }
+
+ /* find the dq associated with the given asid */
+ dq = hbl_cn_asid_to_dq(ev_dqs, asid);
+ if (!dq) {
+ rc = -ENODATA;
+ goto exit;
+ }
+
+ /* register the QP */
+ qp_info = kmalloc(sizeof(*qp_info), GFP_KERNEL);
+ if (!qp_info) {
+ rc = -ENOMEM;
+ goto exit;
+ }
+
+ qp_info->dq = dq;
+ qp_info->qpn = qp_id;
+ hash_add(ev_dqs->qps, &qp_info->node, qp_id);
+
+exit:
+ mutex_unlock(&ev_dqs->lock);
+
+ return rc;
+}
+
+int hbl_cn_eq_dispatcher_unregister_qp(struct hbl_cn_port *cn_port, u32 qp_id)
+{
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ struct hbl_cn_dq_qp_info *qp_info;
+
+ mutex_lock(&ev_dqs->lock);
+
+ qp_info = hbl_cn_get_qp_info(ev_dqs, qp_id);
+ if (qp_info) {
+ hash_del(&qp_info->node);
+ kfree(qp_info);
+ }
+
+ mutex_unlock(&ev_dqs->lock);
+
+ return 0;
+}
+
+int hbl_cn_eq_dispatcher_register_cq(struct hbl_cn_port *cn_port, u32 asid, u32 cqn)
+{
+ struct hbl_cn_properties *cn_prop = &cn_port->hdev->cn_props;
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ struct hbl_cn_ev_dq *dq;
+ int rc = 0;
+
+ if (cqn >= cn_prop->max_cqs)
+ return -EINVAL;
+
+ mutex_lock(&ev_dqs->lock);
+
+ /* check if such qp is already registered and if with the same
+ * asid
+ */
+ dq = ev_dqs->cq_dq[cqn];
+ if (dq) {
+ if (dq->asid != asid)
+ rc = -EINVAL;
+
+ goto exit;
+ }
+
+ /* find the dq associated with the given asid */
+ dq = hbl_cn_asid_to_dq(ev_dqs, asid);
+ if (!dq) {
+ rc = -ENODATA;
+ goto exit;
+ }
+
+ ev_dqs->cq_dq[cqn] = dq;
+
+exit:
+ mutex_unlock(&ev_dqs->lock);
+
+ return rc;
+}
+
+int hbl_cn_eq_dispatcher_unregister_cq(struct hbl_cn_port *cn_port, u32 cqn)
+{
+ struct hbl_cn_properties *cn_prop = &cn_port->hdev->cn_props;
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+
+ if (cqn >= cn_prop->max_cqs)
+ return -EINVAL;
+
+ mutex_lock(&ev_dqs->lock);
+
+ ev_dqs->cq_dq[cqn] = NULL;
+
+ mutex_unlock(&ev_dqs->lock);
+
+ return 0;
+}
+
+int hbl_cn_eq_dispatcher_register_ccq(struct hbl_cn_port *cn_port, u32 asid, u32 ccqn)
+{
+ struct hbl_cn_properties *cn_prop = &cn_port->hdev->cn_props;
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ struct hbl_cn_ev_dq *dq;
+ int rc = 0;
+
+ if (ccqn >= cn_prop->max_ccqs)
+ return -EINVAL;
+
+ mutex_lock(&ev_dqs->lock);
+
+ /* check if such qp is already registered and if with the same asid */
+ dq = ev_dqs->ccq_dq[ccqn];
+ if (dq) {
+ rc = -EINVAL;
+ goto exit;
+ }
+
+ /* find the dq associated with the given asid */
+ dq = hbl_cn_asid_to_dq(ev_dqs, asid);
+ if (!dq) {
+ rc = -ENODATA;
+ goto exit;
+ }
+
+ ev_dqs->ccq_dq[ccqn] = dq;
+
+exit:
+ mutex_unlock(&ev_dqs->lock);
+ return rc;
+}
+
+int hbl_cn_eq_dispatcher_unregister_ccq(struct hbl_cn_port *cn_port, u32 asid, u32 ccqn)
+{
+ struct hbl_cn_properties *cn_prop = &cn_port->hdev->cn_props;
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+
+ if (ccqn >= cn_prop->max_ccqs)
+ return -EINVAL;
+
+ if (!hbl_cn_asid_to_dq(ev_dqs, asid))
+ return -ENODATA;
+
+ mutex_lock(&ev_dqs->lock);
+
+ ev_dqs->ccq_dq[ccqn] = NULL;
+
+ mutex_unlock(&ev_dqs->lock);
+
+ return 0;
+}
+
+int hbl_cn_eq_dispatcher_register_db(struct hbl_cn_port *cn_port, u32 asid, u32 dbn)
+{
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ struct hbl_cn_ev_dq *dq;
+ u32 min, max;
+ int rc = 0;
+
+ cn_port->hdev->asic_funcs->port_funcs->get_db_fifo_hw_id_range(cn_port, &min, &max);
+ if (dbn < min || dbn > max) {
+ dev_err(cn_port->hdev->dev,
+ "Failed to register dbn %u to the dispatcher (valid range %u-%u)\n", dbn,
+ min, max);
+ return -EINVAL;
+ }
+
+ mutex_lock(&ev_dqs->lock);
+
+ /* check if doorbell is already registered and if so is it with the same
+ * asid
+ */
+ dq = ev_dqs->db_dq[dbn];
+ if (dq) {
+ if (dq->asid != asid)
+ rc = -EINVAL;
+
+ goto exit;
+ }
+
+ /* find the dq associated with the given asid and transport */
+ dq = hbl_cn_asid_to_dq(ev_dqs, asid);
+ if (!dq) {
+ rc = -ENODATA;
+ goto exit;
+ }
+
+ ev_dqs->db_dq[dbn] = dq;
+
+exit:
+ mutex_unlock(&ev_dqs->lock);
+
+ return rc;
+}
+
+int hbl_cn_eq_dispatcher_unregister_db(struct hbl_cn_port *cn_port, u32 dbn)
+{
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ u32 min, max;
+
+ cn_port->hdev->asic_funcs->port_funcs->get_db_fifo_hw_id_range(cn_port, &min, &max);
+ if (dbn < min || dbn > max) {
+ dev_err(cn_port->hdev->dev,
+ "Failed to unregister dbn %u from the dispatcher (valid range %u-%u)\n",
+ dbn, min, max);
+ return -EINVAL;
+ }
+
+ mutex_lock(&ev_dqs->lock);
+
+ ev_dqs->db_dq[dbn] = NULL;
+
+ mutex_unlock(&ev_dqs->lock);
+
+ return 0;
+}
+
+static int __hbl_cn_eq_dispatcher_enqueue(struct hbl_cn_port *cn_port, struct hbl_cn_ev_dq *dq,
+ const struct hbl_cn_eqe *eqe)
+{
+ struct hbl_aux_dev *aux_dev = &cn_port->hdev->ib_aux_dev;
+ struct hbl_ib_aux_ops *aux_ops = aux_dev->aux_ops;
+
+ if (hbl_cn_eq_dispatcher_is_full(dq)) {
+ dq->overflow++;
+ return -ENOSPC;
+ }
+
+ memcpy(&dq->buf.events[dq->buf.head], eqe, min(sizeof(*eqe), sizeof(dq->buf.events[0])));
+ dq->buf.head = (dq->buf.head + 1) & (NIC_EQ_INFO_BUF_SIZE - 1);
+ dq->buf.events_count++;
+
+ /* If IB device exist, call work scheduler for hbl to poll eq */
+ if (aux_ops->eqe_work_schd)
+ aux_ops->eqe_work_schd(aux_dev, cn_port->port);
+
+ return 0;
+}
+
+/* Broadcast event to all user ASIDs */
+int hbl_cn_eq_dispatcher_enqueue_bcast(struct hbl_cn_port *cn_port, const struct hbl_cn_eqe *eqe)
+{
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_ev_dq *dq;
+ int i, rc = 0;
+
+ if (!hbl_cn_is_port_open(cn_port))
+ return 0;
+
+ mutex_lock(&ev_dqs->lock);
+
+ for (i = 0; i < NIC_NUM_CONCUR_ASIDS; i++) {
+ if (i == hdev->kernel_asid)
+ continue;
+
+ dq = hbl_cn_asid_to_dq(ev_dqs, i);
+ if (!dq)
+ continue;
+
+ rc = __hbl_cn_eq_dispatcher_enqueue(cn_port, dq, eqe);
+ if (rc) {
+ dev_dbg_ratelimited(cn_port->hdev->dev,
+ "Port %d, failed to enqueue dispatcher for ASID %d. %d\n",
+ cn_port->port, i, rc);
+ break;
+ }
+ }
+
+ mutex_unlock(&ev_dqs->lock);
+
+ return rc;
+}
+
+int hbl_cn_eq_dispatcher_enqueue(struct hbl_cn_port *cn_port, const struct hbl_cn_eqe *eqe)
+{
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_ev_dq *dq;
+ int rc;
+
+ if (!hbl_cn_is_port_open(cn_port))
+ return 0;
+
+ port_funcs = cn_port->hdev->asic_funcs->port_funcs;
+
+ mutex_lock(&ev_dqs->lock);
+
+ dq = port_funcs->eq_dispatcher_select_dq(cn_port, eqe);
+ if (!dq) {
+ rc = -ENODATA;
+ goto exit;
+ }
+
+ rc = __hbl_cn_eq_dispatcher_enqueue(cn_port, dq, eqe);
+ if (rc)
+ dev_dbg_ratelimited(cn_port->hdev->dev,
+ "Port %d, failed to enqueue dispatcher. %d\n", cn_port->port,
+ rc);
+
+exit:
+ mutex_unlock(&ev_dqs->lock);
+ return rc;
+}
+
+int hbl_cn_eq_dispatcher_dequeue(struct hbl_cn_port *cn_port, u32 asid, struct hbl_cn_eqe *eqe,
+ bool is_default)
+{
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ struct hbl_cn_ev_dq *dq;
+ int rc;
+
+ mutex_lock(&ev_dqs->lock);
+
+ if (is_default)
+ dq = &ev_dqs->default_edq;
+ else
+ dq = hbl_cn_asid_to_dq(ev_dqs, asid);
+
+ if (!dq) {
+ rc = -ESRCH;
+ goto exit;
+ }
+
+ if (hbl_cn_eq_dispatcher_is_empty(dq)) {
+ rc = -ENODATA;
+ goto exit;
+ }
+
+ /* We do a copy here instead of returning a pointer since a reset or
+ * destroy operation may occur after we return from the routine
+ */
+ memcpy(eqe, &dq->buf.events[dq->buf.tail], min(sizeof(*eqe), sizeof(dq->buf.events[0])));
+
+ dq->buf.tail = (dq->buf.tail + 1) & (NIC_EQ_INFO_BUF_SIZE - 1);
+ dq->buf.events_count--;
+ rc = 0;
+
+exit:
+ mutex_unlock(&ev_dqs->lock);
+ return rc;
+}
+
+u32 hbl_cn_dram_readl(struct hbl_cn_device *hdev, u64 addr)
+{
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ return aux_ops->dram_readl(aux_dev, addr);
+}
+
+void hbl_cn_dram_writel(struct hbl_cn_device *hdev, u32 val, u64 addr)
+{
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ aux_ops->dram_writel(aux_dev, val, addr);
+}
+
+u32 hbl_cn_rreg(struct hbl_cn_device *hdev, u32 reg)
+{
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ return aux_ops->rreg(aux_dev, reg);
+}
+
+void hbl_cn_wreg(struct hbl_cn_device *hdev, u32 reg, u32 val)
+{
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ return aux_ops->wreg(aux_dev, reg, val);
+}
+
+int hbl_cn_reserve_wq_dva(struct hbl_cn_ctx *ctx, struct hbl_cn_port *cn_port, u64 wq_arr_size,
+ u32 type, u64 *dva)
+{
+ struct hbl_cn_wq_array_properties *wq_arr_props;
+ int rc;
+
+ /* The Device VA block for WQ array is just reserved here. It will be backed by host
+ * physical pages once the MMU mapping is done via hbl_map_vmalloc_range inside the
+ * alloc_and_map_wq. Using host page alignment ensures we start with offset 0, both
+ * on host and device side.
+ */
+ rc = hbl_cn_reserve_dva_block(ctx, wq_arr_size, dva);
+ if (rc)
+ return rc;
+
+ wq_arr_props = &cn_port->wq_arr_props[type];
+
+ wq_arr_props->dva_base = *dva;
+ wq_arr_props->dva_size = wq_arr_size;
+
+ return 0;
+}
+
+void hbl_cn_unreserve_wq_dva(struct hbl_cn_ctx *ctx, struct hbl_cn_port *cn_port, u32 type)
+{
+ struct hbl_cn_wq_array_properties *wq_arr_props = &cn_port->wq_arr_props[type];
+
+ hbl_cn_unreserve_dva_block(ctx, wq_arr_props->dva_base, wq_arr_props->dva_size);
+ wq_arr_props->dva_base = 0;
+}
+
+void hbl_cn_track_port_reset(struct hbl_cn_port *cn_port, u32 syndrome)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_reset_tracker *reset_tracker;
+ unsigned long timestamp_jiffies = jiffies;
+ u32 max_qp_error_syndromes;
+
+ max_qp_error_syndromes = hdev->cn_props.max_qp_error_syndromes;
+ if (syndrome >= max_qp_error_syndromes) {
+ dev_dbg(hdev->dev, "Invalid syndrome %u\n", syndrome);
+ return;
+ }
+
+ reset_tracker = &cn_port->reset_tracker[syndrome];
+
+ /* In case the timeout passed, reset the tracker parameters and return */
+ if (time_after_eq(timestamp_jiffies, reset_tracker->timeout_jiffies)) {
+ reset_tracker->num_seq_resets = 1;
+ reset_tracker->timeout_jiffies = timestamp_jiffies +
+ msecs_to_jiffies(NIC_SEQ_RESETS_TIMEOUT_MS);
+ return;
+ }
+
+ reset_tracker->num_seq_resets++;
+
+ /* In case the max sequential resets was reached before we passed the timeout,
+ * disable that port.
+ */
+ if (reset_tracker->num_seq_resets == NIC_MAX_SEQ_RESETS) {
+ dev_err(hdev->dev,
+ "Disabling port %u due to %d sequential resets, syndrome %u\n",
+ cn_port->port, NIC_MAX_SEQ_RESETS, syndrome);
+ cn_port->disabled = true;
+ }
+}
+
+void hbl_cn_eq_handler(struct hbl_cn_port *cn_port)
+{
+ struct hbl_en_aux_ops *en_aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_cn_device *hdev;
+ struct hbl_cn_eqe eqe;
+ u32 port;
+
+ if (!cn_port->eq_handler_enable)
+ return;
+
+ hdev = cn_port->hdev;
+ aux_dev = &hdev->en_aux_dev;
+ en_aux_ops = aux_dev->aux_ops;
+ port = cn_port->port;
+
+ mutex_lock(&cn_port->control_lock);
+
+ if (!hbl_cn_is_port_open(cn_port)) {
+ dev_dbg(hdev->dev, "ignoring events while port %d closed", port);
+ goto out;
+ }
+
+ if (en_aux_ops->handle_eqe)
+ while (!hbl_cn_eq_dispatcher_dequeue(cn_port, hdev->kernel_asid, &eqe, false))
+ en_aux_ops->handle_eqe(aux_dev, port, &eqe);
+
+out:
+ mutex_unlock(&cn_port->control_lock);
+}
+
+void hbl_cn_get_self_hw_block_handle(struct hbl_cn_device *hdev, u64 address, u64 *handle)
+{
+ *handle = lower_32_bits(address) | (HBL_CN_MMAP_TYPE_BLOCK);
+ *handle <<= PAGE_SHIFT;
+}
+
+u32 hbl_cn_hw_block_handle_to_addr32(struct hbl_cn_device *hdev, u64 handle)
+{
+ return lower_32_bits(handle >> PAGE_SHIFT);
+}
+
+void *__hbl_cn_dma_alloc_coherent(struct hbl_cn_device *hdev, size_t size, dma_addr_t *dma_handle,
+ gfp_t flag, const char *caller)
+{
+ const struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+
+ return asic_funcs->dma_alloc_coherent(hdev, size, dma_handle, flag);
+}
+
+void __hbl_cn_dma_free_coherent(struct hbl_cn_device *hdev, size_t size, void *cpu_addr,
+ dma_addr_t dma_addr, const char *caller)
+{
+ const struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+
+ asic_funcs->dma_free_coherent(hdev, size, cpu_addr, dma_addr);
+}
+
+void *__hbl_cn_dma_pool_zalloc(struct hbl_cn_device *hdev, size_t size, gfp_t mem_flags,
+ dma_addr_t *dma_handle, const char *caller)
+{
+ const struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+
+ return asic_funcs->dma_pool_zalloc(hdev, size, mem_flags, dma_handle);
+}
+
+void __hbl_cn_dma_pool_free(struct hbl_cn_device *hdev, void *vaddr, dma_addr_t dma_addr,
+ const char *caller)
+{
+ const struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+
+ asic_funcs->dma_pool_free(hdev, vaddr, dma_addr);
+}
+
+int hbl_cn_get_reg_pcie_addr(struct hbl_cn_device *hdev, u8 bar_id, u32 reg, u64 *pci_addr)
+{
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u64 offset;
+ int rc;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ rc = aux_ops->get_reg_pcie_addr(aux_dev, reg, &offset);
+ if (rc)
+ return rc;
+
+ *pci_addr = pci_resource_start(hdev->pdev, bar_id) + offset;
+
+ return 0;
+}
+
+int hbl_cn_get_src_ip(struct hbl_cn_port *cn_port, u32 *src_ip)
+{
+ struct hbl_aux_dev *aux_dev = &cn_port->hdev->en_aux_dev;
+ struct hbl_en_aux_ops *aux_ops = aux_dev->aux_ops;
+ u32 port = cn_port->port;
+
+ if (cn_port->eth_enable && aux_ops->get_src_ip)
+ return aux_ops->get_src_ip(aux_dev, port, src_ip);
+
+ *src_ip = 0;
+
+ return 0;
+}
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.h b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.h
new file mode 100644
index 000000000000..27139e93d990
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.h
@@ -0,0 +1,1627 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#ifndef HABANALABS_CN_H_
+#define HABANALABS_CN_H_
+
+#include <linux/habanalabs/cpucp_if.h>
+#include <linux/net/intel/cni.h>
+#include <linux/net/intel/cn.h>
+
+#include <linux/bitfield.h>
+#include <linux/ctype.h>
+#include <linux/kfifo.h>
+#include <linux/netdevice.h>
+#include <linux/types.h>
+#include <linux/genalloc.h>
+
+/* Use upper bits of mmap offset to store habana CN driver specific information.
+ * bits[63:60] - Encode mmap type
+ * bits[45:0] - mmap offset value
+ *
+ * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these
+ * defines are w.r.t to PAGE_SIZE
+ */
+#define HBL_CN_MMAP_TYPE_SHIFT (60 - PAGE_SHIFT)
+#define HBL_CN_MMAP_TYPE_MASK (0xfull << HBL_CN_MMAP_TYPE_SHIFT)
+#define HBL_CN_MMAP_TYPE_CN_MEM (0x2ull << HBL_CN_MMAP_TYPE_SHIFT)
+#define HBL_CN_MMAP_TYPE_BLOCK (0x1ull << HBL_CN_MMAP_TYPE_SHIFT)
+
+#define HBL_CN_MMAP_OFFSET_VALUE_MASK (0x0FFFFFFFFFFFull >> PAGE_SHIFT)
+#define HBL_CN_MMAP_OFFSET_VALUE_GET(off) ((off) & HBL_CN_MMAP_OFFSET_VALUE_MASK)
+
+#define RREG32(reg) hbl_cn_rreg(hdev, (reg))
+#define WREG32(reg, v) hbl_cn_wreg(hdev, (reg), (v))
+#define WREG32_P(reg, val, mask) \
+ do { \
+ u32 __reg = (reg); \
+ u32 tmp_ = RREG32(__reg); \
+ u32 __mask = (mask); \
+ tmp_ &= __mask; \
+ tmp_ |= ((val) & ~__mask); \
+ WREG32(__reg, tmp_); \
+ } while (0)
+
+#define RMWREG32_SHIFTED(reg, val, mask) WREG32_P(reg, val, ~(mask))
+
+#define RMWREG32(reg, val, mask) \
+ do { \
+ u32 _mask = (mask); \
+ RMWREG32_SHIFTED(reg, (val) << __ffs(_mask), _mask); \
+ } while (0)
+
+#define __snprintf(buf, bsize, fmt, ...) \
+ do { \
+ size_t _bsize = (bsize); \
+ char *_buf = (buf); \
+ size_t _blen; \
+ \
+ _blen = strlen(_buf); \
+ \
+ if (_blen < _bsize) \
+ snprintf(_buf + _blen, _bsize - _blen, fmt, ##__VA_ARGS__); \
+ } while (0)
+
+#define NIC_MAX_TNL_HDR_SIZE 32 /* Bytes */
+
+#define NIC_EQ_INFO_BUF_SIZE 256
+#define NIC_NUM_CONCUR_ASIDS 4
+#define RDMA_OFFSET 1
+
+#define NIC_QPC_INV_USEC 1000000 /* 1s */
+#define NIC_SIM_QPC_INV_USEC (NIC_QPC_INV_USEC * 5)
+#define NIC_PLDM_QPC_INV_USEC (NIC_QPC_INV_USEC * 10)
+
+#define NIC_SPMU_STATS_LEN_MAX 6
+
+#define NIC_TMR_TIMEOUT_DEFAULT_GRAN 13
+#define NIC_TMR_TIMEOUT_MAX_GRAN 31
+#define NIC_ADAPTIVE_TIMEOUT_RANGE 6
+#define NIC_GRAN_TO_USEC(gran) (1UL << ((gran) + 2))
+#define NIC_TMR_RESET_FACTOR 3
+
+#define PARSE_FIELD(data, shift, size) (((data) >> (shift)) & (BIT(size) - 1))
+#define MERGE_FIELDS(data_hi, data_lo, shift) ((data_hi) << (shift) | (data_lo))
+
+#define NIC_MACRO_CFG_SIZE hdev->cn_props.macro_cfg_size
+#define NIC_MACRO_CFG_BASE(port) (NIC_MACRO_CFG_SIZE * ((port) >> 1))
+
+#define NIC_MACRO_RREG32(reg) RREG32(NIC_MACRO_CFG_BASE(port) + (reg))
+#define NIC_MACRO_WREG32(reg, val) WREG32(NIC_MACRO_CFG_BASE(port) + (reg), (val))
+#define NIC_MACRO_RMWREG32(reg, val, mask) RMWREG32(NIC_MACRO_CFG_BASE(port) + (reg), val, mask)
+
+#define NIC_PORT_CHECK_ENABLE BIT(0)
+#define NIC_PORT_CHECK_OPEN BIT(1)
+#define NIC_PORT_PRINT_ON_ERR BIT(2)
+#define NIC_PORT_CHECK_ALL GENMASK(2, 0)
+
+#define QPC_REQ_BURST_SIZE 16
+#define QPC_REQ_SCHED_Q 3
+#define QPC_RES_SCHED_Q 2
+#define QPC_RAW_SCHED_Q 1
+
+#define REGMASK(V, F) (((V) << F##_SHIFT) & F##_MASK)
+#define REGMASK2(V, F) (((V) << F##_S) & F##_M)
+
+#define NIC_DR_10 1031250
+#define NIC_DR_25 2578125
+#define NIC_DR_26 2656250
+#define NIC_DR_50 5312500
+#define NIC_DR_100 10625000
+
+#define NIC_MAC_LANE_0 0U
+#define NIC_MAC_LANE_1 1U
+#define NIC_MAC_LANE_2 2U
+#define NIC_MAC_LANE_3 3U
+#define NIC_MAC_LANES 4U
+
+#define CC_CQE_SIZE 16
+#define USER_CCQ_MAX_ENTRIES (BIT(21) / CC_CQE_SIZE) /* dma_alloc can only allocate 2M */
+#define USER_CCQ_MIN_ENTRIES 16
+
+#define DMA_COHERENT_MAX_SIZE SZ_4M
+
+#define PHY_TX_TAPS_NUM 5
+
+#define ACCUMULATE_FEC_STATS_DURATION_MS 100 /* ms */
+#define ACCUMULATE_FEC_STATS_DURATION_MS_MAX 10000 /* ms */
+
+#define HBL_CN_BLOCK_SIZE 0x1000
+
+/* DMA alloc/free wrappers */
+#define hbl_cn_dma_alloc_coherent(hdev, size, dma_handle, flags) \
+ __hbl_cn_dma_alloc_coherent(hdev, size, dma_handle, flags, __func__)
+#define hbl_cn_dma_free_coherent(hdev, size, cpu_addr, dma_addr) \
+ __hbl_cn_dma_free_coherent(hdev, size, cpu_addr, dma_addr, __func__)
+
+#define hbl_cn_dma_pool_zalloc(hdev, size, mem_flags, dma_handle) \
+ __hbl_cn_dma_pool_zalloc(hdev, size, mem_flags, dma_handle, __func__)
+#define hbl_cn_dma_pool_free(hdev, vaddr, dma_addr) \
+ __hbl_cn_dma_pool_free(hdev, vaddr, dma_addr, __func__)
+
+extern struct hbl_cn_stat hbl_cn_mac_fec_stats[];
+extern struct hbl_cn_stat hbl_cn_mac_stats_rx[];
+extern struct hbl_cn_stat hbl_cn_mac_stats_tx[];
+extern size_t hbl_cn_mac_fec_stats_len;
+extern size_t hbl_cn_mac_stats_rx_len;
+extern size_t hbl_cn_mac_stats_tx_len;
+
+/**
+ * enum mtu_type - Describes QP's MTU value source.
+ * @MTU_INVALID: MTU is not configured yet.
+ * @MTU_FROM_USER: MTU gotten from user call to set requester context.
+ * @MTU_FROM_NETDEV: MTU gotten from netdev.
+ * @MTU_DEFAULT: Use default MTU value.
+ */
+enum mtu_type {
+ MTU_INVALID,
+ MTU_FROM_USER,
+ MTU_FROM_NETDEV,
+ MTU_DEFAULT
+};
+
+/**
+ * enum hbl_cn_qp_state - The states the QPs can be.
+ * Follows the spirit of "10.3.1 QUEUE PAIR AND EE CONTEXT STATES" section in
+ * InfiniBand(TM) Architecture Release.
+ * CN_QP_STATE_RESET: QP is in reset state
+ * CN_QP_STATE_INIT: Initialized state where all QP resources are allocated. QP can post Recv WRs.
+ * CN_QP_STATE_RTR: Ready to receive state. QP can post & process Rcv WRs & send ACKs,
+ * CN_QP_STATE_RTS: Ready to send state. QP can post and process recv & send WRs
+ * CN_QP_STATE_SQD: SQ is in drained state (a sub-state of the QP draining process).
+ * CN_QP_STATE_QPD: QP is in drained state, both RQ and SQ are drained.
+ * CN_QP_STATE_SQERR: Send queue error state. QP can Post & process Receive WRs, Send WRs are
+ * completed in error.
+ * CN_QP_STATE_ERR: Error state.
+ * CN_QP_NUM_STATE: Number of states the QP can be in.
+ */
+enum hbl_cn_qp_state {
+ CN_QP_STATE_RESET = 0,
+ CN_QP_STATE_INIT,
+ CN_QP_STATE_RTR,
+ CN_QP_STATE_RTS,
+ CN_QP_STATE_SQD,
+ CN_QP_STATE_QPD,
+ CN_QP_STATE_SQERR,
+ CN_QP_STATE_ERR,
+ CN_QP_NUM_STATE, /* must be last */
+};
+
+/**
+ * enum hbl_cn_qp_state_op - The Valid state transition operations on QP.
+ * CN_QP_OP_INVAL: Invalid OP, indicates invalid state transition path, not to be used. Must be 0.
+ * CN_QP_OP_RST_2INIT: Move the QP from the Reset state to the Init state.
+ * CN_QP_OP_INIT_2RTR: Move the QP from the Init state to the Ready-to-receive state.
+ * CN_QP_OP_RTR_2RTR: Reconfig Responder.
+ * CN_QP_OP_RTR_2QPD: drain the Responder.
+ * CN_QP_OP_RTR_2RTS: Move the QP from RTR state to the Ready-to-send state.
+ * CN_QP_OP_RTR_2SQD: Move the QP from RTR state to the drained state.
+ * CN_QP_OP_RTS_2RTS: Reconfigure the requester.
+ * CN_QP_OP_RTS_2SQERR: move the QP from RTS to the SQER state due to HW errors.
+ * CN_QP_OP_RTS_2SQD: Drain the SQ and move to the SQ-Drained state.
+ * CN_QP_OP_RTS_2QPD: drain the QP (requester and responder).
+ * CN_QP_OP_SQD_2SQD: Re-drain the SQ.
+ * CN_QP_OP_SQD_2QPD: Drain the QP (Responder too).
+ * CN_QP_OP_SQD_2RTS: Enable the requester after draining is done.
+ * CN_QP_OP_SQD_2SQ_ERR: move the QP to SQ_Err due to HW error.
+ * CN_QP_OP_QPD_2RTR: restart the Responder.
+ * CN_QP_OP_QPD_2QPD: drain the QP (again).
+ * CN_QP_OP_SQ_ERR_2SQD: recover from SQ err and return to work
+ * CN_QP_OP_2ERR: Place the QP in error state (due to HW errors).
+ * An error can be forced from any state, except Reset.
+ * CN_QP_OP_2RESET: Move to reset state.
+ * it is possible to transition from any state to the Reset state.
+ * CN_QP_OP_NOP: Do nothing.
+ */
+enum hbl_cn_qp_state_op {
+ CN_QP_OP_INVAL = 0,
+ CN_QP_OP_RST_2INIT,
+ CN_QP_OP_INIT_2RTR,
+ CN_QP_OP_RTR_2RTR,
+ CN_QP_OP_RTR_2QPD,
+ CN_QP_OP_RTR_2RTS,
+ CN_QP_OP_RTR_2SQD,
+ CN_QP_OP_RTS_2RTS,
+ CN_QP_OP_RTS_2SQERR,
+ CN_QP_OP_RTS_2SQD,
+ CN_QP_OP_RTS_2QPD,
+ CN_QP_OP_SQD_2SQD,
+ CN_QP_OP_SQD_2QPD,
+ CN_QP_OP_SQD_2RTS,
+ CN_QP_OP_SQD_2SQ_ERR,
+ CN_QP_OP_QPD_2RTR,
+ CN_QP_OP_QPD_2QPD,
+ CN_QP_OP_SQ_ERR_2SQD,
+ CN_QP_OP_2ERR,
+ CN_QP_OP_2RESET,
+ CN_QP_OP_NOP,
+};
+
+/**
+ * enum db_fifo_state - Describes db fifo's current state. Starting it from 1 because by default
+ * on reset when the state is 0, it shouldn't be confused as Allocated state.
+ * @DB_FIFO_STATE_ALLOC: db fifo id has been allocated.
+ * @DB_FIFO_STATE_SET: db fifo set is done for the corresponding id.
+ */
+enum db_fifo_state {
+ DB_FIFO_STATE_ALLOC = 1,
+ DB_FIFO_STATE_SET,
+};
+
+/**
+ * struct hbl_cn_qp_reset_mode - QP reset method.
+ * @CN_QP_RESET_MODE_GRACEFUL: Graceful reset, reset the QP components in an orderly manner and wait
+ * on each component to settle before moving to the next step.
+ * @CN_QP_RESET_MODE_FAST: Fast reset, reset the QP components in an orderly manner, without waiting
+ * for the components to settle .
+ * @CN_QP_RESET_MODE_HARD: Clear the QP contexts immediately.
+ */
+enum hbl_cn_qp_reset_mode {
+ CN_QP_RESET_MODE_GRACEFUL = 0,
+ CN_QP_RESET_MODE_FAST = 1,
+ CN_QP_RESET_MODE_HARD = 2,
+};
+
+/**
+ * enum hbl_cn_user_cq_state - User CQ states.
+ * @USER_CQ_STATE_ALLOC: ID allocated.
+ * @USER_CQ_STATE_SET: HW configured. Resources allocated.
+ * @USER_CQ_STATE_ALLOC_TO_UNSET: CQ moved to unset state from alloc state directly.
+ * @USER_CQ_STATE_SET_TO_UNSET: CQ moved to unset from set state. HW config cleared.
+ * Resources ready to be reclaimed.
+ */
+enum hbl_cn_user_cq_state {
+ USER_CQ_STATE_ALLOC = 1,
+ USER_CQ_STATE_SET,
+ USER_CQ_STATE_ALLOC_TO_UNSET,
+ USER_CQ_STATE_SET_TO_UNSET,
+};
+
+/**
+ * enum hbl_cn_drv_mem_id - Memory allocation methods:
+ * HBL_CN_DRV_MEM_INVALID: N/A option.
+ * HBL_CN_DRV_MEM_HOST_DMA_COHERENT: Host DMA coherent memory.
+ * HBL_CN_DRV_MEM_HOST_VIRTUAL: Host virtual memory.
+ * HBL_CN_DRV_MEM_DEVICE: Device HBM memory.
+ * HBL_CN_DRV_MEM_HOST_MAP_ONLY: Host mapping only.
+ */
+enum hbl_cn_drv_mem_id {
+ HBL_CN_DRV_MEM_INVALID,
+ HBL_CN_DRV_MEM_HOST_DMA_COHERENT,
+ HBL_CN_DRV_MEM_HOST_VIRTUAL,
+ HBL_CN_DRV_MEM_DEVICE,
+ HBL_CN_DRV_MEM_HOST_MAP_ONLY,
+};
+
+struct hbl_cn_port;
+struct hbl_cn_device;
+struct hbl_cn_macro;
+
+/**
+ * struct hbl_cn_dq_qp_info - structure to hold qp info for dispatch queue.
+ * @node: reference to a QP within the list
+ * @dq: dq per asid event dispatcher queue
+ * @qpn: QP id
+ */
+struct hbl_cn_dq_qp_info {
+ struct hlist_node node;
+ struct hbl_cn_ev_dq *dq;
+ u32 qpn;
+};
+
+/**
+ * struct hbl_cn_eq_raw_buf - a buffer holding unparsed raw EQ events
+ * @events: an array which stores the events
+ * @head: the queue head
+ * @tail: the queue tail
+ * @events_count: number of available events in the queue
+ */
+struct hbl_cn_eq_raw_buf {
+ struct hbl_cn_eqe events[NIC_EQ_INFO_BUF_SIZE];
+ u32 head;
+ u32 tail;
+ u32 events_count;
+};
+
+/**
+ * struct hbl_cn_ev_dq - per-asid/app event dispatch queue
+ * @buf: the dispatched events queue.
+ * @asid: the asid registered on this dq
+ * @overflow: buffer overflow counter
+ * @associated: if this dq associate with a user/asid or not.
+ */
+struct hbl_cn_ev_dq {
+ struct hbl_cn_eq_raw_buf buf;
+ u32 asid;
+ u32 overflow;
+ u8 associated;
+};
+
+/**
+ * struct hbl_cn_ev_dqs - software managed events dispatch queues.
+ * used for dispatching events to their applications.
+ * @qps: a hash table to convert QP-numbers to their owner (ASID).
+ * @cq_dq: array to associate/convert cq-numbers to the dispatch queues.
+ * @ccq_dq: array to associate/convert ccq-numbers to the dispatch queues.
+ * @db_dq: array to associate/convert doorbell-numbers to the dispatch queues.
+ * @edq: the events dispatch queues (as many queues as the number of possible same-time ASIDs).
+ * @default_edq: default events dispatch queue for unknown resources and events.
+ * @lock: protects from simultaneous operations.
+ */
+struct hbl_cn_ev_dqs {
+ DECLARE_HASHTABLE(qps, 11);
+ struct hbl_cn_ev_dq *cq_dq[NIC_DRV_MAX_CQS_NUM];
+ struct hbl_cn_ev_dq *ccq_dq[NIC_DRV_MAX_CCQS_NUM];
+ struct hbl_cn_ev_dq *db_dq[NIC_DRV_NUM_DB_FIFOS];
+ struct hbl_cn_ev_dq edq[NIC_NUM_CONCUR_ASIDS];
+ struct hbl_cn_ev_dq default_edq;
+ /* protects from simultaneous operations */
+ struct mutex lock;
+};
+
+/**
+ * struct hbl_cn_qp_info - holds information of a QP to read via debugfs.
+ * @port: the port the QP belongs to.
+ * @qpn: QP number.
+ * @req: true for requester QP, otherwise responder.
+ * @full_print: print full QP information.
+ * @force_read: force reading a QP in invalid/error state.
+ */
+struct hbl_cn_qp_info {
+ u32 port;
+ u32 qpn;
+ u8 req;
+ u8 full_print;
+ u8 force_read;
+};
+
+/**
+ * struct hbl_cn_wqe_info - holds information of a WQE to read via debugfs.
+ * @port: the port the WQE belongs to.
+ * @qpn: QP number.
+ * @wqe_idx: WQE index.
+ * @tx: true for tx WQE, otherwise rx WQE.
+ */
+struct hbl_cn_wqe_info {
+ u32 port;
+ u32 qpn;
+ u32 wqe_idx;
+ u8 tx;
+};
+
+/**
+ * struct hbl_cn_db_fifo_xarray_pdata - Holds private data of userspace doorbell xarray
+ * @asid: Associated user context.
+ * @port: Associated port index.
+ * @id: fifo index.
+ * @ci_mmap_handle: Consumer index mmap handle.
+ * @umr_mmap_handle: UMR block mmap handle.
+ * @umr_db_offset: db fifo offset in UMR block.
+ * @state: db fifo's state.
+ * @db_pool_addr: offset of the allocated address in gen pool.
+ * @fifo_offset: actual fifo offset allocated for that id.
+ * @fifo_size: size of the fifo allocated.
+ * @fifo_mode: mode of the fifo as received in the IOCTL.
+ */
+struct hbl_cn_db_fifo_xarray_pdata {
+ u32 asid;
+ u32 port;
+ u32 id;
+ u64 ci_mmap_handle;
+ u64 umr_mmap_handle;
+ u32 umr_db_offset;
+ enum db_fifo_state state;
+ u32 db_pool_addr;
+ u32 fifo_offset;
+ u32 fifo_size;
+ u8 fifo_mode;
+};
+
+/**
+ * struct hbl_cn_encap_xarray_pdata - Holds private data of userspace encapsulation xarray
+ * @port: Associated port index
+ * @id: Encapsulation ID
+ * @src_ip: Source port IPv4 address.
+ * @encap_type: L3/L4 encapsulation
+ * @encap_type_data: IPv4 protocol or UDP port
+ * @encap_header: Encapsulation header
+ * @encap_header_size: Encapsulation header size
+ * @is_set: True if encap was set, false otherwise
+ */
+struct hbl_cn_encap_xarray_pdata {
+ u32 port;
+ u32 id;
+ u32 src_ip;
+ enum hbl_nic_encap_type encap_type;
+ u32 encap_type_data;
+ void *encap_header;
+ u32 encap_header_size;
+ u8 is_set;
+};
+
+/**
+ * struct hbl_cn_user_cq - user CQ data.
+ * @cn_port: associated port.
+ * @refcount: number of QPs that use this CQ.
+ * @ctx: Associated user context.
+ * @state: User CQ state.
+ * @overrun_lock: protects the setting\unsetting of CQ overrun.
+ * @mem_handle: mmap handle of buffer memory.
+ * @pi_handle: mmap handle of PI memory.
+ * @id: CQ ID.
+ * @qp_set_overrun_cnt: number of QPs which expect CQ overrun to be enabled.
+ * @is_mmu_bp: is MMU bypass enabled for the memory buffer.
+ */
+struct hbl_cn_user_cq {
+ struct hbl_cn_port *cn_port;
+ struct kref refcount;
+ struct hbl_cn_ctx *ctx;
+ enum hbl_cn_user_cq_state state;
+ /* protects the setting\unsetting of CQ overrun */
+ struct mutex overrun_lock;
+ u64 mem_handle;
+ u64 pi_handle;
+ u32 id;
+ u32 qp_set_overrun_cnt;
+ u8 is_mmu_bp;
+};
+
+/**
+ * struct hbl_cn_wq_array_properties - WQ array properties.
+ * @type_str: string of this WQ array type.
+ * @handle: handle for this WQ array.
+ * @dva_base: reserved device VA for this WQ array.
+ * @dva_size: size in bytes of device VA block of this WQ array.
+ * @wq_size: size in bytes of each WQ in this WQ array.
+ * @idx: index of this WQ array.
+ * @offset: offset inside the memory chunk.
+ * @under_unset: true if this WQ array is waiting for unset (will be done when all QPs are
+ * destroyed), false otherwise.
+ * @on_device_mem: true if this WQ array resides on HBM, false if on host.
+ * @is_send: true if this WQ array should contain send WQEs, false if recv WQEs.
+ * @wq_mmu_bypass: true if WQs has MMU-BP access, false otherwise.
+ * @enabled: true if this WQ array is enabled, false otherwise.
+ */
+struct hbl_cn_wq_array_properties {
+ char *type_str;
+ u64 handle;
+ u64 dva_base;
+ u64 dva_size;
+ u64 wq_size;
+ u32 idx;
+ u32 offset;
+ u8 under_unset;
+ u8 on_device_mem;
+ u8 is_send;
+ u8 wq_mmu_bypass;
+ u8 enabled;
+};
+
+/**
+ * struct hbl_cn_reset_tracker - port reset tracking information.
+ * @timeout_jiffies: end of the measurement window.
+ * @num_seq_resets: how many sequential resets were triggered inside the measurement window.
+ */
+struct hbl_cn_reset_tracker {
+ unsigned long timeout_jiffies;
+ u8 num_seq_resets;
+};
+
+/**
+ * struct hbl_cn_mem_buf - describes a memory allocation.
+ * @ctx: pointer to the context this memory belongs to.
+ * @bus_address: Holds the memory's DMA address.
+ * @kernel_address: Holds the memory's kernel virtual address.
+ * @refcount: reference counter for buffer users.
+ * @mmap: atomic boolean indicating whether or not the buffer is mapped right now.
+ * @real_mapped_size: the actual size of buffer mapped, after part of it may be released, may
+ * change at runtime.
+ * @mappable_size: the original mappable size of the buffer, does not change after the allocation.
+ * @device_addr: Holds the HBM address.
+ * @device_va: Device virtual address. Valid only for MMU mapped allocations.
+ * @handle: The buffer id that is stored in the mem xarray.
+ * @mem_id: specify host/device memory allocation.
+ * @is_destroyed: Indicates whether or not the memory was destroyed.
+ */
+struct hbl_cn_mem_buf {
+ struct hbl_cn_ctx *ctx;
+ dma_addr_t bus_address;
+ void *kernel_address;
+ struct kref refcount;
+ atomic_t mmap;
+ u64 real_mapped_size;
+ u64 mappable_size;
+ u64 device_addr;
+ u64 device_va;
+ u64 handle;
+ u32 mem_id;
+ atomic_t is_destroyed;
+};
+
+/**
+ * struct hbl_cn_qp - Describes a Queue Pair.
+ * @cn_port: Pointer to the port this QP belongs to.
+ * @async_work: async work performed on QP, when destroying the QP.
+ * @adaptive_tmr_reset: reset work performed on QP, for adaptive timer.
+ * @req_user_cq: CQ ID used by the requester context.
+ * @res_user_cq: CQ ID used by the responder context.
+ * @ctx: Associated user context.
+ * @curr_state: The current state of the QP.
+ * @mtu_type: Source of MTU value from user, from netdev or default.
+ * @swq_handle: Send WQ mmap handle.
+ * @rwq_handle: Receive WQ mmap handle.
+ * @port: The port number this QP belongs to.
+ * @qp_id: The QP number within its port.
+ * @local_key: Key for local access.
+ * @remote_key: Key for remote access.
+ * @mtu: Current MTU value.
+ * @swq_size: Send WQ mmap size.
+ * @rwq_size: Receive WQ mmap size.
+ * @is_req: is requester context was set for the QP.
+ * @is_res: is responder context was set for the QP.
+ * @force_cq_overrun: force CQ overrun, if needed, during destruction phase.
+ * @timeout_granularity: User supplied granularity value.
+ * @timeout_curr: Currently used granularity value.
+ */
+struct hbl_cn_qp {
+ struct hbl_cn_port *cn_port;
+ struct work_struct async_work;
+ struct delayed_work adaptive_tmr_reset;
+ struct hbl_cn_user_cq *req_user_cq;
+ struct hbl_cn_user_cq *res_user_cq;
+ struct hbl_cn_ctx *ctx;
+ enum hbl_cn_qp_state curr_state;
+ enum mtu_type mtu_type;
+ u64 swq_handle;
+ u64 rwq_handle;
+ u32 port;
+ u32 qp_id;
+ u32 local_key;
+ u32 remote_key;
+ u32 mtu;
+ u32 swq_size;
+ u32 rwq_size;
+ u8 is_req;
+ u8 is_res;
+ u8 force_cq_overrun;
+ u8 timeout_granularity;
+ u8 timeout_curr;
+};
+
+/**
+ * enum qp_conn_state - State of retransmission flow.
+ * @QP_CONN_STATE_OPEN: connection is open.
+ * @QP_CONN_STATE_CLOSED: connection is closed.
+ * @QP_CONN_STATE_RESYNC: Connection is re-synchronizing.
+ * @QP_CONN_STATE_ERROR: Connection is in error state.
+ */
+enum qp_conn_state {
+ QP_CONN_STATE_OPEN = 0,
+ QP_CONN_STATE_CLOSED = 1,
+ QP_CONN_STATE_RESYNC = 2,
+ QP_CONN_STATE_ERROR = 3,
+};
+
+/**
+ * struct hbl_cn_qpc_attr - QPC attributes as read from the HW.
+ * @valid: QPC is valid.
+ * @in_work: qp was scheduled to work.
+ * @error: QPC is in error state (relevant in Req QPC only).
+ * @conn_state - state of retransmission flow (relevant in Res QPC only).
+ */
+struct hbl_cn_qpc_attr {
+ u8 valid;
+ u8 in_work;
+ u8 error;
+ enum qp_conn_state conn_state;
+};
+
+/**
+ * struct hbl_cn_qpc_reset_attr - attributes used when setting QP state to reset.
+ * @reset_mode: the type/mode of reset to be used.
+ */
+struct hbl_cn_qpc_reset_attr {
+ enum hbl_cn_qp_reset_mode reset_mode;
+};
+
+/**
+ * struct hbl_cn_qpc_drain_attr - QPC attributes used for draining operation.
+ * @wait_for_idle: wait for QPC to become idle.
+ */
+struct hbl_cn_qpc_drain_attr {
+ bool wait_for_idle;
+};
+
+/**
+ * struct hbl_cn_mem_data - memory allocation metadata.
+ * @in: mem_id specific allocation parameters.
+ * @in.device_mem_data: mem_id HBL_CN_DRV_MEM_DEVICE specific allocation parameters.
+ * @in.device_mem_data.port: Associated port index.
+ * @in.device_mem_data.type: enum hbl_nic_mem_type to be allocated.
+ * @in.host_map_data: mem_id HBL_CN_DRV_MEM_HOST_MAP_ONLY specific mapping parameters.
+ * @in.host_map_data.bus_address: Memory DMA address.
+ * @in.host_map_data.kernel_address: Memory kernel virtual address.
+ * @mem_id: Allocation type, enum hbl_cn_mem_id.
+ * @size: Allocation size.
+ * @device_va: Device virtual address. Valid only for MMU mapped allocation.
+ * @handle: Returned mmap handle.
+ * @addr: Returned allocation address.
+ */
+struct hbl_cn_mem_data {
+ union {
+ /* HBL_CN_DRV_MEM_DEVICE */
+ struct {
+ u32 port;
+ enum hbl_nic_mem_type type;
+ } device_mem_data;
+
+ /* HBL_CN_DRV_MEM_HOST_MAP_ONLY */
+ struct {
+ dma_addr_t bus_address;
+ void *kernel_address;
+ } host_map_data;
+ } in;
+
+ /* Common in params */
+ enum hbl_cn_drv_mem_id mem_id;
+ u64 size;
+ u64 device_va;
+
+ /* Common out params */
+ u64 handle;
+ u64 addr;
+};
+
+/**
+ * struct hbl_cni_user_cq_set_in_params - user CQ configuration in params.
+ * @port: port index.
+ * @num_of_cqes: Number of CQ entries in the buffer.
+ * @id: CQ ID.
+ */
+struct hbl_cni_user_cq_set_in_params {
+ u32 port;
+ u32 num_of_cqes;
+ u32 id;
+};
+
+/**
+ * struct hbl_cni_user_cq_set_out_params - user CQ configuration out params.
+ * @mem_handle: Handle of CQ memory buffer.
+ * @pi_handle: Handle of CQ producer-inder memory buffer.
+ * @regs_handle: Handle of CQ Registers base-address.
+ * @regs_offset: CQ Registers sub-offset.
+ */
+struct hbl_cni_user_cq_set_out_params {
+ u64 mem_handle;
+ u64 pi_handle;
+ u64 regs_handle;
+ u32 regs_offset;
+};
+
+/**
+ * struct hbl_cni_user_cq_unset_in_params - user CQ unconfiguration in params.
+ * @port: port index.
+ * @id: CQ ID.
+ */
+struct hbl_cni_user_cq_unset_in_params {
+ u32 port;
+ u32 id;
+};
+
+/**
+ * struct hbl_cn_cpucp_status - describes the status of a port.
+ * @port: port index.
+ * @bad_format_cnt: e.g. CRC.
+ * @responder_out_of_sequence_psn_cnt: e.g NAK.
+ * @high_ber_reinit_cnt: link reinit due to high BER.
+ * @correctable_err_cnt: e.g. bit-flip.
+ * @uncorrectable_err_cnt: e.g. MAC errors.
+ * @retraining_cnt: re-training counter.
+ * @up: is port up.
+ * @pcs_link: has PCS link.
+ * @phy_ready: is PHY ready.
+ * @auto_neg: is Autoneg enabled.
+ * @timeout_retransmission_cnt: timeout retransmission events.
+ * @high_ber_cnt: high ber events.
+ * @pre_fec_ser: pre FEC SER value.
+ * @post_fec_ser: post FEC SER value.
+ * @bandwidth: measured bandwidth.
+ * @lat: measured latency.
+ * @port_toggle_cnt: counts how many times the link toggled since last port PHY init.
+ */
+struct hbl_cn_cpucp_status {
+ u32 port;
+ u32 bad_format_cnt;
+ u32 responder_out_of_sequence_psn_cnt;
+ u32 high_ber_reinit;
+ u32 correctable_err_cnt;
+ u32 uncorrectable_err_cnt;
+ u32 retraining_cnt;
+ u8 up;
+ u8 pcs_link;
+ u8 phy_ready;
+ u8 auto_neg;
+ u32 timeout_retransmission_cnt;
+ u32 high_ber_cnt;
+ struct hbl_cn_cpucp_ser_val pre_fec_ser;
+ struct hbl_cn_cpucp_ser_val post_fec_ser;
+ struct hbl_cn_cpucp_frac_val bandwidth;
+ struct hbl_cn_cpucp_frac_val lat;
+ u32 port_toggle_cnt;
+};
+
+/**
+ * struct hbl_cn_asic_port_funcs - ASIC specific functions that are can be called from common code
+ * for a specific port.
+ * @port_hw_init: initialize the port HW.
+ * @port_hw_fini: cleanup the port HW.
+ * @phy_port_init: port PHY init.
+ * @phy_port_start_stop: port PHY start/stop.
+ * @phy_port_power_up: port PHY power-up.
+ * @phy_port_reconfig: port PHY reconfigure.
+ * @phy_port_fini: port PHY cleanup.
+ * @phy_link_status_work: link status handler.
+ * @update_mtu: updates MTU inside a requestor QP context.
+ * @user_wq_arr_unset: unset user WQ array (check whether user_wq_lock should be taken).
+ * @get_cq_id_range: get user CQ ID range.
+ * @user_cq_set: set user CQ.
+ * @user_cq_unset: unset user CQ.
+ * @user_cq_destroy: destroy user CQ.
+ * @get_cnts_num: get the number of available counters.
+ * @get_cnts_names: get the names of the available counters.
+ * @get_cnts_values: get the values of the available counters.
+ * @port_sw_init: initialize per port software components.
+ * @port_sw_fini: finalize per port software components.
+ * @register_qp: register a new qp-id with the NIC.
+ * @unregister_qp: unregister a qp.
+ * @get_qp_id_range: Get unsecure QP ID range.
+ * @eq_poll: poll the EQ for asid/app-specific events.
+ * @get_db_fifo_id_range: Get the fifo ID range that is available to the user.
+ * @get_db_fifo_hw_id_range: Get the actual HW fifo ID range.
+ * @db_fifo_set: Config unsecure userspace doorbell fifo.
+ * @db_fifo_unset: Destroy unsecure userspace doorbell fifo.
+ * @get_db_fifo_umr: Get UMR block address and db fifo offset.
+ * @get_db_fifo_modes_mask: Get the supported db fifo modes
+ * @db_fifo_allocate: Allocate fifo for the specific mode
+ * @db_fifo_free: Free the fifo for the specific id
+ * @set_pfc: enable/disable PFC.
+ * @get_encap_id_range: Get user encapsulation ID range
+ * @encap_set: Start encapsulation
+ * @encap_unset: Stop encapsulation
+ * @set_ip_addr_encap: Setup IP address encapsulation.
+ * @qpc_write: write a QP context to the HW.
+ * @qpc_invalidate: invalidate a QP context.
+ * @qpc_query: read a QP context.
+ * @qpc_clear: clear a QP context.
+ * @user_ccq_set: set user congestion completion queue.
+ * @user_ccq_unset: unset user congestion completion queue.
+ * @reset_mac_stats: reset MAC statistics.
+ * @collect_fec_stats: collect FEC statistics.
+ * @disable_wqe_index_checker: Disable WQE index checker for both Rx and Tx.
+ * @get_status: get status information for F/W.
+ * @cfg_lock: acquire the port configuration lock.
+ * @cfg_unlock: release the port configuration lock.
+ * @cfg_is_locked: check if the port configuration lock is locked.
+ * @qp_pre_destroy: prepare for a QP destroy. Called under the cfg lock.
+ * @qp_post_destroy: cleanup after a QP destroy. Called under the cfg lock.
+ * @set_port_status: config port status before notifying user.
+ * @send_cpucp_packet: Send cpucp packet to FW.
+ * @adaptive_tmr_reset: Reset timer granularity for adaptive timeout feature.
+ * @spmu_get_stats_info: get SPMU statistics information.
+ * @spmu_config: config the SPMU.
+ * @spmu_sample: read SPMU counters.
+ * @post_send_status: handler for post sending status packet to FW.
+ */
+struct hbl_cn_asic_port_funcs {
+ int (*port_hw_init)(struct hbl_cn_port *cn_port);
+ void (*port_hw_fini)(struct hbl_cn_port *cn_port);
+ int (*phy_port_init)(struct hbl_cn_port *cn_port);
+ void (*phy_port_start_stop)(struct hbl_cn_port *cn_port, bool is_start);
+ int (*phy_port_power_up)(struct hbl_cn_port *cn_port);
+ void (*phy_port_reconfig)(struct hbl_cn_port *cn_port);
+ void (*phy_port_fini)(struct hbl_cn_port *cn_port);
+ void (*phy_link_status_work)(struct work_struct *work);
+ int (*update_qp_mtu)(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp, u32 mtu);
+ int (*user_wq_arr_unset)(struct hbl_cn_ctx *ctx, struct hbl_cn_port *cn_port, u32 type);
+ void (*get_cq_id_range)(struct hbl_cn_port *cn_port, u32 *min_id, u32 *max_id);
+ int (*user_cq_set)(struct hbl_cn_user_cq *user_cq, struct hbl_cni_user_cq_set_in_params *in,
+ struct hbl_cni_user_cq_set_out_params *out);
+ int (*user_cq_unset)(struct hbl_cn_user_cq *user_cq);
+ void (*user_cq_destroy)(struct hbl_cn_user_cq *user_cq);
+ int (*get_cnts_num)(struct hbl_cn_port *cn_port);
+ void (*get_cnts_names)(struct hbl_cn_port *cn_port, u8 *data, bool ext);
+ void (*get_cnts_values)(struct hbl_cn_port *cn_port, u64 *data);
+ int (*port_sw_init)(struct hbl_cn_port *cn_port);
+ void (*port_sw_fini)(struct hbl_cn_port *cn_port);
+ int (*register_qp)(struct hbl_cn_port *cn_port, u32 qp_id, u32 asid);
+ void (*unregister_qp)(struct hbl_cn_port *cn_port, u32 qp_id);
+ void (*get_qp_id_range)(struct hbl_cn_port *cn_port, u32 *min_id, u32 *max_id);
+ int (*eq_poll)(struct hbl_cn_port *cn_port, u32 asid,
+ struct hbl_cni_eq_poll_out *event);
+ struct hbl_cn_ev_dq * (*eq_dispatcher_select_dq)(struct hbl_cn_port *cn_port,
+ const struct hbl_cn_eqe *eqe);
+ void (*get_db_fifo_id_range)(struct hbl_cn_port *cn_port, u32 *min_id, u32 *max_id);
+ void (*get_db_fifo_hw_id_range)(struct hbl_cn_port *cn_port, u32 *min_id, u32 *max_id);
+ int (*db_fifo_set)(struct hbl_cn_port *cn_port, struct hbl_cn_ctx *ctx, u32 id,
+ u64 ci_device_handle, struct hbl_cn_db_fifo_xarray_pdata *xa_pdata);
+ void (*db_fifo_unset)(struct hbl_cn_port *cn_port, u32 id,
+ struct hbl_cn_db_fifo_xarray_pdata *xa_pdata);
+ void (*get_db_fifo_umr)(struct hbl_cn_port *cn_port, u32 id,
+ u64 *umr_block_addr, u32 *umr_db_offset);
+ void (*get_db_fifo_modes_mask)(struct hbl_cn_port *cn_port, u32 *mode_mask);
+ int (*db_fifo_allocate)(struct hbl_cn_port *cn_port,
+ struct hbl_cn_db_fifo_xarray_pdata *xa_pdata);
+ void (*db_fifo_free)(struct hbl_cn_port *cn_port, u32 db_pool_addr, u32 fifo_size);
+ int (*set_pfc)(struct hbl_cn_port *cn_port);
+ void (*get_encap_id_range)(struct hbl_cn_port *cn_port, u32 *min_id, u32 *max_id);
+ int (*encap_set)(struct hbl_cn_port *cn_port, u32 encap_id,
+ struct hbl_cn_encap_xarray_pdata *xa_pdata);
+ void (*encap_unset)(struct hbl_cn_port *cn_port, u32 encap_id,
+ struct hbl_cn_encap_xarray_pdata *xa_pdata);
+ void (*set_ip_addr_encap)(struct hbl_cn_port *cn_port, u32 *encap_id, u32 src_ip);
+ int (*qpc_write)(struct hbl_cn_port *cn_port, void *qpc, struct qpc_mask *qpc_mask,
+ u32 qpn, bool is_req);
+ int (*qpc_invalidate)(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp, bool is_req);
+ int (*qpc_query)(struct hbl_cn_port *cn_port, u32 qpn, bool is_req,
+ struct hbl_cn_qpc_attr *attr);
+ int (*qpc_clear)(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp, bool is_req);
+ void (*user_ccq_set)(struct hbl_cn_port *cn_port, u64 ccq_device_addr, u64 pi_device_addr,
+ u32 num_of_entries, u32 *ccqn);
+ void (*user_ccq_unset)(struct hbl_cn_port *cn_port, u32 *ccqn);
+ void (*reset_mac_stats)(struct hbl_cn_port *cn_port);
+ void (*collect_fec_stats)(struct hbl_cn_port *cn_port, char *buf, size_t size);
+ int (*disable_wqe_index_checker)(struct hbl_cn_port *cn_port);
+ void (*get_status)(struct hbl_cn_port *cn_port, struct hbl_cn_cpucp_status *status);
+ void (*cfg_lock)(struct hbl_cn_port *cn_port);
+ void (*cfg_unlock)(struct hbl_cn_port *cn_port);
+ bool (*cfg_is_locked)(struct hbl_cn_port *cn_port);
+ void (*qp_pre_destroy)(struct hbl_cn_qp *qp);
+ void (*qp_post_destroy)(struct hbl_cn_qp *qp);
+ void (*set_port_status)(struct hbl_cn_port *cn_port, bool up);
+ int (*send_cpucp_packet)(struct hbl_cn_port *cn_port, enum cpucp_packet_id packet_id,
+ int val);
+ void (*adaptive_tmr_reset)(struct hbl_cn_qp *qp);
+ void (*spmu_get_stats_info)(struct hbl_cn_port *cn_port, struct hbl_cn_stat **stats,
+ u32 *n_stats);
+ int (*spmu_config)(struct hbl_cn_port *cn_port, u32 num_event_types, u32 event_types[],
+ bool enable);
+ int (*spmu_sample)(struct hbl_cn_port *cn_port, u32 num_out_data, u64 out_data[]);
+ void (*post_send_status)(struct hbl_cn_port *cn_port);
+};
+
+/**
+ * struct hbl_cn_asic_funcs - ASIC specific functions that are can be called from common code.
+ * @core_init: core infrastructure init.
+ * @core_fini: core infrastructure cleanup.
+ * @get_default_port_speed: get the default port BW in MB/s.
+ * @phy_reset_macro: macro PHY reset.
+ * @phy_get_crc: get PHY CRC.
+ * @set_req_qp_ctx: set up a requester QP context.
+ * @set_res_qp_ctx: set up a responder QP context.
+ * @user_wq_arr_set: set user WQ array (check whether user_wq_lock should be taken).
+ * @user_set_app_params: update user params to be later retrieved by user_get_app_params.
+ * @user_get_app_params: retrieve user params, previously configured or saved by
+ * user_set_app_params.
+ * @get_phy_fw_name: returns the PHY FW file name.
+ * @pre_sw_init: initialize device SW fixed properties.
+ * @sw_init: initialize device SW.
+ * @sw_fini: cleanup device SW.
+ * @macro_sw_init: initialize per macro software components.
+ * @macro_sw_fini: finalize per macro software components.
+ * @kernel_ctx_init: initialize kernel context.
+ * @kernel_ctx_fini: de-initialize kernel context.
+ * @ctx_init: initialize user context.
+ * @ctx_fini: de-initialize user context.
+ * @qp_read: read a QP content.
+ * @wqe_read: read a WQE content.
+ * @phy_fw_load_all: load PHY fw on all the ports.
+ * @set_en_data: ASIC data to be used by the Ethernet driver.
+ * @request_irqs: Add handlers to interrupt lines.
+ * @free_irqs: Free interrupts allocated with request_irqs.
+ * @synchronize_irqs: Wait for pending IRQ handlers (on other CPUs).
+ * @phy_dump_serdes_params: dump the serdes parameters.
+ * @get_max_msg_sz: get maximum message size.
+ * @qp_syndrome_to_str: convert a QP error syndrome to an error string.
+ * @app_params_clear: clear app params.
+ * @inject_rx_err: Force RX packet drops.
+ * @is_encap_supported: true if encapsulation is supported according to the given parameters.
+ * @set_wqe_index_checker: set wqe index checker (enable/disable).
+ * @get_wqe_index_checker: get wqe index checker (enabled/disabled).
+ * @set_static_properties: Sets static CN properties.
+ * @set_dram_properties: Sets DRAM CN properties.
+ * @late_init: set post initialization properties, e.g., compute2cn ops.
+ * @late_fini: clear post initialization properties, e.g., compute2cn ops.
+ * @get_hw_block_handle: Map block and return its handle.
+ * @get_hw_block_addr: Get address and size for a memory handle.
+ * @create_mem_ctx: create a HW memory context.
+ * @destroy_mem_ctx: destroy a HW memory context.
+ * @phy_speed_rate_write: set PHY speed rate ID.
+ * @phy_speed_rate_read: get PHY speed rate ID.
+ * @phy_training_type_write: set PHY training type ID.
+ * @phy_training_type_read: get PHY training type ID.
+ * @dma_alloc_coherent: Allocate coherent DMA memory.
+ * @dma_free_coherent: Free coherent DMA memory.
+ * @dma_pool_zalloc: Allocate a memory block from a DMA memory pool.
+ * @dma_pool_free: Free a DMA memory pool block.
+ * @set_maintenance_work_interval: Set maintenance work interval.
+ * @get_maintenance_work_interval: Get maintenance work interval.
+ * @send_cpu_message: Send message to F/W. If the message is timedout, the driver will eventually
+ * reset the device. The timeout is passed as an argument. If it is 0 the
+ * timeout set is the default timeout for the specific ASIC.
+ * @ports_cancel_status_work: Cancel status work of all ports.
+ * @port_funcs: Functions called from common code for a specific port.
+ */
+struct hbl_cn_asic_funcs {
+ int (*core_init)(struct hbl_cn_device *hdev);
+ void (*core_fini)(struct hbl_cn_device *hdev);
+ u32 (*get_default_port_speed)(struct hbl_cn_device *hdev);
+ int (*phy_reset_macro)(struct hbl_cn_macro *cn_macro);
+ u16 (*phy_get_crc)(struct hbl_cn_device *hdev);
+ int (*set_req_qp_ctx)(struct hbl_cn_device *hdev, struct hbl_cni_req_conn_ctx_in *in,
+ struct hbl_cn_qp *qp);
+ int (*set_res_qp_ctx)(struct hbl_cn_device *hdev, struct hbl_cni_res_conn_ctx_in *in,
+ struct hbl_cn_qp *qp);
+ int (*user_wq_arr_set)(struct hbl_cn_device *hdev, struct hbl_cni_user_wq_arr_set_in *in,
+ struct hbl_cni_user_wq_arr_set_out *out, struct hbl_cn_ctx *ctx);
+ int (*user_set_app_params)(struct hbl_cn_device *hdev,
+ struct hbl_cni_set_user_app_params_in *in,
+ bool *modify_wqe_checkers, struct hbl_cn_ctx *ctx);
+ void (*user_get_app_params)(struct hbl_cn_device *hdev,
+ struct hbl_cni_get_user_app_params_in *in,
+ struct hbl_cni_get_user_app_params_out *out);
+ const char* (*get_phy_fw_name)(void);
+ void (*pre_sw_init)(struct hbl_cn_device *hdev);
+ int (*sw_init)(struct hbl_cn_device *hdev);
+ void (*sw_fini)(struct hbl_cn_device *hdev);
+ int (*macro_sw_init)(struct hbl_cn_macro *cn_macro);
+ void (*macro_sw_fini)(struct hbl_cn_macro *cn_macro);
+ int (*kernel_ctx_init)(struct hbl_cn_device *hdev, u32 asid);
+ void (*kernel_ctx_fini)(struct hbl_cn_device *hdev, u32 asid);
+ int (*ctx_init)(struct hbl_cn_ctx *ctx);
+ void (*ctx_fini)(struct hbl_cn_ctx *ctx);
+ int (*qp_read)(struct hbl_cn_device *hdev, struct hbl_cn_qp_info *qp_info, char *buf,
+ size_t bsize);
+ int (*wqe_read)(struct hbl_cn_device *hdev, char *buf, size_t bsize);
+ int (*phy_fw_load_all)(struct hbl_cn_device *hdev);
+ void (*set_en_data)(struct hbl_cn_device *hdev);
+ int (*request_irqs)(struct hbl_cn_device *hdev);
+ void (*free_irqs)(struct hbl_cn_device *hdev);
+ void (*synchronize_irqs)(struct hbl_cn_device *hdev);
+ void (*phy_dump_serdes_params)(struct hbl_cn_device *hdev, char *buf, size_t size);
+ u32 (*get_max_msg_sz)(struct hbl_cn_device *hdev);
+ char *(*qp_syndrome_to_str)(u32 syndrome);
+ void (*app_params_clear)(struct hbl_cn_device *hdev);
+ int (*inject_rx_err)(struct hbl_cn_device *hdev, u8 drop_percent);
+ bool (*is_encap_supported)(struct hbl_cn_device *hdev,
+ struct hbl_cni_user_encap_set_in *in);
+ int (*set_wqe_index_checker)(struct hbl_cn_device *hdev, u32 enable);
+ int (*get_wqe_index_checker)(struct hbl_cn_device *hdev);
+ int (*set_static_properties)(struct hbl_cn_device *hdev);
+ int (*set_dram_properties)(struct hbl_cn_device *hdev);
+ void (*late_init)(struct hbl_cn_device *hdev);
+ void (*late_fini)(struct hbl_cn_device *hdev);
+ int (*get_hw_block_handle)(struct hbl_cn_device *hdev, u64 address, u64 *handle);
+ int (*get_hw_block_addr)(struct hbl_cn_device *hdev, u64 handle, u64 *addr, u64 *size);
+ int (*create_mem_ctx)(struct hbl_cn_ctx *ctx, u32 pasid, u64 page_tbl_addr);
+ void (*destroy_mem_ctx)(struct hbl_cn_ctx *ctx, u32 pasid, u64 page_tbl_addr);
+ int (*phy_speed_rate_write)(struct hbl_cn_device *hdev, u32 speed_rate_id);
+ u32 (*phy_speed_rate_read)(struct hbl_cn_device *hdev);
+ int (*phy_training_type_write)(struct hbl_cn_device *hdev, u32 training_type_id);
+ u32 (*phy_training_type_read)(struct hbl_cn_device *hdev);
+ void *(*dma_alloc_coherent)(struct hbl_cn_device *hdev, size_t size, dma_addr_t *dma_handle,
+ gfp_t flag);
+ void (*dma_free_coherent)(struct hbl_cn_device *hdev, size_t size, void *cpu_addr,
+ dma_addr_t dma_addr);
+ void *(*dma_pool_zalloc)(struct hbl_cn_device *hdev, size_t size, gfp_t mem_flags,
+ dma_addr_t *dma_handle);
+ void (*dma_pool_free)(struct hbl_cn_device *hdev, void *vaddr, dma_addr_t dma_addr);
+ void (*set_maintenance_work_interval)(struct hbl_cn_device *hdev, u32 value);
+ u32 (*get_maintenance_work_interval)(struct hbl_cn_device *hdev);
+ int (*send_cpu_message)(struct hbl_cn_device *hdev, u32 *msg, u16 len, u32 timeout,
+ u64 *result);
+ void (*ports_cancel_status_work)(struct hbl_cn_device *hdev);
+ struct hbl_cn_asic_port_funcs *port_funcs;
+};
+
+/**
+ * struct hbl_cn_tx_taps - holds the Tx taps values for a specific lane (tx_pre2, tx_pre1, tx_main,
+ * tx_post1 and tx_post2).
+ * @pam4_taps: taps for PAM4 mode.
+ * @nrz_taps: taps for NRZ mode.
+ */
+struct hbl_cn_tx_taps {
+ s32 pam4_taps[PHY_TX_TAPS_NUM];
+ s32 nrz_taps[PHY_TX_TAPS_NUM];
+};
+
+/**
+ * struct hbl_cn_ber_info - holds the last calculated BER info for a specific lane.
+ * the BER (bit error rate) value is represented by "integer.frac * e ^ -exp".
+ * @integer: the integer part of the BER value.
+ * @frac: the fracture part of the BER value.
+ * @exp: the exponent part of the BER value.
+ * @valid: is info valid.
+ */
+struct hbl_cn_ber_info {
+ u64 integer;
+ u64 frac;
+ u8 exp;
+ u8 valid;
+};
+
+/**
+ * struct hbl_cn_macro - manage specific macro that holds multiple engines.
+ * @hdev: habanalabs device structure.
+ * @rec_link_sts: link status bits as received from the MAC_REC_STS0 register.
+ * @phy_macro_needs_reset: true if the PHY macro needs to be reset.
+ * @idx: index of the macro.
+ */
+struct hbl_cn_macro {
+ struct hbl_cn_device *hdev;
+ u32 rec_link_sts;
+ u8 phy_macro_needs_reset;
+ u8 idx;
+};
+
+/**
+ * struct hbl_cn_port - manage specific port common structure.
+ * @hdev: habanalabs device structure.
+ * @cn_specific: pointer to an ASIC specific port structure.
+ * @cn_macro: pointer to the manage structure of the containing macro.
+ * @wq: general purpose WQ for low/medium priority jobs like link status detection or status fetch.
+ * @qp_wq: QP work queue for handling the reset or destruction of QPs.
+ * @wq_arr_props: array per type of WQ array properties.
+ * @ev_dqs: per ASID/App events dispatch queues managed by the driver.
+ * @num_of_allocated_qps: the currently number of allocated qps for this port.
+ * @link_status_work: work for checking port link status.
+ * @fw_status_work: work for sending port status to the FW.
+ * @control_lock: protects from a race between port open/close and other stuff that might run in
+ * parallel (such as event handling).
+ * @cnt_lock: protects the counters from concurrent reading. Needed for SPMU and XPCS91 counters.
+ * @qp_ids: xarray to hold all QP IDs.
+ * @db_fifo_ids: Allocated doorbell fifo IDs.
+ * @cq_ids: xarray to hold all CQ IDs.
+ * @encap_ids: Allocated encapsulation IDs.
+ * @fw_tuning_limit_ts: time stamp of FW tuning time limit.
+ * @correctable_errors_cnt: count the correctable FEC blocks.
+ * @uncorrectable_errors_cnt: count the uncorrectable FEC blocks.
+ * @port: port index.
+ * @speed: the bandwidth of the port in Mb/s.
+ * @pflags: private flags bit mask.
+ * @retry_cnt: counts the number of retries during link establishment.
+ * @pcs_local_fault_cnt: counter of PCS link local errors since last F/W configuration. These errors
+ * can appear even when link is up.
+ * @pcs_remote_fault_cnt: counter of PCS link remote errors since last F/W configuration. These
+ * errors can appear even when link is up.
+ * @pcs_remote_fault_seq_cnt: counter for number of PCS remote faults in a row, or in other words
+ * the length of their sequence.
+ * @pcs_remote_fault_reconfig_cnt: counter of PHY reconfigurations due to remote fault errors since
+ * last port open.
+ * @pcs_link_restore_cnt: counter of PCS link momentary loss (glitch) since last F/W configuration.
+ * @data_rate: data rate according to speed and number of lanes.
+ * @num_of_wq_entries: number of entries configured in the port WQ.
+ * @num_of_wqs: number of WQs configured for this port.
+ * @qp_idx_offset: offset to the base QP index of this port for generic QPs.
+ * @port_toggle_cnt: counts number of times port link status was toggled since PHY init.
+ * @port_toggle_cnt_prev: holds the value of port_toggle_cnt in the last pcs link check.
+ * @cong_q_err_cnt: error count of congestion queue error.
+ * @port_open: true if the port H/W is initialized, false otherwise.
+ * @mac_loopback: true if port in MAC loopback mode, false otherwise.
+ * @pfc_enable: true if this port supports Priority Flow Control, false otherwise.
+ * @sw_initialized: true if the basic SW initialization was completed successfully for this port,
+ * false otherwise.
+ * @phy_fw_tuned: true if F/W is tuned, false otherwise.
+ * @phy_func_mode_en: true if PHY is set to functional mode, false otherwise.
+ * @pcs_link: true if the port has PCS link, false otherwise.
+ * @eq_pcs_link: true if the port got PCS link in the EQ, false otherwise..
+ * @link_eqe: cache link status EQE. Dispatched to user for internal ports only.
+ * @auto_neg_enable: true if this port supports Autonegotiation, false otherwise.
+ * @auto_neg_resolved: true if Autonegotiation was completed for this port, false otherwise.
+ * @auto_neg_skipped: true if Autonegotiation was skipped for this port, false otherwise.
+ * @eth_enable: is Ethernet traffic enabled in addition to RDMA.
+ * @ccq_enable: true if the CCQ was initialized successfully for this port, false otherwise.
+ * @set_app_params: set_app_params operation was executed by the user. This is a mandatory step in
+ * order to initialize the uAPI.
+ * @disabled: true if this port is disabled, i.e. need to block its initialization, false otherwise.
+ * @bp_enable: true if WQ back-pressure was enabled, false otherwise.
+ * @eq_handler_enable: true if event queue events are handled, false otherwise.
+ */
+struct hbl_cn_port {
+ struct hbl_cn_device *hdev;
+ void *cn_specific;
+ struct hbl_cn_macro *cn_macro;
+ struct workqueue_struct *wq;
+ struct workqueue_struct *qp_wq;
+ struct hbl_cn_wq_array_properties wq_arr_props[HBL_CNI_USER_WQ_TYPE_MAX];
+ struct hbl_cn_ev_dqs ev_dqs;
+ struct hbl_cn_reset_tracker *reset_tracker;
+ atomic_t num_of_allocated_qps;
+ struct delayed_work link_status_work;
+ struct delayed_work fw_status_work;
+ /* protects from a race between port open/close and event handling */
+ struct mutex control_lock;
+ /* protects the counters from concurrent reading */
+ struct mutex cnt_lock;
+ struct xarray qp_ids;
+ struct xarray db_fifo_ids;
+ struct xarray cq_ids;
+ struct xarray encap_ids;
+ struct hbl_cn_eqe link_eqe;
+ ktime_t fw_tuning_limit_ts;
+ u64 ccq_handle;
+ u64 ccq_pi_handle;
+ u64 correctable_errors_cnt;
+ u64 uncorrectable_errors_cnt;
+ u32 port;
+ u32 speed;
+ u32 pflags;
+ u32 retry_cnt;
+ u32 pcs_local_fault_cnt;
+ u32 pcs_remote_fault_seq_cnt;
+ u32 pcs_remote_fault_reconfig_cnt;
+ u32 pcs_remote_fault_cnt;
+ u32 pcs_link_restore_cnt;
+ u32 data_rate;
+ u32 num_of_wq_entries;
+ u32 num_of_wqs;
+ u32 qp_idx_offset;
+ u32 swqe_size;
+ u32 port_toggle_cnt;
+ u32 port_toggle_cnt_prev;
+ u32 cong_q_err_cnt;
+ u8 port_open;
+ u8 mac_loopback;
+ u8 pfc_enable;
+ u8 sw_initialized;
+ u8 phy_fw_tuned;
+ u8 phy_func_mode_en;
+ u8 pcs_link;
+ u8 eq_pcs_link;
+ u8 auto_neg_enable;
+ u8 auto_neg_resolved;
+ u8 auto_neg_skipped;
+ u8 eth_enable;
+ u8 ccq_enable;
+ u8 set_app_params;
+ u8 disabled;
+ u8 bp_enable;
+ u8 eq_handler_enable;
+};
+
+/**
+ * struct hbl_cn_comp_vm_info - Compute virtual memory info.
+ * @vm_info: VM info.
+ * @vm_handle: VM handle.
+ */
+struct hbl_cn_comp_vm_info {
+ struct hbl_cn_vm_info vm_info;
+ u64 vm_handle;
+};
+
+/**
+ * struct hbl_cn_ctx - user context common structure.
+ * @hdev: device structure.
+ * @user_vm_info: info of user compute VM.
+ * @driver_vm_info: info of driver compute VM.
+ * @lock: protects context from specific concurrent operations.
+ * @comp_handle: compute handle.
+ * @asid: ASID for accessing driver memory.
+ * @user_asid: ASID for accessing user memory:
+ */
+struct hbl_cn_ctx {
+ struct hbl_cn_device *hdev;
+ struct hbl_cn_comp_vm_info user_vm_info;
+ struct hbl_cn_comp_vm_info driver_vm_info;
+ /* protects context from specific concurrent operations */
+ struct mutex lock;
+ u64 comp_handle;
+ u32 asid;
+ u32 user_asid;
+};
+
+/**
+ * struct hbl_cn_properties - ASIC specific properties.
+ * @phy_base_addr: base address of the PHY.
+ * @nic_drv_addr: the base address of the memory in the device
+ * @nic_drv_size: the size of the memory in the device
+ * @nic_drv_base_addr: the aligned base address of the memory in the device
+ * @nic_drv_end_addr: the aligned end address of the memory in the device
+ * @txs_base_addr: base address of the ports timer cfg
+ * @txs_base_size: size of the ports timer cfg
+ * @wq_base_addr: base address of send and receive work-q
+ * @wq_base_size: base address of send and receive work-q
+ * @tmr_base_addr: base address of the macros timer cfg
+ * @tmr_base_size: size of the macros timer cfg
+ * @req_qpc_base_addr: the base address of a requester (sender) QP context buffer
+ * @req_qpc_base_size: the size of a requester (sender) QP context buffer
+ * @res_qpc_base_addr: the base address of a responder (receiver) QP context buffer
+ * @res_qpc_base_size: the size of a requester (receiver) QP context buffer
+ * @max_hw_qps_num: maximum number of QPs supported by HW.
+ * @max_qps_num: maximum number of QPs to allocate.
+ * @max_hw_user_wqs_num: maximum number of WQ entries supported by HW.
+ * @min_hw_user_wqs_num: minimum number of WQ entries supported by HW.
+ * @macro_cfg_size: the size of the macro configuration space.
+ * @rwqe_size: receive WQE size.
+ * @user_cq_min_entries: minimum number of supported user CQ entries.
+ * @user_cq_max_entries: max number of supported user CQ entries.
+ * @max_frm_len: maximum allowed frame length.
+ * @raw_elem_size: size of element in raw buffers.
+ * @status_packet_size: size of the status packet we are going to send to F/W.
+ * @cqe_size: Size of the Completion queue Entry.
+ * @max_qp_error_syndromes: maximum number of QP error syndromes.
+ * @max_raw_mtu: maximum MTU size for raw packets.
+ * @min_raw_mtu: minimum MTU size for raw packets.
+ * @clk: clock frequency in MHz.
+ * @force_cq: all CQs should be enabled regardless of the ports link mask.
+ * @max_num_of_lanes: maximum number of lanes supported by ASIC.
+ * @max_num_of_ports: maximum number of ports supported by ASIC.
+ * @num_of_macros: number of macros supported by ASIC.
+ * @max_cqs: maximum number of completion queues.
+ * @max_ccqs: maximum number of congestion control completion queues.
+ * @max_db_fifos: maximum number of DB fifos.
+ * @max_wq_arr_type: maximum WQ array type number.
+ * @is_phy_fw_binary: True if phy FW is in binary format, false otherwise.
+ */
+struct hbl_cn_properties {
+ u64 phy_base_addr;
+ u64 nic_drv_addr;
+ u64 nic_drv_size;
+ u64 nic_drv_base_addr;
+ u64 nic_drv_end_addr;
+ u64 txs_base_addr;
+ u64 txs_base_size;
+ u64 wq_base_addr;
+ u64 wq_base_size;
+ u64 tmr_base_addr;
+ u64 tmr_base_size;
+ u64 req_qpc_base_addr;
+ u64 req_qpc_base_size;
+ u64 res_qpc_base_addr;
+ u64 res_qpc_base_size;
+ u32 max_hw_qps_num;
+ u32 max_qps_num;
+ u32 max_hw_user_wqs_num;
+ u32 min_hw_user_wqs_num;
+ u32 macro_cfg_size;
+ u32 rwqe_size;
+ u32 user_cq_min_entries;
+ u32 user_cq_max_entries;
+ u32 max_frm_len;
+ u32 raw_elem_size;
+ u32 status_packet_size;
+ u32 cqe_size;
+ u32 max_qp_error_syndromes;
+ u16 max_raw_mtu;
+ u16 min_raw_mtu;
+ u16 clk;
+ u8 force_cq;
+ u8 max_num_of_lanes;
+ u8 max_num_of_ports;
+ u8 num_of_macros;
+ u8 max_cqs;
+ u8 max_ccqs;
+ u8 max_db_fifos;
+ u8 max_wq_arr_type;
+ u8 is_phy_fw_binary;
+};
+
+/**
+ * struct hbl_cn_device - habanalabs CN device structure.
+ * @pdev: pointer to PCI device.
+ * @dev: related kernel basic device structure.
+ * @cpucp_info: FW info.
+ * @asic_funcs: ASIC specific functions that can be called from common code.
+ * @phy_tx_taps: array that holds all PAM4 Tx taps of all lanes.
+ * @phy_ber_info: array that holds last calculated BER info of all lanes.
+ * @cn_ports: pointer to an array that holds all ports manage common structures.
+ * @cn_macros: pointer to an array that holds all macros manage structures.
+ * @wq_arrays_pool: memory pool for WQ arrays on HBM.
+ * @cn_props: fixed NIC properties.
+ * @asic_specific: ASIC specific information to use only from ASIC files.
+ * @cn_aux_dev: pointer to CN auxiliary device.
+ * @en_aux_dev: Ethernet auxiliary device.
+ * @ib_aux_dev: InfiniBand auxiliary device.
+ * @qp_info: details of a QP to read via debugfs.
+ * @wqe_info: details of a WQE to read via debugfs.
+ * @ctx: user context.
+ * @hw_access_lock: protects from HW access during reset flows.
+ * @asic_type: ASIC specific type.
+ * @status_cmd: status packet command from FW.
+ * @qp_reset_mode: Graceful/fast reset.
+ * @fw_ver: FW version.
+ * @mem_ids: an xarray holding all active memory handles.
+ * @ctrl_op_mask: mask of supported control operations.
+ * @ports_mask: mask of available ports.
+ * @ext_ports_mask: mask of external ports (subset of ports_mask).
+ * @phys_auto_neg_mask: mask of ports with Autonegotiation availability.
+ * @auto_neg_mask: mask of port with Autonegotiation enabled.
+ * @mac_loopback: enable MAC loopback on specific ports.
+ * @dram_size: available DRAM size.
+ * @mmap_type_flag: flag to indicate NIC MMAP type.
+ * @pol_tx_mask: bitmap of tx polarity for all lanes.
+ * @pol_rx_mask: bitmap of rx polarity for all lanes.
+ * @device_timeout: device access timeout in usec.
+ * @mac_lane_remap: MAC to PHY lane mapping.
+ * @pending_reset_long_timeout: Long timeout for pending hard reset to finish in seconds.
+ * @kernel_asid: kernel ASID.
+ * @qp_drain_time: drain waiting time in seconds after QP invalidation.
+ * @card_location: the OAM number in the HLS (relevant for PMC card type).
+ * @phy_port_to_dump: the port which its serdes params will be dumped.
+ * @fw_major_version: major version of current loaded preboot.
+ * @fw_minor_version: minor version of current loaded preboot.
+ * @qpc_cache_inv_timeout: timeout for QPC cache invalidation.
+ * @fw_app_cpu_boot_dev_sts0: bitmap representation of application security status reported by FW,
+ * bit description can be found in CPU_BOOT_DEV_STS0.
+ * @fw_app_cpu_boot_dev_sts1: bitmap representation of application security status reported by FW,
+ * bit description can be found in CPU_BOOT_DEV_STS1.
+ * @accumulate_fec_duration: Time (ms) to accumulate FEC errors for.
+ * @id: device ID.
+ * @phy_calc_ber_wait_sec: time in seconds to wait before BER calculation.
+ * @cache_line_size: device cache line size.
+ * @operational: is device operational.
+ * @in_reset: is device under reset.
+ * @fw_reset: is device under reset which was initiated by FW.
+ * @in_teardown: is device under teardown.
+ * @is_initialized: is device initialized.
+ * @pldm: is running on Palladium setup.
+ * @skip_phy_init: avoid writing/reading PHY registers.
+ * @load_phy_fw: true if the PHY F/W should be loaded, false otherwise.
+ * @cpucp_fw: is CPUCP FW enabled.
+ * @supports_coresight: is CoreSight supported.
+ * @use_fw_serdes_info: true if FW serdes values should be used, false if hard coded values should
+ * be used.
+ * @phy_config_fw: true if the PHY F/W should be configured, false otherwise. The PHY F/W should be
+ * configured on ASIC only, in contrary to Palladium.
+ * @mmu_bypass: use MMU bypass for allocated data structures (false is used only for debug mode).
+ * @wq_arrays_pool_enable: Use device memory pool for WQ arrays.
+ * @poll_enable: enable polling mode rather than interrupt mode.
+ * @has_eq: is event queue is supported.
+ * @skip_mac_reset: skip MAC reset.
+ * @skip_mac_cnts: Used to skip MAC counters if not supported.
+ * @skip_odd_ports_cfg_lock: do not lock the odd ports when acquiring the cfg lock for all ports.
+ * @ib_support: InfiniBand support.
+ * @mmu_enable: is MMU enabled.
+ * @eth_loopback: enable hack in hbl_en_handle_tx to test eth traffic.
+ * @lanes_per_port: number of physical lanes per port.
+ * @is_eth_aux_dev_initialized: true if the eth auxiliary device is initialized.
+ * @is_ib_aux_dev_initialized: true if the IB auxiliary device is initialized.
+ * @rx_drop_percent: RX packet drop percentage set via debugfs.
+ * @rand_status: randomize the FW status counters (used for testing).
+ * @status_period: periodic time in secs at which FW expects status packet.
+ * @phy_regs_print: print all PHY registers reads/writes.
+ * @phy_calc_ber: show PHY BER statistics during power-up.
+ * @is_decap_disabled: true if need to skip decapsulation, false otherwise.
+ * @phy_set_nrz: Set the PHY to NRZ mode (25Gbps speed).
+ * @skip_phy_default_tx_taps_cfg: Used to skip re-configuration of the default tx_taps.
+ * @cpucp_checkers_shift: CPUCP checkers flags shift.
+ * @mixed_qp_wq_types: Using mixed QP WQ types is supported.
+ * @hw_stop_during_teardown: Stopping the HW should take place during device teardown.
+ * @qp_wait_for_idle: Wait for QP to be idle.
+ * @hw_invalid_while_teardown: HW is unavailable during device teardown.
+ * @umr_support: device supports UMR.
+ * @ib_device_opened: Is true if IB deviced has been opened.
+ * @multi_ctx_support: device supports multiple contexts.
+ * @skip_phy_pol_cfg: Used to prevent overwriting polarity cfg after setting them via debugfs.
+ * @cc_support: device supports congestion control.
+ * @phy_force_first_tx_taps_cfg: start with first Tx taps config in PHY power-up.
+ */
+struct hbl_cn_device {
+ struct pci_dev *pdev;
+ struct device *dev;
+ struct hbl_cn_cpucp_info *cpucp_info;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct hbl_cn_tx_taps *phy_tx_taps;
+ struct hbl_cn_ber_info *phy_ber_info;
+ struct hbl_cn_port *cn_ports;
+ struct hbl_cn_macro *cn_macros;
+ struct gen_pool *wq_arrays_pool;
+ struct hbl_cn_properties cn_props;
+ void *asic_specific;
+ char *fw_ver;
+ struct hbl_aux_dev *cn_aux_dev;
+ struct hbl_aux_dev en_aux_dev;
+ struct hbl_aux_dev ib_aux_dev;
+ struct hbl_cn_qp_info qp_info;
+ struct hbl_cn_wqe_info wqe_info;
+ struct hbl_cn_ctx *ctx;
+ /* protects from HW access during reset flows */
+ struct mutex hw_access_lock;
+ enum hbl_cn_asic_type asic_type;
+ enum hbl_cn_status_cmd status_cmd;
+ enum hbl_cn_qp_reset_mode qp_reset_mode;
+ struct xarray mem_ids;
+ u64 ctrl_op_mask;
+ u64 ports_mask;
+ u64 ext_ports_mask;
+ u64 phys_auto_neg_mask;
+ u64 auto_neg_mask;
+ u64 mac_loopback;
+ u64 dram_size;
+ u64 mmap_type_flag;
+ u64 pol_tx_mask;
+ u64 pol_rx_mask;
+ u32 device_timeout;
+ u32 *mac_lane_remap;
+ u32 pending_reset_long_timeout;
+ u32 kernel_asid;
+ u32 qp_drain_time;
+ u32 card_location;
+ u32 phy_port_to_dump;
+ u32 fw_major_version;
+ u32 fw_minor_version;
+ u32 qpc_cache_inv_timeout;
+ u32 fw_app_cpu_boot_dev_sts0;
+ u32 fw_app_cpu_boot_dev_sts1;
+ u32 accumulate_fec_duration;
+ u16 id;
+ u16 phy_calc_ber_wait_sec;
+ u16 cache_line_size;
+ u8 operational;
+ u8 in_reset;
+ u8 fw_reset;
+ u8 in_teardown;
+ u8 is_initialized;
+ u8 pldm;
+ u8 skip_phy_init;
+ u8 load_phy_fw;
+ u8 cpucp_fw;
+ u8 supports_coresight;
+ u8 use_fw_serdes_info;
+ u8 phy_config_fw;
+ u8 mmu_bypass;
+ u8 wq_arrays_pool_enable;
+ u8 poll_enable;
+ u8 has_eq;
+ u8 skip_mac_reset;
+ u8 skip_mac_cnts;
+ u8 skip_odd_ports_cfg_lock;
+ u8 ib_support;
+ u8 mmu_enable;
+ u8 eth_loopback;
+ u8 lanes_per_port;
+ u8 is_eth_aux_dev_initialized;
+ u8 is_ib_aux_dev_initialized;
+ u8 rx_drop_percent;
+ u8 rand_status;
+ u8 status_period;
+ u8 phy_regs_print;
+ u8 phy_calc_ber;
+ u8 is_decap_disabled;
+ u8 phy_set_nrz;
+ u8 skip_phy_default_tx_taps_cfg;
+ u8 cpucp_checkers_shift;
+ u8 mixed_qp_wq_types;
+ u8 hw_stop_during_teardown;
+ u8 qp_wait_for_idle;
+ u8 hw_invalid_while_teardown;
+ u8 umr_support;
+ u8 ib_device_opened;
+ u8 multi_ctx_support;
+ u8 skip_phy_pol_cfg;
+ u8 cc_support;
+ u8 phy_force_first_tx_taps_cfg;
+};
+
+static inline void hbl_cn_strtolower(char *str)
+{
+ while (*str) {
+ *str = tolower(*str);
+ str++;
+ }
+}
+
+int hbl_cn_dev_init(struct hbl_cn_device *hdev);
+void hbl_cn_dev_fini(struct hbl_cn_device *hdev);
+bool hbl_cn_comp_device_operational(struct hbl_cn_device *hdev);
+void hbl_cn_spmu_get_stats_info(struct hbl_cn_port *cn_port, struct hbl_cn_stat **stats,
+ u32 *n_stats);
+int hbl_cn_reserve_dva_block(struct hbl_cn_ctx *ctx, u64 size, u64 *dva);
+void hbl_cn_unreserve_dva_block(struct hbl_cn_ctx *ctx, u64 dva, u64 size);
+int hbl_cn_get_hw_block_handle(struct hbl_cn_device *hdev, u64 address, u64 *handle);
+int hbl_cn_send_cpucp_packet(struct hbl_cn_device *hdev, u32 port, enum cpucp_packet_id pkt_id,
+ int val);
+int hbl_cn_internal_port_init_locked(struct hbl_cn_port *cn_port);
+void hbl_cn_internal_port_fini_locked(struct hbl_cn_port *cn_port);
+int hbl_cn_phy_init(struct hbl_cn_port *cn_port);
+void hbl_cn_phy_fini(struct hbl_cn_port *cn_port);
+void hbl_cn_phy_port_reconfig(struct hbl_cn_port *cn_port);
+int hbl_cn_phy_has_binary_fw(struct hbl_cn_device *hdev);
+void hbl_cn_phy_set_fw_polarity(struct hbl_cn_device *hdev);
+void hbl_cn_phy_set_port_status(struct hbl_cn_port *cn_port, bool up);
+int hbl_cn_read_spmu_counters(struct hbl_cn_port *cn_port, u64 out_data[], u32 *num_out_data);
+int hbl_cn_qp_modify(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp,
+ enum hbl_cn_qp_state new_state, void *params);
+u32 hbl_cn_get_max_qp_id(struct hbl_cn_port *cn_port);
+bool hbl_cn_is_port_open(struct hbl_cn_port *cn_port);
+u32 hbl_cn_get_pflags(struct hbl_cn_port *cn_port);
+u8 hbl_cn_get_num_of_digits(u64 num);
+void hbl_cn_reset_stats_counters(struct hbl_cn_device *hdev);
+void hbl_cn_reset_ports_toggle_counters(struct hbl_cn_device *hdev);
+void hbl_cn_get_self_hw_block_handle(struct hbl_cn_device *hdev, u64 address, u64 *handle);
+u32 hbl_cn_hw_block_handle_to_addr32(struct hbl_cn_device *hdev, u64 handle);
+
+struct hbl_cn_ev_dq *hbl_cn_asid_to_dq(struct hbl_cn_ev_dqs *ev_dqs, u32 asid);
+struct hbl_cn_ev_dq *hbl_cn_dbn_to_dq(struct hbl_cn_ev_dqs *ev_dqs, u32 dbn,
+ struct hbl_cn_device *hdev);
+struct hbl_cn_ev_dq *hbl_cn_qpn_to_dq(struct hbl_cn_ev_dqs *ev_dqs, u32 qpn);
+struct hbl_cn_dq_qp_info *hbl_cn_get_qp_info(struct hbl_cn_ev_dqs *ev_dqs, u32 qpn);
+struct hbl_cn_ev_dq *hbl_cn_cqn_to_dq(struct hbl_cn_ev_dqs *ev_dqs,
+ u32 cqn, struct hbl_cn_device *hdev);
+struct hbl_cn_ev_dq *hbl_cn_ccqn_to_dq(struct hbl_cn_ev_dqs *ev_dqs, u32 ccqn,
+ struct hbl_cn_device *hdev);
+
+int hbl_cn_reserve_wq_dva(struct hbl_cn_ctx *ctx, struct hbl_cn_port *cn_port, u64 wq_arr_size,
+ u32 type, u64 *dva);
+void hbl_cn_unreserve_wq_dva(struct hbl_cn_ctx *ctx, struct hbl_cn_port *cn_port, u32 type);
+u32 hbl_cn_get_wq_array_type(bool is_send);
+
+void hbl_cn_track_port_reset(struct hbl_cn_port *cn_port, u32 syndrome);
+int hbl_cn_get_reg_pcie_addr(struct hbl_cn_device *hdev, u8 bar_id, u32 reg, u64 *pci_addr);
+void hbl_cn_ports_cancel_status_work(struct hbl_cn_device *hdev);
+
+/* Memory related functions */
+int hbl_cn_mem_alloc(struct hbl_cn_ctx *ctx, struct hbl_cn_mem_data *mem_data);
+int hbl_cn_mem_destroy(struct hbl_cn_device *hdev, u64 handle);
+struct hbl_cn_mem_buf *hbl_cn_mem_buf_get(struct hbl_cn_device *hdev, u64 handle);
+int hbl_cn_mem_buf_put(struct hbl_cn_mem_buf *buf);
+int hbl_cn_mem_buf_put_handle(struct hbl_cn_device *hdev, u64 handle);
+void hbl_cn_mem_init(struct hbl_cn_device *hdev);
+void hbl_cn_mem_fini(struct hbl_cn_device *hdev);
+
+u32 hbl_cn_dram_readl(struct hbl_cn_device *hdev, u64 addr);
+void hbl_cn_dram_writel(struct hbl_cn_device *hdev, u32 val, u64 addr);
+u32 hbl_cn_rreg(struct hbl_cn_device *hdev, u32 reg);
+void hbl_cn_wreg(struct hbl_cn_device *hdev, u32 reg, u32 val);
+void hbl_cn_get_frac_info(u64 numerator, u64 denominator, u64 *integer, u64 *exp);
+
+bool hbl_cn_eq_dispatcher_is_empty(struct hbl_cn_ev_dq *dq);
+bool hbl_cn_eq_dispatcher_is_full(struct hbl_cn_ev_dq *dq);
+void hbl_cn_eq_dispatcher_init(struct hbl_cn_port *cn_port);
+void hbl_cn_eq_dispatcher_fini(struct hbl_cn_port *cn_port);
+void hbl_cn_eq_dispatcher_reset(struct hbl_cn_port *cn_port);
+int hbl_cn_eq_dispatcher_associate_dq(struct hbl_cn_port *cn_port, u32 asid);
+int hbl_cn_eq_dispatcher_dissociate_dq(struct hbl_cn_port *cn_port, u32 asid);
+int hbl_cn_eq_dispatcher_register_qp(struct hbl_cn_port *cn_port, u32 asid, u32 qp_id);
+int hbl_cn_eq_dispatcher_unregister_qp(struct hbl_cn_port *cn_port, u32 qp_id);
+int hbl_cn_eq_dispatcher_register_cq(struct hbl_cn_port *cn_port, u32 asid, u32 cqn);
+int hbl_cn_eq_dispatcher_unregister_cq(struct hbl_cn_port *cn_port, u32 cqn);
+int hbl_cn_eq_dispatcher_register_db(struct hbl_cn_port *cn_port, u32 asid, u32 dbn);
+int hbl_cn_eq_dispatcher_unregister_db(struct hbl_cn_port *cn_port, u32 dbn);
+int hbl_cn_eq_dispatcher_dequeue(struct hbl_cn_port *cn_port, u32 asid,
+ struct hbl_cn_eqe *eqe, bool is_default);
+int hbl_cn_eq_dispatcher_register_ccq(struct hbl_cn_port *cn_port, u32 asid, u32 ccqn);
+int hbl_cn_eq_dispatcher_unregister_ccq(struct hbl_cn_port *cn_port, u32 asid, u32 ccqn);
+int hbl_cn_eq_dispatcher_enqueue(struct hbl_cn_port *cn_port, const struct hbl_cn_eqe *eqe);
+int hbl_cn_eq_dispatcher_enqueue_bcast(struct hbl_cn_port *cn_port, const struct hbl_cn_eqe *eqe);
+void hbl_cn_eq_handler(struct hbl_cn_port *cn_port);
+int hbl_cn_alloc_ring(struct hbl_cn_device *hdev, struct hbl_cn_ring *ring, int elem_size,
+ int count);
+void hbl_cn_free_ring(struct hbl_cn_device *hdev, struct hbl_cn_ring *ring);
+
+struct hbl_cn_user_cq *hbl_cn_user_cq_get(struct hbl_cn_port *cn_port, u8 cq_id);
+int hbl_cn_user_cq_put(struct hbl_cn_user_cq *user_cq);
+bool hbl_cn_is_ibdev(struct hbl_cn_device *hdev);
+void hbl_cn_hard_reset_prepare(struct hbl_aux_dev *cn_aux_dev, bool fw_reset, bool in_teardown);
+int hbl_cn_send_port_cpucp_status(struct hbl_aux_dev *aux_dev, u32 port, u8 cmd, u8 period);
+void hbl_cn_fw_status_work(struct work_struct *work);
+int hbl_cn_get_src_ip(struct hbl_cn_port *cn_port, u32 *src_ip);
+void hbl_cn_ctx_resources_destroy(struct hbl_cn_device *hdev, struct hbl_cn_ctx *ctx);
+
+int __hbl_cn_ports_reopen(struct hbl_cn_device *hdev);
+void __hbl_cn_hard_reset_prepare(struct hbl_cn_device *hdev, bool fw_reset, bool in_teardown);
+void __hbl_cn_stop(struct hbl_cn_device *hdev);
+
+/* DMA memory allocations */
+void *__hbl_cn_dma_alloc_coherent(struct hbl_cn_device *hdev, size_t size, dma_addr_t *dma_handle,
+ gfp_t flag, const char *caller);
+void __hbl_cn_dma_free_coherent(struct hbl_cn_device *hdev, size_t size, void *cpu_addr,
+ dma_addr_t dma_addr, const char *caller);
+void *__hbl_cn_dma_pool_zalloc(struct hbl_cn_device *hdev, size_t size, gfp_t mem_flags,
+ dma_addr_t *dma_handle, const char *caller);
+void __hbl_cn_dma_pool_free(struct hbl_cn_device *hdev, void *vaddr, dma_addr_t dma_addr,
+ const char *caller);
+
+#endif /* HABANALABS_CN_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_drv.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_drv.c
new file mode 100644
index 000000000000..47eedd27f36e
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_drv.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#define pr_fmt(fmt) "habanalabs_cn: " fmt
+
+#include "hbl_cn.h"
+
+#include <linux/module.h>
+#include <linux/auxiliary_bus.h>
+#include <linux/sched/clock.h>
+
+#define HBL_DRIVER_AUTHOR "HabanaLabs Kernel Driver Team"
+
+#define HBL_DRIVER_DESC "HabanaLabs AI accelerators Core Network driver"
+
+MODULE_AUTHOR(HBL_DRIVER_AUTHOR);
+MODULE_DESCRIPTION(HBL_DRIVER_DESC);
+MODULE_LICENSE("GPL");
+
+/* QP drain time in seconds */
+#define HBL_CN_QP_DRAIN_TIME 5
+
+static bool poll_enable;
+static uint qp_drain_time = HBL_CN_QP_DRAIN_TIME;
+
+module_param(poll_enable, bool, 0444);
+MODULE_PARM_DESC(poll_enable,
+ "Enable driver in polling mode rather than IRQ (0 = no, 1 = yes, default: no)");
+
+module_param(qp_drain_time, uint, 0444);
+MODULE_PARM_DESC(qp_drain_time, "QP drain time in seconds after QP invalidation (default: 2)");
+
+static int hdev_init(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_cn_aux_data *aux_data = aux_dev->aux_data;
+ struct hbl_cn_device *hdev;
+ int rc;
+
+ hdev = kzalloc(sizeof(*hdev), GFP_KERNEL);
+ if (!hdev)
+ return -ENOMEM;
+
+ hdev->cpucp_info = kzalloc(sizeof(*hdev->cpucp_info), GFP_KERNEL);
+ if (!hdev->cpucp_info) {
+ rc = -ENOMEM;
+ goto free_hdev;
+ }
+
+ aux_dev->priv = hdev;
+ hdev->cn_aux_dev = aux_dev;
+ hdev->pdev = aux_data->pdev;
+ hdev->dev = aux_data->dev;
+ hdev->asic_type = aux_data->asic_type;
+ hdev->pending_reset_long_timeout = aux_data->pending_reset_long_timeout;
+ hdev->pldm = aux_data->pldm;
+ hdev->skip_phy_init = aux_data->skip_phy_init;
+ hdev->cpucp_fw = aux_data->cpucp_fw;
+ hdev->load_phy_fw = aux_data->load_phy_fw;
+ hdev->supports_coresight = aux_data->supports_coresight;
+ hdev->use_fw_serdes_info = aux_data->use_fw_serdes_info;
+ hdev->fw_ver = aux_data->fw_ver;
+ hdev->id = aux_data->id;
+ hdev->dram_size = aux_data->dram_size;
+ hdev->ports_mask = aux_data->ports_mask;
+ hdev->ext_ports_mask = aux_data->ext_ports_mask;
+ hdev->phys_auto_neg_mask = aux_data->auto_neg_mask;
+ hdev->cache_line_size = aux_data->cache_line_size;
+ hdev->kernel_asid = aux_data->kernel_asid;
+ hdev->qp_drain_time = qp_drain_time;
+ hdev->card_location = aux_data->card_location;
+ hdev->mmu_enable = aux_data->mmu_enable;
+ hdev->lanes_per_port = aux_data->lanes_per_port;
+ hdev->device_timeout = aux_data->device_timeout;
+ hdev->fw_major_version = aux_data->fw_major_version;
+ hdev->fw_minor_version = aux_data->fw_minor_version;
+ hdev->fw_app_cpu_boot_dev_sts0 = aux_data->fw_app_cpu_boot_dev_sts0;
+ hdev->fw_app_cpu_boot_dev_sts1 = aux_data->fw_app_cpu_boot_dev_sts1;
+ hdev->cpucp_checkers_shift = aux_data->cpucp_checkers_shift;
+ hdev->accumulate_fec_duration = ACCUMULATE_FEC_STATS_DURATION_MS;
+ hdev->poll_enable = poll_enable;
+
+ mutex_init(&hdev->hw_access_lock);
+
+ return 0;
+
+free_hdev:
+ kfree(hdev);
+ return rc;
+}
+
+static void hdev_fini(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_cn_device *hdev = aux_dev->priv;
+
+ mutex_destroy(&hdev->hw_access_lock);
+
+ kfree(hdev->cpucp_info);
+ kfree(hdev);
+ aux_dev->priv = NULL;
+}
+
+static const struct auxiliary_device_id hbl_cn_id_table[] = {
+ { .name = "habanalabs.cn", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(auxiliary, hbl_cn_id_table);
+
+static int hbl_cn_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
+{
+ struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
+ struct hbl_cn_aux_ops *aux_ops = aux_dev->aux_ops;
+ struct hbl_cn_device *hdev;
+ ktime_t timeout;
+ int rc;
+
+ rc = hdev_init(aux_dev);
+ if (rc) {
+ dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
+ return -EIO;
+ }
+
+ hdev = aux_dev->priv;
+
+ /* don't allow module unloading while it is attached */
+ if (!try_module_get(THIS_MODULE)) {
+ dev_err(hdev->dev, "Failed to increment %s module refcount\n",
+ module_name(THIS_MODULE));
+ rc = -EIO;
+ goto module_get_err;
+ }
+
+ timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
+ while (1) {
+ aux_ops->hw_access_lock(aux_dev);
+
+ /* if the device is operational, proceed to actual init while holding the lock in
+ * order to prevent concurrent hard reset
+ */
+ if (aux_ops->device_operational(aux_dev))
+ break;
+
+ aux_ops->hw_access_unlock(aux_dev);
+
+ if (ktime_compare(ktime_get(), timeout) > 0) {
+ dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
+ rc = -EBUSY;
+ goto timeout_err;
+ }
+
+ dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing CN\n");
+
+ msleep_interruptible(MSEC_PER_SEC);
+ }
+
+ rc = hbl_cn_dev_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init CN device\n");
+ goto dev_init_err;
+ }
+
+ aux_ops->hw_access_unlock(aux_dev);
+
+ return 0;
+
+dev_init_err:
+ aux_ops->hw_access_unlock(aux_dev);
+timeout_err:
+ module_put(THIS_MODULE);
+module_get_err:
+ hdev_fini(aux_dev);
+
+ return rc;
+}
+
+/* This function can be called only from the compute driver when deleting the aux bus, because we
+ * incremented the module refcount on probing. Hence no need to protect here from hard reset.
+ */
+static void hbl_cn_remove(struct auxiliary_device *adev)
+{
+ struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
+ struct hbl_cn_device *hdev = aux_dev->priv;
+
+ if (!hdev)
+ return;
+
+ hbl_cn_dev_fini(hdev);
+
+ /* allow module unloading as now it is detached */
+ module_put(THIS_MODULE);
+
+ hdev_fini(aux_dev);
+}
+
+static struct auxiliary_driver hbl_cn_driver = {
+ .name = "cn",
+ .probe = hbl_cn_probe,
+ .remove = hbl_cn_remove,
+ .id_table = hbl_cn_id_table,
+};
+
+static int __init hbl_cn_init(void)
+{
+ pr_info("loading driver\n");
+
+ return auxiliary_driver_register(&hbl_cn_driver);
+}
+
+static void __exit hbl_cn_exit(void)
+{
+ auxiliary_driver_unregister(&hbl_cn_driver);
+
+ pr_info("driver removed\n");
+}
+
+module_init(hbl_cn_init);
+module_exit(hbl_cn_exit);
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_memory.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_memory.c
new file mode 100644
index 000000000000..93c97fad6a20
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_memory.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "hbl_cn.h"
+
+int hbl_cn_mem_alloc(struct hbl_cn_ctx *ctx, struct hbl_cn_mem_data *mem_data)
+{
+ return 0;
+}
+
+int hbl_cn_mem_destroy(struct hbl_cn_device *hdev, u64 handle)
+{
+ return 0;
+}
+
+struct hbl_cn_mem_buf *hbl_cn_mem_buf_get(struct hbl_cn_device *hdev, u64 handle)
+{
+ return NULL;
+}
+
+int hbl_cn_mem_buf_put(struct hbl_cn_mem_buf *buf)
+{
+ return 0;
+}
+
+int hbl_cn_mem_buf_put_handle(struct hbl_cn_device *hdev, u64 handle)
+{
+ return 0;
+}
+
+void hbl_cn_mem_init(struct hbl_cn_device *hdev)
+{
+}
+
+void hbl_cn_mem_fini(struct hbl_cn_device *hdev)
+{
+}
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_phy.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_phy.c
new file mode 100644
index 000000000000..0d07cd78221d
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_phy.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "hbl_cn.h"
+
+void hbl_cn_phy_set_port_status(struct hbl_cn_port *cn_port, bool up)
+{
+}
+
+int hbl_cn_phy_init(struct hbl_cn_port *cn_port)
+{
+ return 0;
+}
+
+void hbl_cn_phy_fini(struct hbl_cn_port *cn_port)
+{
+}
+
+void hbl_cn_phy_port_reconfig(struct hbl_cn_port *cn_port)
+{
+}
+
+int hbl_cn_phy_has_binary_fw(struct hbl_cn_device *hdev)
+{
+ return 0;
+}
+
+void hbl_cn_phy_set_fw_polarity(struct hbl_cn_device *hdev)
+{
+}
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
new file mode 100644
index 000000000000..9ddc23bf8194
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "hbl_cn.h"
+
+int hbl_cn_qp_modify(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp,
+ enum hbl_cn_qp_state new_state, void *params)
+{
+ return 0;
+}
diff --git a/include/linux/habanalabs/cpucp_if.h b/include/linux/habanalabs/cpucp_if.h
index f316c8d0f3fc..7fe3f3e68b04 100644
--- a/include/linux/habanalabs/cpucp_if.h
+++ b/include/linux/habanalabs/cpucp_if.h
@@ -366,6 +366,27 @@ struct hl_eq_addr_dec_intr_data {
__u8 pad[7];
};
+#define MAX_PORTS_PER_NIC 4
+
+/* NIC interrupt type */
+enum hl_nic_interrupt_type {
+ NIC_INTR_NONE = 0,
+ NIC_INTR_TMR = 1,
+ NIC_INTR_RXB_CORE_SPI,
+ NIC_INTR_RXB_CORE_SEI,
+ NIC_INTR_QPC_RESP_ERR,
+ NIC_INTR_RXE_SPI,
+ NIC_INTR_RXE_SEI,
+ NIC_INTR_TXS,
+ NIC_INTR_TXE,
+};
+
+struct hl_eq_nic_intr_cause {
+ __le32 intr_type; /* enum hl_nic_interrupt_type */
+ __le32 pad;
+ struct hl_eq_intr_cause intr_cause[MAX_PORTS_PER_NIC];
+};
+
struct hl_eq_entry {
struct hl_eq_header hdr;
union {
@@ -382,6 +403,7 @@ struct hl_eq_entry {
struct hl_eq_hbm_sei_data sei_data; /* Gaudi2 HBM */
struct hl_eq_engine_arc_intr_data arc_data;
struct hl_eq_addr_dec_intr_data addr_dec;
+ struct hl_eq_nic_intr_cause nic_intr_cause;
__le64 data[7];
};
};
@@ -665,6 +687,9 @@ enum pq_init_status {
* by the host to prevent replay attacks. public key and certificate also
* provided as part of the FW response.
*
+ * CPUCP_PACKET_NIC_SET_CHECKERS -
+ * Packet to set a specific NIC checker bit.
+ *
* CPUCP_PACKET_MONITOR_DUMP_GET -
* Get monitors registers dump from the CpuCP kernel.
* The CPU will put the registers dump in the a buffer allocated by the driver
@@ -673,6 +698,14 @@ enum pq_init_status {
* data corruption in case of mismatched driver/FW versions.
* Obsolete.
*
+ * CPUCP_PACKET_NIC_WQE_ASID_SET -
+ * Packet to set nic wqe asid as the registers needed are privilege and to be configured by FW
+ *
+ * CPUCP_PACKET_NIC_ECC_INTRS_UNMASK -
+ * Packet to unmask NIC memory registers which are masked at preboot stage. As per the Arch
+ * team recommendation, NIC memory ECC errors should be unmasked after NIC driver is up and
+ * running
+ *
* CPUCP_PACKET_GENERIC_PASSTHROUGH -
* Generic opcode for all firmware info that is only passed to host
* through the LKD, without getting parsed there.
@@ -681,12 +714,28 @@ enum pq_init_status {
* LKD sends FW indication whether device is free or in use, this indication is reported
* also to the BMC.
*
+ * CPUCP_PACKET_NIC_MAC_TX_RESET -
+ * Packet to reset the NIC MAC Tx.
+ *
+ * CPUCP_PACKET_NIC_WQE_ASID_UNSET -
+ * Packet to unset nic wqe asid as the registers needed are privilege and to be configured
+ * by FW.
+ *
* CPUCP_PACKET_SOFT_RESET -
* Packet to perform soft-reset.
*
* CPUCP_PACKET_INTS_REGISTER -
* Packet to inform FW that queues have been established and LKD is ready to receive
* EQ events.
+ *
+ * CPUCP_PACKET_NIC_INIT_TXS_MEM -
+ * Init TXS related memory in HBM.
+ *
+ * CPUCP_PACKET_NIC_INIT_TMR_MEM -
+ * Init HW timer related memory in HBM.
+ *
+ * CPUCP_PACKET_NIC_CLR_MEM -
+ * Clear NIC related memory in HBM.
*/
enum cpucp_packet_id {
@@ -740,21 +789,24 @@ enum cpucp_packet_id {
CPUCP_PACKET_RESERVED2, /* not used */
CPUCP_PACKET_SEC_ATTEST_GET, /* internal */
CPUCP_PACKET_INFO_SIGNED_GET, /* internal */
- CPUCP_PACKET_RESERVED4, /* not used */
+ CPUCP_PACKET_NIC_SET_CHECKERS, /* internal */
CPUCP_PACKET_MONITOR_DUMP_GET, /* debugfs */
- CPUCP_PACKET_RESERVED5, /* not used */
- CPUCP_PACKET_RESERVED6, /* not used */
- CPUCP_PACKET_RESERVED7, /* not used */
+ CPUCP_PACKET_RESERVED3, /* not used */
+ CPUCP_PACKET_NIC_WQE_ASID_SET, /* internal */
+ CPUCP_PACKET_NIC_ECC_INTRS_UNMASK, /* internal */
CPUCP_PACKET_GENERIC_PASSTHROUGH, /* IOCTL */
- CPUCP_PACKET_RESERVED8, /* not used */
+ CPUCP_PACKET_RESERVED4, /* not used */
CPUCP_PACKET_ACTIVE_STATUS_SET, /* internal */
- CPUCP_PACKET_RESERVED9, /* not used */
- CPUCP_PACKET_RESERVED10, /* not used */
- CPUCP_PACKET_RESERVED11, /* not used */
- CPUCP_PACKET_RESERVED12, /* internal */
- CPUCP_PACKET_RESERVED13, /* internal */
+ CPUCP_PACKET_NIC_MAC_TX_RESET, /* internal */
+ CPUCP_PACKET_RESERVED5, /* not used */
+ CPUCP_PACKET_NIC_WQE_ASID_UNSET, /* internal */
+ CPUCP_PACKET_RESERVED6, /* internal */
+ CPUCP_PACKET_RESERVED7, /* internal */
CPUCP_PACKET_SOFT_RESET, /* internal */
CPUCP_PACKET_INTS_REGISTER, /* internal */
+ CPUCP_PACKET_NIC_INIT_TXS_MEM, /* internal */
+ CPUCP_PACKET_NIC_INIT_TMR_MEM, /* internal */
+ CPUCP_PACKET_NIC_CLR_MEM, /* internal */
CPUCP_PACKET_ID_MAX /* must be last */
};
@@ -862,6 +914,9 @@ struct cpucp_packet {
/* For NIC requests */
__le32 port_index;
+ /* For NIC requests */
+ __le32 macro_index;
+
/* For Generic packet sub index */
__le32 pkt_subidx;
};
@@ -1058,6 +1113,21 @@ enum pvt_index {
PVT_NE
};
+#define NIC_CHECKERS_TYPE_SHIFT 0
+#define NIC_CHECKERS_TYPE_MASK 0xFFFF
+#define NIC_CHECKERS_CHECK_SHIFT 16
+#define NIC_CHECKERS_CHECK_MASK 0x1
+#define NIC_CHECKERS_DROP_SHIFT 17
+#define NIC_CHECKERS_DROP_MASK 0x1
+
+enum nic_checkers_types {
+ RX_PKT_BAD_FORMAT = 0,
+ RX_INV_OPCODE,
+ RX_INV_SYNDROME,
+ RX_WQE_IDX_MISMATCH,
+ TX_WQE_IDX_MISMATCH = 0x80
+};
+
/* Event Queue Packets */
struct eq_generic_event {
@@ -1273,6 +1343,7 @@ struct ser_val {
* @post_fec_ser: post FEC SER value.
* @throughput: measured throughput.
* @latency: measured latency.
+ * @port_toggle_cnt: counts how many times the link toggled since last port PHY init.
*/
struct cpucp_nic_status {
__le32 port;
@@ -1292,6 +1363,8 @@ struct cpucp_nic_status {
struct ser_val post_fec_ser;
struct frac_val bandwidth;
struct frac_val lat;
+ __le32 port_toggle_cnt;
+ __u8 reserved[4];
};
enum cpucp_hbm_row_replace_cause {
@@ -1420,4 +1493,36 @@ enum hl_passthrough_type {
HL_PASSTHROUGH_VERSIONS,
};
+/* structure cpucp_cn_init_hw_mem_packet - used for initializing the associated CN (Core Network)
+ * hw(TIMER, TX-SCHEDQ) memory in HBM using the provided parameters.
+ * @cpucp_pkt: basic cpucp packet, the rest of the parameters extend the packet.
+ * @mem_base_addr: base address of the associated memory
+ * @num_entries: number of entries.
+ * @entry_size: size of entry.
+ * @granularity: base value for first element.
+ * @pad: padding
+ */
+struct cpucp_cn_init_hw_mem_packet {
+ struct cpucp_packet cpucp_pkt;
+ __le64 mem_base_addr;
+ __le16 num_entries;
+ __le16 entry_size;
+ __le16 granularity;
+ __u8 pad[2];
+};
+
+/* structure cpucp_cn_clear_mem_packet - used for clearing the associated CN (Core Network)
+ * memory in HBM using the provided parameters.
+ * @cpucp_pkt: basic cpucp packet, the rest of the parameters extend the packet.
+ * @mem_base_addr: base address of the associated memory
+ * @size: size in bytes of the associated memory.
+ * @pad: padding
+ */
+struct cpucp_cn_clear_mem_packet {
+ struct cpucp_packet cpucp_pkt;
+ __le64 mem_base_addr;
+ __le32 size;
+ __u8 pad[4];
+};
+
#endif /* CPUCP_IF_H */
diff --git a/include/linux/habanalabs/hl_boot_if.h b/include/linux/habanalabs/hl_boot_if.h
index 93366d5621fd..a6d9e510a974 100644
--- a/include/linux/habanalabs/hl_boot_if.h
+++ b/include/linux/habanalabs/hl_boot_if.h
@@ -194,6 +194,7 @@ enum cpu_boot_dev_sts {
CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN = 24,
CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN = 25,
CPU_BOOT_DEV_STS_MAP_HWMON_EN = 26,
+ CPU_BOOT_DEV_STS_NIC_MEM_CLEAR_EN = 27,
CPU_BOOT_DEV_STS_ENABLED = 31,
CPU_BOOT_DEV_STS_SCND_EN = 63,
CPU_BOOT_DEV_STS_LAST = 64 /* we have 2 registers of 32 bits */
@@ -331,6 +332,11 @@ enum cpu_boot_dev_sts {
* HWMON enum mapping to cpucp enums.
* Initialized in: linux
*
+ * CPU_BOOT_DEV_STS0_NIC_MEM_CLEAR_EN
+ * If set, means f/w supports nic hbm memory clear and
+ * tmr,txs hbm memory init.
+ * Initialized in: zephyr-mgmt
+ *
* CPU_BOOT_DEV_STS0_ENABLED Device status register enabled.
* This is a main indication that the
* running FW populates the device status
@@ -367,6 +373,7 @@ enum cpu_boot_dev_sts {
#define CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN)
#define CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN (1 << CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN)
#define CPU_BOOT_DEV_STS0_MAP_HWMON_EN (1 << CPU_BOOT_DEV_STS_MAP_HWMON_EN)
+#define CPU_BOOT_DEV_STS0_NIC_MEM_CLEAR_EN (1 << CPU_BOOT_DEV_STS_NIC_MEM_CLEAR_EN)
#define CPU_BOOT_DEV_STS0_ENABLED (1 << CPU_BOOT_DEV_STS_ENABLED)
#define CPU_BOOT_DEV_STS1_ENABLED (1 << CPU_BOOT_DEV_STS_ENABLED)
@@ -403,7 +410,7 @@ enum kmd_msg {
KMD_MSG_GOTO_WFE,
KMD_MSG_FIT_RDY,
KMD_MSG_SKIP_BMC,
- RESERVED,
+ KMD_MSG_RESERVED,
KMD_MSG_RST_DEV,
KMD_MSG_LAST
};
diff --git a/include/linux/net/intel/cn.h b/include/linux/net/intel/cn.h
new file mode 100644
index 000000000000..d040b0bbd94c
--- /dev/null
+++ b/include/linux/net/intel/cn.h
@@ -0,0 +1,474 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#ifndef HBL_CN_H_
+#define HBL_CN_H_
+
+#include <linux/types.h>
+#include <linux/sizes.h>
+#include <linux/net/intel/cn_aux.h>
+
+#define HBL_EN_PFC_PRIO_NUM 4
+#define CQ_ARM_TIMEOUT_USEC 10
+
+struct qpc_mask;
+
+/**
+ * enum hbl_cn_pflags - mutable capabilities of the port.
+ * PFLAGS_PCS_LINK_CHECK: check for PCS link periodically.
+ * PFLAGS_PHY_AUTO_NEG_LPBK: allow Autonegotiation in loopback.
+ */
+enum hbl_cn_pflags {
+ PFLAGS_PCS_LINK_CHECK = BIT(0),
+ PFLAGS_PHY_AUTO_NEG_LPBK = BIT(1),
+};
+
+enum hbl_ts_type {
+ TS_RC = 0,
+ TS_RAW = 1
+};
+
+enum hbl_trust_level {
+ UNSECURED = 0,
+ SECURED = 1,
+ PRIVILEGE = 2
+};
+
+/**
+ * enum qpc_req_wq_type - QP REQ WQ type.
+ * @QPC_REQ_WQ_TYPE_WRITE: WRITE, "native" SEND, RECV-RDV or READ-RDV operations are allowed.
+ * @QPC_REQ_WQ_TYPE_RDV_READ: No operation is allowed on this endpoint QP.
+ * @QPC_REQ_WQ_TYPE_RDV_WRITE: SEND-RDV operation is allowed on this QP.
+ */
+enum qpc_req_wq_type {
+ QPC_REQ_WQ_TYPE_WRITE = 1,
+ QPC_REQ_WQ_TYPE_RDV_READ = 2,
+ QPC_REQ_WQ_TYPE_RDV_WRITE = 3
+};
+
+/**
+ * enum hbl_ib_mem_type - Memory allocation types.
+ * @HBL_IB_MEM_INVALID: N/A option.
+ * @HBL_IB_MEM_HOST_DMA_COHERENT: Host DMA coherent memory.
+ * @HBL_IB_MEM_HOST_VIRTUAL: Host virtual memory.
+ * @HBL_IB_MEM_DEVICE: Device HBM memory.
+ * @HBL_IB_MEM_HOST_MAP_ONLY: Host mapping only.
+ * @HBL_IB_MEM_HW_BLOCK: Hw registers.
+ */
+enum hbl_ib_mem_type {
+ HBL_IB_MEM_INVALID,
+ HBL_IB_MEM_HOST_DMA_COHERENT,
+ HBL_IB_MEM_HOST_VIRTUAL,
+ HBL_IB_MEM_DEVICE,
+ HBL_IB_MEM_HOST_MAP_ONLY,
+ HBL_IB_MEM_HW_BLOCK,
+};
+
+/**
+ * struct hbl_cn_eqe - describes an event-queue entry
+ * @data: the data each event-queue entry contains
+ */
+struct hbl_cn_eqe {
+ u32 data[4];
+};
+
+/**
+ * struct hbl_cn_mem_resources - memory resource used by a memory ring.
+ * @addr: virtual address of the memory.
+ * @dma_addr: physical address of the memory.
+ * @size: memory size.
+ */
+struct hbl_cn_mem_resource {
+ void *addr;
+ dma_addr_t dma_addr;
+ u32 size;
+};
+
+/**
+ * struct hbl_cn_ring - represents a memory ring.
+ * @buf: the ring buffer memory resource.
+ * @pi: the memory-resident producer index of the ring, updated by HW
+ * @pi_shadow: producer shadow index - used by SW
+ * @ci_shadow: consumer shadow index - used by SW
+ * @rep_idx: use to count until a threshold value, like HW update
+ * @asid: the asid of the ring
+ * @count: the number of elements the ring can hold
+ * @elem_size: the rings's element size
+ */
+struct hbl_cn_ring {
+ struct hbl_cn_mem_resource buf;
+ struct hbl_cn_mem_resource pi;
+ u32 pi_shadow;
+ u32 ci_shadow;
+ u32 rep_idx;
+ u32 asid;
+ u32 count;
+ u32 elem_size;
+};
+
+/* ring support */
+#define RING_BUF_DMA_ADDRESS(ring) ((ring)->buf.dma_addr)
+#define RING_BUF_ADDRESS(ring) ((ring)->buf.addr)
+#define RING_BUF_SIZE(ring) ((ring)->buf.size)
+#define RING_PI_DMA_ADDRESS(ring) ((ring)->pi.dma_addr)
+#define RING_PI_ADDRESS(ring) ((ring)->pi.addr)
+#define RING_PI_SIZE(ring) ((ring)->pi.size)
+#define RING_CI_ADDRESS(ring) RING_BUF_ADDRESS(ring)
+
+/* Ethernet */
+
+/**
+ * struct hbl_en_aux_data - habanalabs data for the Ethernet driver.
+ * @pdev: pointer to PCI device.
+ * @dev: related kernel basic device structure.
+ * @asic_specific: ASIC specific data.
+ * @fw_ver: FW version.
+ * @qsfp_eeprom: QSFPD EEPROM info.
+ * @mac_addr: array of all MAC addresses.
+ * @asic_type: ASIC specific type.
+ * @ports_mask: mask of available ports.
+ * @auto_neg_mask: mask of port with Autonegotiation enabled.
+ * @pending_reset_long_timeout: long timeout for pending hard reset to finish in seconds.
+ * @max_frm_len: maximum allowed frame length.
+ * @raw_elem_size: size of element in raw buffers.
+ * @max_raw_mtu: maximum MTU size for raw packets.
+ * @min_raw_mtu: minimum MTU size for raw packets.
+ * @id: device ID.
+ * @max_num_of_ports: max number of available ports.
+ * @has_eq: true if event queue is supported.
+ */
+struct hbl_en_aux_data {
+ struct pci_dev *pdev;
+ struct device *dev;
+ void *asic_specific;
+ char *fw_ver;
+ char *qsfp_eeprom;
+ char **mac_addr;
+ enum hbl_cn_asic_type asic_type;
+ u64 ports_mask;
+ u64 auto_neg_mask;
+ u32 pending_reset_long_timeout;
+ u32 max_frm_len;
+ u32 raw_elem_size;
+ u16 max_raw_mtu;
+ u16 min_raw_mtu;
+ u16 id;
+ u8 max_num_of_ports;
+ u8 has_eq;
+};
+
+/**
+ * struct hbl_en_aux_ops - pointer functions for cn <-> en drivers communication.
+ * @device_operational: is device operational.
+ * @hw_access_lock: prevent HW access.
+ * @hw_access_unlock: allow HW access.
+ * @is_eth_lpbk: is Ethernet loopback enabled.
+ * @port_hw_init: port HW init.
+ * @port_hw_fini: port HW cleanup.
+ * @phy_init: port PHY init.
+ * @phy_fini: port PHY cleanup.
+ * @set_pfc: enable/disable PFC.
+ * @get_cnts_num: get the number of available counters.
+ * @get_cnts_names: get the names of the available counters.
+ * @get_cnts_values: get the values of the available counters.
+ * @eq_dispatcher_register_qp: register QP to its event dispatch queue.
+ * @eq_dispatcher_unregister_qp: un-register QP from its event dispatch queue.
+ * @get_speed: get the port speed in Mb/s.
+ * @track_ext_port_reset: track the reset of the given port according to the given syndrome.
+ * @port_toggle_count: count port toggles upon actions that teardown or create a port.
+ * @ports_reopen: reopen the ports after hard reset.
+ * @ports_stop_prepare: prepare the ports for a stop.
+ * @ports_stop: stop traffic.
+ * @set_port_status: set the link port status.
+ * @get_mac_lpbk: get MAC loopback status.
+ * @set_mac_lpbk: set MAC loopback status.
+ * @update_mtu: update all QPs to use the new MTU value.
+ * @qpc_write: write a QP context to the HW.
+ * @ctrl_lock: control mutex lock.
+ * @ctrl_unlock: control mutex unlock.
+ * @is_port_open: is port open;
+ * @get_src_ip: get the source IP of the given port.
+ * @reset_stats: reset port statistics (called from debugfs only).
+ * @get_mtu: get the port MTU value.
+ * @get_pflags: get the port private flags.
+ * @set_dev_lpbk: set loopback status on the net-device.
+ * @handle_eqe: handle event queue entry from H/W.
+ * @asic_ops: pointer for ASIC specific ops struct.
+ */
+struct hbl_en_aux_ops {
+ /* en2cn */
+ bool (*device_operational)(struct hbl_aux_dev *aux_dev);
+ void (*hw_access_lock)(struct hbl_aux_dev *aux_dev);
+ void (*hw_access_unlock)(struct hbl_aux_dev *aux_dev);
+ bool (*is_eth_lpbk)(struct hbl_aux_dev *aux_dev);
+ int (*port_hw_init)(struct hbl_aux_dev *aux_dev, u32 port);
+ void (*port_hw_fini)(struct hbl_aux_dev *aux_dev, u32 port);
+ int (*phy_init)(struct hbl_aux_dev *aux_dev, u32 port);
+ void (*phy_fini)(struct hbl_aux_dev *aux_dev, u32 port);
+ int (*set_pfc)(struct hbl_aux_dev *aux_dev, u32 port, bool enable);
+ int (*get_cnts_num)(struct hbl_aux_dev *aux_dev, u32 port);
+ void (*get_cnts_names)(struct hbl_aux_dev *aux_dev, u32 port, u8 *data);
+ void (*get_cnts_values)(struct hbl_aux_dev *aux_dev, u32 port, u64 *data);
+ bool (*get_mac_lpbk)(struct hbl_aux_dev *aux_dev, u32 port);
+ int (*set_mac_lpbk)(struct hbl_aux_dev *aux_dev, u32 port, bool enable);
+ int (*update_mtu)(struct hbl_aux_dev *aux_dev, u32 port, u32 mtu);
+ int (*qpc_write)(struct hbl_aux_dev *aux_dev, u32 port, void *qpc,
+ struct qpc_mask *qpc_mask, u32 qpn, bool is_req);
+ void (*ctrl_lock)(struct hbl_aux_dev *aux_dev, u32 port);
+ void (*ctrl_unlock)(struct hbl_aux_dev *aux_dev, u32 port);
+ int (*eq_dispatcher_register_qp)(struct hbl_aux_dev *aux_dev, u32 port, u32 asid,
+ u32 qp_id);
+ int (*eq_dispatcher_unregister_qp)(struct hbl_aux_dev *aux_dev, u32 port, u32 qp_id);
+ u32 (*get_speed)(struct hbl_aux_dev *aux_dev, u32 port);
+ void (*track_ext_port_reset)(struct hbl_aux_dev *aux_dev, u32 port, u32 syndrome);
+ void (*port_toggle_count)(struct hbl_aux_dev *aux_dev, u32 port);
+
+ /* cn2en */
+ int (*ports_reopen)(struct hbl_aux_dev *aux_dev);
+ void (*ports_stop_prepare)(struct hbl_aux_dev *aux_dev);
+ void (*ports_stop)(struct hbl_aux_dev *aux_dev);
+ void (*set_port_status)(struct hbl_aux_dev *aux_dev, u32 port_idx, bool up);
+ bool (*is_port_open)(struct hbl_aux_dev *aux_dev, u32 port_idx);
+ int (*get_src_ip)(struct hbl_aux_dev *aux_dev, u32 port_idx, u32 *src_ip);
+ void (*reset_stats)(struct hbl_aux_dev *aux_dev, u32 port_idx);
+ u32 (*get_mtu)(struct hbl_aux_dev *aux_dev, u32 port_idx);
+ u32 (*get_pflags)(struct hbl_aux_dev *aux_dev, u32 port_idx);
+ void (*set_dev_lpbk)(struct hbl_aux_dev *aux_dev, u32 port_idx, bool enable);
+ void (*handle_eqe)(struct hbl_aux_dev *aux_dev, u32 port, struct hbl_cn_eqe *eqe);
+ void *asic_ops;
+};
+
+/* InfiniBand */
+
+#define HBL_IB_CNT_NAME_LEN (ETH_GSTRING_LEN * 2)
+
+/**
+ * struct hbl_ib_device_attr - IB device attributes.
+ * @fw_ver: firmware version.
+ * @max_mr_size: max size of a memory region.
+ * @page_size_cap: largest page size in MMU.
+ * @vendor_id: device vendor ID.
+ * @vendor_part_id: device vendor part ID.
+ * @hw_ver: device chip version.
+ * @cqe_size: Size of Completion Queue Entry.
+ * @min_cq_entries: Minimum completion queue entries needed.
+ * @max_qp: max QPs supported.
+ * @max_qp_wr: max QPs per work-request supported.
+ * @max_cqe: max completion-queue entries supported.
+ */
+struct hbl_ib_device_attr {
+ u64 fw_ver;
+ u64 max_mr_size;
+ u64 page_size_cap;
+ u32 vendor_id;
+ u32 vendor_part_id;
+ u32 hw_ver;
+ u32 cqe_size;
+ u32 min_cq_entries;
+ s32 max_qp;
+ s32 max_qp_wr;
+ s32 max_cqe;
+};
+
+/**
+ * struct hbl_ib_port_attr - IB port attributes.
+ * @speed: speed in Mb/s.
+ * @max_msg_sz: max message size
+ * @max_mtu: max mtu size
+ * @open: is open and fully initialized.
+ * @link_up: has PCS link.
+ * @num_lanes: number of lanes per port.
+ */
+struct hbl_ib_port_attr {
+ u32 speed;
+ u32 max_msg_sz;
+ u32 max_mtu;
+ u8 open;
+ u8 link_up;
+ u8 num_lanes;
+};
+
+/**
+ * struct hbl_ib_port_cnts_data - IB port counters data.
+ * @names: Names of the counters.
+ * @num: Number of counters.
+ */
+struct hbl_ib_port_cnts_data {
+ u8 *names;
+ u32 num;
+};
+
+/**
+ * struct hbl_ib_dump_qp_attr - IB QP dump attributes.
+ * @port: Port ID the QP belongs to.
+ * @qpn: QP number.
+ * @req: Requester QP, otherwise responder.
+ * @full: Include full QP information.
+ * @force: Force reading a QP in invalid/error state.
+ */
+struct hbl_ib_dump_qp_attr {
+ u32 port;
+ u32 qpn;
+ u8 req;
+ u8 full;
+ u8 force;
+};
+
+/**
+ * struct hbl_ib_mem_info - Information for a memory region pertaining to a memory handle.
+ * @cpu_addr: The kernel virtual address.
+ * @bus_addr: The bus address.
+ * @mtype: The memory type.
+ * @mem_handle: The memory handle.
+ * @size: The size of the memory region.
+ * @vmalloc: The memory is virtually contiguous only.
+ */
+struct hbl_ib_mem_info {
+ void *cpu_addr;
+ dma_addr_t bus_addr;
+ enum hbl_ib_mem_type mtype;
+ u64 mem_handle;
+ u64 size;
+ u8 vmalloc;
+};
+
+/**
+ * struct hbl_ib_aux_data - habanalabs data for the IB driver.
+ * @pdev: pointer to PCI device.
+ * @dev: related kernel basic device structure.
+ * @cnts_data: Ports counters data.
+ * @ports_mask: mask of available ports.
+ * @ext_ports_mask: mask of external ports (subset of ports_mask).
+ * @dram_size: available DRAM size.
+ * @max_num_of_wqes: maximum number of WQ entries.
+ * @pending_reset_long_timeout: long timeout for pending hard reset to finish in seconds.
+ * @id: device ID.
+ * @max_num_of_ports: maximum number of ports supported by ASIC.
+ * @mixed_qp_wq_types: Using mixed QP WQ types is supported.
+ * @umr_support: device supports UMR.
+ * @cc_support: device supports congestion control.
+ */
+struct hbl_ib_aux_data {
+ struct pci_dev *pdev;
+ struct device *dev;
+ struct hbl_ib_port_cnts_data *cnts_data;
+ u64 ports_mask;
+ u64 ext_ports_mask;
+ u64 dram_size;
+ u32 max_num_of_wqes;
+ u32 pending_reset_long_timeout;
+ u16 id;
+ u8 max_num_of_ports;
+ u8 mixed_qp_wq_types;
+ u8 umr_support;
+ u8 cc_support;
+};
+
+/**
+ * struct hbl_ib_aux_ops - pointer functions for cn <-> ib drivers communication.
+ * @device_operational: is device operational.
+ * @hw_access_lock: prevent HW access.
+ * @hw_access_unlock: allow HW access.
+ * @alloc_ucontext: allocate user context.
+ * @dealloc_ucontext: deallocate user context.
+ * @query_port: get port attributes.
+ * @cmd_ctrl: operate the device with proprietary opcodes.
+ * @query_device: get device attributes.
+ * @set_ip_addr_encap: setup IP address encapsulation.
+ * @qp_syndrome_to_str: translates syndrome qp number to string.
+ * @verify_qp_id: verify if the specified QP id is valid.
+ * @get_cnts_values: get the values of the available counters.
+ * @dump_qp: dump QP context to the given buffer.
+ * @query_mem_handle: query information for a memory handle.
+ * @eqe_work_schd: schedule a user eq poll work on hbl side.
+ * @dispatch_fatal_event: raise a fatal event to user space.
+ */
+struct hbl_ib_aux_ops {
+ /* ib2cn */
+ bool (*device_operational)(struct hbl_aux_dev *aux_dev);
+ void (*hw_access_lock)(struct hbl_aux_dev *aux_dev);
+ void (*hw_access_unlock)(struct hbl_aux_dev *aux_dev);
+ int (*alloc_ucontext)(struct hbl_aux_dev *aux_dev, int user_fd, void **cn_ib_ctx);
+ void (*dealloc_ucontext)(struct hbl_aux_dev *aux_dev, void *cn_ib_ctx);
+ void (*query_port)(struct hbl_aux_dev *aux_dev, u32 port,
+ struct hbl_ib_port_attr *port_attr);
+ int (*cmd_ctrl)(struct hbl_aux_dev *aux_dev, void *cn_ib_ctx, u32 op, void *input,
+ void *output);
+ void (*query_device)(struct hbl_aux_dev *aux_dev, struct hbl_ib_device_attr *device_attr);
+ void (*set_ip_addr_encap)(struct hbl_aux_dev *aux_dev, u32 ip_addr, u32 port);
+ char *(*qp_syndrome_to_str)(struct hbl_aux_dev *aux_dev, u32 syndrome);
+ int (*verify_qp_id)(struct hbl_aux_dev *aux_dev, u32 qp_id, u32 port);
+ void (*get_cnts_values)(struct hbl_aux_dev *aux_dev, u32 port, u64 *data);
+ int (*dump_qp)(struct hbl_aux_dev *aux_dev, struct hbl_ib_dump_qp_attr *attr, char *buf,
+ size_t size);
+ int (*query_mem_handle)(struct hbl_aux_dev *aux_dev, u64 mem_handle,
+ struct hbl_ib_mem_info *info);
+
+ /* cn2ib */
+ void (*eqe_work_schd)(struct hbl_aux_dev *aux_dev, u32 port);
+ void (*dispatch_fatal_event)(struct hbl_aux_dev *aux_dev, u32 asid);
+};
+
+/* CN */
+
+/* interrupt type */
+enum hbl_cn_cpucp_interrupt_type {
+ HBL_CN_CPUCP_INTR_NONE = 0,
+ HBL_CN_CPUCP_INTR_TMR = 1,
+ HBL_CN_CPUCP_INTR_RXB_CORE_SPI,
+ HBL_CN_CPUCP_INTR_RXB_CORE_SEI,
+ HBL_CN_CPUCP_INTR_QPC_RESP_ERR,
+ HBL_CN_CPUCP_INTR_RXE_SPI,
+ HBL_CN_CPUCP_INTR_RXE_SEI,
+ HBL_CN_CPUCP_INTR_TXS,
+ HBL_CN_CPUCP_INTR_TXE,
+};
+
+/*
+ * struct hbl_cn_eq_port_intr_cause - port interrupt cause data.
+ * @intr_cause_data: interrupt cause data.
+ */
+struct hbl_cn_eq_port_intr_cause {
+ u64 intr_cause_data;
+};
+
+/*
+ * struct hbl_cn_eq_intr_cause - interrupt cause data.
+ * @intr_type: interrupt type.
+ * @intr_cause: array of ports interrupt cause data.
+ */
+struct hbl_cn_eq_intr_cause {
+ u32 intr_type; /* enum hbl_cn_cpucp_interrupt_type */
+ u32 pad;
+ struct hbl_cn_eq_port_intr_cause intr_cause[MAX_PORTS_PER_NIC];
+};
+
+/*
+ * struct hbl_cn_cpucp_frac_val - fracture value represented by "integer.frac".
+ * @integer: the integer part of the fracture value;
+ * @frac: the fracture part of the fracture value.
+ */
+struct hbl_cn_cpucp_frac_val {
+ union {
+ struct {
+ u16 integer;
+ u16 frac;
+ };
+ u16 val;
+ };
+};
+
+/*
+ * struct hbl_cn_cpucp_ser_val - Symbol Error Rate value represented by "integer * 10 ^ -exp".
+ * @integer: the integer part of the SER value.
+ * @exp: the exponent part of the SER value.
+ */
+struct hbl_cn_cpucp_ser_val {
+ u16 integer;
+ u16 exp;
+};
+
+#endif /* HBL_CN_H_ */
diff --git a/include/linux/net/intel/cn_aux.h b/include/linux/net/intel/cn_aux.h
new file mode 100644
index 000000000000..8a7f54e78afb
--- /dev/null
+++ b/include/linux/net/intel/cn_aux.h
@@ -0,0 +1,298 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#ifndef HBL_CN_AUX_H_
+#define HBL_CN_AUX_H_
+
+#include <linux/irqreturn.h>
+#include <linux/habanalabs/cpucp_if.h>
+#include <linux/auxiliary_bus.h>
+#include <linux/if_vlan.h>
+#include <uapi/linux/ethtool.h>
+
+#define HBL_EN_MAX_HEADERS_SZ (ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN)
+
+/* driver specific value, should always be >= asic specific h/w resource */
+#define NIC_DRV_MAX_CQS_NUM 32
+#define NIC_DRV_MAX_CCQS_NUM 4
+#define NIC_DRV_NUM_DB_FIFOS 32
+
+/**
+ * enum hbl_cn_asic_type - supported ASIC types.
+ * @ASIC_GAUDI2: Gaudi2 device.
+ */
+enum hbl_cn_asic_type {
+ HBL_ASIC_GAUDI2,
+};
+
+/**
+ * enum hbl_cn_status_cmd - status cmd type.
+ * @HBL_CN_STATUS_ONE_SHOT: one shot command.
+ * @HBL_CN_STATUS_PERIODIC_START: start periodic status update.
+ * @HBL_CN_STATUS_PERIODIC_STOP: stop periodic status update.
+ */
+enum hbl_cn_status_cmd {
+ HBL_CN_STATUS_ONE_SHOT,
+ HBL_CN_STATUS_PERIODIC_START,
+ HBL_CN_STATUS_PERIODIC_STOP,
+};
+
+/**
+ * enum hbl_aux_dev_type - auxiliary device type.
+ * HBL_AUX_DEV_CN: Shared Network Interface.
+ * HBL_AUX_DEV_ETH: Ethernet.
+ * HBL_AUX_DEV_IB: InfiniBand.
+ */
+enum hbl_aux_dev_type {
+ HBL_AUX_DEV_CN,
+ HBL_AUX_DEV_ETH,
+ HBL_AUX_DEV_IB,
+};
+
+/**
+ * struct hbl_aux_dev - habanalabs auxiliary device structure.
+ * @adev: auxiliary device.
+ * @aux_ops: pointer functions for drivers communication.
+ * @aux_data: essential data for operating the auxiliary device.
+ * @priv: auxiliary device private data.
+ * @type: type of the auxiliary device.
+ */
+struct hbl_aux_dev {
+ struct auxiliary_device adev;
+ void *aux_ops;
+ void *aux_data;
+ void *priv;
+ enum hbl_aux_dev_type type;
+};
+
+/**
+ * struct hbl_cn_stat - Holds ASIC specific statistics string and default register offset.
+ * @str: String name of ethtool stat.
+ * @lo_offset: Register offset of the stat.
+ * @hi_offset: High register offset. May be unused for some stats.
+ */
+struct hbl_cn_stat {
+ char str[ETH_GSTRING_LEN];
+ int lo_offset;
+ int hi_offset;
+};
+
+/*
+ * struct hbl_cn_cpucp_mac_addr - port MAC address received from FW.
+ * @mac_addr: port MAC address.
+ */
+struct hbl_cn_cpucp_mac_addr {
+ u8 mac_addr[ETH_ALEN];
+};
+
+/*
+ * struct hbl_cn_cpucp_info - info received from FW.
+ * @mac_addrs: array of MAC address for all physical ports.
+ * @link_mask: mask of available ports.
+ * @pol_tx_mask: array of Tx polarity value for all ports.
+ * @pol_rx_mask: array of Rx polarity value for all ports.
+ * @link_ext_mask: mask of external ports.
+ * @qsfp_eeprom: QSFP EEPROM info.
+ * @auto_neg_mask: mask of ports which supports Autonegotiation.
+ * @serdes_type: type of serdes.
+ * @tx_swap_map: lane swapping map.
+ */
+struct hbl_cn_cpucp_info {
+ struct hbl_cn_cpucp_mac_addr mac_addrs[CPUCP_MAX_NICS];
+ u64 link_mask[CPUCP_NIC_MASK_ARR_LEN];
+ u64 pol_tx_mask[CPUCP_NIC_POLARITY_ARR_LEN];
+ u64 pol_rx_mask[CPUCP_NIC_POLARITY_ARR_LEN];
+ u64 link_ext_mask[CPUCP_NIC_MASK_ARR_LEN];
+ u8 qsfp_eeprom[CPUCP_NIC_QSFP_EEPROM_MAX_LEN];
+ u64 auto_neg_mask[CPUCP_NIC_MASK_ARR_LEN];
+ enum cpucp_serdes_type serdes_type;
+ u16 tx_swap_map[CPUCP_MAX_NICS];
+};
+
+/**
+ * struct hbl_cn_aux_data - habanalabs data for the cn driver.
+ * @pdev: pointer to PCI device.
+ * @dev: related kernel basic device structure.
+ * @asic_specific: ASIC specific data.
+ * @fw_ver: FW version.
+ * @asic_type: ASIC specific type.
+ * @ports_mask: mask of available ports.
+ * @ext_ports_mask: mask of external ports (subset of ports_mask).
+ * @auto_neg_mask: mask of ports with Autonegotiation enabled.
+ * @dram_size: available DRAM size.
+ * @nic_drv_addr: base address for NIC driver on DRAM.
+ * @nic_drv_size: driver size reserved for NIC driver on DRAM.
+ * @macro_cfg_size: the size of the macro configuration space.
+ * @max_num_of_ports: max number of available ports.
+ * @pending_reset_long_timeout: long timeout for pending hard reset to finish in seconds.
+ * @kernel_asid: kernel ASID.
+ * @card_location: the OAM number in the HLS (relevant for PMC card type).
+ * @device_timeout: device access timeout in usec.
+ * @fw_major_version: major version of current loaded preboot.
+ * @fw_minor_version: minor version of current loaded preboot.
+ * @fw_app_cpu_boot_dev_sts0: bitmap representation of application security
+ * status reported by FW, bit description can be
+ * found in CPU_BOOT_DEV_STS0
+ * @fw_app_cpu_boot_dev_sts1: bitmap representation of application security
+ * status reported by FW, bit description can be
+ * found in CPU_BOOT_DEV_STS1
+ * @id: device ID.
+ * @cache_line_size: device cache line size.
+ * @clk: clock frequency in MHz.
+ * @pldm: is running on Palladium setup.
+ * @skip_phy_init: avoid writing/reading PHY registers.
+ * @load_phy_fw: load PHY F/W.
+ * @cpucp_fw: is CPUCP FW enabled.
+ * @supports_coresight: is CoreSight supported.
+ * @use_fw_serdes_info: true if FW serdes values should be used, false if hard coded values should
+ * be used.
+ * @mmu_enable: is MMU enabled.
+ * @lanes_per_port: number of physical lanes per port.
+ * @cpucp_checkers_shift: CPUCP checkers flags shift.
+ */
+struct hbl_cn_aux_data {
+ struct pci_dev *pdev;
+ struct device *dev;
+ void *asic_specific;
+ char *fw_ver;
+ enum hbl_cn_asic_type asic_type;
+ u64 ports_mask;
+ u64 ext_ports_mask;
+ u64 auto_neg_mask;
+ u64 dram_size;
+ u64 nic_drv_addr;
+ u64 nic_drv_size;
+ u32 macro_cfg_size;
+ u32 pending_reset_long_timeout;
+ u32 kernel_asid;
+ u32 card_location;
+ u32 device_timeout;
+ u32 fw_major_version;
+ u32 fw_minor_version;
+ u32 fw_app_cpu_boot_dev_sts0;
+ u32 fw_app_cpu_boot_dev_sts1;
+ u16 id;
+ u16 cache_line_size;
+ u16 clk;
+ u8 pldm;
+ u8 skip_phy_init;
+ u8 load_phy_fw;
+ u8 cpucp_fw;
+ u8 supports_coresight;
+ u8 use_fw_serdes_info;
+ u8 mmu_enable;
+ u8 lanes_per_port;
+ u8 cpucp_checkers_shift;
+};
+
+/**
+ * enum hbl_cn_mmu_mode - MMU modes the CN can work with.
+ * @HBL_CN_MMU_MODE_EXTERNAL: using external MMU HW IP.
+ * @HBL_CN_MMU_MODE_NETWORK_TLB: Using internal network TLB (but external page-table).
+ */
+enum hbl_cn_mmu_mode {
+ HBL_CN_MMU_MODE_EXTERNAL,
+ HBL_CN_MMU_MODE_NETWORK_TLB,
+};
+
+/**
+ * struct hbl_cn_vm_info - VM related info for the cn driver.
+ * @mmu_mode: the type (or mode) of MMU currently configured.
+ * @ext_mmu.work_id: the unique work-ID assigned to this VM when in external MMU mode.
+ * @net_tlb.pasid: the PCI process space address ID assigned to the device.
+ * @net_tlb.page_tbl_addr: the address of the MMU page table of this VM.
+ */
+struct hbl_cn_vm_info {
+ enum hbl_cn_mmu_mode mmu_mode;
+ union {
+ struct {
+ u32 work_id;
+ } ext_mmu;
+
+ struct {
+ u32 pasid;
+ u64 page_tbl_addr;
+ } net_tlb;
+ };
+};
+
+typedef bool (*hbl_cn_poll_cond_func)(u32 val, void *arg);
+
+enum hbl_cn_mem_type {
+ HBL_CN_MEM_TYPE_HOST,
+ HBL_CN_MEM_TYPE_DEVICE,
+};
+
+/**
+ * struct hbl_cn_aux_ops - pointer functions for cn <-> compute drivers communication.
+ * @device_operational: is device operational.
+ * @hw_access_lock: prevent HW access.
+ * @hw_access_unlock: allow HW access.
+ * @device_reset: Perform device reset.
+ * @vm_dev_mmu_map: map cpu/kernel address or device memory range to device address range in order
+ * to provide device-memory access.
+ * @vm_dev_mmu_unmap: unmap a previously mapped address range.
+ * @vm_reserve_dva_block: Reserve a device virtual block of a given size.
+ * @vm_unreserve_dva_block: Release a given device virtual block.
+ * @dram_readl: Read long from DRAM.
+ * @dram_writel: Write long to DRAM.
+ * @rreg: Read register.
+ * @wreg: Write register.
+ * @get_reg_pcie_addr: Retrieve pci address.
+ * @poll_reg: Poll on a register until a given condition is fulfilled or timeout.
+ * @get_cpucp_info: fetch updated CPUCP info.
+ * @register_cn_user_context: register a user context represented by user provided FD. If the
+ * returned comp_handle and vm_handle are equal then this context doesn't
+ * support data transfer.
+ * @deregister_cn_user_context: de-register the user context represented by the vm_handle returned
+ * from calling register_cn_user_context.
+ * @vm_create: create a VM in registered context.
+ * @vm_destroy: destroy a VM in registered context.
+ * @get_vm_info: get information on a VM.
+ * @ports_reopen: reopen the ports after hard reset.
+ * @ports_stop_prepare: prepare the ports for a stop.
+ * @ports_stop: stop traffic.
+ * @synchronize_irqs: Synchronize IRQs.
+ * @asic_ops: pointer for ASIC specific ops struct.
+ */
+struct hbl_cn_aux_ops {
+ /* cn2compute */
+ bool (*device_operational)(struct hbl_aux_dev *aux_dev);
+ void (*hw_access_lock)(struct hbl_aux_dev *aux_dev);
+ void (*hw_access_unlock)(struct hbl_aux_dev *aux_dev);
+ void (*device_reset)(struct hbl_aux_dev *aux_dev);
+ int (*vm_dev_mmu_map)(struct hbl_aux_dev *aux_dev, u64 vm_handle,
+ enum hbl_cn_mem_type mem_type, u64 addr, u64 dva, size_t size);
+ void (*vm_dev_mmu_unmap)(struct hbl_aux_dev *aux_dev, u64 vm_handle, u64 dva, size_t size);
+ int (*vm_reserve_dva_block)(struct hbl_aux_dev *aux_dev, u64 vm_handle, u64 size, u64 *dva);
+ void (*vm_unreserve_dva_block)(struct hbl_aux_dev *aux_dev, u64 vm_handle, u64 dva,
+ u64 size);
+ u32 (*dram_readl)(struct hbl_aux_dev *aux_dev, u64 addr);
+ void (*dram_writel)(struct hbl_aux_dev *aux_dev, u32 val, u64 addr);
+ u32 (*rreg)(struct hbl_aux_dev *aux_dev, u32 reg);
+ void (*wreg)(struct hbl_aux_dev *aux_dev, u32 reg, u32 val);
+ int (*get_reg_pcie_addr)(struct hbl_aux_dev *aux_dev, u32 reg, u64 *pci_addr);
+ int (*poll_reg)(struct hbl_aux_dev *aux_dev, u32 reg, u64 timeout_us,
+ hbl_cn_poll_cond_func func, void *arg);
+ void (*get_cpucp_info)(struct hbl_aux_dev *aux_dev,
+ struct hbl_cn_cpucp_info *hbl_cn_cpucp_info);
+ int (*register_cn_user_context)(struct hbl_aux_dev *aux_dev, int user_fd,
+ const void *cn_ctx, u64 *comp_handle, u64 *vm_handle);
+ void (*deregister_cn_user_context)(struct hbl_aux_dev *aux_dev, u64 vm_handle);
+ int (*vm_create)(struct hbl_aux_dev *aux_dev, u64 comp_handle, u32 flags, u64 *vm_handle);
+ void (*vm_destroy)(struct hbl_aux_dev *aux_dev, u64 vm_handle);
+ int (*get_vm_info)(struct hbl_aux_dev *aux_dev, u64 vm_handle,
+ struct hbl_cn_vm_info *vm_info);
+
+ /* compute2cn */
+ int (*ports_reopen)(struct hbl_aux_dev *aux_dev);
+ void (*ports_stop_prepare)(struct hbl_aux_dev *aux_dev, bool fw_reset, bool in_teardown);
+ void (*ports_stop)(struct hbl_aux_dev *aux_dev);
+ void (*synchronize_irqs)(struct hbl_aux_dev *aux_dev);
+ void *asic_ops;
+};
+
+#endif /* HBL_CN_AUX_H_ */
diff --git a/include/linux/net/intel/cni.h b/include/linux/net/intel/cni.h
new file mode 100644
index 000000000000..206b93ffd0e8
--- /dev/null
+++ b/include/linux/net/intel/cni.h
@@ -0,0 +1,636 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#ifndef HBL_CNI_H_
+#define HBL_CNI_H_
+
+#include <linux/if_ether.h>
+#include <linux/types.h>
+
+#define HBL_CNI_STAT_STR_LEN 32
+
+/* Requester */
+#define HBL_CNI_CQE_TYPE_REQ 0
+/* Responder */
+#define HBL_CNI_CQE_TYPE_RES 1
+
+/* Number of backpressure offsets */
+#define HBL_CNI_USER_BP_OFFS_MAX 16
+
+/* Number of FnA addresses for SRAM/DCCM completion */
+#define HBL_CNI_FNA_CMPL_ADDR_NUM 2
+
+/**
+ * struct hbl_cni_alloc_conn_in - NIC opcode HBL_CNI_OP_ALLOC_CONN in param.
+ * @port: NIC port ID.
+ * @hint: this may be used as the connection-number hint for the driver as a recommendation of user.
+ */
+struct hbl_cni_alloc_conn_in {
+ u32 port;
+ u32 hint;
+};
+
+/**
+ * struct hbl_cni_alloc_conn_out - NIC opcode HBL_CNI_OP_ALLOC_CONN out param.
+ * @conn_id: Connection ID.
+ */
+struct hbl_cni_alloc_conn_out {
+ u32 conn_id;
+};
+
+/**
+ * struct hbl_cni_req_conn_ctx_in - NIC opcode HBL_CNI_OP_SET_REQ_CONN_CTX in param.
+ * @dst_ip_addr: Destination IP address in native endianness.
+ * @dst_conn_id: Destination connection ID.
+ * @port: NIC port ID.
+ * @conn_id: Connection ID.
+ * @dst_mac_addr: Destination MAC address.
+ * @priority: Connection priority [0..3].
+ * @timer_granularity: Timer granularity [0..127].
+ * @swq_granularity: SWQ granularity [0 for 32B or 1 for 64B].
+ * @wq_type: Work queue type [1..3].
+ * @cq_number: Completion queue number.
+ * @wq_remote_log_size: Remote Work queue log size [2^QPC] Rendezvous.
+ * @congestion_en: Enable/disable Congestion-Control.
+ * @congestion_wnd: Congestion-Window size.
+ * @mtu: Max Transmit Unit.
+ * @encap_en: used as boolean; indicates if this QP has encapsulation support.
+ * @encap_id: Encapsulation-id; valid only if 'encap_en' is set.
+ * @wq_size: Max number of elements in the work queue.
+ * @loopback: used as boolean; indicates if this QP used for loopback mode.
+ * @compression_en: Enable compression.
+ * @remote_key: Remote-key to be used to generate on outgoing packets.
+ */
+struct hbl_cni_req_conn_ctx_in {
+ u32 reserved0;
+ u32 dst_ip_addr;
+ u32 dst_conn_id;
+ u32 deprecated0;
+ u32 reserved1;
+ u32 port;
+ u32 conn_id;
+ u8 dst_mac_addr[ETH_ALEN];
+ u8 deprecated1;
+ u8 priority;
+ u8 deprecated2;
+ u8 timer_granularity;
+ u8 swq_granularity;
+ u8 wq_type;
+ u8 deprecated3;
+ u8 cq_number;
+ u8 wq_remote_log_size;
+ u8 congestion_en;
+ u32 congestion_wnd;
+ u16 mtu;
+ u8 encap_en;
+ u8 encap_id;
+ u32 wq_size;
+ u8 loopback;
+ u8 reserved2;
+ u8 reserved3;
+ u8 compression_en;
+ u32 remote_key;
+};
+
+/**
+ * struct hbl_cni_req_conn_ctx_out - NIC opcode HBL_CNI_OP_SET_REQ_CONN_CTX out param.
+ * @swq_mem_handle: Handle for send WQ memory.
+ * @rwq_mem_handle: Handle for receive WQ memory.
+ * @swq_mem_size: Size of the send WQ memory.
+ * @rwq_mem_size: Size of the receive WQ memory.
+ */
+struct hbl_cni_req_conn_ctx_out {
+ u64 swq_mem_handle;
+ u64 rwq_mem_handle;
+ u32 swq_mem_size;
+ u32 rwq_mem_size;
+};
+
+/**
+ * struct hbl_cni_res_conn_ctx_in - NIC opcode HBL_CNI_OP_SET_RES_CONN_CTX in param.
+ * @dst_ip_addr: Destination IP address in native endianness.
+ * @dst_conn_id: Destination connection ID.
+ * @port: NIC port ID.
+ * @conn_id: Connection ID.
+ * @dst_mac_addr: Destination MAC address.
+ * @priority: Connection priority [0..3].
+ * @wq_peer_granularity: Work queue granularity.
+ * @cq_number: Completion queue number.
+ * @conn_peer: Connection peer.
+ * @rdv: used as boolean; indicates if this QP is RDV (WRITE or READ).
+ * @loopback: used as boolean; indicates if this QP used for loopback mode.
+ * @encap_en: used as boolean; indicates if this QP has encapsulation support.
+ * @encap_id: Encapsulation-id; valid only if 'encap_en' is set.
+ * @wq_peer_size: size of the peer Work queue.
+ * @local_key: Local-key to be used to validate against incoming packets.
+ */
+struct hbl_cni_res_conn_ctx_in {
+ u32 reserved;
+ u32 dst_ip_addr;
+ u32 dst_conn_id;
+ u32 port;
+ u32 conn_id;
+ u8 dst_mac_addr[ETH_ALEN];
+ u8 priority;
+ u8 deprecated1;
+ u8 deprecated2;
+ u8 wq_peer_granularity;
+ u8 cq_number;
+ u8 deprecated3;
+ u32 conn_peer;
+ u8 rdv;
+ u8 loopback;
+ u8 encap_en;
+ u8 encap_id;
+ u32 wq_peer_size;
+ u32 local_key;
+};
+
+/**
+ * struct hbl_cni_destroy_conn_in - NIC opcode HBL_CNI_OP_DESTROY_CONN in param.
+ * @port: NIC port ID.
+ * @conn_id: Connection ID.
+ */
+struct hbl_cni_destroy_conn_in {
+ u32 port;
+ u32 conn_id;
+};
+
+/**
+ * enum hbl_nic_mem_type - NIC WQ memory allocation type.
+ * @HBL_CNI_USER_WQ_SEND: Allocate memory for the user send WQ array.
+ * @HBL_CNI_USER_WQ_RECV: Allocate memory for the user receive WQ array.
+ * @HBL_CNI_USER_WQ_TYPE_MAX: number of values in enum.
+ */
+enum hbl_nic_mem_type {
+ HBL_CNI_USER_WQ_SEND,
+ HBL_CNI_USER_WQ_RECV,
+ HBL_CNI_USER_WQ_TYPE_MAX
+};
+
+/**
+ * enum hbl_nic_mem_id - memory allocation methods.
+ * @HBL_CNI_MEM_HOST: memory allocated on the host memory.
+ * @HBL_CNI_MEM_DEVICE: memory allocated on the device memory.
+ */
+enum hbl_nic_mem_id {
+ HBL_CNI_MEM_HOST = 1,
+ HBL_CNI_MEM_DEVICE
+};
+
+/**
+ * enum hbl_nic_swq_granularity - send WQE granularity.
+ * @HBL_CNI_SWQE_GRAN_32B: 32 byte WQE for linear write.
+ * @HBL_CNI_SWQE_GRAN_64B: 64 byte WQE for multi-stride write.
+ */
+enum hbl_nic_swq_granularity {
+ HBL_CNI_SWQE_GRAN_32B,
+ HBL_CNI_SWQE_GRAN_64B
+};
+
+/**
+ * struct hbl_cni_user_wq_arr_set_in - NIC opcode HBL_CNI_OP_USER_WQ_SET in param.
+ * @port: NIC port ID.
+ * @num_of_wqs: Number of user WQs.
+ * @num_of_wq_entries: Number of entries per user WQ.
+ * @type: Type of user WQ array.
+ * @mem_id: Specify host/device memory allocation.
+ * @swq_granularity: Specify the granularity of send WQ, 0: 32 bytes, 1: 64 bytes.
+ */
+struct hbl_cni_user_wq_arr_set_in {
+ u64 reserved;
+ u32 port;
+ u32 num_of_wqs;
+ u32 num_of_wq_entries;
+ u32 type;
+ u32 mem_id;
+ u8 swq_granularity;
+};
+
+/**
+ * struct hbl_cni_user_wq_arr_set_out - NIC opcode HBL_CNI_OP_USER_WQ_SET out param.
+ * @mem_handle: Handle of WQ array memory buffer.
+ */
+struct hbl_cni_user_wq_arr_set_out {
+ u64 mem_handle;
+};
+
+/**
+ * struct hbl_cni_user_wq_arr_unset_in - NIC opcode HBL_CNI_OP_USER_WQ_UNSET in param.
+ * @port: NIC port ID.
+ * @type: Type of user WQ array.
+ */
+struct hbl_cni_user_wq_arr_unset_in {
+ u32 port;
+ u32 type;
+};
+
+/**
+ * struct hbl_cni_alloc_user_cq_id_in - NIC opcode HBL_CNI_OP_ALLOC_USER_CQ_ID in param.
+ * @port: NIC port ID.
+ */
+struct hbl_cni_alloc_user_cq_id_in {
+ u32 port;
+};
+
+/**
+ * struct hbl_cni_alloc_user_cq_id_out - NIC opcode HBL_CNI_OP_ALLOC_USER_CQ_ID out param.
+ * @id: CQ ID.
+ */
+struct hbl_cni_alloc_user_cq_id_out {
+ u32 id;
+};
+
+/**
+ * struct hbl_cni_user_cq_id_set_in - NIC opcode HBL_CNI_OP_USER_CQ_SET in param.
+ * @port: NIC port ID.
+ * @num_of_cqes: Number of CQ entries in the buffer.
+ * @id: CQ ID.
+ */
+struct hbl_cni_user_cq_id_set_in {
+ u32 port;
+ u32 num_of_cqes;
+ u32 id;
+};
+
+/**
+ * struct hbl_cni_user_cq_id_set_out - NIC opcode HBL_CNI_OP_USER_CQ_ID_SET out param.
+ * @mem_handle: Handle of CQ memory buffer.
+ * @pi_handle: Handle of CQ producer-inder memory buffer.
+ * @regs_handle: Handle of CQ Registers base-address.
+ * @regs_offset: CQ Registers sub-offset.
+ */
+struct hbl_cni_user_cq_id_set_out {
+ u64 mem_handle;
+ u64 pi_handle;
+ u64 regs_handle;
+ u32 regs_offset;
+};
+
+/**
+ * struct hbl_cni_user_cq_id_unset_in - NIC opcode HBL_CNI_OP_USER_CQ_ID_UNSET in param.
+ * @port: NIC port ID.
+ * @id: NIC CQ ID.
+ */
+struct hbl_cni_user_cq_id_unset_in {
+ u32 port;
+ u32 id;
+};
+
+/**
+ * struct hbl_cni_dump_qp_in - NIC opcode HBL_CNI_OP_DUMP_QP in param.
+ * @user_buf_address: Pre-allocated user buffer address to hold the dump output.
+ * @user_buf_size: Size of the user buffer.
+ * @port: NIC port ID.
+ * @qpn: NIC QP ID.
+ * @req: is requester (otherwise responder).
+ */
+struct hbl_cni_dump_qp_in {
+ u64 user_buf;
+ u32 user_buf_size;
+ u32 port;
+ u32 qpn;
+ u8 req;
+};
+
+/* User App Params */
+
+/**
+ * struct hbl_cni_set_user_app_params_in - NIC opcode HBL_CNI_OP_SET_USER_APP_PARAMS in param.
+ * allow the user application to set general parameters
+ * regarding the RDMA nic operation. These parameters stay
+ * in effect until the application releases the device
+ * @port: NIC port ID.
+ * @bp_offs: Offsets in NIC memory to signal a back pressure. Note that the advanced flag must be
+ * enabled in case it's being set.
+ * @advanced: A boolean that indicates whether this WQ should support advanced operations, such as
+ * RDV, QMan, WTD, etc.
+ * @adaptive_timeout_en: Enable adaptive timeout feature for this port.
+ */
+struct hbl_cni_set_user_app_params_in {
+ u32 port;
+ u32 bp_offs[HBL_CNI_USER_BP_OFFS_MAX];
+ u8 advanced;
+ u8 adaptive_timeout_en;
+};
+
+/**
+ * struct hbl_cni_get_user_app_params_in - NIC opcode HBL_CNI_OP_GET_USER_APP_PARAMS in param.
+ * @port: NIC port ID.
+ */
+struct hbl_cni_get_user_app_params_in {
+ u32 port;
+};
+
+/**
+ * struct hbl_cni_get_user_app_params_out - NIC opcode HBL_CNI_OP_GET_USER_APP_PARAMS out param.
+ * @max_num_of_qps: Number of QPs that are supported by the driver. User must allocate enough room
+ * for his work-queues according to this number.
+ * @num_allocated_qps: Number of QPs that were already allocated (in use).
+ * @max_allocated_qp_idx: The highest index of the allocated QPs (i.e. this is where the
+ * driver may allocate its next QP).
+ * @max_cq_size: Maximum size of a CQ buffer.
+ * @advanced: true if advanced features are supported.
+ * @max_num_of_cqs: Maximum number of CQs.
+ * @max_num_of_db_fifos: Maximum number of DB-FIFOs.
+ * @max_num_of_encaps: Maximum number of encapsulations.
+ * @speed: port speed in Mbps.
+ * @nic_macro_idx: macro index of this specific port.
+ * @nic_phys_port_idx: physical port index (AKA lane) of this specific port.
+ */
+struct hbl_cni_get_user_app_params_out {
+ u32 max_num_of_qps;
+ u32 num_allocated_qps;
+ u32 max_allocated_qp_idx;
+ u32 max_cq_size;
+ u8 advanced;
+ u8 max_num_of_cqs;
+ u8 max_num_of_db_fifos;
+ u8 max_num_of_encaps;
+ u32 speed;
+ u8 nic_macro_idx;
+ u8 nic_phys_port_idx;
+};
+
+/**
+ * struct hbl_cni_alloc_user_db_fifo_in - NIC opcode HBL_CNI_OP_ALLOC_USER_DB_FIFO in param
+ * @port: NIC port ID
+ * @id_hint: Hint to allocate a specific HW resource
+ */
+struct hbl_cni_alloc_user_db_fifo_in {
+ u32 port;
+ u32 id_hint;
+};
+
+/**
+ * struct hbl_cni_alloc_user_db_fifo_out - NIC opcode HBL_CNI_OP_ALLOC_USER_DB_FIFO out param
+ * @id: DB-FIFO ID
+ */
+struct hbl_cni_alloc_user_db_fifo_out {
+ u32 id;
+};
+
+/**
+ * enum hbl_nic_db_fifo_type - NIC users FIFO modes of operation.
+ * @HBL_CNI_DB_FIFO_TYPE_DB: mode for direct user door-bell submit.
+ * @HBL_CNI_DB_FIFO_TYPE_CC: mode for congestion control.
+ */
+enum hbl_nic_db_fifo_type {
+ HBL_CNI_DB_FIFO_TYPE_DB = 0,
+ HBL_CNI_DB_FIFO_TYPE_CC,
+};
+
+/**
+ * struct hbl_cni_user_db_fifo_set_in - NIC opcode HBL_CNI_OP_USER_DB_FIFO_SET in param.
+ * @port: NIC port ID
+ * @id: NIC DB-FIFO ID
+ * @mode: represents desired mode of operation for provided FIFO, according to hbl_nic_db_fifo_type
+ */
+struct hbl_cni_user_db_fifo_set_in {
+ u32 port;
+ u32 id;
+ u8 mode;
+};
+
+/**
+ * struct hbl_cni_user_db_fifo_set_out - NIC opcode HBL_CNI_OP_USER_DB_FIFO_SET out param.
+ * @ci_handle: Handle of DB-FIFO consumer-inder memory buffer.
+ * @regs_handle: Handle of DB-FIFO Registers base-address.
+ * @regs_offset: Offset to the DB-FIFO Registers.
+ * @fifo_size: fifo size that was allocated.
+ * @fifo_bp_thresh: fifo threshold that was set by the driver.
+ */
+struct hbl_cni_user_db_fifo_set_out {
+ u64 ci_handle;
+ u64 regs_handle;
+ u32 regs_offset;
+ u32 fifo_size;
+ u32 fifo_bp_thresh;
+};
+
+/**
+ * struct hbl_cni_user_db_fifo_unset_in - NIC opcode HBL_CNI_OP_USER_DB_FIFO_UNSET in param.
+ * @port: NIC port ID.
+ * @id: NIC DB-FIFO ID.
+ */
+struct hbl_cni_user_db_fifo_unset_in {
+ u32 port;
+ u32 id;
+};
+
+/* The operation completed successfully and an event was read */
+#define HBL_CNI_EQ_POLL_STATUS_SUCCESS 0
+/* The operation completed successfully, no event was found */
+#define HBL_CNI_EQ_POLL_STATUS_EQ_EMPTY 1
+/* The operation failed since it is not supported by the device/driver */
+#define HBL_CNI_EQ_POLL_STATUS_ERR_UNSUPPORTED_OP 2
+/* The operation failed, port was not found */
+#define HBL_CNI_EQ_POLL_STATUS_ERR_NO_SUCH_PORT 3
+/* The operation failed, port is disabled */
+#define HBL_CNI_EQ_POLL_STATUS_ERR_PORT_DISABLED 4
+/* The operation failed, an event-queue associated with the app was not found */
+#define HBL_CNI_EQ_POLL_STATUS_ERR_NO_SUCH_EQ 5
+/* The operation failed with an undefined error */
+#define HBL_CNI_EQ_POLL_STATUS_ERR_UNDEF 6
+
+/* completion-queue events */
+#define HBL_CNI_EQ_EVENT_TYPE_CQ_ERR 0
+/* Queue-pair events */
+#define HBL_CNI_EQ_EVENT_TYPE_QP_ERR 1
+/* Doorbell events */
+#define HBL_CNI_EQ_EVENT_TYPE_DB_FIFO_ERR 2
+/* congestion completion-queue events */
+#define HBL_CNI_EQ_EVENT_TYPE_CCQ 3
+/* Direct WQE security error. */
+#define HBL_CNI_EQ_EVENT_TYPE_WTD_SECURITY_ERR 4
+/* Numerical error */
+#define HBL_CNI_EQ_EVENT_TYPE_NUMERICAL_ERR 5
+/* Link status. */
+#define HBL_CNI_EQ_EVENT_TYPE_LINK_STATUS 6
+/* Queue-pair counters aligned */
+#define HBL_CNI_EQ_EVENT_TYPE_QP_ALIGN_COUNTERS 7
+
+/**
+ * struct hbl_cni_eq_poll_in - NIC opcode HBL_CNI_OP_EQ_POLL in param.
+ * @port: NIC port ID.
+ */
+struct hbl_cni_eq_poll_in {
+ u32 port;
+};
+
+/**
+ * struct hbl_cni_eq_poll_out - NIC opcode HBL_CNI_OP_EQ_POLL out param.
+ * @status: HBL_CNI_EQ_POLL_STATUS_*.
+ * @idx: Connection/CQ/DB-fifo index, depends on event type.
+ * @ev_data: Event-specific data.
+ * @ev_type: Event type.
+ * @rest_occurred: Was the error due to reset.
+ * @is_req: For QP events marks if corresponding QP is requestor.
+ */
+struct hbl_cni_eq_poll_out {
+ u32 status;
+ u32 idx;
+ u32 ev_data;
+ u8 ev_type;
+ u8 rest_occurred;
+ u8 is_req;
+};
+
+/**
+ * enum hbl_nic_encap_type - Supported encapsulation types
+ * @HBL_CNI_ENCAP_NONE: No Tunneling.
+ * @HBL_CNI_ENCAP_OVER_IPV4: Tunnel RDMA packets through L3 layer
+ * @HBL_CNI_ENCAP_OVER_UDP: Tunnel RDMA packets through L4 layer
+ */
+enum hbl_nic_encap_type {
+ HBL_CNI_ENCAP_NONE,
+ HBL_CNI_ENCAP_OVER_IPV4,
+ HBL_CNI_ENCAP_OVER_UDP,
+};
+
+/**
+ * struct hbl_cni_user_encap_alloc_in - NIC opcode HBL_CNI_OP_USER_ENCAP_ALLOC in param.
+ * @port: NIC port ID.
+ */
+struct hbl_cni_user_encap_alloc_in {
+ u32 port;
+};
+
+/**
+ * struct hbl_cni_user_encap_alloc_out - NIC opcode HBL_CNI_OP_USER_ENCAP_ALLOC out param.
+ * @id: Encapsulation ID.
+ */
+struct hbl_cni_user_encap_alloc_out {
+ u32 id;
+};
+
+/**
+ * struct hbl_cni_user_encap_set_in - NIC opcode HBL_CNI_OP_USER_ENCAP_SET in param.
+ * @tnl_hdr_ptr: Pointer to the tunnel encapsulation header. i.e. specific tunnel header data to be
+ * used in the encapsulation by the HW.
+ * @tnl_hdr_size: Tunnel encapsulation header size.
+ * @port: NIC port ID.
+ * @id: Encapsulation ID.
+ * @ipv4_addr: Source IP address, set regardless of encapsulation type.
+ * @udp_dst_port: The UDP destination-port. Valid for L4 tunnel.
+ * @ip_proto: IP protocol to use. Valid for L3 tunnel.
+ * @encap_type: Encapsulation type. May be either no-encapsulation or encapsulation over L3 or L4.
+ */
+struct hbl_cni_user_encap_set_in {
+ u64 tnl_hdr_ptr;
+ u32 tnl_hdr_size;
+ u32 port;
+ u32 id;
+ u32 ipv4_addr;
+ union {
+ u16 udp_dst_port;
+ u16 ip_proto;
+ };
+ u8 encap_type;
+};
+
+/**
+ * struct hbl_cni_user_encap_unset_in - NIC opcode HBL_CNI_OP_USER_ENCAP_UNSET in param.
+ * @port: NIC port ID.
+ * @id: Encapsulation ID.
+ */
+struct hbl_cni_user_encap_unset_in {
+ u32 port;
+ u32 id;
+};
+
+/**
+ * struct hbl_cni_user_ccq_set_in - NIC opcode HBL_CNI_OP_USER_CCQ_SET in param.
+ * @port: NIC port ID.
+ * @num_of_entries: Number of CCQ entries in the buffer.
+ */
+struct hbl_cni_user_ccq_set_in {
+ u32 port;
+ u32 num_of_entries;
+};
+
+/**
+ * struct hbl_cni_user_ccq_set_out - NIC opcode HBL_CNI_OP_USER_CCQ_SET out param.
+ * @mem_handle: Handle of CCQ memory buffer.
+ * @pi_handle: Handle of CCQ producer-index memory buffer.
+ * @id: CQ ID.
+ */
+struct hbl_cni_user_ccq_set_out {
+ u64 mem_handle;
+ u64 pi_handle;
+ u32 id;
+};
+
+/**
+ * struct hbl_cni_user_ccq_unset_in - NIC opcode HBL_CNI_OP_USER_CCQ_UNSET in param.
+ * @port: NIC port ID.
+ */
+struct hbl_cni_user_ccq_unset_in {
+ u32 port;
+};
+
+/* Opcode to allocate connection ID */
+#define HBL_CNI_OP_ALLOC_CONN 0
+/* Opcode to set up a requester connection context */
+#define HBL_CNI_OP_SET_REQ_CONN_CTX 1
+/* Opcode to set up a responder connection context */
+#define HBL_CNI_OP_SET_RES_CONN_CTX 2
+/* Opcode to destroy a connection */
+#define HBL_CNI_OP_DESTROY_CONN 3
+/* Opcode reserved (deprecated) */
+#define HBL_CNI_OP_RESERVED0 4
+/* Opcode reserved (deprecated) */
+#define HBL_CNI_OP_RESERVED1 5
+/* Opcode reserved (deprecated) */
+#define HBL_CNI_OP_RESERVED2 6
+/* Opcode reserved (deprecated) */
+#define HBL_CNI_OP_RESERVED3 7
+/* Opcode reserved (deprecated) */
+#define HBL_CNI_OP_RESERVED4 8
+/* Opcode to set a user WQ array */
+#define HBL_CNI_OP_USER_WQ_SET 9
+/* Opcode to unset a user WQ array */
+#define HBL_CNI_OP_USER_WQ_UNSET 10
+/* Opcode reserved */
+#define HBL_CNI_OP_RESERVED5 11
+/* Opcode reserved */
+#define HBL_CNI_OP_RESERVED6 12
+/* Opcode reserved */
+#define HBL_CNI_OP_RESERVED7 13
+/* Opcode to allocate a CQ */
+#define HBL_CNI_OP_ALLOC_USER_CQ_ID 14
+/* Opcode to set specific user-application parameters */
+#define HBL_CNI_OP_SET_USER_APP_PARAMS 15
+/* Opcode to get specific user-application parameters */
+#define HBL_CNI_OP_GET_USER_APP_PARAMS 16
+/* Opcode to allocate a DB-FIFO */
+#define HBL_CNI_OP_ALLOC_USER_DB_FIFO 17
+/* Opcode to create a DB-FIFO */
+#define HBL_CNI_OP_USER_DB_FIFO_SET 18
+/* Opcode to destroy a DB-FIFO */
+#define HBL_CNI_OP_USER_DB_FIFO_UNSET 19
+/* Opcode to poll on EQ */
+#define HBL_CNI_OP_EQ_POLL 20
+/* Opcode to allocate encapsulation ID */
+#define HBL_CNI_OP_USER_ENCAP_ALLOC 21
+/* Opcode to create an encapsulation */
+#define HBL_CNI_OP_USER_ENCAP_SET 22
+/* Opcode to destroy an encapsulation */
+#define HBL_CNI_OP_USER_ENCAP_UNSET 23
+/* Opcode to create a CCQ */
+#define HBL_CNI_OP_USER_CCQ_SET 24
+/* Opcode to destroy a CCQ */
+#define HBL_CNI_OP_USER_CCQ_UNSET 25
+/* Opcode to set user CQ by ID */
+#define HBL_CNI_OP_USER_CQ_ID_SET 26
+/* Opcode to unset user CQ by ID */
+#define HBL_CNI_OP_USER_CQ_ID_UNSET 27
+/* Opcode reserved */
+#define HBL_CNI_OP_RESERVED8 28
+/* Opcode to dump the context of a QP */
+#define HBL_CNI_OP_DUMP_QP 29
+
+#endif /* HBL_CNI_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* Re: [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver
2024-06-13 8:21 ` [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver Omer Shpigelman
@ 2024-06-13 13:01 ` Przemek Kitszel
2024-06-13 14:16 ` Przemek Kitszel
2024-06-17 8:08 ` Omer Shpigelman
2024-06-15 0:05 ` Stephen Hemminger
2024-06-17 14:05 ` Markus Elfring
2 siblings, 2 replies; 108+ messages in thread
From: Przemek Kitszel @ 2024-06-13 13:01 UTC (permalink / raw)
To: Omer Shpigelman, linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, zyehudai
On 6/13/24 10:21, Omer Shpigelman wrote:
> Add the hbl_cn driver which will serve both Ethernet and InfiniBand
> drivers.
> hbl_cn is the layer which is used by the satellite drivers for many shared
> operations that are needed by both EN and IB subsystems like QPs, CQs etc.
> The CN driver is initialized via auxiliary bus by the habanalabs driver.
>
> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> Co-developed-by: David Meriin <dmeriin@habana.ai>
> Signed-off-by: David Meriin <dmeriin@habana.ai>
> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
> ---
> .../device_drivers/ethernet/index.rst | 1 +
> .../device_drivers/ethernet/intel/hbl.rst | 82 +
> MAINTAINERS | 11 +
> drivers/net/ethernet/intel/Kconfig | 20 +
> drivers/net/ethernet/intel/Makefile | 1 +
> drivers/net/ethernet/intel/hbl_cn/Makefile | 9 +
> .../net/ethernet/intel/hbl_cn/common/Makefile | 3 +
> .../net/ethernet/intel/hbl_cn/common/hbl_cn.c | 5954 +++++++++++++++++
> .../net/ethernet/intel/hbl_cn/common/hbl_cn.h | 1627 +++++
> .../ethernet/intel/hbl_cn/common/hbl_cn_drv.c | 220 +
> .../intel/hbl_cn/common/hbl_cn_memory.c | 40 +
> .../ethernet/intel/hbl_cn/common/hbl_cn_phy.c | 33 +
> .../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 13 +
> include/linux/habanalabs/cpucp_if.h | 125 +-
> include/linux/habanalabs/hl_boot_if.h | 9 +-
> include/linux/net/intel/cn.h | 474 ++
> include/linux/net/intel/cn_aux.h | 298 +
> include/linux/net/intel/cni.h | 636 ++
> 18 files changed, 9545 insertions(+), 11 deletions(-)
this is a very big patch, it asks for a split; what's worse, it's
proportional to the size of this series:
146 files changed, 148514 insertions(+), 70 deletions(-)
which is just too big
[...]
> +Support
> +=======
> +For general information, go to the Intel support website at:
> +https://www.intel.com/support/
> +
> +If an issue is identified with the released source code on a supported kernel
> +with a supported adapter, email the specific information related to the issue
> +to intel-wired-lan@lists.osuosl.org.
I'm welcoming you to post next version of the driver to the IWL mailing
list, and before that, to go through our Intel path for ethernet
subsystem (rdma and a few smaller ones also go through that)
(that starts internally, I will PM you the details)
[...]
> +++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
> @@ -0,0 +1,5954 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#include "hbl_cn.h"
> +
> +#include <linux/file.h>
> +#include <linux/module.h>
> +#include <linux/overflow.h>
> +#include <linux/pci.h>
> +#include <linux/slab.h>
> +
> +#define NIC_MIN_WQS_PER_PORT 2
> +
> +#define NIC_SEQ_RESETS_TIMEOUT_MS 15000 /* 15 seconds */
> +#define NIC_MAX_SEQ_RESETS 3
> +
> +#define HBL_CN_IPV4_PROTOCOL_UDP 17
> +
> +/* SOB mask is not expected to change across ASIC. Hence common defines. */
> +#define NIC_SOB_INC_MASK 0x80000000
> +#define NIC_SOB_VAL_MASK 0x7fff
> +
> +#define NIC_DUMP_QP_SZ SZ_4K
> +
> +#define HBL_AUX2NIC(aux_dev) \
> + ({ \
> + struct hbl_aux_dev *__aux_dev = (aux_dev); \
> + ((__aux_dev)->type == HBL_AUX_DEV_ETH) ? \
> + container_of(__aux_dev, struct hbl_cn_device, en_aux_dev) : \
> + container_of(__aux_dev, struct hbl_cn_device, ib_aux_dev); \
> + })
this should be a function
> +
> +#define RAND_STAT_CNT(cnt) \
> + do { \
> + u32 __cnt = get_random_u32(); \
> + (cnt) = __cnt; \
> + dev_info(hdev->dev, "port %d, %s: %u\n", port, #cnt, __cnt); \
no way for such message, ditto for the function
> + } while (0)
> +
> +struct hbl_cn_stat hbl_cn_mac_fec_stats[] = {
> + {"correctable_errors", 0x2, 0x3},
> + {"uncorrectable_errors", 0x4, 0x5}
> +};
> +
> +struct hbl_cn_stat hbl_cn_mac_stats_rx[] = {
> + {"Octets", 0x0},
> + {"OctetsReceivedOK", 0x4},
> + {"aAlignmentErrors", 0x8},
> + {"aPAUSEMACCtrlFramesReceived", 0xC},
> + {"aFrameTooLongErrors", 0x10},
> + {"aInRangeLengthErrors", 0x14},
> + {"aFramesReceivedOK", 0x18},
> + {"aFrameCheckSequenceErrors", 0x1C},
> + {"VLANReceivedOK", 0x20},
> + {"ifInErrors", 0x24},
> + {"ifInUcastPkts", 0x28},
> + {"ifInMulticastPkts", 0x2C},
> + {"ifInBroadcastPkts", 0x30},
> + {"DropEvents", 0x34},
> + {"Pkts", 0x38},
> + {"UndersizePkts", 0x3C},
> + {"Pkts64Octets", 0x40},
> + {"Pkts65to127Octets", 0x44},
> + {"Pkts128to255Octets", 0x48},
> + {"Pkts256to511Octets", 0x4C},
> + {"Pkts512to1023Octets", 0x50},
> + {"Pkts1024to1518Octets", 0x54},
> + {"Pkts1519toMaxOctets", 0x58},
> + {"OversizePkts", 0x5C},
> + {"Jabbers", 0x60},
> + {"Fragments", 0x64},
> + {"aCBFCPAUSERx0", 0x68},
> + {"aCBFCPAUSERx1", 0x6C},
> + {"aCBFCPAUSERx2", 0x70},
> + {"aCBFCPAUSERx3", 0x74},
> + {"aCBFCPAUSERx4", 0x78},
> + {"aCBFCPAUSERx5", 0x7C},
> + {"aCBFCPAUSERx6", 0x80},
> + {"aCBFCPAUSERx7", 0x84},
> + {"aMACControlFramesReceived", 0x88}
> +};
> +
> +struct hbl_cn_stat hbl_cn_mac_stats_tx[] = {
> + {"Octets", 0x0},
> + {"OctetsTransmittedOK", 0x4},
> + {"aPAUSEMACCtrlFramesTransmitted", 0x8},
> + {"aFramesTransmittedOK", 0xC},
> + {"VLANTransmittedOK", 0x10},
> + {"ifOutErrors", 0x14},
> + {"ifOutUcastPkts", 0x18},
> + {"ifOutMulticastPkts", 0x1C},
> + {"ifOutBroadcastPkts", 0x20},
> + {"Pkts64Octets", 0x24},
> + {"Pkts65to127Octets", 0x28},
> + {"Pkts128to255Octets", 0x2C},
> + {"Pkts256to511Octets", 0x30},
> + {"Pkts512to1023Octets", 0x34},
> + {"Pkts1024to1518Octets", 0x38},
> + {"Pkts1519toMaxOctets", 0x3C},
> + {"aCBFCPAUSETx0", 0x40},
> + {"aCBFCPAUSETx1", 0x44},
> + {"aCBFCPAUSETx2", 0x48},
> + {"aCBFCPAUSETx3", 0x4C},
> + {"aCBFCPAUSETx4", 0x50},
> + {"aCBFCPAUSETx5", 0x54},
> + {"aCBFCPAUSETx6", 0x58},
> + {"aCBFCPAUSETx7", 0x5C},
> + {"aMACControlFramesTx", 0x60},
> + {"Pkts", 0x64}
> +};
> +
> +static const char pcs_counters_str[][ETH_GSTRING_LEN] = {
> + {"pcs_local_faults"},
> + {"pcs_remote_faults"},
> + {"pcs_remote_fault_reconfig"},
> + {"pcs_link_restores"},
> + {"pcs_link_toggles"},
> +};
> +
> +static size_t pcs_counters_str_len = ARRAY_SIZE(pcs_counters_str);
> +size_t hbl_cn_mac_fec_stats_len = ARRAY_SIZE(hbl_cn_mac_fec_stats);
> +size_t hbl_cn_mac_stats_rx_len = ARRAY_SIZE(hbl_cn_mac_stats_rx);
> +size_t hbl_cn_mac_stats_tx_len = ARRAY_SIZE(hbl_cn_mac_stats_tx);
why those are not const?
> +
> +static void qps_stop(struct hbl_cn_device *hdev);
> +static void qp_destroy_work(struct work_struct *work);
> +static int __user_wq_arr_unset(struct hbl_cn_ctx *ctx, struct hbl_cn_port *cn_port, u32 type);
> +static void user_cq_destroy(struct kref *kref);
> +static void set_app_params_clear(struct hbl_cn_device *hdev);
> +static int hbl_cn_ib_cmd_ctrl(struct hbl_aux_dev *aux_dev, void *cn_ib_ctx, u32 op, void *input,
> + void *output);
> +static int hbl_cn_ib_query_mem_handle(struct hbl_aux_dev *ib_aux_dev, u64 mem_handle,
> + struct hbl_ib_mem_info *info);
> +
> +static void hbl_cn_reset_stats_counters_port(struct hbl_cn_device *hdev, u32 port);
> +static void hbl_cn_late_init(struct hbl_cn_device *hdev);
> +static void hbl_cn_late_fini(struct hbl_cn_device *hdev);
> +static int hbl_cn_sw_init(struct hbl_cn_device *hdev);
> +static void hbl_cn_sw_fini(struct hbl_cn_device *hdev);
> +static void hbl_cn_spmu_init(struct hbl_cn_port *cn_port, bool full);
> +static int hbl_cn_cmd_port_check(struct hbl_cn_device *hdev, u32 port, u32 flags);
> +static void hbl_cn_qps_stop(struct hbl_cn_port *cn_port);
> +
> +static int hbl_cn_request_irqs(struct hbl_cn_device *hdev)
> +{
> + struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
> +
> + return asic_funcs->request_irqs(hdev);
> +}
> +
> +static void hbl_cn_free_irqs(struct hbl_cn_device *hdev)
> +{
> + struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
> +
> + asic_funcs->free_irqs(hdev);
> +}
> +
> +static void hbl_cn_synchronize_irqs(struct hbl_aux_dev *cn_aux_dev)
> +{
> + struct hbl_cn_device *hdev = cn_aux_dev->priv;
> + struct hbl_cn_asic_funcs *asic_funcs;
> +
> + asic_funcs = hdev->asic_funcs;
> +
> + asic_funcs->synchronize_irqs(hdev);
> +}
> +
> +void hbl_cn_get_frac_info(u64 numerator, u64 denominator, u64 *integer, u64 *exp)
> +{
> + u64 high_digit_n, high_digit_d, integer_tmp, exp_tmp;
> + u8 num_digits_n, num_digits_d;
> + int i;
> +
> + num_digits_d = hbl_cn_get_num_of_digits(denominator);
> + high_digit_d = denominator;
> + for (i = 0; i < num_digits_d - 1; i++)
> + high_digit_d /= 10;
> +
> + integer_tmp = 0;
> + exp_tmp = 0;
> +
> + if (numerator) {
> + num_digits_n = hbl_cn_get_num_of_digits(numerator);
> + high_digit_n = numerator;
> + for (i = 0; i < num_digits_n - 1; i++)
> + high_digit_n /= 10;
> +
> + exp_tmp = num_digits_d - num_digits_n;
> +
> + if (high_digit_n < high_digit_d) {
> + high_digit_n *= 10;
> + exp_tmp++;
> + }
> +
> + integer_tmp = div_u64(high_digit_n, high_digit_d);
> + }
> +
> + *integer = integer_tmp;
> + *exp = exp_tmp;
> +}
this function sounds suspicious for a network driver, what do you need
it for?
> +
> +int hbl_cn_read_spmu_counters(struct hbl_cn_port *cn_port, u64 out_data[], u32 *num_out_data)
> +{
> + struct hbl_cn_device *hdev = cn_port->hdev;
> + struct hbl_cn_asic_port_funcs *port_funcs;
> + struct hbl_cn_stat *ignore;
> + int rc;
> +
> + port_funcs = hdev->asic_funcs->port_funcs;
> +
> + port_funcs->spmu_get_stats_info(cn_port, &ignore, num_out_data);
hard to ignore that you deref uninitialized pointer...
please consider going one step back and start with our internal mailing
lists, thank you
Przemek
[...]
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver
2024-06-13 13:01 ` Przemek Kitszel
@ 2024-06-13 14:16 ` Przemek Kitszel
2024-06-17 8:08 ` Omer Shpigelman
1 sibling, 0 replies; 108+ messages in thread
From: Przemek Kitszel @ 2024-06-13 14:16 UTC (permalink / raw)
To: Omer Shpigelman, linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, zyehudai
On 6/13/24 15:01, Przemek Kitszel wrote:
> On 6/13/24 10:21, Omer Shpigelman wrote:
[...]
>> +
>> +int hbl_cn_read_spmu_counters(struct hbl_cn_port *cn_port, u64
>> out_data[], u32 *num_out_data)
>> +{
>> + struct hbl_cn_device *hdev = cn_port->hdev;
>> + struct hbl_cn_asic_port_funcs *port_funcs;
>> + struct hbl_cn_stat *ignore;
>> + int rc;
>> +
>> + port_funcs = hdev->asic_funcs->port_funcs;
>> +
>> + port_funcs->spmu_get_stats_info(cn_port, &ignore, num_out_data);
>
> hard to ignore that you deref uninitialized pointer...
oh, sorry, I was in hurry, please disregard this particular comment
>
> please consider going one step back and start with our internal mailing
> lists, thank you
> Przemek
but this option very much still holds
>
> [...]
>
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver
2024-06-13 13:01 ` Przemek Kitszel
2024-06-13 14:16 ` Przemek Kitszel
@ 2024-06-17 8:08 ` Omer Shpigelman
2024-06-17 11:48 ` Leon Romanovsky
1 sibling, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-17 8:08 UTC (permalink / raw)
To: Przemek Kitszel, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org
Cc: ogabbay@kernel.org, Zvika Yehudai
On 6/13/24 16:01, Przemek Kitszel wrote:
> [Some people who received this message don't often get email from przemyslaw.kitszel@intel.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On 6/13/24 10:21, Omer Shpigelman wrote:
>> Add the hbl_cn driver which will serve both Ethernet and InfiniBand
>> drivers.
>> hbl_cn is the layer which is used by the satellite drivers for many shared
>> operations that are needed by both EN and IB subsystems like QPs, CQs etc.
>> The CN driver is initialized via auxiliary bus by the habanalabs driver.
>>
>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
>> Co-developed-by: David Meriin <dmeriin@habana.ai>
>> Signed-off-by: David Meriin <dmeriin@habana.ai>
>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
>> ---
>> .../device_drivers/ethernet/index.rst | 1 +
>> .../device_drivers/ethernet/intel/hbl.rst | 82 +
>> MAINTAINERS | 11 +
>> drivers/net/ethernet/intel/Kconfig | 20 +
>> drivers/net/ethernet/intel/Makefile | 1 +
>> drivers/net/ethernet/intel/hbl_cn/Makefile | 9 +
>> .../net/ethernet/intel/hbl_cn/common/Makefile | 3 +
>> .../net/ethernet/intel/hbl_cn/common/hbl_cn.c | 5954 +++++++++++++++++
>> .../net/ethernet/intel/hbl_cn/common/hbl_cn.h | 1627 +++++
>> .../ethernet/intel/hbl_cn/common/hbl_cn_drv.c | 220 +
>> .../intel/hbl_cn/common/hbl_cn_memory.c | 40 +
>> .../ethernet/intel/hbl_cn/common/hbl_cn_phy.c | 33 +
>> .../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 13 +
>> include/linux/habanalabs/cpucp_if.h | 125 +-
>> include/linux/habanalabs/hl_boot_if.h | 9 +-
>> include/linux/net/intel/cn.h | 474 ++
>> include/linux/net/intel/cn_aux.h | 298 +
>> include/linux/net/intel/cni.h | 636 ++
>> 18 files changed, 9545 insertions(+), 11 deletions(-)
>
> this is a very big patch, it asks for a split; what's worse, it's
> proportional to the size of this series:
> 146 files changed, 148514 insertions(+), 70 deletions(-)
> which is just too big
>
> [...]
>
Yeah, well I'm limited to 15 patches per patch set according to the kernel
doc so I had to have this big patch.
Our changes are contained in 4 different drivers and all of the changes
should be merged together so the HW will be operational.
Hence I had to squeeze some code to a big patch.
>> +Support
>> +=======
>> +For general information, go to the Intel support website at:
>> +https://www.intel.com/support/
>> +
>> +If an issue is identified with the released source code on a supported kernel
>> +with a supported adapter, email the specific information related to the issue
>> +to intel-wired-lan@lists.osuosl.org.
>
> I'm welcoming you to post next version of the driver to the IWL mailing
> list, and before that, to go through our Intel path for ethernet
> subsystem (rdma and a few smaller ones also go through that)
> (that starts internally, I will PM you the details)
>
> [...]
>
Ok, I'll go the Intel path first.
>> +++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
>> @@ -0,0 +1,5954 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/* Copyright 2020-2024 HabanaLabs, Ltd.
>> + * Copyright (C) 2023-2024, Intel Corporation.
>> + * All Rights Reserved.
>> + */
>> +
>> +#include "hbl_cn.h"
>> +
>> +#include <linux/file.h>
>> +#include <linux/module.h>
>> +#include <linux/overflow.h>
>> +#include <linux/pci.h>
>> +#include <linux/slab.h>
>> +
>> +#define NIC_MIN_WQS_PER_PORT 2
>> +
>> +#define NIC_SEQ_RESETS_TIMEOUT_MS 15000 /* 15 seconds */
>> +#define NIC_MAX_SEQ_RESETS 3
>> +
>> +#define HBL_CN_IPV4_PROTOCOL_UDP 17
>> +
>> +/* SOB mask is not expected to change across ASIC. Hence common defines. */
>> +#define NIC_SOB_INC_MASK 0x80000000
>> +#define NIC_SOB_VAL_MASK 0x7fff
>> +
>> +#define NIC_DUMP_QP_SZ SZ_4K
>> +
>> +#define HBL_AUX2NIC(aux_dev) \
>> + ({ \
>> + struct hbl_aux_dev *__aux_dev = (aux_dev); \
>> + ((__aux_dev)->type == HBL_AUX_DEV_ETH) ? \
>> + container_of(__aux_dev, struct hbl_cn_device, en_aux_dev) : \
>> + container_of(__aux_dev, struct hbl_cn_device, ib_aux_dev); \
>> + })
>
> this should be a function
>
I'll switch it to a function.
>> +
>> +#define RAND_STAT_CNT(cnt) \
>> + do { \
>> + u32 __cnt = get_random_u32(); \
>> + (cnt) = __cnt; \
>> + dev_info(hdev->dev, "port %d, %s: %u\n", port, #cnt, __cnt); \
>
> no way for such message, ditto for the function
>
The thing is that I'd like to print the counter name and it's value.
For that I need to stringify the counter name.
IMO it is nicer to have the current code rather than something like:
RAND_STAT_CNT(status->high_ber_reinit,
__stringify(status->high_ber_reinit));
RAND_STAT_CNT(status->correctable_err_cnt,
__stringify(status->correctable_err_cnt));
or:
RAND_STAT_CNT(status->high_ber_reinit, "high_ber_reinit");
RAND_STAT_CNT(status->correctable_err_cnt, "correctable_err_cnt");
But I'll change it if it's not common to print from macros.
>> + } while (0)
>> +
>> +struct hbl_cn_stat hbl_cn_mac_fec_stats[] = {
>> + {"correctable_errors", 0x2, 0x3},
>> + {"uncorrectable_errors", 0x4, 0x5}
>> +};
>> +
>> +struct hbl_cn_stat hbl_cn_mac_stats_rx[] = {
>> + {"Octets", 0x0},
>> + {"OctetsReceivedOK", 0x4},
>> + {"aAlignmentErrors", 0x8},
>> + {"aPAUSEMACCtrlFramesReceived", 0xC},
>> + {"aFrameTooLongErrors", 0x10},
>> + {"aInRangeLengthErrors", 0x14},
>> + {"aFramesReceivedOK", 0x18},
>> + {"aFrameCheckSequenceErrors", 0x1C},
>> + {"VLANReceivedOK", 0x20},
>> + {"ifInErrors", 0x24},
>> + {"ifInUcastPkts", 0x28},
>> + {"ifInMulticastPkts", 0x2C},
>> + {"ifInBroadcastPkts", 0x30},
>> + {"DropEvents", 0x34},
>> + {"Pkts", 0x38},
>> + {"UndersizePkts", 0x3C},
>> + {"Pkts64Octets", 0x40},
>> + {"Pkts65to127Octets", 0x44},
>> + {"Pkts128to255Octets", 0x48},
>> + {"Pkts256to511Octets", 0x4C},
>> + {"Pkts512to1023Octets", 0x50},
>> + {"Pkts1024to1518Octets", 0x54},
>> + {"Pkts1519toMaxOctets", 0x58},
>> + {"OversizePkts", 0x5C},
>> + {"Jabbers", 0x60},
>> + {"Fragments", 0x64},
>> + {"aCBFCPAUSERx0", 0x68},
>> + {"aCBFCPAUSERx1", 0x6C},
>> + {"aCBFCPAUSERx2", 0x70},
>> + {"aCBFCPAUSERx3", 0x74},
>> + {"aCBFCPAUSERx4", 0x78},
>> + {"aCBFCPAUSERx5", 0x7C},
>> + {"aCBFCPAUSERx6", 0x80},
>> + {"aCBFCPAUSERx7", 0x84},
>> + {"aMACControlFramesReceived", 0x88}
>> +};
>> +
>> +struct hbl_cn_stat hbl_cn_mac_stats_tx[] = {
>> + {"Octets", 0x0},
>> + {"OctetsTransmittedOK", 0x4},
>> + {"aPAUSEMACCtrlFramesTransmitted", 0x8},
>> + {"aFramesTransmittedOK", 0xC},
>> + {"VLANTransmittedOK", 0x10},
>> + {"ifOutErrors", 0x14},
>> + {"ifOutUcastPkts", 0x18},
>> + {"ifOutMulticastPkts", 0x1C},
>> + {"ifOutBroadcastPkts", 0x20},
>> + {"Pkts64Octets", 0x24},
>> + {"Pkts65to127Octets", 0x28},
>> + {"Pkts128to255Octets", 0x2C},
>> + {"Pkts256to511Octets", 0x30},
>> + {"Pkts512to1023Octets", 0x34},
>> + {"Pkts1024to1518Octets", 0x38},
>> + {"Pkts1519toMaxOctets", 0x3C},
>> + {"aCBFCPAUSETx0", 0x40},
>> + {"aCBFCPAUSETx1", 0x44},
>> + {"aCBFCPAUSETx2", 0x48},
>> + {"aCBFCPAUSETx3", 0x4C},
>> + {"aCBFCPAUSETx4", 0x50},
>> + {"aCBFCPAUSETx5", 0x54},
>> + {"aCBFCPAUSETx6", 0x58},
>> + {"aCBFCPAUSETx7", 0x5C},
>> + {"aMACControlFramesTx", 0x60},
>> + {"Pkts", 0x64}
>> +};
>> +
>> +static const char pcs_counters_str[][ETH_GSTRING_LEN] = {
>> + {"pcs_local_faults"},
>> + {"pcs_remote_faults"},
>> + {"pcs_remote_fault_reconfig"},
>> + {"pcs_link_restores"},
>> + {"pcs_link_toggles"},
>> +};
>> +
>> +static size_t pcs_counters_str_len = ARRAY_SIZE(pcs_counters_str);
>> +size_t hbl_cn_mac_fec_stats_len = ARRAY_SIZE(hbl_cn_mac_fec_stats);
>> +size_t hbl_cn_mac_stats_rx_len = ARRAY_SIZE(hbl_cn_mac_stats_rx);
>> +size_t hbl_cn_mac_stats_tx_len = ARRAY_SIZE(hbl_cn_mac_stats_tx);
>
> why those are not const?
>
I'll add const.
>> +
>> +static void qps_stop(struct hbl_cn_device *hdev);
>> +static void qp_destroy_work(struct work_struct *work);
>> +static int __user_wq_arr_unset(struct hbl_cn_ctx *ctx, struct hbl_cn_port *cn_port, u32 type);
>> +static void user_cq_destroy(struct kref *kref);
>> +static void set_app_params_clear(struct hbl_cn_device *hdev);
>> +static int hbl_cn_ib_cmd_ctrl(struct hbl_aux_dev *aux_dev, void *cn_ib_ctx, u32 op, void *input,
>> + void *output);
>> +static int hbl_cn_ib_query_mem_handle(struct hbl_aux_dev *ib_aux_dev, u64 mem_handle,
>> + struct hbl_ib_mem_info *info);
>> +
>> +static void hbl_cn_reset_stats_counters_port(struct hbl_cn_device *hdev, u32 port);
>> +static void hbl_cn_late_init(struct hbl_cn_device *hdev);
>> +static void hbl_cn_late_fini(struct hbl_cn_device *hdev);
>> +static int hbl_cn_sw_init(struct hbl_cn_device *hdev);
>> +static void hbl_cn_sw_fini(struct hbl_cn_device *hdev);
>> +static void hbl_cn_spmu_init(struct hbl_cn_port *cn_port, bool full);
>> +static int hbl_cn_cmd_port_check(struct hbl_cn_device *hdev, u32 port, u32 flags);
>> +static void hbl_cn_qps_stop(struct hbl_cn_port *cn_port);
>> +
>> +static int hbl_cn_request_irqs(struct hbl_cn_device *hdev)
>> +{
>> + struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
>> +
>> + return asic_funcs->request_irqs(hdev);
>> +}
>> +
>> +static void hbl_cn_free_irqs(struct hbl_cn_device *hdev)
>> +{
>> + struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
>> +
>> + asic_funcs->free_irqs(hdev);
>> +}
>> +
>> +static void hbl_cn_synchronize_irqs(struct hbl_aux_dev *cn_aux_dev)
>> +{
>> + struct hbl_cn_device *hdev = cn_aux_dev->priv;
>> + struct hbl_cn_asic_funcs *asic_funcs;
>> +
>> + asic_funcs = hdev->asic_funcs;
>> +
>> + asic_funcs->synchronize_irqs(hdev);
>> +}
>> +
>> +void hbl_cn_get_frac_info(u64 numerator, u64 denominator, u64 *integer, u64 *exp)
>> +{
>> + u64 high_digit_n, high_digit_d, integer_tmp, exp_tmp;
>> + u8 num_digits_n, num_digits_d;
>> + int i;
>> +
>> + num_digits_d = hbl_cn_get_num_of_digits(denominator);
>> + high_digit_d = denominator;
>> + for (i = 0; i < num_digits_d - 1; i++)
>> + high_digit_d /= 10;
>> +
>> + integer_tmp = 0;
>> + exp_tmp = 0;
>> +
>> + if (numerator) {
>> + num_digits_n = hbl_cn_get_num_of_digits(numerator);
>> + high_digit_n = numerator;
>> + for (i = 0; i < num_digits_n - 1; i++)
>> + high_digit_n /= 10;
>> +
>> + exp_tmp = num_digits_d - num_digits_n;
>> +
>> + if (high_digit_n < high_digit_d) {
>> + high_digit_n *= 10;
>> + exp_tmp++;
>> + }
>> +
>> + integer_tmp = div_u64(high_digit_n, high_digit_d);
>> + }
>> +
>> + *integer = integer_tmp;
>> + *exp = exp_tmp;
>> +}
>
> this function sounds suspicious for a network driver, what do you need
> it for?
>
Some of our counters are exposed by the HW with numerator/denominator
representation and we'd like to expose them to the user with exponent
representation.
This function converts a counter value from one representation to the
other.
>> +
>> +int hbl_cn_read_spmu_counters(struct hbl_cn_port *cn_port, u64 out_data[], u32 *num_out_data)
>> +{
>> + struct hbl_cn_device *hdev = cn_port->hdev;
>> + struct hbl_cn_asic_port_funcs *port_funcs;
>> + struct hbl_cn_stat *ignore;
>> + int rc;
>> +
>> + port_funcs = hdev->asic_funcs->port_funcs;
>> +
>> + port_funcs->spmu_get_stats_info(cn_port, &ignore, num_out_data);
>
> hard to ignore that you deref uninitialized pointer...
>
> please consider going one step back and start with our internal mailing
> lists, thank you
> Przemek
>
> [...]
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver
2024-06-17 8:08 ` Omer Shpigelman
@ 2024-06-17 11:48 ` Leon Romanovsky
2024-06-18 7:28 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Leon Romanovsky @ 2024-06-17 11:48 UTC (permalink / raw)
To: Omer Shpigelman
Cc: Przemek Kitszel, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On Mon, Jun 17, 2024 at 08:08:26AM +0000, Omer Shpigelman wrote:
> On 6/13/24 16:01, Przemek Kitszel wrote:
> > [Some people who received this message don't often get email from przemyslaw.kitszel@intel.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > On 6/13/24 10:21, Omer Shpigelman wrote:
> >> Add the hbl_cn driver which will serve both Ethernet and InfiniBand
> >> drivers.
> >> hbl_cn is the layer which is used by the satellite drivers for many shared
> >> operations that are needed by both EN and IB subsystems like QPs, CQs etc.
> >> The CN driver is initialized via auxiliary bus by the habanalabs driver.
> >>
> >> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> >> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> >> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> >> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> >> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> >> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> >> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> >> Co-developed-by: David Meriin <dmeriin@habana.ai>
> >> Signed-off-by: David Meriin <dmeriin@habana.ai>
> >> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> >> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> >> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> >> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
> >> ---
> >> .../device_drivers/ethernet/index.rst | 1 +
> >> .../device_drivers/ethernet/intel/hbl.rst | 82 +
> >> MAINTAINERS | 11 +
> >> drivers/net/ethernet/intel/Kconfig | 20 +
> >> drivers/net/ethernet/intel/Makefile | 1 +
> >> drivers/net/ethernet/intel/hbl_cn/Makefile | 9 +
> >> .../net/ethernet/intel/hbl_cn/common/Makefile | 3 +
> >> .../net/ethernet/intel/hbl_cn/common/hbl_cn.c | 5954 +++++++++++++++++
> >> .../net/ethernet/intel/hbl_cn/common/hbl_cn.h | 1627 +++++
> >> .../ethernet/intel/hbl_cn/common/hbl_cn_drv.c | 220 +
> >> .../intel/hbl_cn/common/hbl_cn_memory.c | 40 +
> >> .../ethernet/intel/hbl_cn/common/hbl_cn_phy.c | 33 +
> >> .../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 13 +
> >> include/linux/habanalabs/cpucp_if.h | 125 +-
> >> include/linux/habanalabs/hl_boot_if.h | 9 +-
> >> include/linux/net/intel/cn.h | 474 ++
> >> include/linux/net/intel/cn_aux.h | 298 +
> >> include/linux/net/intel/cni.h | 636 ++
> >> 18 files changed, 9545 insertions(+), 11 deletions(-)
> >
> > this is a very big patch, it asks for a split; what's worse, it's
> > proportional to the size of this series:
> > 146 files changed, 148514 insertions(+), 70 deletions(-)
> > which is just too big
> >
> > [...]
> >
>
> Yeah, well I'm limited to 15 patches per patch set according to the kernel
> doc so I had to have this big patch.
> Our changes are contained in 4 different drivers and all of the changes
> should be merged together so the HW will be operational.
> Hence I had to squeeze some code to a big patch.
Submit your code in multiple steps. One driver at a time.
Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver
2024-06-17 11:48 ` Leon Romanovsky
@ 2024-06-18 7:28 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-18 7:28 UTC (permalink / raw)
To: Leon Romanovsky
Cc: Przemek Kitszel, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On 6/17/24 14:48, Leon Romanovsky wrote:
> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On Mon, Jun 17, 2024 at 08:08:26AM +0000, Omer Shpigelman wrote:
>> On 6/13/24 16:01, Przemek Kitszel wrote:
>>> [Some people who received this message don't often get email from przemyslaw.kitszel@intel.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>
>>> On 6/13/24 10:21, Omer Shpigelman wrote:
>>>> Add the hbl_cn driver which will serve both Ethernet and InfiniBand
>>>> drivers.
>>>> hbl_cn is the layer which is used by the satellite drivers for many shared
>>>> operations that are needed by both EN and IB subsystems like QPs, CQs etc.
>>>> The CN driver is initialized via auxiliary bus by the habanalabs driver.
>>>>
>>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
>>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
>>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
>>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
>>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
>>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
>>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
>>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
>>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
>>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
>>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
>>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
>>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
>>>> ---
>>>> .../device_drivers/ethernet/index.rst | 1 +
>>>> .../device_drivers/ethernet/intel/hbl.rst | 82 +
>>>> MAINTAINERS | 11 +
>>>> drivers/net/ethernet/intel/Kconfig | 20 +
>>>> drivers/net/ethernet/intel/Makefile | 1 +
>>>> drivers/net/ethernet/intel/hbl_cn/Makefile | 9 +
>>>> .../net/ethernet/intel/hbl_cn/common/Makefile | 3 +
>>>> .../net/ethernet/intel/hbl_cn/common/hbl_cn.c | 5954 +++++++++++++++++
>>>> .../net/ethernet/intel/hbl_cn/common/hbl_cn.h | 1627 +++++
>>>> .../ethernet/intel/hbl_cn/common/hbl_cn_drv.c | 220 +
>>>> .../intel/hbl_cn/common/hbl_cn_memory.c | 40 +
>>>> .../ethernet/intel/hbl_cn/common/hbl_cn_phy.c | 33 +
>>>> .../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 13 +
>>>> include/linux/habanalabs/cpucp_if.h | 125 +-
>>>> include/linux/habanalabs/hl_boot_if.h | 9 +-
>>>> include/linux/net/intel/cn.h | 474 ++
>>>> include/linux/net/intel/cn_aux.h | 298 +
>>>> include/linux/net/intel/cni.h | 636 ++
>>>> 18 files changed, 9545 insertions(+), 11 deletions(-)
>>>
>>> this is a very big patch, it asks for a split; what's worse, it's
>>> proportional to the size of this series:
>>> 146 files changed, 148514 insertions(+), 70 deletions(-)
>>> which is just too big
>>>
>>> [...]
>>>
>>
>> Yeah, well I'm limited to 15 patches per patch set according to the kernel
>> doc so I had to have this big patch.
>> Our changes are contained in 4 different drivers and all of the changes
>> should be merged together so the HW will be operational.
>> Hence I had to squeeze some code to a big patch.
>
> Submit your code in multiple steps. One driver at a time.
>
> Thanks
I can push each driver at a time but it is missing the big context. Every
single driver is useless without the others (or at least a subset of
them).
But I'll do that anyway so it will be possible to review.
Thanks.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver
2024-06-13 8:21 ` [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver Omer Shpigelman
2024-06-13 13:01 ` Przemek Kitszel
@ 2024-06-15 0:05 ` Stephen Hemminger
2024-06-17 8:14 ` Omer Shpigelman
2024-06-17 14:05 ` Markus Elfring
2 siblings, 1 reply; 108+ messages in thread
From: Stephen Hemminger @ 2024-06-15 0:05 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel, linux-rdma, netdev, dri-devel, ogabbay, zyehudai
> +#define HBL_AUX2NIC(aux_dev) \
> + ({ \
> + struct hbl_aux_dev *__aux_dev = (aux_dev); \
> + ((__aux_dev)->type == HBL_AUX_DEV_ETH) ? \
> + container_of(__aux_dev, struct hbl_cn_device, en_aux_dev) : \
> + container_of(__aux_dev, struct hbl_cn_device, ib_aux_dev); \
> + })
> +
> +#define RAND_STAT_CNT(cnt) \
> + do { \
> + u32 __cnt = get_random_u32(); \
> + (cnt) = __cnt; \
> + dev_info(hdev->dev, "port %d, %s: %u\n", port, #cnt, __cnt); \
> + } while (0)
> +
> +struct hbl_cn_stat hbl_cn_mac_fec_stats[] = {
> + {"correctable_errors", 0x2, 0x3},
> + {"uncorrectable_errors", 0x4, 0x5}
> +};
> +
These tables should be marked const?
> +struct hbl_cn_stat hbl_cn_mac_stats_rx[] = {
> + {"Octets", 0x0},
> + {"OctetsReceivedOK", 0x4},
> + {"aAlignmentErrors", 0x8},
> + {"aPAUSEMACCtrlFramesReceived", 0xC},
> + {"aFrameTooLongErrors", 0x10},
> + {"aInRangeLengthErrors", 0x14},
> + {"aFramesReceivedOK", 0x18},
> + {"aFrameCheckSequenceErrors", 0x1C},
> + {"VLANReceivedOK", 0x20},
> + {"ifInErrors", 0x24},
> + {"ifInUcastPkts", 0x28},
> + {"ifInMulticastPkts", 0x2C},
> + {"ifInBroadcastPkts", 0x30},
> + {"DropEvents", 0x34},
> + {"Pkts", 0x38},
> + {"UndersizePkts", 0x3C},
> + {"Pkts64Octets", 0x40},
> + {"Pkts65to127Octets", 0x44},
> + {"Pkts128to255Octets", 0x48},
> + {"Pkts256to511Octets", 0x4C},
> + {"Pkts512to1023Octets", 0x50},
> + {"Pkts1024to1518Octets", 0x54},
> + {"Pkts1519toMaxOctets", 0x58},
> + {"OversizePkts", 0x5C},
> + {"Jabbers", 0x60},
> + {"Fragments", 0x64},
> + {"aCBFCPAUSERx0", 0x68},
> + {"aCBFCPAUSERx1", 0x6C},
> + {"aCBFCPAUSERx2", 0x70},
> + {"aCBFCPAUSERx3", 0x74},
> + {"aCBFCPAUSERx4", 0x78},
> + {"aCBFCPAUSERx5", 0x7C},
> + {"aCBFCPAUSERx6", 0x80},
> + {"aCBFCPAUSERx7", 0x84},
> + {"aMACControlFramesReceived", 0x88}
> +};
> +
> +struct hbl_cn_stat hbl_cn_mac_stats_tx[] = {
> + {"Octets", 0x0},
> + {"OctetsTransmittedOK", 0x4},
> + {"aPAUSEMACCtrlFramesTransmitted", 0x8},
> + {"aFramesTransmittedOK", 0xC},
> + {"VLANTransmittedOK", 0x10},
> + {"ifOutErrors", 0x14},
> + {"ifOutUcastPkts", 0x18},
> + {"ifOutMulticastPkts", 0x1C},
> + {"ifOutBroadcastPkts", 0x20},
> + {"Pkts64Octets", 0x24},
> + {"Pkts65to127Octets", 0x28},
> + {"Pkts128to255Octets", 0x2C},
> + {"Pkts256to511Octets", 0x30},
> + {"Pkts512to1023Octets", 0x34},
> + {"Pkts1024to1518Octets", 0x38},
> + {"Pkts1519toMaxOctets", 0x3C},
> + {"aCBFCPAUSETx0", 0x40},
> + {"aCBFCPAUSETx1", 0x44},
> + {"aCBFCPAUSETx2", 0x48},
> + {"aCBFCPAUSETx3", 0x4C},
> + {"aCBFCPAUSETx4", 0x50},
> + {"aCBFCPAUSETx5", 0x54},
> + {"aCBFCPAUSETx6", 0x58},
> + {"aCBFCPAUSETx7", 0x5C},
> + {"aMACControlFramesTx", 0x60},
> + {"Pkts", 0x64}
> +};
> +
> +static const char pcs_counters_str[][ETH_GSTRING_LEN] = {
> + {"pcs_local_faults"},
> + {"pcs_remote_faults"},
> + {"pcs_remote_fault_reconfig"},
> + {"pcs_link_restores"},
> + {"pcs_link_toggles"},
> +};
> +
> +static size_t pcs_counters_str_len = ARRAY_SIZE(pcs_counters_str);
> +size_t hbl_cn_mac_fec_stats_len = ARRAY_SIZE(hbl_cn_mac_fec_stats);
> +size_t hbl_cn_mac_stats_rx_len = ARRAY_SIZE(hbl_cn_mac_stats_rx);
> +size_t hbl_cn_mac_stats_tx_len = ARRAY_SIZE(hbl_cn_mac_stats_tx);
> +
> +static void qps_stop(struct hbl_cn_device *hdev);
> +static void qp_destroy_work(struct work_struct *work);
> +static int __user_wq_arr_unset(struct hbl_cn_ctx *ctx, struct hbl_cn_port *cn_port, u32 type);
> +static void user_cq_destroy(struct kref *kref);
> +static void set_app_params_clear(struct hbl_cn_device *hdev);
> +static int hbl_cn_ib_cmd_ctrl(struct hbl_aux_dev *aux_dev, void *cn_ib_ctx, u32 op, void *input,
> + void *output);
> +static int hbl_cn_ib_query_mem_handle(struct hbl_aux_dev *ib_aux_dev, u64 mem_handle,
> + struct hbl_ib_mem_info *info);
> +
> +static void hbl_cn_reset_stats_counters_port(struct hbl_cn_device *hdev, u32 port);
> +static void hbl_cn_late_init(struct hbl_cn_device *hdev);
> +static void hbl_cn_late_fini(struct hbl_cn_device *hdev);
> +static int hbl_cn_sw_init(struct hbl_cn_device *hdev);
> +static void hbl_cn_sw_fini(struct hbl_cn_device *hdev);
> +static void hbl_cn_spmu_init(struct hbl_cn_port *cn_port, bool full);
> +static int hbl_cn_cmd_port_check(struct hbl_cn_device *hdev, u32 port, u32 flags);
> +static void hbl_cn_qps_stop(struct hbl_cn_port *cn_port);
Can you reorder code so forward declarations are not required?
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver
2024-06-15 0:05 ` Stephen Hemminger
@ 2024-06-17 8:14 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-17 8:14 UTC (permalink / raw)
To: Stephen Hemminger
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/15/24 03:05, Stephen Hemminger wrote:
> [You don't often get email from stephen@networkplumber.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
>> +#define HBL_AUX2NIC(aux_dev) \
>> + ({ \
>> + struct hbl_aux_dev *__aux_dev = (aux_dev); \
>> + ((__aux_dev)->type == HBL_AUX_DEV_ETH) ? \
>> + container_of(__aux_dev, struct hbl_cn_device, en_aux_dev) : \
>> + container_of(__aux_dev, struct hbl_cn_device, ib_aux_dev); \
>> + })
>> +
>> +#define RAND_STAT_CNT(cnt) \
>> + do { \
>> + u32 __cnt = get_random_u32(); \
>> + (cnt) = __cnt; \
>> + dev_info(hdev->dev, "port %d, %s: %u\n", port, #cnt, __cnt); \
>> + } while (0)
>> +
>> +struct hbl_cn_stat hbl_cn_mac_fec_stats[] = {
>> + {"correctable_errors", 0x2, 0x3},
>> + {"uncorrectable_errors", 0x4, 0x5}
>> +};
>> +
>
> These tables should be marked const?
>
I'll add const to them.
>> +struct hbl_cn_stat hbl_cn_mac_stats_rx[] = {
>> + {"Octets", 0x0},
>> + {"OctetsReceivedOK", 0x4},
>> + {"aAlignmentErrors", 0x8},
>> + {"aPAUSEMACCtrlFramesReceived", 0xC},
>> + {"aFrameTooLongErrors", 0x10},
>> + {"aInRangeLengthErrors", 0x14},
>> + {"aFramesReceivedOK", 0x18},
>> + {"aFrameCheckSequenceErrors", 0x1C},
>> + {"VLANReceivedOK", 0x20},
>> + {"ifInErrors", 0x24},
>> + {"ifInUcastPkts", 0x28},
>> + {"ifInMulticastPkts", 0x2C},
>> + {"ifInBroadcastPkts", 0x30},
>> + {"DropEvents", 0x34},
>> + {"Pkts", 0x38},
>> + {"UndersizePkts", 0x3C},
>> + {"Pkts64Octets", 0x40},
>> + {"Pkts65to127Octets", 0x44},
>> + {"Pkts128to255Octets", 0x48},
>> + {"Pkts256to511Octets", 0x4C},
>> + {"Pkts512to1023Octets", 0x50},
>> + {"Pkts1024to1518Octets", 0x54},
>> + {"Pkts1519toMaxOctets", 0x58},
>> + {"OversizePkts", 0x5C},
>> + {"Jabbers", 0x60},
>> + {"Fragments", 0x64},
>> + {"aCBFCPAUSERx0", 0x68},
>> + {"aCBFCPAUSERx1", 0x6C},
>> + {"aCBFCPAUSERx2", 0x70},
>> + {"aCBFCPAUSERx3", 0x74},
>> + {"aCBFCPAUSERx4", 0x78},
>> + {"aCBFCPAUSERx5", 0x7C},
>> + {"aCBFCPAUSERx6", 0x80},
>> + {"aCBFCPAUSERx7", 0x84},
>> + {"aMACControlFramesReceived", 0x88}
>> +};
>> +
>> +struct hbl_cn_stat hbl_cn_mac_stats_tx[] = {
>> + {"Octets", 0x0},
>> + {"OctetsTransmittedOK", 0x4},
>> + {"aPAUSEMACCtrlFramesTransmitted", 0x8},
>> + {"aFramesTransmittedOK", 0xC},
>> + {"VLANTransmittedOK", 0x10},
>> + {"ifOutErrors", 0x14},
>> + {"ifOutUcastPkts", 0x18},
>> + {"ifOutMulticastPkts", 0x1C},
>> + {"ifOutBroadcastPkts", 0x20},
>> + {"Pkts64Octets", 0x24},
>> + {"Pkts65to127Octets", 0x28},
>> + {"Pkts128to255Octets", 0x2C},
>> + {"Pkts256to511Octets", 0x30},
>> + {"Pkts512to1023Octets", 0x34},
>> + {"Pkts1024to1518Octets", 0x38},
>> + {"Pkts1519toMaxOctets", 0x3C},
>> + {"aCBFCPAUSETx0", 0x40},
>> + {"aCBFCPAUSETx1", 0x44},
>> + {"aCBFCPAUSETx2", 0x48},
>> + {"aCBFCPAUSETx3", 0x4C},
>> + {"aCBFCPAUSETx4", 0x50},
>> + {"aCBFCPAUSETx5", 0x54},
>> + {"aCBFCPAUSETx6", 0x58},
>> + {"aCBFCPAUSETx7", 0x5C},
>> + {"aMACControlFramesTx", 0x60},
>> + {"Pkts", 0x64}
>> +};
>> +
>> +static const char pcs_counters_str[][ETH_GSTRING_LEN] = {
>> + {"pcs_local_faults"},
>> + {"pcs_remote_faults"},
>> + {"pcs_remote_fault_reconfig"},
>> + {"pcs_link_restores"},
>> + {"pcs_link_toggles"},
>> +};
>> +
>> +static size_t pcs_counters_str_len = ARRAY_SIZE(pcs_counters_str);
>> +size_t hbl_cn_mac_fec_stats_len = ARRAY_SIZE(hbl_cn_mac_fec_stats);
>> +size_t hbl_cn_mac_stats_rx_len = ARRAY_SIZE(hbl_cn_mac_stats_rx);
>> +size_t hbl_cn_mac_stats_tx_len = ARRAY_SIZE(hbl_cn_mac_stats_tx);
>> +
>> +static void qps_stop(struct hbl_cn_device *hdev);
>> +static void qp_destroy_work(struct work_struct *work);
>> +static int __user_wq_arr_unset(struct hbl_cn_ctx *ctx, struct hbl_cn_port *cn_port, u32 type);
>> +static void user_cq_destroy(struct kref *kref);
>> +static void set_app_params_clear(struct hbl_cn_device *hdev);
>> +static int hbl_cn_ib_cmd_ctrl(struct hbl_aux_dev *aux_dev, void *cn_ib_ctx, u32 op, void *input,
>> + void *output);
>> +static int hbl_cn_ib_query_mem_handle(struct hbl_aux_dev *ib_aux_dev, u64 mem_handle,
>> + struct hbl_ib_mem_info *info);
>> +
>> +static void hbl_cn_reset_stats_counters_port(struct hbl_cn_device *hdev, u32 port);
>> +static void hbl_cn_late_init(struct hbl_cn_device *hdev);
>> +static void hbl_cn_late_fini(struct hbl_cn_device *hdev);
>> +static int hbl_cn_sw_init(struct hbl_cn_device *hdev);
>> +static void hbl_cn_sw_fini(struct hbl_cn_device *hdev);
>> +static void hbl_cn_spmu_init(struct hbl_cn_port *cn_port, bool full);
>> +static int hbl_cn_cmd_port_check(struct hbl_cn_device *hdev, u32 port, u32 flags);
>> +static void hbl_cn_qps_stop(struct hbl_cn_port *cn_port);
>
> Can you reorder code so forward declarations are not required?
I'll try to reorder to get rid of the forward declarations.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver
2024-06-13 8:21 ` [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver Omer Shpigelman
2024-06-13 13:01 ` Przemek Kitszel
2024-06-15 0:05 ` Stephen Hemminger
@ 2024-06-17 14:05 ` Markus Elfring
2024-06-17 15:02 ` Andrew Lunn
2 siblings, 1 reply; 108+ messages in thread
From: Markus Elfring @ 2024-06-17 14:05 UTC (permalink / raw)
To: Abhilash K V, Andrey Agranovich, Bharat Jauhari, David Meriin,
Omer Shpigelman, Sagiv Ozeri, Zvika Yehudai, netdev, linux-rdma,
dri-devel
Cc: LKML
…
> +++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
> @@ -0,0 +1,5954 @@
…
> +int hbl_cn_read_spmu_counters(struct hbl_cn_port *cn_port, u64 out_data[], u32 *num_out_data)
> +{
…
> + mutex_lock(&cn_port->cnt_lock);
> + rc = port_funcs->spmu_sample(cn_port, *num_out_data, out_data);
> + mutex_unlock(&cn_port->cnt_lock);
> +
> + return rc;
> +}
…
Would you become interested to apply a statement like “guard(mutex)(&cn_port->cnt_lock);”?
https://elixir.bootlin.com/linux/v6.10-rc4/source/include/linux/mutex.h#L196
Regards,
Markus
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver
2024-06-17 14:05 ` Markus Elfring
@ 2024-06-17 15:02 ` Andrew Lunn
2024-06-18 7:51 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Andrew Lunn @ 2024-06-17 15:02 UTC (permalink / raw)
To: Markus Elfring
Cc: Abhilash K V, Andrey Agranovich, Bharat Jauhari, David Meriin,
Omer Shpigelman, Sagiv Ozeri, Zvika Yehudai, netdev, linux-rdma,
dri-devel, LKML
On Mon, Jun 17, 2024 at 04:05:57PM +0200, Markus Elfring wrote:
> …
> > +++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
> > @@ -0,0 +1,5954 @@
> …
> > +int hbl_cn_read_spmu_counters(struct hbl_cn_port *cn_port, u64 out_data[], u32 *num_out_data)
> > +{
> …
> > + mutex_lock(&cn_port->cnt_lock);
> > + rc = port_funcs->spmu_sample(cn_port, *num_out_data, out_data);
> > + mutex_unlock(&cn_port->cnt_lock);
> > +
> > + return rc;
> > +}
> …
>
> Would you become interested to apply a statement like “guard(mutex)(&cn_port->cnt_lock);”?
> https://elixir.bootlin.com/linux/v6.10-rc4/source/include/linux/mutex.h#L196
Hi Markus
We decided for netdev that guard() was too magical, at least for the
moment. Lets wait a few years to see how it pans out. scoped_guard()
is however O.K.
Andrew
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver
2024-06-17 15:02 ` Andrew Lunn
@ 2024-06-18 7:51 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-18 7:51 UTC (permalink / raw)
To: Andrew Lunn, Markus Elfring
Cc: Abhilash K V, Andrey Agranovich, Bharat Jauhari, David Meriin,
Sagiv Ozeri, Zvika Yehudai, netdev@vger.kernel.org,
linux-rdma@vger.kernel.org, dri-devel@lists.freedesktop.org, LKML
On 6/17/24 18:02, Andrew Lunn wrote:
> [Some people who received this message don't often get email from andrew@lunn.ch. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On Mon, Jun 17, 2024 at 04:05:57PM +0200, Markus Elfring wrote:
>> …
>>> +++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
>>> @@ -0,0 +1,5954 @@
>> …
>>> +int hbl_cn_read_spmu_counters(struct hbl_cn_port *cn_port, u64 out_data[], u32 *num_out_data)
>>> +{
>> …
>>> + mutex_lock(&cn_port->cnt_lock);
>>> + rc = port_funcs->spmu_sample(cn_port, *num_out_data, out_data);
>>> + mutex_unlock(&cn_port->cnt_lock);
>>> +
>>> + return rc;
>>> +}
>> …
>>
>> Would you become interested to apply a statement like “guard(mutex)(&cn_port->cnt_lock);”?
>> https://elixir.bootlin.com/linux/v6.10-rc4/source/include/linux/mutex.h#L196
>
> Hi Markus
>
> We decided for netdev that guard() was too magical, at least for the
> moment. Lets wait a few years to see how it pans out. scoped_guard()
> is however O.K.
>
> Andrew
Thanks for the reference.
I don't see any other Ethernet driver that uses these so let me first
handle the necessary changes and later on I'll check optional
enhancements.
But yeah, we are always open to improve the code.
^ permalink raw reply [flat|nested] 108+ messages in thread
* [PATCH 02/15] net: hbl_cn: memory manager component
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
2024-06-13 8:21 ` [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver Omer Shpigelman
@ 2024-06-13 8:21 ` Omer Shpigelman
2024-06-13 8:21 ` [PATCH 03/15] net: hbl_cn: physical layer support Omer Shpigelman
` (14 subsequent siblings)
16 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:21 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
Add a common memory manager which handles allocation and mapping.
It manages physical/virtual memory on host/device.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
.../intel/hbl_cn/common/hbl_cn_memory.c | 325 +++++++++++++++++-
1 file changed, 322 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_memory.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_memory.c
index 93c97fad6a20..878ecba66aa3 100644
--- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_memory.c
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_memory.c
@@ -4,37 +4,356 @@
* All Rights Reserved.
*/
+#include <linux/vmalloc.h>
#include "hbl_cn.h"
-int hbl_cn_mem_alloc(struct hbl_cn_ctx *ctx, struct hbl_cn_mem_data *mem_data)
+static int hbl_cn_map_vmalloc_range(struct hbl_cn_ctx *ctx, u64 vmalloc_va, u64 device_va,
+ u64 size)
+{
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = ctx->hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ return aux_ops->vm_dev_mmu_map(aux_dev, ctx->driver_vm_info.vm_handle, HBL_CN_MEM_TYPE_HOST,
+ vmalloc_va, device_va, size);
+}
+
+static void hbl_cn_unmap_vmalloc_range(struct hbl_cn_ctx *ctx, u64 device_va, u64 size)
+{
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = ctx->hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ aux_ops->vm_dev_mmu_unmap(aux_dev, ctx->driver_vm_info.vm_handle, device_va, size);
+}
+
+static int alloc_mem(struct hbl_cn_mem_buf *buf, gfp_t gfp, struct hbl_cn_mem_data *mem_data)
+{
+ u64 device_addr, size = mem_data->size;
+ struct hbl_cn_ctx *ctx = buf->ctx;
+ u32 mem_id = mem_data->mem_id;
+ struct hbl_cn_device *hdev;
+ void *p = NULL;
+
+ hdev = ctx->hdev;
+
+ switch (mem_id) {
+ case HBL_CN_DRV_MEM_HOST_DMA_COHERENT:
+ if (get_order(size) > MAX_PAGE_ORDER) {
+ dev_err(hdev->dev, "memory size 0x%llx must be less than 0x%lx\n", size,
+ 1UL << (PAGE_SHIFT + MAX_PAGE_ORDER));
+ return -ENOMEM;
+ }
+
+ p = hbl_cn_dma_alloc_coherent(hdev, size, &buf->bus_address, GFP_USER | __GFP_ZERO);
+ if (!p) {
+ dev_err(hdev->dev,
+ "failed to allocate 0x%llx of dma memory for the NIC\n", size);
+ return -ENOMEM;
+ }
+
+ break;
+ case HBL_CN_DRV_MEM_HOST_VIRTUAL:
+ p = vmalloc_user(size);
+ if (!p) {
+ dev_err(hdev->dev, "failed to allocate vmalloc memory, size 0x%llx\n",
+ size);
+ return -ENOMEM;
+ }
+
+ break;
+ case HBL_CN_DRV_MEM_HOST_MAP_ONLY:
+ p = mem_data->in.host_map_data.kernel_address;
+ buf->bus_address = mem_data->in.host_map_data.bus_address;
+ break;
+ case HBL_CN_DRV_MEM_DEVICE:
+ if (!hdev->wq_arrays_pool_enable) {
+ dev_err(hdev->dev, "No WQ arrays pool support for device memory\n");
+ return -EOPNOTSUPP;
+ }
+
+ device_addr = (u64)gen_pool_alloc(hdev->wq_arrays_pool, size);
+ if (!device_addr) {
+ dev_err(hdev->dev, "Failed to allocate device memory, size 0x%llx\n", size);
+ return -ENOMEM;
+ }
+
+ buf->device_addr = device_addr;
+ break;
+ default:
+ dev_err(hdev->dev, "Invalid mem_id %d\n", mem_id);
+ return -EINVAL;
+ }
+
+ buf->kernel_address = p;
+ buf->mappable_size = size;
+
+ return 0;
+}
+
+static int map_mem(struct hbl_cn_mem_buf *buf, struct hbl_cn_mem_data *mem_data)
+{
+ struct hbl_cn_ctx *ctx = buf->ctx;
+ struct hbl_cn_device *hdev;
+ int rc;
+
+ hdev = ctx->hdev;
+
+ if (mem_data->mem_id == HBL_CN_DRV_MEM_HOST_DMA_COHERENT) {
+ dev_err(hdev->dev, "Mapping DMA coherent host memory is not yet supported\n");
+ return -EPERM;
+ }
+
+ rc = hbl_cn_map_vmalloc_range(ctx, (u64)buf->kernel_address, mem_data->device_va,
+ buf->mappable_size);
+ if (rc)
+ return rc;
+
+ buf->device_va = mem_data->device_va;
+
+ return 0;
+}
+
+static void mem_do_release(struct hbl_cn_device *hdev, struct hbl_cn_mem_buf *buf)
+{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+
+ if (buf->mem_id == HBL_CN_DRV_MEM_HOST_DMA_COHERENT)
+ asic_funcs->dma_free_coherent(hdev, buf->mappable_size, buf->kernel_address,
+ buf->bus_address);
+ else if (buf->mem_id == HBL_CN_DRV_MEM_HOST_VIRTUAL)
+ vfree(buf->kernel_address);
+ else if (buf->mem_id == HBL_CN_DRV_MEM_DEVICE)
+ gen_pool_free(hdev->wq_arrays_pool, buf->device_addr, buf->mappable_size);
+}
+
+static int __cn_mem_buf_alloc(struct hbl_cn_mem_buf *buf, gfp_t gfp,
+ struct hbl_cn_mem_data *mem_data)
+{
+ struct hbl_cn_ctx *ctx = buf->ctx;
+ struct hbl_cn_device *hdev;
+ int rc;
+
+ hdev = ctx->hdev;
+
+ if (mem_data->mem_id != HBL_CN_DRV_MEM_DEVICE)
+ mem_data->size = PAGE_ALIGN(mem_data->size);
+
+ rc = alloc_mem(buf, gfp, mem_data);
+ if (rc)
+ return rc;
+
+ if (mem_data->device_va) {
+ mem_data->device_va = PAGE_ALIGN(mem_data->device_va);
+ rc = map_mem(buf, mem_data);
+ if (rc)
+ goto release_mem;
+ }
+
+ return 0;
+
+release_mem:
+ mem_do_release(hdev, buf);
+ return rc;
+}
+
+static struct hbl_cn_mem_buf *cn_mem_buf_alloc(struct hbl_cn_ctx *ctx, gfp_t gfp,
+ struct hbl_cn_mem_data *mem_data)
+{
+ struct xa_limit id_limit = XA_LIMIT(1, INT_MAX);
+ struct hbl_cn_device *hdev = ctx->hdev;
+ struct hbl_cn_mem_buf *buf;
+ int rc;
+ u32 id;
+
+ buf = kzalloc(sizeof(*buf), gfp);
+ if (!buf)
+ return NULL;
+
+ rc = xa_alloc(&hdev->mem_ids, &id, buf, id_limit, GFP_ATOMIC);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to allocate xarray for a new buffer, rc=%d\n", rc);
+ goto free_buf;
+ }
+
+ buf->ctx = ctx;
+ buf->mem_id = mem_data->mem_id;
+
+ buf->handle = (((u64)id | hdev->mmap_type_flag) << PAGE_SHIFT);
+ kref_init(&buf->refcount);
+
+ rc = __cn_mem_buf_alloc(buf, gfp, mem_data);
+ if (rc)
+ goto remove_xa;
+
+ return buf;
+
+remove_xa:
+ xa_erase(&hdev->mem_ids, lower_32_bits(buf->handle >> PAGE_SHIFT));
+free_buf:
+ kfree(buf);
+ return NULL;
+}
+
+static int cn_mem_alloc(struct hbl_cn_ctx *ctx, struct hbl_cn_mem_data *mem_data)
{
+ struct hbl_cn_mem_buf *buf;
+
+ buf = cn_mem_buf_alloc(ctx, GFP_KERNEL, mem_data);
+ if (!buf)
+ return -ENOMEM;
+
+ mem_data->handle = buf->handle;
+
+ if (mem_data->mem_id == HBL_CN_DRV_MEM_HOST_DMA_COHERENT)
+ mem_data->addr = (u64)buf->bus_address;
+ else if (mem_data->mem_id == HBL_CN_DRV_MEM_HOST_VIRTUAL)
+ mem_data->addr = (u64)buf->kernel_address;
+ else if (mem_data->mem_id == HBL_CN_DRV_MEM_DEVICE)
+ mem_data->addr = (u64)buf->device_addr;
+
return 0;
}
+int hbl_cn_mem_alloc(struct hbl_cn_ctx *ctx, struct hbl_cn_mem_data *mem_data)
+{
+ struct hbl_cn_device *hdev = ctx->hdev;
+ int rc;
+
+ switch (mem_data->mem_id) {
+ case HBL_CN_DRV_MEM_HOST_DMA_COHERENT:
+ case HBL_CN_DRV_MEM_HOST_VIRTUAL:
+ case HBL_CN_DRV_MEM_HOST_MAP_ONLY:
+ case HBL_CN_DRV_MEM_DEVICE:
+ rc = cn_mem_alloc(ctx, mem_data);
+ break;
+ default:
+ dev_dbg(hdev->dev, "Invalid mem_id %d\n", mem_data->mem_id);
+ rc = -EINVAL;
+ break;
+ }
+
+ return rc;
+}
+
+static void cn_mem_buf_destroy(struct hbl_cn_mem_buf *buf)
+{
+ if (buf->device_va)
+ hbl_cn_unmap_vmalloc_range(buf->ctx, buf->device_va, buf->mappable_size);
+
+ mem_do_release(buf->ctx->hdev, buf);
+
+ kfree(buf);
+}
+
int hbl_cn_mem_destroy(struct hbl_cn_device *hdev, u64 handle)
{
+ struct hbl_cn_mem_buf *buf;
+ int rc;
+
+ buf = hbl_cn_mem_buf_get(hdev, handle);
+ if (!buf) {
+ dev_dbg(hdev->dev, "Memory destroy failed, no match for handle 0x%llx\n", handle);
+ return -EINVAL;
+ }
+
+ rc = atomic_cmpxchg(&buf->is_destroyed, 0, 1);
+ hbl_cn_mem_buf_put(buf);
+ if (rc) {
+ dev_dbg(hdev->dev, "Memory destroy failed, handle 0x%llx was already destroyed\n",
+ handle);
+ return -EINVAL;
+ }
+
+ rc = hbl_cn_mem_buf_put_handle(hdev, handle);
+ if (rc < 0)
+ return rc;
+
+ if (rc == 0)
+ dev_dbg(hdev->dev, "Handle 0x%llx is destroyed while still in use\n", handle);
+
return 0;
}
+static void cn_mem_buf_release(struct kref *kref)
+{
+ struct hbl_cn_mem_buf *buf = container_of(kref, struct hbl_cn_mem_buf, refcount);
+ struct hbl_cn_device *hdev = buf->ctx->hdev;
+
+ xa_erase(&hdev->mem_ids, lower_32_bits(buf->handle >> PAGE_SHIFT));
+
+ cn_mem_buf_destroy(buf);
+}
+
struct hbl_cn_mem_buf *hbl_cn_mem_buf_get(struct hbl_cn_device *hdev, u64 handle)
{
- return NULL;
+ struct hbl_cn_mem_buf *buf;
+
+ xa_lock(&hdev->mem_ids);
+ buf = xa_load(&hdev->mem_ids, lower_32_bits(handle >> PAGE_SHIFT));
+ if (!buf) {
+ xa_unlock(&hdev->mem_ids);
+ dev_dbg(hdev->dev, "Buff get failed, no match to handle %#llx\n", handle);
+ return NULL;
+ }
+
+ kref_get(&buf->refcount);
+ xa_unlock(&hdev->mem_ids);
+
+ return buf;
}
int hbl_cn_mem_buf_put(struct hbl_cn_mem_buf *buf)
{
- return 0;
+ return kref_put(&buf->refcount, cn_mem_buf_release);
+}
+
+static void cn_mem_buf_remove_xa_locked(struct kref *kref)
+{
+ struct hbl_cn_mem_buf *buf = container_of(kref, struct hbl_cn_mem_buf, refcount);
+
+ __xa_erase(&buf->ctx->hdev->mem_ids, lower_32_bits(buf->handle >> PAGE_SHIFT));
}
int hbl_cn_mem_buf_put_handle(struct hbl_cn_device *hdev, u64 handle)
{
+ struct hbl_cn_mem_buf *buf;
+
+ xa_lock(&hdev->mem_ids);
+ buf = xa_load(&hdev->mem_ids, lower_32_bits(handle >> PAGE_SHIFT));
+ if (!buf) {
+ xa_unlock(&hdev->mem_ids);
+ dev_dbg(hdev->dev, "Buff put failed, no match to handle %#llx\n", handle);
+ return -EINVAL;
+ }
+
+ if (kref_put(&buf->refcount, cn_mem_buf_remove_xa_locked)) {
+ xa_unlock(&hdev->mem_ids);
+ cn_mem_buf_destroy(buf);
+ return 1;
+ }
+
+ xa_unlock(&hdev->mem_ids);
return 0;
}
void hbl_cn_mem_init(struct hbl_cn_device *hdev)
{
+ xa_init_flags(&hdev->mem_ids, XA_FLAGS_ALLOC);
}
void hbl_cn_mem_fini(struct hbl_cn_device *hdev)
{
+ struct xarray *mem_ids;
+
+ mem_ids = &hdev->mem_ids;
+
+ if (!xa_empty(mem_ids))
+ dev_crit(hdev->dev, "memory manager is destroyed while not empty!\n");
+
+ xa_destroy(mem_ids);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* [PATCH 03/15] net: hbl_cn: physical layer support
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
2024-06-13 8:21 ` [PATCH 01/15] net: hbl_cn: add habanalabs Core Network driver Omer Shpigelman
2024-06-13 8:21 ` [PATCH 02/15] net: hbl_cn: memory manager component Omer Shpigelman
@ 2024-06-13 8:21 ` Omer Shpigelman
2024-06-13 8:21 ` [PATCH 04/15] net: hbl_cn: QP state machine Omer Shpigelman
` (13 subsequent siblings)
16 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:21 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
Add a common physical (PHY) layer initialization and link notification.
An notification is sent on every link up/down change.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
.../ethernet/intel/hbl_cn/common/hbl_cn_phy.c | 201 ++++++++++++++++++
1 file changed, 201 insertions(+)
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_phy.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_phy.c
index 0d07cd78221d..6753d54ae2b0 100644
--- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_phy.c
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_phy.c
@@ -4,30 +4,231 @@
* All Rights Reserved.
*/
+#include <linux/firmware.h>
#include "hbl_cn.h"
+static void port_reset_state(struct hbl_cn_port *cn_port)
+{
+ cn_port->pcs_link = false;
+ cn_port->eq_pcs_link = false;
+ cn_port->auto_neg_resolved = false;
+ cn_port->auto_neg_skipped = false;
+ cn_port->phy_fw_tuned = false;
+ cn_port->retry_cnt = 0;
+ cn_port->pcs_remote_fault_seq_cnt = 0;
+ cn_port->pcs_link_restore_cnt = 0;
+ cn_port->correctable_errors_cnt = 0;
+ cn_port->uncorrectable_errors_cnt = 0;
+}
+
+static u32 get_data_rate(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port, speed, data_rate;
+
+ port = cn_port->port;
+ speed = cn_port->speed;
+
+ switch (speed) {
+ case SPEED_10000:
+ data_rate = NIC_DR_10;
+ break;
+ case SPEED_25000:
+ data_rate = NIC_DR_25;
+ break;
+ case SPEED_50000:
+ data_rate = NIC_DR_50;
+ break;
+ case SPEED_100000:
+ data_rate = NIC_DR_50;
+ break;
+ case SPEED_200000:
+ data_rate = NIC_DR_100;
+ break;
+ case SPEED_400000:
+ data_rate = NIC_DR_100;
+ break;
+ default:
+ data_rate = NIC_DR_50;
+ dev_err(hdev->dev, "unknown port %d speed, continue with 50 GHz\n", port);
+ break;
+ }
+
+ dev_dbg(hdev->dev, "port %d, speed %d data rate %d\n", port, speed, data_rate);
+
+ return data_rate;
+}
+
void hbl_cn_phy_set_port_status(struct hbl_cn_port *cn_port, bool up)
{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port = cn_port->port;
+ bool is_ibdev;
+ int rc;
+
+ aux_dev = &hdev->en_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ port_funcs = hdev->asic_funcs->port_funcs;
+ is_ibdev = hbl_cn_is_ibdev(hdev);
+
+ port_funcs->set_port_status(cn_port, up);
+
+ if (cn_port->eth_enable) {
+ if (aux_ops->set_port_status)
+ aux_ops->set_port_status(aux_dev, port, up);
+ } else {
+ if (hdev->ctx)
+ dev_info(hdev->dev, "Card %u Port %u: link %s\n",
+ hdev->card_location, port, up ? "up" : "down");
+ else
+ dev_dbg(hdev->dev, "Card %u Port %u: link %s\n",
+ hdev->card_location, port, up ? "up" : "down");
+ }
+
+ /* IB flow. User polls for IB events.
+ * - internal ports: Enqueue link event in EQ dispatcher. IB event would be dispatched in
+ * response.
+ * - external ports: Do not enqueue. hbl IB driver dispatches IB events from netdev
+ * notifier chain handler.
+ * non-IB flow. User polls for EQ events.
+ * - internal ports: Enqueue link event in EQ dispatcher.
+ * - external ports: Enqueue link event in EQ dispatcher.
+ */
+ if (!is_ibdev || !cn_port->eth_enable) {
+ if (hdev->has_eq) {
+ rc = hbl_cn_eq_dispatcher_enqueue_bcast(cn_port, &cn_port->link_eqe);
+ if (rc)
+ dev_dbg_ratelimited(hdev->dev,
+ "Port %d, failed to dispatch link event %s, %d\n",
+ port, up ? "up" : "down", rc);
+ }
+ }
+
+ cn_port->port_toggle_cnt++;
+
+ /* The FEC counters are relevant during the time that link is UP, hence reset them here */
+ if (up) {
+ cn_port->correctable_errors_cnt = 0;
+ cn_port->uncorrectable_errors_cnt = 0;
+ }
+
+ if (hdev->pldm) {
+ dev_dbg(hdev->dev, "%s: port %u\n", __func__, port);
+ msleep(1000);
+ }
}
int hbl_cn_phy_init(struct hbl_cn_port *cn_port)
{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ int rc;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ /* If mac_loopback is enabled on this port, move the port status to UP state */
+ if (cn_port->mac_loopback) {
+ cn_port->pcs_link = true;
+ hbl_cn_phy_set_port_status(cn_port, true);
+ return 0;
+ }
+
+ if (!hdev->phy_config_fw) {
+ /* If EQ is supported, it will take care of setting the port status */
+ if (!hdev->has_eq) {
+ cn_port->pcs_link = true;
+ hbl_cn_phy_set_port_status(cn_port, true);
+ }
+
+ return 0;
+ }
+
+ cn_port->data_rate = get_data_rate(cn_port);
+
+ rc = port_funcs->phy_port_power_up(cn_port);
+ if (rc) {
+ dev_err(hdev->dev, "ASIC specific phy port power-up failed, %d\n", rc);
+ return rc;
+ }
+
+ port_funcs->phy_port_start_stop(cn_port, true);
+
+ queue_delayed_work(cn_port->wq, &cn_port->link_status_work, msecs_to_jiffies(1));
+
return 0;
}
+/* This function does not change the port link status in order to avoid unnecessary netdev actions
+ * and prints. Hence it should be done from outside.
+ */
void hbl_cn_phy_fini(struct hbl_cn_port *cn_port)
{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+
+ /* This is done before the check because we support setting mac loopback for a specific port
+ * and this function might be called when cn_port->mac_loopback is true (during the port
+ * reset after setting mac loopback), but the link status work was scheduled before (when
+ * the port was opened w/o mac loopback).
+ */
+ cancel_delayed_work_sync(&cn_port->link_status_work);
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ if (!hdev->phy_config_fw || cn_port->mac_loopback) {
+ cn_port->pcs_link = false;
+ cn_port->eq_pcs_link = false;
+ return;
+ }
+
+ port_reset_state(cn_port);
+ port_funcs->phy_port_start_stop(cn_port, false);
}
void hbl_cn_phy_port_reconfig(struct hbl_cn_port *cn_port)
{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ port_funcs->phy_port_reconfig(cn_port);
+
+ port_reset_state(cn_port);
}
int hbl_cn_phy_has_binary_fw(struct hbl_cn_device *hdev)
{
+ struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+ const struct firmware *fw;
+ const char *fw_name;
+ int rc;
+
+ fw_name = asic_funcs->get_phy_fw_name();
+
+ rc = request_firmware(&fw, fw_name, hdev->dev);
+ if (rc) {
+ dev_err(hdev->dev, "Firmware file %s is not found!\n", fw_name);
+ return rc;
+ }
+
+ release_firmware(fw);
+
return 0;
}
void hbl_cn_phy_set_fw_polarity(struct hbl_cn_device *hdev)
{
+ struct hbl_cn_cpucp_info *cpucp_info;
+
+ if (hdev->skip_phy_pol_cfg)
+ return;
+
+ cpucp_info = hdev->cpucp_info;
+
+ hdev->pol_tx_mask = cpucp_info->pol_tx_mask[0];
+ hdev->pol_rx_mask = cpucp_info->pol_rx_mask[0];
}
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* [PATCH 04/15] net: hbl_cn: QP state machine
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
` (2 preceding siblings ...)
2024-06-13 8:21 ` [PATCH 03/15] net: hbl_cn: physical layer support Omer Shpigelman
@ 2024-06-13 8:21 ` Omer Shpigelman
2024-06-17 13:18 ` Leon Romanovsky
2024-06-13 8:21 ` [PATCH 05/15] net: hbl_cn: memory trace events Omer Shpigelman
` (12 subsequent siblings)
16 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:21 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
Add a common QP state machine which handles the moving for a QP from one
state to another including performing necessary checks, draining
in-flight transactions, invalidating caches and error reporting.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
.../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 480 +++++++++++++++++-
1 file changed, 479 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
index 9ddc23bf8194..26ebdf448193 100644
--- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
@@ -6,8 +6,486 @@
#include "hbl_cn.h"
+#define OP_RETRY_COUNT 4
+#define OPC_SETTLE_RETRY_COUNT 20
+
+/* The following table represents the (valid) operations that can be performed on
+ * a QP in order to move it from one state to another
+ * For example: a QP in RTR state can be moved to RTS state using the CN_QP_OP_RTR_2RTS
+ * operation.
+ */
+static const enum hbl_cn_qp_state_op qp_valid_state_op[CN_QP_NUM_STATE][CN_QP_NUM_STATE] = {
+ [CN_QP_STATE_RESET] = {
+ [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
+ [CN_QP_STATE_INIT] = CN_QP_OP_RST_2INIT,
+ [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
+ [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
+ },
+ [CN_QP_STATE_INIT] = {
+ [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
+ [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
+ [CN_QP_STATE_INIT] = CN_QP_OP_NOP,
+ [CN_QP_STATE_RTR] = CN_QP_OP_INIT_2RTR,
+ [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
+ [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
+ },
+ [CN_QP_STATE_RTR] = {
+ [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
+ [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
+ [CN_QP_STATE_RTR] = CN_QP_OP_RTR_2RTR,
+ [CN_QP_STATE_RTS] = CN_QP_OP_RTR_2RTS,
+ [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
+ [CN_QP_STATE_QPD] = CN_QP_OP_RTR_2QPD,
+ },
+ [CN_QP_STATE_RTS] = {
+ [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
+ [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
+ [CN_QP_STATE_RTS] = CN_QP_OP_RTS_2RTS,
+ [CN_QP_STATE_SQD] = CN_QP_OP_RTS_2SQD,
+ [CN_QP_STATE_QPD] = CN_QP_OP_RTS_2QPD,
+ [CN_QP_STATE_SQERR] = CN_QP_OP_RTS_2SQERR,
+ },
+ [CN_QP_STATE_SQD] = {
+ [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
+ [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
+ [CN_QP_STATE_SQD] = CN_QP_OP_SQD_2SQD,
+ [CN_QP_STATE_RTS] = CN_QP_OP_SQD_2RTS,
+ [CN_QP_STATE_QPD] = CN_QP_OP_SQD_2QPD,
+ [CN_QP_STATE_SQERR] = CN_QP_OP_SQD_2SQ_ERR,
+ },
+ [CN_QP_STATE_QPD] = {
+ [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
+ [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
+ [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
+ [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
+ [CN_QP_STATE_RTR] = CN_QP_OP_QPD_2RTR,
+ },
+ [CN_QP_STATE_SQERR] = {
+ [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
+ [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
+ [CN_QP_STATE_SQD] = CN_QP_OP_SQ_ERR_2SQD,
+ [CN_QP_STATE_SQERR] = CN_QP_OP_NOP,
+ },
+ [CN_QP_STATE_ERR] = {
+ [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
+ [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
+ }
+};
+
+static char *cn_qp_state_2name(enum hbl_cn_qp_state state)
+{
+ static char *arr[CN_QP_NUM_STATE] = {
+ "Reset",
+ "Init",
+ "RTR",
+ "RTS",
+ "SQD",
+ "QPD",
+ "SQERR",
+ "ERR",
+ };
+
+ return arr[state];
+}
+
+static inline int wait_for_qpc_idle(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp, bool is_req)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_qpc_attr qpc_attr;
+ int i, rc;
+
+ if (!hdev->qp_wait_for_idle)
+ return 0;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ for (i = 0; i < OPC_SETTLE_RETRY_COUNT; i++) {
+ rc = port_funcs->qpc_query(cn_port, qp->qp_id, is_req, &qpc_attr);
+
+ if (rc && (rc != -EBUSY && rc != -ETIMEDOUT))
+ return rc;
+
+ if (!(rc || qpc_attr.in_work))
+ return 0;
+
+ /* Release lock while we wait before retry.
+ * Note, we can assert that we are already locked.
+ */
+ port_funcs->cfg_unlock(cn_port);
+
+ msleep(20);
+
+ port_funcs->cfg_lock(cn_port);
+ }
+
+ rc = port_funcs->qpc_query(cn_port, qp->qp_id, is_req, &qpc_attr);
+
+ if (rc && (rc != -EBUSY && rc != -ETIMEDOUT))
+ return rc;
+
+ if (rc || qpc_attr.in_work)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int cn_qp_op_reset(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ int rc, rc1;
+
+ asic_funcs = hdev->asic_funcs;
+
+ /* clear the QPCs */
+ rc = asic_funcs->port_funcs->qpc_clear(cn_port, qp, false);
+ if (rc && hbl_cn_comp_device_operational(hdev))
+ /* Device might not respond during reset if the reset was due to error */
+ dev_err(hdev->dev, "Port %d QP %d: Failed to clear responder QPC\n",
+ qp->port, qp->qp_id);
+ else
+ qp->is_res = false;
+
+ rc1 = asic_funcs->port_funcs->qpc_clear(cn_port, qp, true);
+ if (rc1) {
+ rc = rc1;
+ if (hbl_cn_comp_device_operational(hdev))
+ /* Device might not respond during reset if the reset was due to error */
+ dev_err(hdev->dev, "Port %d QP %d: Failed to clear requestor QPC\n",
+ qp->port, qp->qp_id);
+ } else {
+ qp->is_req = false;
+ }
+
+ /* wait for REQ idle, RES idle is already done in cn_qp_op_2qpd */
+ rc = wait_for_qpc_idle(cn_port, qp, true);
+ if (rc) {
+ dev_err(hdev->dev, "Port %d QP %d, Requestor QPC is not idle (rc %d)\n",
+ cn_port->port, qp->qp_id, rc);
+ return rc;
+ }
+
+ qp->curr_state = CN_QP_STATE_RESET;
+
+ return rc;
+}
+
+static int cn_qp_op_reset_2init(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp)
+{
+ if (ZERO_OR_NULL_PTR(qp))
+ return -EINVAL;
+
+ qp->curr_state = CN_QP_STATE_INIT;
+
+ return 0;
+}
+
+static int cn_qp_op_2rts(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp,
+ struct hbl_cni_req_conn_ctx_in *in)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ int rc;
+
+ asic_funcs = hdev->asic_funcs;
+
+ rc = asic_funcs->set_req_qp_ctx(hdev, in, qp);
+ if (rc)
+ return rc;
+
+ qp->curr_state = CN_QP_STATE_RTS;
+ qp->is_req = true;
+
+ return 0;
+}
+
+static int cn_qp_op_2rtr(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp,
+ struct hbl_cni_res_conn_ctx_in *in)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ int rc;
+
+ asic_funcs = hdev->asic_funcs;
+
+ rc = asic_funcs->set_res_qp_ctx(hdev, in, qp);
+ if (rc)
+ return rc;
+
+ qp->curr_state = CN_QP_STATE_RTR;
+ qp->is_res = true;
+
+ return 0;
+}
+
+static inline int cn_qp_invalidate_qpc(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp,
+ bool is_req)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ int i, rc;
+
+ asic_funcs = hdev->asic_funcs;
+
+ for (i = 0; i < OP_RETRY_COUNT; i++) {
+ rc = asic_funcs->port_funcs->qpc_invalidate(cn_port, qp, is_req);
+ if (!rc)
+ break;
+
+ usleep_range(100, 200);
+ }
+
+ return rc;
+}
+
+static int cn_qp_invalidate(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp, bool is_req,
+ bool wait_for_idle)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ int rc;
+
+ rc = cn_qp_invalidate_qpc(cn_port, qp, is_req);
+ if (rc) {
+ if (hbl_cn_comp_device_operational(hdev))
+ dev_err(hdev->dev, "Port %d QP %d, failed to invalidate %s QPC (rc %d)\n",
+ cn_port->port, qp->qp_id, is_req ? "Requester" : "Responder", rc);
+ return rc;
+ }
+
+ if (!wait_for_idle || is_req)
+ return 0;
+
+ /* check for QP idle in case of responder only */
+ rc = wait_for_qpc_idle(cn_port, qp, false);
+ if (rc) {
+ dev_err(hdev->dev, "Port %d QP %d, Responder QPC is not idle (rc %d)\n",
+ cn_port->port, qp->qp_id, rc);
+ return rc;
+ }
+
+ return rc;
+}
+
+/* Drain the Requester */
+static int cn_qp_op_rts_2sqd(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp, void *attr)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_qpc_drain_attr *drain = attr;
+ int rc = 0;
+
+ switch (qp->curr_state) {
+ case CN_QP_STATE_RTS:
+ cn_qp_invalidate(cn_port, qp, true, drain->wait_for_idle);
+ if (drain->wait_for_idle)
+ ssleep(hdev->qp_drain_time);
+
+ break;
+ default:
+ rc = -EOPNOTSUPP;
+ break;
+ }
+
+ if (!rc)
+ qp->curr_state = CN_QP_STATE_SQD;
+
+ return rc;
+}
+
+/* Re-drain the Requester. This function is called without holding the cfg lock so it must not
+ * access the HW or do anything other than just sleeping.
+ */
+static int cn_qp_op_sqd_2sqd(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp, void *attr)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_qpc_drain_attr *drain = attr;
+
+ /* no need to invalidate the QP as it was already invalidated just extend the wait time */
+ if (drain->wait_for_idle)
+ ssleep(hdev->qp_drain_time);
+
+ return 0;
+}
+
+/* Drain the QP (Requester and Responder) */
+static int cn_qp_op_2qpd(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp, void *attr)
+{
+ struct hbl_cn_qpc_drain_attr *drain = attr;
+ int rc = 0;
+
+ switch (qp->curr_state) {
+ case CN_QP_STATE_RTR:
+ /* In RTR only the Resp is working */
+ cn_qp_invalidate(cn_port, qp, false, drain->wait_for_idle);
+ break;
+ case CN_QP_STATE_RTS:
+ /* In RTS both the Resp and Req are working */
+ cn_qp_op_rts_2sqd(cn_port, qp, attr);
+ cn_qp_invalidate(cn_port, qp, false, drain->wait_for_idle);
+ break;
+ case CN_QP_STATE_SQD:
+ /* In SQD only the Resp is working */
+ cn_qp_invalidate(cn_port, qp, false, drain->wait_for_idle);
+ break;
+ case CN_QP_STATE_QPD:
+ break;
+ default:
+ rc = -EOPNOTSUPP;
+ break;
+ }
+
+ if (!rc)
+ qp->curr_state = CN_QP_STATE_QPD;
+
+ return rc;
+}
+
+static int cn_qp_op_2reset(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp,
+ const struct hbl_cn_qpc_reset_attr *attr)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct hbl_cn_qpc_drain_attr drain;
+
+ asic_funcs = hdev->asic_funcs;
+
+ /* brute-force reset when reset mode is Hard */
+ if (attr->reset_mode == CN_QP_RESET_MODE_HARD && qp->curr_state != CN_QP_STATE_RESET) {
+ /* invalidate */
+ asic_funcs->port_funcs->qpc_invalidate(cn_port, qp, true);
+ asic_funcs->port_funcs->qpc_invalidate(cn_port, qp, false);
+
+ /* wait for HW digest the invalidation */
+ usleep_range(100, 150);
+
+ cn_qp_op_reset(cn_port, qp);
+ return 0;
+ }
+
+ if (attr->reset_mode == CN_QP_RESET_MODE_GRACEFUL)
+ drain.wait_for_idle = true;
+ else
+ drain.wait_for_idle = false;
+
+ switch (qp->curr_state) {
+ case CN_QP_STATE_RESET:
+ break;
+ case CN_QP_STATE_INIT:
+ cn_qp_op_reset(cn_port, qp);
+ break;
+ case CN_QP_STATE_RTR:
+ case CN_QP_STATE_RTS:
+ case CN_QP_STATE_SQD:
+ cn_qp_op_2qpd(cn_port, qp, &drain);
+ cn_qp_op_reset(cn_port, qp);
+ break;
+ case CN_QP_STATE_QPD:
+ cn_qp_op_reset(cn_port, qp);
+ break;
+ case CN_QP_STATE_SQERR:
+ case CN_QP_STATE_ERR:
+ cn_qp_op_reset(cn_port, qp);
+ break;
+ default:
+ dev_err(hdev->dev, "Port %d QP %d: Unknown state %d, moving to RESET state\n",
+ qp->port, qp->qp_id, qp->curr_state);
+ cn_qp_op_reset(cn_port, qp);
+ break;
+ }
+
+ return 0;
+}
+
+/* QP state handling routines */
int hbl_cn_qp_modify(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp,
enum hbl_cn_qp_state new_state, void *params)
{
- return 0;
+ enum hbl_cn_qp_state prev_state = qp->curr_state;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ enum hbl_cn_qp_state_op op;
+ int rc;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ /* only SQD->SQD transition can be executed without holding the configuration lock */
+ if (prev_state != CN_QP_STATE_SQD || new_state != CN_QP_STATE_SQD) {
+ if (!port_funcs->cfg_is_locked(cn_port)) {
+ dev_err(hdev->dev,
+ "Configuration lock must be held while moving Port %u QP %u from state %s to %s\n",
+ qp->port, qp->qp_id, cn_qp_state_2name(prev_state),
+ cn_qp_state_2name(new_state));
+ return -EACCES;
+ }
+ }
+
+ if (qp->curr_state >= CN_QP_NUM_STATE || new_state >= CN_QP_NUM_STATE ||
+ qp_valid_state_op[qp->curr_state][new_state] == CN_QP_OP_INVAL) {
+ dev_err(hdev->dev,
+ "Invalid QP state transition, Port %u QP %u from state %s to %s\n",
+ qp->port, qp->qp_id, cn_qp_state_2name(prev_state),
+ cn_qp_state_2name(new_state));
+ return -EINVAL;
+ }
+
+ if (new_state >= CN_QP_NUM_STATE) {
+ dev_err(hdev->dev, "Invalid QP state %d\n", new_state);
+ return -EINVAL;
+ }
+
+ /* get the operation needed for this state transition */
+ op = qp_valid_state_op[qp->curr_state][new_state];
+
+ switch (op) {
+ case CN_QP_OP_2RESET:
+ rc = cn_qp_op_2reset(cn_port, qp, params);
+ break;
+ case CN_QP_OP_RST_2INIT:
+ rc = cn_qp_op_reset_2init(cn_port, qp);
+ break;
+ case CN_QP_OP_INIT_2RTR:
+ rc = cn_qp_op_2rtr(cn_port, qp, params);
+ break;
+ case CN_QP_OP_RTR_2RTR:
+ rc = cn_qp_op_2rtr(cn_port, qp, params);
+ break;
+ case CN_QP_OP_RTR_2QPD:
+ rc = cn_qp_op_2qpd(cn_port, qp, params);
+ break;
+ case CN_QP_OP_RTR_2RTS:
+ rc = cn_qp_op_2rts(cn_port, qp, params);
+ break;
+ case CN_QP_OP_RTS_2RTS:
+ rc = cn_qp_op_2rts(cn_port, qp, params);
+ break;
+ case CN_QP_OP_RTS_2SQD:
+ rc = cn_qp_op_rts_2sqd(cn_port, qp, params);
+ break;
+ case CN_QP_OP_SQD_2SQD:
+ rc = cn_qp_op_sqd_2sqd(cn_port, qp, params);
+ break;
+ case CN_QP_OP_RTS_2QPD:
+ rc = cn_qp_op_2qpd(cn_port, qp, params);
+ break;
+ case CN_QP_OP_SQD_2QPD:
+ rc = cn_qp_op_2qpd(cn_port, qp, params);
+ break;
+ case CN_QP_OP_INVAL:
+ rc = -EINVAL;
+ break;
+ case CN_QP_OP_NOP:
+ rc = 0;
+ break;
+ default:
+ rc = -EOPNOTSUPP;
+ break;
+ }
+
+ if (rc)
+ dev_err(hdev->dev,
+ "Errors detected while moving Port %u QP %u from state %s to %s, (rc %d)\n",
+ qp->port, qp->qp_id, cn_qp_state_2name(prev_state),
+ cn_qp_state_2name(new_state), rc);
+
+ return rc;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* Re: [PATCH 04/15] net: hbl_cn: QP state machine
2024-06-13 8:21 ` [PATCH 04/15] net: hbl_cn: QP state machine Omer Shpigelman
@ 2024-06-17 13:18 ` Leon Romanovsky
2024-06-18 5:50 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Leon Romanovsky @ 2024-06-17 13:18 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel, linux-rdma, netdev, dri-devel, ogabbay, zyehudai
On Thu, Jun 13, 2024 at 11:21:57AM +0300, Omer Shpigelman wrote:
> Add a common QP state machine which handles the moving for a QP from one
> state to another including performing necessary checks, draining
> in-flight transactions, invalidating caches and error reporting.
>
> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> Co-developed-by: David Meriin <dmeriin@habana.ai>
> Signed-off-by: David Meriin <dmeriin@habana.ai>
> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
> ---
> .../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 480 +++++++++++++++++-
> 1 file changed, 479 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
> index 9ddc23bf8194..26ebdf448193 100644
> --- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
> +++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
> @@ -6,8 +6,486 @@
<...>
> +/* The following table represents the (valid) operations that can be performed on
> + * a QP in order to move it from one state to another
> + * For example: a QP in RTR state can be moved to RTS state using the CN_QP_OP_RTR_2RTS
> + * operation.
> + */
> +static const enum hbl_cn_qp_state_op qp_valid_state_op[CN_QP_NUM_STATE][CN_QP_NUM_STATE] = {
> + [CN_QP_STATE_RESET] = {
> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> + [CN_QP_STATE_INIT] = CN_QP_OP_RST_2INIT,
> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
> + },
> + [CN_QP_STATE_INIT] = {
> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> + [CN_QP_STATE_INIT] = CN_QP_OP_NOP,
> + [CN_QP_STATE_RTR] = CN_QP_OP_INIT_2RTR,
> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
> + },
> + [CN_QP_STATE_RTR] = {
> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> + [CN_QP_STATE_RTR] = CN_QP_OP_RTR_2RTR,
> + [CN_QP_STATE_RTS] = CN_QP_OP_RTR_2RTS,
> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
> + [CN_QP_STATE_QPD] = CN_QP_OP_RTR_2QPD,
> + },
> + [CN_QP_STATE_RTS] = {
> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> + [CN_QP_STATE_RTS] = CN_QP_OP_RTS_2RTS,
> + [CN_QP_STATE_SQD] = CN_QP_OP_RTS_2SQD,
> + [CN_QP_STATE_QPD] = CN_QP_OP_RTS_2QPD,
> + [CN_QP_STATE_SQERR] = CN_QP_OP_RTS_2SQERR,
> + },
> + [CN_QP_STATE_SQD] = {
> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> + [CN_QP_STATE_SQD] = CN_QP_OP_SQD_2SQD,
> + [CN_QP_STATE_RTS] = CN_QP_OP_SQD_2RTS,
> + [CN_QP_STATE_QPD] = CN_QP_OP_SQD_2QPD,
> + [CN_QP_STATE_SQERR] = CN_QP_OP_SQD_2SQ_ERR,
> + },
> + [CN_QP_STATE_QPD] = {
> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
> + [CN_QP_STATE_RTR] = CN_QP_OP_QPD_2RTR,
> + },
> + [CN_QP_STATE_SQERR] = {
> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> + [CN_QP_STATE_SQD] = CN_QP_OP_SQ_ERR_2SQD,
> + [CN_QP_STATE_SQERR] = CN_QP_OP_NOP,
> + },
> + [CN_QP_STATE_ERR] = {
> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> + }
> +};
I don't understand why IBTA QP state machine is declared in ETH driver
and not in IB driver.
> +
<...>
> + /* Release lock while we wait before retry.
> + * Note, we can assert that we are already locked.
> + */
> + port_funcs->cfg_unlock(cn_port);
> +
> + msleep(20);
> +
> + port_funcs->cfg_lock(cn_port);
lock/unlock through ops pointer doesn't look like a good idea.
Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 04/15] net: hbl_cn: QP state machine
2024-06-17 13:18 ` Leon Romanovsky
@ 2024-06-18 5:50 ` Omer Shpigelman
2024-06-18 7:08 ` Leon Romanovsky
0 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-18 5:50 UTC (permalink / raw)
To: Leon Romanovsky
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/17/24 16:18, Leon Romanovsky wrote:
> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On Thu, Jun 13, 2024 at 11:21:57AM +0300, Omer Shpigelman wrote:
>> Add a common QP state machine which handles the moving for a QP from one
>> state to another including performing necessary checks, draining
>> in-flight transactions, invalidating caches and error reporting.
>>
>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
>> Co-developed-by: David Meriin <dmeriin@habana.ai>
>> Signed-off-by: David Meriin <dmeriin@habana.ai>
>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
>> ---
>> .../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 480 +++++++++++++++++-
>> 1 file changed, 479 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
>> index 9ddc23bf8194..26ebdf448193 100644
>> --- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
>> +++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
>> @@ -6,8 +6,486 @@
>
> <...>
>
>> +/* The following table represents the (valid) operations that can be performed on
>> + * a QP in order to move it from one state to another
>> + * For example: a QP in RTR state can be moved to RTS state using the CN_QP_OP_RTR_2RTS
>> + * operation.
>> + */
>> +static const enum hbl_cn_qp_state_op qp_valid_state_op[CN_QP_NUM_STATE][CN_QP_NUM_STATE] = {
>> + [CN_QP_STATE_RESET] = {
>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>> + [CN_QP_STATE_INIT] = CN_QP_OP_RST_2INIT,
>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
>> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
>> + },
>> + [CN_QP_STATE_INIT] = {
>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>> + [CN_QP_STATE_INIT] = CN_QP_OP_NOP,
>> + [CN_QP_STATE_RTR] = CN_QP_OP_INIT_2RTR,
>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
>> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
>> + },
>> + [CN_QP_STATE_RTR] = {
>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>> + [CN_QP_STATE_RTR] = CN_QP_OP_RTR_2RTR,
>> + [CN_QP_STATE_RTS] = CN_QP_OP_RTR_2RTS,
>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
>> + [CN_QP_STATE_QPD] = CN_QP_OP_RTR_2QPD,
>> + },
>> + [CN_QP_STATE_RTS] = {
>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>> + [CN_QP_STATE_RTS] = CN_QP_OP_RTS_2RTS,
>> + [CN_QP_STATE_SQD] = CN_QP_OP_RTS_2SQD,
>> + [CN_QP_STATE_QPD] = CN_QP_OP_RTS_2QPD,
>> + [CN_QP_STATE_SQERR] = CN_QP_OP_RTS_2SQERR,
>> + },
>> + [CN_QP_STATE_SQD] = {
>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>> + [CN_QP_STATE_SQD] = CN_QP_OP_SQD_2SQD,
>> + [CN_QP_STATE_RTS] = CN_QP_OP_SQD_2RTS,
>> + [CN_QP_STATE_QPD] = CN_QP_OP_SQD_2QPD,
>> + [CN_QP_STATE_SQERR] = CN_QP_OP_SQD_2SQ_ERR,
>> + },
>> + [CN_QP_STATE_QPD] = {
>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
>> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
>> + [CN_QP_STATE_RTR] = CN_QP_OP_QPD_2RTR,
>> + },
>> + [CN_QP_STATE_SQERR] = {
>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>> + [CN_QP_STATE_SQD] = CN_QP_OP_SQ_ERR_2SQD,
>> + [CN_QP_STATE_SQERR] = CN_QP_OP_NOP,
>> + },
>> + [CN_QP_STATE_ERR] = {
>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>> + }
>> +};
>
> I don't understand why IBTA QP state machine is declared in ETH driver
> and not in IB driver.
>
Implementing the actual transitions between the states requires full
knowledge of the HW e.g. when to flush, cache invalidation, timeouts.
Our IB driver is agnostic to the ASIC type by design. Note that more ASIC
generations are planned to be added and the IB driver should not be aware
of these additional HWs.
Hence we implemeted the QP state machine in the CN driver which is aware
of the actual HW.
>> +
>
> <...>
>
>> + /* Release lock while we wait before retry.
>> + * Note, we can assert that we are already locked.
>> + */
>> + port_funcs->cfg_unlock(cn_port);
>> +
>> + msleep(20);
>> +
>> + port_funcs->cfg_lock(cn_port);
>
> lock/unlock through ops pointer doesn't look like a good idea.
>
More ASIC generations will be added once we merge the current Gaudi2 code.
On other ASICs the locking granularity is different because some of the HW
resources are shared between different logical ports.
Hence it is was logical for us to implement it with a function pointer so
each ASIC specific code can implemnet the locking properly.
> Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 04/15] net: hbl_cn: QP state machine
2024-06-18 5:50 ` Omer Shpigelman
@ 2024-06-18 7:08 ` Leon Romanovsky
2024-06-18 7:58 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Leon Romanovsky @ 2024-06-18 7:08 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On Tue, Jun 18, 2024 at 05:50:15AM +0000, Omer Shpigelman wrote:
> On 6/17/24 16:18, Leon Romanovsky wrote:
> > [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > On Thu, Jun 13, 2024 at 11:21:57AM +0300, Omer Shpigelman wrote:
> >> Add a common QP state machine which handles the moving for a QP from one
> >> state to another including performing necessary checks, draining
> >> in-flight transactions, invalidating caches and error reporting.
> >>
> >> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> >> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> >> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> >> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> >> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> >> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> >> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> >> Co-developed-by: David Meriin <dmeriin@habana.ai>
> >> Signed-off-by: David Meriin <dmeriin@habana.ai>
> >> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> >> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> >> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> >> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
> >> ---
> >> .../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 480 +++++++++++++++++-
> >> 1 file changed, 479 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
> >> index 9ddc23bf8194..26ebdf448193 100644
> >> --- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
> >> +++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
> >> @@ -6,8 +6,486 @@
> >
> > <...>
> >
> >> +/* The following table represents the (valid) operations that can be performed on
> >> + * a QP in order to move it from one state to another
> >> + * For example: a QP in RTR state can be moved to RTS state using the CN_QP_OP_RTR_2RTS
> >> + * operation.
> >> + */
> >> +static const enum hbl_cn_qp_state_op qp_valid_state_op[CN_QP_NUM_STATE][CN_QP_NUM_STATE] = {
> >> + [CN_QP_STATE_RESET] = {
> >> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >> + [CN_QP_STATE_INIT] = CN_QP_OP_RST_2INIT,
> >> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
> >> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
> >> + },
> >> + [CN_QP_STATE_INIT] = {
> >> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> >> + [CN_QP_STATE_INIT] = CN_QP_OP_NOP,
> >> + [CN_QP_STATE_RTR] = CN_QP_OP_INIT_2RTR,
> >> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
> >> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
> >> + },
> >> + [CN_QP_STATE_RTR] = {
> >> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> >> + [CN_QP_STATE_RTR] = CN_QP_OP_RTR_2RTR,
> >> + [CN_QP_STATE_RTS] = CN_QP_OP_RTR_2RTS,
> >> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
> >> + [CN_QP_STATE_QPD] = CN_QP_OP_RTR_2QPD,
> >> + },
> >> + [CN_QP_STATE_RTS] = {
> >> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> >> + [CN_QP_STATE_RTS] = CN_QP_OP_RTS_2RTS,
> >> + [CN_QP_STATE_SQD] = CN_QP_OP_RTS_2SQD,
> >> + [CN_QP_STATE_QPD] = CN_QP_OP_RTS_2QPD,
> >> + [CN_QP_STATE_SQERR] = CN_QP_OP_RTS_2SQERR,
> >> + },
> >> + [CN_QP_STATE_SQD] = {
> >> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> >> + [CN_QP_STATE_SQD] = CN_QP_OP_SQD_2SQD,
> >> + [CN_QP_STATE_RTS] = CN_QP_OP_SQD_2RTS,
> >> + [CN_QP_STATE_QPD] = CN_QP_OP_SQD_2QPD,
> >> + [CN_QP_STATE_SQERR] = CN_QP_OP_SQD_2SQ_ERR,
> >> + },
> >> + [CN_QP_STATE_QPD] = {
> >> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> >> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
> >> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
> >> + [CN_QP_STATE_RTR] = CN_QP_OP_QPD_2RTR,
> >> + },
> >> + [CN_QP_STATE_SQERR] = {
> >> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> >> + [CN_QP_STATE_SQD] = CN_QP_OP_SQ_ERR_2SQD,
> >> + [CN_QP_STATE_SQERR] = CN_QP_OP_NOP,
> >> + },
> >> + [CN_QP_STATE_ERR] = {
> >> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> >> + }
> >> +};
> >
> > I don't understand why IBTA QP state machine is declared in ETH driver
> > and not in IB driver.
> >
>
> Implementing the actual transitions between the states requires full
> knowledge of the HW e.g. when to flush, cache invalidation, timeouts.
> Our IB driver is agnostic to the ASIC type by design. Note that more ASIC
> generations are planned to be added and the IB driver should not be aware
> of these additional HWs.
> Hence we implemeted the QP state machine in the CN driver which is aware
> of the actual HW.
Somehow ALL other IB drivers are able to implement this logic in the IB,
while supporting multiple ASICs. I don't see a reason why you can't do
the same.
>
> >> +
> >
> > <...>
> >
> >> + /* Release lock while we wait before retry.
> >> + * Note, we can assert that we are already locked.
> >> + */
> >> + port_funcs->cfg_unlock(cn_port);
> >> +
> >> + msleep(20);
> >> +
> >> + port_funcs->cfg_lock(cn_port);
> >
> > lock/unlock through ops pointer doesn't look like a good idea.
> >
>
> More ASIC generations will be added once we merge the current Gaudi2 code.
> On other ASICs the locking granularity is different because some of the HW
> resources are shared between different logical ports.
> Hence it is was logical for us to implement it with a function pointer so
> each ASIC specific code can implemnet the locking properly.
We are reviewing this code which is for the current ASIC, not for the
unknown future ASICs. Please don't over engineer the first submission.
You will always be able to improve/change the code once you decide to
upstream your future ASICs.
Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 04/15] net: hbl_cn: QP state machine
2024-06-18 7:08 ` Leon Romanovsky
@ 2024-06-18 7:58 ` Omer Shpigelman
2024-06-18 9:00 ` Leon Romanovsky
0 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-18 7:58 UTC (permalink / raw)
To: Leon Romanovsky
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/18/24 10:08, Leon Romanovsky wrote:
> On Tue, Jun 18, 2024 at 05:50:15AM +0000, Omer Shpigelman wrote:
>> On 6/17/24 16:18, Leon Romanovsky wrote:
>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>
>>> On Thu, Jun 13, 2024 at 11:21:57AM +0300, Omer Shpigelman wrote:
>>>> Add a common QP state machine which handles the moving for a QP from one
>>>> state to another including performing necessary checks, draining
>>>> in-flight transactions, invalidating caches and error reporting.
>>>>
>>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
>>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
>>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
>>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
>>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
>>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
>>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
>>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
>>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
>>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
>>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
>>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
>>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
>>>> ---
>>>> .../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 480 +++++++++++++++++-
>>>> 1 file changed, 479 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
>>>> index 9ddc23bf8194..26ebdf448193 100644
>>>> --- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
>>>> +++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
>>>> @@ -6,8 +6,486 @@
>>>
>>> <...>
>>>
>>>> +/* The following table represents the (valid) operations that can be performed on
>>>> + * a QP in order to move it from one state to another
>>>> + * For example: a QP in RTR state can be moved to RTS state using the CN_QP_OP_RTR_2RTS
>>>> + * operation.
>>>> + */
>>>> +static const enum hbl_cn_qp_state_op qp_valid_state_op[CN_QP_NUM_STATE][CN_QP_NUM_STATE] = {
>>>> + [CN_QP_STATE_RESET] = {
>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>> + [CN_QP_STATE_INIT] = CN_QP_OP_RST_2INIT,
>>>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
>>>> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
>>>> + },
>>>> + [CN_QP_STATE_INIT] = {
>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>>>> + [CN_QP_STATE_INIT] = CN_QP_OP_NOP,
>>>> + [CN_QP_STATE_RTR] = CN_QP_OP_INIT_2RTR,
>>>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
>>>> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
>>>> + },
>>>> + [CN_QP_STATE_RTR] = {
>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>>>> + [CN_QP_STATE_RTR] = CN_QP_OP_RTR_2RTR,
>>>> + [CN_QP_STATE_RTS] = CN_QP_OP_RTR_2RTS,
>>>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
>>>> + [CN_QP_STATE_QPD] = CN_QP_OP_RTR_2QPD,
>>>> + },
>>>> + [CN_QP_STATE_RTS] = {
>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>>>> + [CN_QP_STATE_RTS] = CN_QP_OP_RTS_2RTS,
>>>> + [CN_QP_STATE_SQD] = CN_QP_OP_RTS_2SQD,
>>>> + [CN_QP_STATE_QPD] = CN_QP_OP_RTS_2QPD,
>>>> + [CN_QP_STATE_SQERR] = CN_QP_OP_RTS_2SQERR,
>>>> + },
>>>> + [CN_QP_STATE_SQD] = {
>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>>>> + [CN_QP_STATE_SQD] = CN_QP_OP_SQD_2SQD,
>>>> + [CN_QP_STATE_RTS] = CN_QP_OP_SQD_2RTS,
>>>> + [CN_QP_STATE_QPD] = CN_QP_OP_SQD_2QPD,
>>>> + [CN_QP_STATE_SQERR] = CN_QP_OP_SQD_2SQ_ERR,
>>>> + },
>>>> + [CN_QP_STATE_QPD] = {
>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>>>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
>>>> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
>>>> + [CN_QP_STATE_RTR] = CN_QP_OP_QPD_2RTR,
>>>> + },
>>>> + [CN_QP_STATE_SQERR] = {
>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>>>> + [CN_QP_STATE_SQD] = CN_QP_OP_SQ_ERR_2SQD,
>>>> + [CN_QP_STATE_SQERR] = CN_QP_OP_NOP,
>>>> + },
>>>> + [CN_QP_STATE_ERR] = {
>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>>>> + }
>>>> +};
>>>
>>> I don't understand why IBTA QP state machine is declared in ETH driver
>>> and not in IB driver.
>>>
>>
>> Implementing the actual transitions between the states requires full
>> knowledge of the HW e.g. when to flush, cache invalidation, timeouts.
>> Our IB driver is agnostic to the ASIC type by design. Note that more ASIC
>> generations are planned to be added and the IB driver should not be aware
>> of these additional HWs.
>> Hence we implemeted the QP state machine in the CN driver which is aware
>> of the actual HW.
>
> Somehow ALL other IB drivers are able to implement this logic in the IB,
> while supporting multiple ASICs. I don't see a reason why you can't do
> the same.
>
If we are referring to this actual table, then I can move it to the IB
driver and the CN driver will fetch the needed opcode via a function
pointer.
Is that ok?
>>
>>>> +
>>>
>>> <...>
>>>
>>>> + /* Release lock while we wait before retry.
>>>> + * Note, we can assert that we are already locked.
>>>> + */
>>>> + port_funcs->cfg_unlock(cn_port);
>>>> +
>>>> + msleep(20);
>>>> +
>>>> + port_funcs->cfg_lock(cn_port);
>>>
>>> lock/unlock through ops pointer doesn't look like a good idea.
>>>
>>
>> More ASIC generations will be added once we merge the current Gaudi2 code.
>> On other ASICs the locking granularity is different because some of the HW
>> resources are shared between different logical ports.
>> Hence it is was logical for us to implement it with a function pointer so
>> each ASIC specific code can implemnet the locking properly.
>
> We are reviewing this code which is for the current ASIC, not for the
> unknown future ASICs. Please don't over engineer the first submission.
> You will always be able to improve/change the code once you decide to
> upstream your future ASICs.
>
I see. I'll refactor the code then.
> Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 04/15] net: hbl_cn: QP state machine
2024-06-18 7:58 ` Omer Shpigelman
@ 2024-06-18 9:00 ` Leon Romanovsky
2024-06-24 7:24 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Leon Romanovsky @ 2024-06-18 9:00 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On Tue, Jun 18, 2024 at 07:58:55AM +0000, Omer Shpigelman wrote:
> On 6/18/24 10:08, Leon Romanovsky wrote:
> > On Tue, Jun 18, 2024 at 05:50:15AM +0000, Omer Shpigelman wrote:
> >> On 6/17/24 16:18, Leon Romanovsky wrote:
> >>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >>>
> >>> On Thu, Jun 13, 2024 at 11:21:57AM +0300, Omer Shpigelman wrote:
> >>>> Add a common QP state machine which handles the moving for a QP from one
> >>>> state to another including performing necessary checks, draining
> >>>> in-flight transactions, invalidating caches and error reporting.
> >>>>
> >>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> >>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> >>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> >>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> >>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> >>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> >>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> >>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
> >>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
> >>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> >>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> >>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> >>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
> >>>> ---
> >>>> .../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 480 +++++++++++++++++-
> >>>> 1 file changed, 479 insertions(+), 1 deletion(-)
> >>>>
> >>>> diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
> >>>> index 9ddc23bf8194..26ebdf448193 100644
> >>>> --- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
> >>>> +++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
> >>>> @@ -6,8 +6,486 @@
> >>>
> >>> <...>
> >>>
> >>>> +/* The following table represents the (valid) operations that can be performed on
> >>>> + * a QP in order to move it from one state to another
> >>>> + * For example: a QP in RTR state can be moved to RTS state using the CN_QP_OP_RTR_2RTS
> >>>> + * operation.
> >>>> + */
> >>>> +static const enum hbl_cn_qp_state_op qp_valid_state_op[CN_QP_NUM_STATE][CN_QP_NUM_STATE] = {
> >>>> + [CN_QP_STATE_RESET] = {
> >>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >>>> + [CN_QP_STATE_INIT] = CN_QP_OP_RST_2INIT,
> >>>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
> >>>> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
> >>>> + },
> >>>> + [CN_QP_STATE_INIT] = {
> >>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> >>>> + [CN_QP_STATE_INIT] = CN_QP_OP_NOP,
> >>>> + [CN_QP_STATE_RTR] = CN_QP_OP_INIT_2RTR,
> >>>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
> >>>> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
> >>>> + },
> >>>> + [CN_QP_STATE_RTR] = {
> >>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> >>>> + [CN_QP_STATE_RTR] = CN_QP_OP_RTR_2RTR,
> >>>> + [CN_QP_STATE_RTS] = CN_QP_OP_RTR_2RTS,
> >>>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
> >>>> + [CN_QP_STATE_QPD] = CN_QP_OP_RTR_2QPD,
> >>>> + },
> >>>> + [CN_QP_STATE_RTS] = {
> >>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> >>>> + [CN_QP_STATE_RTS] = CN_QP_OP_RTS_2RTS,
> >>>> + [CN_QP_STATE_SQD] = CN_QP_OP_RTS_2SQD,
> >>>> + [CN_QP_STATE_QPD] = CN_QP_OP_RTS_2QPD,
> >>>> + [CN_QP_STATE_SQERR] = CN_QP_OP_RTS_2SQERR,
> >>>> + },
> >>>> + [CN_QP_STATE_SQD] = {
> >>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> >>>> + [CN_QP_STATE_SQD] = CN_QP_OP_SQD_2SQD,
> >>>> + [CN_QP_STATE_RTS] = CN_QP_OP_SQD_2RTS,
> >>>> + [CN_QP_STATE_QPD] = CN_QP_OP_SQD_2QPD,
> >>>> + [CN_QP_STATE_SQERR] = CN_QP_OP_SQD_2SQ_ERR,
> >>>> + },
> >>>> + [CN_QP_STATE_QPD] = {
> >>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> >>>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
> >>>> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
> >>>> + [CN_QP_STATE_RTR] = CN_QP_OP_QPD_2RTR,
> >>>> + },
> >>>> + [CN_QP_STATE_SQERR] = {
> >>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> >>>> + [CN_QP_STATE_SQD] = CN_QP_OP_SQ_ERR_2SQD,
> >>>> + [CN_QP_STATE_SQERR] = CN_QP_OP_NOP,
> >>>> + },
> >>>> + [CN_QP_STATE_ERR] = {
> >>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
> >>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
> >>>> + }
> >>>> +};
> >>>
> >>> I don't understand why IBTA QP state machine is declared in ETH driver
> >>> and not in IB driver.
> >>>
> >>
> >> Implementing the actual transitions between the states requires full
> >> knowledge of the HW e.g. when to flush, cache invalidation, timeouts.
> >> Our IB driver is agnostic to the ASIC type by design. Note that more ASIC
> >> generations are planned to be added and the IB driver should not be aware
> >> of these additional HWs.
> >> Hence we implemeted the QP state machine in the CN driver which is aware
> >> of the actual HW.
> >
> > Somehow ALL other IB drivers are able to implement this logic in the IB,
> > while supporting multiple ASICs. I don't see a reason why you can't do
> > the same.
> >
>
> If we are referring to this actual table, then I can move it to the IB
> driver and the CN driver will fetch the needed opcode via a function
> pointer.
> Is that ok?
This table spotted my attention, but right separation shouldn't be limited
to only this table. The outcome of this conversation should be:
"IB specific logic should be in IB driver, and CN driver should be able to
handle only low-level operations".
Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 04/15] net: hbl_cn: QP state machine
2024-06-18 9:00 ` Leon Romanovsky
@ 2024-06-24 7:24 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-24 7:24 UTC (permalink / raw)
To: Leon Romanovsky
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/18/24 12:00, Leon Romanovsky wrote:
> On Tue, Jun 18, 2024 at 07:58:55AM +0000, Omer Shpigelman wrote:
>> On 6/18/24 10:08, Leon Romanovsky wrote:
>>> On Tue, Jun 18, 2024 at 05:50:15AM +0000, Omer Shpigelman wrote:
>>>> On 6/17/24 16:18, Leon Romanovsky wrote:
>>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>>
>>>>> On Thu, Jun 13, 2024 at 11:21:57AM +0300, Omer Shpigelman wrote:
>>>>>> Add a common QP state machine which handles the moving for a QP from one
>>>>>> state to another including performing necessary checks, draining
>>>>>> in-flight transactions, invalidating caches and error reporting.
>>>>>>
>>>>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
>>>>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
>>>>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
>>>>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
>>>>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
>>>>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
>>>>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
>>>>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
>>>>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
>>>>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
>>>>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
>>>>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
>>>>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
>>>>>> ---
>>>>>> .../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 480 +++++++++++++++++-
>>>>>> 1 file changed, 479 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
>>>>>> index 9ddc23bf8194..26ebdf448193 100644
>>>>>> --- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
>>>>>> +++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
>>>>>> @@ -6,8 +6,486 @@
>>>>>
>>>>> <...>
>>>>>
>>>>>> +/* The following table represents the (valid) operations that can be performed on
>>>>>> + * a QP in order to move it from one state to another
>>>>>> + * For example: a QP in RTR state can be moved to RTS state using the CN_QP_OP_RTR_2RTS
>>>>>> + * operation.
>>>>>> + */
>>>>>> +static const enum hbl_cn_qp_state_op qp_valid_state_op[CN_QP_NUM_STATE][CN_QP_NUM_STATE] = {
>>>>>> + [CN_QP_STATE_RESET] = {
>>>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>>>> + [CN_QP_STATE_INIT] = CN_QP_OP_RST_2INIT,
>>>>>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
>>>>>> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
>>>>>> + },
>>>>>> + [CN_QP_STATE_INIT] = {
>>>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>>>>>> + [CN_QP_STATE_INIT] = CN_QP_OP_NOP,
>>>>>> + [CN_QP_STATE_RTR] = CN_QP_OP_INIT_2RTR,
>>>>>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
>>>>>> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
>>>>>> + },
>>>>>> + [CN_QP_STATE_RTR] = {
>>>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>>>>>> + [CN_QP_STATE_RTR] = CN_QP_OP_RTR_2RTR,
>>>>>> + [CN_QP_STATE_RTS] = CN_QP_OP_RTR_2RTS,
>>>>>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
>>>>>> + [CN_QP_STATE_QPD] = CN_QP_OP_RTR_2QPD,
>>>>>> + },
>>>>>> + [CN_QP_STATE_RTS] = {
>>>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>>>>>> + [CN_QP_STATE_RTS] = CN_QP_OP_RTS_2RTS,
>>>>>> + [CN_QP_STATE_SQD] = CN_QP_OP_RTS_2SQD,
>>>>>> + [CN_QP_STATE_QPD] = CN_QP_OP_RTS_2QPD,
>>>>>> + [CN_QP_STATE_SQERR] = CN_QP_OP_RTS_2SQERR,
>>>>>> + },
>>>>>> + [CN_QP_STATE_SQD] = {
>>>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>>>>>> + [CN_QP_STATE_SQD] = CN_QP_OP_SQD_2SQD,
>>>>>> + [CN_QP_STATE_RTS] = CN_QP_OP_SQD_2RTS,
>>>>>> + [CN_QP_STATE_QPD] = CN_QP_OP_SQD_2QPD,
>>>>>> + [CN_QP_STATE_SQERR] = CN_QP_OP_SQD_2SQ_ERR,
>>>>>> + },
>>>>>> + [CN_QP_STATE_QPD] = {
>>>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>>>>>> + [CN_QP_STATE_SQD] = CN_QP_OP_NOP,
>>>>>> + [CN_QP_STATE_QPD] = CN_QP_OP_NOP,
>>>>>> + [CN_QP_STATE_RTR] = CN_QP_OP_QPD_2RTR,
>>>>>> + },
>>>>>> + [CN_QP_STATE_SQERR] = {
>>>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>>>>>> + [CN_QP_STATE_SQD] = CN_QP_OP_SQ_ERR_2SQD,
>>>>>> + [CN_QP_STATE_SQERR] = CN_QP_OP_NOP,
>>>>>> + },
>>>>>> + [CN_QP_STATE_ERR] = {
>>>>>> + [CN_QP_STATE_RESET] = CN_QP_OP_2RESET,
>>>>>> + [CN_QP_STATE_ERR] = CN_QP_OP_2ERR,
>>>>>> + }
>>>>>> +};
>>>>>
>>>>> I don't understand why IBTA QP state machine is declared in ETH driver
>>>>> and not in IB driver.
>>>>>
>>>>
>>>> Implementing the actual transitions between the states requires full
>>>> knowledge of the HW e.g. when to flush, cache invalidation, timeouts.
>>>> Our IB driver is agnostic to the ASIC type by design. Note that more ASIC
>>>> generations are planned to be added and the IB driver should not be aware
>>>> of these additional HWs.
>>>> Hence we implemeted the QP state machine in the CN driver which is aware
>>>> of the actual HW.
>>>
>>> Somehow ALL other IB drivers are able to implement this logic in the IB,
>>> while supporting multiple ASICs. I don't see a reason why you can't do
>>> the same.
>>>
>>
>> If we are referring to this actual table, then I can move it to the IB
>> driver and the CN driver will fetch the needed opcode via a function
>> pointer.
>> Is that ok?
>
> This table spotted my attention, but right separation shouldn't be limited
> to only this table. The outcome of this conversation should be:
> "IB specific logic should be in IB driver, and CN driver should be able to
> handle only low-level operations".
>
> Thanks
Ok, I'll check how we can move the IB specific logic to the IB driver.
^ permalink raw reply [flat|nested] 108+ messages in thread
* [PATCH 05/15] net: hbl_cn: memory trace events
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
` (3 preceding siblings ...)
2024-06-13 8:21 ` [PATCH 04/15] net: hbl_cn: QP state machine Omer Shpigelman
@ 2024-06-13 8:21 ` Omer Shpigelman
2024-06-13 8:21 ` [PATCH 06/15] net: hbl_cn: debugfs support Omer Shpigelman
` (11 subsequent siblings)
16 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:21 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
Add trace events for hbl_cn to track memory allocations.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
.../net/ethernet/intel/hbl_cn/common/hbl_cn.c | 28 ++++-
.../ethernet/intel/hbl_cn/common/hbl_cn_drv.c | 3 +
.../intel/hbl_cn/common/hbl_cn_memory.c | 9 ++
include/trace/events/habanalabs_cn.h | 116 ++++++++++++++++++
4 files changed, 154 insertions(+), 2 deletions(-)
create mode 100644 include/trace/events/habanalabs_cn.h
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
index 946b11bfa61b..4e910b2cb8ac 100644
--- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
@@ -12,6 +12,8 @@
#include <linux/pci.h>
#include <linux/slab.h>
+#include <trace/events/habanalabs_cn.h>
+
#define NIC_MIN_WQS_PER_PORT 2
#define NIC_SEQ_RESETS_TIMEOUT_MS 15000 /* 15 seconds */
@@ -5892,8 +5894,15 @@ void *__hbl_cn_dma_alloc_coherent(struct hbl_cn_device *hdev, size_t size, dma_a
gfp_t flag, const char *caller)
{
const struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+ void *ptr;
+
+ ptr = asic_funcs->dma_alloc_coherent(hdev, size, dma_handle, flag);
- return asic_funcs->dma_alloc_coherent(hdev, size, dma_handle, flag);
+ if (trace_habanalabs_cn_dma_alloc_coherent_enabled())
+ trace_habanalabs_cn_dma_alloc_coherent(hdev->dev, (u64)(uintptr_t)ptr, *dma_handle,
+ size, caller);
+
+ return ptr;
}
void __hbl_cn_dma_free_coherent(struct hbl_cn_device *hdev, size_t size, void *cpu_addr,
@@ -5902,14 +5911,25 @@ void __hbl_cn_dma_free_coherent(struct hbl_cn_device *hdev, size_t size, void *c
const struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
asic_funcs->dma_free_coherent(hdev, size, cpu_addr, dma_addr);
+
+ if (trace_habanalabs_cn_dma_free_coherent_enabled())
+ trace_habanalabs_cn_dma_free_coherent(hdev->dev, (u64)(uintptr_t)cpu_addr, dma_addr,
+ size, caller);
}
void *__hbl_cn_dma_pool_zalloc(struct hbl_cn_device *hdev, size_t size, gfp_t mem_flags,
dma_addr_t *dma_handle, const char *caller)
{
const struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
+ void *ptr;
- return asic_funcs->dma_pool_zalloc(hdev, size, mem_flags, dma_handle);
+ ptr = asic_funcs->dma_pool_zalloc(hdev, size, mem_flags, dma_handle);
+
+ if (trace_habanalabs_cn_dma_pool_zalloc_enabled())
+ trace_habanalabs_cn_dma_pool_zalloc(hdev->dev, (u64)(uintptr_t)ptr, *dma_handle,
+ size, caller);
+
+ return ptr;
}
void __hbl_cn_dma_pool_free(struct hbl_cn_device *hdev, void *vaddr, dma_addr_t dma_addr,
@@ -5918,6 +5938,10 @@ void __hbl_cn_dma_pool_free(struct hbl_cn_device *hdev, void *vaddr, dma_addr_t
const struct hbl_cn_asic_funcs *asic_funcs = hdev->asic_funcs;
asic_funcs->dma_pool_free(hdev, vaddr, dma_addr);
+
+ if (trace_habanalabs_cn_dma_pool_free_enabled())
+ trace_habanalabs_cn_dma_pool_free(hdev->dev, (u64)(uintptr_t)vaddr, dma_addr, 0,
+ caller);
}
int hbl_cn_get_reg_pcie_addr(struct hbl_cn_device *hdev, u8 bar_id, u32 reg, u64 *pci_addr)
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_drv.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_drv.c
index 47eedd27f36e..5ea690509592 100644
--- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_drv.c
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_drv.c
@@ -12,6 +12,9 @@
#include <linux/auxiliary_bus.h>
#include <linux/sched/clock.h>
+#define CREATE_TRACE_POINTS
+#include <trace/events/habanalabs_cn.h>
+
#define HBL_DRIVER_AUTHOR "HabanaLabs Kernel Driver Team"
#define HBL_DRIVER_DESC "HabanaLabs AI accelerators Core Network driver"
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_memory.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_memory.c
index 878ecba66aa3..305b5b85acbe 100644
--- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_memory.c
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_memory.c
@@ -6,6 +6,7 @@
#include <linux/vmalloc.h>
#include "hbl_cn.h"
+#include <trace/events/habanalabs_cn.h>
static int hbl_cn_map_vmalloc_range(struct hbl_cn_ctx *ctx, u64 vmalloc_va, u64 device_va,
u64 size)
@@ -201,12 +202,16 @@ static struct hbl_cn_mem_buf *cn_mem_buf_alloc(struct hbl_cn_ctx *ctx, gfp_t gfp
static int cn_mem_alloc(struct hbl_cn_ctx *ctx, struct hbl_cn_mem_data *mem_data)
{
+ struct hbl_cn_device *hdev = ctx->hdev;
struct hbl_cn_mem_buf *buf;
buf = cn_mem_buf_alloc(ctx, GFP_KERNEL, mem_data);
if (!buf)
return -ENOMEM;
+ trace_habanalabs_cn_mem_alloc(hdev->dev, buf->mem_id, buf->handle, (u64)buf->kernel_address,
+ buf->bus_address, buf->device_va, buf->mappable_size);
+
mem_data->handle = buf->handle;
if (mem_data->mem_id == HBL_CN_DRV_MEM_HOST_DMA_COHERENT)
@@ -242,6 +247,10 @@ int hbl_cn_mem_alloc(struct hbl_cn_ctx *ctx, struct hbl_cn_mem_data *mem_data)
static void cn_mem_buf_destroy(struct hbl_cn_mem_buf *buf)
{
+ trace_habanalabs_cn_mem_destroy(buf->ctx->hdev->dev, buf->mem_id, buf->handle,
+ (u64)buf->kernel_address, buf->bus_address, buf->device_va,
+ buf->mappable_size);
+
if (buf->device_va)
hbl_cn_unmap_vmalloc_range(buf->ctx, buf->device_va, buf->mappable_size);
diff --git a/include/trace/events/habanalabs_cn.h b/include/trace/events/habanalabs_cn.h
new file mode 100644
index 000000000000..aca962cf3130
--- /dev/null
+++ b/include/trace/events/habanalabs_cn.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2023 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM habanalabs_cn
+
+#if !defined(_TRACE_HABANALABS_CN_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_HABANALABS_CN_H
+
+#include <linux/tracepoint.h>
+
+DECLARE_EVENT_CLASS(habanalabs_cn_mem_template,
+ TP_PROTO(struct device *dev, u32 mem_id, u64 handle, u64 kernel_addr, u64 bus_addr,
+ u64 device_va, size_t size),
+
+ TP_ARGS(dev, mem_id, handle, kernel_addr, bus_addr, device_va, size),
+
+ TP_STRUCT__entry(
+ __string(dname, dev_name(dev))
+ __field(u32, mem_id)
+ __field(u64, handle)
+ __field(u64, kernel_addr)
+ __field(u64, bus_addr)
+ __field(u64, device_va)
+ __field(u32, size)
+ ),
+
+ TP_fast_assign(
+ __assign_str(dname);
+ __entry->mem_id = mem_id;
+ __entry->handle = handle;
+ __entry->kernel_addr = kernel_addr;
+ __entry->bus_addr = bus_addr;
+ __entry->device_va = device_va;
+ __entry->size = size;
+ ),
+
+ TP_printk("%s: mem_id: %#x, handle: %#llx, kernel_addr: %#llx, bus_addr: %#llx, device_va: %#llx, size: %#x",
+ __get_str(dname),
+ __entry->mem_id,
+ __entry->handle,
+ __entry->kernel_addr,
+ __entry->bus_addr,
+ __entry->device_va,
+ __entry->size)
+);
+
+DEFINE_EVENT(habanalabs_cn_mem_template, habanalabs_cn_mem_alloc,
+ TP_PROTO(struct device *dev, u32 mem_id, u64 handle, u64 kernel_addr, u64 bus_addr,
+ u64 device_va, size_t size),
+ TP_ARGS(dev, mem_id, handle, kernel_addr, bus_addr, device_va, size));
+
+DEFINE_EVENT(habanalabs_cn_mem_template, habanalabs_cn_mem_destroy,
+ TP_PROTO(struct device *dev, u32 mem_id, u64 handle, u64 kernel_addr, u64 bus_addr,
+ u64 device_va, size_t size),
+ TP_ARGS(dev, mem_id, handle, kernel_addr, bus_addr, device_va, size));
+
+DECLARE_EVENT_CLASS(habanalabs_cn_dma_alloc_template,
+ TP_PROTO(struct device *dev, u64 cpu_addr, u64 dma_addr, size_t size, const char *caller),
+
+ TP_ARGS(dev, cpu_addr, dma_addr, size, caller),
+
+ TP_STRUCT__entry(
+ __string(dname, dev_name(dev))
+ __field(u64, cpu_addr)
+ __field(u64, dma_addr)
+ __field(u32, size)
+ __field(const char *, caller)
+ ),
+
+ TP_fast_assign(
+ __assign_str(dname);
+ __entry->cpu_addr = cpu_addr;
+ __entry->dma_addr = dma_addr;
+ __entry->size = size;
+ __entry->caller = caller;
+ ),
+
+ TP_printk("%s: cpu_addr: %#llx, dma_addr: %#llx, size: %#x, caller: %s",
+ __get_str(dname),
+ __entry->cpu_addr,
+ __entry->dma_addr,
+ __entry->size,
+ __entry->caller
+ )
+);
+
+DEFINE_EVENT(habanalabs_cn_dma_alloc_template, habanalabs_cn_dma_alloc_coherent,
+ TP_PROTO(struct device *dev, u64 cpu_addr, u64 dma_addr, size_t size,
+ const char *caller),
+ TP_ARGS(dev, cpu_addr, dma_addr, size, caller));
+
+DEFINE_EVENT(habanalabs_cn_dma_alloc_template, habanalabs_cn_dma_free_coherent,
+ TP_PROTO(struct device *dev, u64 cpu_addr, u64 dma_addr, size_t size,
+ const char *caller),
+ TP_ARGS(dev, cpu_addr, dma_addr, size, caller));
+
+DEFINE_EVENT(habanalabs_cn_dma_alloc_template, habanalabs_cn_dma_pool_zalloc,
+ TP_PROTO(struct device *dev, u64 cpu_addr, u64 dma_addr, size_t size,
+ const char *caller),
+ TP_ARGS(dev, cpu_addr, dma_addr, size, caller));
+
+DEFINE_EVENT(habanalabs_cn_dma_alloc_template, habanalabs_cn_dma_pool_free,
+ TP_PROTO(struct device *dev, u64 cpu_addr, u64 dma_addr, size_t size,
+ const char *caller),
+ TP_ARGS(dev, cpu_addr, dma_addr, size, caller));
+
+#endif /* if !defined(_TRACE_HABANALABS_CN_H) || defined(TRACE_HEADER_MULTI_READ) */
+
+/* This part must be outside protection */
+#include <trace/define_trace.h>
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* [PATCH 06/15] net: hbl_cn: debugfs support
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
` (4 preceding siblings ...)
2024-06-13 8:21 ` [PATCH 05/15] net: hbl_cn: memory trace events Omer Shpigelman
@ 2024-06-13 8:21 ` Omer Shpigelman
2024-06-19 18:35 ` Sunil Kovvuri Goutham
2024-06-13 8:22 ` [PATCH 07/15] net: hbl_cn: gaudi2: ASIC register header files Omer Shpigelman
` (10 subsequent siblings)
16 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:21 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
Add debugfs files for advanced settings, debug options and testing.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
.../ABI/testing/debugfs-driver-habanalabs_cn | 195 +++
MAINTAINERS | 1 +
drivers/net/ethernet/intel/hbl_cn/Makefile | 2 +
.../net/ethernet/intel/hbl_cn/common/hbl_cn.c | 4 +
.../net/ethernet/intel/hbl_cn/common/hbl_cn.h | 37 +
.../intel/hbl_cn/common/hbl_cn_debugfs.c | 1457 +++++++++++++++++
.../ethernet/intel/hbl_cn/common/hbl_cn_drv.c | 19 +-
7 files changed, 1714 insertions(+), 1 deletion(-)
create mode 100644 Documentation/ABI/testing/debugfs-driver-habanalabs_cn
create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_debugfs.c
diff --git a/Documentation/ABI/testing/debugfs-driver-habanalabs_cn b/Documentation/ABI/testing/debugfs-driver-habanalabs_cn
new file mode 100644
index 000000000000..5de689b0986d
--- /dev/null
+++ b/Documentation/ABI/testing/debugfs-driver-habanalabs_cn
@@ -0,0 +1,195 @@
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_accumulate_fec_duration
+Date: May 2024
+KernelVersion: N/A
+Contact: kvabhilash@habana.ai
+Description: Time (in ms) to accumulate FEC errors for. This is used as
+ divisor in calculation of pre & post FEC (Forward Error
+ Correction) SER (Symbol Error Rate).
+ Valid values are from 1 to ACCUMULATE_FEC_STATS_DURATION_MS_MAX.
+ Default value is ACCUMULATE_FEC_STATS_DURATION_MS.
+ Usage: echo <time_ms> > nic_accumulate_fec_duration
+ cat nic_accumulate_fec_duration
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_disable_decap
+Date: May 2024
+KernelVersion: 6.9
+Contact: gkgurumurthy@habana.ai
+Description: Allows the root user to enable/disable the decapsulation logic
+ on the RX path.
+ '1' disables the logic, '0' enables the logic.
+ The typical use case is to disable the decap on rx with encap
+ enabled on the tx, and run the RDMA traffic. This causes the
+ packets to be forwarded to ethernet ring which is ultimately
+ sent to linux kernel. The user can analyze the RDMA packet using
+ tcpdump and validate the encapsulation header.
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_inject_rx_err
+Date: May 2024
+KernelVersion: 6.9
+Contact: akishore@habana.ai
+Description: Allows the root user to force RX packet drop.
+ Usage: echo <drop_percent> > nic_inject_rx_err
+ cat nic_inject_rx_err
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_mac_lane_remap
+Date: May 2024
+KernelVersion: 6.9
+Contact: akishore@habana.ai
+Description: Allows root user to change MAC to PHY lane mapping. User should
+ provide space separated bitmap for all lanes on all NIC macros.
+ Usage: echo macro0 macro1 macro2 ... macroX > nic_mac_lane_remap
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_mac_loopback
+Date: May 2024
+KernelVersion: 6.9
+Contact: oshpigelman@habana.ai
+Description: Allows the root user to disable/enable MAC loopback for each NIC
+ port. The ports will function as if a physical loopback
+ transceiver was connected. A bitmask should be provided where
+ each bit represents a port.
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_mmu_bypass
+Date: May 2024
+KernelVersion: 6.9
+Contact: zyehudai@habana.ai
+Description: Sets the NIC to use MMU bypass for its allocated data structure.
+ Value of "0" is for disable, otherwise enable.
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_nrz_tx_taps
+Date: May 2024
+KernelVersion: 6.9
+Contact: sozeri@habana.ai
+Description: Allows the root user to set and show the NRZ Tx taps for the
+ port lanes. The lanes indices are 0-47.
+ Acceptable input string form:
+ <lane> <tx_pre2> <tx_pre1> <tx_main> <tx_post1> <tx_post2>.
+ cat nic_nrz_tx_taps will dump all taps.
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_override_port_status
+Date: May 2024
+KernelVersion: 6.9
+Contact: aagranovich@habana.ai
+Description: Allows the root user to force set ports link status.
+ Usage: echo <port> <status> > nic_override_port_status
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_pam4_tx_taps
+Date: May 2024
+KernelVersion: 6.9
+Contact: oshpigelman@habana.ai
+Description: Allows the root user to set and show the PAM4 Tx taps for the
+ port lanes. The lanes indices are 0-47.
+ Acceptable input string form:
+ <lane> <tx_pre2> <tx_pre1> <tx_main> <tx_post1> <tx_post2>.
+ cat nic_pam4_tx_taps will dump all taps.
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_phy_calc_ber
+Date: May 2024
+KernelVersion: 6.9
+Contact: sozeri@habana.ai
+Description: Allows the root user to enable calculation of PHY BER during the
+ PHY power_up flow.
+ value "0" is for disable, otherwise enable.
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_phy_calc_ber_wait_sec
+Date: May 2024
+KernelVersion: 6.9
+Contact: sozeri@habana.ai
+Description: Allows the root user to set the waiting time in seconds before
+ BER calculating.
+ Usage: echo <time_in_seconds> > nic_phy_calc_ber_wait_sec
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_phy_dump_serdes_params
+Date: May 2024
+KernelVersion: 6.9
+Contact: sozeri@habana.ai
+Description: Allows the root user to dump serdes parameters for a given port.
+ Need to write the port and then read it in order to dump the
+ parameters.
+ Usage: echo <port> > nic_phy_dump_serdes_params
+ cat nic_phy_dump_serdes_params
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_phy_force_first_tx_taps_cfg
+Date: May 2024
+KernelVersion: 6.9
+Contact: sozeri@habana.ai
+Description: Allows the root user to determine that every PHY power-up will
+ set the first Tx taps cfg instead of the current one.
+ Usage: echo 1 > nic_phy_force_first_tx_taps_cfg
+ cat nic_phy_force_first_tx_taps_cfg
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_phy_regs_print
+Date: May 2024
+KernelVersion: 6.9
+Contact: sozeri@habana.ai
+Description: Allows the root user to dump all PHY registers reads/writes
+ during the PHY power_up flow.
+ value "0" is for disable, otherwise enable.
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_phy_set_nrz
+Date: May 2024
+KernelVersion: 6.9
+Contact: sozeri@habana.ai
+Description: Allows the root user to set/unset NRZ mode (25Gbps speed).
+ Usage: echo 0/1 > nic_phy_set_nrz
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_polarity
+Date: May 2024
+KernelVersion: 6.9
+Contact: oshpigelman@habana.ai
+Description: Allows the root user to set the polarity for the port lanes.
+ The lanes indices are 0-47.
+ Acceptable input string form: <lane> <pol_tx> <pol_rx>.
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_print_fec_stats
+Date: May 2024
+KernelVersion: 6.9
+Contact: sozeri@habana.ai
+Description: Allows the root user to dump the FEC stats for all NIC ports to
+ dmesg.
+ Usage: cat nic_print_fec_stats
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_qp
+Date: May 2024
+KernelVersion: 6.9
+Contact: oshpigelman@habana.ai
+Description: Read a QP (Queue Pair) HW structure content. Need to write the
+ QP number, port, type and other flags to the file and then read
+ it in order to dump the QP content.
+ Input form: <port> <qpn> <is_req> <is_full_print> <force_read>.
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_rand_status
+Date: May 2024
+KernelVersion: 6.9
+Contact: oshpigelman@habana.ai
+Description: Enable randomization for the values returned in the NIC status
+ packet. Value of "0" is for disable, otherwise enable.
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_reset_cnt
+Date: May 2024
+KernelVersion: 6.9
+Contact: oshpigelman@habana.ai
+Description: Resets nic counters. Any decimal value is a valid input.
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_show_internal_ports_status
+Date: May 2024
+KernelVersion: 6.9
+Contact: sozeri@habana.ai
+Description: Allows the root user to read the link status of all internal
+ NIC ports.
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_wqe
+Date: May 2024
+KernelVersion: 6.9
+Contact: zyehudai@habana.ai
+Description: Read a WQE (Work Queue Entry) HW structure content. Need to
+ write the port, QP number, WQE index and it's type to the file
+ and then read it in order to dump the WQE content.
+ Input form: <port> <qpn> <wqe_idx> <is_tx>.
+
+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_wqe_index_checker
+Date: May 2024
+KernelVersion: 6.9
+Contact: dmeriin@habana.ai
+Description: Allows the root user to enable/disable the WQE index checker.
+ value "0" is for disable, otherwise enable.
+ Usage: echo <enable> > nic_wqe_index_checker
diff --git a/MAINTAINERS b/MAINTAINERS
index e948e33e990d..906224204aba 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9610,6 +9610,7 @@ L: netdev@vger.kernel.org
L: linux-rdma@vger.kernel.org
S: Supported
W: https://www.habana.ai
+F: Documentation/ABI/testing/debugfs-driver-habanalabs_cn
F: Documentation/networking/device_drivers/ethernet/intel/hbl.rst
F: drivers/net/ethernet/intel/hbl_cn/
F: include/linux/habanalabs/
diff --git a/drivers/net/ethernet/intel/hbl_cn/Makefile b/drivers/net/ethernet/intel/hbl_cn/Makefile
index 84ee2a6d7c3b..c2c4142f18a0 100644
--- a/drivers/net/ethernet/intel/hbl_cn/Makefile
+++ b/drivers/net/ethernet/intel/hbl_cn/Makefile
@@ -7,3 +7,5 @@ obj-$(CONFIG_HABANA_CN) := habanalabs_cn.o
include $(src)/common/Makefile
habanalabs_cn-y += $(HBL_CN_COMMON_FILES)
+
+habanalabs_cn-$(CONFIG_DEBUG_FS) += common/hbl_cn_debugfs.o
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
index 4e910b2cb8ac..fc7bd6474404 100644
--- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
@@ -1842,6 +1842,8 @@ int hbl_cn_dev_init(struct hbl_cn_device *hdev)
hbl_cn_late_init(hdev);
+ hbl_cn_debugfs_dev_init(hdev);
+
hdev->is_initialized = true;
return 0;
@@ -1878,6 +1880,8 @@ void hbl_cn_dev_fini(struct hbl_cn_device *hdev)
hbl_cn_stop(hdev->cn_aux_dev);
}
+ hbl_cn_debugfs_dev_fini(hdev);
+
hbl_cn_late_fini(hdev);
hbl_cn_ib_aux_drv_fini(hdev);
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.h b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.h
index 27139e93d990..0b96cd3db719 100644
--- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.h
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.h
@@ -142,6 +142,34 @@
#define hbl_cn_dma_pool_free(hdev, vaddr, dma_addr) \
__hbl_cn_dma_pool_free(hdev, vaddr, dma_addr, __func__)
+/* CN debugfs files enum */
+enum hbl_cn_debugfs_files_idx {
+ NIC_MAC_LOOPBACK = 0,
+ NIC_PAM4_TX_TAPS,
+ NIC_NRZ_TX_TAPS,
+ NIC_POLARITY,
+ NIC_QP,
+ NIC_WQE,
+ NIC_RESET_CNT,
+ NIC_MAC_LANE_REMAP,
+ NIC_RAND_STATUS,
+ NIC_MMU_BYPASS,
+ NIC_ETH_LOOPBACK,
+ NIC_PHY_REGS_PRINT,
+ NIC_SHOW_INTERNAL_PORTS_STATUS,
+ NIC_PRINT_FEC_STATS,
+ NIC_DISABLE_DECAP,
+ NIC_PHY_SET_NRZ,
+ NIC_PHY_DUMP_SERDES_PARAMS,
+ NIC_INJECT_RX_ERR,
+ NIC_PHY_CALC_BER,
+ NIC_PHY_CALC_BER_WAIT_SEC,
+ NIC_OVERRIDE_PORT_STATUS,
+ NIC_WQE_INDEX_CHECKER,
+ NIC_ACCUMULATE_FEC_DURATION,
+ NIC_PHY_FORCE_FIRST_TX_TAPS_CFG,
+};
+
extern struct hbl_cn_stat hbl_cn_mac_fec_stats[];
extern struct hbl_cn_stat hbl_cn_mac_stats_rx[];
extern struct hbl_cn_stat hbl_cn_mac_stats_tx[];
@@ -1312,6 +1340,7 @@ struct hbl_cn_properties {
* struct hbl_cn_device - habanalabs CN device structure.
* @pdev: pointer to PCI device.
* @dev: related kernel basic device structure.
+ * @cn_dentry: CN debugfs root dentry.
* @cpucp_info: FW info.
* @asic_funcs: ASIC specific functions that can be called from common code.
* @phy_tx_taps: array that holds all PAM4 Tx taps of all lanes.
@@ -1341,6 +1370,7 @@ struct hbl_cn_properties {
* @mac_loopback: enable MAC loopback on specific ports.
* @dram_size: available DRAM size.
* @mmap_type_flag: flag to indicate NIC MMAP type.
+ * @debugfs_supp_mask: mask of supported debugfs files.
* @pol_tx_mask: bitmap of tx polarity for all lanes.
* @pol_rx_mask: bitmap of rx polarity for all lanes.
* @device_timeout: device access timeout in usec.
@@ -1411,6 +1441,7 @@ struct hbl_cn_properties {
struct hbl_cn_device {
struct pci_dev *pdev;
struct device *dev;
+ struct dentry *cn_dentry;
struct hbl_cn_cpucp_info *cpucp_info;
struct hbl_cn_asic_funcs *asic_funcs;
struct hbl_cn_tx_taps *phy_tx_taps;
@@ -1441,6 +1472,7 @@ struct hbl_cn_device {
u64 mac_loopback;
u64 dram_size;
u64 mmap_type_flag;
+ u64 debugfs_supp_mask;
u64 pol_tx_mask;
u64 pol_rx_mask;
u32 device_timeout;
@@ -1534,6 +1566,8 @@ void hbl_cn_phy_set_port_status(struct hbl_cn_port *cn_port, bool up);
int hbl_cn_read_spmu_counters(struct hbl_cn_port *cn_port, u64 out_data[], u32 *num_out_data);
int hbl_cn_qp_modify(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp,
enum hbl_cn_qp_state new_state, void *params);
+void hbl_cn_debugfs_dev_init(struct hbl_cn_device *hdev);
+void hbl_cn_debugfs_dev_fini(struct hbl_cn_device *hdev);
u32 hbl_cn_get_max_qp_id(struct hbl_cn_port *cn_port);
bool hbl_cn_is_port_open(struct hbl_cn_port *cn_port);
u32 hbl_cn_get_pflags(struct hbl_cn_port *cn_port);
@@ -1614,6 +1648,9 @@ int __hbl_cn_ports_reopen(struct hbl_cn_device *hdev);
void __hbl_cn_hard_reset_prepare(struct hbl_cn_device *hdev, bool fw_reset, bool in_teardown);
void __hbl_cn_stop(struct hbl_cn_device *hdev);
+void __init hbl_cn_debugfs_init(void);
+void hbl_cn_debugfs_fini(void);
+
/* DMA memory allocations */
void *__hbl_cn_dma_alloc_coherent(struct hbl_cn_device *hdev, size_t size, dma_addr_t *dma_handle,
gfp_t flag, const char *caller);
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_debugfs.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_debugfs.c
new file mode 100644
index 000000000000..b13da28fdcb7
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_debugfs.c
@@ -0,0 +1,1457 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "hbl_cn.h"
+
+#ifdef CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include <linux/module.h>
+#include <linux/nospec.h>
+
+#define POLARITY_KBUF_SIZE 8
+#define TX_TAPS_KBUF_SIZE 25
+#define KBUF_IN_SIZE 18
+#define KBUF_OUT_SIZE BIT(12)
+#define KBUF_OUT_BIG_SIZE BIT(14)
+#define MAC_LANE_REMAP_READ_SIZE 10
+#define MAX_INT_PORT_STS_KBUF_SIZE 20
+#define HBL_CN_DEBUGFS_CREATE_FILE(op, perm, dir, dev, fops) \
+ do { \
+ enum hbl_cn_debugfs_files_idx __op = op; \
+ if (hdev->debugfs_supp_mask & BIT(__op)) \
+ debugfs_create_file(hbl_cn_debugfs_names[__op], perm, dir, dev, fops); \
+ } while (0)
+
+#define HBL_CN_DEBUGFS_CREATE_U8(op, perm, dir, fops) \
+ do { \
+ enum hbl_cn_debugfs_files_idx __op = op; \
+ if (hdev->debugfs_supp_mask & BIT(__op)) \
+ debugfs_create_u8(hbl_cn_debugfs_names[__op], perm, dir, fops); \
+ } while (0)
+
+#define HBL_CN_DEBUGFS_CREATE_U16(op, perm, dir, fops) \
+ do { \
+ enum hbl_cn_debugfs_files_idx __op = op; \
+ if (hdev->debugfs_supp_mask & BIT(__op)) \
+ debugfs_create_u16(hbl_cn_debugfs_names[__op], perm, dir, fops); \
+ } while (0)
+
+static char hbl_cn_debugfs_names[][NAME_MAX] = {
+ [NIC_MAC_LOOPBACK] = "nic_mac_loopback",
+ [NIC_PAM4_TX_TAPS] = "nic_pam4_tx_taps",
+ [NIC_NRZ_TX_TAPS] = "nic_nrz_tx_taps",
+ [NIC_POLARITY] = "nic_polarity",
+ [NIC_QP] = "nic_qp",
+ [NIC_WQE] = "nic_wqe",
+ [NIC_RESET_CNT] = "nic_reset_cnt",
+ [NIC_MAC_LANE_REMAP] = "nic_mac_lane_remap",
+ [NIC_RAND_STATUS] = "nic_rand_status",
+ [NIC_MMU_BYPASS] = "nic_mmu_bypass",
+ [NIC_ETH_LOOPBACK] = "nic_eth_loopback",
+ [NIC_PHY_REGS_PRINT] = "nic_phy_regs_print",
+ [NIC_SHOW_INTERNAL_PORTS_STATUS] = "nic_show_internal_ports_status",
+ [NIC_PRINT_FEC_STATS] = "nic_print_fec_stats",
+ [NIC_DISABLE_DECAP] = "nic_disable_decap",
+ [NIC_PHY_SET_NRZ] = "nic_phy_set_nrz",
+ [NIC_PHY_DUMP_SERDES_PARAMS] = "nic_phy_dump_serdes_params",
+ [NIC_INJECT_RX_ERR] = "nic_inject_rx_err",
+ [NIC_PHY_CALC_BER] = "nic_phy_calc_ber",
+ [NIC_PHY_CALC_BER_WAIT_SEC] = "nic_phy_calc_ber_wait_sec",
+ [NIC_OVERRIDE_PORT_STATUS] = "nic_override_port_status",
+ [NIC_WQE_INDEX_CHECKER] = "nic_wqe_index_checker",
+ [NIC_ACCUMULATE_FEC_DURATION] = "nic_accumulate_fec_duration",
+ [NIC_PHY_FORCE_FIRST_TX_TAPS_CFG] = "nic_phy_force_first_tx_taps_cfg",
+};
+
+static struct dentry *hbl_cn_debug_root;
+
+static int hbl_device_hard_reset_sync(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ ktime_t timeout;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ aux_ops->device_reset(aux_dev);
+
+ timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * 1000ull);
+ while (!hbl_cn_comp_device_operational(hdev) && !READ_ONCE(hdev->in_teardown)) {
+ ssleep(1);
+ if (ktime_compare(ktime_get(), timeout) > 0) {
+ dev_crit(hdev->dev, "Timed out waiting for hard reset to finish\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+static ssize_t debugfs_print_value_to_buffer(void *buf, size_t count, loff_t *ppos, char *fmt,
+ u32 val)
+{
+ size_t fmt_len = strlen(fmt);
+ char tmp_fmt[32] = {0};
+ char tmp[32] = {0};
+
+ if (*ppos)
+ return 0;
+
+ if (fmt_len > sizeof(tmp_fmt) - 2)
+ return -ENOMEM;
+
+ strscpy(tmp_fmt, fmt, sizeof(tmp_fmt));
+
+ tmp_fmt[fmt_len] = '\n';
+ tmp_fmt[fmt_len + 1] = '\0';
+
+ snprintf(tmp, sizeof(tmp), tmp_fmt, val);
+
+ return simple_read_from_buffer(buf, count, ppos, tmp, strlen(tmp) + 1);
+}
+
+static ssize_t debugfs_pam4_tx_taps_write(struct file *f, const char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ s32 tx_pre2, tx_pre1, tx_main, tx_post1, tx_post2, *taps;
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ char kbuf[TX_TAPS_KBUF_SIZE] = {0};
+ u32 lane, max_num_of_lanes;
+ char *c1, *c2;
+ ssize_t rc;
+
+ max_num_of_lanes = hdev->cn_props.max_num_of_lanes;
+
+ if (count > sizeof(kbuf) - 1)
+ goto err;
+ if (copy_from_user(kbuf, buf, count))
+ goto err;
+ kbuf[count] = '\0';
+
+ c1 = kbuf;
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtou32(c1, 10, &lane);
+ if (rc)
+ goto err;
+
+ if (lane >= max_num_of_lanes) {
+ dev_err(hdev->dev, "lane max value is %d\n", max_num_of_lanes - 1);
+ return -EINVAL;
+ }
+
+ /* Turn off speculation due to Spectre vulnerability */
+ lane = array_index_nospec(lane, max_num_of_lanes);
+
+ c1 = c2 + 1;
+
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtos32(c1, 10, &tx_pre2);
+ if (rc)
+ goto err;
+
+ c1 = c2 + 1;
+
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtos32(c1, 10, &tx_pre1);
+ if (rc)
+ goto err;
+
+ c1 = c2 + 1;
+
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtos32(c1, 10, &tx_main);
+ if (rc)
+ goto err;
+
+ c1 = c2 + 1;
+
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtos32(c1, 10, &tx_post1);
+ if (rc)
+ goto err;
+
+ c1 = c2 + 1;
+
+ rc = kstrtos32(c1, 10, &tx_post2);
+ if (rc)
+ goto err;
+
+ taps = hdev->phy_tx_taps[lane].pam4_taps;
+ taps[0] = tx_pre2;
+ taps[1] = tx_pre1;
+ taps[2] = tx_main;
+ taps[3] = tx_post1;
+ taps[4] = tx_post2;
+
+ return count;
+err:
+ dev_err(hdev->dev,
+ "usage: echo <lane> <tx_pre2> <tx_pre1> <tx_main> <tx_post1> <tx_post2> > nic_pam4_tx_taps\n");
+
+ return -EINVAL;
+}
+
+static ssize_t debugfs_pam4_tx_taps_read(struct file *f, char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ u32 lane, max_num_of_lanes;
+ ssize_t rc, len;
+ char *kbuf;
+ s32 *taps;
+
+ max_num_of_lanes = hdev->cn_props.max_num_of_lanes;
+
+ if (*ppos)
+ return 0;
+
+ kbuf = kzalloc(KBUF_OUT_SIZE, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ sprintf(kbuf + strlen(kbuf), "PAM4 tx taps:\n");
+
+ for (lane = 0; lane < max_num_of_lanes; lane++) {
+ taps = hdev->phy_tx_taps[lane].pam4_taps;
+ len = strlen(kbuf);
+ if ((KBUF_OUT_SIZE - len) <= 1) {
+ rc = -EFBIG;
+ goto out;
+ }
+ snprintf(kbuf + len, KBUF_OUT_SIZE - len, "lane %u: %d %d %d %d %d\n", lane,
+ taps[0], taps[1], taps[2], taps[3], taps[4]);
+ }
+
+ rc = simple_read_from_buffer(buf, count, ppos, kbuf, strlen(kbuf) + 1);
+
+out:
+ kfree(kbuf);
+
+ return rc;
+}
+
+static const struct file_operations debugfs_pam4_tx_taps_fops = {
+ .owner = THIS_MODULE,
+ .write = debugfs_pam4_tx_taps_write,
+ .read = debugfs_pam4_tx_taps_read,
+};
+
+static ssize_t debugfs_nrz_tx_taps_write(struct file *f, const char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ s32 tx_pre2, tx_pre1, tx_main, tx_post1, tx_post2, *taps;
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ char kbuf[TX_TAPS_KBUF_SIZE] = {0};
+ u32 lane, max_num_of_lanes;
+ char *c1, *c2;
+ ssize_t rc;
+
+ max_num_of_lanes = hdev->cn_props.max_num_of_lanes;
+
+ if (count > sizeof(kbuf) - 1)
+ goto err;
+ if (copy_from_user(kbuf, buf, count))
+ goto err;
+ kbuf[count] = '\0';
+
+ c1 = kbuf;
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtou32(c1, 10, &lane);
+ if (rc)
+ goto err;
+
+ if (lane >= max_num_of_lanes) {
+ dev_err(hdev->dev, "lane max value is %d\n", max_num_of_lanes - 1);
+ return -EINVAL;
+ }
+
+ /* Turn off speculation due to Spectre vulnerability */
+ lane = array_index_nospec(lane, max_num_of_lanes);
+
+ c1 = c2 + 1;
+
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtos32(c1, 10, &tx_pre2);
+ if (rc)
+ goto err;
+
+ c1 = c2 + 1;
+
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtos32(c1, 10, &tx_pre1);
+ if (rc)
+ goto err;
+
+ c1 = c2 + 1;
+
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtos32(c1, 10, &tx_main);
+ if (rc)
+ goto err;
+
+ c1 = c2 + 1;
+
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtos32(c1, 10, &tx_post1);
+ if (rc)
+ goto err;
+
+ c1 = c2 + 1;
+
+ rc = kstrtos32(c1, 10, &tx_post2);
+ if (rc)
+ goto err;
+
+ taps = hdev->phy_tx_taps[lane].nrz_taps;
+ taps[0] = tx_pre2;
+ taps[1] = tx_pre1;
+ taps[2] = tx_main;
+ taps[3] = tx_post1;
+ taps[4] = tx_post2;
+
+ return count;
+err:
+ dev_err(hdev->dev,
+ "usage: echo <lane> <tx_pre2> <tx_pre1> <tx_main> <tx_post1> <tx_post2> > nic_nrz_tx_taps\n");
+
+ return -EINVAL;
+}
+
+static ssize_t debugfs_nrz_tx_taps_read(struct file *f, char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ u32 lane, max_num_of_lanes;
+ ssize_t rc, len;
+ char *kbuf;
+ s32 *taps;
+
+ max_num_of_lanes = hdev->cn_props.max_num_of_lanes;
+
+ if (*ppos)
+ return 0;
+
+ kbuf = kzalloc(KBUF_OUT_SIZE, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ sprintf(kbuf + strlen(kbuf), "NRZ tx taps:\n");
+
+ for (lane = 0; lane < max_num_of_lanes; lane++) {
+ taps = hdev->phy_tx_taps[lane].nrz_taps;
+ len = strlen(kbuf);
+ if ((KBUF_OUT_SIZE - len) <= 1) {
+ rc = -EFBIG;
+ goto out;
+ }
+ snprintf(kbuf + len, KBUF_OUT_SIZE - len, "lane %u: %d %d %d %d %d\n", lane,
+ taps[0], taps[1], taps[2], taps[3], taps[4]);
+ }
+
+ rc = simple_read_from_buffer(buf, count, ppos, kbuf, strlen(kbuf) + 1);
+
+out:
+ kfree(kbuf);
+
+ return rc;
+}
+
+static const struct file_operations debugfs_nrz_tx_taps_fops = {
+ .owner = THIS_MODULE,
+ .write = debugfs_nrz_tx_taps_write,
+ .read = debugfs_nrz_tx_taps_read,
+};
+
+static ssize_t debugfs_polarity_write(struct file *f, const char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ char kbuf[POLARITY_KBUF_SIZE] = {0};
+ u32 lane, max_num_of_lanes;
+ u8 pol_tx, pol_rx;
+ char *c1, *c2;
+ ssize_t rc;
+ u64 val;
+
+ max_num_of_lanes = hdev->cn_props.max_num_of_lanes;
+
+ if (count > sizeof(kbuf) - 1)
+ goto err;
+ if (copy_from_user(kbuf, buf, count))
+ goto err;
+ kbuf[count] = '\0';
+
+ c1 = kbuf;
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtou32(c1, 10, &lane);
+ if (rc)
+ goto err;
+
+ if (lane >= max_num_of_lanes) {
+ dev_err(hdev->dev, "lane max value is %d\n", max_num_of_lanes - 1);
+ return -EINVAL;
+ }
+
+ c1 = c2 + 1;
+
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtou8(c1, 10, &pol_tx);
+ if (rc)
+ goto err;
+
+ c1 = c2 + 1;
+
+ rc = kstrtou8(c1, 10, &pol_rx);
+ if (rc)
+ goto err;
+
+ if ((pol_tx & ~1) || (pol_rx & ~1)) {
+ dev_err(hdev->dev, "pol_tx and pol_rx should be 0 or 1\n");
+ goto err;
+ }
+
+ val = hdev->pol_tx_mask;
+ val &= ~BIT_ULL(lane);
+ val |= ((u64)pol_tx) << lane;
+ hdev->pol_tx_mask = val;
+
+ val = hdev->pol_rx_mask;
+ val &= ~BIT_ULL(lane);
+ val |= ((u64)pol_rx) << lane;
+ hdev->pol_rx_mask = val;
+
+ /* This flag is set to prevent overwriting the new values after reset */
+ hdev->skip_phy_pol_cfg = true;
+
+ return count;
+err:
+ dev_err(hdev->dev, "usage: echo <lane> <pol_tx> <pol_rx> > nic_polarity\n");
+
+ return -EINVAL;
+}
+
+static const struct file_operations debugfs_polarity_fops = {
+ .owner = THIS_MODULE,
+ .write = debugfs_polarity_write,
+};
+
+static ssize_t debugfs_qp_read(struct file *f, char __user *buf, size_t count, loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ char *kbuf;
+ ssize_t rc;
+
+ asic_funcs = hdev->asic_funcs;
+
+ if (*ppos)
+ return 0;
+
+ kbuf = kzalloc(KBUF_OUT_SIZE, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ rc = asic_funcs->qp_read(hdev, &hdev->qp_info, kbuf, KBUF_OUT_SIZE);
+ if (rc)
+ goto out;
+
+ rc = simple_read_from_buffer(buf, count, ppos, kbuf, strlen(kbuf) + 1);
+
+out:
+ kfree(kbuf);
+
+ return rc;
+}
+
+static ssize_t debugfs_qp_write(struct file *f, const char __user *buf, size_t count, loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ struct hbl_cn_qp_info *qp_info = &hdev->qp_info;
+ u32 port, qpn, max_num_of_ports;
+ u8 req, full_print, force_read;
+ char kbuf[KBUF_IN_SIZE] = {0};
+ char *c1, *c2;
+ ssize_t rc;
+
+ max_num_of_ports = hdev->cn_props.max_num_of_ports;
+
+ if (count > sizeof(kbuf) - 1)
+ goto err;
+ if (copy_from_user(kbuf, buf, count))
+ goto err;
+ kbuf[count] = '\0';
+
+ c1 = kbuf;
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtou32(c1, 10, &port);
+ if (rc)
+ goto err;
+
+ if (port >= max_num_of_ports) {
+ dev_err(hdev->dev, "port max value is %d\n", max_num_of_ports - 1);
+ return -EINVAL;
+ }
+
+ c1 = c2 + 1;
+
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtou32(c1, 10, &qpn);
+ if (rc)
+ goto err;
+
+ c1 = c2 + 1;
+
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtou8(c1, 10, &req);
+ if (rc)
+ goto err;
+
+ if (req & ~1) {
+ dev_err(hdev->dev, "req should be 0 or 1\n");
+ goto err;
+ }
+
+ c1 = c2 + 1;
+
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtou8(c1, 10, &full_print);
+ if (rc)
+ goto err;
+
+ if (full_print & ~1) {
+ dev_err(hdev->dev, "full_print should be 0 or 1\n");
+ goto err;
+ }
+
+ c1 = c2 + 1;
+
+ /* may not be the last element due to the optional params */
+ c2 = strchr(c1, ' ');
+ if (c2)
+ *c2 = '\0';
+
+ rc = kstrtou8(c1, 10, &force_read);
+ if (rc)
+ goto err;
+
+ if (force_read & ~1) {
+ dev_err(hdev->dev, "force_read should be 0 or 1\n");
+ goto err;
+ }
+
+ qp_info->port = port;
+ qp_info->qpn = qpn;
+ qp_info->req = req;
+ qp_info->full_print = full_print;
+ qp_info->force_read = force_read;
+
+ return count;
+err:
+ dev_err(hdev->dev,
+ "usage: echo <port> <qpn> <is_req> <is_full_print> <force_read> [<exts_print>] > nic_qp\n");
+
+ return -EINVAL;
+}
+
+static const struct file_operations debugfs_qp_fops = {
+ .owner = THIS_MODULE,
+ .read = debugfs_qp_read,
+ .write = debugfs_qp_write
+};
+
+static ssize_t debugfs_wqe_read(struct file *f, char __user *buf, size_t count, loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ char *kbuf;
+ ssize_t rc;
+
+ asic_funcs = hdev->asic_funcs;
+
+ if (*ppos)
+ return 0;
+
+ kbuf = kzalloc(KBUF_OUT_SIZE, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ rc = asic_funcs->wqe_read(hdev, kbuf, KBUF_OUT_SIZE);
+ if (rc)
+ goto out;
+
+ rc = simple_read_from_buffer(buf, count, ppos, kbuf, strlen(kbuf) + 1);
+
+out:
+ kfree(kbuf);
+
+ return rc;
+}
+
+static ssize_t debugfs_wqe_write(struct file *f, const char __user *buf, size_t count, loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ struct hbl_cn_wqe_info *wqe_info = &hdev->wqe_info;
+ u32 port, qpn, wqe_idx, max_num_of_lanes;
+ char kbuf[KBUF_IN_SIZE] = {0};
+ char *c1, *c2;
+ ssize_t rc;
+ u8 tx;
+
+ max_num_of_lanes = hdev->cn_props.max_num_of_lanes;
+
+ if (count > sizeof(kbuf) - 1)
+ goto err;
+ if (copy_from_user(kbuf, buf, count))
+ goto err;
+ kbuf[count] = '\0';
+
+ c1 = kbuf;
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtou32(c1, 10, &port);
+ if (rc)
+ goto err;
+
+ if (port >= max_num_of_lanes) {
+ dev_err(hdev->dev, "port max value is %d\n", max_num_of_lanes - 1);
+ return -EINVAL;
+ }
+
+ c1 = c2 + 1;
+
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtou32(c1, 10, &qpn);
+ if (rc)
+ goto err;
+
+ c1 = c2 + 1;
+
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtou32(c1, 10, &wqe_idx);
+ if (rc)
+ goto err;
+
+ c1 = c2 + 1;
+
+ rc = kstrtou8(c1, 10, &tx);
+ if (rc)
+ goto err;
+
+ if (tx & ~1) {
+ dev_err(hdev->dev, "tx should be 0 or 1\n");
+ goto err;
+ }
+
+ wqe_info->port = port;
+ wqe_info->qpn = qpn;
+ wqe_info->wqe_idx = wqe_idx;
+ wqe_info->tx = tx;
+
+ return count;
+err:
+ dev_err(hdev->dev, "usage: echo <port> <qpn> <wqe_idx> <is_tx> > nic_wqe\n");
+
+ return -EINVAL;
+}
+
+static const struct file_operations debugfs_wqe_fops = {
+ .owner = THIS_MODULE,
+ .read = debugfs_wqe_read,
+ .write = debugfs_wqe_write
+};
+
+static ssize_t debugfs_reset_cnt_write(struct file *f, const char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ ssize_t rc;
+ u32 val;
+
+ rc = kstrtou32_from_user(buf, count, 10, &val);
+ if (rc)
+ return rc;
+
+ hbl_cn_reset_ports_toggle_counters(hdev);
+ hbl_cn_reset_stats_counters(hdev);
+
+ return count;
+}
+
+static const struct file_operations debugfs_reset_cnt_fops = {
+ .owner = THIS_MODULE,
+ .write = debugfs_reset_cnt_write
+};
+
+static int parse_user_mac_lane_remap_data(u32 *dest_arr, int *dest_arr_cnt, char *buf, int count)
+{
+ int i = 0, j = 0, rc;
+ int offset;
+ u32 val;
+
+ while (i < count) {
+ offset = strcspn(&buf[i], " ");
+ buf[i + offset] = '\0';
+
+ rc = kstrtou32(&buf[i], 16, &val);
+ if (rc)
+ return rc;
+
+ dest_arr[j++] = val;
+ i += (offset + 1);
+ }
+
+ *dest_arr_cnt = j;
+
+ return 0;
+}
+
+static ssize_t debugfs_mac_lane_remap_write(struct file *f, const char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ struct hbl_cn_properties *cn_props;
+ u32 *mac_lane_remap_buf;
+ int rc, n_parsed = 0;
+ char *kbuf;
+
+ cn_props = &hdev->cn_props;
+
+ kbuf = kcalloc(count + 1, sizeof(*buf), GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ mac_lane_remap_buf = kcalloc(cn_props->num_of_macros, sizeof(*mac_lane_remap_buf),
+ GFP_KERNEL);
+ if (!mac_lane_remap_buf) {
+ rc = -ENOMEM;
+ goto err_free_kbuf;
+ }
+
+ rc = copy_from_user(kbuf, buf, count);
+ if (rc)
+ goto err_free_mac_lane_remap_buf;
+
+ /* Add trailing space to simplify parsing user data. */
+ kbuf[count] = ' ';
+
+ rc = parse_user_mac_lane_remap_data(mac_lane_remap_buf, &n_parsed, kbuf, count + 1);
+ if (rc || n_parsed != cn_props->num_of_macros) {
+ rc = -EINVAL;
+ goto err_parse;
+ }
+
+ memcpy(hdev->mac_lane_remap, mac_lane_remap_buf,
+ sizeof(*mac_lane_remap_buf) * cn_props->num_of_macros);
+
+ rc = hbl_device_hard_reset_sync(hdev);
+ if (rc)
+ goto err_free_mac_lane_remap_buf;
+
+ kfree(mac_lane_remap_buf);
+ kfree(kbuf);
+
+ return count;
+err_parse:
+ dev_err_ratelimited(hdev->dev,
+ "usage: echo macro0 macro1 macro2 ... macroX > mac_lane_remap\n");
+err_free_mac_lane_remap_buf:
+ kfree(mac_lane_remap_buf);
+err_free_kbuf:
+ kfree(kbuf);
+ return -EINVAL;
+}
+
+static ssize_t debugfs_mac_lane_remap_read(struct file *f, char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ char kbuf[MAC_LANE_REMAP_READ_SIZE];
+ struct hbl_cn_properties *cn_props;
+ int i, j;
+
+ cn_props = &hdev->cn_props;
+
+ if (*ppos)
+ return 0;
+
+ for (i = 0, j = 0; i < cn_props->num_of_macros; i++, j += MAC_LANE_REMAP_READ_SIZE) {
+ memset(kbuf, 0, MAC_LANE_REMAP_READ_SIZE);
+ sprintf(kbuf, "0x%x ", hdev->mac_lane_remap[i]);
+
+ if (copy_to_user(&buf[j], kbuf, MAC_LANE_REMAP_READ_SIZE)) {
+ dev_err(hdev->dev, "error in copying lane info to user\n");
+ return -EFAULT;
+ }
+
+ *ppos += MAC_LANE_REMAP_READ_SIZE;
+ }
+
+ return j + 1;
+}
+
+static const struct file_operations debugfs_mac_lane_remap_fops = {
+ .owner = THIS_MODULE,
+ .write = debugfs_mac_lane_remap_write,
+ .read = debugfs_mac_lane_remap_read,
+};
+
+static ssize_t debugfs_eth_loopback_write(struct file *f, const char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ u32 val = 0;
+ int rc;
+
+ rc = kstrtou32_from_user(buf, count, 10, &val);
+ if (rc)
+ return rc;
+
+ hdev->eth_loopback = !!val;
+
+ dev_info(hdev->dev, "%s eth_loopback\n", hdev->eth_loopback ? "enable" : "disable");
+
+ return count;
+}
+
+static ssize_t debugfs_eth_loopback_read(struct file *f, char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+
+ return debugfs_print_value_to_buffer(buf, count, ppos, "%u", hdev->eth_loopback);
+}
+
+static const struct file_operations debugfs_eth_loopback_fops = {
+ .owner = THIS_MODULE,
+ .write = debugfs_eth_loopback_write,
+ .read = debugfs_eth_loopback_read,
+};
+
+static ssize_t debugfs_phy_regs_print_write(struct file *f, const char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ u32 val = 0;
+ int rc;
+
+ rc = kstrtou32_from_user(buf, count, 10, &val);
+ if (rc)
+ return rc;
+
+ hdev->phy_regs_print = !!val;
+
+ dev_info(hdev->dev, "%s printing PHY registers\n",
+ hdev->phy_regs_print ? "enable" : "disable");
+
+ return count;
+}
+
+static ssize_t debugfs_phy_regs_print_read(struct file *f, char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+
+ return debugfs_print_value_to_buffer(buf, count, ppos, "%u", hdev->phy_regs_print);
+}
+
+static const struct file_operations debugfs_phy_regs_print_fops = {
+ .owner = THIS_MODULE,
+ .write = debugfs_phy_regs_print_write,
+ .read = debugfs_phy_regs_print_read,
+};
+
+static ssize_t debugfs_show_internal_ports_status_read(struct file *f, char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ char kbuf[MAX_INT_PORT_STS_KBUF_SIZE];
+ struct hbl_cn_port *cn_port;
+ int i, cnt, total_cnt;
+
+ if (*ppos)
+ return 0;
+
+ total_cnt = 0;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)) || (hdev->ext_ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ memset(kbuf, 0, MAX_INT_PORT_STS_KBUF_SIZE);
+ cnt = sprintf(kbuf, "Port %-2u: %s\n",
+ cn_port->port, cn_port->pcs_link ? "UP" : "DOWN");
+
+ if (copy_to_user(&buf[total_cnt], kbuf, cnt)) {
+ dev_err(hdev->dev, "error in copying info to user\n");
+ return -EFAULT;
+ }
+
+ total_cnt += cnt;
+ *ppos += cnt;
+ }
+
+ if (!total_cnt) {
+ char *msg = "No internal ports found\n";
+
+ return simple_read_from_buffer(buf, count, ppos, msg, strlen(msg));
+ }
+
+ return total_cnt + 1;
+}
+
+static const struct file_operations debugfs_show_internal_ports_status_fops = {
+ .owner = THIS_MODULE,
+ .read = debugfs_show_internal_ports_status_read,
+};
+
+static ssize_t debugfs_print_fec_stats_read(struct file *f, char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ struct hbl_cn_port *cn_port;
+ char *kbuf;
+ int i, rc;
+
+ asic_funcs = hdev->asic_funcs;
+
+ if (*ppos)
+ return 0;
+
+ kbuf = kzalloc(KBUF_OUT_BIG_SIZE, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ sprintf(kbuf + strlen(kbuf), "Card %u FEC stats:\n", hdev->card_location);
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ asic_funcs->port_funcs->collect_fec_stats(cn_port, kbuf, KBUF_OUT_BIG_SIZE);
+ }
+
+ rc = simple_read_from_buffer(buf, count, ppos, kbuf, strlen(kbuf) + 1);
+
+ kfree(kbuf);
+
+ return rc;
+}
+
+static const struct file_operations debugfs_print_fec_stats_fops = {
+ .owner = THIS_MODULE,
+ .read = debugfs_print_fec_stats_read,
+};
+
+static ssize_t debugfs_phy_set_nrz_write(struct file *f, const char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ bool val;
+ int rc;
+
+ rc = kstrtobool_from_user(buf, count, &val);
+ if (rc)
+ return rc;
+
+ if (val == hdev->phy_set_nrz)
+ return count;
+
+ hdev->phy_set_nrz = val;
+ hdev->skip_phy_default_tx_taps_cfg = 0;
+
+ dev_info(hdev->dev, "%s NRZ mode\n", hdev->phy_set_nrz ? "Enable" : "Disable");
+
+ rc = hbl_device_hard_reset_sync(hdev);
+ if (rc)
+ return -EINVAL;
+
+ return count;
+}
+
+static const struct file_operations debugfs_phy_set_nrz_fops = {
+ .owner = THIS_MODULE,
+ .write = debugfs_phy_set_nrz_write,
+};
+
+static ssize_t debugfs_phy_dump_serdes_params_read(struct file *f, char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ char *kbuf;
+ ssize_t rc;
+
+ asic_funcs = hdev->asic_funcs;
+
+ if (*ppos)
+ return 0;
+
+ /* For ASICs that don't support this feature, return an error */
+ if (!asic_funcs->phy_dump_serdes_params)
+ return -EINVAL;
+
+ kbuf = kzalloc(KBUF_OUT_BIG_SIZE, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ asic_funcs->phy_dump_serdes_params(hdev, kbuf, KBUF_OUT_BIG_SIZE);
+
+ rc = simple_read_from_buffer(buf, count, ppos, kbuf, strlen(kbuf) + 1);
+
+ kfree(kbuf);
+
+ return rc;
+}
+
+static ssize_t debugfs_phy_dump_serdes_params_write(struct file *f, const char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ u32 port;
+ int rc;
+
+ asic_funcs = hdev->asic_funcs;
+
+ /* For ASICs that don't support this feature, return an error */
+ if (!asic_funcs->phy_dump_serdes_params)
+ return -EINVAL;
+
+ rc = kstrtou32_from_user(buf, count, 10, &port);
+ if (rc)
+ return rc;
+
+ if (port >= hdev->cn_props.max_num_of_ports) {
+ dev_err(hdev->dev, "Invalid port number %u\n", port);
+ return -EINVAL;
+ }
+
+ hdev->phy_port_to_dump = port;
+
+ return count;
+}
+
+static const struct file_operations debugfs_phy_dump_serdes_params_fops = {
+ .owner = THIS_MODULE,
+ .read = debugfs_phy_dump_serdes_params_read,
+ .write = debugfs_phy_dump_serdes_params_write,
+};
+
+static ssize_t debugfs_inject_rx_err_read(struct file *f, char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+
+ return debugfs_print_value_to_buffer(buf, count, ppos, "%u", hdev->rx_drop_percent);
+}
+
+static ssize_t debugfs_inject_rx_err_write(struct file *f, const char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ u32 val;
+ int rc;
+
+ asic_funcs = hdev->asic_funcs;
+
+ if (*ppos)
+ return 0;
+
+ rc = kstrtou32_from_user(buf, count, 10, &val);
+ if (rc)
+ return rc;
+
+ if (val > 100) {
+ dev_dbg_ratelimited(hdev->dev, "Invalid drop percentage %d\n", val);
+ return -EINVAL;
+ }
+
+ asic_funcs->inject_rx_err(hdev, val);
+
+ return count;
+}
+
+static const struct file_operations debugfs_inject_rx_err_fops = {
+ .owner = THIS_MODULE,
+ .read = debugfs_inject_rx_err_read,
+ .write = debugfs_inject_rx_err_write,
+};
+
+static ssize_t debugfs_override_port_status_write(struct file *f, const char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ char kbuf[KBUF_IN_SIZE] = {0};
+ struct hbl_cn_port *cn_port;
+ u32 port, max_num_of_ports;
+ char *c1, *c2;
+ ssize_t rc;
+ u8 up;
+
+ max_num_of_ports = hdev->cn_props.max_num_of_ports;
+
+ if (count > sizeof(kbuf) - 1)
+ goto err;
+ if (copy_from_user(kbuf, buf, count))
+ goto err;
+ kbuf[count] = '\0';
+
+ c1 = kbuf;
+ c2 = strchr(c1, ' ');
+ if (!c2)
+ goto err;
+ *c2 = '\0';
+
+ rc = kstrtou32(c1, 10, &port);
+ if (rc)
+ goto err;
+
+ if (port >= max_num_of_ports) {
+ dev_err(hdev->dev, "port max value is %d\n", max_num_of_ports - 1);
+ return -EINVAL;
+ }
+
+ /* Turn off speculation due to Spectre vulnerability */
+ port = array_index_nospec(port, max_num_of_ports);
+
+ c1 = c2 + 1;
+
+ rc = kstrtou8(c1, 10, &up);
+ if (rc)
+ goto err;
+
+ if (hdev->ports_mask & BIT(port)) {
+ cn_port = &hdev->cn_ports[port];
+
+ cn_port->pcs_link = !!up;
+ hbl_cn_phy_set_port_status(cn_port, !!up);
+ }
+
+ return count;
+err:
+ dev_err(hdev->dev, "usage: echo <port> <status> > nic_override_port_status\n");
+
+ return -EINVAL;
+}
+
+static const struct file_operations debugfs_override_port_status_fops = {
+ .owner = THIS_MODULE,
+ .write = debugfs_override_port_status_write,
+};
+
+static ssize_t debugfs_write_wqe_index_checker(struct file *f, const char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ u32 val;
+ int rc;
+
+ asic_funcs = hdev->asic_funcs;
+
+ /* For ASICs that don't support this feature, return an error */
+ if (!asic_funcs->set_wqe_index_checker)
+ return -EINVAL;
+
+ rc = kstrtou32_from_user(buf, count, 10, &val);
+ if (rc)
+ return rc;
+
+ rc = asic_funcs->set_wqe_index_checker(hdev, !!val);
+ if (rc)
+ return rc;
+
+ return count;
+}
+
+static ssize_t debugfs_read_wqe_index_checker(struct file *f, char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ struct hbl_cn_asic_funcs *asic_funcs;
+ u32 index_checker;
+
+ asic_funcs = hdev->asic_funcs;
+
+ if (!asic_funcs->get_wqe_index_checker)
+ return -EINVAL;
+
+ index_checker = asic_funcs->get_wqe_index_checker(hdev);
+
+ return debugfs_print_value_to_buffer(buf, count, ppos, "%u", index_checker);
+}
+
+static const struct file_operations debugfs_wqe_index_checker_fops = {
+ .owner = THIS_MODULE,
+ .write = debugfs_write_wqe_index_checker,
+ .read = debugfs_read_wqe_index_checker,
+};
+
+static ssize_t debugfs_accumulate_fec_duration_write(struct file *f, const char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ u32 val = 0;
+ int rc;
+
+ rc = kstrtou32_from_user(buf, count, 10, &val);
+ if (rc)
+ return rc;
+
+ if (!val || val > ACCUMULATE_FEC_STATS_DURATION_MS_MAX)
+ return -EINVAL;
+
+ hdev->accumulate_fec_duration = val;
+
+ return count;
+}
+
+static ssize_t debugfs_accumulate_fec_duration_read(struct file *f, char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+
+ return debugfs_print_value_to_buffer(buf, count, ppos, "%u",
+ hdev->accumulate_fec_duration);
+}
+
+static const struct file_operations debugfs_accumulate_fec_duration_fops = {
+ .owner = THIS_MODULE,
+ .write = debugfs_accumulate_fec_duration_write,
+ .read = debugfs_accumulate_fec_duration_read,
+};
+
+static ssize_t debugfs_mac_loopback_read(struct file *f, char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+
+ return debugfs_print_value_to_buffer(buf, count, ppos, "0x%llx", hdev->mac_loopback);
+}
+
+static ssize_t debugfs_mac_loopback_write(struct file *f, const char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct hbl_cn_device *hdev = file_inode(f)->i_private;
+ ssize_t ret;
+ u64 val;
+ int rc;
+
+ ret = kstrtoull_from_user(buf, count, 16, &val);
+ if (ret)
+ return ret;
+
+ if (val == hdev->mac_loopback)
+ return count;
+
+ hdev->mac_loopback = val;
+ rc = hbl_device_hard_reset_sync(hdev);
+ if (rc)
+ return rc;
+
+ return count;
+}
+
+static const struct file_operations debugfs_mac_loopback_fops = {
+ .owner = THIS_MODULE,
+ .read = debugfs_mac_loopback_read,
+ .write = debugfs_mac_loopback_write,
+};
+
+static void __hbl_cn_debugfs_dev_init(struct hbl_cn_device *hdev, struct dentry *root_dir)
+{
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_MAC_LOOPBACK, 0644, root_dir, hdev,
+ &debugfs_mac_loopback_fops);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_PAM4_TX_TAPS, 0444, root_dir, hdev,
+ &debugfs_pam4_tx_taps_fops);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_NRZ_TX_TAPS, 0444, root_dir, hdev,
+ &debugfs_nrz_tx_taps_fops);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_POLARITY, 0444, root_dir, hdev, &debugfs_polarity_fops);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_QP, 0444, root_dir, hdev, &debugfs_qp_fops);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_WQE, 0444, root_dir, hdev, &debugfs_wqe_fops);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_RESET_CNT, 0444, root_dir, hdev,
+ &debugfs_reset_cnt_fops);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_MAC_LANE_REMAP, 0644, root_dir, hdev,
+ &debugfs_mac_lane_remap_fops);
+
+ HBL_CN_DEBUGFS_CREATE_U8(NIC_RAND_STATUS, 0644, root_dir, &hdev->rand_status);
+
+ HBL_CN_DEBUGFS_CREATE_U8(NIC_MMU_BYPASS, 0644, root_dir, &hdev->mmu_bypass);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_ETH_LOOPBACK, 0644, root_dir, hdev,
+ &debugfs_eth_loopback_fops);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_PHY_REGS_PRINT, 0444, root_dir, hdev,
+ &debugfs_phy_regs_print_fops);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_SHOW_INTERNAL_PORTS_STATUS, 0444, root_dir, hdev,
+ &debugfs_show_internal_ports_status_fops);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_PRINT_FEC_STATS, 0444, root_dir, hdev,
+ &debugfs_print_fec_stats_fops);
+
+ HBL_CN_DEBUGFS_CREATE_U8(NIC_DISABLE_DECAP, 0644, root_dir, &hdev->is_decap_disabled);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_PHY_SET_NRZ, 0444, root_dir, hdev,
+ &debugfs_phy_set_nrz_fops);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_PHY_DUMP_SERDES_PARAMS, 0444, root_dir, hdev,
+ &debugfs_phy_dump_serdes_params_fops);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_INJECT_RX_ERR, 0444, root_dir, hdev,
+ &debugfs_inject_rx_err_fops);
+
+ HBL_CN_DEBUGFS_CREATE_U8(NIC_PHY_CALC_BER, 0644, root_dir, &hdev->phy_calc_ber);
+
+ HBL_CN_DEBUGFS_CREATE_U16(NIC_PHY_CALC_BER_WAIT_SEC, 0644, root_dir,
+ &hdev->phy_calc_ber_wait_sec);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_OVERRIDE_PORT_STATUS, 0200, root_dir, hdev,
+ &debugfs_override_port_status_fops);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_WQE_INDEX_CHECKER, 0644, root_dir, hdev,
+ &debugfs_wqe_index_checker_fops);
+
+ HBL_CN_DEBUGFS_CREATE_FILE(NIC_ACCUMULATE_FEC_DURATION, 0644, root_dir, hdev,
+ &debugfs_accumulate_fec_duration_fops);
+
+ HBL_CN_DEBUGFS_CREATE_U8(NIC_PHY_FORCE_FIRST_TX_TAPS_CFG, 0644, root_dir,
+ &hdev->phy_force_first_tx_taps_cfg);
+}
+
+void hbl_cn_debugfs_dev_init(struct hbl_cn_device *hdev)
+{
+ char name[64] = {0};
+
+ snprintf(name, sizeof(name), "hbl_cn%d", hdev->id);
+ hdev->cn_dentry = debugfs_create_dir(name, hbl_cn_debug_root);
+ __hbl_cn_debugfs_dev_init(hdev, hdev->cn_dentry);
+}
+
+void hbl_cn_debugfs_dev_fini(struct hbl_cn_device *hdev)
+{
+ debugfs_remove_recursive(hdev->cn_dentry);
+}
+
+void __init hbl_cn_debugfs_init(void)
+{
+ hbl_cn_debug_root = debugfs_create_dir(module_name(THIS_MODULE), NULL);
+}
+
+void hbl_cn_debugfs_fini(void)
+{
+ debugfs_remove_recursive(hbl_cn_debug_root);
+}
+
+#else
+
+void hbl_cn_debugfs_dev_init(struct hbl_cn_device *hdev)
+{
+}
+
+void hbl_cn_debugfs_dev_fini(struct hbl_cn_device *hdev)
+{
+}
+
+void __init hbl_cn_debugfs_init(void)
+{
+}
+
+void hbl_cn_debugfs_fini(void)
+{
+}
+
+#endif /* CONFIG_DEBUG_FS */
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_drv.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_drv.c
index 5ea690509592..1a26d9f3b9a4 100644
--- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_drv.c
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_drv.c
@@ -207,15 +207,32 @@ static struct auxiliary_driver hbl_cn_driver = {
static int __init hbl_cn_init(void)
{
+ int rc;
+
pr_info("loading driver\n");
- return auxiliary_driver_register(&hbl_cn_driver);
+ hbl_cn_debugfs_init();
+
+ rc = auxiliary_driver_register(&hbl_cn_driver);
+ if (rc) {
+ pr_err("Failed to register auxiliary driver\n");
+ goto remove_debugfs;
+ }
+
+ return 0;
+
+remove_debugfs:
+ hbl_cn_debugfs_fini();
+
+ return rc;
}
static void __exit hbl_cn_exit(void)
{
auxiliary_driver_unregister(&hbl_cn_driver);
+ hbl_cn_debugfs_fini();
+
pr_info("driver removed\n");
}
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* RE: [PATCH 06/15] net: hbl_cn: debugfs support
2024-06-13 8:21 ` [PATCH 06/15] net: hbl_cn: debugfs support Omer Shpigelman
@ 2024-06-19 18:35 ` Sunil Kovvuri Goutham
2024-06-21 10:17 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Sunil Kovvuri Goutham @ 2024-06-19 18:35 UTC (permalink / raw)
To: Omer Shpigelman, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org
Cc: ogabbay@kernel.org, zyehudai@habana.ai
>+
>+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_disable_decap
>+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_inject_rx_err
>+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_mac_lane_remap
Don't think debugfs is the correct interface for all this configuration.
Debugfs should ideally be used for dumping runtime device state info for debug purposes.
>+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_mac_loopback
Why not use ethtool ?
>+
>+What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_mmu_bypass
How does this work ?
Thanks,
Sunil.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 06/15] net: hbl_cn: debugfs support
2024-06-19 18:35 ` Sunil Kovvuri Goutham
@ 2024-06-21 10:17 ` Omer Shpigelman
2024-06-21 10:30 ` Sunil Kovvuri Goutham
2024-06-21 15:33 ` Andrew Lunn
0 siblings, 2 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-21 10:17 UTC (permalink / raw)
To: Sunil Kovvuri Goutham, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org
Cc: ogabbay@kernel.org, Zvika Yehudai
On 6/19/24 21:35, Sunil Kovvuri Goutham wrote:
> [Some people who received this message don't often get email from sgoutham@marvell.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
>> +
>> +What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_disable_decap
>> +What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_inject_rx_err
>> +What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_mac_lane_remap
>
> Don't think debugfs is the correct interface for all this configuration.
> Debugfs should ideally be used for dumping runtime device state info for debug purposes.
>
I see other vendors have debugfs entries for debug configurations or
settings, not just for dumping debug info.
>> +What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_mac_loopback
>
> Why not use ethtool ?
>
We have an ethtool option for that, but we have also internal NIC ports
that are not exposed as netdevices and for them the ethtool path is
irrelevant. Hence we need this debugfs option as well.
>> +
>> +What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_mmu_bypass
>
> How does this work ?
>
When this option is enabled the RDMA data buffers the user allocated on the
host memory are being accessed directly i.e. without MMU.
But now after you brought this up I see that it is not fully supported
anymore so I'll remove in the next version.
> Thanks,
> Sunil.
^ permalink raw reply [flat|nested] 108+ messages in thread
* RE: [PATCH 06/15] net: hbl_cn: debugfs support
2024-06-21 10:17 ` Omer Shpigelman
@ 2024-06-21 10:30 ` Sunil Kovvuri Goutham
2024-06-23 7:25 ` Omer Shpigelman
2024-06-21 15:33 ` Andrew Lunn
1 sibling, 1 reply; 108+ messages in thread
From: Sunil Kovvuri Goutham @ 2024-06-21 10:30 UTC (permalink / raw)
To: Omer Shpigelman, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org
Cc: ogabbay@kernel.org, Zvika Yehudai
>>> +
>>> +What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_disable_decap
>>> +What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_inject_rx_err
>>> +What:
>/sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_mac_lane_remap
>>
>> Don't think debugfs is the correct interface for all this configuration.
>> Debugfs should ideally be used for dumping runtime device state info for debug
>purposes.
>>
>
>I see other vendors have debugfs entries for debug configurations or settings, not
>just for dumping debug info.
>
But disable_decap / mac_lane_remap seems configuration related which changes the way pkts are processed not debug.
Configurations are supported via devlink.
Thanks,
Sunil.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 06/15] net: hbl_cn: debugfs support
2024-06-21 10:30 ` Sunil Kovvuri Goutham
@ 2024-06-23 7:25 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-23 7:25 UTC (permalink / raw)
To: Sunil Kovvuri Goutham, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org
Cc: ogabbay@kernel.org, Zvika Yehudai
On 6/21/24 13:30, Sunil Kovvuri Goutham wrote:
>>>> +
>>>> +What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_disable_decap
>>>> +What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_inject_rx_err
>>>> +What:
>> /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_mac_lane_remap
>>>
>>> Don't think debugfs is the correct interface for all this configuration.
>>> Debugfs should ideally be used for dumping runtime device state info for debug
>> purposes.
>>>
>>
>> I see other vendors have debugfs entries for debug configurations or settings, not
>> just for dumping debug info.
>>
>
> But disable_decap / mac_lane_remap seems configuration related which changes the way pkts are processed not debug.
> Configurations are supported via devlink.
>
As I wrote to Andrew, I'll stick to the debugfs entries that are really
necessary for us.
BTW the entries you mentioned are not regular configurations but advanced
settings to augment debuggability. But yeah, if we can set these via
devlink then it is better to use it.
Let me revisit this for the next patch set version.
> Thanks,
> Sunil.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 06/15] net: hbl_cn: debugfs support
2024-06-21 10:17 ` Omer Shpigelman
2024-06-21 10:30 ` Sunil Kovvuri Goutham
@ 2024-06-21 15:33 ` Andrew Lunn
2024-06-23 6:57 ` Omer Shpigelman
1 sibling, 1 reply; 108+ messages in thread
From: Andrew Lunn @ 2024-06-21 15:33 UTC (permalink / raw)
To: Omer Shpigelman
Cc: Sunil Kovvuri Goutham, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
> I see other vendors have debugfs entries for debug configurations or
> settings, not just for dumping debug info.
Did you see any added in the last few years? This is also something
DaveM pushed back on. We want uniform APIs so that all devices look
alike. Please consider what you are exporting here, how it should
cleanly fit into ethtool, devlink, etc, and expand these APIs to cover
your needs.
>
> >> +What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_mac_loopback
> >
> > Why not use ethtool ?
> >
>
> We have an ethtool option for that, but we have also internal NIC ports
> that are not exposed as netdevices and for them the ethtool path is
> irrelevant. Hence we need this debugfs option as well.
If there is no netdev, what is the point of putting it into loopback?
How do you send packets which are to be looped back? How do you
receive them to see if they were actually looped back?
Andrew
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 06/15] net: hbl_cn: debugfs support
2024-06-21 15:33 ` Andrew Lunn
@ 2024-06-23 6:57 ` Omer Shpigelman
2024-06-23 15:02 ` Andrew Lunn
0 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-23 6:57 UTC (permalink / raw)
To: Andrew Lunn
Cc: Sunil Kovvuri Goutham, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On 6/21/24 18:33, Andrew Lunn wrote:
>> I see other vendors have debugfs entries for debug configurations or
>> settings, not just for dumping debug info.
>
> Did you see any added in the last few years? This is also something
> DaveM pushed back on. We want uniform APIs so that all devices look
> alike. Please consider what you are exporting here, how it should
> cleanly fit into ethtool, devlink, etc, and expand these APIs to cover
> your needs.
>
If it's problematic then I'll try to stick to the ones which expose debug
info and maybe some other necessary debug options e.g. loopback. I'll try
to minimize by removing anything that is not mandatory.
>>
>>>> +What: /sys/kernel/debug/habanalabs_cn/hbl_cn<n>/nic_mac_loopback
>>>
>>> Why not use ethtool ?
>>>
>>
>> We have an ethtool option for that, but we have also internal NIC ports
>> that are not exposed as netdevices and for them the ethtool path is
>> irrelevant. Hence we need this debugfs option as well.
>
> If there is no netdev, what is the point of putting it into loopback?
> How do you send packets which are to be looped back? How do you
> receive them to see if they were actually looped back?
>
> Andrew
To run RDMA test in loopback. That's how we can pinpoint problems like
packet drops or performance degradation. For example, if packet drops were
seen on the port then it is crucial to know if these drops are
reproducible in loopback mode. If they are, then the root cause is
probably some internal HW failure or misconfiguration. If not, then the
packet drops might be related to the link quality.
We send these packets by setting a loopback bypass in the MAC layer. The
packets themselves and the NIC HW logic are agnostic to the loopback
setting (except of the packet's MAC address).
We receive and validate them and in the same way we receive and validate
regular packets - the loopback bypass is in the MAC layer which is in a
lower layer than our NIC HW logic.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 06/15] net: hbl_cn: debugfs support
2024-06-23 6:57 ` Omer Shpigelman
@ 2024-06-23 15:02 ` Andrew Lunn
2024-06-24 7:21 ` Omer Shpigelman
` (2 more replies)
0 siblings, 3 replies; 108+ messages in thread
From: Andrew Lunn @ 2024-06-23 15:02 UTC (permalink / raw)
To: Omer Shpigelman
Cc: Sunil Kovvuri Goutham, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
> > If there is no netdev, what is the point of putting it into loopback?
> > How do you send packets which are to be looped back? How do you
> > receive them to see if they were actually looped back?
> >
> > Andrew
>
> To run RDMA test in loopback.
What is special about your RDMA? Why do you need something which other
vendors don't? Please solve this problem for all RDMA devices, not
yours.
This all part of the same thing with respect to module
parameters. Vendors would add module parameters for something. Other
vendors would have the same concept, but give it a different name,
different values. It was all poorly documented. You had to read the
kernel sources to figure out what kernel module parameters do. Same
goes for debugfs, driver values in /proc, /sysfs or /debugfs. So for
years we have been pushing back on things like this.
If you have something which is unique to your hardware, no other
vendor is ever going to have the same, then you can make an argument
for something driver specific in /debugfs. But RDMA loopback tests is
clearly not specific to your driver. Extend the KAPI and tools to
cover this, document the KAPI, write the man page, and let other
vendors implement the little bit they need in their driver, so users
have a uniform way of doing things over a rather of devices.
You will get a lot of pushback on everything in /debugfs, so please
review them all with this in mind.
Andrew
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 06/15] net: hbl_cn: debugfs support
2024-06-23 15:02 ` Andrew Lunn
@ 2024-06-24 7:21 ` Omer Shpigelman
2024-06-24 9:22 ` Leon Romanovsky
2024-12-17 10:00 ` Avri Kehat
2 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-24 7:21 UTC (permalink / raw)
To: Andrew Lunn
Cc: Sunil Kovvuri Goutham, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On 6/23/24 18:02, Andrew Lunn wrote:
>>> If there is no netdev, what is the point of putting it into loopback?
>>> How do you send packets which are to be looped back? How do you
>>> receive them to see if they were actually looped back?
>>>
>>> Andrew
>>
>> To run RDMA test in loopback.
>
> What is special about your RDMA? Why do you need something which other
> vendors don't? Please solve this problem for all RDMA devices, not
> yours.
>
> This all part of the same thing with respect to module
> parameters. Vendors would add module parameters for something. Other
> vendors would have the same concept, but give it a different name,
> different values. It was all poorly documented. You had to read the
> kernel sources to figure out what kernel module parameters do. Same
> goes for debugfs, driver values in /proc, /sysfs or /debugfs. So for
> years we have been pushing back on things like this.
>
> If you have something which is unique to your hardware, no other
> vendor is ever going to have the same, then you can make an argument
> for something driver specific in /debugfs. But RDMA loopback tests is
> clearly not specific to your driver. Extend the KAPI and tools to
> cover this, document the KAPI, write the man page, and let other
> vendors implement the little bit they need in their driver, so users
> have a uniform way of doing things over a rather of devices.
>
> You will get a lot of pushback on everything in /debugfs, so please
> review them all with this in mind.
>
> Andrew
I see your point and I'll keep that in mind. For these kinds of
configurations we can use devlink instead of debugfs.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 06/15] net: hbl_cn: debugfs support
2024-06-23 15:02 ` Andrew Lunn
2024-06-24 7:21 ` Omer Shpigelman
@ 2024-06-24 9:22 ` Leon Romanovsky
2024-12-17 10:00 ` Avri Kehat
2 siblings, 0 replies; 108+ messages in thread
From: Leon Romanovsky @ 2024-06-24 9:22 UTC (permalink / raw)
To: Andrew Lunn
Cc: Omer Shpigelman, Sunil Kovvuri Goutham,
linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On Sun, Jun 23, 2024 at 05:02:44PM +0200, Andrew Lunn wrote:
> > > If there is no netdev, what is the point of putting it into loopback?
> > > How do you send packets which are to be looped back? How do you
> > > receive them to see if they were actually looped back?
> > >
> > > Andrew
> >
> > To run RDMA test in loopback.
>
> What is special about your RDMA? Why do you need something which other
> vendors don't? Please solve this problem for all RDMA devices, not
> yours.
I'm not aware of anything special here, which require special treatment.
All RDMA devices support loopback natively and can "put" traffic from
their TX directly to their RX. This is how we can run RDMA tests, which
are part of rdma-core https://github.com/linux-rdma/rdma-core/tree/master/tests.
Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 06/15] net: hbl_cn: debugfs support
2024-06-23 15:02 ` Andrew Lunn
2024-06-24 7:21 ` Omer Shpigelman
2024-06-24 9:22 ` Leon Romanovsky
@ 2024-12-17 10:00 ` Avri Kehat
2024-12-17 10:52 ` Andrew Lunn
2 siblings, 1 reply; 108+ messages in thread
From: Avri Kehat @ 2024-12-17 10:00 UTC (permalink / raw)
To: andrew
Cc: dri-devel, linux-kernel, linux-rdma, netdev, ogabbay, oshpigelman,
sgoutham, zyehudai
Revisiting the comments regarding our use of debugfs as an interface for device configurations -
A big part of the non-statistics debugfs parameters are HW related debug-only capabilities, and not configurations required by the user.
Should these sort of parameters be part of devlink as well?
Is there another location where debug related configurations for development can reside in?
Avri
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 06/15] net: hbl_cn: debugfs support
2024-12-17 10:00 ` Avri Kehat
@ 2024-12-17 10:52 ` Andrew Lunn
0 siblings, 0 replies; 108+ messages in thread
From: Andrew Lunn @ 2024-12-17 10:52 UTC (permalink / raw)
To: Avri Kehat
Cc: dri-devel, linux-kernel, linux-rdma, netdev, ogabbay, oshpigelman,
sgoutham, zyehudai
On Tue, Dec 17, 2024 at 12:00:39PM +0200, Avri Kehat wrote:
> Revisiting the comments regarding our use of debugfs as an interface for device configurations -
> A big part of the non-statistics debugfs parameters are HW related debug-only capabilities, and not configurations required by the user.
> Should these sort of parameters be part of devlink as well?
> Is there another location where debug related configurations for development can reside in?
There are a few options:
If the user does not require them, don't even implement them. If the
user is not using them, who is?
Implement them in an out of tree patch, which your development team
can use, since these are not user configuration options.
devlink is a possibility, but developers complain it is slow to get
them merged since we want to understand what the configuration option
does, why would i want to use it, would any other vendor have the same
need, and should it be made generic etc.
You could join those asking for fwctl, which is a contentious subject.
Andrew
^ permalink raw reply [flat|nested] 108+ messages in thread
* [PATCH 07/15] net: hbl_cn: gaudi2: ASIC register header files
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
` (5 preceding siblings ...)
2024-06-13 8:21 ` [PATCH 06/15] net: hbl_cn: debugfs support Omer Shpigelman
@ 2024-06-13 8:22 ` Omer Shpigelman
2024-06-13 8:22 ` [PATCH 08/15] net: hbl_cn: gaudi2: ASIC specific support Omer Shpigelman
` (9 subsequent siblings)
16 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:22 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
Add the relevant GAUDI2 ASIC registers header files. These files are
generated automatically from a tool maintained by the VLSI engineers.
These are required for the upcoming driver logic support.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
.../asic_reg/arc_farm_kdma_ctx_axuser_masks.h | 135 +
.../asic_reg/dcore0_sync_mngr_objs_regs.h | 43543 +++++++++++++++
.../asic_reg/gaudi2_blocks_linux_driver.h | 45068 ++++++++++++++++
.../hbl_cn/gaudi2/asic_reg/gaudi2_regs.h | 77 +
.../asic_reg/nic0_mac_ch0_mac_128_masks.h | 339 +
.../asic_reg/nic0_mac_ch0_mac_128_regs.h | 101 +
.../asic_reg/nic0_mac_ch0_mac_pcs_masks.h | 713 +
.../asic_reg/nic0_mac_ch0_mac_pcs_regs.h | 271 +
.../asic_reg/nic0_mac_ch1_mac_pcs_regs.h | 271 +
.../asic_reg/nic0_mac_ch2_mac_pcs_regs.h | 271 +
.../asic_reg/nic0_mac_ch3_mac_pcs_regs.h | 271 +
.../nic0_mac_glob_stat_control_reg_masks.h | 67 +
.../nic0_mac_glob_stat_control_reg_regs.h | 37 +
.../asic_reg/nic0_mac_glob_stat_rx0_regs.h | 93 +
.../asic_reg/nic0_mac_glob_stat_rx2_regs.h | 93 +
.../asic_reg/nic0_mac_glob_stat_tx0_regs.h | 75 +
.../asic_reg/nic0_mac_glob_stat_tx2_regs.h | 75 +
.../gaudi2/asic_reg/nic0_mac_rs_fec_regs.h | 157 +
.../hbl_cn/gaudi2/asic_reg/nic0_phy_masks.h | 77 +
.../hbl_cn/gaudi2/asic_reg/nic0_phy_regs.h | 59 +
.../nic0_qm0_axuser_nonsecured_regs.h | 61 +
.../asic_reg/nic0_qpc0_axuser_cong_que_regs.h | 61 +
.../asic_reg/nic0_qpc0_axuser_db_fifo_regs.h | 61 +
.../asic_reg/nic0_qpc0_axuser_err_fifo_regs.h | 61 +
.../nic0_qpc0_axuser_ev_que_lbw_intr_regs.h | 61 +
.../asic_reg/nic0_qpc0_axuser_qpc_req_regs.h | 61 +
.../asic_reg/nic0_qpc0_axuser_qpc_resp_regs.h | 61 +
.../asic_reg/nic0_qpc0_axuser_rxwqe_regs.h | 61 +
.../nic0_qpc0_axuser_txwqe_lbw_qman_bp_regs.h | 61 +
.../nic0_qpc0_dbfifo0_ci_upd_addr_regs.h | 27 +
.../nic0_qpc0_dbfifosecur_ci_upd_addr_regs.h | 27 +
.../hbl_cn/gaudi2/asic_reg/nic0_qpc0_masks.h | 963 +
.../hbl_cn/gaudi2/asic_reg/nic0_qpc0_regs.h | 905 +
.../hbl_cn/gaudi2/asic_reg/nic0_qpc1_regs.h | 905 +
.../gaudi2/asic_reg/nic0_rxb_core_masks.h | 459 +
.../gaudi2/asic_reg/nic0_rxb_core_regs.h | 665 +
.../nic0_rxe0_axuser_axuser_cq0_regs.h | 61 +
.../nic0_rxe0_axuser_axuser_cq1_regs.h | 61 +
.../hbl_cn/gaudi2/asic_reg/nic0_rxe0_masks.h | 705 +
.../hbl_cn/gaudi2/asic_reg/nic0_rxe0_regs.h | 725 +
.../asic_reg/nic0_rxe0_wqe_aruser_regs.h | 61 +
.../hbl_cn/gaudi2/asic_reg/nic0_rxe1_regs.h | 725 +
.../gaudi2/asic_reg/nic0_serdes0_masks.h | 7163 +++
.../gaudi2/asic_reg/nic0_serdes0_regs.h | 1679 +
.../gaudi2/asic_reg/nic0_serdes1_regs.h | 1679 +
.../asic_reg/nic0_tmr_axuser_tmr_fifo_regs.h | 61 +
.../nic0_tmr_axuser_tmr_free_list_regs.h | 61 +
.../asic_reg/nic0_tmr_axuser_tmr_fsm_regs.h | 61 +
.../hbl_cn/gaudi2/asic_reg/nic0_tmr_masks.h | 361 +
.../hbl_cn/gaudi2/asic_reg/nic0_tmr_regs.h | 183 +
.../hbl_cn/gaudi2/asic_reg/nic0_txb_regs.h | 167 +
.../hbl_cn/gaudi2/asic_reg/nic0_txe0_masks.h | 759 +
.../hbl_cn/gaudi2/asic_reg/nic0_txe0_regs.h | 529 +
.../hbl_cn/gaudi2/asic_reg/nic0_txs0_masks.h | 555 +
.../hbl_cn/gaudi2/asic_reg/nic0_txs0_regs.h | 289 +
.../nic0_umr0_0_completion_queue_ci_1_regs.h | 27 +
.../nic0_umr0_0_unsecure_doorbell0_regs.h | 31 +
.../nic0_umr0_0_unsecure_doorbell1_regs.h | 31 +
.../gaudi2/asic_reg/prt0_mac_core_masks.h | 137 +
.../gaudi2/asic_reg/prt0_mac_core_regs.h | 67 +
60 files changed, 112471 insertions(+)
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/gaudi2_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_128_masks.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_128_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_pcs_masks.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_pcs_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch1_mac_pcs_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch2_mac_pcs_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch3_mac_pcs_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_control_reg_masks.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_control_reg_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_rx0_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_rx2_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_tx0_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_tx2_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_rs_fec_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_phy_masks.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_phy_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qm0_axuser_nonsecured_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_cong_que_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_db_fifo_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_err_fifo_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_ev_que_lbw_intr_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_qpc_req_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_qpc_resp_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_rxwqe_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_txwqe_lbw_qman_bp_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_dbfifo0_ci_upd_addr_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_dbfifosecur_ci_upd_addr_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_masks.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc1_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxb_core_masks.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxb_core_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_axuser_axuser_cq0_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_axuser_axuser_cq1_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_masks.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_wqe_aruser_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe1_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes0_masks.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes0_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes1_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_fifo_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_free_list_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_fsm_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_masks.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txb_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txe0_masks.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txe0_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txs0_masks.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txs0_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell1_regs.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/prt0_mac_core_masks.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/prt0_mac_core_regs.h
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h
new file mode 100644
index 000000000000..ed8a60571392
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_
+#define ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_
+
+/*****************************************
+ * ARC_FARM_KDMA_CTX_AXUSER
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_ASID */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_MASK 0x3FF
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT 16
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_MASK 0x3FF0000
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_MASK 0x1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_MASK 0x10
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_WR_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_WR_MASK 0x1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_RD_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_RD_MASK 0x10
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_WR_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_WR_MASK 0x1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_RD_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_RD_MASK 0x10
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_IND_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_IND_MASK 0x1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_DTYPE_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_DTYPE_MASK 0xF0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_OP_SHIFT 8
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_OP_MASK 0x300
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_ROUND_SHIFT 12
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_ROUND_MASK 0x3000
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_MAX_SHIFT 16
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_MAX_MASK 0x10000
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_IND_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_IND_MASK 0x3
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_MASK 0xFF0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_MSB_MASK_SHIFT 12
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_MSB_MASK_MASK 0x1F000
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_QOS */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_WR_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_WR_MASK 0xF
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_RD_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_RD_MASK 0x70
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_27_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_27_MASK 0x1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_28_SHIFT 1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_28_MASK 0x2
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_30_SHIFT 2
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_30_MASK 0x4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_31_SHIFT 3
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_31_MASK 0x8
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_WR_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_WR_MASK 0x1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_RD_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_RD_MASK 0x10
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_CORE */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_WR_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_WR_MASK 0x1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_RD_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_RD_MASK 0x10
+
+/* ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD */
+#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_X_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_X_MASK 0x1F
+#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_Y_SHIFT 8
+#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_Y_MASK 0xF00
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI_VAL_MASK 0x3FF
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI_VAL_MASK 0x3FF
+
+/* ARC_FARM_KDMA_CTX_AXUSER_LB_COORD */
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_COORD_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_COORD_VAL_MASK 0x3FF
+
+/* ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK */
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK_VAL_MASK 0x1
+
+/* ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD */
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_21_11_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_21_11_MASK 0x7FF
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_22_SHIFT 12
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_22_MASK 0x1000
+
+/* ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD */
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD_VAL_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h
new file mode 100644
index 000000000000..3a361f5abcbc
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h
@@ -0,0 +1,43543 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_SYNC_MNGR_OBJS_REGS_H_
+#define ASIC_REG_DCORE0_SYNC_MNGR_OBJS_REGS_H_
+
+/*****************************************
+ * DCORE0_SYNC_MNGR_OBJS
+ * (Prototype: SOB_OBJS)
+ *****************************************
+ */
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4100000
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1 0x4100004
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2 0x4100008
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3 0x410000C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4 0x4100010
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5 0x4100014
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6 0x4100018
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7 0x410001C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8 0x4100020
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_9 0x4100024
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_10 0x4100028
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_11 0x410002C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_12 0x4100030
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_13 0x4100034
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_14 0x4100038
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_15 0x410003C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_16 0x4100040
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_17 0x4100044
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_18 0x4100048
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_19 0x410004C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_20 0x4100050
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_21 0x4100054
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_22 0x4100058
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_23 0x410005C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_24 0x4100060
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_25 0x4100064
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_26 0x4100068
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_27 0x410006C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_28 0x4100070
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_29 0x4100074
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_30 0x4100078
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_31 0x410007C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_32 0x4100080
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_33 0x4100084
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_34 0x4100088
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_35 0x410008C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_36 0x4100090
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_37 0x4100094
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_38 0x4100098
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_39 0x410009C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_40 0x41000A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_41 0x41000A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_42 0x41000A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_43 0x41000AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_44 0x41000B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_45 0x41000B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_46 0x41000B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_47 0x41000BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_48 0x41000C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_49 0x41000C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_50 0x41000C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_51 0x41000CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_52 0x41000D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_53 0x41000D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_54 0x41000D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_55 0x41000DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_56 0x41000E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_57 0x41000E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_58 0x41000E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_59 0x41000EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_60 0x41000F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_61 0x41000F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_62 0x41000F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_63 0x41000FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_64 0x4100100
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_65 0x4100104
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_66 0x4100108
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_67 0x410010C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_68 0x4100110
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_69 0x4100114
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_70 0x4100118
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_71 0x410011C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_72 0x4100120
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_73 0x4100124
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_74 0x4100128
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_75 0x410012C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_76 0x4100130
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_77 0x4100134
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_78 0x4100138
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_79 0x410013C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_80 0x4100140
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_81 0x4100144
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_82 0x4100148
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_83 0x410014C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_84 0x4100150
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_85 0x4100154
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_86 0x4100158
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_87 0x410015C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_88 0x4100160
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_89 0x4100164
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_90 0x4100168
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_91 0x410016C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_92 0x4100170
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_93 0x4100174
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_94 0x4100178
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_95 0x410017C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_96 0x4100180
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_97 0x4100184
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_98 0x4100188
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_99 0x410018C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_100 0x4100190
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_101 0x4100194
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_102 0x4100198
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_103 0x410019C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_104 0x41001A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_105 0x41001A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_106 0x41001A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_107 0x41001AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_108 0x41001B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_109 0x41001B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_110 0x41001B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_111 0x41001BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_112 0x41001C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_113 0x41001C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_114 0x41001C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_115 0x41001CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_116 0x41001D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_117 0x41001D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_118 0x41001D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_119 0x41001DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_120 0x41001E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_121 0x41001E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_122 0x41001E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_123 0x41001EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_124 0x41001F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_125 0x41001F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_126 0x41001F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_127 0x41001FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_128 0x4100200
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_129 0x4100204
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_130 0x4100208
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_131 0x410020C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_132 0x4100210
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_133 0x4100214
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_134 0x4100218
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_135 0x410021C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_136 0x4100220
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_137 0x4100224
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_138 0x4100228
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_139 0x410022C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_140 0x4100230
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_141 0x4100234
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_142 0x4100238
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_143 0x410023C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_144 0x4100240
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_145 0x4100244
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_146 0x4100248
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_147 0x410024C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_148 0x4100250
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_149 0x4100254
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_150 0x4100258
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_151 0x410025C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_152 0x4100260
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_153 0x4100264
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_154 0x4100268
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_155 0x410026C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_156 0x4100270
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_157 0x4100274
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_158 0x4100278
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_159 0x410027C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_160 0x4100280
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_161 0x4100284
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_162 0x4100288
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_163 0x410028C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_164 0x4100290
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_165 0x4100294
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_166 0x4100298
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_167 0x410029C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_168 0x41002A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_169 0x41002A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_170 0x41002A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_171 0x41002AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_172 0x41002B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_173 0x41002B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_174 0x41002B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_175 0x41002BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_176 0x41002C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_177 0x41002C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_178 0x41002C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_179 0x41002CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_180 0x41002D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_181 0x41002D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_182 0x41002D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_183 0x41002DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_184 0x41002E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_185 0x41002E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_186 0x41002E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_187 0x41002EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_188 0x41002F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_189 0x41002F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_190 0x41002F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_191 0x41002FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_192 0x4100300
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_193 0x4100304
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_194 0x4100308
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_195 0x410030C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_196 0x4100310
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_197 0x4100314
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_198 0x4100318
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_199 0x410031C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_200 0x4100320
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_201 0x4100324
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_202 0x4100328
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_203 0x410032C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_204 0x4100330
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_205 0x4100334
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_206 0x4100338
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_207 0x410033C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_208 0x4100340
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_209 0x4100344
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_210 0x4100348
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_211 0x410034C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_212 0x4100350
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_213 0x4100354
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_214 0x4100358
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_215 0x410035C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_216 0x4100360
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_217 0x4100364
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_218 0x4100368
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_219 0x410036C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_220 0x4100370
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_221 0x4100374
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_222 0x4100378
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_223 0x410037C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_224 0x4100380
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_225 0x4100384
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_226 0x4100388
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_227 0x410038C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_228 0x4100390
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_229 0x4100394
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_230 0x4100398
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_231 0x410039C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_232 0x41003A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_233 0x41003A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_234 0x41003A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_235 0x41003AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_236 0x41003B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_237 0x41003B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_238 0x41003B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_239 0x41003BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_240 0x41003C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_241 0x41003C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_242 0x41003C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_243 0x41003CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_244 0x41003D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_245 0x41003D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_246 0x41003D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_247 0x41003DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_248 0x41003E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_249 0x41003E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_250 0x41003E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_251 0x41003EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_252 0x41003F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_253 0x41003F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_254 0x41003F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_255 0x41003FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_256 0x4100400
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_257 0x4100404
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_258 0x4100408
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_259 0x410040C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_260 0x4100410
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_261 0x4100414
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_262 0x4100418
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_263 0x410041C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_264 0x4100420
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_265 0x4100424
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_266 0x4100428
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_267 0x410042C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_268 0x4100430
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_269 0x4100434
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_270 0x4100438
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_271 0x410043C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_272 0x4100440
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_273 0x4100444
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_274 0x4100448
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_275 0x410044C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_276 0x4100450
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_277 0x4100454
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_278 0x4100458
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_279 0x410045C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_280 0x4100460
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_281 0x4100464
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_282 0x4100468
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_283 0x410046C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_284 0x4100470
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_285 0x4100474
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_286 0x4100478
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_287 0x410047C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_288 0x4100480
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_289 0x4100484
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_290 0x4100488
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_291 0x410048C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_292 0x4100490
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_293 0x4100494
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_294 0x4100498
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_295 0x410049C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_296 0x41004A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_297 0x41004A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_298 0x41004A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_299 0x41004AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_300 0x41004B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_301 0x41004B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_302 0x41004B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_303 0x41004BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_304 0x41004C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_305 0x41004C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_306 0x41004C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_307 0x41004CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_308 0x41004D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_309 0x41004D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_310 0x41004D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_311 0x41004DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_312 0x41004E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_313 0x41004E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_314 0x41004E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_315 0x41004EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_316 0x41004F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_317 0x41004F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_318 0x41004F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_319 0x41004FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_320 0x4100500
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_321 0x4100504
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_322 0x4100508
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_323 0x410050C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_324 0x4100510
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_325 0x4100514
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_326 0x4100518
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_327 0x410051C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_328 0x4100520
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_329 0x4100524
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_330 0x4100528
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_331 0x410052C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_332 0x4100530
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_333 0x4100534
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_334 0x4100538
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_335 0x410053C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_336 0x4100540
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_337 0x4100544
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_338 0x4100548
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_339 0x410054C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_340 0x4100550
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_341 0x4100554
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_342 0x4100558
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_343 0x410055C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_344 0x4100560
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_345 0x4100564
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_346 0x4100568
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_347 0x410056C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_348 0x4100570
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_349 0x4100574
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_350 0x4100578
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_351 0x410057C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_352 0x4100580
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_353 0x4100584
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_354 0x4100588
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_355 0x410058C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_356 0x4100590
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_357 0x4100594
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_358 0x4100598
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_359 0x410059C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_360 0x41005A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_361 0x41005A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_362 0x41005A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_363 0x41005AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_364 0x41005B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_365 0x41005B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_366 0x41005B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_367 0x41005BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_368 0x41005C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_369 0x41005C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_370 0x41005C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_371 0x41005CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_372 0x41005D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_373 0x41005D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_374 0x41005D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_375 0x41005DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_376 0x41005E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_377 0x41005E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_378 0x41005E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_379 0x41005EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_380 0x41005F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_381 0x41005F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_382 0x41005F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_383 0x41005FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_384 0x4100600
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_385 0x4100604
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_386 0x4100608
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_387 0x410060C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_388 0x4100610
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_389 0x4100614
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_390 0x4100618
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_391 0x410061C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_392 0x4100620
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_393 0x4100624
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_394 0x4100628
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_395 0x410062C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_396 0x4100630
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_397 0x4100634
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_398 0x4100638
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_399 0x410063C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_400 0x4100640
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_401 0x4100644
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_402 0x4100648
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_403 0x410064C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_404 0x4100650
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_405 0x4100654
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_406 0x4100658
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_407 0x410065C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_408 0x4100660
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_409 0x4100664
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_410 0x4100668
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_411 0x410066C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_412 0x4100670
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_413 0x4100674
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_414 0x4100678
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_415 0x410067C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_416 0x4100680
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_417 0x4100684
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_418 0x4100688
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_419 0x410068C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_420 0x4100690
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_421 0x4100694
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_422 0x4100698
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_423 0x410069C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_424 0x41006A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_425 0x41006A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_426 0x41006A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_427 0x41006AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_428 0x41006B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_429 0x41006B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_430 0x41006B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_431 0x41006BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_432 0x41006C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_433 0x41006C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_434 0x41006C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_435 0x41006CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_436 0x41006D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_437 0x41006D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_438 0x41006D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_439 0x41006DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_440 0x41006E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_441 0x41006E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_442 0x41006E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_443 0x41006EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_444 0x41006F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_445 0x41006F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_446 0x41006F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_447 0x41006FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_448 0x4100700
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_449 0x4100704
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_450 0x4100708
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_451 0x410070C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_452 0x4100710
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_453 0x4100714
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_454 0x4100718
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_455 0x410071C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_456 0x4100720
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_457 0x4100724
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_458 0x4100728
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_459 0x410072C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_460 0x4100730
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_461 0x4100734
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_462 0x4100738
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_463 0x410073C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_464 0x4100740
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_465 0x4100744
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_466 0x4100748
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_467 0x410074C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_468 0x4100750
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_469 0x4100754
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_470 0x4100758
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_471 0x410075C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_472 0x4100760
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_473 0x4100764
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_474 0x4100768
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_475 0x410076C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_476 0x4100770
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_477 0x4100774
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_478 0x4100778
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_479 0x410077C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_480 0x4100780
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_481 0x4100784
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_482 0x4100788
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_483 0x410078C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_484 0x4100790
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_485 0x4100794
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_486 0x4100798
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_487 0x410079C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_488 0x41007A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_489 0x41007A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_490 0x41007A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_491 0x41007AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_492 0x41007B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_493 0x41007B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_494 0x41007B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_495 0x41007BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_496 0x41007C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_497 0x41007C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_498 0x41007C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_499 0x41007CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_500 0x41007D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_501 0x41007D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_502 0x41007D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_503 0x41007DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_504 0x41007E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_505 0x41007E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_506 0x41007E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_507 0x41007EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_508 0x41007F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_509 0x41007F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_510 0x41007F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_511 0x41007FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_512 0x4100800
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_513 0x4100804
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_514 0x4100808
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_515 0x410080C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_516 0x4100810
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_517 0x4100814
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_518 0x4100818
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_519 0x410081C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_520 0x4100820
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_521 0x4100824
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_522 0x4100828
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_523 0x410082C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_524 0x4100830
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_525 0x4100834
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_526 0x4100838
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_527 0x410083C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_528 0x4100840
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_529 0x4100844
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_530 0x4100848
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_531 0x410084C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_532 0x4100850
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_533 0x4100854
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_534 0x4100858
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_535 0x410085C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_536 0x4100860
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_537 0x4100864
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_538 0x4100868
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_539 0x410086C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_540 0x4100870
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_541 0x4100874
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_542 0x4100878
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_543 0x410087C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_544 0x4100880
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_545 0x4100884
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_546 0x4100888
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_547 0x410088C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_548 0x4100890
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_549 0x4100894
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_550 0x4100898
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_551 0x410089C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_552 0x41008A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_553 0x41008A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_554 0x41008A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_555 0x41008AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_556 0x41008B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_557 0x41008B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_558 0x41008B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_559 0x41008BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_560 0x41008C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_561 0x41008C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_562 0x41008C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_563 0x41008CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_564 0x41008D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_565 0x41008D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_566 0x41008D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_567 0x41008DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_568 0x41008E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_569 0x41008E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_570 0x41008E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_571 0x41008EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_572 0x41008F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_573 0x41008F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_574 0x41008F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_575 0x41008FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_576 0x4100900
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_577 0x4100904
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_578 0x4100908
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_579 0x410090C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_580 0x4100910
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_581 0x4100914
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_582 0x4100918
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_583 0x410091C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_584 0x4100920
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_585 0x4100924
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_586 0x4100928
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_587 0x410092C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_588 0x4100930
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_589 0x4100934
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_590 0x4100938
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_591 0x410093C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_592 0x4100940
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_593 0x4100944
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_594 0x4100948
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_595 0x410094C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_596 0x4100950
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_597 0x4100954
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_598 0x4100958
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_599 0x410095C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_600 0x4100960
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_601 0x4100964
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_602 0x4100968
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_603 0x410096C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_604 0x4100970
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_605 0x4100974
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_606 0x4100978
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_607 0x410097C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_608 0x4100980
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_609 0x4100984
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_610 0x4100988
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_611 0x410098C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_612 0x4100990
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_613 0x4100994
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_614 0x4100998
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_615 0x410099C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_616 0x41009A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_617 0x41009A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_618 0x41009A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_619 0x41009AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_620 0x41009B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_621 0x41009B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_622 0x41009B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_623 0x41009BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_624 0x41009C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_625 0x41009C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_626 0x41009C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_627 0x41009CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_628 0x41009D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_629 0x41009D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_630 0x41009D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_631 0x41009DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_632 0x41009E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_633 0x41009E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_634 0x41009E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_635 0x41009EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_636 0x41009F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_637 0x41009F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_638 0x41009F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_639 0x41009FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_640 0x4100A00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_641 0x4100A04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_642 0x4100A08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_643 0x4100A0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_644 0x4100A10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_645 0x4100A14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_646 0x4100A18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_647 0x4100A1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_648 0x4100A20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_649 0x4100A24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_650 0x4100A28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_651 0x4100A2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_652 0x4100A30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_653 0x4100A34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_654 0x4100A38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_655 0x4100A3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_656 0x4100A40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_657 0x4100A44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_658 0x4100A48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_659 0x4100A4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_660 0x4100A50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_661 0x4100A54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_662 0x4100A58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_663 0x4100A5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_664 0x4100A60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_665 0x4100A64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_666 0x4100A68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_667 0x4100A6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_668 0x4100A70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_669 0x4100A74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_670 0x4100A78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_671 0x4100A7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_672 0x4100A80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_673 0x4100A84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_674 0x4100A88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_675 0x4100A8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_676 0x4100A90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_677 0x4100A94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_678 0x4100A98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_679 0x4100A9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_680 0x4100AA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_681 0x4100AA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_682 0x4100AA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_683 0x4100AAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_684 0x4100AB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_685 0x4100AB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_686 0x4100AB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_687 0x4100ABC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_688 0x4100AC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_689 0x4100AC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_690 0x4100AC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_691 0x4100ACC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_692 0x4100AD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_693 0x4100AD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_694 0x4100AD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_695 0x4100ADC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_696 0x4100AE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_697 0x4100AE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_698 0x4100AE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_699 0x4100AEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_700 0x4100AF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_701 0x4100AF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_702 0x4100AF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_703 0x4100AFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_704 0x4100B00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_705 0x4100B04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_706 0x4100B08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_707 0x4100B0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_708 0x4100B10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_709 0x4100B14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_710 0x4100B18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_711 0x4100B1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_712 0x4100B20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_713 0x4100B24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_714 0x4100B28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_715 0x4100B2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_716 0x4100B30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_717 0x4100B34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_718 0x4100B38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_719 0x4100B3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_720 0x4100B40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_721 0x4100B44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_722 0x4100B48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_723 0x4100B4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_724 0x4100B50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_725 0x4100B54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_726 0x4100B58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_727 0x4100B5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_728 0x4100B60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_729 0x4100B64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_730 0x4100B68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_731 0x4100B6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_732 0x4100B70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_733 0x4100B74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_734 0x4100B78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_735 0x4100B7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_736 0x4100B80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_737 0x4100B84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_738 0x4100B88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_739 0x4100B8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_740 0x4100B90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_741 0x4100B94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_742 0x4100B98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_743 0x4100B9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_744 0x4100BA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_745 0x4100BA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_746 0x4100BA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_747 0x4100BAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_748 0x4100BB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_749 0x4100BB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_750 0x4100BB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_751 0x4100BBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_752 0x4100BC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_753 0x4100BC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_754 0x4100BC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_755 0x4100BCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_756 0x4100BD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_757 0x4100BD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_758 0x4100BD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_759 0x4100BDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_760 0x4100BE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_761 0x4100BE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_762 0x4100BE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_763 0x4100BEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_764 0x4100BF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_765 0x4100BF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_766 0x4100BF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_767 0x4100BFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_768 0x4100C00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_769 0x4100C04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_770 0x4100C08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_771 0x4100C0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_772 0x4100C10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_773 0x4100C14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_774 0x4100C18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_775 0x4100C1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_776 0x4100C20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_777 0x4100C24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_778 0x4100C28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_779 0x4100C2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_780 0x4100C30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_781 0x4100C34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_782 0x4100C38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_783 0x4100C3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_784 0x4100C40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_785 0x4100C44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_786 0x4100C48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_787 0x4100C4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_788 0x4100C50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_789 0x4100C54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_790 0x4100C58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_791 0x4100C5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_792 0x4100C60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_793 0x4100C64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_794 0x4100C68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_795 0x4100C6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_796 0x4100C70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_797 0x4100C74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_798 0x4100C78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_799 0x4100C7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_800 0x4100C80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_801 0x4100C84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_802 0x4100C88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_803 0x4100C8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_804 0x4100C90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_805 0x4100C94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_806 0x4100C98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_807 0x4100C9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_808 0x4100CA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_809 0x4100CA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_810 0x4100CA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_811 0x4100CAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_812 0x4100CB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_813 0x4100CB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_814 0x4100CB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_815 0x4100CBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_816 0x4100CC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_817 0x4100CC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_818 0x4100CC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_819 0x4100CCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_820 0x4100CD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_821 0x4100CD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_822 0x4100CD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_823 0x4100CDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_824 0x4100CE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_825 0x4100CE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_826 0x4100CE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_827 0x4100CEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_828 0x4100CF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_829 0x4100CF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_830 0x4100CF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_831 0x4100CFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_832 0x4100D00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_833 0x4100D04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_834 0x4100D08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_835 0x4100D0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_836 0x4100D10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_837 0x4100D14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_838 0x4100D18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_839 0x4100D1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_840 0x4100D20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_841 0x4100D24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_842 0x4100D28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_843 0x4100D2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_844 0x4100D30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_845 0x4100D34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_846 0x4100D38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_847 0x4100D3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_848 0x4100D40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_849 0x4100D44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_850 0x4100D48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_851 0x4100D4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_852 0x4100D50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_853 0x4100D54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_854 0x4100D58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_855 0x4100D5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_856 0x4100D60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_857 0x4100D64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_858 0x4100D68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_859 0x4100D6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_860 0x4100D70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_861 0x4100D74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_862 0x4100D78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_863 0x4100D7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_864 0x4100D80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_865 0x4100D84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_866 0x4100D88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_867 0x4100D8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_868 0x4100D90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_869 0x4100D94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_870 0x4100D98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_871 0x4100D9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_872 0x4100DA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_873 0x4100DA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_874 0x4100DA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_875 0x4100DAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_876 0x4100DB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_877 0x4100DB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_878 0x4100DB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_879 0x4100DBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_880 0x4100DC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_881 0x4100DC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_882 0x4100DC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_883 0x4100DCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_884 0x4100DD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_885 0x4100DD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_886 0x4100DD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_887 0x4100DDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_888 0x4100DE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_889 0x4100DE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_890 0x4100DE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_891 0x4100DEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_892 0x4100DF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_893 0x4100DF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_894 0x4100DF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_895 0x4100DFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_896 0x4100E00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_897 0x4100E04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_898 0x4100E08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_899 0x4100E0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_900 0x4100E10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_901 0x4100E14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_902 0x4100E18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_903 0x4100E1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_904 0x4100E20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_905 0x4100E24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_906 0x4100E28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_907 0x4100E2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_908 0x4100E30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_909 0x4100E34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_910 0x4100E38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_911 0x4100E3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_912 0x4100E40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_913 0x4100E44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_914 0x4100E48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_915 0x4100E4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_916 0x4100E50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_917 0x4100E54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_918 0x4100E58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_919 0x4100E5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_920 0x4100E60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_921 0x4100E64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_922 0x4100E68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_923 0x4100E6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_924 0x4100E70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_925 0x4100E74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_926 0x4100E78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_927 0x4100E7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_928 0x4100E80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_929 0x4100E84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_930 0x4100E88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_931 0x4100E8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_932 0x4100E90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_933 0x4100E94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_934 0x4100E98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_935 0x4100E9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_936 0x4100EA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_937 0x4100EA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_938 0x4100EA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_939 0x4100EAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_940 0x4100EB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_941 0x4100EB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_942 0x4100EB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_943 0x4100EBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_944 0x4100EC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_945 0x4100EC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_946 0x4100EC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_947 0x4100ECC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_948 0x4100ED0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_949 0x4100ED4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_950 0x4100ED8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_951 0x4100EDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_952 0x4100EE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_953 0x4100EE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_954 0x4100EE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_955 0x4100EEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_956 0x4100EF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_957 0x4100EF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_958 0x4100EF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_959 0x4100EFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_960 0x4100F00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_961 0x4100F04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_962 0x4100F08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_963 0x4100F0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_964 0x4100F10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_965 0x4100F14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_966 0x4100F18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_967 0x4100F1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_968 0x4100F20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_969 0x4100F24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_970 0x4100F28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_971 0x4100F2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_972 0x4100F30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_973 0x4100F34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_974 0x4100F38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_975 0x4100F3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_976 0x4100F40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_977 0x4100F44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_978 0x4100F48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_979 0x4100F4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_980 0x4100F50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_981 0x4100F54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_982 0x4100F58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_983 0x4100F5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_984 0x4100F60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_985 0x4100F64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_986 0x4100F68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_987 0x4100F6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_988 0x4100F70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_989 0x4100F74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_990 0x4100F78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_991 0x4100F7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_992 0x4100F80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_993 0x4100F84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_994 0x4100F88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_995 0x4100F8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_996 0x4100F90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_997 0x4100F94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_998 0x4100F98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_999 0x4100F9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1000 0x4100FA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1001 0x4100FA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1002 0x4100FA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1003 0x4100FAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1004 0x4100FB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1005 0x4100FB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1006 0x4100FB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1007 0x4100FBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1008 0x4100FC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1009 0x4100FC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1010 0x4100FC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1011 0x4100FCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1012 0x4100FD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1013 0x4100FD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1014 0x4100FD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1015 0x4100FDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1016 0x4100FE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1017 0x4100FE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1018 0x4100FE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1019 0x4100FEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1020 0x4100FF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1021 0x4100FF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1022 0x4100FF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1023 0x4100FFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1024 0x4101000
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1025 0x4101004
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1026 0x4101008
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1027 0x410100C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1028 0x4101010
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1029 0x4101014
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1030 0x4101018
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1031 0x410101C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1032 0x4101020
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1033 0x4101024
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1034 0x4101028
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1035 0x410102C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1036 0x4101030
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1037 0x4101034
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1038 0x4101038
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1039 0x410103C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1040 0x4101040
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1041 0x4101044
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1042 0x4101048
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1043 0x410104C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1044 0x4101050
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1045 0x4101054
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1046 0x4101058
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1047 0x410105C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1048 0x4101060
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1049 0x4101064
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1050 0x4101068
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1051 0x410106C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1052 0x4101070
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1053 0x4101074
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1054 0x4101078
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1055 0x410107C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1056 0x4101080
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1057 0x4101084
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1058 0x4101088
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1059 0x410108C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1060 0x4101090
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1061 0x4101094
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1062 0x4101098
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1063 0x410109C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1064 0x41010A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1065 0x41010A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1066 0x41010A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1067 0x41010AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1068 0x41010B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1069 0x41010B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1070 0x41010B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1071 0x41010BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1072 0x41010C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1073 0x41010C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1074 0x41010C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1075 0x41010CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1076 0x41010D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1077 0x41010D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1078 0x41010D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1079 0x41010DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1080 0x41010E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1081 0x41010E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1082 0x41010E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1083 0x41010EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1084 0x41010F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1085 0x41010F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1086 0x41010F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1087 0x41010FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1088 0x4101100
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1089 0x4101104
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1090 0x4101108
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1091 0x410110C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1092 0x4101110
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1093 0x4101114
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1094 0x4101118
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1095 0x410111C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1096 0x4101120
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1097 0x4101124
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1098 0x4101128
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1099 0x410112C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1100 0x4101130
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1101 0x4101134
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1102 0x4101138
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1103 0x410113C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1104 0x4101140
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1105 0x4101144
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1106 0x4101148
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1107 0x410114C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1108 0x4101150
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1109 0x4101154
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1110 0x4101158
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1111 0x410115C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1112 0x4101160
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1113 0x4101164
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1114 0x4101168
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1115 0x410116C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1116 0x4101170
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1117 0x4101174
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1118 0x4101178
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1119 0x410117C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1120 0x4101180
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1121 0x4101184
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1122 0x4101188
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1123 0x410118C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1124 0x4101190
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1125 0x4101194
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1126 0x4101198
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1127 0x410119C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1128 0x41011A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1129 0x41011A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1130 0x41011A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1131 0x41011AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1132 0x41011B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1133 0x41011B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1134 0x41011B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1135 0x41011BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1136 0x41011C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1137 0x41011C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1138 0x41011C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1139 0x41011CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1140 0x41011D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1141 0x41011D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1142 0x41011D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1143 0x41011DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1144 0x41011E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1145 0x41011E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1146 0x41011E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1147 0x41011EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1148 0x41011F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1149 0x41011F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1150 0x41011F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1151 0x41011FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1152 0x4101200
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1153 0x4101204
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1154 0x4101208
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1155 0x410120C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1156 0x4101210
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1157 0x4101214
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1158 0x4101218
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1159 0x410121C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1160 0x4101220
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1161 0x4101224
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1162 0x4101228
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1163 0x410122C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1164 0x4101230
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1165 0x4101234
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1166 0x4101238
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1167 0x410123C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1168 0x4101240
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1169 0x4101244
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1170 0x4101248
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1171 0x410124C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1172 0x4101250
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1173 0x4101254
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1174 0x4101258
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1175 0x410125C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1176 0x4101260
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1177 0x4101264
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1178 0x4101268
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1179 0x410126C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1180 0x4101270
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1181 0x4101274
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1182 0x4101278
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1183 0x410127C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1184 0x4101280
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1185 0x4101284
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1186 0x4101288
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1187 0x410128C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1188 0x4101290
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1189 0x4101294
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1190 0x4101298
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1191 0x410129C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1192 0x41012A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1193 0x41012A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1194 0x41012A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1195 0x41012AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1196 0x41012B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1197 0x41012B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1198 0x41012B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1199 0x41012BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1200 0x41012C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1201 0x41012C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1202 0x41012C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1203 0x41012CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1204 0x41012D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1205 0x41012D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1206 0x41012D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1207 0x41012DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1208 0x41012E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1209 0x41012E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1210 0x41012E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1211 0x41012EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1212 0x41012F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1213 0x41012F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1214 0x41012F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1215 0x41012FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1216 0x4101300
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1217 0x4101304
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1218 0x4101308
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1219 0x410130C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1220 0x4101310
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1221 0x4101314
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1222 0x4101318
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1223 0x410131C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1224 0x4101320
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1225 0x4101324
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1226 0x4101328
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1227 0x410132C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1228 0x4101330
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1229 0x4101334
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1230 0x4101338
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1231 0x410133C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1232 0x4101340
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1233 0x4101344
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1234 0x4101348
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1235 0x410134C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1236 0x4101350
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1237 0x4101354
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1238 0x4101358
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1239 0x410135C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1240 0x4101360
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1241 0x4101364
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1242 0x4101368
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1243 0x410136C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1244 0x4101370
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1245 0x4101374
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1246 0x4101378
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1247 0x410137C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1248 0x4101380
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1249 0x4101384
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1250 0x4101388
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1251 0x410138C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1252 0x4101390
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1253 0x4101394
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1254 0x4101398
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1255 0x410139C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1256 0x41013A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1257 0x41013A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1258 0x41013A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1259 0x41013AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1260 0x41013B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1261 0x41013B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1262 0x41013B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1263 0x41013BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1264 0x41013C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1265 0x41013C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1266 0x41013C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1267 0x41013CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1268 0x41013D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1269 0x41013D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1270 0x41013D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1271 0x41013DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1272 0x41013E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1273 0x41013E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1274 0x41013E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1275 0x41013EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1276 0x41013F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1277 0x41013F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1278 0x41013F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1279 0x41013FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1280 0x4101400
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1281 0x4101404
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1282 0x4101408
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1283 0x410140C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1284 0x4101410
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1285 0x4101414
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1286 0x4101418
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1287 0x410141C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1288 0x4101420
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1289 0x4101424
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1290 0x4101428
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1291 0x410142C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1292 0x4101430
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1293 0x4101434
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1294 0x4101438
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1295 0x410143C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1296 0x4101440
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1297 0x4101444
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1298 0x4101448
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1299 0x410144C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1300 0x4101450
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1301 0x4101454
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1302 0x4101458
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1303 0x410145C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1304 0x4101460
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1305 0x4101464
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1306 0x4101468
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1307 0x410146C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1308 0x4101470
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1309 0x4101474
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1310 0x4101478
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1311 0x410147C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1312 0x4101480
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1313 0x4101484
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1314 0x4101488
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1315 0x410148C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1316 0x4101490
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1317 0x4101494
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1318 0x4101498
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1319 0x410149C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1320 0x41014A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1321 0x41014A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1322 0x41014A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1323 0x41014AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1324 0x41014B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1325 0x41014B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1326 0x41014B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1327 0x41014BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1328 0x41014C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1329 0x41014C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1330 0x41014C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1331 0x41014CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1332 0x41014D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1333 0x41014D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1334 0x41014D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1335 0x41014DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1336 0x41014E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1337 0x41014E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1338 0x41014E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1339 0x41014EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1340 0x41014F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1341 0x41014F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1342 0x41014F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1343 0x41014FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1344 0x4101500
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1345 0x4101504
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1346 0x4101508
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1347 0x410150C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1348 0x4101510
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1349 0x4101514
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1350 0x4101518
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1351 0x410151C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1352 0x4101520
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1353 0x4101524
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1354 0x4101528
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1355 0x410152C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1356 0x4101530
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1357 0x4101534
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1358 0x4101538
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1359 0x410153C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1360 0x4101540
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1361 0x4101544
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1362 0x4101548
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1363 0x410154C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1364 0x4101550
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1365 0x4101554
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1366 0x4101558
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1367 0x410155C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1368 0x4101560
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1369 0x4101564
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1370 0x4101568
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1371 0x410156C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1372 0x4101570
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1373 0x4101574
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1374 0x4101578
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1375 0x410157C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1376 0x4101580
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1377 0x4101584
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1378 0x4101588
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1379 0x410158C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1380 0x4101590
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1381 0x4101594
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1382 0x4101598
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1383 0x410159C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1384 0x41015A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1385 0x41015A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1386 0x41015A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1387 0x41015AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1388 0x41015B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1389 0x41015B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1390 0x41015B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1391 0x41015BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1392 0x41015C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1393 0x41015C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1394 0x41015C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1395 0x41015CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1396 0x41015D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1397 0x41015D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1398 0x41015D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1399 0x41015DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1400 0x41015E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1401 0x41015E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1402 0x41015E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1403 0x41015EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1404 0x41015F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1405 0x41015F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1406 0x41015F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1407 0x41015FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1408 0x4101600
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1409 0x4101604
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1410 0x4101608
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1411 0x410160C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1412 0x4101610
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1413 0x4101614
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1414 0x4101618
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1415 0x410161C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1416 0x4101620
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1417 0x4101624
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1418 0x4101628
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1419 0x410162C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1420 0x4101630
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1421 0x4101634
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1422 0x4101638
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1423 0x410163C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1424 0x4101640
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1425 0x4101644
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1426 0x4101648
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1427 0x410164C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1428 0x4101650
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1429 0x4101654
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1430 0x4101658
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1431 0x410165C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1432 0x4101660
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1433 0x4101664
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1434 0x4101668
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1435 0x410166C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1436 0x4101670
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1437 0x4101674
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1438 0x4101678
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1439 0x410167C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1440 0x4101680
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1441 0x4101684
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1442 0x4101688
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1443 0x410168C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1444 0x4101690
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1445 0x4101694
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1446 0x4101698
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1447 0x410169C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1448 0x41016A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1449 0x41016A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1450 0x41016A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1451 0x41016AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1452 0x41016B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1453 0x41016B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1454 0x41016B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1455 0x41016BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1456 0x41016C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1457 0x41016C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1458 0x41016C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1459 0x41016CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1460 0x41016D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1461 0x41016D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1462 0x41016D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1463 0x41016DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1464 0x41016E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1465 0x41016E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1466 0x41016E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1467 0x41016EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1468 0x41016F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1469 0x41016F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1470 0x41016F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1471 0x41016FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1472 0x4101700
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1473 0x4101704
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1474 0x4101708
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1475 0x410170C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1476 0x4101710
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1477 0x4101714
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1478 0x4101718
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1479 0x410171C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1480 0x4101720
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1481 0x4101724
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1482 0x4101728
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1483 0x410172C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1484 0x4101730
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1485 0x4101734
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1486 0x4101738
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1487 0x410173C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1488 0x4101740
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1489 0x4101744
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1490 0x4101748
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1491 0x410174C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1492 0x4101750
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1493 0x4101754
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1494 0x4101758
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1495 0x410175C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1496 0x4101760
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1497 0x4101764
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1498 0x4101768
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1499 0x410176C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1500 0x4101770
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1501 0x4101774
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1502 0x4101778
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1503 0x410177C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1504 0x4101780
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1505 0x4101784
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1506 0x4101788
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1507 0x410178C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1508 0x4101790
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1509 0x4101794
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1510 0x4101798
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1511 0x410179C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1512 0x41017A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1513 0x41017A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1514 0x41017A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1515 0x41017AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1516 0x41017B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1517 0x41017B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1518 0x41017B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1519 0x41017BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1520 0x41017C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1521 0x41017C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1522 0x41017C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1523 0x41017CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1524 0x41017D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1525 0x41017D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1526 0x41017D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1527 0x41017DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1528 0x41017E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1529 0x41017E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1530 0x41017E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1531 0x41017EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1532 0x41017F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1533 0x41017F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1534 0x41017F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1535 0x41017FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1536 0x4101800
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1537 0x4101804
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1538 0x4101808
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1539 0x410180C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1540 0x4101810
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1541 0x4101814
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1542 0x4101818
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1543 0x410181C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1544 0x4101820
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1545 0x4101824
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1546 0x4101828
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1547 0x410182C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1548 0x4101830
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1549 0x4101834
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1550 0x4101838
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1551 0x410183C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1552 0x4101840
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1553 0x4101844
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1554 0x4101848
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1555 0x410184C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1556 0x4101850
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1557 0x4101854
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1558 0x4101858
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1559 0x410185C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1560 0x4101860
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1561 0x4101864
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1562 0x4101868
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1563 0x410186C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1564 0x4101870
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1565 0x4101874
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1566 0x4101878
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1567 0x410187C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1568 0x4101880
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1569 0x4101884
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1570 0x4101888
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1571 0x410188C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1572 0x4101890
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1573 0x4101894
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1574 0x4101898
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1575 0x410189C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1576 0x41018A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1577 0x41018A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1578 0x41018A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1579 0x41018AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1580 0x41018B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1581 0x41018B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1582 0x41018B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1583 0x41018BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1584 0x41018C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1585 0x41018C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1586 0x41018C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1587 0x41018CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1588 0x41018D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1589 0x41018D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1590 0x41018D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1591 0x41018DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1592 0x41018E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1593 0x41018E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1594 0x41018E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1595 0x41018EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1596 0x41018F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1597 0x41018F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1598 0x41018F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1599 0x41018FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1600 0x4101900
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1601 0x4101904
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1602 0x4101908
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1603 0x410190C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1604 0x4101910
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1605 0x4101914
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1606 0x4101918
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1607 0x410191C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1608 0x4101920
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1609 0x4101924
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1610 0x4101928
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1611 0x410192C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1612 0x4101930
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1613 0x4101934
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1614 0x4101938
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1615 0x410193C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1616 0x4101940
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1617 0x4101944
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1618 0x4101948
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1619 0x410194C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1620 0x4101950
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1621 0x4101954
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1622 0x4101958
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1623 0x410195C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1624 0x4101960
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1625 0x4101964
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1626 0x4101968
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1627 0x410196C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1628 0x4101970
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1629 0x4101974
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1630 0x4101978
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1631 0x410197C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1632 0x4101980
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1633 0x4101984
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1634 0x4101988
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1635 0x410198C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1636 0x4101990
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1637 0x4101994
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1638 0x4101998
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1639 0x410199C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1640 0x41019A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1641 0x41019A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1642 0x41019A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1643 0x41019AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1644 0x41019B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1645 0x41019B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1646 0x41019B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1647 0x41019BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1648 0x41019C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1649 0x41019C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1650 0x41019C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1651 0x41019CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1652 0x41019D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1653 0x41019D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1654 0x41019D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1655 0x41019DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1656 0x41019E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1657 0x41019E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1658 0x41019E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1659 0x41019EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1660 0x41019F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1661 0x41019F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1662 0x41019F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1663 0x41019FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1664 0x4101A00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1665 0x4101A04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1666 0x4101A08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1667 0x4101A0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1668 0x4101A10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1669 0x4101A14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1670 0x4101A18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1671 0x4101A1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1672 0x4101A20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1673 0x4101A24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1674 0x4101A28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1675 0x4101A2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1676 0x4101A30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1677 0x4101A34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1678 0x4101A38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1679 0x4101A3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1680 0x4101A40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1681 0x4101A44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1682 0x4101A48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1683 0x4101A4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1684 0x4101A50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1685 0x4101A54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1686 0x4101A58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1687 0x4101A5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1688 0x4101A60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1689 0x4101A64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1690 0x4101A68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1691 0x4101A6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1692 0x4101A70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1693 0x4101A74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1694 0x4101A78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1695 0x4101A7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1696 0x4101A80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1697 0x4101A84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1698 0x4101A88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1699 0x4101A8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1700 0x4101A90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1701 0x4101A94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1702 0x4101A98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1703 0x4101A9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1704 0x4101AA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1705 0x4101AA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1706 0x4101AA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1707 0x4101AAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1708 0x4101AB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1709 0x4101AB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1710 0x4101AB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1711 0x4101ABC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1712 0x4101AC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1713 0x4101AC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1714 0x4101AC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1715 0x4101ACC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1716 0x4101AD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1717 0x4101AD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1718 0x4101AD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1719 0x4101ADC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1720 0x4101AE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1721 0x4101AE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1722 0x4101AE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1723 0x4101AEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1724 0x4101AF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1725 0x4101AF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1726 0x4101AF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1727 0x4101AFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1728 0x4101B00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1729 0x4101B04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1730 0x4101B08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1731 0x4101B0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1732 0x4101B10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1733 0x4101B14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1734 0x4101B18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1735 0x4101B1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1736 0x4101B20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1737 0x4101B24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1738 0x4101B28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1739 0x4101B2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1740 0x4101B30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1741 0x4101B34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1742 0x4101B38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1743 0x4101B3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1744 0x4101B40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1745 0x4101B44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1746 0x4101B48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1747 0x4101B4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1748 0x4101B50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1749 0x4101B54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1750 0x4101B58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1751 0x4101B5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1752 0x4101B60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1753 0x4101B64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1754 0x4101B68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1755 0x4101B6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1756 0x4101B70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1757 0x4101B74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1758 0x4101B78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1759 0x4101B7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1760 0x4101B80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1761 0x4101B84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1762 0x4101B88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1763 0x4101B8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1764 0x4101B90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1765 0x4101B94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1766 0x4101B98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1767 0x4101B9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1768 0x4101BA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1769 0x4101BA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1770 0x4101BA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1771 0x4101BAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1772 0x4101BB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1773 0x4101BB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1774 0x4101BB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1775 0x4101BBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1776 0x4101BC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1777 0x4101BC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1778 0x4101BC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1779 0x4101BCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1780 0x4101BD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1781 0x4101BD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1782 0x4101BD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1783 0x4101BDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1784 0x4101BE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1785 0x4101BE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1786 0x4101BE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1787 0x4101BEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1788 0x4101BF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1789 0x4101BF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1790 0x4101BF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1791 0x4101BFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1792 0x4101C00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1793 0x4101C04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1794 0x4101C08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1795 0x4101C0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1796 0x4101C10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1797 0x4101C14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1798 0x4101C18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1799 0x4101C1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1800 0x4101C20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1801 0x4101C24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1802 0x4101C28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1803 0x4101C2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1804 0x4101C30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1805 0x4101C34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1806 0x4101C38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1807 0x4101C3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1808 0x4101C40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1809 0x4101C44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1810 0x4101C48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1811 0x4101C4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1812 0x4101C50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1813 0x4101C54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1814 0x4101C58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1815 0x4101C5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1816 0x4101C60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1817 0x4101C64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1818 0x4101C68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1819 0x4101C6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1820 0x4101C70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1821 0x4101C74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1822 0x4101C78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1823 0x4101C7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1824 0x4101C80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1825 0x4101C84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1826 0x4101C88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1827 0x4101C8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1828 0x4101C90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1829 0x4101C94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1830 0x4101C98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1831 0x4101C9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1832 0x4101CA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1833 0x4101CA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1834 0x4101CA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1835 0x4101CAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1836 0x4101CB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1837 0x4101CB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1838 0x4101CB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1839 0x4101CBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1840 0x4101CC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1841 0x4101CC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1842 0x4101CC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1843 0x4101CCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1844 0x4101CD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1845 0x4101CD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1846 0x4101CD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1847 0x4101CDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1848 0x4101CE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1849 0x4101CE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1850 0x4101CE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1851 0x4101CEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1852 0x4101CF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1853 0x4101CF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1854 0x4101CF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1855 0x4101CFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1856 0x4101D00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1857 0x4101D04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1858 0x4101D08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1859 0x4101D0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1860 0x4101D10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1861 0x4101D14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1862 0x4101D18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1863 0x4101D1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1864 0x4101D20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1865 0x4101D24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1866 0x4101D28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1867 0x4101D2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1868 0x4101D30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1869 0x4101D34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1870 0x4101D38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1871 0x4101D3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1872 0x4101D40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1873 0x4101D44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1874 0x4101D48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1875 0x4101D4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1876 0x4101D50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1877 0x4101D54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1878 0x4101D58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1879 0x4101D5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1880 0x4101D60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1881 0x4101D64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1882 0x4101D68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1883 0x4101D6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1884 0x4101D70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1885 0x4101D74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1886 0x4101D78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1887 0x4101D7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1888 0x4101D80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1889 0x4101D84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1890 0x4101D88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1891 0x4101D8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1892 0x4101D90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1893 0x4101D94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1894 0x4101D98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1895 0x4101D9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1896 0x4101DA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1897 0x4101DA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1898 0x4101DA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1899 0x4101DAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1900 0x4101DB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1901 0x4101DB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1902 0x4101DB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1903 0x4101DBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1904 0x4101DC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1905 0x4101DC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1906 0x4101DC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1907 0x4101DCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1908 0x4101DD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1909 0x4101DD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1910 0x4101DD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1911 0x4101DDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1912 0x4101DE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1913 0x4101DE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1914 0x4101DE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1915 0x4101DEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1916 0x4101DF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1917 0x4101DF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1918 0x4101DF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1919 0x4101DFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1920 0x4101E00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1921 0x4101E04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1922 0x4101E08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1923 0x4101E0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1924 0x4101E10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1925 0x4101E14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1926 0x4101E18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1927 0x4101E1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1928 0x4101E20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1929 0x4101E24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1930 0x4101E28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1931 0x4101E2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1932 0x4101E30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1933 0x4101E34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1934 0x4101E38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1935 0x4101E3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1936 0x4101E40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1937 0x4101E44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1938 0x4101E48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1939 0x4101E4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1940 0x4101E50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1941 0x4101E54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1942 0x4101E58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1943 0x4101E5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1944 0x4101E60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1945 0x4101E64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1946 0x4101E68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1947 0x4101E6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1948 0x4101E70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1949 0x4101E74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1950 0x4101E78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1951 0x4101E7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1952 0x4101E80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1953 0x4101E84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1954 0x4101E88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1955 0x4101E8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1956 0x4101E90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1957 0x4101E94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1958 0x4101E98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1959 0x4101E9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1960 0x4101EA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1961 0x4101EA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1962 0x4101EA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1963 0x4101EAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1964 0x4101EB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1965 0x4101EB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1966 0x4101EB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1967 0x4101EBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1968 0x4101EC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1969 0x4101EC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1970 0x4101EC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1971 0x4101ECC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1972 0x4101ED0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1973 0x4101ED4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1974 0x4101ED8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1975 0x4101EDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1976 0x4101EE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1977 0x4101EE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1978 0x4101EE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1979 0x4101EEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1980 0x4101EF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1981 0x4101EF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1982 0x4101EF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1983 0x4101EFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1984 0x4101F00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1985 0x4101F04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1986 0x4101F08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1987 0x4101F0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1988 0x4101F10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1989 0x4101F14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1990 0x4101F18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1991 0x4101F1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1992 0x4101F20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1993 0x4101F24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1994 0x4101F28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1995 0x4101F2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1996 0x4101F30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1997 0x4101F34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1998 0x4101F38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1999 0x4101F3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2000 0x4101F40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2001 0x4101F44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2002 0x4101F48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2003 0x4101F4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2004 0x4101F50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2005 0x4101F54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2006 0x4101F58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2007 0x4101F5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2008 0x4101F60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2009 0x4101F64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2010 0x4101F68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2011 0x4101F6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2012 0x4101F70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2013 0x4101F74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2014 0x4101F78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2015 0x4101F7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2016 0x4101F80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2017 0x4101F84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2018 0x4101F88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2019 0x4101F8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2020 0x4101F90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2021 0x4101F94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2022 0x4101F98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2023 0x4101F9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2024 0x4101FA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2025 0x4101FA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2026 0x4101FA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2027 0x4101FAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2028 0x4101FB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2029 0x4101FB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2030 0x4101FB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2031 0x4101FBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2032 0x4101FC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2033 0x4101FC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2034 0x4101FC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2035 0x4101FCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2036 0x4101FD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2037 0x4101FD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2038 0x4101FD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2039 0x4101FDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2040 0x4101FE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2041 0x4101FE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2042 0x4101FE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2043 0x4101FEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2044 0x4101FF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2045 0x4101FF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2046 0x4101FF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2047 0x4101FFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2048 0x4102000
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2049 0x4102004
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2050 0x4102008
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2051 0x410200C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2052 0x4102010
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2053 0x4102014
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2054 0x4102018
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2055 0x410201C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2056 0x4102020
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2057 0x4102024
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2058 0x4102028
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2059 0x410202C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2060 0x4102030
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2061 0x4102034
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2062 0x4102038
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2063 0x410203C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2064 0x4102040
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2065 0x4102044
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2066 0x4102048
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2067 0x410204C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2068 0x4102050
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2069 0x4102054
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2070 0x4102058
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2071 0x410205C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2072 0x4102060
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2073 0x4102064
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2074 0x4102068
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2075 0x410206C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2076 0x4102070
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2077 0x4102074
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2078 0x4102078
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2079 0x410207C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2080 0x4102080
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2081 0x4102084
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2082 0x4102088
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2083 0x410208C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2084 0x4102090
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2085 0x4102094
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2086 0x4102098
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2087 0x410209C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2088 0x41020A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2089 0x41020A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2090 0x41020A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2091 0x41020AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2092 0x41020B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2093 0x41020B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2094 0x41020B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2095 0x41020BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2096 0x41020C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2097 0x41020C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2098 0x41020C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2099 0x41020CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2100 0x41020D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2101 0x41020D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2102 0x41020D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2103 0x41020DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2104 0x41020E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2105 0x41020E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2106 0x41020E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2107 0x41020EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2108 0x41020F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2109 0x41020F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2110 0x41020F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2111 0x41020FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2112 0x4102100
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2113 0x4102104
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2114 0x4102108
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2115 0x410210C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2116 0x4102110
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2117 0x4102114
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2118 0x4102118
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2119 0x410211C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2120 0x4102120
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2121 0x4102124
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2122 0x4102128
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2123 0x410212C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2124 0x4102130
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2125 0x4102134
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2126 0x4102138
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2127 0x410213C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2128 0x4102140
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2129 0x4102144
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2130 0x4102148
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2131 0x410214C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2132 0x4102150
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2133 0x4102154
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2134 0x4102158
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2135 0x410215C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2136 0x4102160
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2137 0x4102164
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2138 0x4102168
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2139 0x410216C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2140 0x4102170
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2141 0x4102174
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2142 0x4102178
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2143 0x410217C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2144 0x4102180
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2145 0x4102184
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2146 0x4102188
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2147 0x410218C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2148 0x4102190
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2149 0x4102194
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2150 0x4102198
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2151 0x410219C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2152 0x41021A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2153 0x41021A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2154 0x41021A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2155 0x41021AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2156 0x41021B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2157 0x41021B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2158 0x41021B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2159 0x41021BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2160 0x41021C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2161 0x41021C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2162 0x41021C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2163 0x41021CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2164 0x41021D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2165 0x41021D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2166 0x41021D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2167 0x41021DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2168 0x41021E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2169 0x41021E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2170 0x41021E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2171 0x41021EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2172 0x41021F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2173 0x41021F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2174 0x41021F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2175 0x41021FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2176 0x4102200
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2177 0x4102204
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2178 0x4102208
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2179 0x410220C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2180 0x4102210
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2181 0x4102214
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2182 0x4102218
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2183 0x410221C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2184 0x4102220
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2185 0x4102224
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2186 0x4102228
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2187 0x410222C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2188 0x4102230
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2189 0x4102234
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2190 0x4102238
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2191 0x410223C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2192 0x4102240
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2193 0x4102244
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2194 0x4102248
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2195 0x410224C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2196 0x4102250
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2197 0x4102254
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2198 0x4102258
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2199 0x410225C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2200 0x4102260
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2201 0x4102264
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2202 0x4102268
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2203 0x410226C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2204 0x4102270
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2205 0x4102274
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2206 0x4102278
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2207 0x410227C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2208 0x4102280
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2209 0x4102284
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2210 0x4102288
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2211 0x410228C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2212 0x4102290
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2213 0x4102294
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2214 0x4102298
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2215 0x410229C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2216 0x41022A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2217 0x41022A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2218 0x41022A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2219 0x41022AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2220 0x41022B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2221 0x41022B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2222 0x41022B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2223 0x41022BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2224 0x41022C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2225 0x41022C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2226 0x41022C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2227 0x41022CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2228 0x41022D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2229 0x41022D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2230 0x41022D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2231 0x41022DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2232 0x41022E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2233 0x41022E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2234 0x41022E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2235 0x41022EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2236 0x41022F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2237 0x41022F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2238 0x41022F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2239 0x41022FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2240 0x4102300
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2241 0x4102304
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2242 0x4102308
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2243 0x410230C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2244 0x4102310
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2245 0x4102314
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2246 0x4102318
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2247 0x410231C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2248 0x4102320
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2249 0x4102324
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2250 0x4102328
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2251 0x410232C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2252 0x4102330
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2253 0x4102334
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2254 0x4102338
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2255 0x410233C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2256 0x4102340
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2257 0x4102344
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2258 0x4102348
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2259 0x410234C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2260 0x4102350
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2261 0x4102354
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2262 0x4102358
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2263 0x410235C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2264 0x4102360
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2265 0x4102364
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2266 0x4102368
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2267 0x410236C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2268 0x4102370
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2269 0x4102374
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2270 0x4102378
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2271 0x410237C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2272 0x4102380
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2273 0x4102384
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2274 0x4102388
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2275 0x410238C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2276 0x4102390
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2277 0x4102394
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2278 0x4102398
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2279 0x410239C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2280 0x41023A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2281 0x41023A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2282 0x41023A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2283 0x41023AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2284 0x41023B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2285 0x41023B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2286 0x41023B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2287 0x41023BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2288 0x41023C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2289 0x41023C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2290 0x41023C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2291 0x41023CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2292 0x41023D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2293 0x41023D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2294 0x41023D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2295 0x41023DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2296 0x41023E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2297 0x41023E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2298 0x41023E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2299 0x41023EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2300 0x41023F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2301 0x41023F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2302 0x41023F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2303 0x41023FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2304 0x4102400
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2305 0x4102404
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2306 0x4102408
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2307 0x410240C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2308 0x4102410
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2309 0x4102414
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2310 0x4102418
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2311 0x410241C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2312 0x4102420
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2313 0x4102424
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2314 0x4102428
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2315 0x410242C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2316 0x4102430
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2317 0x4102434
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2318 0x4102438
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2319 0x410243C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2320 0x4102440
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2321 0x4102444
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2322 0x4102448
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2323 0x410244C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2324 0x4102450
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2325 0x4102454
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2326 0x4102458
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2327 0x410245C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2328 0x4102460
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2329 0x4102464
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2330 0x4102468
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2331 0x410246C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2332 0x4102470
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2333 0x4102474
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2334 0x4102478
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2335 0x410247C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2336 0x4102480
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2337 0x4102484
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2338 0x4102488
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2339 0x410248C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2340 0x4102490
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2341 0x4102494
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2342 0x4102498
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2343 0x410249C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2344 0x41024A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2345 0x41024A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2346 0x41024A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2347 0x41024AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2348 0x41024B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2349 0x41024B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2350 0x41024B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2351 0x41024BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2352 0x41024C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2353 0x41024C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2354 0x41024C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2355 0x41024CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2356 0x41024D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2357 0x41024D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2358 0x41024D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2359 0x41024DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2360 0x41024E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2361 0x41024E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2362 0x41024E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2363 0x41024EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2364 0x41024F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2365 0x41024F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2366 0x41024F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2367 0x41024FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2368 0x4102500
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2369 0x4102504
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2370 0x4102508
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2371 0x410250C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2372 0x4102510
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2373 0x4102514
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2374 0x4102518
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2375 0x410251C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2376 0x4102520
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2377 0x4102524
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2378 0x4102528
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2379 0x410252C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2380 0x4102530
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2381 0x4102534
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2382 0x4102538
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2383 0x410253C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2384 0x4102540
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2385 0x4102544
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2386 0x4102548
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2387 0x410254C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2388 0x4102550
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2389 0x4102554
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2390 0x4102558
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2391 0x410255C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2392 0x4102560
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2393 0x4102564
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2394 0x4102568
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2395 0x410256C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2396 0x4102570
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2397 0x4102574
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2398 0x4102578
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2399 0x410257C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2400 0x4102580
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2401 0x4102584
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2402 0x4102588
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2403 0x410258C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2404 0x4102590
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2405 0x4102594
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2406 0x4102598
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2407 0x410259C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2408 0x41025A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2409 0x41025A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2410 0x41025A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2411 0x41025AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2412 0x41025B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2413 0x41025B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2414 0x41025B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2415 0x41025BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2416 0x41025C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2417 0x41025C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2418 0x41025C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2419 0x41025CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2420 0x41025D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2421 0x41025D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2422 0x41025D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2423 0x41025DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2424 0x41025E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2425 0x41025E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2426 0x41025E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2427 0x41025EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2428 0x41025F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2429 0x41025F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2430 0x41025F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2431 0x41025FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2432 0x4102600
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2433 0x4102604
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2434 0x4102608
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2435 0x410260C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2436 0x4102610
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2437 0x4102614
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2438 0x4102618
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2439 0x410261C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2440 0x4102620
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2441 0x4102624
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2442 0x4102628
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2443 0x410262C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2444 0x4102630
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2445 0x4102634
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2446 0x4102638
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2447 0x410263C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2448 0x4102640
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2449 0x4102644
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2450 0x4102648
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2451 0x410264C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2452 0x4102650
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2453 0x4102654
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2454 0x4102658
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2455 0x410265C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2456 0x4102660
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2457 0x4102664
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2458 0x4102668
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2459 0x410266C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2460 0x4102670
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2461 0x4102674
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2462 0x4102678
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2463 0x410267C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2464 0x4102680
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2465 0x4102684
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2466 0x4102688
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2467 0x410268C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2468 0x4102690
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2469 0x4102694
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2470 0x4102698
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2471 0x410269C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2472 0x41026A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2473 0x41026A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2474 0x41026A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2475 0x41026AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2476 0x41026B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2477 0x41026B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2478 0x41026B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2479 0x41026BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2480 0x41026C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2481 0x41026C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2482 0x41026C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2483 0x41026CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2484 0x41026D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2485 0x41026D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2486 0x41026D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2487 0x41026DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2488 0x41026E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2489 0x41026E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2490 0x41026E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2491 0x41026EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2492 0x41026F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2493 0x41026F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2494 0x41026F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2495 0x41026FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2496 0x4102700
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2497 0x4102704
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2498 0x4102708
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2499 0x410270C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2500 0x4102710
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2501 0x4102714
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2502 0x4102718
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2503 0x410271C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2504 0x4102720
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2505 0x4102724
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2506 0x4102728
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2507 0x410272C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2508 0x4102730
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2509 0x4102734
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2510 0x4102738
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2511 0x410273C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2512 0x4102740
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2513 0x4102744
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2514 0x4102748
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2515 0x410274C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2516 0x4102750
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2517 0x4102754
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2518 0x4102758
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2519 0x410275C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2520 0x4102760
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2521 0x4102764
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2522 0x4102768
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2523 0x410276C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2524 0x4102770
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2525 0x4102774
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2526 0x4102778
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2527 0x410277C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2528 0x4102780
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2529 0x4102784
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2530 0x4102788
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2531 0x410278C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2532 0x4102790
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2533 0x4102794
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2534 0x4102798
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2535 0x410279C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2536 0x41027A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2537 0x41027A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2538 0x41027A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2539 0x41027AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2540 0x41027B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2541 0x41027B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2542 0x41027B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2543 0x41027BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2544 0x41027C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2545 0x41027C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2546 0x41027C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2547 0x41027CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2548 0x41027D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2549 0x41027D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2550 0x41027D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2551 0x41027DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2552 0x41027E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2553 0x41027E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2554 0x41027E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2555 0x41027EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2556 0x41027F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2557 0x41027F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2558 0x41027F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2559 0x41027FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2560 0x4102800
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2561 0x4102804
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2562 0x4102808
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2563 0x410280C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2564 0x4102810
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2565 0x4102814
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2566 0x4102818
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2567 0x410281C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2568 0x4102820
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2569 0x4102824
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2570 0x4102828
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2571 0x410282C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2572 0x4102830
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2573 0x4102834
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2574 0x4102838
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2575 0x410283C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2576 0x4102840
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2577 0x4102844
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2578 0x4102848
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2579 0x410284C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2580 0x4102850
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2581 0x4102854
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2582 0x4102858
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2583 0x410285C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2584 0x4102860
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2585 0x4102864
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2586 0x4102868
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2587 0x410286C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2588 0x4102870
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2589 0x4102874
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2590 0x4102878
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2591 0x410287C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2592 0x4102880
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2593 0x4102884
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2594 0x4102888
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2595 0x410288C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2596 0x4102890
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2597 0x4102894
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2598 0x4102898
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2599 0x410289C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2600 0x41028A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2601 0x41028A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2602 0x41028A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2603 0x41028AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2604 0x41028B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2605 0x41028B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2606 0x41028B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2607 0x41028BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2608 0x41028C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2609 0x41028C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2610 0x41028C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2611 0x41028CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2612 0x41028D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2613 0x41028D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2614 0x41028D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2615 0x41028DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2616 0x41028E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2617 0x41028E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2618 0x41028E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2619 0x41028EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2620 0x41028F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2621 0x41028F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2622 0x41028F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2623 0x41028FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2624 0x4102900
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2625 0x4102904
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2626 0x4102908
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2627 0x410290C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2628 0x4102910
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2629 0x4102914
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2630 0x4102918
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2631 0x410291C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2632 0x4102920
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2633 0x4102924
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2634 0x4102928
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2635 0x410292C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2636 0x4102930
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2637 0x4102934
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2638 0x4102938
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2639 0x410293C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2640 0x4102940
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2641 0x4102944
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2642 0x4102948
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2643 0x410294C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2644 0x4102950
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2645 0x4102954
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2646 0x4102958
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2647 0x410295C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2648 0x4102960
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2649 0x4102964
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2650 0x4102968
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2651 0x410296C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2652 0x4102970
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2653 0x4102974
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2654 0x4102978
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2655 0x410297C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2656 0x4102980
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2657 0x4102984
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2658 0x4102988
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2659 0x410298C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2660 0x4102990
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2661 0x4102994
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2662 0x4102998
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2663 0x410299C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2664 0x41029A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2665 0x41029A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2666 0x41029A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2667 0x41029AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2668 0x41029B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2669 0x41029B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2670 0x41029B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2671 0x41029BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2672 0x41029C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2673 0x41029C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2674 0x41029C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2675 0x41029CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2676 0x41029D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2677 0x41029D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2678 0x41029D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2679 0x41029DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2680 0x41029E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2681 0x41029E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2682 0x41029E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2683 0x41029EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2684 0x41029F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2685 0x41029F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2686 0x41029F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2687 0x41029FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2688 0x4102A00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2689 0x4102A04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2690 0x4102A08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2691 0x4102A0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2692 0x4102A10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2693 0x4102A14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2694 0x4102A18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2695 0x4102A1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2696 0x4102A20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2697 0x4102A24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2698 0x4102A28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2699 0x4102A2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2700 0x4102A30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2701 0x4102A34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2702 0x4102A38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2703 0x4102A3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2704 0x4102A40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2705 0x4102A44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2706 0x4102A48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2707 0x4102A4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2708 0x4102A50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2709 0x4102A54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2710 0x4102A58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2711 0x4102A5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2712 0x4102A60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2713 0x4102A64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2714 0x4102A68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2715 0x4102A6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2716 0x4102A70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2717 0x4102A74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2718 0x4102A78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2719 0x4102A7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2720 0x4102A80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2721 0x4102A84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2722 0x4102A88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2723 0x4102A8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2724 0x4102A90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2725 0x4102A94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2726 0x4102A98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2727 0x4102A9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2728 0x4102AA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2729 0x4102AA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2730 0x4102AA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2731 0x4102AAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2732 0x4102AB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2733 0x4102AB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2734 0x4102AB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2735 0x4102ABC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2736 0x4102AC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2737 0x4102AC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2738 0x4102AC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2739 0x4102ACC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2740 0x4102AD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2741 0x4102AD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2742 0x4102AD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2743 0x4102ADC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2744 0x4102AE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2745 0x4102AE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2746 0x4102AE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2747 0x4102AEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2748 0x4102AF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2749 0x4102AF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2750 0x4102AF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2751 0x4102AFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2752 0x4102B00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2753 0x4102B04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2754 0x4102B08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2755 0x4102B0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2756 0x4102B10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2757 0x4102B14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2758 0x4102B18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2759 0x4102B1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2760 0x4102B20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2761 0x4102B24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2762 0x4102B28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2763 0x4102B2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2764 0x4102B30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2765 0x4102B34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2766 0x4102B38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2767 0x4102B3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2768 0x4102B40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2769 0x4102B44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2770 0x4102B48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2771 0x4102B4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2772 0x4102B50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2773 0x4102B54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2774 0x4102B58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2775 0x4102B5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2776 0x4102B60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2777 0x4102B64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2778 0x4102B68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2779 0x4102B6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2780 0x4102B70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2781 0x4102B74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2782 0x4102B78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2783 0x4102B7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2784 0x4102B80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2785 0x4102B84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2786 0x4102B88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2787 0x4102B8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2788 0x4102B90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2789 0x4102B94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2790 0x4102B98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2791 0x4102B9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2792 0x4102BA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2793 0x4102BA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2794 0x4102BA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2795 0x4102BAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2796 0x4102BB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2797 0x4102BB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2798 0x4102BB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2799 0x4102BBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2800 0x4102BC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2801 0x4102BC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2802 0x4102BC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2803 0x4102BCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2804 0x4102BD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2805 0x4102BD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2806 0x4102BD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2807 0x4102BDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2808 0x4102BE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2809 0x4102BE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2810 0x4102BE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2811 0x4102BEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2812 0x4102BF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2813 0x4102BF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2814 0x4102BF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2815 0x4102BFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2816 0x4102C00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2817 0x4102C04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2818 0x4102C08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2819 0x4102C0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2820 0x4102C10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2821 0x4102C14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2822 0x4102C18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2823 0x4102C1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2824 0x4102C20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2825 0x4102C24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2826 0x4102C28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2827 0x4102C2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2828 0x4102C30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2829 0x4102C34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2830 0x4102C38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2831 0x4102C3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2832 0x4102C40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2833 0x4102C44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2834 0x4102C48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2835 0x4102C4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2836 0x4102C50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2837 0x4102C54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2838 0x4102C58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2839 0x4102C5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2840 0x4102C60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2841 0x4102C64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2842 0x4102C68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2843 0x4102C6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2844 0x4102C70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2845 0x4102C74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2846 0x4102C78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2847 0x4102C7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2848 0x4102C80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2849 0x4102C84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2850 0x4102C88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2851 0x4102C8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2852 0x4102C90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2853 0x4102C94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2854 0x4102C98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2855 0x4102C9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2856 0x4102CA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2857 0x4102CA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2858 0x4102CA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2859 0x4102CAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2860 0x4102CB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2861 0x4102CB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2862 0x4102CB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2863 0x4102CBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2864 0x4102CC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2865 0x4102CC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2866 0x4102CC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2867 0x4102CCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2868 0x4102CD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2869 0x4102CD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2870 0x4102CD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2871 0x4102CDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2872 0x4102CE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2873 0x4102CE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2874 0x4102CE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2875 0x4102CEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2876 0x4102CF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2877 0x4102CF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2878 0x4102CF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2879 0x4102CFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2880 0x4102D00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2881 0x4102D04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2882 0x4102D08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2883 0x4102D0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2884 0x4102D10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2885 0x4102D14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2886 0x4102D18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2887 0x4102D1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2888 0x4102D20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2889 0x4102D24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2890 0x4102D28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2891 0x4102D2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2892 0x4102D30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2893 0x4102D34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2894 0x4102D38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2895 0x4102D3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2896 0x4102D40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2897 0x4102D44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2898 0x4102D48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2899 0x4102D4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2900 0x4102D50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2901 0x4102D54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2902 0x4102D58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2903 0x4102D5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2904 0x4102D60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2905 0x4102D64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2906 0x4102D68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2907 0x4102D6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2908 0x4102D70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2909 0x4102D74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2910 0x4102D78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2911 0x4102D7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2912 0x4102D80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2913 0x4102D84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2914 0x4102D88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2915 0x4102D8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2916 0x4102D90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2917 0x4102D94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2918 0x4102D98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2919 0x4102D9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2920 0x4102DA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2921 0x4102DA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2922 0x4102DA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2923 0x4102DAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2924 0x4102DB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2925 0x4102DB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2926 0x4102DB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2927 0x4102DBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2928 0x4102DC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2929 0x4102DC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2930 0x4102DC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2931 0x4102DCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2932 0x4102DD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2933 0x4102DD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2934 0x4102DD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2935 0x4102DDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2936 0x4102DE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2937 0x4102DE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2938 0x4102DE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2939 0x4102DEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2940 0x4102DF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2941 0x4102DF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2942 0x4102DF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2943 0x4102DFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2944 0x4102E00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2945 0x4102E04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2946 0x4102E08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2947 0x4102E0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2948 0x4102E10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2949 0x4102E14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2950 0x4102E18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2951 0x4102E1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2952 0x4102E20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2953 0x4102E24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2954 0x4102E28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2955 0x4102E2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2956 0x4102E30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2957 0x4102E34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2958 0x4102E38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2959 0x4102E3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2960 0x4102E40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2961 0x4102E44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2962 0x4102E48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2963 0x4102E4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2964 0x4102E50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2965 0x4102E54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2966 0x4102E58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2967 0x4102E5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2968 0x4102E60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2969 0x4102E64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2970 0x4102E68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2971 0x4102E6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2972 0x4102E70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2973 0x4102E74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2974 0x4102E78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2975 0x4102E7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2976 0x4102E80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2977 0x4102E84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2978 0x4102E88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2979 0x4102E8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2980 0x4102E90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2981 0x4102E94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2982 0x4102E98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2983 0x4102E9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2984 0x4102EA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2985 0x4102EA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2986 0x4102EA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2987 0x4102EAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2988 0x4102EB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2989 0x4102EB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2990 0x4102EB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2991 0x4102EBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2992 0x4102EC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2993 0x4102EC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2994 0x4102EC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2995 0x4102ECC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2996 0x4102ED0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2997 0x4102ED4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2998 0x4102ED8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2999 0x4102EDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3000 0x4102EE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3001 0x4102EE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3002 0x4102EE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3003 0x4102EEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3004 0x4102EF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3005 0x4102EF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3006 0x4102EF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3007 0x4102EFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3008 0x4102F00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3009 0x4102F04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3010 0x4102F08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3011 0x4102F0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3012 0x4102F10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3013 0x4102F14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3014 0x4102F18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3015 0x4102F1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3016 0x4102F20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3017 0x4102F24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3018 0x4102F28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3019 0x4102F2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3020 0x4102F30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3021 0x4102F34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3022 0x4102F38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3023 0x4102F3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3024 0x4102F40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3025 0x4102F44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3026 0x4102F48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3027 0x4102F4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3028 0x4102F50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3029 0x4102F54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3030 0x4102F58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3031 0x4102F5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3032 0x4102F60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3033 0x4102F64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3034 0x4102F68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3035 0x4102F6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3036 0x4102F70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3037 0x4102F74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3038 0x4102F78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3039 0x4102F7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3040 0x4102F80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3041 0x4102F84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3042 0x4102F88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3043 0x4102F8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3044 0x4102F90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3045 0x4102F94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3046 0x4102F98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3047 0x4102F9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3048 0x4102FA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3049 0x4102FA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3050 0x4102FA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3051 0x4102FAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3052 0x4102FB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3053 0x4102FB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3054 0x4102FB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3055 0x4102FBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3056 0x4102FC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3057 0x4102FC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3058 0x4102FC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3059 0x4102FCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3060 0x4102FD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3061 0x4102FD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3062 0x4102FD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3063 0x4102FDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3064 0x4102FE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3065 0x4102FE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3066 0x4102FE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3067 0x4102FEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3068 0x4102FF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3069 0x4102FF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3070 0x4102FF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3071 0x4102FFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3072 0x4103000
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3073 0x4103004
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3074 0x4103008
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3075 0x410300C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3076 0x4103010
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3077 0x4103014
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3078 0x4103018
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3079 0x410301C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3080 0x4103020
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3081 0x4103024
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3082 0x4103028
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3083 0x410302C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3084 0x4103030
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3085 0x4103034
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3086 0x4103038
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3087 0x410303C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3088 0x4103040
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3089 0x4103044
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3090 0x4103048
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3091 0x410304C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3092 0x4103050
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3093 0x4103054
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3094 0x4103058
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3095 0x410305C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3096 0x4103060
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3097 0x4103064
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3098 0x4103068
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3099 0x410306C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3100 0x4103070
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3101 0x4103074
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3102 0x4103078
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3103 0x410307C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3104 0x4103080
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3105 0x4103084
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3106 0x4103088
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3107 0x410308C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3108 0x4103090
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3109 0x4103094
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3110 0x4103098
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3111 0x410309C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3112 0x41030A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3113 0x41030A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3114 0x41030A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3115 0x41030AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3116 0x41030B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3117 0x41030B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3118 0x41030B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3119 0x41030BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3120 0x41030C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3121 0x41030C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3122 0x41030C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3123 0x41030CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3124 0x41030D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3125 0x41030D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3126 0x41030D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3127 0x41030DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3128 0x41030E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3129 0x41030E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3130 0x41030E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3131 0x41030EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3132 0x41030F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3133 0x41030F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3134 0x41030F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3135 0x41030FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3136 0x4103100
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3137 0x4103104
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3138 0x4103108
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3139 0x410310C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3140 0x4103110
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3141 0x4103114
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3142 0x4103118
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3143 0x410311C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3144 0x4103120
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3145 0x4103124
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3146 0x4103128
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3147 0x410312C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3148 0x4103130
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3149 0x4103134
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3150 0x4103138
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3151 0x410313C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3152 0x4103140
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3153 0x4103144
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3154 0x4103148
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3155 0x410314C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3156 0x4103150
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3157 0x4103154
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3158 0x4103158
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3159 0x410315C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3160 0x4103160
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3161 0x4103164
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3162 0x4103168
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3163 0x410316C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3164 0x4103170
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3165 0x4103174
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3166 0x4103178
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3167 0x410317C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3168 0x4103180
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3169 0x4103184
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3170 0x4103188
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3171 0x410318C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3172 0x4103190
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3173 0x4103194
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3174 0x4103198
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3175 0x410319C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3176 0x41031A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3177 0x41031A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3178 0x41031A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3179 0x41031AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3180 0x41031B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3181 0x41031B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3182 0x41031B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3183 0x41031BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3184 0x41031C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3185 0x41031C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3186 0x41031C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3187 0x41031CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3188 0x41031D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3189 0x41031D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3190 0x41031D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3191 0x41031DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3192 0x41031E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3193 0x41031E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3194 0x41031E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3195 0x41031EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3196 0x41031F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3197 0x41031F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3198 0x41031F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3199 0x41031FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3200 0x4103200
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3201 0x4103204
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3202 0x4103208
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3203 0x410320C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3204 0x4103210
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3205 0x4103214
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3206 0x4103218
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3207 0x410321C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3208 0x4103220
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3209 0x4103224
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3210 0x4103228
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3211 0x410322C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3212 0x4103230
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3213 0x4103234
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3214 0x4103238
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3215 0x410323C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3216 0x4103240
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3217 0x4103244
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3218 0x4103248
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3219 0x410324C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3220 0x4103250
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3221 0x4103254
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3222 0x4103258
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3223 0x410325C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3224 0x4103260
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3225 0x4103264
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3226 0x4103268
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3227 0x410326C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3228 0x4103270
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3229 0x4103274
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3230 0x4103278
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3231 0x410327C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3232 0x4103280
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3233 0x4103284
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3234 0x4103288
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3235 0x410328C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3236 0x4103290
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3237 0x4103294
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3238 0x4103298
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3239 0x410329C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3240 0x41032A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3241 0x41032A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3242 0x41032A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3243 0x41032AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3244 0x41032B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3245 0x41032B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3246 0x41032B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3247 0x41032BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3248 0x41032C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3249 0x41032C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3250 0x41032C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3251 0x41032CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3252 0x41032D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3253 0x41032D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3254 0x41032D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3255 0x41032DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3256 0x41032E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3257 0x41032E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3258 0x41032E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3259 0x41032EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3260 0x41032F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3261 0x41032F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3262 0x41032F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3263 0x41032FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3264 0x4103300
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3265 0x4103304
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3266 0x4103308
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3267 0x410330C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3268 0x4103310
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3269 0x4103314
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3270 0x4103318
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3271 0x410331C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3272 0x4103320
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3273 0x4103324
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3274 0x4103328
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3275 0x410332C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3276 0x4103330
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3277 0x4103334
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3278 0x4103338
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3279 0x410333C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3280 0x4103340
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3281 0x4103344
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3282 0x4103348
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3283 0x410334C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3284 0x4103350
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3285 0x4103354
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3286 0x4103358
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3287 0x410335C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3288 0x4103360
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3289 0x4103364
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3290 0x4103368
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3291 0x410336C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3292 0x4103370
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3293 0x4103374
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3294 0x4103378
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3295 0x410337C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3296 0x4103380
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3297 0x4103384
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3298 0x4103388
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3299 0x410338C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3300 0x4103390
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3301 0x4103394
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3302 0x4103398
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3303 0x410339C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3304 0x41033A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3305 0x41033A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3306 0x41033A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3307 0x41033AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3308 0x41033B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3309 0x41033B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3310 0x41033B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3311 0x41033BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3312 0x41033C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3313 0x41033C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3314 0x41033C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3315 0x41033CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3316 0x41033D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3317 0x41033D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3318 0x41033D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3319 0x41033DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3320 0x41033E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3321 0x41033E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3322 0x41033E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3323 0x41033EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3324 0x41033F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3325 0x41033F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3326 0x41033F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3327 0x41033FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3328 0x4103400
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3329 0x4103404
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3330 0x4103408
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3331 0x410340C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3332 0x4103410
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3333 0x4103414
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3334 0x4103418
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3335 0x410341C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3336 0x4103420
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3337 0x4103424
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3338 0x4103428
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3339 0x410342C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3340 0x4103430
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3341 0x4103434
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3342 0x4103438
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3343 0x410343C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3344 0x4103440
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3345 0x4103444
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3346 0x4103448
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3347 0x410344C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3348 0x4103450
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3349 0x4103454
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3350 0x4103458
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3351 0x410345C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3352 0x4103460
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3353 0x4103464
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3354 0x4103468
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3355 0x410346C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3356 0x4103470
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3357 0x4103474
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3358 0x4103478
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3359 0x410347C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3360 0x4103480
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3361 0x4103484
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3362 0x4103488
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3363 0x410348C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3364 0x4103490
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3365 0x4103494
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3366 0x4103498
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3367 0x410349C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3368 0x41034A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3369 0x41034A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3370 0x41034A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3371 0x41034AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3372 0x41034B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3373 0x41034B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3374 0x41034B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3375 0x41034BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3376 0x41034C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3377 0x41034C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3378 0x41034C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3379 0x41034CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3380 0x41034D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3381 0x41034D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3382 0x41034D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3383 0x41034DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3384 0x41034E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3385 0x41034E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3386 0x41034E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3387 0x41034EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3388 0x41034F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3389 0x41034F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3390 0x41034F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3391 0x41034FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3392 0x4103500
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3393 0x4103504
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3394 0x4103508
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3395 0x410350C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3396 0x4103510
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3397 0x4103514
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3398 0x4103518
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3399 0x410351C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3400 0x4103520
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3401 0x4103524
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3402 0x4103528
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3403 0x410352C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3404 0x4103530
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3405 0x4103534
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3406 0x4103538
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3407 0x410353C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3408 0x4103540
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3409 0x4103544
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3410 0x4103548
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3411 0x410354C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3412 0x4103550
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3413 0x4103554
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3414 0x4103558
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3415 0x410355C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3416 0x4103560
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3417 0x4103564
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3418 0x4103568
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3419 0x410356C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3420 0x4103570
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3421 0x4103574
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3422 0x4103578
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3423 0x410357C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3424 0x4103580
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3425 0x4103584
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3426 0x4103588
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3427 0x410358C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3428 0x4103590
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3429 0x4103594
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3430 0x4103598
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3431 0x410359C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3432 0x41035A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3433 0x41035A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3434 0x41035A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3435 0x41035AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3436 0x41035B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3437 0x41035B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3438 0x41035B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3439 0x41035BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3440 0x41035C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3441 0x41035C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3442 0x41035C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3443 0x41035CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3444 0x41035D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3445 0x41035D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3446 0x41035D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3447 0x41035DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3448 0x41035E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3449 0x41035E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3450 0x41035E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3451 0x41035EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3452 0x41035F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3453 0x41035F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3454 0x41035F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3455 0x41035FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3456 0x4103600
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3457 0x4103604
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3458 0x4103608
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3459 0x410360C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3460 0x4103610
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3461 0x4103614
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3462 0x4103618
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3463 0x410361C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3464 0x4103620
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3465 0x4103624
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3466 0x4103628
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3467 0x410362C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3468 0x4103630
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3469 0x4103634
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3470 0x4103638
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3471 0x410363C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3472 0x4103640
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3473 0x4103644
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3474 0x4103648
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3475 0x410364C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3476 0x4103650
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3477 0x4103654
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3478 0x4103658
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3479 0x410365C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3480 0x4103660
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3481 0x4103664
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3482 0x4103668
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3483 0x410366C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3484 0x4103670
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3485 0x4103674
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3486 0x4103678
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3487 0x410367C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3488 0x4103680
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3489 0x4103684
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3490 0x4103688
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3491 0x410368C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3492 0x4103690
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3493 0x4103694
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3494 0x4103698
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3495 0x410369C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3496 0x41036A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3497 0x41036A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3498 0x41036A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3499 0x41036AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3500 0x41036B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3501 0x41036B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3502 0x41036B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3503 0x41036BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3504 0x41036C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3505 0x41036C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3506 0x41036C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3507 0x41036CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3508 0x41036D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3509 0x41036D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3510 0x41036D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3511 0x41036DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3512 0x41036E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3513 0x41036E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3514 0x41036E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3515 0x41036EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3516 0x41036F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3517 0x41036F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3518 0x41036F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3519 0x41036FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3520 0x4103700
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3521 0x4103704
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3522 0x4103708
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3523 0x410370C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3524 0x4103710
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3525 0x4103714
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3526 0x4103718
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3527 0x410371C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3528 0x4103720
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3529 0x4103724
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3530 0x4103728
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3531 0x410372C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3532 0x4103730
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3533 0x4103734
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3534 0x4103738
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3535 0x410373C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3536 0x4103740
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3537 0x4103744
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3538 0x4103748
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3539 0x410374C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3540 0x4103750
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3541 0x4103754
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3542 0x4103758
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3543 0x410375C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3544 0x4103760
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3545 0x4103764
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3546 0x4103768
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3547 0x410376C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3548 0x4103770
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3549 0x4103774
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3550 0x4103778
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3551 0x410377C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3552 0x4103780
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3553 0x4103784
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3554 0x4103788
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3555 0x410378C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3556 0x4103790
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3557 0x4103794
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3558 0x4103798
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3559 0x410379C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3560 0x41037A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3561 0x41037A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3562 0x41037A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3563 0x41037AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3564 0x41037B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3565 0x41037B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3566 0x41037B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3567 0x41037BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3568 0x41037C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3569 0x41037C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3570 0x41037C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3571 0x41037CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3572 0x41037D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3573 0x41037D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3574 0x41037D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3575 0x41037DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3576 0x41037E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3577 0x41037E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3578 0x41037E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3579 0x41037EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3580 0x41037F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3581 0x41037F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3582 0x41037F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3583 0x41037FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3584 0x4103800
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3585 0x4103804
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3586 0x4103808
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3587 0x410380C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3588 0x4103810
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3589 0x4103814
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3590 0x4103818
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3591 0x410381C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3592 0x4103820
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3593 0x4103824
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3594 0x4103828
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3595 0x410382C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3596 0x4103830
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3597 0x4103834
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3598 0x4103838
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3599 0x410383C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3600 0x4103840
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3601 0x4103844
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3602 0x4103848
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3603 0x410384C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3604 0x4103850
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3605 0x4103854
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3606 0x4103858
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3607 0x410385C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3608 0x4103860
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3609 0x4103864
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3610 0x4103868
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3611 0x410386C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3612 0x4103870
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3613 0x4103874
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3614 0x4103878
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3615 0x410387C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3616 0x4103880
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3617 0x4103884
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3618 0x4103888
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3619 0x410388C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3620 0x4103890
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3621 0x4103894
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3622 0x4103898
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3623 0x410389C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3624 0x41038A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3625 0x41038A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3626 0x41038A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3627 0x41038AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3628 0x41038B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3629 0x41038B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3630 0x41038B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3631 0x41038BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3632 0x41038C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3633 0x41038C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3634 0x41038C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3635 0x41038CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3636 0x41038D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3637 0x41038D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3638 0x41038D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3639 0x41038DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3640 0x41038E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3641 0x41038E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3642 0x41038E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3643 0x41038EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3644 0x41038F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3645 0x41038F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3646 0x41038F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3647 0x41038FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3648 0x4103900
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3649 0x4103904
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3650 0x4103908
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3651 0x410390C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3652 0x4103910
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3653 0x4103914
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3654 0x4103918
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3655 0x410391C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3656 0x4103920
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3657 0x4103924
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3658 0x4103928
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3659 0x410392C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3660 0x4103930
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3661 0x4103934
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3662 0x4103938
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3663 0x410393C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3664 0x4103940
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3665 0x4103944
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3666 0x4103948
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3667 0x410394C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3668 0x4103950
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3669 0x4103954
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3670 0x4103958
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3671 0x410395C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3672 0x4103960
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3673 0x4103964
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3674 0x4103968
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3675 0x410396C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3676 0x4103970
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3677 0x4103974
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3678 0x4103978
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3679 0x410397C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3680 0x4103980
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3681 0x4103984
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3682 0x4103988
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3683 0x410398C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3684 0x4103990
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3685 0x4103994
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3686 0x4103998
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3687 0x410399C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3688 0x41039A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3689 0x41039A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3690 0x41039A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3691 0x41039AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3692 0x41039B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3693 0x41039B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3694 0x41039B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3695 0x41039BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3696 0x41039C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3697 0x41039C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3698 0x41039C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3699 0x41039CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3700 0x41039D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3701 0x41039D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3702 0x41039D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3703 0x41039DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3704 0x41039E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3705 0x41039E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3706 0x41039E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3707 0x41039EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3708 0x41039F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3709 0x41039F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3710 0x41039F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3711 0x41039FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3712 0x4103A00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3713 0x4103A04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3714 0x4103A08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3715 0x4103A0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3716 0x4103A10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3717 0x4103A14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3718 0x4103A18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3719 0x4103A1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3720 0x4103A20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3721 0x4103A24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3722 0x4103A28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3723 0x4103A2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3724 0x4103A30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3725 0x4103A34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3726 0x4103A38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3727 0x4103A3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3728 0x4103A40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3729 0x4103A44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3730 0x4103A48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3731 0x4103A4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3732 0x4103A50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3733 0x4103A54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3734 0x4103A58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3735 0x4103A5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3736 0x4103A60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3737 0x4103A64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3738 0x4103A68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3739 0x4103A6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3740 0x4103A70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3741 0x4103A74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3742 0x4103A78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3743 0x4103A7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3744 0x4103A80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3745 0x4103A84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3746 0x4103A88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3747 0x4103A8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3748 0x4103A90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3749 0x4103A94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3750 0x4103A98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3751 0x4103A9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3752 0x4103AA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3753 0x4103AA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3754 0x4103AA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3755 0x4103AAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3756 0x4103AB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3757 0x4103AB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3758 0x4103AB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3759 0x4103ABC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3760 0x4103AC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3761 0x4103AC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3762 0x4103AC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3763 0x4103ACC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3764 0x4103AD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3765 0x4103AD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3766 0x4103AD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3767 0x4103ADC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3768 0x4103AE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3769 0x4103AE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3770 0x4103AE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3771 0x4103AEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3772 0x4103AF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3773 0x4103AF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3774 0x4103AF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3775 0x4103AFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3776 0x4103B00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3777 0x4103B04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3778 0x4103B08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3779 0x4103B0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3780 0x4103B10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3781 0x4103B14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3782 0x4103B18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3783 0x4103B1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3784 0x4103B20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3785 0x4103B24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3786 0x4103B28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3787 0x4103B2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3788 0x4103B30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3789 0x4103B34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3790 0x4103B38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3791 0x4103B3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3792 0x4103B40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3793 0x4103B44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3794 0x4103B48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3795 0x4103B4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3796 0x4103B50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3797 0x4103B54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3798 0x4103B58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3799 0x4103B5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3800 0x4103B60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3801 0x4103B64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3802 0x4103B68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3803 0x4103B6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3804 0x4103B70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3805 0x4103B74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3806 0x4103B78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3807 0x4103B7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3808 0x4103B80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3809 0x4103B84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3810 0x4103B88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3811 0x4103B8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3812 0x4103B90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3813 0x4103B94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3814 0x4103B98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3815 0x4103B9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3816 0x4103BA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3817 0x4103BA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3818 0x4103BA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3819 0x4103BAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3820 0x4103BB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3821 0x4103BB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3822 0x4103BB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3823 0x4103BBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3824 0x4103BC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3825 0x4103BC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3826 0x4103BC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3827 0x4103BCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3828 0x4103BD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3829 0x4103BD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3830 0x4103BD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3831 0x4103BDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3832 0x4103BE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3833 0x4103BE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3834 0x4103BE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3835 0x4103BEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3836 0x4103BF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3837 0x4103BF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3838 0x4103BF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3839 0x4103BFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3840 0x4103C00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3841 0x4103C04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3842 0x4103C08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3843 0x4103C0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3844 0x4103C10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3845 0x4103C14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3846 0x4103C18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3847 0x4103C1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3848 0x4103C20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3849 0x4103C24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3850 0x4103C28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3851 0x4103C2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3852 0x4103C30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3853 0x4103C34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3854 0x4103C38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3855 0x4103C3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3856 0x4103C40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3857 0x4103C44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3858 0x4103C48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3859 0x4103C4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3860 0x4103C50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3861 0x4103C54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3862 0x4103C58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3863 0x4103C5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3864 0x4103C60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3865 0x4103C64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3866 0x4103C68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3867 0x4103C6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3868 0x4103C70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3869 0x4103C74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3870 0x4103C78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3871 0x4103C7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3872 0x4103C80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3873 0x4103C84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3874 0x4103C88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3875 0x4103C8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3876 0x4103C90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3877 0x4103C94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3878 0x4103C98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3879 0x4103C9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3880 0x4103CA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3881 0x4103CA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3882 0x4103CA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3883 0x4103CAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3884 0x4103CB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3885 0x4103CB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3886 0x4103CB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3887 0x4103CBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3888 0x4103CC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3889 0x4103CC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3890 0x4103CC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3891 0x4103CCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3892 0x4103CD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3893 0x4103CD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3894 0x4103CD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3895 0x4103CDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3896 0x4103CE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3897 0x4103CE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3898 0x4103CE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3899 0x4103CEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3900 0x4103CF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3901 0x4103CF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3902 0x4103CF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3903 0x4103CFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3904 0x4103D00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3905 0x4103D04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3906 0x4103D08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3907 0x4103D0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3908 0x4103D10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3909 0x4103D14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3910 0x4103D18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3911 0x4103D1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3912 0x4103D20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3913 0x4103D24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3914 0x4103D28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3915 0x4103D2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3916 0x4103D30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3917 0x4103D34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3918 0x4103D38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3919 0x4103D3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3920 0x4103D40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3921 0x4103D44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3922 0x4103D48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3923 0x4103D4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3924 0x4103D50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3925 0x4103D54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3926 0x4103D58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3927 0x4103D5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3928 0x4103D60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3929 0x4103D64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3930 0x4103D68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3931 0x4103D6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3932 0x4103D70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3933 0x4103D74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3934 0x4103D78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3935 0x4103D7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3936 0x4103D80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3937 0x4103D84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3938 0x4103D88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3939 0x4103D8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3940 0x4103D90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3941 0x4103D94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3942 0x4103D98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3943 0x4103D9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3944 0x4103DA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3945 0x4103DA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3946 0x4103DA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3947 0x4103DAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3948 0x4103DB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3949 0x4103DB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3950 0x4103DB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3951 0x4103DBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3952 0x4103DC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3953 0x4103DC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3954 0x4103DC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3955 0x4103DCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3956 0x4103DD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3957 0x4103DD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3958 0x4103DD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3959 0x4103DDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3960 0x4103DE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3961 0x4103DE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3962 0x4103DE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3963 0x4103DEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3964 0x4103DF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3965 0x4103DF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3966 0x4103DF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3967 0x4103DFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3968 0x4103E00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3969 0x4103E04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3970 0x4103E08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3971 0x4103E0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3972 0x4103E10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3973 0x4103E14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3974 0x4103E18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3975 0x4103E1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3976 0x4103E20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3977 0x4103E24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3978 0x4103E28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3979 0x4103E2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3980 0x4103E30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3981 0x4103E34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3982 0x4103E38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3983 0x4103E3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3984 0x4103E40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3985 0x4103E44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3986 0x4103E48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3987 0x4103E4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3988 0x4103E50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3989 0x4103E54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3990 0x4103E58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3991 0x4103E5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3992 0x4103E60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3993 0x4103E64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3994 0x4103E68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3995 0x4103E6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3996 0x4103E70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3997 0x4103E74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3998 0x4103E78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3999 0x4103E7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4000 0x4103E80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4001 0x4103E84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4002 0x4103E88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4003 0x4103E8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4004 0x4103E90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4005 0x4103E94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4006 0x4103E98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4007 0x4103E9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4008 0x4103EA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4009 0x4103EA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4010 0x4103EA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4011 0x4103EAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4012 0x4103EB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4013 0x4103EB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4014 0x4103EB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4015 0x4103EBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4016 0x4103EC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4017 0x4103EC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4018 0x4103EC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4019 0x4103ECC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4020 0x4103ED0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4021 0x4103ED4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4022 0x4103ED8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4023 0x4103EDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4024 0x4103EE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4025 0x4103EE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4026 0x4103EE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4027 0x4103EEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4028 0x4103EF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4029 0x4103EF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4030 0x4103EF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4031 0x4103EFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4032 0x4103F00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4033 0x4103F04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4034 0x4103F08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4035 0x4103F0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4036 0x4103F10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4037 0x4103F14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4038 0x4103F18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4039 0x4103F1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4040 0x4103F20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4041 0x4103F24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4042 0x4103F28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4043 0x4103F2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4044 0x4103F30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4045 0x4103F34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4046 0x4103F38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4047 0x4103F3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4048 0x4103F40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4049 0x4103F44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4050 0x4103F48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4051 0x4103F4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4052 0x4103F50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4053 0x4103F54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4054 0x4103F58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4055 0x4103F5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4056 0x4103F60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4057 0x4103F64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4058 0x4103F68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4059 0x4103F6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4060 0x4103F70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4061 0x4103F74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4062 0x4103F78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4063 0x4103F7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4064 0x4103F80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4065 0x4103F84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4066 0x4103F88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4067 0x4103F8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4068 0x4103F90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4069 0x4103F94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4070 0x4103F98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4071 0x4103F9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4072 0x4103FA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4073 0x4103FA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4074 0x4103FA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4075 0x4103FAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4076 0x4103FB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4077 0x4103FB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4078 0x4103FB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4079 0x4103FBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4080 0x4103FC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4081 0x4103FC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4082 0x4103FC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4083 0x4103FCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4084 0x4103FD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4085 0x4103FD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4086 0x4103FD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4087 0x4103FDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4088 0x4103FE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4089 0x4103FE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4090 0x4103FE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4091 0x4103FEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4092 0x4103FF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4093 0x4103FF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4094 0x4103FF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4095 0x4103FFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4096 0x4104000
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4097 0x4104004
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4098 0x4104008
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4099 0x410400C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4100 0x4104010
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4101 0x4104014
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4102 0x4104018
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4103 0x410401C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4104 0x4104020
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4105 0x4104024
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4106 0x4104028
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4107 0x410402C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4108 0x4104030
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4109 0x4104034
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4110 0x4104038
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4111 0x410403C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4112 0x4104040
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4113 0x4104044
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4114 0x4104048
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4115 0x410404C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4116 0x4104050
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4117 0x4104054
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4118 0x4104058
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4119 0x410405C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4120 0x4104060
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4121 0x4104064
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4122 0x4104068
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4123 0x410406C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4124 0x4104070
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4125 0x4104074
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4126 0x4104078
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4127 0x410407C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4128 0x4104080
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4129 0x4104084
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4130 0x4104088
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4131 0x410408C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4132 0x4104090
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4133 0x4104094
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4134 0x4104098
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4135 0x410409C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4136 0x41040A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4137 0x41040A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4138 0x41040A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4139 0x41040AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4140 0x41040B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4141 0x41040B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4142 0x41040B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4143 0x41040BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4144 0x41040C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4145 0x41040C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4146 0x41040C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4147 0x41040CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4148 0x41040D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4149 0x41040D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4150 0x41040D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4151 0x41040DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4152 0x41040E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4153 0x41040E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4154 0x41040E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4155 0x41040EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4156 0x41040F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4157 0x41040F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4158 0x41040F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4159 0x41040FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4160 0x4104100
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4161 0x4104104
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4162 0x4104108
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4163 0x410410C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4164 0x4104110
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4165 0x4104114
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4166 0x4104118
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4167 0x410411C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4168 0x4104120
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4169 0x4104124
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4170 0x4104128
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4171 0x410412C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4172 0x4104130
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4173 0x4104134
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4174 0x4104138
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4175 0x410413C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4176 0x4104140
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4177 0x4104144
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4178 0x4104148
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4179 0x410414C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4180 0x4104150
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4181 0x4104154
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4182 0x4104158
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4183 0x410415C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4184 0x4104160
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4185 0x4104164
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4186 0x4104168
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4187 0x410416C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4188 0x4104170
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4189 0x4104174
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4190 0x4104178
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4191 0x410417C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4192 0x4104180
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4193 0x4104184
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4194 0x4104188
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4195 0x410418C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4196 0x4104190
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4197 0x4104194
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4198 0x4104198
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4199 0x410419C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4200 0x41041A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4201 0x41041A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4202 0x41041A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4203 0x41041AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4204 0x41041B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4205 0x41041B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4206 0x41041B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4207 0x41041BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4208 0x41041C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4209 0x41041C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4210 0x41041C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4211 0x41041CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4212 0x41041D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4213 0x41041D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4214 0x41041D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4215 0x41041DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4216 0x41041E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4217 0x41041E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4218 0x41041E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4219 0x41041EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4220 0x41041F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4221 0x41041F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4222 0x41041F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4223 0x41041FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4224 0x4104200
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4225 0x4104204
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4226 0x4104208
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4227 0x410420C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4228 0x4104210
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4229 0x4104214
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4230 0x4104218
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4231 0x410421C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4232 0x4104220
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4233 0x4104224
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4234 0x4104228
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4235 0x410422C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4236 0x4104230
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4237 0x4104234
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4238 0x4104238
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4239 0x410423C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4240 0x4104240
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4241 0x4104244
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4242 0x4104248
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4243 0x410424C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4244 0x4104250
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4245 0x4104254
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4246 0x4104258
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4247 0x410425C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4248 0x4104260
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4249 0x4104264
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4250 0x4104268
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4251 0x410426C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4252 0x4104270
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4253 0x4104274
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4254 0x4104278
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4255 0x410427C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4256 0x4104280
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4257 0x4104284
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4258 0x4104288
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4259 0x410428C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4260 0x4104290
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4261 0x4104294
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4262 0x4104298
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4263 0x410429C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4264 0x41042A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4265 0x41042A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4266 0x41042A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4267 0x41042AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4268 0x41042B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4269 0x41042B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4270 0x41042B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4271 0x41042BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4272 0x41042C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4273 0x41042C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4274 0x41042C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4275 0x41042CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4276 0x41042D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4277 0x41042D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4278 0x41042D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4279 0x41042DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4280 0x41042E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4281 0x41042E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4282 0x41042E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4283 0x41042EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4284 0x41042F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4285 0x41042F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4286 0x41042F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4287 0x41042FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4288 0x4104300
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4289 0x4104304
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4290 0x4104308
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4291 0x410430C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4292 0x4104310
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4293 0x4104314
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4294 0x4104318
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4295 0x410431C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4296 0x4104320
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4297 0x4104324
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4298 0x4104328
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4299 0x410432C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4300 0x4104330
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4301 0x4104334
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4302 0x4104338
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4303 0x410433C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4304 0x4104340
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4305 0x4104344
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4306 0x4104348
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4307 0x410434C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4308 0x4104350
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4309 0x4104354
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4310 0x4104358
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4311 0x410435C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4312 0x4104360
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4313 0x4104364
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4314 0x4104368
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4315 0x410436C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4316 0x4104370
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4317 0x4104374
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4318 0x4104378
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4319 0x410437C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4320 0x4104380
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4321 0x4104384
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4322 0x4104388
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4323 0x410438C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4324 0x4104390
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4325 0x4104394
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4326 0x4104398
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4327 0x410439C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4328 0x41043A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4329 0x41043A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4330 0x41043A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4331 0x41043AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4332 0x41043B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4333 0x41043B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4334 0x41043B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4335 0x41043BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4336 0x41043C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4337 0x41043C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4338 0x41043C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4339 0x41043CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4340 0x41043D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4341 0x41043D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4342 0x41043D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4343 0x41043DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4344 0x41043E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4345 0x41043E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4346 0x41043E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4347 0x41043EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4348 0x41043F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4349 0x41043F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4350 0x41043F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4351 0x41043FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4352 0x4104400
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4353 0x4104404
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4354 0x4104408
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4355 0x410440C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4356 0x4104410
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4357 0x4104414
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4358 0x4104418
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4359 0x410441C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4360 0x4104420
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4361 0x4104424
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4362 0x4104428
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4363 0x410442C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4364 0x4104430
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4365 0x4104434
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4366 0x4104438
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4367 0x410443C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4368 0x4104440
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4369 0x4104444
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4370 0x4104448
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4371 0x410444C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4372 0x4104450
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4373 0x4104454
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4374 0x4104458
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4375 0x410445C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4376 0x4104460
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4377 0x4104464
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4378 0x4104468
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4379 0x410446C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4380 0x4104470
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4381 0x4104474
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4382 0x4104478
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4383 0x410447C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4384 0x4104480
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4385 0x4104484
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4386 0x4104488
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4387 0x410448C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4388 0x4104490
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4389 0x4104494
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4390 0x4104498
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4391 0x410449C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4392 0x41044A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4393 0x41044A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4394 0x41044A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4395 0x41044AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4396 0x41044B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4397 0x41044B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4398 0x41044B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4399 0x41044BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4400 0x41044C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4401 0x41044C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4402 0x41044C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4403 0x41044CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4404 0x41044D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4405 0x41044D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4406 0x41044D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4407 0x41044DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4408 0x41044E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4409 0x41044E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4410 0x41044E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4411 0x41044EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4412 0x41044F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4413 0x41044F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4414 0x41044F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4415 0x41044FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4416 0x4104500
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4417 0x4104504
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4418 0x4104508
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4419 0x410450C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4420 0x4104510
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4421 0x4104514
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4422 0x4104518
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4423 0x410451C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4424 0x4104520
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4425 0x4104524
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4426 0x4104528
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4427 0x410452C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4428 0x4104530
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4429 0x4104534
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4430 0x4104538
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4431 0x410453C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4432 0x4104540
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4433 0x4104544
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4434 0x4104548
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4435 0x410454C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4436 0x4104550
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4437 0x4104554
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4438 0x4104558
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4439 0x410455C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4440 0x4104560
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4441 0x4104564
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4442 0x4104568
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4443 0x410456C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4444 0x4104570
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4445 0x4104574
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4446 0x4104578
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4447 0x410457C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4448 0x4104580
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4449 0x4104584
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4450 0x4104588
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4451 0x410458C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4452 0x4104590
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4453 0x4104594
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4454 0x4104598
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4455 0x410459C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4456 0x41045A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4457 0x41045A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4458 0x41045A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4459 0x41045AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4460 0x41045B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4461 0x41045B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4462 0x41045B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4463 0x41045BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4464 0x41045C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4465 0x41045C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4466 0x41045C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4467 0x41045CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4468 0x41045D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4469 0x41045D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4470 0x41045D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4471 0x41045DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4472 0x41045E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4473 0x41045E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4474 0x41045E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4475 0x41045EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4476 0x41045F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4477 0x41045F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4478 0x41045F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4479 0x41045FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4480 0x4104600
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4481 0x4104604
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4482 0x4104608
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4483 0x410460C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4484 0x4104610
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4485 0x4104614
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4486 0x4104618
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4487 0x410461C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4488 0x4104620
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4489 0x4104624
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4490 0x4104628
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4491 0x410462C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4492 0x4104630
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4493 0x4104634
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4494 0x4104638
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4495 0x410463C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4496 0x4104640
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4497 0x4104644
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4498 0x4104648
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4499 0x410464C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4500 0x4104650
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4501 0x4104654
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4502 0x4104658
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4503 0x410465C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4504 0x4104660
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4505 0x4104664
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4506 0x4104668
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4507 0x410466C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4508 0x4104670
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4509 0x4104674
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4510 0x4104678
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4511 0x410467C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4512 0x4104680
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4513 0x4104684
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4514 0x4104688
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4515 0x410468C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4516 0x4104690
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4517 0x4104694
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4518 0x4104698
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4519 0x410469C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4520 0x41046A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4521 0x41046A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4522 0x41046A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4523 0x41046AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4524 0x41046B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4525 0x41046B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4526 0x41046B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4527 0x41046BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4528 0x41046C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4529 0x41046C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4530 0x41046C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4531 0x41046CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4532 0x41046D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4533 0x41046D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4534 0x41046D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4535 0x41046DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4536 0x41046E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4537 0x41046E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4538 0x41046E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4539 0x41046EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4540 0x41046F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4541 0x41046F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4542 0x41046F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4543 0x41046FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4544 0x4104700
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4545 0x4104704
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4546 0x4104708
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4547 0x410470C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4548 0x4104710
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4549 0x4104714
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4550 0x4104718
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4551 0x410471C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4552 0x4104720
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4553 0x4104724
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4554 0x4104728
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4555 0x410472C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4556 0x4104730
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4557 0x4104734
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4558 0x4104738
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4559 0x410473C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4560 0x4104740
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4561 0x4104744
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4562 0x4104748
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4563 0x410474C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4564 0x4104750
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4565 0x4104754
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4566 0x4104758
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4567 0x410475C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4568 0x4104760
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4569 0x4104764
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4570 0x4104768
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4571 0x410476C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4572 0x4104770
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4573 0x4104774
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4574 0x4104778
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4575 0x410477C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4576 0x4104780
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4577 0x4104784
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4578 0x4104788
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4579 0x410478C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4580 0x4104790
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4581 0x4104794
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4582 0x4104798
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4583 0x410479C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4584 0x41047A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4585 0x41047A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4586 0x41047A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4587 0x41047AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4588 0x41047B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4589 0x41047B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4590 0x41047B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4591 0x41047BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4592 0x41047C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4593 0x41047C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4594 0x41047C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4595 0x41047CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4596 0x41047D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4597 0x41047D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4598 0x41047D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4599 0x41047DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4600 0x41047E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4601 0x41047E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4602 0x41047E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4603 0x41047EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4604 0x41047F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4605 0x41047F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4606 0x41047F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4607 0x41047FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4608 0x4104800
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4609 0x4104804
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4610 0x4104808
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4611 0x410480C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4612 0x4104810
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4613 0x4104814
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4614 0x4104818
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4615 0x410481C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4616 0x4104820
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4617 0x4104824
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4618 0x4104828
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4619 0x410482C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4620 0x4104830
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4621 0x4104834
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4622 0x4104838
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4623 0x410483C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4624 0x4104840
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4625 0x4104844
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4626 0x4104848
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4627 0x410484C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4628 0x4104850
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4629 0x4104854
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4630 0x4104858
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4631 0x410485C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4632 0x4104860
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4633 0x4104864
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4634 0x4104868
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4635 0x410486C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4636 0x4104870
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4637 0x4104874
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4638 0x4104878
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4639 0x410487C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4640 0x4104880
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4641 0x4104884
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4642 0x4104888
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4643 0x410488C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4644 0x4104890
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4645 0x4104894
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4646 0x4104898
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4647 0x410489C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4648 0x41048A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4649 0x41048A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4650 0x41048A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4651 0x41048AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4652 0x41048B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4653 0x41048B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4654 0x41048B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4655 0x41048BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4656 0x41048C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4657 0x41048C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4658 0x41048C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4659 0x41048CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4660 0x41048D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4661 0x41048D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4662 0x41048D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4663 0x41048DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4664 0x41048E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4665 0x41048E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4666 0x41048E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4667 0x41048EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4668 0x41048F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4669 0x41048F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4670 0x41048F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4671 0x41048FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4672 0x4104900
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4673 0x4104904
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4674 0x4104908
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4675 0x410490C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4676 0x4104910
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4677 0x4104914
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4678 0x4104918
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4679 0x410491C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4680 0x4104920
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4681 0x4104924
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4682 0x4104928
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4683 0x410492C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4684 0x4104930
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4685 0x4104934
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4686 0x4104938
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4687 0x410493C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4688 0x4104940
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4689 0x4104944
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4690 0x4104948
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4691 0x410494C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4692 0x4104950
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4693 0x4104954
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4694 0x4104958
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4695 0x410495C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4696 0x4104960
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4697 0x4104964
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4698 0x4104968
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4699 0x410496C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4700 0x4104970
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4701 0x4104974
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4702 0x4104978
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4703 0x410497C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4704 0x4104980
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4705 0x4104984
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4706 0x4104988
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4707 0x410498C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4708 0x4104990
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4709 0x4104994
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4710 0x4104998
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4711 0x410499C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4712 0x41049A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4713 0x41049A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4714 0x41049A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4715 0x41049AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4716 0x41049B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4717 0x41049B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4718 0x41049B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4719 0x41049BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4720 0x41049C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4721 0x41049C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4722 0x41049C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4723 0x41049CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4724 0x41049D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4725 0x41049D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4726 0x41049D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4727 0x41049DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4728 0x41049E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4729 0x41049E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4730 0x41049E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4731 0x41049EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4732 0x41049F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4733 0x41049F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4734 0x41049F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4735 0x41049FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4736 0x4104A00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4737 0x4104A04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4738 0x4104A08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4739 0x4104A0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4740 0x4104A10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4741 0x4104A14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4742 0x4104A18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4743 0x4104A1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4744 0x4104A20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4745 0x4104A24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4746 0x4104A28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4747 0x4104A2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4748 0x4104A30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4749 0x4104A34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4750 0x4104A38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4751 0x4104A3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4752 0x4104A40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4753 0x4104A44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4754 0x4104A48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4755 0x4104A4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4756 0x4104A50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4757 0x4104A54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4758 0x4104A58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4759 0x4104A5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4760 0x4104A60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4761 0x4104A64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4762 0x4104A68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4763 0x4104A6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4764 0x4104A70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4765 0x4104A74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4766 0x4104A78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4767 0x4104A7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4768 0x4104A80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4769 0x4104A84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4770 0x4104A88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4771 0x4104A8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4772 0x4104A90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4773 0x4104A94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4774 0x4104A98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4775 0x4104A9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4776 0x4104AA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4777 0x4104AA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4778 0x4104AA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4779 0x4104AAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4780 0x4104AB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4781 0x4104AB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4782 0x4104AB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4783 0x4104ABC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4784 0x4104AC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4785 0x4104AC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4786 0x4104AC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4787 0x4104ACC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4788 0x4104AD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4789 0x4104AD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4790 0x4104AD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4791 0x4104ADC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4792 0x4104AE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4793 0x4104AE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4794 0x4104AE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4795 0x4104AEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4796 0x4104AF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4797 0x4104AF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4798 0x4104AF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4799 0x4104AFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4800 0x4104B00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4801 0x4104B04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4802 0x4104B08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4803 0x4104B0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4804 0x4104B10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4805 0x4104B14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4806 0x4104B18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4807 0x4104B1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4808 0x4104B20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4809 0x4104B24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4810 0x4104B28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4811 0x4104B2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4812 0x4104B30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4813 0x4104B34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4814 0x4104B38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4815 0x4104B3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4816 0x4104B40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4817 0x4104B44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4818 0x4104B48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4819 0x4104B4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4820 0x4104B50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4821 0x4104B54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4822 0x4104B58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4823 0x4104B5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4824 0x4104B60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4825 0x4104B64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4826 0x4104B68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4827 0x4104B6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4828 0x4104B70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4829 0x4104B74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4830 0x4104B78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4831 0x4104B7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4832 0x4104B80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4833 0x4104B84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4834 0x4104B88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4835 0x4104B8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4836 0x4104B90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4837 0x4104B94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4838 0x4104B98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4839 0x4104B9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4840 0x4104BA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4841 0x4104BA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4842 0x4104BA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4843 0x4104BAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4844 0x4104BB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4845 0x4104BB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4846 0x4104BB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4847 0x4104BBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4848 0x4104BC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4849 0x4104BC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4850 0x4104BC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4851 0x4104BCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4852 0x4104BD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4853 0x4104BD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4854 0x4104BD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4855 0x4104BDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4856 0x4104BE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4857 0x4104BE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4858 0x4104BE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4859 0x4104BEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4860 0x4104BF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4861 0x4104BF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4862 0x4104BF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4863 0x4104BFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4864 0x4104C00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4865 0x4104C04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4866 0x4104C08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4867 0x4104C0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4868 0x4104C10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4869 0x4104C14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4870 0x4104C18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4871 0x4104C1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4872 0x4104C20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4873 0x4104C24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4874 0x4104C28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4875 0x4104C2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4876 0x4104C30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4877 0x4104C34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4878 0x4104C38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4879 0x4104C3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4880 0x4104C40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4881 0x4104C44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4882 0x4104C48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4883 0x4104C4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4884 0x4104C50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4885 0x4104C54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4886 0x4104C58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4887 0x4104C5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4888 0x4104C60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4889 0x4104C64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4890 0x4104C68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4891 0x4104C6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4892 0x4104C70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4893 0x4104C74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4894 0x4104C78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4895 0x4104C7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4896 0x4104C80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4897 0x4104C84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4898 0x4104C88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4899 0x4104C8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4900 0x4104C90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4901 0x4104C94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4902 0x4104C98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4903 0x4104C9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4904 0x4104CA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4905 0x4104CA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4906 0x4104CA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4907 0x4104CAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4908 0x4104CB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4909 0x4104CB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4910 0x4104CB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4911 0x4104CBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4912 0x4104CC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4913 0x4104CC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4914 0x4104CC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4915 0x4104CCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4916 0x4104CD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4917 0x4104CD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4918 0x4104CD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4919 0x4104CDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4920 0x4104CE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4921 0x4104CE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4922 0x4104CE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4923 0x4104CEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4924 0x4104CF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4925 0x4104CF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4926 0x4104CF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4927 0x4104CFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4928 0x4104D00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4929 0x4104D04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4930 0x4104D08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4931 0x4104D0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4932 0x4104D10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4933 0x4104D14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4934 0x4104D18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4935 0x4104D1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4936 0x4104D20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4937 0x4104D24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4938 0x4104D28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4939 0x4104D2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4940 0x4104D30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4941 0x4104D34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4942 0x4104D38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4943 0x4104D3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4944 0x4104D40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4945 0x4104D44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4946 0x4104D48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4947 0x4104D4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4948 0x4104D50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4949 0x4104D54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4950 0x4104D58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4951 0x4104D5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4952 0x4104D60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4953 0x4104D64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4954 0x4104D68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4955 0x4104D6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4956 0x4104D70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4957 0x4104D74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4958 0x4104D78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4959 0x4104D7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4960 0x4104D80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4961 0x4104D84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4962 0x4104D88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4963 0x4104D8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4964 0x4104D90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4965 0x4104D94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4966 0x4104D98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4967 0x4104D9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4968 0x4104DA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4969 0x4104DA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4970 0x4104DA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4971 0x4104DAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4972 0x4104DB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4973 0x4104DB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4974 0x4104DB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4975 0x4104DBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4976 0x4104DC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4977 0x4104DC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4978 0x4104DC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4979 0x4104DCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4980 0x4104DD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4981 0x4104DD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4982 0x4104DD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4983 0x4104DDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4984 0x4104DE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4985 0x4104DE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4986 0x4104DE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4987 0x4104DEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4988 0x4104DF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4989 0x4104DF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4990 0x4104DF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4991 0x4104DFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4992 0x4104E00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4993 0x4104E04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4994 0x4104E08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4995 0x4104E0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4996 0x4104E10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4997 0x4104E14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4998 0x4104E18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4999 0x4104E1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5000 0x4104E20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5001 0x4104E24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5002 0x4104E28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5003 0x4104E2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5004 0x4104E30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5005 0x4104E34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5006 0x4104E38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5007 0x4104E3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5008 0x4104E40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5009 0x4104E44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5010 0x4104E48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5011 0x4104E4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5012 0x4104E50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5013 0x4104E54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5014 0x4104E58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5015 0x4104E5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5016 0x4104E60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5017 0x4104E64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5018 0x4104E68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5019 0x4104E6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5020 0x4104E70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5021 0x4104E74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5022 0x4104E78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5023 0x4104E7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5024 0x4104E80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5025 0x4104E84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5026 0x4104E88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5027 0x4104E8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5028 0x4104E90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5029 0x4104E94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5030 0x4104E98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5031 0x4104E9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5032 0x4104EA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5033 0x4104EA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5034 0x4104EA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5035 0x4104EAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5036 0x4104EB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5037 0x4104EB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5038 0x4104EB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5039 0x4104EBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5040 0x4104EC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5041 0x4104EC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5042 0x4104EC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5043 0x4104ECC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5044 0x4104ED0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5045 0x4104ED4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5046 0x4104ED8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5047 0x4104EDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5048 0x4104EE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5049 0x4104EE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5050 0x4104EE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5051 0x4104EEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5052 0x4104EF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5053 0x4104EF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5054 0x4104EF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5055 0x4104EFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5056 0x4104F00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5057 0x4104F04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5058 0x4104F08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5059 0x4104F0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5060 0x4104F10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5061 0x4104F14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5062 0x4104F18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5063 0x4104F1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5064 0x4104F20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5065 0x4104F24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5066 0x4104F28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5067 0x4104F2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5068 0x4104F30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5069 0x4104F34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5070 0x4104F38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5071 0x4104F3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5072 0x4104F40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5073 0x4104F44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5074 0x4104F48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5075 0x4104F4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5076 0x4104F50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5077 0x4104F54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5078 0x4104F58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5079 0x4104F5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5080 0x4104F60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5081 0x4104F64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5082 0x4104F68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5083 0x4104F6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5084 0x4104F70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5085 0x4104F74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5086 0x4104F78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5087 0x4104F7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5088 0x4104F80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5089 0x4104F84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5090 0x4104F88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5091 0x4104F8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5092 0x4104F90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5093 0x4104F94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5094 0x4104F98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5095 0x4104F9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5096 0x4104FA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5097 0x4104FA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5098 0x4104FA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5099 0x4104FAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5100 0x4104FB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5101 0x4104FB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5102 0x4104FB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5103 0x4104FBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5104 0x4104FC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5105 0x4104FC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5106 0x4104FC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5107 0x4104FCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5108 0x4104FD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5109 0x4104FD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5110 0x4104FD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5111 0x4104FDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5112 0x4104FE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5113 0x4104FE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5114 0x4104FE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5115 0x4104FEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5116 0x4104FF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5117 0x4104FF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5118 0x4104FF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5119 0x4104FFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5120 0x4105000
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5121 0x4105004
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5122 0x4105008
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5123 0x410500C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5124 0x4105010
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5125 0x4105014
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5126 0x4105018
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5127 0x410501C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5128 0x4105020
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5129 0x4105024
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5130 0x4105028
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5131 0x410502C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5132 0x4105030
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5133 0x4105034
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5134 0x4105038
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5135 0x410503C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5136 0x4105040
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5137 0x4105044
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5138 0x4105048
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5139 0x410504C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5140 0x4105050
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5141 0x4105054
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5142 0x4105058
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5143 0x410505C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5144 0x4105060
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5145 0x4105064
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5146 0x4105068
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5147 0x410506C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5148 0x4105070
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5149 0x4105074
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5150 0x4105078
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5151 0x410507C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5152 0x4105080
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5153 0x4105084
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5154 0x4105088
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5155 0x410508C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5156 0x4105090
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5157 0x4105094
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5158 0x4105098
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5159 0x410509C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5160 0x41050A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5161 0x41050A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5162 0x41050A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5163 0x41050AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5164 0x41050B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5165 0x41050B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5166 0x41050B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5167 0x41050BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5168 0x41050C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5169 0x41050C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5170 0x41050C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5171 0x41050CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5172 0x41050D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5173 0x41050D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5174 0x41050D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5175 0x41050DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5176 0x41050E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5177 0x41050E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5178 0x41050E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5179 0x41050EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5180 0x41050F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5181 0x41050F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5182 0x41050F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5183 0x41050FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5184 0x4105100
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5185 0x4105104
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5186 0x4105108
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5187 0x410510C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5188 0x4105110
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5189 0x4105114
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5190 0x4105118
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5191 0x410511C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5192 0x4105120
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5193 0x4105124
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5194 0x4105128
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5195 0x410512C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5196 0x4105130
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5197 0x4105134
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5198 0x4105138
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5199 0x410513C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5200 0x4105140
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5201 0x4105144
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5202 0x4105148
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5203 0x410514C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5204 0x4105150
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5205 0x4105154
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5206 0x4105158
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5207 0x410515C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5208 0x4105160
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5209 0x4105164
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5210 0x4105168
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5211 0x410516C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5212 0x4105170
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5213 0x4105174
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5214 0x4105178
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5215 0x410517C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5216 0x4105180
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5217 0x4105184
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5218 0x4105188
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5219 0x410518C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5220 0x4105190
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5221 0x4105194
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5222 0x4105198
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5223 0x410519C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5224 0x41051A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5225 0x41051A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5226 0x41051A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5227 0x41051AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5228 0x41051B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5229 0x41051B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5230 0x41051B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5231 0x41051BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5232 0x41051C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5233 0x41051C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5234 0x41051C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5235 0x41051CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5236 0x41051D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5237 0x41051D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5238 0x41051D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5239 0x41051DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5240 0x41051E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5241 0x41051E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5242 0x41051E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5243 0x41051EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5244 0x41051F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5245 0x41051F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5246 0x41051F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5247 0x41051FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5248 0x4105200
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5249 0x4105204
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5250 0x4105208
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5251 0x410520C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5252 0x4105210
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5253 0x4105214
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5254 0x4105218
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5255 0x410521C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5256 0x4105220
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5257 0x4105224
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5258 0x4105228
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5259 0x410522C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5260 0x4105230
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5261 0x4105234
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5262 0x4105238
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5263 0x410523C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5264 0x4105240
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5265 0x4105244
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5266 0x4105248
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5267 0x410524C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5268 0x4105250
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5269 0x4105254
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5270 0x4105258
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5271 0x410525C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5272 0x4105260
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5273 0x4105264
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5274 0x4105268
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5275 0x410526C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5276 0x4105270
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5277 0x4105274
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5278 0x4105278
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5279 0x410527C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5280 0x4105280
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5281 0x4105284
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5282 0x4105288
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5283 0x410528C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5284 0x4105290
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5285 0x4105294
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5286 0x4105298
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5287 0x410529C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5288 0x41052A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5289 0x41052A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5290 0x41052A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5291 0x41052AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5292 0x41052B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5293 0x41052B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5294 0x41052B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5295 0x41052BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5296 0x41052C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5297 0x41052C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5298 0x41052C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5299 0x41052CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5300 0x41052D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5301 0x41052D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5302 0x41052D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5303 0x41052DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5304 0x41052E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5305 0x41052E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5306 0x41052E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5307 0x41052EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5308 0x41052F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5309 0x41052F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5310 0x41052F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5311 0x41052FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5312 0x4105300
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5313 0x4105304
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5314 0x4105308
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5315 0x410530C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5316 0x4105310
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5317 0x4105314
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5318 0x4105318
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5319 0x410531C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5320 0x4105320
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5321 0x4105324
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5322 0x4105328
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5323 0x410532C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5324 0x4105330
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5325 0x4105334
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5326 0x4105338
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5327 0x410533C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5328 0x4105340
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5329 0x4105344
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5330 0x4105348
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5331 0x410534C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5332 0x4105350
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5333 0x4105354
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5334 0x4105358
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5335 0x410535C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5336 0x4105360
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5337 0x4105364
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5338 0x4105368
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5339 0x410536C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5340 0x4105370
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5341 0x4105374
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5342 0x4105378
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5343 0x410537C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5344 0x4105380
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5345 0x4105384
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5346 0x4105388
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5347 0x410538C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5348 0x4105390
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5349 0x4105394
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5350 0x4105398
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5351 0x410539C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5352 0x41053A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5353 0x41053A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5354 0x41053A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5355 0x41053AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5356 0x41053B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5357 0x41053B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5358 0x41053B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5359 0x41053BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5360 0x41053C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5361 0x41053C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5362 0x41053C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5363 0x41053CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5364 0x41053D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5365 0x41053D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5366 0x41053D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5367 0x41053DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5368 0x41053E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5369 0x41053E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5370 0x41053E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5371 0x41053EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5372 0x41053F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5373 0x41053F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5374 0x41053F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5375 0x41053FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5376 0x4105400
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5377 0x4105404
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5378 0x4105408
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5379 0x410540C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5380 0x4105410
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5381 0x4105414
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5382 0x4105418
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5383 0x410541C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5384 0x4105420
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5385 0x4105424
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5386 0x4105428
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5387 0x410542C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5388 0x4105430
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5389 0x4105434
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5390 0x4105438
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5391 0x410543C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5392 0x4105440
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5393 0x4105444
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5394 0x4105448
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5395 0x410544C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5396 0x4105450
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5397 0x4105454
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5398 0x4105458
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5399 0x410545C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5400 0x4105460
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5401 0x4105464
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5402 0x4105468
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5403 0x410546C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5404 0x4105470
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5405 0x4105474
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5406 0x4105478
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5407 0x410547C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5408 0x4105480
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5409 0x4105484
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5410 0x4105488
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5411 0x410548C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5412 0x4105490
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5413 0x4105494
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5414 0x4105498
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5415 0x410549C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5416 0x41054A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5417 0x41054A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5418 0x41054A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5419 0x41054AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5420 0x41054B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5421 0x41054B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5422 0x41054B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5423 0x41054BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5424 0x41054C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5425 0x41054C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5426 0x41054C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5427 0x41054CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5428 0x41054D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5429 0x41054D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5430 0x41054D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5431 0x41054DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5432 0x41054E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5433 0x41054E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5434 0x41054E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5435 0x41054EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5436 0x41054F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5437 0x41054F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5438 0x41054F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5439 0x41054FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5440 0x4105500
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5441 0x4105504
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5442 0x4105508
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5443 0x410550C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5444 0x4105510
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5445 0x4105514
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5446 0x4105518
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5447 0x410551C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5448 0x4105520
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5449 0x4105524
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5450 0x4105528
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5451 0x410552C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5452 0x4105530
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5453 0x4105534
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5454 0x4105538
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5455 0x410553C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5456 0x4105540
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5457 0x4105544
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5458 0x4105548
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5459 0x410554C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5460 0x4105550
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5461 0x4105554
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5462 0x4105558
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5463 0x410555C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5464 0x4105560
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5465 0x4105564
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5466 0x4105568
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5467 0x410556C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5468 0x4105570
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5469 0x4105574
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5470 0x4105578
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5471 0x410557C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5472 0x4105580
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5473 0x4105584
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5474 0x4105588
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5475 0x410558C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5476 0x4105590
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5477 0x4105594
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5478 0x4105598
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5479 0x410559C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5480 0x41055A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5481 0x41055A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5482 0x41055A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5483 0x41055AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5484 0x41055B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5485 0x41055B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5486 0x41055B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5487 0x41055BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5488 0x41055C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5489 0x41055C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5490 0x41055C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5491 0x41055CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5492 0x41055D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5493 0x41055D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5494 0x41055D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5495 0x41055DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5496 0x41055E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5497 0x41055E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5498 0x41055E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5499 0x41055EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5500 0x41055F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5501 0x41055F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5502 0x41055F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5503 0x41055FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5504 0x4105600
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5505 0x4105604
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5506 0x4105608
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5507 0x410560C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5508 0x4105610
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5509 0x4105614
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5510 0x4105618
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5511 0x410561C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5512 0x4105620
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5513 0x4105624
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5514 0x4105628
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5515 0x410562C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5516 0x4105630
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5517 0x4105634
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5518 0x4105638
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5519 0x410563C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5520 0x4105640
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5521 0x4105644
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5522 0x4105648
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5523 0x410564C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5524 0x4105650
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5525 0x4105654
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5526 0x4105658
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5527 0x410565C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5528 0x4105660
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5529 0x4105664
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5530 0x4105668
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5531 0x410566C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5532 0x4105670
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5533 0x4105674
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5534 0x4105678
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5535 0x410567C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5536 0x4105680
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5537 0x4105684
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5538 0x4105688
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5539 0x410568C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5540 0x4105690
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5541 0x4105694
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5542 0x4105698
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5543 0x410569C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5544 0x41056A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5545 0x41056A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5546 0x41056A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5547 0x41056AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5548 0x41056B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5549 0x41056B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5550 0x41056B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5551 0x41056BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5552 0x41056C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5553 0x41056C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5554 0x41056C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5555 0x41056CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5556 0x41056D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5557 0x41056D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5558 0x41056D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5559 0x41056DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5560 0x41056E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5561 0x41056E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5562 0x41056E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5563 0x41056EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5564 0x41056F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5565 0x41056F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5566 0x41056F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5567 0x41056FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5568 0x4105700
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5569 0x4105704
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5570 0x4105708
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5571 0x410570C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5572 0x4105710
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5573 0x4105714
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5574 0x4105718
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5575 0x410571C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5576 0x4105720
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5577 0x4105724
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5578 0x4105728
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5579 0x410572C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5580 0x4105730
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5581 0x4105734
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5582 0x4105738
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5583 0x410573C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5584 0x4105740
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5585 0x4105744
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5586 0x4105748
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5587 0x410574C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5588 0x4105750
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5589 0x4105754
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5590 0x4105758
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5591 0x410575C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5592 0x4105760
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5593 0x4105764
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5594 0x4105768
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5595 0x410576C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5596 0x4105770
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5597 0x4105774
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5598 0x4105778
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5599 0x410577C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5600 0x4105780
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5601 0x4105784
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5602 0x4105788
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5603 0x410578C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5604 0x4105790
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5605 0x4105794
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5606 0x4105798
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5607 0x410579C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5608 0x41057A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5609 0x41057A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5610 0x41057A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5611 0x41057AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5612 0x41057B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5613 0x41057B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5614 0x41057B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5615 0x41057BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5616 0x41057C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5617 0x41057C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5618 0x41057C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5619 0x41057CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5620 0x41057D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5621 0x41057D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5622 0x41057D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5623 0x41057DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5624 0x41057E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5625 0x41057E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5626 0x41057E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5627 0x41057EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5628 0x41057F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5629 0x41057F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5630 0x41057F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5631 0x41057FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5632 0x4105800
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5633 0x4105804
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5634 0x4105808
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5635 0x410580C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5636 0x4105810
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5637 0x4105814
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5638 0x4105818
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5639 0x410581C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5640 0x4105820
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5641 0x4105824
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5642 0x4105828
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5643 0x410582C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5644 0x4105830
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5645 0x4105834
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5646 0x4105838
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5647 0x410583C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5648 0x4105840
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5649 0x4105844
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5650 0x4105848
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5651 0x410584C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5652 0x4105850
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5653 0x4105854
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5654 0x4105858
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5655 0x410585C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5656 0x4105860
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5657 0x4105864
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5658 0x4105868
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5659 0x410586C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5660 0x4105870
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5661 0x4105874
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5662 0x4105878
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5663 0x410587C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5664 0x4105880
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5665 0x4105884
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5666 0x4105888
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5667 0x410588C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5668 0x4105890
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5669 0x4105894
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5670 0x4105898
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5671 0x410589C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5672 0x41058A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5673 0x41058A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5674 0x41058A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5675 0x41058AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5676 0x41058B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5677 0x41058B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5678 0x41058B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5679 0x41058BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5680 0x41058C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5681 0x41058C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5682 0x41058C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5683 0x41058CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5684 0x41058D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5685 0x41058D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5686 0x41058D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5687 0x41058DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5688 0x41058E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5689 0x41058E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5690 0x41058E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5691 0x41058EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5692 0x41058F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5693 0x41058F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5694 0x41058F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5695 0x41058FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5696 0x4105900
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5697 0x4105904
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5698 0x4105908
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5699 0x410590C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5700 0x4105910
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5701 0x4105914
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5702 0x4105918
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5703 0x410591C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5704 0x4105920
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5705 0x4105924
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5706 0x4105928
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5707 0x410592C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5708 0x4105930
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5709 0x4105934
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5710 0x4105938
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5711 0x410593C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5712 0x4105940
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5713 0x4105944
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5714 0x4105948
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5715 0x410594C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5716 0x4105950
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5717 0x4105954
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5718 0x4105958
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5719 0x410595C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5720 0x4105960
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5721 0x4105964
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5722 0x4105968
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5723 0x410596C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5724 0x4105970
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5725 0x4105974
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5726 0x4105978
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5727 0x410597C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5728 0x4105980
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5729 0x4105984
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5730 0x4105988
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5731 0x410598C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5732 0x4105990
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5733 0x4105994
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5734 0x4105998
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5735 0x410599C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5736 0x41059A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5737 0x41059A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5738 0x41059A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5739 0x41059AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5740 0x41059B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5741 0x41059B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5742 0x41059B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5743 0x41059BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5744 0x41059C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5745 0x41059C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5746 0x41059C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5747 0x41059CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5748 0x41059D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5749 0x41059D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5750 0x41059D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5751 0x41059DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5752 0x41059E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5753 0x41059E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5754 0x41059E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5755 0x41059EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5756 0x41059F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5757 0x41059F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5758 0x41059F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5759 0x41059FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5760 0x4105A00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5761 0x4105A04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5762 0x4105A08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5763 0x4105A0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5764 0x4105A10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5765 0x4105A14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5766 0x4105A18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5767 0x4105A1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5768 0x4105A20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5769 0x4105A24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5770 0x4105A28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5771 0x4105A2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5772 0x4105A30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5773 0x4105A34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5774 0x4105A38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5775 0x4105A3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5776 0x4105A40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5777 0x4105A44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5778 0x4105A48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5779 0x4105A4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5780 0x4105A50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5781 0x4105A54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5782 0x4105A58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5783 0x4105A5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5784 0x4105A60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5785 0x4105A64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5786 0x4105A68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5787 0x4105A6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5788 0x4105A70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5789 0x4105A74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5790 0x4105A78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5791 0x4105A7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5792 0x4105A80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5793 0x4105A84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5794 0x4105A88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5795 0x4105A8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5796 0x4105A90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5797 0x4105A94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5798 0x4105A98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5799 0x4105A9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5800 0x4105AA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5801 0x4105AA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5802 0x4105AA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5803 0x4105AAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5804 0x4105AB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5805 0x4105AB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5806 0x4105AB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5807 0x4105ABC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5808 0x4105AC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5809 0x4105AC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5810 0x4105AC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5811 0x4105ACC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5812 0x4105AD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5813 0x4105AD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5814 0x4105AD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5815 0x4105ADC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5816 0x4105AE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5817 0x4105AE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5818 0x4105AE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5819 0x4105AEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5820 0x4105AF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5821 0x4105AF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5822 0x4105AF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5823 0x4105AFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5824 0x4105B00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5825 0x4105B04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5826 0x4105B08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5827 0x4105B0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5828 0x4105B10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5829 0x4105B14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5830 0x4105B18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5831 0x4105B1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5832 0x4105B20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5833 0x4105B24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5834 0x4105B28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5835 0x4105B2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5836 0x4105B30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5837 0x4105B34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5838 0x4105B38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5839 0x4105B3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5840 0x4105B40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5841 0x4105B44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5842 0x4105B48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5843 0x4105B4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5844 0x4105B50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5845 0x4105B54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5846 0x4105B58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5847 0x4105B5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5848 0x4105B60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5849 0x4105B64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5850 0x4105B68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5851 0x4105B6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5852 0x4105B70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5853 0x4105B74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5854 0x4105B78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5855 0x4105B7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5856 0x4105B80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5857 0x4105B84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5858 0x4105B88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5859 0x4105B8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5860 0x4105B90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5861 0x4105B94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5862 0x4105B98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5863 0x4105B9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5864 0x4105BA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5865 0x4105BA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5866 0x4105BA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5867 0x4105BAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5868 0x4105BB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5869 0x4105BB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5870 0x4105BB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5871 0x4105BBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5872 0x4105BC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5873 0x4105BC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5874 0x4105BC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5875 0x4105BCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5876 0x4105BD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5877 0x4105BD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5878 0x4105BD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5879 0x4105BDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5880 0x4105BE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5881 0x4105BE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5882 0x4105BE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5883 0x4105BEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5884 0x4105BF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5885 0x4105BF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5886 0x4105BF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5887 0x4105BFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5888 0x4105C00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5889 0x4105C04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5890 0x4105C08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5891 0x4105C0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5892 0x4105C10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5893 0x4105C14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5894 0x4105C18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5895 0x4105C1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5896 0x4105C20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5897 0x4105C24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5898 0x4105C28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5899 0x4105C2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5900 0x4105C30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5901 0x4105C34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5902 0x4105C38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5903 0x4105C3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5904 0x4105C40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5905 0x4105C44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5906 0x4105C48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5907 0x4105C4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5908 0x4105C50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5909 0x4105C54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5910 0x4105C58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5911 0x4105C5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5912 0x4105C60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5913 0x4105C64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5914 0x4105C68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5915 0x4105C6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5916 0x4105C70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5917 0x4105C74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5918 0x4105C78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5919 0x4105C7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5920 0x4105C80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5921 0x4105C84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5922 0x4105C88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5923 0x4105C8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5924 0x4105C90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5925 0x4105C94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5926 0x4105C98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5927 0x4105C9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5928 0x4105CA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5929 0x4105CA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5930 0x4105CA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5931 0x4105CAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5932 0x4105CB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5933 0x4105CB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5934 0x4105CB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5935 0x4105CBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5936 0x4105CC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5937 0x4105CC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5938 0x4105CC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5939 0x4105CCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5940 0x4105CD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5941 0x4105CD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5942 0x4105CD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5943 0x4105CDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5944 0x4105CE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5945 0x4105CE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5946 0x4105CE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5947 0x4105CEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5948 0x4105CF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5949 0x4105CF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5950 0x4105CF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5951 0x4105CFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5952 0x4105D00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5953 0x4105D04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5954 0x4105D08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5955 0x4105D0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5956 0x4105D10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5957 0x4105D14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5958 0x4105D18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5959 0x4105D1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5960 0x4105D20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5961 0x4105D24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5962 0x4105D28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5963 0x4105D2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5964 0x4105D30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5965 0x4105D34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5966 0x4105D38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5967 0x4105D3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5968 0x4105D40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5969 0x4105D44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5970 0x4105D48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5971 0x4105D4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5972 0x4105D50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5973 0x4105D54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5974 0x4105D58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5975 0x4105D5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5976 0x4105D60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5977 0x4105D64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5978 0x4105D68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5979 0x4105D6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5980 0x4105D70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5981 0x4105D74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5982 0x4105D78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5983 0x4105D7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5984 0x4105D80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5985 0x4105D84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5986 0x4105D88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5987 0x4105D8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5988 0x4105D90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5989 0x4105D94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5990 0x4105D98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5991 0x4105D9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5992 0x4105DA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5993 0x4105DA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5994 0x4105DA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5995 0x4105DAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5996 0x4105DB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5997 0x4105DB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5998 0x4105DB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5999 0x4105DBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6000 0x4105DC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6001 0x4105DC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6002 0x4105DC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6003 0x4105DCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6004 0x4105DD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6005 0x4105DD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6006 0x4105DD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6007 0x4105DDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6008 0x4105DE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6009 0x4105DE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6010 0x4105DE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6011 0x4105DEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6012 0x4105DF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6013 0x4105DF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6014 0x4105DF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6015 0x4105DFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6016 0x4105E00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6017 0x4105E04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6018 0x4105E08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6019 0x4105E0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6020 0x4105E10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6021 0x4105E14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6022 0x4105E18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6023 0x4105E1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6024 0x4105E20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6025 0x4105E24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6026 0x4105E28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6027 0x4105E2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6028 0x4105E30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6029 0x4105E34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6030 0x4105E38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6031 0x4105E3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6032 0x4105E40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6033 0x4105E44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6034 0x4105E48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6035 0x4105E4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6036 0x4105E50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6037 0x4105E54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6038 0x4105E58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6039 0x4105E5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6040 0x4105E60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6041 0x4105E64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6042 0x4105E68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6043 0x4105E6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6044 0x4105E70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6045 0x4105E74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6046 0x4105E78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6047 0x4105E7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6048 0x4105E80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6049 0x4105E84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6050 0x4105E88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6051 0x4105E8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6052 0x4105E90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6053 0x4105E94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6054 0x4105E98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6055 0x4105E9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6056 0x4105EA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6057 0x4105EA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6058 0x4105EA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6059 0x4105EAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6060 0x4105EB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6061 0x4105EB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6062 0x4105EB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6063 0x4105EBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6064 0x4105EC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6065 0x4105EC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6066 0x4105EC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6067 0x4105ECC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6068 0x4105ED0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6069 0x4105ED4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6070 0x4105ED8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6071 0x4105EDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6072 0x4105EE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6073 0x4105EE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6074 0x4105EE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6075 0x4105EEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6076 0x4105EF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6077 0x4105EF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6078 0x4105EF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6079 0x4105EFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6080 0x4105F00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6081 0x4105F04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6082 0x4105F08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6083 0x4105F0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6084 0x4105F10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6085 0x4105F14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6086 0x4105F18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6087 0x4105F1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6088 0x4105F20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6089 0x4105F24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6090 0x4105F28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6091 0x4105F2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6092 0x4105F30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6093 0x4105F34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6094 0x4105F38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6095 0x4105F3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6096 0x4105F40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6097 0x4105F44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6098 0x4105F48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6099 0x4105F4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6100 0x4105F50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6101 0x4105F54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6102 0x4105F58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6103 0x4105F5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6104 0x4105F60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6105 0x4105F64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6106 0x4105F68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6107 0x4105F6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6108 0x4105F70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6109 0x4105F74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6110 0x4105F78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6111 0x4105F7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6112 0x4105F80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6113 0x4105F84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6114 0x4105F88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6115 0x4105F8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6116 0x4105F90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6117 0x4105F94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6118 0x4105F98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6119 0x4105F9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6120 0x4105FA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6121 0x4105FA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6122 0x4105FA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6123 0x4105FAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6124 0x4105FB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6125 0x4105FB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6126 0x4105FB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6127 0x4105FBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6128 0x4105FC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6129 0x4105FC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6130 0x4105FC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6131 0x4105FCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6132 0x4105FD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6133 0x4105FD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6134 0x4105FD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6135 0x4105FDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6136 0x4105FE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6137 0x4105FE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6138 0x4105FE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6139 0x4105FEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6140 0x4105FF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6141 0x4105FF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6142 0x4105FF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6143 0x4105FFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6144 0x4106000
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6145 0x4106004
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6146 0x4106008
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6147 0x410600C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6148 0x4106010
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6149 0x4106014
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6150 0x4106018
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6151 0x410601C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6152 0x4106020
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6153 0x4106024
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6154 0x4106028
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6155 0x410602C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6156 0x4106030
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6157 0x4106034
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6158 0x4106038
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6159 0x410603C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6160 0x4106040
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6161 0x4106044
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6162 0x4106048
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6163 0x410604C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6164 0x4106050
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6165 0x4106054
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6166 0x4106058
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6167 0x410605C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6168 0x4106060
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6169 0x4106064
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6170 0x4106068
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6171 0x410606C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6172 0x4106070
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6173 0x4106074
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6174 0x4106078
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6175 0x410607C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6176 0x4106080
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6177 0x4106084
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6178 0x4106088
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6179 0x410608C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6180 0x4106090
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6181 0x4106094
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6182 0x4106098
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6183 0x410609C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6184 0x41060A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6185 0x41060A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6186 0x41060A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6187 0x41060AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6188 0x41060B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6189 0x41060B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6190 0x41060B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6191 0x41060BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6192 0x41060C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6193 0x41060C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6194 0x41060C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6195 0x41060CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6196 0x41060D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6197 0x41060D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6198 0x41060D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6199 0x41060DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6200 0x41060E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6201 0x41060E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6202 0x41060E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6203 0x41060EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6204 0x41060F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6205 0x41060F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6206 0x41060F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6207 0x41060FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6208 0x4106100
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6209 0x4106104
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6210 0x4106108
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6211 0x410610C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6212 0x4106110
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6213 0x4106114
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6214 0x4106118
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6215 0x410611C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6216 0x4106120
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6217 0x4106124
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6218 0x4106128
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6219 0x410612C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6220 0x4106130
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6221 0x4106134
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6222 0x4106138
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6223 0x410613C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6224 0x4106140
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6225 0x4106144
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6226 0x4106148
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6227 0x410614C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6228 0x4106150
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6229 0x4106154
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6230 0x4106158
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6231 0x410615C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6232 0x4106160
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6233 0x4106164
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6234 0x4106168
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6235 0x410616C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6236 0x4106170
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6237 0x4106174
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6238 0x4106178
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6239 0x410617C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6240 0x4106180
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6241 0x4106184
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6242 0x4106188
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6243 0x410618C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6244 0x4106190
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6245 0x4106194
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6246 0x4106198
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6247 0x410619C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6248 0x41061A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6249 0x41061A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6250 0x41061A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6251 0x41061AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6252 0x41061B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6253 0x41061B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6254 0x41061B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6255 0x41061BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6256 0x41061C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6257 0x41061C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6258 0x41061C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6259 0x41061CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6260 0x41061D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6261 0x41061D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6262 0x41061D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6263 0x41061DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6264 0x41061E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6265 0x41061E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6266 0x41061E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6267 0x41061EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6268 0x41061F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6269 0x41061F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6270 0x41061F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6271 0x41061FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6272 0x4106200
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6273 0x4106204
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6274 0x4106208
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6275 0x410620C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6276 0x4106210
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6277 0x4106214
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6278 0x4106218
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6279 0x410621C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6280 0x4106220
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6281 0x4106224
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6282 0x4106228
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6283 0x410622C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6284 0x4106230
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6285 0x4106234
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6286 0x4106238
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6287 0x410623C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6288 0x4106240
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6289 0x4106244
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6290 0x4106248
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6291 0x410624C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6292 0x4106250
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6293 0x4106254
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6294 0x4106258
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6295 0x410625C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6296 0x4106260
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6297 0x4106264
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6298 0x4106268
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6299 0x410626C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6300 0x4106270
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6301 0x4106274
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6302 0x4106278
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6303 0x410627C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6304 0x4106280
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6305 0x4106284
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6306 0x4106288
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6307 0x410628C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6308 0x4106290
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6309 0x4106294
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6310 0x4106298
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6311 0x410629C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6312 0x41062A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6313 0x41062A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6314 0x41062A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6315 0x41062AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6316 0x41062B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6317 0x41062B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6318 0x41062B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6319 0x41062BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6320 0x41062C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6321 0x41062C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6322 0x41062C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6323 0x41062CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6324 0x41062D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6325 0x41062D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6326 0x41062D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6327 0x41062DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6328 0x41062E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6329 0x41062E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6330 0x41062E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6331 0x41062EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6332 0x41062F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6333 0x41062F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6334 0x41062F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6335 0x41062FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6336 0x4106300
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6337 0x4106304
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6338 0x4106308
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6339 0x410630C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6340 0x4106310
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6341 0x4106314
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6342 0x4106318
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6343 0x410631C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6344 0x4106320
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6345 0x4106324
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6346 0x4106328
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6347 0x410632C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6348 0x4106330
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6349 0x4106334
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6350 0x4106338
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6351 0x410633C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6352 0x4106340
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6353 0x4106344
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6354 0x4106348
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6355 0x410634C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6356 0x4106350
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6357 0x4106354
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6358 0x4106358
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6359 0x410635C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6360 0x4106360
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6361 0x4106364
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6362 0x4106368
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6363 0x410636C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6364 0x4106370
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6365 0x4106374
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6366 0x4106378
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6367 0x410637C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6368 0x4106380
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6369 0x4106384
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6370 0x4106388
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6371 0x410638C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6372 0x4106390
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6373 0x4106394
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6374 0x4106398
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6375 0x410639C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6376 0x41063A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6377 0x41063A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6378 0x41063A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6379 0x41063AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6380 0x41063B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6381 0x41063B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6382 0x41063B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6383 0x41063BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6384 0x41063C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6385 0x41063C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6386 0x41063C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6387 0x41063CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6388 0x41063D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6389 0x41063D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6390 0x41063D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6391 0x41063DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6392 0x41063E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6393 0x41063E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6394 0x41063E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6395 0x41063EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6396 0x41063F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6397 0x41063F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6398 0x41063F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6399 0x41063FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6400 0x4106400
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6401 0x4106404
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6402 0x4106408
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6403 0x410640C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6404 0x4106410
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6405 0x4106414
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6406 0x4106418
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6407 0x410641C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6408 0x4106420
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6409 0x4106424
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6410 0x4106428
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6411 0x410642C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6412 0x4106430
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6413 0x4106434
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6414 0x4106438
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6415 0x410643C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6416 0x4106440
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6417 0x4106444
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6418 0x4106448
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6419 0x410644C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6420 0x4106450
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6421 0x4106454
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6422 0x4106458
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6423 0x410645C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6424 0x4106460
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6425 0x4106464
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6426 0x4106468
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6427 0x410646C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6428 0x4106470
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6429 0x4106474
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6430 0x4106478
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6431 0x410647C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6432 0x4106480
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6433 0x4106484
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6434 0x4106488
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6435 0x410648C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6436 0x4106490
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6437 0x4106494
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6438 0x4106498
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6439 0x410649C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6440 0x41064A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6441 0x41064A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6442 0x41064A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6443 0x41064AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6444 0x41064B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6445 0x41064B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6446 0x41064B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6447 0x41064BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6448 0x41064C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6449 0x41064C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6450 0x41064C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6451 0x41064CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6452 0x41064D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6453 0x41064D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6454 0x41064D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6455 0x41064DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6456 0x41064E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6457 0x41064E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6458 0x41064E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6459 0x41064EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6460 0x41064F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6461 0x41064F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6462 0x41064F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6463 0x41064FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6464 0x4106500
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6465 0x4106504
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6466 0x4106508
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6467 0x410650C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6468 0x4106510
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6469 0x4106514
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6470 0x4106518
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6471 0x410651C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6472 0x4106520
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6473 0x4106524
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6474 0x4106528
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6475 0x410652C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6476 0x4106530
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6477 0x4106534
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6478 0x4106538
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6479 0x410653C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6480 0x4106540
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6481 0x4106544
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6482 0x4106548
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6483 0x410654C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6484 0x4106550
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6485 0x4106554
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6486 0x4106558
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6487 0x410655C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6488 0x4106560
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6489 0x4106564
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6490 0x4106568
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6491 0x410656C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6492 0x4106570
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6493 0x4106574
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6494 0x4106578
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6495 0x410657C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6496 0x4106580
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6497 0x4106584
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6498 0x4106588
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6499 0x410658C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6500 0x4106590
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6501 0x4106594
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6502 0x4106598
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6503 0x410659C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6504 0x41065A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6505 0x41065A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6506 0x41065A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6507 0x41065AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6508 0x41065B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6509 0x41065B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6510 0x41065B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6511 0x41065BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6512 0x41065C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6513 0x41065C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6514 0x41065C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6515 0x41065CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6516 0x41065D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6517 0x41065D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6518 0x41065D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6519 0x41065DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6520 0x41065E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6521 0x41065E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6522 0x41065E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6523 0x41065EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6524 0x41065F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6525 0x41065F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6526 0x41065F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6527 0x41065FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6528 0x4106600
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6529 0x4106604
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6530 0x4106608
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6531 0x410660C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6532 0x4106610
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6533 0x4106614
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6534 0x4106618
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6535 0x410661C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6536 0x4106620
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6537 0x4106624
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6538 0x4106628
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6539 0x410662C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6540 0x4106630
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6541 0x4106634
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6542 0x4106638
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6543 0x410663C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6544 0x4106640
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6545 0x4106644
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6546 0x4106648
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6547 0x410664C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6548 0x4106650
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6549 0x4106654
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6550 0x4106658
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6551 0x410665C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6552 0x4106660
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6553 0x4106664
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6554 0x4106668
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6555 0x410666C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6556 0x4106670
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6557 0x4106674
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6558 0x4106678
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6559 0x410667C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6560 0x4106680
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6561 0x4106684
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6562 0x4106688
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6563 0x410668C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6564 0x4106690
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6565 0x4106694
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6566 0x4106698
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6567 0x410669C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6568 0x41066A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6569 0x41066A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6570 0x41066A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6571 0x41066AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6572 0x41066B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6573 0x41066B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6574 0x41066B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6575 0x41066BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6576 0x41066C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6577 0x41066C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6578 0x41066C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6579 0x41066CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6580 0x41066D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6581 0x41066D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6582 0x41066D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6583 0x41066DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6584 0x41066E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6585 0x41066E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6586 0x41066E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6587 0x41066EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6588 0x41066F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6589 0x41066F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6590 0x41066F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6591 0x41066FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6592 0x4106700
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6593 0x4106704
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6594 0x4106708
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6595 0x410670C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6596 0x4106710
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6597 0x4106714
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6598 0x4106718
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6599 0x410671C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6600 0x4106720
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6601 0x4106724
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6602 0x4106728
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6603 0x410672C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6604 0x4106730
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6605 0x4106734
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6606 0x4106738
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6607 0x410673C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6608 0x4106740
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6609 0x4106744
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6610 0x4106748
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6611 0x410674C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6612 0x4106750
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6613 0x4106754
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6614 0x4106758
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6615 0x410675C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6616 0x4106760
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6617 0x4106764
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6618 0x4106768
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6619 0x410676C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6620 0x4106770
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6621 0x4106774
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6622 0x4106778
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6623 0x410677C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6624 0x4106780
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6625 0x4106784
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6626 0x4106788
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6627 0x410678C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6628 0x4106790
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6629 0x4106794
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6630 0x4106798
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6631 0x410679C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6632 0x41067A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6633 0x41067A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6634 0x41067A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6635 0x41067AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6636 0x41067B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6637 0x41067B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6638 0x41067B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6639 0x41067BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6640 0x41067C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6641 0x41067C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6642 0x41067C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6643 0x41067CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6644 0x41067D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6645 0x41067D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6646 0x41067D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6647 0x41067DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6648 0x41067E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6649 0x41067E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6650 0x41067E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6651 0x41067EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6652 0x41067F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6653 0x41067F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6654 0x41067F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6655 0x41067FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6656 0x4106800
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6657 0x4106804
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6658 0x4106808
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6659 0x410680C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6660 0x4106810
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6661 0x4106814
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6662 0x4106818
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6663 0x410681C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6664 0x4106820
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6665 0x4106824
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6666 0x4106828
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6667 0x410682C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6668 0x4106830
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6669 0x4106834
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6670 0x4106838
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6671 0x410683C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6672 0x4106840
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6673 0x4106844
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6674 0x4106848
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6675 0x410684C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6676 0x4106850
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6677 0x4106854
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6678 0x4106858
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6679 0x410685C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6680 0x4106860
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6681 0x4106864
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6682 0x4106868
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6683 0x410686C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6684 0x4106870
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6685 0x4106874
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6686 0x4106878
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6687 0x410687C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6688 0x4106880
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6689 0x4106884
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6690 0x4106888
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6691 0x410688C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6692 0x4106890
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6693 0x4106894
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6694 0x4106898
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6695 0x410689C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6696 0x41068A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6697 0x41068A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6698 0x41068A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6699 0x41068AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6700 0x41068B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6701 0x41068B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6702 0x41068B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6703 0x41068BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6704 0x41068C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6705 0x41068C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6706 0x41068C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6707 0x41068CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6708 0x41068D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6709 0x41068D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6710 0x41068D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6711 0x41068DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6712 0x41068E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6713 0x41068E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6714 0x41068E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6715 0x41068EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6716 0x41068F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6717 0x41068F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6718 0x41068F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6719 0x41068FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6720 0x4106900
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6721 0x4106904
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6722 0x4106908
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6723 0x410690C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6724 0x4106910
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6725 0x4106914
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6726 0x4106918
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6727 0x410691C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6728 0x4106920
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6729 0x4106924
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6730 0x4106928
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6731 0x410692C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6732 0x4106930
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6733 0x4106934
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6734 0x4106938
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6735 0x410693C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6736 0x4106940
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6737 0x4106944
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6738 0x4106948
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6739 0x410694C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6740 0x4106950
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6741 0x4106954
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6742 0x4106958
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6743 0x410695C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6744 0x4106960
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6745 0x4106964
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6746 0x4106968
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6747 0x410696C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6748 0x4106970
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6749 0x4106974
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6750 0x4106978
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6751 0x410697C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6752 0x4106980
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6753 0x4106984
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6754 0x4106988
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6755 0x410698C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6756 0x4106990
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6757 0x4106994
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6758 0x4106998
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6759 0x410699C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6760 0x41069A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6761 0x41069A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6762 0x41069A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6763 0x41069AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6764 0x41069B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6765 0x41069B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6766 0x41069B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6767 0x41069BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6768 0x41069C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6769 0x41069C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6770 0x41069C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6771 0x41069CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6772 0x41069D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6773 0x41069D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6774 0x41069D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6775 0x41069DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6776 0x41069E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6777 0x41069E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6778 0x41069E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6779 0x41069EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6780 0x41069F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6781 0x41069F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6782 0x41069F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6783 0x41069FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6784 0x4106A00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6785 0x4106A04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6786 0x4106A08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6787 0x4106A0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6788 0x4106A10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6789 0x4106A14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6790 0x4106A18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6791 0x4106A1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6792 0x4106A20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6793 0x4106A24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6794 0x4106A28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6795 0x4106A2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6796 0x4106A30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6797 0x4106A34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6798 0x4106A38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6799 0x4106A3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6800 0x4106A40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6801 0x4106A44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6802 0x4106A48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6803 0x4106A4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6804 0x4106A50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6805 0x4106A54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6806 0x4106A58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6807 0x4106A5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6808 0x4106A60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6809 0x4106A64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6810 0x4106A68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6811 0x4106A6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6812 0x4106A70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6813 0x4106A74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6814 0x4106A78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6815 0x4106A7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6816 0x4106A80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6817 0x4106A84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6818 0x4106A88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6819 0x4106A8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6820 0x4106A90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6821 0x4106A94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6822 0x4106A98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6823 0x4106A9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6824 0x4106AA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6825 0x4106AA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6826 0x4106AA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6827 0x4106AAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6828 0x4106AB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6829 0x4106AB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6830 0x4106AB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6831 0x4106ABC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6832 0x4106AC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6833 0x4106AC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6834 0x4106AC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6835 0x4106ACC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6836 0x4106AD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6837 0x4106AD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6838 0x4106AD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6839 0x4106ADC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6840 0x4106AE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6841 0x4106AE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6842 0x4106AE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6843 0x4106AEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6844 0x4106AF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6845 0x4106AF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6846 0x4106AF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6847 0x4106AFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6848 0x4106B00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6849 0x4106B04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6850 0x4106B08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6851 0x4106B0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6852 0x4106B10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6853 0x4106B14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6854 0x4106B18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6855 0x4106B1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6856 0x4106B20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6857 0x4106B24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6858 0x4106B28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6859 0x4106B2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6860 0x4106B30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6861 0x4106B34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6862 0x4106B38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6863 0x4106B3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6864 0x4106B40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6865 0x4106B44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6866 0x4106B48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6867 0x4106B4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6868 0x4106B50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6869 0x4106B54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6870 0x4106B58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6871 0x4106B5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6872 0x4106B60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6873 0x4106B64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6874 0x4106B68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6875 0x4106B6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6876 0x4106B70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6877 0x4106B74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6878 0x4106B78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6879 0x4106B7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6880 0x4106B80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6881 0x4106B84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6882 0x4106B88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6883 0x4106B8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6884 0x4106B90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6885 0x4106B94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6886 0x4106B98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6887 0x4106B9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6888 0x4106BA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6889 0x4106BA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6890 0x4106BA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6891 0x4106BAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6892 0x4106BB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6893 0x4106BB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6894 0x4106BB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6895 0x4106BBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6896 0x4106BC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6897 0x4106BC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6898 0x4106BC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6899 0x4106BCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6900 0x4106BD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6901 0x4106BD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6902 0x4106BD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6903 0x4106BDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6904 0x4106BE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6905 0x4106BE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6906 0x4106BE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6907 0x4106BEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6908 0x4106BF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6909 0x4106BF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6910 0x4106BF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6911 0x4106BFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6912 0x4106C00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6913 0x4106C04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6914 0x4106C08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6915 0x4106C0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6916 0x4106C10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6917 0x4106C14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6918 0x4106C18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6919 0x4106C1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6920 0x4106C20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6921 0x4106C24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6922 0x4106C28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6923 0x4106C2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6924 0x4106C30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6925 0x4106C34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6926 0x4106C38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6927 0x4106C3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6928 0x4106C40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6929 0x4106C44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6930 0x4106C48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6931 0x4106C4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6932 0x4106C50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6933 0x4106C54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6934 0x4106C58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6935 0x4106C5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6936 0x4106C60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6937 0x4106C64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6938 0x4106C68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6939 0x4106C6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6940 0x4106C70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6941 0x4106C74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6942 0x4106C78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6943 0x4106C7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6944 0x4106C80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6945 0x4106C84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6946 0x4106C88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6947 0x4106C8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6948 0x4106C90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6949 0x4106C94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6950 0x4106C98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6951 0x4106C9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6952 0x4106CA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6953 0x4106CA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6954 0x4106CA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6955 0x4106CAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6956 0x4106CB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6957 0x4106CB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6958 0x4106CB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6959 0x4106CBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6960 0x4106CC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6961 0x4106CC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6962 0x4106CC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6963 0x4106CCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6964 0x4106CD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6965 0x4106CD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6966 0x4106CD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6967 0x4106CDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6968 0x4106CE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6969 0x4106CE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6970 0x4106CE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6971 0x4106CEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6972 0x4106CF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6973 0x4106CF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6974 0x4106CF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6975 0x4106CFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6976 0x4106D00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6977 0x4106D04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6978 0x4106D08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6979 0x4106D0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6980 0x4106D10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6981 0x4106D14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6982 0x4106D18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6983 0x4106D1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6984 0x4106D20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6985 0x4106D24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6986 0x4106D28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6987 0x4106D2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6988 0x4106D30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6989 0x4106D34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6990 0x4106D38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6991 0x4106D3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6992 0x4106D40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6993 0x4106D44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6994 0x4106D48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6995 0x4106D4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6996 0x4106D50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6997 0x4106D54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6998 0x4106D58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6999 0x4106D5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7000 0x4106D60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7001 0x4106D64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7002 0x4106D68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7003 0x4106D6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7004 0x4106D70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7005 0x4106D74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7006 0x4106D78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7007 0x4106D7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7008 0x4106D80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7009 0x4106D84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7010 0x4106D88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7011 0x4106D8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7012 0x4106D90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7013 0x4106D94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7014 0x4106D98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7015 0x4106D9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7016 0x4106DA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7017 0x4106DA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7018 0x4106DA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7019 0x4106DAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7020 0x4106DB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7021 0x4106DB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7022 0x4106DB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7023 0x4106DBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7024 0x4106DC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7025 0x4106DC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7026 0x4106DC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7027 0x4106DCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7028 0x4106DD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7029 0x4106DD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7030 0x4106DD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7031 0x4106DDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7032 0x4106DE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7033 0x4106DE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7034 0x4106DE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7035 0x4106DEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7036 0x4106DF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7037 0x4106DF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7038 0x4106DF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7039 0x4106DFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7040 0x4106E00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7041 0x4106E04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7042 0x4106E08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7043 0x4106E0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7044 0x4106E10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7045 0x4106E14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7046 0x4106E18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7047 0x4106E1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7048 0x4106E20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7049 0x4106E24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7050 0x4106E28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7051 0x4106E2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7052 0x4106E30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7053 0x4106E34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7054 0x4106E38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7055 0x4106E3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7056 0x4106E40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7057 0x4106E44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7058 0x4106E48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7059 0x4106E4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7060 0x4106E50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7061 0x4106E54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7062 0x4106E58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7063 0x4106E5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7064 0x4106E60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7065 0x4106E64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7066 0x4106E68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7067 0x4106E6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7068 0x4106E70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7069 0x4106E74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7070 0x4106E78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7071 0x4106E7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7072 0x4106E80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7073 0x4106E84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7074 0x4106E88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7075 0x4106E8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7076 0x4106E90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7077 0x4106E94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7078 0x4106E98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7079 0x4106E9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7080 0x4106EA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7081 0x4106EA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7082 0x4106EA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7083 0x4106EAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7084 0x4106EB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7085 0x4106EB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7086 0x4106EB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7087 0x4106EBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7088 0x4106EC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7089 0x4106EC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7090 0x4106EC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7091 0x4106ECC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7092 0x4106ED0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7093 0x4106ED4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7094 0x4106ED8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7095 0x4106EDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7096 0x4106EE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7097 0x4106EE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7098 0x4106EE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7099 0x4106EEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7100 0x4106EF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7101 0x4106EF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7102 0x4106EF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7103 0x4106EFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7104 0x4106F00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7105 0x4106F04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7106 0x4106F08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7107 0x4106F0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7108 0x4106F10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7109 0x4106F14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7110 0x4106F18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7111 0x4106F1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7112 0x4106F20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7113 0x4106F24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7114 0x4106F28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7115 0x4106F2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7116 0x4106F30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7117 0x4106F34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7118 0x4106F38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7119 0x4106F3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7120 0x4106F40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7121 0x4106F44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7122 0x4106F48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7123 0x4106F4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7124 0x4106F50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7125 0x4106F54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7126 0x4106F58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7127 0x4106F5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7128 0x4106F60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7129 0x4106F64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7130 0x4106F68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7131 0x4106F6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7132 0x4106F70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7133 0x4106F74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7134 0x4106F78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7135 0x4106F7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7136 0x4106F80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7137 0x4106F84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7138 0x4106F88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7139 0x4106F8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7140 0x4106F90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7141 0x4106F94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7142 0x4106F98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7143 0x4106F9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7144 0x4106FA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7145 0x4106FA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7146 0x4106FA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7147 0x4106FAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7148 0x4106FB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7149 0x4106FB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7150 0x4106FB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7151 0x4106FBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7152 0x4106FC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7153 0x4106FC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7154 0x4106FC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7155 0x4106FCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7156 0x4106FD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7157 0x4106FD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7158 0x4106FD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7159 0x4106FDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7160 0x4106FE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7161 0x4106FE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7162 0x4106FE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7163 0x4106FEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7164 0x4106FF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7165 0x4106FF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7166 0x4106FF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7167 0x4106FFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7168 0x4107000
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7169 0x4107004
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7170 0x4107008
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7171 0x410700C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7172 0x4107010
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7173 0x4107014
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7174 0x4107018
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7175 0x410701C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7176 0x4107020
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7177 0x4107024
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7178 0x4107028
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7179 0x410702C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7180 0x4107030
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7181 0x4107034
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7182 0x4107038
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7183 0x410703C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7184 0x4107040
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7185 0x4107044
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7186 0x4107048
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7187 0x410704C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7188 0x4107050
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7189 0x4107054
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7190 0x4107058
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7191 0x410705C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7192 0x4107060
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7193 0x4107064
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7194 0x4107068
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7195 0x410706C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7196 0x4107070
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7197 0x4107074
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7198 0x4107078
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7199 0x410707C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7200 0x4107080
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7201 0x4107084
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7202 0x4107088
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7203 0x410708C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7204 0x4107090
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7205 0x4107094
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7206 0x4107098
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7207 0x410709C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7208 0x41070A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7209 0x41070A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7210 0x41070A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7211 0x41070AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7212 0x41070B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7213 0x41070B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7214 0x41070B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7215 0x41070BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7216 0x41070C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7217 0x41070C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7218 0x41070C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7219 0x41070CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7220 0x41070D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7221 0x41070D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7222 0x41070D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7223 0x41070DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7224 0x41070E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7225 0x41070E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7226 0x41070E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7227 0x41070EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7228 0x41070F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7229 0x41070F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7230 0x41070F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7231 0x41070FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7232 0x4107100
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7233 0x4107104
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7234 0x4107108
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7235 0x410710C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7236 0x4107110
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7237 0x4107114
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7238 0x4107118
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7239 0x410711C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7240 0x4107120
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7241 0x4107124
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7242 0x4107128
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7243 0x410712C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7244 0x4107130
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7245 0x4107134
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7246 0x4107138
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7247 0x410713C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7248 0x4107140
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7249 0x4107144
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7250 0x4107148
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7251 0x410714C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7252 0x4107150
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7253 0x4107154
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7254 0x4107158
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7255 0x410715C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7256 0x4107160
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7257 0x4107164
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7258 0x4107168
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7259 0x410716C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7260 0x4107170
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7261 0x4107174
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7262 0x4107178
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7263 0x410717C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7264 0x4107180
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7265 0x4107184
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7266 0x4107188
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7267 0x410718C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7268 0x4107190
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7269 0x4107194
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7270 0x4107198
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7271 0x410719C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7272 0x41071A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7273 0x41071A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7274 0x41071A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7275 0x41071AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7276 0x41071B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7277 0x41071B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7278 0x41071B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7279 0x41071BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7280 0x41071C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7281 0x41071C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7282 0x41071C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7283 0x41071CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7284 0x41071D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7285 0x41071D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7286 0x41071D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7287 0x41071DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7288 0x41071E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7289 0x41071E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7290 0x41071E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7291 0x41071EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7292 0x41071F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7293 0x41071F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7294 0x41071F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7295 0x41071FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7296 0x4107200
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7297 0x4107204
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7298 0x4107208
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7299 0x410720C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7300 0x4107210
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7301 0x4107214
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7302 0x4107218
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7303 0x410721C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7304 0x4107220
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7305 0x4107224
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7306 0x4107228
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7307 0x410722C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7308 0x4107230
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7309 0x4107234
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7310 0x4107238
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7311 0x410723C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7312 0x4107240
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7313 0x4107244
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7314 0x4107248
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7315 0x410724C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7316 0x4107250
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7317 0x4107254
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7318 0x4107258
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7319 0x410725C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7320 0x4107260
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7321 0x4107264
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7322 0x4107268
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7323 0x410726C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7324 0x4107270
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7325 0x4107274
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7326 0x4107278
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7327 0x410727C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7328 0x4107280
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7329 0x4107284
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7330 0x4107288
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7331 0x410728C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7332 0x4107290
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7333 0x4107294
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7334 0x4107298
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7335 0x410729C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7336 0x41072A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7337 0x41072A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7338 0x41072A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7339 0x41072AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7340 0x41072B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7341 0x41072B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7342 0x41072B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7343 0x41072BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7344 0x41072C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7345 0x41072C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7346 0x41072C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7347 0x41072CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7348 0x41072D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7349 0x41072D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7350 0x41072D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7351 0x41072DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7352 0x41072E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7353 0x41072E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7354 0x41072E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7355 0x41072EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7356 0x41072F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7357 0x41072F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7358 0x41072F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7359 0x41072FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7360 0x4107300
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7361 0x4107304
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7362 0x4107308
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7363 0x410730C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7364 0x4107310
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7365 0x4107314
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7366 0x4107318
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7367 0x410731C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7368 0x4107320
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7369 0x4107324
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7370 0x4107328
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7371 0x410732C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7372 0x4107330
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7373 0x4107334
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7374 0x4107338
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7375 0x410733C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7376 0x4107340
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7377 0x4107344
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7378 0x4107348
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7379 0x410734C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7380 0x4107350
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7381 0x4107354
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7382 0x4107358
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7383 0x410735C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7384 0x4107360
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7385 0x4107364
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7386 0x4107368
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7387 0x410736C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7388 0x4107370
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7389 0x4107374
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7390 0x4107378
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7391 0x410737C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7392 0x4107380
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7393 0x4107384
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7394 0x4107388
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7395 0x410738C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7396 0x4107390
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7397 0x4107394
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7398 0x4107398
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7399 0x410739C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7400 0x41073A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7401 0x41073A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7402 0x41073A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7403 0x41073AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7404 0x41073B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7405 0x41073B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7406 0x41073B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7407 0x41073BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7408 0x41073C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7409 0x41073C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7410 0x41073C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7411 0x41073CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7412 0x41073D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7413 0x41073D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7414 0x41073D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7415 0x41073DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7416 0x41073E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7417 0x41073E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7418 0x41073E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7419 0x41073EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7420 0x41073F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7421 0x41073F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7422 0x41073F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7423 0x41073FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7424 0x4107400
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7425 0x4107404
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7426 0x4107408
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7427 0x410740C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7428 0x4107410
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7429 0x4107414
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7430 0x4107418
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7431 0x410741C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7432 0x4107420
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7433 0x4107424
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7434 0x4107428
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7435 0x410742C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7436 0x4107430
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7437 0x4107434
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7438 0x4107438
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7439 0x410743C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7440 0x4107440
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7441 0x4107444
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7442 0x4107448
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7443 0x410744C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7444 0x4107450
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7445 0x4107454
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7446 0x4107458
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7447 0x410745C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7448 0x4107460
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7449 0x4107464
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7450 0x4107468
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7451 0x410746C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7452 0x4107470
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7453 0x4107474
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7454 0x4107478
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7455 0x410747C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7456 0x4107480
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7457 0x4107484
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7458 0x4107488
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7459 0x410748C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7460 0x4107490
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7461 0x4107494
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7462 0x4107498
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7463 0x410749C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7464 0x41074A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7465 0x41074A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7466 0x41074A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7467 0x41074AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7468 0x41074B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7469 0x41074B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7470 0x41074B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7471 0x41074BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7472 0x41074C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7473 0x41074C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7474 0x41074C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7475 0x41074CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7476 0x41074D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7477 0x41074D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7478 0x41074D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7479 0x41074DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7480 0x41074E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7481 0x41074E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7482 0x41074E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7483 0x41074EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7484 0x41074F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7485 0x41074F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7486 0x41074F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7487 0x41074FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7488 0x4107500
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7489 0x4107504
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7490 0x4107508
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7491 0x410750C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7492 0x4107510
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7493 0x4107514
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7494 0x4107518
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7495 0x410751C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7496 0x4107520
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7497 0x4107524
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7498 0x4107528
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7499 0x410752C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7500 0x4107530
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7501 0x4107534
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7502 0x4107538
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7503 0x410753C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7504 0x4107540
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7505 0x4107544
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7506 0x4107548
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7507 0x410754C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7508 0x4107550
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7509 0x4107554
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7510 0x4107558
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7511 0x410755C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7512 0x4107560
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7513 0x4107564
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7514 0x4107568
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7515 0x410756C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7516 0x4107570
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7517 0x4107574
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7518 0x4107578
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7519 0x410757C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7520 0x4107580
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7521 0x4107584
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7522 0x4107588
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7523 0x410758C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7524 0x4107590
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7525 0x4107594
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7526 0x4107598
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7527 0x410759C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7528 0x41075A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7529 0x41075A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7530 0x41075A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7531 0x41075AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7532 0x41075B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7533 0x41075B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7534 0x41075B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7535 0x41075BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7536 0x41075C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7537 0x41075C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7538 0x41075C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7539 0x41075CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7540 0x41075D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7541 0x41075D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7542 0x41075D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7543 0x41075DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7544 0x41075E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7545 0x41075E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7546 0x41075E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7547 0x41075EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7548 0x41075F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7549 0x41075F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7550 0x41075F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7551 0x41075FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7552 0x4107600
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7553 0x4107604
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7554 0x4107608
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7555 0x410760C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7556 0x4107610
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7557 0x4107614
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7558 0x4107618
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7559 0x410761C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7560 0x4107620
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7561 0x4107624
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7562 0x4107628
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7563 0x410762C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7564 0x4107630
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7565 0x4107634
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7566 0x4107638
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7567 0x410763C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7568 0x4107640
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7569 0x4107644
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7570 0x4107648
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7571 0x410764C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7572 0x4107650
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7573 0x4107654
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7574 0x4107658
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7575 0x410765C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7576 0x4107660
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7577 0x4107664
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7578 0x4107668
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7579 0x410766C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7580 0x4107670
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7581 0x4107674
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7582 0x4107678
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7583 0x410767C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7584 0x4107680
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7585 0x4107684
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7586 0x4107688
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7587 0x410768C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7588 0x4107690
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7589 0x4107694
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7590 0x4107698
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7591 0x410769C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7592 0x41076A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7593 0x41076A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7594 0x41076A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7595 0x41076AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7596 0x41076B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7597 0x41076B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7598 0x41076B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7599 0x41076BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7600 0x41076C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7601 0x41076C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7602 0x41076C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7603 0x41076CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7604 0x41076D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7605 0x41076D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7606 0x41076D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7607 0x41076DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7608 0x41076E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7609 0x41076E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7610 0x41076E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7611 0x41076EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7612 0x41076F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7613 0x41076F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7614 0x41076F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7615 0x41076FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7616 0x4107700
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7617 0x4107704
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7618 0x4107708
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7619 0x410770C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7620 0x4107710
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7621 0x4107714
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7622 0x4107718
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7623 0x410771C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7624 0x4107720
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7625 0x4107724
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7626 0x4107728
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7627 0x410772C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7628 0x4107730
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7629 0x4107734
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7630 0x4107738
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7631 0x410773C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7632 0x4107740
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7633 0x4107744
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7634 0x4107748
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7635 0x410774C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7636 0x4107750
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7637 0x4107754
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7638 0x4107758
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7639 0x410775C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7640 0x4107760
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7641 0x4107764
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7642 0x4107768
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7643 0x410776C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7644 0x4107770
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7645 0x4107774
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7646 0x4107778
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7647 0x410777C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7648 0x4107780
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7649 0x4107784
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7650 0x4107788
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7651 0x410778C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7652 0x4107790
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7653 0x4107794
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7654 0x4107798
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7655 0x410779C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7656 0x41077A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7657 0x41077A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7658 0x41077A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7659 0x41077AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7660 0x41077B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7661 0x41077B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7662 0x41077B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7663 0x41077BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7664 0x41077C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7665 0x41077C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7666 0x41077C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7667 0x41077CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7668 0x41077D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7669 0x41077D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7670 0x41077D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7671 0x41077DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7672 0x41077E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7673 0x41077E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7674 0x41077E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7675 0x41077EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7676 0x41077F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7677 0x41077F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7678 0x41077F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7679 0x41077FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7680 0x4107800
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7681 0x4107804
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7682 0x4107808
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7683 0x410780C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7684 0x4107810
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7685 0x4107814
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7686 0x4107818
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7687 0x410781C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7688 0x4107820
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7689 0x4107824
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7690 0x4107828
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7691 0x410782C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7692 0x4107830
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7693 0x4107834
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7694 0x4107838
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7695 0x410783C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7696 0x4107840
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7697 0x4107844
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7698 0x4107848
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7699 0x410784C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7700 0x4107850
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7701 0x4107854
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7702 0x4107858
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7703 0x410785C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7704 0x4107860
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7705 0x4107864
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7706 0x4107868
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7707 0x410786C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7708 0x4107870
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7709 0x4107874
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7710 0x4107878
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7711 0x410787C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7712 0x4107880
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7713 0x4107884
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7714 0x4107888
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7715 0x410788C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7716 0x4107890
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7717 0x4107894
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7718 0x4107898
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7719 0x410789C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7720 0x41078A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7721 0x41078A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7722 0x41078A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7723 0x41078AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7724 0x41078B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7725 0x41078B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7726 0x41078B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7727 0x41078BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7728 0x41078C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7729 0x41078C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7730 0x41078C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7731 0x41078CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7732 0x41078D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7733 0x41078D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7734 0x41078D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7735 0x41078DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7736 0x41078E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7737 0x41078E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7738 0x41078E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7739 0x41078EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7740 0x41078F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7741 0x41078F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7742 0x41078F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7743 0x41078FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7744 0x4107900
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7745 0x4107904
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7746 0x4107908
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7747 0x410790C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7748 0x4107910
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7749 0x4107914
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7750 0x4107918
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7751 0x410791C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7752 0x4107920
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7753 0x4107924
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7754 0x4107928
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7755 0x410792C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7756 0x4107930
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7757 0x4107934
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7758 0x4107938
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7759 0x410793C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7760 0x4107940
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7761 0x4107944
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7762 0x4107948
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7763 0x410794C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7764 0x4107950
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7765 0x4107954
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7766 0x4107958
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7767 0x410795C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7768 0x4107960
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7769 0x4107964
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7770 0x4107968
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7771 0x410796C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7772 0x4107970
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7773 0x4107974
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7774 0x4107978
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7775 0x410797C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7776 0x4107980
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7777 0x4107984
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7778 0x4107988
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7779 0x410798C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7780 0x4107990
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7781 0x4107994
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7782 0x4107998
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7783 0x410799C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7784 0x41079A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7785 0x41079A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7786 0x41079A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7787 0x41079AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7788 0x41079B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7789 0x41079B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7790 0x41079B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7791 0x41079BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7792 0x41079C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7793 0x41079C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7794 0x41079C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7795 0x41079CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7796 0x41079D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7797 0x41079D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7798 0x41079D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7799 0x41079DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7800 0x41079E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7801 0x41079E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7802 0x41079E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7803 0x41079EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7804 0x41079F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7805 0x41079F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7806 0x41079F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7807 0x41079FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7808 0x4107A00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7809 0x4107A04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7810 0x4107A08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7811 0x4107A0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7812 0x4107A10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7813 0x4107A14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7814 0x4107A18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7815 0x4107A1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7816 0x4107A20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7817 0x4107A24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7818 0x4107A28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7819 0x4107A2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7820 0x4107A30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7821 0x4107A34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7822 0x4107A38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7823 0x4107A3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7824 0x4107A40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7825 0x4107A44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7826 0x4107A48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7827 0x4107A4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7828 0x4107A50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7829 0x4107A54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7830 0x4107A58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7831 0x4107A5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7832 0x4107A60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7833 0x4107A64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7834 0x4107A68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7835 0x4107A6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7836 0x4107A70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7837 0x4107A74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7838 0x4107A78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7839 0x4107A7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7840 0x4107A80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7841 0x4107A84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7842 0x4107A88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7843 0x4107A8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7844 0x4107A90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7845 0x4107A94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7846 0x4107A98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7847 0x4107A9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7848 0x4107AA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7849 0x4107AA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7850 0x4107AA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7851 0x4107AAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7852 0x4107AB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7853 0x4107AB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7854 0x4107AB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7855 0x4107ABC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7856 0x4107AC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7857 0x4107AC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7858 0x4107AC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7859 0x4107ACC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7860 0x4107AD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7861 0x4107AD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7862 0x4107AD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7863 0x4107ADC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7864 0x4107AE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7865 0x4107AE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7866 0x4107AE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7867 0x4107AEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7868 0x4107AF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7869 0x4107AF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7870 0x4107AF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7871 0x4107AFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7872 0x4107B00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7873 0x4107B04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7874 0x4107B08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7875 0x4107B0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7876 0x4107B10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7877 0x4107B14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7878 0x4107B18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7879 0x4107B1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7880 0x4107B20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7881 0x4107B24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7882 0x4107B28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7883 0x4107B2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7884 0x4107B30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7885 0x4107B34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7886 0x4107B38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7887 0x4107B3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7888 0x4107B40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7889 0x4107B44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7890 0x4107B48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7891 0x4107B4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7892 0x4107B50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7893 0x4107B54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7894 0x4107B58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7895 0x4107B5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7896 0x4107B60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7897 0x4107B64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7898 0x4107B68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7899 0x4107B6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7900 0x4107B70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7901 0x4107B74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7902 0x4107B78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7903 0x4107B7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7904 0x4107B80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7905 0x4107B84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7906 0x4107B88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7907 0x4107B8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7908 0x4107B90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7909 0x4107B94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7910 0x4107B98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7911 0x4107B9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7912 0x4107BA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7913 0x4107BA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7914 0x4107BA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7915 0x4107BAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7916 0x4107BB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7917 0x4107BB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7918 0x4107BB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7919 0x4107BBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7920 0x4107BC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7921 0x4107BC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7922 0x4107BC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7923 0x4107BCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7924 0x4107BD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7925 0x4107BD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7926 0x4107BD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7927 0x4107BDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7928 0x4107BE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7929 0x4107BE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7930 0x4107BE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7931 0x4107BEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7932 0x4107BF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7933 0x4107BF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7934 0x4107BF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7935 0x4107BFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7936 0x4107C00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7937 0x4107C04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7938 0x4107C08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7939 0x4107C0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7940 0x4107C10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7941 0x4107C14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7942 0x4107C18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7943 0x4107C1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7944 0x4107C20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7945 0x4107C24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7946 0x4107C28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7947 0x4107C2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7948 0x4107C30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7949 0x4107C34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7950 0x4107C38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7951 0x4107C3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7952 0x4107C40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7953 0x4107C44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7954 0x4107C48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7955 0x4107C4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7956 0x4107C50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7957 0x4107C54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7958 0x4107C58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7959 0x4107C5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7960 0x4107C60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7961 0x4107C64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7962 0x4107C68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7963 0x4107C6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7964 0x4107C70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7965 0x4107C74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7966 0x4107C78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7967 0x4107C7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7968 0x4107C80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7969 0x4107C84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7970 0x4107C88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7971 0x4107C8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7972 0x4107C90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7973 0x4107C94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7974 0x4107C98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7975 0x4107C9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7976 0x4107CA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7977 0x4107CA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7978 0x4107CA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7979 0x4107CAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7980 0x4107CB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7981 0x4107CB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7982 0x4107CB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7983 0x4107CBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7984 0x4107CC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7985 0x4107CC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7986 0x4107CC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7987 0x4107CCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7988 0x4107CD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7989 0x4107CD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7990 0x4107CD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7991 0x4107CDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7992 0x4107CE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7993 0x4107CE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7994 0x4107CE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7995 0x4107CEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7996 0x4107CF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7997 0x4107CF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7998 0x4107CF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7999 0x4107CFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8000 0x4107D00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8001 0x4107D04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8002 0x4107D08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8003 0x4107D0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8004 0x4107D10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8005 0x4107D14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8006 0x4107D18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8007 0x4107D1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8008 0x4107D20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8009 0x4107D24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8010 0x4107D28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8011 0x4107D2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8012 0x4107D30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8013 0x4107D34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8014 0x4107D38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8015 0x4107D3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8016 0x4107D40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8017 0x4107D44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8018 0x4107D48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8019 0x4107D4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8020 0x4107D50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8021 0x4107D54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8022 0x4107D58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8023 0x4107D5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8024 0x4107D60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8025 0x4107D64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8026 0x4107D68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8027 0x4107D6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8028 0x4107D70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8029 0x4107D74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8030 0x4107D78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8031 0x4107D7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8032 0x4107D80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8033 0x4107D84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8034 0x4107D88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8035 0x4107D8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8036 0x4107D90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8037 0x4107D94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8038 0x4107D98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8039 0x4107D9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8040 0x4107DA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8041 0x4107DA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8042 0x4107DA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8043 0x4107DAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8044 0x4107DB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8045 0x4107DB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8046 0x4107DB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8047 0x4107DBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8048 0x4107DC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8049 0x4107DC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8050 0x4107DC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8051 0x4107DCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8052 0x4107DD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8053 0x4107DD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8054 0x4107DD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8055 0x4107DDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8056 0x4107DE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8057 0x4107DE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8058 0x4107DE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8059 0x4107DEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8060 0x4107DF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8061 0x4107DF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8062 0x4107DF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8063 0x4107DFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8064 0x4107E00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8065 0x4107E04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8066 0x4107E08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8067 0x4107E0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8068 0x4107E10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8069 0x4107E14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8070 0x4107E18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8071 0x4107E1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8072 0x4107E20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8073 0x4107E24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8074 0x4107E28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8075 0x4107E2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8076 0x4107E30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8077 0x4107E34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8078 0x4107E38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8079 0x4107E3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8080 0x4107E40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8081 0x4107E44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8082 0x4107E48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8083 0x4107E4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8084 0x4107E50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8085 0x4107E54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8086 0x4107E58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8087 0x4107E5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8088 0x4107E60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8089 0x4107E64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8090 0x4107E68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8091 0x4107E6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8092 0x4107E70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8093 0x4107E74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8094 0x4107E78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8095 0x4107E7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8096 0x4107E80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8097 0x4107E84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8098 0x4107E88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8099 0x4107E8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8100 0x4107E90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8101 0x4107E94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8102 0x4107E98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8103 0x4107E9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8104 0x4107EA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8105 0x4107EA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8106 0x4107EA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8107 0x4107EAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8108 0x4107EB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8109 0x4107EB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8110 0x4107EB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8111 0x4107EBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8112 0x4107EC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8113 0x4107EC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8114 0x4107EC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8115 0x4107ECC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8116 0x4107ED0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8117 0x4107ED4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8118 0x4107ED8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8119 0x4107EDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8120 0x4107EE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8121 0x4107EE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8122 0x4107EE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8123 0x4107EEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8124 0x4107EF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8125 0x4107EF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8126 0x4107EF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8127 0x4107EFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8128 0x4107F00
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8129 0x4107F04
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8130 0x4107F08
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8131 0x4107F0C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8132 0x4107F10
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8133 0x4107F14
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8134 0x4107F18
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8135 0x4107F1C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8136 0x4107F20
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8137 0x4107F24
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8138 0x4107F28
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8139 0x4107F2C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8140 0x4107F30
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8141 0x4107F34
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8142 0x4107F38
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8143 0x4107F3C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8144 0x4107F40
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8145 0x4107F44
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8146 0x4107F48
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8147 0x4107F4C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8148 0x4107F50
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8149 0x4107F54
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8150 0x4107F58
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8151 0x4107F5C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8152 0x4107F60
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8153 0x4107F64
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8154 0x4107F68
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8155 0x4107F6C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8156 0x4107F70
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8157 0x4107F74
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8158 0x4107F78
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8159 0x4107F7C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8160 0x4107F80
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8161 0x4107F84
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8162 0x4107F88
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8163 0x4107F8C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8164 0x4107F90
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8165 0x4107F94
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8166 0x4107F98
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8167 0x4107F9C
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8168 0x4107FA0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8169 0x4107FA4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8170 0x4107FA8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8171 0x4107FAC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8172 0x4107FB0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8173 0x4107FB4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8174 0x4107FB8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8175 0x4107FBC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8176 0x4107FC0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8177 0x4107FC4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8178 0x4107FC8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8179 0x4107FCC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8180 0x4107FD0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8181 0x4107FD4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8182 0x4107FD8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8183 0x4107FDC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8184 0x4107FE0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8185 0x4107FE4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8186 0x4107FE8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8187 0x4107FEC
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8188 0x4107FF0
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8189 0x4107FF4
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8190 0x4107FF8
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 0x4107FFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x4108000
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1 0x4108004
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2 0x4108008
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_3 0x410800C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_4 0x4108010
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_5 0x4108014
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_6 0x4108018
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_7 0x410801C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_8 0x4108020
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_9 0x4108024
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_10 0x4108028
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_11 0x410802C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_12 0x4108030
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_13 0x4108034
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_14 0x4108038
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_15 0x410803C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_16 0x4108040
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_17 0x4108044
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_18 0x4108048
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_19 0x410804C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_20 0x4108050
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_21 0x4108054
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_22 0x4108058
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_23 0x410805C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_24 0x4108060
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_25 0x4108064
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_26 0x4108068
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_27 0x410806C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_28 0x4108070
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_29 0x4108074
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_30 0x4108078
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_31 0x410807C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_32 0x4108080
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_33 0x4108084
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_34 0x4108088
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_35 0x410808C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_36 0x4108090
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_37 0x4108094
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_38 0x4108098
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_39 0x410809C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_40 0x41080A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_41 0x41080A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_42 0x41080A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_43 0x41080AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_44 0x41080B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_45 0x41080B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_46 0x41080B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_47 0x41080BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_48 0x41080C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_49 0x41080C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_50 0x41080C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_51 0x41080CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_52 0x41080D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_53 0x41080D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_54 0x41080D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_55 0x41080DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_56 0x41080E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_57 0x41080E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_58 0x41080E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_59 0x41080EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_60 0x41080F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_61 0x41080F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_62 0x41080F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_63 0x41080FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_64 0x4108100
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_65 0x4108104
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_66 0x4108108
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_67 0x410810C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_68 0x4108110
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_69 0x4108114
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_70 0x4108118
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_71 0x410811C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_72 0x4108120
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_73 0x4108124
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_74 0x4108128
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_75 0x410812C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_76 0x4108130
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_77 0x4108134
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_78 0x4108138
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_79 0x410813C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_80 0x4108140
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_81 0x4108144
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_82 0x4108148
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_83 0x410814C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_84 0x4108150
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_85 0x4108154
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_86 0x4108158
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_87 0x410815C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_88 0x4108160
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_89 0x4108164
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_90 0x4108168
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_91 0x410816C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_92 0x4108170
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_93 0x4108174
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_94 0x4108178
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_95 0x410817C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_96 0x4108180
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_97 0x4108184
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_98 0x4108188
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_99 0x410818C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_100 0x4108190
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_101 0x4108194
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_102 0x4108198
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_103 0x410819C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_104 0x41081A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_105 0x41081A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_106 0x41081A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_107 0x41081AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_108 0x41081B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_109 0x41081B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_110 0x41081B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_111 0x41081BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_112 0x41081C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_113 0x41081C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_114 0x41081C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_115 0x41081CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_116 0x41081D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_117 0x41081D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_118 0x41081D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_119 0x41081DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_120 0x41081E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_121 0x41081E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_122 0x41081E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_123 0x41081EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_124 0x41081F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_125 0x41081F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_126 0x41081F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_127 0x41081FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_128 0x4108200
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_129 0x4108204
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_130 0x4108208
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_131 0x410820C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_132 0x4108210
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_133 0x4108214
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_134 0x4108218
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_135 0x410821C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_136 0x4108220
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_137 0x4108224
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_138 0x4108228
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_139 0x410822C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_140 0x4108230
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_141 0x4108234
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_142 0x4108238
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_143 0x410823C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_144 0x4108240
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_145 0x4108244
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_146 0x4108248
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_147 0x410824C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_148 0x4108250
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_149 0x4108254
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_150 0x4108258
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_151 0x410825C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_152 0x4108260
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_153 0x4108264
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_154 0x4108268
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_155 0x410826C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_156 0x4108270
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_157 0x4108274
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_158 0x4108278
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_159 0x410827C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_160 0x4108280
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_161 0x4108284
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_162 0x4108288
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_163 0x410828C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_164 0x4108290
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_165 0x4108294
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_166 0x4108298
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_167 0x410829C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_168 0x41082A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_169 0x41082A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_170 0x41082A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_171 0x41082AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_172 0x41082B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_173 0x41082B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_174 0x41082B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_175 0x41082BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_176 0x41082C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_177 0x41082C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_178 0x41082C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_179 0x41082CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_180 0x41082D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_181 0x41082D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_182 0x41082D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_183 0x41082DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_184 0x41082E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_185 0x41082E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_186 0x41082E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_187 0x41082EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_188 0x41082F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_189 0x41082F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_190 0x41082F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_191 0x41082FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_192 0x4108300
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_193 0x4108304
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_194 0x4108308
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_195 0x410830C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_196 0x4108310
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_197 0x4108314
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_198 0x4108318
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_199 0x410831C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_200 0x4108320
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_201 0x4108324
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_202 0x4108328
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_203 0x410832C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_204 0x4108330
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_205 0x4108334
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_206 0x4108338
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_207 0x410833C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_208 0x4108340
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_209 0x4108344
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_210 0x4108348
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_211 0x410834C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_212 0x4108350
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_213 0x4108354
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_214 0x4108358
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_215 0x410835C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_216 0x4108360
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_217 0x4108364
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_218 0x4108368
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_219 0x410836C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_220 0x4108370
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_221 0x4108374
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_222 0x4108378
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_223 0x410837C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_224 0x4108380
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_225 0x4108384
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_226 0x4108388
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_227 0x410838C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_228 0x4108390
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_229 0x4108394
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_230 0x4108398
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_231 0x410839C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_232 0x41083A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_233 0x41083A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_234 0x41083A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_235 0x41083AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_236 0x41083B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_237 0x41083B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_238 0x41083B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_239 0x41083BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_240 0x41083C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_241 0x41083C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_242 0x41083C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_243 0x41083CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_244 0x41083D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_245 0x41083D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_246 0x41083D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_247 0x41083DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_248 0x41083E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_249 0x41083E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_250 0x41083E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_251 0x41083EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_252 0x41083F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_253 0x41083F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_254 0x41083F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_255 0x41083FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_256 0x4108400
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_257 0x4108404
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_258 0x4108408
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_259 0x410840C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_260 0x4108410
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_261 0x4108414
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_262 0x4108418
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_263 0x410841C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_264 0x4108420
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_265 0x4108424
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_266 0x4108428
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_267 0x410842C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_268 0x4108430
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_269 0x4108434
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_270 0x4108438
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_271 0x410843C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_272 0x4108440
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_273 0x4108444
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_274 0x4108448
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_275 0x410844C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_276 0x4108450
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_277 0x4108454
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_278 0x4108458
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_279 0x410845C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_280 0x4108460
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_281 0x4108464
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_282 0x4108468
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_283 0x410846C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_284 0x4108470
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_285 0x4108474
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_286 0x4108478
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_287 0x410847C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_288 0x4108480
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_289 0x4108484
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_290 0x4108488
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_291 0x410848C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_292 0x4108490
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_293 0x4108494
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_294 0x4108498
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_295 0x410849C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_296 0x41084A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_297 0x41084A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_298 0x41084A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_299 0x41084AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_300 0x41084B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_301 0x41084B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_302 0x41084B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_303 0x41084BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_304 0x41084C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_305 0x41084C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_306 0x41084C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_307 0x41084CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_308 0x41084D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_309 0x41084D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_310 0x41084D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_311 0x41084DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_312 0x41084E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_313 0x41084E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_314 0x41084E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_315 0x41084EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_316 0x41084F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_317 0x41084F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_318 0x41084F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_319 0x41084FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_320 0x4108500
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_321 0x4108504
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_322 0x4108508
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_323 0x410850C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_324 0x4108510
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_325 0x4108514
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_326 0x4108518
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_327 0x410851C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_328 0x4108520
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_329 0x4108524
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_330 0x4108528
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_331 0x410852C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_332 0x4108530
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_333 0x4108534
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_334 0x4108538
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_335 0x410853C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_336 0x4108540
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_337 0x4108544
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_338 0x4108548
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_339 0x410854C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_340 0x4108550
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_341 0x4108554
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_342 0x4108558
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_343 0x410855C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_344 0x4108560
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_345 0x4108564
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_346 0x4108568
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_347 0x410856C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_348 0x4108570
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_349 0x4108574
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_350 0x4108578
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_351 0x410857C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_352 0x4108580
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_353 0x4108584
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_354 0x4108588
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_355 0x410858C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_356 0x4108590
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_357 0x4108594
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_358 0x4108598
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_359 0x410859C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_360 0x41085A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_361 0x41085A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_362 0x41085A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_363 0x41085AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_364 0x41085B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_365 0x41085B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_366 0x41085B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_367 0x41085BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_368 0x41085C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_369 0x41085C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_370 0x41085C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_371 0x41085CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_372 0x41085D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_373 0x41085D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_374 0x41085D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_375 0x41085DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_376 0x41085E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_377 0x41085E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_378 0x41085E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_379 0x41085EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_380 0x41085F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_381 0x41085F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_382 0x41085F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_383 0x41085FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_384 0x4108600
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_385 0x4108604
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_386 0x4108608
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_387 0x410860C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_388 0x4108610
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_389 0x4108614
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_390 0x4108618
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_391 0x410861C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_392 0x4108620
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_393 0x4108624
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_394 0x4108628
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_395 0x410862C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_396 0x4108630
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_397 0x4108634
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_398 0x4108638
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_399 0x410863C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_400 0x4108640
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_401 0x4108644
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_402 0x4108648
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_403 0x410864C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_404 0x4108650
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_405 0x4108654
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_406 0x4108658
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_407 0x410865C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_408 0x4108660
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_409 0x4108664
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_410 0x4108668
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_411 0x410866C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_412 0x4108670
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_413 0x4108674
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_414 0x4108678
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_415 0x410867C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_416 0x4108680
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_417 0x4108684
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_418 0x4108688
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_419 0x410868C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_420 0x4108690
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_421 0x4108694
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_422 0x4108698
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_423 0x410869C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_424 0x41086A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_425 0x41086A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_426 0x41086A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_427 0x41086AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_428 0x41086B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_429 0x41086B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_430 0x41086B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_431 0x41086BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_432 0x41086C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_433 0x41086C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_434 0x41086C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_435 0x41086CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_436 0x41086D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_437 0x41086D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_438 0x41086D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_439 0x41086DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_440 0x41086E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_441 0x41086E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_442 0x41086E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_443 0x41086EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_444 0x41086F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_445 0x41086F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_446 0x41086F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_447 0x41086FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_448 0x4108700
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_449 0x4108704
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_450 0x4108708
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_451 0x410870C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_452 0x4108710
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_453 0x4108714
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_454 0x4108718
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_455 0x410871C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_456 0x4108720
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_457 0x4108724
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_458 0x4108728
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_459 0x410872C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_460 0x4108730
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_461 0x4108734
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_462 0x4108738
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_463 0x410873C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_464 0x4108740
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_465 0x4108744
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_466 0x4108748
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_467 0x410874C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_468 0x4108750
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_469 0x4108754
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_470 0x4108758
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_471 0x410875C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_472 0x4108760
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_473 0x4108764
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_474 0x4108768
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_475 0x410876C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_476 0x4108770
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_477 0x4108774
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_478 0x4108778
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_479 0x410877C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_480 0x4108780
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_481 0x4108784
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_482 0x4108788
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_483 0x410878C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_484 0x4108790
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_485 0x4108794
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_486 0x4108798
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_487 0x410879C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_488 0x41087A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_489 0x41087A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_490 0x41087A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_491 0x41087AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_492 0x41087B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_493 0x41087B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_494 0x41087B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_495 0x41087BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_496 0x41087C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_497 0x41087C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_498 0x41087C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_499 0x41087CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_500 0x41087D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_501 0x41087D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_502 0x41087D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_503 0x41087DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_504 0x41087E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_505 0x41087E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_506 0x41087E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_507 0x41087EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_508 0x41087F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_509 0x41087F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_510 0x41087F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_511 0x41087FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_512 0x4108800
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_513 0x4108804
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_514 0x4108808
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_515 0x410880C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_516 0x4108810
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_517 0x4108814
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_518 0x4108818
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_519 0x410881C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_520 0x4108820
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_521 0x4108824
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_522 0x4108828
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_523 0x410882C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_524 0x4108830
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_525 0x4108834
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_526 0x4108838
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_527 0x410883C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_528 0x4108840
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_529 0x4108844
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_530 0x4108848
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_531 0x410884C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_532 0x4108850
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_533 0x4108854
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_534 0x4108858
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_535 0x410885C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_536 0x4108860
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_537 0x4108864
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_538 0x4108868
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_539 0x410886C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_540 0x4108870
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_541 0x4108874
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_542 0x4108878
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_543 0x410887C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_544 0x4108880
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_545 0x4108884
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_546 0x4108888
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_547 0x410888C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_548 0x4108890
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_549 0x4108894
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_550 0x4108898
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_551 0x410889C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_552 0x41088A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_553 0x41088A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_554 0x41088A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_555 0x41088AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_556 0x41088B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_557 0x41088B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_558 0x41088B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_559 0x41088BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_560 0x41088C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_561 0x41088C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_562 0x41088C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_563 0x41088CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_564 0x41088D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_565 0x41088D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_566 0x41088D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_567 0x41088DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_568 0x41088E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_569 0x41088E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_570 0x41088E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_571 0x41088EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_572 0x41088F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_573 0x41088F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_574 0x41088F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_575 0x41088FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_576 0x4108900
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_577 0x4108904
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_578 0x4108908
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_579 0x410890C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_580 0x4108910
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_581 0x4108914
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_582 0x4108918
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_583 0x410891C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_584 0x4108920
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_585 0x4108924
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_586 0x4108928
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_587 0x410892C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_588 0x4108930
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_589 0x4108934
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_590 0x4108938
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_591 0x410893C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_592 0x4108940
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_593 0x4108944
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_594 0x4108948
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_595 0x410894C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_596 0x4108950
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_597 0x4108954
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_598 0x4108958
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_599 0x410895C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_600 0x4108960
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_601 0x4108964
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_602 0x4108968
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_603 0x410896C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_604 0x4108970
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_605 0x4108974
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_606 0x4108978
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_607 0x410897C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_608 0x4108980
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_609 0x4108984
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_610 0x4108988
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_611 0x410898C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_612 0x4108990
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_613 0x4108994
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_614 0x4108998
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_615 0x410899C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_616 0x41089A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_617 0x41089A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_618 0x41089A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_619 0x41089AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_620 0x41089B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_621 0x41089B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_622 0x41089B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_623 0x41089BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_624 0x41089C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_625 0x41089C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_626 0x41089C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_627 0x41089CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_628 0x41089D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_629 0x41089D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_630 0x41089D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_631 0x41089DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_632 0x41089E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_633 0x41089E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_634 0x41089E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_635 0x41089EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_636 0x41089F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_637 0x41089F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_638 0x41089F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_639 0x41089FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_640 0x4108A00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_641 0x4108A04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_642 0x4108A08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_643 0x4108A0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_644 0x4108A10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_645 0x4108A14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_646 0x4108A18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_647 0x4108A1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_648 0x4108A20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_649 0x4108A24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_650 0x4108A28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_651 0x4108A2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_652 0x4108A30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_653 0x4108A34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_654 0x4108A38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_655 0x4108A3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_656 0x4108A40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_657 0x4108A44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_658 0x4108A48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_659 0x4108A4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_660 0x4108A50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_661 0x4108A54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_662 0x4108A58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_663 0x4108A5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_664 0x4108A60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_665 0x4108A64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_666 0x4108A68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_667 0x4108A6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_668 0x4108A70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_669 0x4108A74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_670 0x4108A78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_671 0x4108A7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_672 0x4108A80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_673 0x4108A84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_674 0x4108A88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_675 0x4108A8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_676 0x4108A90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_677 0x4108A94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_678 0x4108A98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_679 0x4108A9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_680 0x4108AA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_681 0x4108AA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_682 0x4108AA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_683 0x4108AAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_684 0x4108AB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_685 0x4108AB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_686 0x4108AB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_687 0x4108ABC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_688 0x4108AC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_689 0x4108AC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_690 0x4108AC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_691 0x4108ACC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_692 0x4108AD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_693 0x4108AD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_694 0x4108AD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_695 0x4108ADC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_696 0x4108AE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_697 0x4108AE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_698 0x4108AE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_699 0x4108AEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_700 0x4108AF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_701 0x4108AF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_702 0x4108AF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_703 0x4108AFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_704 0x4108B00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_705 0x4108B04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_706 0x4108B08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_707 0x4108B0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_708 0x4108B10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_709 0x4108B14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_710 0x4108B18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_711 0x4108B1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_712 0x4108B20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_713 0x4108B24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_714 0x4108B28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_715 0x4108B2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_716 0x4108B30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_717 0x4108B34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_718 0x4108B38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_719 0x4108B3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_720 0x4108B40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_721 0x4108B44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_722 0x4108B48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_723 0x4108B4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_724 0x4108B50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_725 0x4108B54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_726 0x4108B58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_727 0x4108B5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_728 0x4108B60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_729 0x4108B64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_730 0x4108B68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_731 0x4108B6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_732 0x4108B70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_733 0x4108B74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_734 0x4108B78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_735 0x4108B7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_736 0x4108B80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_737 0x4108B84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_738 0x4108B88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_739 0x4108B8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_740 0x4108B90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_741 0x4108B94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_742 0x4108B98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_743 0x4108B9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_744 0x4108BA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_745 0x4108BA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_746 0x4108BA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_747 0x4108BAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_748 0x4108BB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_749 0x4108BB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_750 0x4108BB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_751 0x4108BBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_752 0x4108BC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_753 0x4108BC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_754 0x4108BC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_755 0x4108BCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_756 0x4108BD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_757 0x4108BD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_758 0x4108BD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_759 0x4108BDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_760 0x4108BE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_761 0x4108BE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_762 0x4108BE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_763 0x4108BEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_764 0x4108BF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_765 0x4108BF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_766 0x4108BF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_767 0x4108BFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_768 0x4108C00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_769 0x4108C04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_770 0x4108C08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_771 0x4108C0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_772 0x4108C10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_773 0x4108C14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_774 0x4108C18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_775 0x4108C1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_776 0x4108C20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_777 0x4108C24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_778 0x4108C28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_779 0x4108C2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_780 0x4108C30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_781 0x4108C34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_782 0x4108C38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_783 0x4108C3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_784 0x4108C40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_785 0x4108C44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_786 0x4108C48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_787 0x4108C4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_788 0x4108C50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_789 0x4108C54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_790 0x4108C58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_791 0x4108C5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_792 0x4108C60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_793 0x4108C64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_794 0x4108C68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_795 0x4108C6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_796 0x4108C70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_797 0x4108C74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_798 0x4108C78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_799 0x4108C7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_800 0x4108C80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_801 0x4108C84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_802 0x4108C88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_803 0x4108C8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_804 0x4108C90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_805 0x4108C94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_806 0x4108C98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_807 0x4108C9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_808 0x4108CA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_809 0x4108CA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_810 0x4108CA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_811 0x4108CAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_812 0x4108CB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_813 0x4108CB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_814 0x4108CB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_815 0x4108CBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_816 0x4108CC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_817 0x4108CC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_818 0x4108CC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_819 0x4108CCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_820 0x4108CD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_821 0x4108CD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_822 0x4108CD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_823 0x4108CDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_824 0x4108CE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_825 0x4108CE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_826 0x4108CE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_827 0x4108CEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_828 0x4108CF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_829 0x4108CF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_830 0x4108CF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_831 0x4108CFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_832 0x4108D00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_833 0x4108D04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_834 0x4108D08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_835 0x4108D0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_836 0x4108D10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_837 0x4108D14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_838 0x4108D18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_839 0x4108D1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_840 0x4108D20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_841 0x4108D24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_842 0x4108D28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_843 0x4108D2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_844 0x4108D30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_845 0x4108D34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_846 0x4108D38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_847 0x4108D3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_848 0x4108D40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_849 0x4108D44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_850 0x4108D48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_851 0x4108D4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_852 0x4108D50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_853 0x4108D54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_854 0x4108D58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_855 0x4108D5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_856 0x4108D60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_857 0x4108D64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_858 0x4108D68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_859 0x4108D6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_860 0x4108D70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_861 0x4108D74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_862 0x4108D78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_863 0x4108D7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_864 0x4108D80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_865 0x4108D84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_866 0x4108D88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_867 0x4108D8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_868 0x4108D90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_869 0x4108D94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_870 0x4108D98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_871 0x4108D9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_872 0x4108DA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_873 0x4108DA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_874 0x4108DA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_875 0x4108DAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_876 0x4108DB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_877 0x4108DB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_878 0x4108DB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_879 0x4108DBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_880 0x4108DC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_881 0x4108DC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_882 0x4108DC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_883 0x4108DCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_884 0x4108DD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_885 0x4108DD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_886 0x4108DD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_887 0x4108DDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_888 0x4108DE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_889 0x4108DE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_890 0x4108DE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_891 0x4108DEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_892 0x4108DF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_893 0x4108DF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_894 0x4108DF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_895 0x4108DFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_896 0x4108E00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_897 0x4108E04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_898 0x4108E08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_899 0x4108E0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_900 0x4108E10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_901 0x4108E14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_902 0x4108E18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_903 0x4108E1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_904 0x4108E20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_905 0x4108E24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_906 0x4108E28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_907 0x4108E2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_908 0x4108E30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_909 0x4108E34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_910 0x4108E38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_911 0x4108E3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_912 0x4108E40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_913 0x4108E44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_914 0x4108E48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_915 0x4108E4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_916 0x4108E50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_917 0x4108E54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_918 0x4108E58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_919 0x4108E5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_920 0x4108E60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_921 0x4108E64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_922 0x4108E68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_923 0x4108E6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_924 0x4108E70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_925 0x4108E74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_926 0x4108E78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_927 0x4108E7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_928 0x4108E80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_929 0x4108E84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_930 0x4108E88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_931 0x4108E8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_932 0x4108E90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_933 0x4108E94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_934 0x4108E98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_935 0x4108E9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_936 0x4108EA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_937 0x4108EA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_938 0x4108EA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_939 0x4108EAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_940 0x4108EB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_941 0x4108EB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_942 0x4108EB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_943 0x4108EBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_944 0x4108EC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_945 0x4108EC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_946 0x4108EC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_947 0x4108ECC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_948 0x4108ED0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_949 0x4108ED4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_950 0x4108ED8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_951 0x4108EDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_952 0x4108EE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_953 0x4108EE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_954 0x4108EE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_955 0x4108EEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_956 0x4108EF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_957 0x4108EF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_958 0x4108EF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_959 0x4108EFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_960 0x4108F00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_961 0x4108F04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_962 0x4108F08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_963 0x4108F0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_964 0x4108F10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_965 0x4108F14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_966 0x4108F18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_967 0x4108F1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_968 0x4108F20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_969 0x4108F24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_970 0x4108F28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_971 0x4108F2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_972 0x4108F30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_973 0x4108F34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_974 0x4108F38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_975 0x4108F3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_976 0x4108F40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_977 0x4108F44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_978 0x4108F48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_979 0x4108F4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_980 0x4108F50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_981 0x4108F54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_982 0x4108F58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_983 0x4108F5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_984 0x4108F60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_985 0x4108F64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_986 0x4108F68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_987 0x4108F6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_988 0x4108F70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_989 0x4108F74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_990 0x4108F78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_991 0x4108F7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_992 0x4108F80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_993 0x4108F84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_994 0x4108F88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_995 0x4108F8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_996 0x4108F90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_997 0x4108F94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_998 0x4108F98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_999 0x4108F9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1000 0x4108FA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1001 0x4108FA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1002 0x4108FA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1003 0x4108FAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1004 0x4108FB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1005 0x4108FB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1006 0x4108FB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1007 0x4108FBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1008 0x4108FC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1009 0x4108FC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1010 0x4108FC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1011 0x4108FCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1012 0x4108FD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1013 0x4108FD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1014 0x4108FD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1015 0x4108FDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1016 0x4108FE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1017 0x4108FE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1018 0x4108FE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1019 0x4108FEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1020 0x4108FF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1021 0x4108FF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1022 0x4108FF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1023 0x4108FFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1024 0x4109000
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1025 0x4109004
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1026 0x4109008
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1027 0x410900C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1028 0x4109010
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1029 0x4109014
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1030 0x4109018
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1031 0x410901C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1032 0x4109020
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1033 0x4109024
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1034 0x4109028
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1035 0x410902C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1036 0x4109030
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1037 0x4109034
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1038 0x4109038
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1039 0x410903C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1040 0x4109040
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1041 0x4109044
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1042 0x4109048
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1043 0x410904C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1044 0x4109050
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1045 0x4109054
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1046 0x4109058
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1047 0x410905C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1048 0x4109060
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1049 0x4109064
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1050 0x4109068
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1051 0x410906C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1052 0x4109070
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1053 0x4109074
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1054 0x4109078
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1055 0x410907C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1056 0x4109080
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1057 0x4109084
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1058 0x4109088
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1059 0x410908C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1060 0x4109090
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1061 0x4109094
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1062 0x4109098
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1063 0x410909C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1064 0x41090A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1065 0x41090A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1066 0x41090A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1067 0x41090AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1068 0x41090B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1069 0x41090B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1070 0x41090B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1071 0x41090BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1072 0x41090C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1073 0x41090C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1074 0x41090C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1075 0x41090CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1076 0x41090D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1077 0x41090D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1078 0x41090D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1079 0x41090DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1080 0x41090E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1081 0x41090E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1082 0x41090E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1083 0x41090EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1084 0x41090F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1085 0x41090F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1086 0x41090F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1087 0x41090FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1088 0x4109100
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1089 0x4109104
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1090 0x4109108
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1091 0x410910C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1092 0x4109110
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1093 0x4109114
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1094 0x4109118
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1095 0x410911C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1096 0x4109120
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1097 0x4109124
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1098 0x4109128
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1099 0x410912C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1100 0x4109130
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1101 0x4109134
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1102 0x4109138
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1103 0x410913C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1104 0x4109140
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1105 0x4109144
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1106 0x4109148
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1107 0x410914C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1108 0x4109150
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1109 0x4109154
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1110 0x4109158
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1111 0x410915C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1112 0x4109160
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1113 0x4109164
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1114 0x4109168
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1115 0x410916C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1116 0x4109170
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1117 0x4109174
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1118 0x4109178
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1119 0x410917C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1120 0x4109180
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1121 0x4109184
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1122 0x4109188
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1123 0x410918C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1124 0x4109190
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1125 0x4109194
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1126 0x4109198
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1127 0x410919C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1128 0x41091A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1129 0x41091A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1130 0x41091A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1131 0x41091AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1132 0x41091B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1133 0x41091B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1134 0x41091B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1135 0x41091BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1136 0x41091C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1137 0x41091C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1138 0x41091C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1139 0x41091CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1140 0x41091D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1141 0x41091D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1142 0x41091D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1143 0x41091DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1144 0x41091E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1145 0x41091E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1146 0x41091E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1147 0x41091EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1148 0x41091F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1149 0x41091F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1150 0x41091F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1151 0x41091FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1152 0x4109200
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1153 0x4109204
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1154 0x4109208
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1155 0x410920C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1156 0x4109210
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1157 0x4109214
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1158 0x4109218
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1159 0x410921C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1160 0x4109220
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1161 0x4109224
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1162 0x4109228
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1163 0x410922C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1164 0x4109230
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1165 0x4109234
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1166 0x4109238
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1167 0x410923C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1168 0x4109240
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1169 0x4109244
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1170 0x4109248
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1171 0x410924C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1172 0x4109250
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1173 0x4109254
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1174 0x4109258
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1175 0x410925C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1176 0x4109260
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1177 0x4109264
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1178 0x4109268
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1179 0x410926C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1180 0x4109270
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1181 0x4109274
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1182 0x4109278
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1183 0x410927C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1184 0x4109280
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1185 0x4109284
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1186 0x4109288
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1187 0x410928C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1188 0x4109290
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1189 0x4109294
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1190 0x4109298
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1191 0x410929C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1192 0x41092A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1193 0x41092A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1194 0x41092A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1195 0x41092AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1196 0x41092B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1197 0x41092B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1198 0x41092B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1199 0x41092BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1200 0x41092C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1201 0x41092C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1202 0x41092C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1203 0x41092CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1204 0x41092D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1205 0x41092D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1206 0x41092D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1207 0x41092DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1208 0x41092E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1209 0x41092E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1210 0x41092E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1211 0x41092EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1212 0x41092F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1213 0x41092F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1214 0x41092F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1215 0x41092FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1216 0x4109300
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1217 0x4109304
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1218 0x4109308
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1219 0x410930C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1220 0x4109310
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1221 0x4109314
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1222 0x4109318
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1223 0x410931C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1224 0x4109320
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1225 0x4109324
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1226 0x4109328
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1227 0x410932C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1228 0x4109330
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1229 0x4109334
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1230 0x4109338
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1231 0x410933C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1232 0x4109340
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1233 0x4109344
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1234 0x4109348
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1235 0x410934C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1236 0x4109350
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1237 0x4109354
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1238 0x4109358
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1239 0x410935C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1240 0x4109360
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1241 0x4109364
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1242 0x4109368
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1243 0x410936C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1244 0x4109370
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1245 0x4109374
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1246 0x4109378
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1247 0x410937C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1248 0x4109380
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1249 0x4109384
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1250 0x4109388
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1251 0x410938C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1252 0x4109390
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1253 0x4109394
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1254 0x4109398
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1255 0x410939C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1256 0x41093A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1257 0x41093A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1258 0x41093A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1259 0x41093AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1260 0x41093B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1261 0x41093B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1262 0x41093B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1263 0x41093BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1264 0x41093C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1265 0x41093C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1266 0x41093C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1267 0x41093CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1268 0x41093D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1269 0x41093D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1270 0x41093D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1271 0x41093DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1272 0x41093E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1273 0x41093E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1274 0x41093E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1275 0x41093EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1276 0x41093F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1277 0x41093F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1278 0x41093F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1279 0x41093FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1280 0x4109400
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1281 0x4109404
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1282 0x4109408
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1283 0x410940C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1284 0x4109410
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1285 0x4109414
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1286 0x4109418
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1287 0x410941C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1288 0x4109420
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1289 0x4109424
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1290 0x4109428
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1291 0x410942C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1292 0x4109430
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1293 0x4109434
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1294 0x4109438
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1295 0x410943C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1296 0x4109440
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1297 0x4109444
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1298 0x4109448
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1299 0x410944C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1300 0x4109450
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1301 0x4109454
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1302 0x4109458
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1303 0x410945C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1304 0x4109460
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1305 0x4109464
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1306 0x4109468
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1307 0x410946C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1308 0x4109470
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1309 0x4109474
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1310 0x4109478
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1311 0x410947C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1312 0x4109480
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1313 0x4109484
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1314 0x4109488
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1315 0x410948C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1316 0x4109490
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1317 0x4109494
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1318 0x4109498
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1319 0x410949C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1320 0x41094A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1321 0x41094A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1322 0x41094A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1323 0x41094AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1324 0x41094B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1325 0x41094B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1326 0x41094B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1327 0x41094BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1328 0x41094C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1329 0x41094C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1330 0x41094C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1331 0x41094CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1332 0x41094D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1333 0x41094D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1334 0x41094D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1335 0x41094DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1336 0x41094E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1337 0x41094E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1338 0x41094E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1339 0x41094EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1340 0x41094F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1341 0x41094F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1342 0x41094F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1343 0x41094FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1344 0x4109500
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1345 0x4109504
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1346 0x4109508
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1347 0x410950C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1348 0x4109510
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1349 0x4109514
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1350 0x4109518
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1351 0x410951C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1352 0x4109520
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1353 0x4109524
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1354 0x4109528
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1355 0x410952C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1356 0x4109530
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1357 0x4109534
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1358 0x4109538
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1359 0x410953C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1360 0x4109540
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1361 0x4109544
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1362 0x4109548
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1363 0x410954C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1364 0x4109550
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1365 0x4109554
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1366 0x4109558
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1367 0x410955C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1368 0x4109560
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1369 0x4109564
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1370 0x4109568
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1371 0x410956C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1372 0x4109570
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1373 0x4109574
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1374 0x4109578
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1375 0x410957C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1376 0x4109580
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1377 0x4109584
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1378 0x4109588
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1379 0x410958C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1380 0x4109590
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1381 0x4109594
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1382 0x4109598
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1383 0x410959C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1384 0x41095A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1385 0x41095A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1386 0x41095A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1387 0x41095AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1388 0x41095B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1389 0x41095B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1390 0x41095B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1391 0x41095BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1392 0x41095C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1393 0x41095C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1394 0x41095C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1395 0x41095CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1396 0x41095D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1397 0x41095D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1398 0x41095D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1399 0x41095DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1400 0x41095E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1401 0x41095E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1402 0x41095E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1403 0x41095EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1404 0x41095F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1405 0x41095F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1406 0x41095F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1407 0x41095FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1408 0x4109600
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1409 0x4109604
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1410 0x4109608
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1411 0x410960C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1412 0x4109610
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1413 0x4109614
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1414 0x4109618
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1415 0x410961C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1416 0x4109620
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1417 0x4109624
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1418 0x4109628
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1419 0x410962C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1420 0x4109630
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1421 0x4109634
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1422 0x4109638
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1423 0x410963C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1424 0x4109640
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1425 0x4109644
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1426 0x4109648
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1427 0x410964C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1428 0x4109650
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1429 0x4109654
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1430 0x4109658
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1431 0x410965C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1432 0x4109660
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1433 0x4109664
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1434 0x4109668
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1435 0x410966C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1436 0x4109670
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1437 0x4109674
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1438 0x4109678
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1439 0x410967C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1440 0x4109680
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1441 0x4109684
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1442 0x4109688
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1443 0x410968C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1444 0x4109690
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1445 0x4109694
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1446 0x4109698
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1447 0x410969C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1448 0x41096A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1449 0x41096A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1450 0x41096A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1451 0x41096AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1452 0x41096B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1453 0x41096B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1454 0x41096B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1455 0x41096BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1456 0x41096C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1457 0x41096C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1458 0x41096C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1459 0x41096CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1460 0x41096D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1461 0x41096D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1462 0x41096D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1463 0x41096DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1464 0x41096E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1465 0x41096E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1466 0x41096E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1467 0x41096EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1468 0x41096F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1469 0x41096F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1470 0x41096F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1471 0x41096FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1472 0x4109700
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1473 0x4109704
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1474 0x4109708
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1475 0x410970C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1476 0x4109710
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1477 0x4109714
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1478 0x4109718
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1479 0x410971C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1480 0x4109720
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1481 0x4109724
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1482 0x4109728
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1483 0x410972C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1484 0x4109730
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1485 0x4109734
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1486 0x4109738
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1487 0x410973C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1488 0x4109740
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1489 0x4109744
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1490 0x4109748
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1491 0x410974C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1492 0x4109750
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1493 0x4109754
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1494 0x4109758
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1495 0x410975C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1496 0x4109760
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1497 0x4109764
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1498 0x4109768
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1499 0x410976C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1500 0x4109770
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1501 0x4109774
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1502 0x4109778
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1503 0x410977C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1504 0x4109780
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1505 0x4109784
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1506 0x4109788
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1507 0x410978C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1508 0x4109790
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1509 0x4109794
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1510 0x4109798
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1511 0x410979C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1512 0x41097A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1513 0x41097A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1514 0x41097A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1515 0x41097AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1516 0x41097B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1517 0x41097B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1518 0x41097B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1519 0x41097BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1520 0x41097C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1521 0x41097C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1522 0x41097C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1523 0x41097CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1524 0x41097D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1525 0x41097D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1526 0x41097D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1527 0x41097DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1528 0x41097E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1529 0x41097E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1530 0x41097E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1531 0x41097EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1532 0x41097F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1533 0x41097F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1534 0x41097F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1535 0x41097FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1536 0x4109800
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1537 0x4109804
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1538 0x4109808
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1539 0x410980C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1540 0x4109810
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1541 0x4109814
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1542 0x4109818
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1543 0x410981C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1544 0x4109820
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1545 0x4109824
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1546 0x4109828
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1547 0x410982C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1548 0x4109830
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1549 0x4109834
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1550 0x4109838
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1551 0x410983C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1552 0x4109840
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1553 0x4109844
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1554 0x4109848
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1555 0x410984C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1556 0x4109850
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1557 0x4109854
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1558 0x4109858
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1559 0x410985C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1560 0x4109860
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1561 0x4109864
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1562 0x4109868
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1563 0x410986C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1564 0x4109870
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1565 0x4109874
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1566 0x4109878
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1567 0x410987C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1568 0x4109880
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1569 0x4109884
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1570 0x4109888
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1571 0x410988C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1572 0x4109890
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1573 0x4109894
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1574 0x4109898
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1575 0x410989C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1576 0x41098A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1577 0x41098A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1578 0x41098A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1579 0x41098AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1580 0x41098B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1581 0x41098B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1582 0x41098B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1583 0x41098BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1584 0x41098C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1585 0x41098C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1586 0x41098C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1587 0x41098CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1588 0x41098D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1589 0x41098D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1590 0x41098D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1591 0x41098DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1592 0x41098E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1593 0x41098E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1594 0x41098E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1595 0x41098EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1596 0x41098F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1597 0x41098F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1598 0x41098F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1599 0x41098FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1600 0x4109900
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1601 0x4109904
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1602 0x4109908
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1603 0x410990C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1604 0x4109910
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1605 0x4109914
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1606 0x4109918
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1607 0x410991C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1608 0x4109920
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1609 0x4109924
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1610 0x4109928
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1611 0x410992C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1612 0x4109930
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1613 0x4109934
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1614 0x4109938
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1615 0x410993C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1616 0x4109940
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1617 0x4109944
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1618 0x4109948
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1619 0x410994C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1620 0x4109950
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1621 0x4109954
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1622 0x4109958
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1623 0x410995C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1624 0x4109960
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1625 0x4109964
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1626 0x4109968
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1627 0x410996C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1628 0x4109970
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1629 0x4109974
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1630 0x4109978
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1631 0x410997C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1632 0x4109980
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1633 0x4109984
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1634 0x4109988
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1635 0x410998C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1636 0x4109990
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1637 0x4109994
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1638 0x4109998
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1639 0x410999C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1640 0x41099A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1641 0x41099A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1642 0x41099A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1643 0x41099AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1644 0x41099B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1645 0x41099B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1646 0x41099B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1647 0x41099BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1648 0x41099C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1649 0x41099C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1650 0x41099C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1651 0x41099CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1652 0x41099D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1653 0x41099D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1654 0x41099D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1655 0x41099DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1656 0x41099E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1657 0x41099E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1658 0x41099E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1659 0x41099EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1660 0x41099F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1661 0x41099F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1662 0x41099F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1663 0x41099FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1664 0x4109A00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1665 0x4109A04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1666 0x4109A08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1667 0x4109A0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1668 0x4109A10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1669 0x4109A14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1670 0x4109A18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1671 0x4109A1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1672 0x4109A20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1673 0x4109A24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1674 0x4109A28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1675 0x4109A2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1676 0x4109A30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1677 0x4109A34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1678 0x4109A38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1679 0x4109A3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1680 0x4109A40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1681 0x4109A44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1682 0x4109A48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1683 0x4109A4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1684 0x4109A50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1685 0x4109A54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1686 0x4109A58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1687 0x4109A5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1688 0x4109A60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1689 0x4109A64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1690 0x4109A68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1691 0x4109A6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1692 0x4109A70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1693 0x4109A74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1694 0x4109A78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1695 0x4109A7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1696 0x4109A80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1697 0x4109A84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1698 0x4109A88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1699 0x4109A8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1700 0x4109A90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1701 0x4109A94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1702 0x4109A98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1703 0x4109A9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1704 0x4109AA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1705 0x4109AA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1706 0x4109AA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1707 0x4109AAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1708 0x4109AB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1709 0x4109AB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1710 0x4109AB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1711 0x4109ABC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1712 0x4109AC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1713 0x4109AC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1714 0x4109AC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1715 0x4109ACC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1716 0x4109AD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1717 0x4109AD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1718 0x4109AD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1719 0x4109ADC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1720 0x4109AE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1721 0x4109AE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1722 0x4109AE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1723 0x4109AEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1724 0x4109AF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1725 0x4109AF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1726 0x4109AF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1727 0x4109AFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1728 0x4109B00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1729 0x4109B04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1730 0x4109B08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1731 0x4109B0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1732 0x4109B10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1733 0x4109B14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1734 0x4109B18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1735 0x4109B1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1736 0x4109B20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1737 0x4109B24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1738 0x4109B28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1739 0x4109B2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1740 0x4109B30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1741 0x4109B34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1742 0x4109B38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1743 0x4109B3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1744 0x4109B40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1745 0x4109B44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1746 0x4109B48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1747 0x4109B4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1748 0x4109B50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1749 0x4109B54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1750 0x4109B58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1751 0x4109B5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1752 0x4109B60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1753 0x4109B64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1754 0x4109B68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1755 0x4109B6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1756 0x4109B70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1757 0x4109B74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1758 0x4109B78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1759 0x4109B7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1760 0x4109B80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1761 0x4109B84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1762 0x4109B88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1763 0x4109B8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1764 0x4109B90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1765 0x4109B94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1766 0x4109B98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1767 0x4109B9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1768 0x4109BA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1769 0x4109BA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1770 0x4109BA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1771 0x4109BAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1772 0x4109BB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1773 0x4109BB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1774 0x4109BB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1775 0x4109BBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1776 0x4109BC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1777 0x4109BC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1778 0x4109BC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1779 0x4109BCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1780 0x4109BD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1781 0x4109BD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1782 0x4109BD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1783 0x4109BDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1784 0x4109BE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1785 0x4109BE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1786 0x4109BE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1787 0x4109BEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1788 0x4109BF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1789 0x4109BF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1790 0x4109BF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1791 0x4109BFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1792 0x4109C00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1793 0x4109C04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1794 0x4109C08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1795 0x4109C0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1796 0x4109C10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1797 0x4109C14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1798 0x4109C18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1799 0x4109C1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1800 0x4109C20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1801 0x4109C24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1802 0x4109C28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1803 0x4109C2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1804 0x4109C30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1805 0x4109C34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1806 0x4109C38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1807 0x4109C3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1808 0x4109C40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1809 0x4109C44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1810 0x4109C48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1811 0x4109C4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1812 0x4109C50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1813 0x4109C54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1814 0x4109C58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1815 0x4109C5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1816 0x4109C60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1817 0x4109C64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1818 0x4109C68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1819 0x4109C6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1820 0x4109C70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1821 0x4109C74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1822 0x4109C78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1823 0x4109C7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1824 0x4109C80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1825 0x4109C84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1826 0x4109C88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1827 0x4109C8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1828 0x4109C90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1829 0x4109C94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1830 0x4109C98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1831 0x4109C9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1832 0x4109CA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1833 0x4109CA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1834 0x4109CA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1835 0x4109CAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1836 0x4109CB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1837 0x4109CB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1838 0x4109CB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1839 0x4109CBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1840 0x4109CC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1841 0x4109CC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1842 0x4109CC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1843 0x4109CCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1844 0x4109CD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1845 0x4109CD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1846 0x4109CD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1847 0x4109CDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1848 0x4109CE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1849 0x4109CE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1850 0x4109CE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1851 0x4109CEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1852 0x4109CF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1853 0x4109CF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1854 0x4109CF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1855 0x4109CFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1856 0x4109D00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1857 0x4109D04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1858 0x4109D08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1859 0x4109D0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1860 0x4109D10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1861 0x4109D14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1862 0x4109D18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1863 0x4109D1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1864 0x4109D20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1865 0x4109D24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1866 0x4109D28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1867 0x4109D2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1868 0x4109D30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1869 0x4109D34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1870 0x4109D38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1871 0x4109D3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1872 0x4109D40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1873 0x4109D44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1874 0x4109D48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1875 0x4109D4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1876 0x4109D50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1877 0x4109D54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1878 0x4109D58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1879 0x4109D5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1880 0x4109D60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1881 0x4109D64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1882 0x4109D68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1883 0x4109D6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1884 0x4109D70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1885 0x4109D74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1886 0x4109D78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1887 0x4109D7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1888 0x4109D80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1889 0x4109D84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1890 0x4109D88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1891 0x4109D8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1892 0x4109D90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1893 0x4109D94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1894 0x4109D98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1895 0x4109D9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1896 0x4109DA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1897 0x4109DA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1898 0x4109DA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1899 0x4109DAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1900 0x4109DB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1901 0x4109DB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1902 0x4109DB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1903 0x4109DBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1904 0x4109DC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1905 0x4109DC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1906 0x4109DC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1907 0x4109DCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1908 0x4109DD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1909 0x4109DD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1910 0x4109DD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1911 0x4109DDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1912 0x4109DE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1913 0x4109DE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1914 0x4109DE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1915 0x4109DEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1916 0x4109DF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1917 0x4109DF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1918 0x4109DF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1919 0x4109DFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1920 0x4109E00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1921 0x4109E04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1922 0x4109E08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1923 0x4109E0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1924 0x4109E10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1925 0x4109E14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1926 0x4109E18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1927 0x4109E1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1928 0x4109E20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1929 0x4109E24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1930 0x4109E28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1931 0x4109E2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1932 0x4109E30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1933 0x4109E34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1934 0x4109E38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1935 0x4109E3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1936 0x4109E40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1937 0x4109E44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1938 0x4109E48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1939 0x4109E4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1940 0x4109E50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1941 0x4109E54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1942 0x4109E58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1943 0x4109E5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1944 0x4109E60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1945 0x4109E64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1946 0x4109E68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1947 0x4109E6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1948 0x4109E70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1949 0x4109E74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1950 0x4109E78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1951 0x4109E7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1952 0x4109E80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1953 0x4109E84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1954 0x4109E88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1955 0x4109E8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1956 0x4109E90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1957 0x4109E94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1958 0x4109E98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1959 0x4109E9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1960 0x4109EA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1961 0x4109EA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1962 0x4109EA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1963 0x4109EAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1964 0x4109EB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1965 0x4109EB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1966 0x4109EB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1967 0x4109EBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1968 0x4109EC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1969 0x4109EC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1970 0x4109EC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1971 0x4109ECC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1972 0x4109ED0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1973 0x4109ED4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1974 0x4109ED8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1975 0x4109EDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1976 0x4109EE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1977 0x4109EE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1978 0x4109EE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1979 0x4109EEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1980 0x4109EF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1981 0x4109EF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1982 0x4109EF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1983 0x4109EFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1984 0x4109F00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1985 0x4109F04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1986 0x4109F08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1987 0x4109F0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1988 0x4109F10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1989 0x4109F14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1990 0x4109F18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1991 0x4109F1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1992 0x4109F20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1993 0x4109F24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1994 0x4109F28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1995 0x4109F2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1996 0x4109F30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1997 0x4109F34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1998 0x4109F38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1999 0x4109F3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2000 0x4109F40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2001 0x4109F44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2002 0x4109F48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2003 0x4109F4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2004 0x4109F50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2005 0x4109F54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2006 0x4109F58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2007 0x4109F5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2008 0x4109F60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2009 0x4109F64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2010 0x4109F68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2011 0x4109F6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2012 0x4109F70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2013 0x4109F74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2014 0x4109F78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2015 0x4109F7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2016 0x4109F80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2017 0x4109F84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2018 0x4109F88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2019 0x4109F8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2020 0x4109F90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2021 0x4109F94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2022 0x4109F98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2023 0x4109F9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2024 0x4109FA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2025 0x4109FA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2026 0x4109FA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2027 0x4109FAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2028 0x4109FB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2029 0x4109FB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2030 0x4109FB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2031 0x4109FBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2032 0x4109FC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2033 0x4109FC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2034 0x4109FC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2035 0x4109FCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2036 0x4109FD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2037 0x4109FD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2038 0x4109FD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2039 0x4109FDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2040 0x4109FE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2041 0x4109FE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2042 0x4109FE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2043 0x4109FEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2044 0x4109FF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2045 0x4109FF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2046 0x4109FF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2047 0x4109FFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x410A000
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1 0x410A004
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2 0x410A008
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_3 0x410A00C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_4 0x410A010
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_5 0x410A014
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_6 0x410A018
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_7 0x410A01C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_8 0x410A020
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_9 0x410A024
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_10 0x410A028
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_11 0x410A02C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_12 0x410A030
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_13 0x410A034
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_14 0x410A038
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_15 0x410A03C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_16 0x410A040
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_17 0x410A044
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_18 0x410A048
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_19 0x410A04C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_20 0x410A050
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_21 0x410A054
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_22 0x410A058
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_23 0x410A05C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_24 0x410A060
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_25 0x410A064
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_26 0x410A068
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_27 0x410A06C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_28 0x410A070
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_29 0x410A074
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_30 0x410A078
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_31 0x410A07C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_32 0x410A080
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_33 0x410A084
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_34 0x410A088
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_35 0x410A08C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_36 0x410A090
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_37 0x410A094
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_38 0x410A098
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_39 0x410A09C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_40 0x410A0A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_41 0x410A0A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_42 0x410A0A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_43 0x410A0AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_44 0x410A0B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_45 0x410A0B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_46 0x410A0B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_47 0x410A0BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_48 0x410A0C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_49 0x410A0C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_50 0x410A0C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_51 0x410A0CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_52 0x410A0D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_53 0x410A0D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_54 0x410A0D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_55 0x410A0DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_56 0x410A0E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_57 0x410A0E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_58 0x410A0E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_59 0x410A0EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_60 0x410A0F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_61 0x410A0F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_62 0x410A0F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_63 0x410A0FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_64 0x410A100
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_65 0x410A104
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_66 0x410A108
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_67 0x410A10C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_68 0x410A110
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_69 0x410A114
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_70 0x410A118
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_71 0x410A11C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_72 0x410A120
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_73 0x410A124
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_74 0x410A128
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_75 0x410A12C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_76 0x410A130
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_77 0x410A134
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_78 0x410A138
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_79 0x410A13C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_80 0x410A140
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_81 0x410A144
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_82 0x410A148
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_83 0x410A14C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_84 0x410A150
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_85 0x410A154
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_86 0x410A158
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_87 0x410A15C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_88 0x410A160
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_89 0x410A164
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_90 0x410A168
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_91 0x410A16C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_92 0x410A170
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_93 0x410A174
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_94 0x410A178
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_95 0x410A17C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_96 0x410A180
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_97 0x410A184
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_98 0x410A188
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_99 0x410A18C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_100 0x410A190
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_101 0x410A194
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_102 0x410A198
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_103 0x410A19C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_104 0x410A1A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_105 0x410A1A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_106 0x410A1A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_107 0x410A1AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_108 0x410A1B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_109 0x410A1B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_110 0x410A1B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_111 0x410A1BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_112 0x410A1C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_113 0x410A1C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_114 0x410A1C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_115 0x410A1CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_116 0x410A1D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_117 0x410A1D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_118 0x410A1D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_119 0x410A1DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_120 0x410A1E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_121 0x410A1E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_122 0x410A1E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_123 0x410A1EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_124 0x410A1F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_125 0x410A1F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_126 0x410A1F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_127 0x410A1FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_128 0x410A200
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_129 0x410A204
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_130 0x410A208
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_131 0x410A20C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_132 0x410A210
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_133 0x410A214
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_134 0x410A218
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_135 0x410A21C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_136 0x410A220
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_137 0x410A224
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_138 0x410A228
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_139 0x410A22C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_140 0x410A230
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_141 0x410A234
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_142 0x410A238
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_143 0x410A23C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_144 0x410A240
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_145 0x410A244
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_146 0x410A248
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_147 0x410A24C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_148 0x410A250
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_149 0x410A254
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_150 0x410A258
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_151 0x410A25C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_152 0x410A260
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_153 0x410A264
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_154 0x410A268
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_155 0x410A26C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_156 0x410A270
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_157 0x410A274
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_158 0x410A278
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_159 0x410A27C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_160 0x410A280
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_161 0x410A284
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_162 0x410A288
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_163 0x410A28C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_164 0x410A290
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_165 0x410A294
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_166 0x410A298
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_167 0x410A29C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_168 0x410A2A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_169 0x410A2A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_170 0x410A2A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_171 0x410A2AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_172 0x410A2B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_173 0x410A2B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_174 0x410A2B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_175 0x410A2BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_176 0x410A2C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_177 0x410A2C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_178 0x410A2C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_179 0x410A2CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_180 0x410A2D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_181 0x410A2D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_182 0x410A2D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_183 0x410A2DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_184 0x410A2E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_185 0x410A2E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_186 0x410A2E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_187 0x410A2EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_188 0x410A2F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_189 0x410A2F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_190 0x410A2F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_191 0x410A2FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_192 0x410A300
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_193 0x410A304
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_194 0x410A308
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_195 0x410A30C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_196 0x410A310
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_197 0x410A314
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_198 0x410A318
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_199 0x410A31C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_200 0x410A320
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_201 0x410A324
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_202 0x410A328
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_203 0x410A32C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_204 0x410A330
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_205 0x410A334
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_206 0x410A338
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_207 0x410A33C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_208 0x410A340
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_209 0x410A344
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_210 0x410A348
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_211 0x410A34C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_212 0x410A350
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_213 0x410A354
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_214 0x410A358
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_215 0x410A35C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_216 0x410A360
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_217 0x410A364
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_218 0x410A368
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_219 0x410A36C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_220 0x410A370
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_221 0x410A374
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_222 0x410A378
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_223 0x410A37C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_224 0x410A380
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_225 0x410A384
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_226 0x410A388
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_227 0x410A38C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_228 0x410A390
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_229 0x410A394
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_230 0x410A398
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_231 0x410A39C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_232 0x410A3A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_233 0x410A3A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_234 0x410A3A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_235 0x410A3AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_236 0x410A3B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_237 0x410A3B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_238 0x410A3B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_239 0x410A3BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_240 0x410A3C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_241 0x410A3C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_242 0x410A3C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_243 0x410A3CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_244 0x410A3D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_245 0x410A3D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_246 0x410A3D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_247 0x410A3DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_248 0x410A3E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_249 0x410A3E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_250 0x410A3E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_251 0x410A3EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_252 0x410A3F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_253 0x410A3F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_254 0x410A3F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_255 0x410A3FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_256 0x410A400
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_257 0x410A404
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_258 0x410A408
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_259 0x410A40C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_260 0x410A410
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_261 0x410A414
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_262 0x410A418
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_263 0x410A41C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_264 0x410A420
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_265 0x410A424
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_266 0x410A428
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_267 0x410A42C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_268 0x410A430
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_269 0x410A434
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_270 0x410A438
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_271 0x410A43C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_272 0x410A440
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_273 0x410A444
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_274 0x410A448
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_275 0x410A44C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_276 0x410A450
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_277 0x410A454
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_278 0x410A458
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_279 0x410A45C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_280 0x410A460
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_281 0x410A464
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_282 0x410A468
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_283 0x410A46C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_284 0x410A470
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_285 0x410A474
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_286 0x410A478
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_287 0x410A47C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_288 0x410A480
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_289 0x410A484
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_290 0x410A488
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_291 0x410A48C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_292 0x410A490
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_293 0x410A494
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_294 0x410A498
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_295 0x410A49C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_296 0x410A4A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_297 0x410A4A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_298 0x410A4A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_299 0x410A4AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_300 0x410A4B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_301 0x410A4B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_302 0x410A4B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_303 0x410A4BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_304 0x410A4C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_305 0x410A4C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_306 0x410A4C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_307 0x410A4CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_308 0x410A4D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_309 0x410A4D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_310 0x410A4D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_311 0x410A4DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_312 0x410A4E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_313 0x410A4E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_314 0x410A4E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_315 0x410A4EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_316 0x410A4F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_317 0x410A4F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_318 0x410A4F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_319 0x410A4FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_320 0x410A500
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_321 0x410A504
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_322 0x410A508
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_323 0x410A50C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_324 0x410A510
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_325 0x410A514
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_326 0x410A518
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_327 0x410A51C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_328 0x410A520
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_329 0x410A524
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_330 0x410A528
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_331 0x410A52C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_332 0x410A530
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_333 0x410A534
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_334 0x410A538
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_335 0x410A53C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_336 0x410A540
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_337 0x410A544
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_338 0x410A548
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_339 0x410A54C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_340 0x410A550
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_341 0x410A554
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_342 0x410A558
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_343 0x410A55C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_344 0x410A560
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_345 0x410A564
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_346 0x410A568
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_347 0x410A56C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_348 0x410A570
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_349 0x410A574
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_350 0x410A578
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_351 0x410A57C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_352 0x410A580
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_353 0x410A584
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_354 0x410A588
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_355 0x410A58C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_356 0x410A590
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_357 0x410A594
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_358 0x410A598
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_359 0x410A59C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_360 0x410A5A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_361 0x410A5A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_362 0x410A5A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_363 0x410A5AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_364 0x410A5B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_365 0x410A5B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_366 0x410A5B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_367 0x410A5BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_368 0x410A5C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_369 0x410A5C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_370 0x410A5C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_371 0x410A5CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_372 0x410A5D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_373 0x410A5D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_374 0x410A5D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_375 0x410A5DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_376 0x410A5E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_377 0x410A5E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_378 0x410A5E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_379 0x410A5EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_380 0x410A5F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_381 0x410A5F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_382 0x410A5F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_383 0x410A5FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_384 0x410A600
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_385 0x410A604
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_386 0x410A608
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_387 0x410A60C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_388 0x410A610
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_389 0x410A614
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_390 0x410A618
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_391 0x410A61C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_392 0x410A620
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_393 0x410A624
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_394 0x410A628
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_395 0x410A62C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_396 0x410A630
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_397 0x410A634
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_398 0x410A638
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_399 0x410A63C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_400 0x410A640
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_401 0x410A644
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_402 0x410A648
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_403 0x410A64C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_404 0x410A650
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_405 0x410A654
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_406 0x410A658
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_407 0x410A65C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_408 0x410A660
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_409 0x410A664
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_410 0x410A668
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_411 0x410A66C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_412 0x410A670
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_413 0x410A674
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_414 0x410A678
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_415 0x410A67C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_416 0x410A680
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_417 0x410A684
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_418 0x410A688
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_419 0x410A68C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_420 0x410A690
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_421 0x410A694
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_422 0x410A698
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_423 0x410A69C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_424 0x410A6A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_425 0x410A6A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_426 0x410A6A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_427 0x410A6AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_428 0x410A6B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_429 0x410A6B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_430 0x410A6B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_431 0x410A6BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_432 0x410A6C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_433 0x410A6C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_434 0x410A6C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_435 0x410A6CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_436 0x410A6D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_437 0x410A6D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_438 0x410A6D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_439 0x410A6DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_440 0x410A6E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_441 0x410A6E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_442 0x410A6E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_443 0x410A6EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_444 0x410A6F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_445 0x410A6F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_446 0x410A6F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_447 0x410A6FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_448 0x410A700
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_449 0x410A704
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_450 0x410A708
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_451 0x410A70C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_452 0x410A710
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_453 0x410A714
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_454 0x410A718
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_455 0x410A71C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_456 0x410A720
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_457 0x410A724
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_458 0x410A728
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_459 0x410A72C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_460 0x410A730
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_461 0x410A734
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_462 0x410A738
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_463 0x410A73C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_464 0x410A740
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_465 0x410A744
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_466 0x410A748
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_467 0x410A74C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_468 0x410A750
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_469 0x410A754
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_470 0x410A758
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_471 0x410A75C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_472 0x410A760
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_473 0x410A764
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_474 0x410A768
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_475 0x410A76C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_476 0x410A770
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_477 0x410A774
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_478 0x410A778
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_479 0x410A77C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_480 0x410A780
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_481 0x410A784
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_482 0x410A788
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_483 0x410A78C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_484 0x410A790
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_485 0x410A794
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_486 0x410A798
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_487 0x410A79C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_488 0x410A7A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_489 0x410A7A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_490 0x410A7A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_491 0x410A7AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_492 0x410A7B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_493 0x410A7B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_494 0x410A7B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_495 0x410A7BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_496 0x410A7C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_497 0x410A7C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_498 0x410A7C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_499 0x410A7CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_500 0x410A7D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_501 0x410A7D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_502 0x410A7D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_503 0x410A7DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_504 0x410A7E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_505 0x410A7E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_506 0x410A7E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_507 0x410A7EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_508 0x410A7F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_509 0x410A7F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_510 0x410A7F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_511 0x410A7FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_512 0x410A800
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_513 0x410A804
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_514 0x410A808
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_515 0x410A80C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_516 0x410A810
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_517 0x410A814
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_518 0x410A818
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_519 0x410A81C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_520 0x410A820
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_521 0x410A824
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_522 0x410A828
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_523 0x410A82C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_524 0x410A830
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_525 0x410A834
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_526 0x410A838
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_527 0x410A83C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_528 0x410A840
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_529 0x410A844
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_530 0x410A848
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_531 0x410A84C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_532 0x410A850
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_533 0x410A854
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_534 0x410A858
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_535 0x410A85C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_536 0x410A860
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_537 0x410A864
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_538 0x410A868
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_539 0x410A86C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_540 0x410A870
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_541 0x410A874
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_542 0x410A878
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_543 0x410A87C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_544 0x410A880
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_545 0x410A884
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_546 0x410A888
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_547 0x410A88C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_548 0x410A890
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_549 0x410A894
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_550 0x410A898
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_551 0x410A89C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_552 0x410A8A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_553 0x410A8A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_554 0x410A8A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_555 0x410A8AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_556 0x410A8B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_557 0x410A8B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_558 0x410A8B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_559 0x410A8BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_560 0x410A8C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_561 0x410A8C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_562 0x410A8C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_563 0x410A8CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_564 0x410A8D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_565 0x410A8D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_566 0x410A8D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_567 0x410A8DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_568 0x410A8E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_569 0x410A8E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_570 0x410A8E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_571 0x410A8EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_572 0x410A8F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_573 0x410A8F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_574 0x410A8F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_575 0x410A8FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_576 0x410A900
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_577 0x410A904
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_578 0x410A908
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_579 0x410A90C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_580 0x410A910
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_581 0x410A914
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_582 0x410A918
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_583 0x410A91C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_584 0x410A920
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_585 0x410A924
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_586 0x410A928
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_587 0x410A92C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_588 0x410A930
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_589 0x410A934
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_590 0x410A938
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_591 0x410A93C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_592 0x410A940
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_593 0x410A944
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_594 0x410A948
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_595 0x410A94C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_596 0x410A950
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_597 0x410A954
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_598 0x410A958
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_599 0x410A95C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_600 0x410A960
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_601 0x410A964
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_602 0x410A968
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_603 0x410A96C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_604 0x410A970
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_605 0x410A974
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_606 0x410A978
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_607 0x410A97C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_608 0x410A980
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_609 0x410A984
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_610 0x410A988
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_611 0x410A98C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_612 0x410A990
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_613 0x410A994
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_614 0x410A998
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_615 0x410A99C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_616 0x410A9A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_617 0x410A9A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_618 0x410A9A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_619 0x410A9AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_620 0x410A9B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_621 0x410A9B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_622 0x410A9B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_623 0x410A9BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_624 0x410A9C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_625 0x410A9C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_626 0x410A9C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_627 0x410A9CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_628 0x410A9D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_629 0x410A9D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_630 0x410A9D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_631 0x410A9DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_632 0x410A9E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_633 0x410A9E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_634 0x410A9E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_635 0x410A9EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_636 0x410A9F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_637 0x410A9F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_638 0x410A9F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_639 0x410A9FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_640 0x410AA00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_641 0x410AA04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_642 0x410AA08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_643 0x410AA0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_644 0x410AA10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_645 0x410AA14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_646 0x410AA18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_647 0x410AA1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_648 0x410AA20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_649 0x410AA24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_650 0x410AA28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_651 0x410AA2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_652 0x410AA30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_653 0x410AA34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_654 0x410AA38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_655 0x410AA3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_656 0x410AA40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_657 0x410AA44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_658 0x410AA48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_659 0x410AA4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_660 0x410AA50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_661 0x410AA54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_662 0x410AA58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_663 0x410AA5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_664 0x410AA60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_665 0x410AA64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_666 0x410AA68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_667 0x410AA6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_668 0x410AA70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_669 0x410AA74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_670 0x410AA78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_671 0x410AA7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_672 0x410AA80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_673 0x410AA84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_674 0x410AA88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_675 0x410AA8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_676 0x410AA90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_677 0x410AA94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_678 0x410AA98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_679 0x410AA9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_680 0x410AAA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_681 0x410AAA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_682 0x410AAA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_683 0x410AAAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_684 0x410AAB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_685 0x410AAB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_686 0x410AAB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_687 0x410AABC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_688 0x410AAC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_689 0x410AAC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_690 0x410AAC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_691 0x410AACC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_692 0x410AAD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_693 0x410AAD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_694 0x410AAD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_695 0x410AADC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_696 0x410AAE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_697 0x410AAE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_698 0x410AAE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_699 0x410AAEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_700 0x410AAF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_701 0x410AAF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_702 0x410AAF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_703 0x410AAFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_704 0x410AB00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_705 0x410AB04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_706 0x410AB08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_707 0x410AB0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_708 0x410AB10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_709 0x410AB14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_710 0x410AB18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_711 0x410AB1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_712 0x410AB20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_713 0x410AB24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_714 0x410AB28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_715 0x410AB2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_716 0x410AB30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_717 0x410AB34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_718 0x410AB38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_719 0x410AB3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_720 0x410AB40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_721 0x410AB44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_722 0x410AB48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_723 0x410AB4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_724 0x410AB50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_725 0x410AB54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_726 0x410AB58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_727 0x410AB5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_728 0x410AB60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_729 0x410AB64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_730 0x410AB68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_731 0x410AB6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_732 0x410AB70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_733 0x410AB74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_734 0x410AB78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_735 0x410AB7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_736 0x410AB80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_737 0x410AB84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_738 0x410AB88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_739 0x410AB8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_740 0x410AB90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_741 0x410AB94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_742 0x410AB98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_743 0x410AB9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_744 0x410ABA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_745 0x410ABA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_746 0x410ABA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_747 0x410ABAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_748 0x410ABB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_749 0x410ABB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_750 0x410ABB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_751 0x410ABBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_752 0x410ABC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_753 0x410ABC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_754 0x410ABC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_755 0x410ABCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_756 0x410ABD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_757 0x410ABD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_758 0x410ABD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_759 0x410ABDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_760 0x410ABE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_761 0x410ABE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_762 0x410ABE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_763 0x410ABEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_764 0x410ABF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_765 0x410ABF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_766 0x410ABF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_767 0x410ABFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_768 0x410AC00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_769 0x410AC04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_770 0x410AC08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_771 0x410AC0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_772 0x410AC10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_773 0x410AC14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_774 0x410AC18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_775 0x410AC1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_776 0x410AC20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_777 0x410AC24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_778 0x410AC28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_779 0x410AC2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_780 0x410AC30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_781 0x410AC34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_782 0x410AC38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_783 0x410AC3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_784 0x410AC40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_785 0x410AC44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_786 0x410AC48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_787 0x410AC4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_788 0x410AC50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_789 0x410AC54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_790 0x410AC58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_791 0x410AC5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_792 0x410AC60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_793 0x410AC64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_794 0x410AC68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_795 0x410AC6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_796 0x410AC70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_797 0x410AC74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_798 0x410AC78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_799 0x410AC7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_800 0x410AC80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_801 0x410AC84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_802 0x410AC88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_803 0x410AC8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_804 0x410AC90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_805 0x410AC94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_806 0x410AC98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_807 0x410AC9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_808 0x410ACA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_809 0x410ACA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_810 0x410ACA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_811 0x410ACAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_812 0x410ACB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_813 0x410ACB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_814 0x410ACB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_815 0x410ACBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_816 0x410ACC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_817 0x410ACC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_818 0x410ACC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_819 0x410ACCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_820 0x410ACD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_821 0x410ACD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_822 0x410ACD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_823 0x410ACDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_824 0x410ACE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_825 0x410ACE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_826 0x410ACE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_827 0x410ACEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_828 0x410ACF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_829 0x410ACF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_830 0x410ACF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_831 0x410ACFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_832 0x410AD00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_833 0x410AD04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_834 0x410AD08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_835 0x410AD0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_836 0x410AD10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_837 0x410AD14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_838 0x410AD18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_839 0x410AD1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_840 0x410AD20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_841 0x410AD24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_842 0x410AD28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_843 0x410AD2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_844 0x410AD30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_845 0x410AD34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_846 0x410AD38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_847 0x410AD3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_848 0x410AD40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_849 0x410AD44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_850 0x410AD48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_851 0x410AD4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_852 0x410AD50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_853 0x410AD54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_854 0x410AD58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_855 0x410AD5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_856 0x410AD60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_857 0x410AD64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_858 0x410AD68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_859 0x410AD6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_860 0x410AD70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_861 0x410AD74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_862 0x410AD78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_863 0x410AD7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_864 0x410AD80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_865 0x410AD84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_866 0x410AD88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_867 0x410AD8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_868 0x410AD90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_869 0x410AD94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_870 0x410AD98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_871 0x410AD9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_872 0x410ADA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_873 0x410ADA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_874 0x410ADA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_875 0x410ADAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_876 0x410ADB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_877 0x410ADB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_878 0x410ADB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_879 0x410ADBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_880 0x410ADC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_881 0x410ADC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_882 0x410ADC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_883 0x410ADCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_884 0x410ADD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_885 0x410ADD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_886 0x410ADD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_887 0x410ADDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_888 0x410ADE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_889 0x410ADE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_890 0x410ADE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_891 0x410ADEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_892 0x410ADF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_893 0x410ADF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_894 0x410ADF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_895 0x410ADFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_896 0x410AE00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_897 0x410AE04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_898 0x410AE08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_899 0x410AE0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_900 0x410AE10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_901 0x410AE14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_902 0x410AE18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_903 0x410AE1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_904 0x410AE20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_905 0x410AE24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_906 0x410AE28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_907 0x410AE2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_908 0x410AE30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_909 0x410AE34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_910 0x410AE38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_911 0x410AE3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_912 0x410AE40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_913 0x410AE44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_914 0x410AE48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_915 0x410AE4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_916 0x410AE50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_917 0x410AE54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_918 0x410AE58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_919 0x410AE5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_920 0x410AE60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_921 0x410AE64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_922 0x410AE68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_923 0x410AE6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_924 0x410AE70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_925 0x410AE74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_926 0x410AE78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_927 0x410AE7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_928 0x410AE80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_929 0x410AE84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_930 0x410AE88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_931 0x410AE8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_932 0x410AE90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_933 0x410AE94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_934 0x410AE98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_935 0x410AE9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_936 0x410AEA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_937 0x410AEA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_938 0x410AEA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_939 0x410AEAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_940 0x410AEB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_941 0x410AEB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_942 0x410AEB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_943 0x410AEBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_944 0x410AEC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_945 0x410AEC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_946 0x410AEC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_947 0x410AECC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_948 0x410AED0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_949 0x410AED4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_950 0x410AED8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_951 0x410AEDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_952 0x410AEE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_953 0x410AEE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_954 0x410AEE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_955 0x410AEEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_956 0x410AEF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_957 0x410AEF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_958 0x410AEF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_959 0x410AEFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_960 0x410AF00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_961 0x410AF04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_962 0x410AF08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_963 0x410AF0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_964 0x410AF10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_965 0x410AF14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_966 0x410AF18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_967 0x410AF1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_968 0x410AF20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_969 0x410AF24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_970 0x410AF28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_971 0x410AF2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_972 0x410AF30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_973 0x410AF34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_974 0x410AF38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_975 0x410AF3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_976 0x410AF40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_977 0x410AF44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_978 0x410AF48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_979 0x410AF4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_980 0x410AF50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_981 0x410AF54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_982 0x410AF58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_983 0x410AF5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_984 0x410AF60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_985 0x410AF64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_986 0x410AF68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_987 0x410AF6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_988 0x410AF70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_989 0x410AF74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_990 0x410AF78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_991 0x410AF7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_992 0x410AF80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_993 0x410AF84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_994 0x410AF88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_995 0x410AF8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_996 0x410AF90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_997 0x410AF94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_998 0x410AF98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_999 0x410AF9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1000 0x410AFA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1001 0x410AFA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1002 0x410AFA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1003 0x410AFAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1004 0x410AFB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1005 0x410AFB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1006 0x410AFB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1007 0x410AFBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1008 0x410AFC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1009 0x410AFC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1010 0x410AFC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1011 0x410AFCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1012 0x410AFD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1013 0x410AFD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1014 0x410AFD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1015 0x410AFDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1016 0x410AFE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1017 0x410AFE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1018 0x410AFE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1019 0x410AFEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1020 0x410AFF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1021 0x410AFF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1022 0x410AFF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1023 0x410AFFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1024 0x410B000
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1025 0x410B004
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1026 0x410B008
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1027 0x410B00C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1028 0x410B010
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1029 0x410B014
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1030 0x410B018
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1031 0x410B01C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1032 0x410B020
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1033 0x410B024
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1034 0x410B028
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1035 0x410B02C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1036 0x410B030
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1037 0x410B034
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1038 0x410B038
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1039 0x410B03C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1040 0x410B040
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1041 0x410B044
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1042 0x410B048
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1043 0x410B04C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1044 0x410B050
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1045 0x410B054
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1046 0x410B058
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1047 0x410B05C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1048 0x410B060
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1049 0x410B064
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1050 0x410B068
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1051 0x410B06C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1052 0x410B070
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1053 0x410B074
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1054 0x410B078
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1055 0x410B07C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1056 0x410B080
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1057 0x410B084
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1058 0x410B088
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1059 0x410B08C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1060 0x410B090
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1061 0x410B094
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1062 0x410B098
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1063 0x410B09C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1064 0x410B0A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1065 0x410B0A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1066 0x410B0A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1067 0x410B0AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1068 0x410B0B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1069 0x410B0B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1070 0x410B0B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1071 0x410B0BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1072 0x410B0C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1073 0x410B0C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1074 0x410B0C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1075 0x410B0CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1076 0x410B0D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1077 0x410B0D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1078 0x410B0D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1079 0x410B0DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1080 0x410B0E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1081 0x410B0E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1082 0x410B0E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1083 0x410B0EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1084 0x410B0F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1085 0x410B0F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1086 0x410B0F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1087 0x410B0FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1088 0x410B100
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1089 0x410B104
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1090 0x410B108
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1091 0x410B10C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1092 0x410B110
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1093 0x410B114
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1094 0x410B118
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1095 0x410B11C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1096 0x410B120
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1097 0x410B124
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1098 0x410B128
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1099 0x410B12C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1100 0x410B130
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1101 0x410B134
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1102 0x410B138
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1103 0x410B13C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1104 0x410B140
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1105 0x410B144
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1106 0x410B148
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1107 0x410B14C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1108 0x410B150
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1109 0x410B154
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1110 0x410B158
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1111 0x410B15C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1112 0x410B160
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1113 0x410B164
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1114 0x410B168
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1115 0x410B16C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1116 0x410B170
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1117 0x410B174
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1118 0x410B178
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1119 0x410B17C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1120 0x410B180
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1121 0x410B184
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1122 0x410B188
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1123 0x410B18C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1124 0x410B190
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1125 0x410B194
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1126 0x410B198
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1127 0x410B19C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1128 0x410B1A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1129 0x410B1A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1130 0x410B1A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1131 0x410B1AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1132 0x410B1B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1133 0x410B1B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1134 0x410B1B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1135 0x410B1BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1136 0x410B1C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1137 0x410B1C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1138 0x410B1C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1139 0x410B1CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1140 0x410B1D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1141 0x410B1D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1142 0x410B1D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1143 0x410B1DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1144 0x410B1E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1145 0x410B1E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1146 0x410B1E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1147 0x410B1EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1148 0x410B1F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1149 0x410B1F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1150 0x410B1F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1151 0x410B1FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1152 0x410B200
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1153 0x410B204
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1154 0x410B208
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1155 0x410B20C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1156 0x410B210
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1157 0x410B214
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1158 0x410B218
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1159 0x410B21C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1160 0x410B220
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1161 0x410B224
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1162 0x410B228
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1163 0x410B22C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1164 0x410B230
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1165 0x410B234
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1166 0x410B238
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1167 0x410B23C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1168 0x410B240
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1169 0x410B244
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1170 0x410B248
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1171 0x410B24C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1172 0x410B250
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1173 0x410B254
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1174 0x410B258
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1175 0x410B25C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1176 0x410B260
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1177 0x410B264
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1178 0x410B268
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1179 0x410B26C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1180 0x410B270
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1181 0x410B274
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1182 0x410B278
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1183 0x410B27C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1184 0x410B280
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1185 0x410B284
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1186 0x410B288
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1187 0x410B28C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1188 0x410B290
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1189 0x410B294
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1190 0x410B298
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1191 0x410B29C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1192 0x410B2A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1193 0x410B2A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1194 0x410B2A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1195 0x410B2AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1196 0x410B2B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1197 0x410B2B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1198 0x410B2B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1199 0x410B2BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1200 0x410B2C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1201 0x410B2C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1202 0x410B2C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1203 0x410B2CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1204 0x410B2D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1205 0x410B2D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1206 0x410B2D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1207 0x410B2DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1208 0x410B2E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1209 0x410B2E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1210 0x410B2E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1211 0x410B2EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1212 0x410B2F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1213 0x410B2F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1214 0x410B2F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1215 0x410B2FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1216 0x410B300
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1217 0x410B304
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1218 0x410B308
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1219 0x410B30C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1220 0x410B310
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1221 0x410B314
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1222 0x410B318
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1223 0x410B31C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1224 0x410B320
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1225 0x410B324
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1226 0x410B328
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1227 0x410B32C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1228 0x410B330
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1229 0x410B334
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1230 0x410B338
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1231 0x410B33C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1232 0x410B340
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1233 0x410B344
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1234 0x410B348
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1235 0x410B34C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1236 0x410B350
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1237 0x410B354
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1238 0x410B358
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1239 0x410B35C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1240 0x410B360
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1241 0x410B364
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1242 0x410B368
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1243 0x410B36C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1244 0x410B370
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1245 0x410B374
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1246 0x410B378
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1247 0x410B37C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1248 0x410B380
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1249 0x410B384
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1250 0x410B388
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1251 0x410B38C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1252 0x410B390
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1253 0x410B394
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1254 0x410B398
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1255 0x410B39C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1256 0x410B3A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1257 0x410B3A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1258 0x410B3A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1259 0x410B3AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1260 0x410B3B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1261 0x410B3B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1262 0x410B3B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1263 0x410B3BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1264 0x410B3C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1265 0x410B3C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1266 0x410B3C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1267 0x410B3CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1268 0x410B3D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1269 0x410B3D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1270 0x410B3D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1271 0x410B3DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1272 0x410B3E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1273 0x410B3E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1274 0x410B3E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1275 0x410B3EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1276 0x410B3F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1277 0x410B3F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1278 0x410B3F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1279 0x410B3FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1280 0x410B400
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1281 0x410B404
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1282 0x410B408
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1283 0x410B40C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1284 0x410B410
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1285 0x410B414
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1286 0x410B418
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1287 0x410B41C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1288 0x410B420
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1289 0x410B424
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1290 0x410B428
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1291 0x410B42C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1292 0x410B430
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1293 0x410B434
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1294 0x410B438
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1295 0x410B43C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1296 0x410B440
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1297 0x410B444
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1298 0x410B448
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1299 0x410B44C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1300 0x410B450
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1301 0x410B454
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1302 0x410B458
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1303 0x410B45C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1304 0x410B460
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1305 0x410B464
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1306 0x410B468
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1307 0x410B46C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1308 0x410B470
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1309 0x410B474
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1310 0x410B478
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1311 0x410B47C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1312 0x410B480
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1313 0x410B484
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1314 0x410B488
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1315 0x410B48C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1316 0x410B490
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1317 0x410B494
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1318 0x410B498
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1319 0x410B49C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1320 0x410B4A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1321 0x410B4A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1322 0x410B4A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1323 0x410B4AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1324 0x410B4B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1325 0x410B4B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1326 0x410B4B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1327 0x410B4BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1328 0x410B4C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1329 0x410B4C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1330 0x410B4C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1331 0x410B4CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1332 0x410B4D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1333 0x410B4D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1334 0x410B4D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1335 0x410B4DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1336 0x410B4E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1337 0x410B4E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1338 0x410B4E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1339 0x410B4EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1340 0x410B4F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1341 0x410B4F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1342 0x410B4F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1343 0x410B4FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1344 0x410B500
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1345 0x410B504
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1346 0x410B508
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1347 0x410B50C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1348 0x410B510
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1349 0x410B514
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1350 0x410B518
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1351 0x410B51C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1352 0x410B520
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1353 0x410B524
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1354 0x410B528
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1355 0x410B52C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1356 0x410B530
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1357 0x410B534
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1358 0x410B538
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1359 0x410B53C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1360 0x410B540
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1361 0x410B544
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1362 0x410B548
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1363 0x410B54C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1364 0x410B550
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1365 0x410B554
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1366 0x410B558
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1367 0x410B55C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1368 0x410B560
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1369 0x410B564
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1370 0x410B568
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1371 0x410B56C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1372 0x410B570
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1373 0x410B574
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1374 0x410B578
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1375 0x410B57C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1376 0x410B580
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1377 0x410B584
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1378 0x410B588
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1379 0x410B58C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1380 0x410B590
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1381 0x410B594
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1382 0x410B598
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1383 0x410B59C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1384 0x410B5A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1385 0x410B5A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1386 0x410B5A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1387 0x410B5AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1388 0x410B5B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1389 0x410B5B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1390 0x410B5B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1391 0x410B5BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1392 0x410B5C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1393 0x410B5C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1394 0x410B5C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1395 0x410B5CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1396 0x410B5D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1397 0x410B5D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1398 0x410B5D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1399 0x410B5DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1400 0x410B5E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1401 0x410B5E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1402 0x410B5E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1403 0x410B5EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1404 0x410B5F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1405 0x410B5F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1406 0x410B5F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1407 0x410B5FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1408 0x410B600
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1409 0x410B604
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1410 0x410B608
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1411 0x410B60C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1412 0x410B610
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1413 0x410B614
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1414 0x410B618
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1415 0x410B61C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1416 0x410B620
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1417 0x410B624
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1418 0x410B628
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1419 0x410B62C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1420 0x410B630
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1421 0x410B634
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1422 0x410B638
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1423 0x410B63C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1424 0x410B640
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1425 0x410B644
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1426 0x410B648
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1427 0x410B64C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1428 0x410B650
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1429 0x410B654
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1430 0x410B658
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1431 0x410B65C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1432 0x410B660
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1433 0x410B664
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1434 0x410B668
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1435 0x410B66C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1436 0x410B670
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1437 0x410B674
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1438 0x410B678
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1439 0x410B67C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1440 0x410B680
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1441 0x410B684
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1442 0x410B688
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1443 0x410B68C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1444 0x410B690
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1445 0x410B694
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1446 0x410B698
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1447 0x410B69C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1448 0x410B6A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1449 0x410B6A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1450 0x410B6A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1451 0x410B6AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1452 0x410B6B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1453 0x410B6B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1454 0x410B6B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1455 0x410B6BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1456 0x410B6C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1457 0x410B6C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1458 0x410B6C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1459 0x410B6CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1460 0x410B6D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1461 0x410B6D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1462 0x410B6D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1463 0x410B6DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1464 0x410B6E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1465 0x410B6E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1466 0x410B6E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1467 0x410B6EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1468 0x410B6F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1469 0x410B6F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1470 0x410B6F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1471 0x410B6FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1472 0x410B700
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1473 0x410B704
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1474 0x410B708
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1475 0x410B70C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1476 0x410B710
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1477 0x410B714
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1478 0x410B718
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1479 0x410B71C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1480 0x410B720
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1481 0x410B724
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1482 0x410B728
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1483 0x410B72C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1484 0x410B730
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1485 0x410B734
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1486 0x410B738
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1487 0x410B73C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1488 0x410B740
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1489 0x410B744
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1490 0x410B748
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1491 0x410B74C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1492 0x410B750
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1493 0x410B754
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1494 0x410B758
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1495 0x410B75C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1496 0x410B760
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1497 0x410B764
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1498 0x410B768
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1499 0x410B76C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1500 0x410B770
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1501 0x410B774
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1502 0x410B778
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1503 0x410B77C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1504 0x410B780
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1505 0x410B784
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1506 0x410B788
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1507 0x410B78C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1508 0x410B790
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1509 0x410B794
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1510 0x410B798
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1511 0x410B79C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1512 0x410B7A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1513 0x410B7A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1514 0x410B7A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1515 0x410B7AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1516 0x410B7B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1517 0x410B7B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1518 0x410B7B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1519 0x410B7BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1520 0x410B7C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1521 0x410B7C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1522 0x410B7C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1523 0x410B7CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1524 0x410B7D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1525 0x410B7D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1526 0x410B7D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1527 0x410B7DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1528 0x410B7E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1529 0x410B7E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1530 0x410B7E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1531 0x410B7EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1532 0x410B7F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1533 0x410B7F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1534 0x410B7F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1535 0x410B7FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1536 0x410B800
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1537 0x410B804
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1538 0x410B808
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1539 0x410B80C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1540 0x410B810
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1541 0x410B814
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1542 0x410B818
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1543 0x410B81C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1544 0x410B820
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1545 0x410B824
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1546 0x410B828
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1547 0x410B82C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1548 0x410B830
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1549 0x410B834
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1550 0x410B838
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1551 0x410B83C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1552 0x410B840
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1553 0x410B844
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1554 0x410B848
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1555 0x410B84C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1556 0x410B850
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1557 0x410B854
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1558 0x410B858
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1559 0x410B85C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1560 0x410B860
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1561 0x410B864
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1562 0x410B868
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1563 0x410B86C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1564 0x410B870
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1565 0x410B874
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1566 0x410B878
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1567 0x410B87C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1568 0x410B880
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1569 0x410B884
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1570 0x410B888
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1571 0x410B88C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1572 0x410B890
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1573 0x410B894
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1574 0x410B898
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1575 0x410B89C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1576 0x410B8A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1577 0x410B8A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1578 0x410B8A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1579 0x410B8AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1580 0x410B8B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1581 0x410B8B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1582 0x410B8B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1583 0x410B8BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1584 0x410B8C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1585 0x410B8C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1586 0x410B8C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1587 0x410B8CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1588 0x410B8D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1589 0x410B8D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1590 0x410B8D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1591 0x410B8DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1592 0x410B8E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1593 0x410B8E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1594 0x410B8E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1595 0x410B8EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1596 0x410B8F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1597 0x410B8F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1598 0x410B8F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1599 0x410B8FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1600 0x410B900
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1601 0x410B904
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1602 0x410B908
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1603 0x410B90C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1604 0x410B910
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1605 0x410B914
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1606 0x410B918
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1607 0x410B91C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1608 0x410B920
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1609 0x410B924
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1610 0x410B928
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1611 0x410B92C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1612 0x410B930
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1613 0x410B934
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1614 0x410B938
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1615 0x410B93C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1616 0x410B940
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1617 0x410B944
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1618 0x410B948
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1619 0x410B94C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1620 0x410B950
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1621 0x410B954
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1622 0x410B958
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1623 0x410B95C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1624 0x410B960
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1625 0x410B964
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1626 0x410B968
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1627 0x410B96C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1628 0x410B970
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1629 0x410B974
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1630 0x410B978
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1631 0x410B97C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1632 0x410B980
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1633 0x410B984
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1634 0x410B988
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1635 0x410B98C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1636 0x410B990
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1637 0x410B994
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1638 0x410B998
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1639 0x410B99C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1640 0x410B9A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1641 0x410B9A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1642 0x410B9A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1643 0x410B9AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1644 0x410B9B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1645 0x410B9B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1646 0x410B9B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1647 0x410B9BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1648 0x410B9C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1649 0x410B9C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1650 0x410B9C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1651 0x410B9CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1652 0x410B9D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1653 0x410B9D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1654 0x410B9D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1655 0x410B9DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1656 0x410B9E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1657 0x410B9E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1658 0x410B9E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1659 0x410B9EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1660 0x410B9F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1661 0x410B9F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1662 0x410B9F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1663 0x410B9FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1664 0x410BA00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1665 0x410BA04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1666 0x410BA08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1667 0x410BA0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1668 0x410BA10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1669 0x410BA14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1670 0x410BA18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1671 0x410BA1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1672 0x410BA20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1673 0x410BA24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1674 0x410BA28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1675 0x410BA2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1676 0x410BA30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1677 0x410BA34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1678 0x410BA38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1679 0x410BA3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1680 0x410BA40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1681 0x410BA44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1682 0x410BA48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1683 0x410BA4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1684 0x410BA50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1685 0x410BA54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1686 0x410BA58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1687 0x410BA5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1688 0x410BA60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1689 0x410BA64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1690 0x410BA68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1691 0x410BA6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1692 0x410BA70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1693 0x410BA74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1694 0x410BA78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1695 0x410BA7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1696 0x410BA80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1697 0x410BA84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1698 0x410BA88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1699 0x410BA8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1700 0x410BA90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1701 0x410BA94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1702 0x410BA98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1703 0x410BA9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1704 0x410BAA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1705 0x410BAA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1706 0x410BAA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1707 0x410BAAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1708 0x410BAB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1709 0x410BAB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1710 0x410BAB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1711 0x410BABC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1712 0x410BAC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1713 0x410BAC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1714 0x410BAC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1715 0x410BACC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1716 0x410BAD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1717 0x410BAD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1718 0x410BAD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1719 0x410BADC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1720 0x410BAE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1721 0x410BAE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1722 0x410BAE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1723 0x410BAEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1724 0x410BAF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1725 0x410BAF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1726 0x410BAF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1727 0x410BAFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1728 0x410BB00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1729 0x410BB04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1730 0x410BB08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1731 0x410BB0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1732 0x410BB10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1733 0x410BB14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1734 0x410BB18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1735 0x410BB1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1736 0x410BB20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1737 0x410BB24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1738 0x410BB28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1739 0x410BB2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1740 0x410BB30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1741 0x410BB34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1742 0x410BB38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1743 0x410BB3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1744 0x410BB40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1745 0x410BB44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1746 0x410BB48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1747 0x410BB4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1748 0x410BB50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1749 0x410BB54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1750 0x410BB58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1751 0x410BB5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1752 0x410BB60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1753 0x410BB64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1754 0x410BB68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1755 0x410BB6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1756 0x410BB70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1757 0x410BB74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1758 0x410BB78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1759 0x410BB7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1760 0x410BB80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1761 0x410BB84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1762 0x410BB88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1763 0x410BB8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1764 0x410BB90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1765 0x410BB94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1766 0x410BB98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1767 0x410BB9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1768 0x410BBA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1769 0x410BBA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1770 0x410BBA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1771 0x410BBAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1772 0x410BBB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1773 0x410BBB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1774 0x410BBB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1775 0x410BBBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1776 0x410BBC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1777 0x410BBC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1778 0x410BBC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1779 0x410BBCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1780 0x410BBD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1781 0x410BBD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1782 0x410BBD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1783 0x410BBDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1784 0x410BBE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1785 0x410BBE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1786 0x410BBE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1787 0x410BBEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1788 0x410BBF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1789 0x410BBF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1790 0x410BBF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1791 0x410BBFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1792 0x410BC00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1793 0x410BC04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1794 0x410BC08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1795 0x410BC0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1796 0x410BC10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1797 0x410BC14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1798 0x410BC18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1799 0x410BC1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1800 0x410BC20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1801 0x410BC24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1802 0x410BC28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1803 0x410BC2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1804 0x410BC30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1805 0x410BC34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1806 0x410BC38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1807 0x410BC3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1808 0x410BC40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1809 0x410BC44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1810 0x410BC48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1811 0x410BC4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1812 0x410BC50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1813 0x410BC54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1814 0x410BC58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1815 0x410BC5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1816 0x410BC60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1817 0x410BC64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1818 0x410BC68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1819 0x410BC6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1820 0x410BC70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1821 0x410BC74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1822 0x410BC78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1823 0x410BC7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1824 0x410BC80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1825 0x410BC84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1826 0x410BC88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1827 0x410BC8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1828 0x410BC90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1829 0x410BC94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1830 0x410BC98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1831 0x410BC9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1832 0x410BCA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1833 0x410BCA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1834 0x410BCA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1835 0x410BCAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1836 0x410BCB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1837 0x410BCB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1838 0x410BCB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1839 0x410BCBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1840 0x410BCC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1841 0x410BCC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1842 0x410BCC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1843 0x410BCCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1844 0x410BCD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1845 0x410BCD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1846 0x410BCD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1847 0x410BCDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1848 0x410BCE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1849 0x410BCE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1850 0x410BCE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1851 0x410BCEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1852 0x410BCF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1853 0x410BCF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1854 0x410BCF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1855 0x410BCFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1856 0x410BD00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1857 0x410BD04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1858 0x410BD08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1859 0x410BD0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1860 0x410BD10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1861 0x410BD14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1862 0x410BD18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1863 0x410BD1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1864 0x410BD20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1865 0x410BD24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1866 0x410BD28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1867 0x410BD2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1868 0x410BD30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1869 0x410BD34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1870 0x410BD38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1871 0x410BD3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1872 0x410BD40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1873 0x410BD44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1874 0x410BD48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1875 0x410BD4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1876 0x410BD50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1877 0x410BD54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1878 0x410BD58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1879 0x410BD5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1880 0x410BD60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1881 0x410BD64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1882 0x410BD68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1883 0x410BD6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1884 0x410BD70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1885 0x410BD74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1886 0x410BD78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1887 0x410BD7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1888 0x410BD80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1889 0x410BD84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1890 0x410BD88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1891 0x410BD8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1892 0x410BD90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1893 0x410BD94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1894 0x410BD98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1895 0x410BD9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1896 0x410BDA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1897 0x410BDA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1898 0x410BDA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1899 0x410BDAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1900 0x410BDB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1901 0x410BDB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1902 0x410BDB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1903 0x410BDBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1904 0x410BDC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1905 0x410BDC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1906 0x410BDC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1907 0x410BDCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1908 0x410BDD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1909 0x410BDD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1910 0x410BDD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1911 0x410BDDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1912 0x410BDE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1913 0x410BDE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1914 0x410BDE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1915 0x410BDEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1916 0x410BDF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1917 0x410BDF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1918 0x410BDF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1919 0x410BDFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1920 0x410BE00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1921 0x410BE04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1922 0x410BE08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1923 0x410BE0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1924 0x410BE10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1925 0x410BE14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1926 0x410BE18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1927 0x410BE1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1928 0x410BE20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1929 0x410BE24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1930 0x410BE28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1931 0x410BE2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1932 0x410BE30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1933 0x410BE34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1934 0x410BE38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1935 0x410BE3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1936 0x410BE40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1937 0x410BE44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1938 0x410BE48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1939 0x410BE4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1940 0x410BE50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1941 0x410BE54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1942 0x410BE58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1943 0x410BE5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1944 0x410BE60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1945 0x410BE64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1946 0x410BE68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1947 0x410BE6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1948 0x410BE70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1949 0x410BE74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1950 0x410BE78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1951 0x410BE7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1952 0x410BE80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1953 0x410BE84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1954 0x410BE88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1955 0x410BE8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1956 0x410BE90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1957 0x410BE94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1958 0x410BE98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1959 0x410BE9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1960 0x410BEA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1961 0x410BEA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1962 0x410BEA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1963 0x410BEAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1964 0x410BEB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1965 0x410BEB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1966 0x410BEB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1967 0x410BEBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1968 0x410BEC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1969 0x410BEC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1970 0x410BEC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1971 0x410BECC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1972 0x410BED0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1973 0x410BED4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1974 0x410BED8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1975 0x410BEDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1976 0x410BEE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1977 0x410BEE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1978 0x410BEE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1979 0x410BEEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1980 0x410BEF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1981 0x410BEF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1982 0x410BEF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1983 0x410BEFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1984 0x410BF00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1985 0x410BF04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1986 0x410BF08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1987 0x410BF0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1988 0x410BF10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1989 0x410BF14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1990 0x410BF18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1991 0x410BF1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1992 0x410BF20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1993 0x410BF24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1994 0x410BF28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1995 0x410BF2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1996 0x410BF30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1997 0x410BF34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1998 0x410BF38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1999 0x410BF3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2000 0x410BF40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2001 0x410BF44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2002 0x410BF48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2003 0x410BF4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2004 0x410BF50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2005 0x410BF54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2006 0x410BF58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2007 0x410BF5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2008 0x410BF60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2009 0x410BF64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2010 0x410BF68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2011 0x410BF6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2012 0x410BF70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2013 0x410BF74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2014 0x410BF78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2015 0x410BF7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2016 0x410BF80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2017 0x410BF84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2018 0x410BF88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2019 0x410BF8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2020 0x410BF90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2021 0x410BF94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2022 0x410BF98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2023 0x410BF9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2024 0x410BFA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2025 0x410BFA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2026 0x410BFA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2027 0x410BFAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2028 0x410BFB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2029 0x410BFB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2030 0x410BFB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2031 0x410BFBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2032 0x410BFC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2033 0x410BFC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2034 0x410BFC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2035 0x410BFCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2036 0x410BFD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2037 0x410BFD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2038 0x410BFD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2039 0x410BFDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2040 0x410BFE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2041 0x410BFE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2042 0x410BFE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2043 0x410BFEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2044 0x410BFF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2045 0x410BFF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2046 0x410BFF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2047 0x410BFFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x410C000
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1 0x410C004
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2 0x410C008
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_3 0x410C00C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_4 0x410C010
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_5 0x410C014
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_6 0x410C018
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_7 0x410C01C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_8 0x410C020
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_9 0x410C024
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_10 0x410C028
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_11 0x410C02C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_12 0x410C030
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_13 0x410C034
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_14 0x410C038
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_15 0x410C03C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_16 0x410C040
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_17 0x410C044
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_18 0x410C048
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_19 0x410C04C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_20 0x410C050
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_21 0x410C054
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_22 0x410C058
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_23 0x410C05C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_24 0x410C060
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_25 0x410C064
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_26 0x410C068
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_27 0x410C06C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_28 0x410C070
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_29 0x410C074
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_30 0x410C078
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_31 0x410C07C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_32 0x410C080
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_33 0x410C084
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_34 0x410C088
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_35 0x410C08C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_36 0x410C090
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_37 0x410C094
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_38 0x410C098
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_39 0x410C09C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_40 0x410C0A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_41 0x410C0A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_42 0x410C0A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_43 0x410C0AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_44 0x410C0B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_45 0x410C0B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_46 0x410C0B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_47 0x410C0BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_48 0x410C0C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_49 0x410C0C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_50 0x410C0C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_51 0x410C0CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_52 0x410C0D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_53 0x410C0D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_54 0x410C0D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_55 0x410C0DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_56 0x410C0E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_57 0x410C0E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_58 0x410C0E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_59 0x410C0EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_60 0x410C0F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_61 0x410C0F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_62 0x410C0F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_63 0x410C0FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_64 0x410C100
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_65 0x410C104
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_66 0x410C108
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_67 0x410C10C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_68 0x410C110
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_69 0x410C114
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_70 0x410C118
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_71 0x410C11C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_72 0x410C120
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_73 0x410C124
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_74 0x410C128
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_75 0x410C12C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_76 0x410C130
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_77 0x410C134
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_78 0x410C138
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_79 0x410C13C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_80 0x410C140
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_81 0x410C144
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_82 0x410C148
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_83 0x410C14C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_84 0x410C150
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_85 0x410C154
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_86 0x410C158
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_87 0x410C15C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_88 0x410C160
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_89 0x410C164
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_90 0x410C168
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_91 0x410C16C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_92 0x410C170
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_93 0x410C174
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_94 0x410C178
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_95 0x410C17C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_96 0x410C180
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_97 0x410C184
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_98 0x410C188
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_99 0x410C18C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_100 0x410C190
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_101 0x410C194
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_102 0x410C198
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_103 0x410C19C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_104 0x410C1A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_105 0x410C1A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_106 0x410C1A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_107 0x410C1AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_108 0x410C1B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_109 0x410C1B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_110 0x410C1B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_111 0x410C1BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_112 0x410C1C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_113 0x410C1C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_114 0x410C1C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_115 0x410C1CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_116 0x410C1D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_117 0x410C1D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_118 0x410C1D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_119 0x410C1DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_120 0x410C1E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_121 0x410C1E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_122 0x410C1E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_123 0x410C1EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_124 0x410C1F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_125 0x410C1F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_126 0x410C1F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_127 0x410C1FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_128 0x410C200
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_129 0x410C204
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_130 0x410C208
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_131 0x410C20C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_132 0x410C210
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_133 0x410C214
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_134 0x410C218
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_135 0x410C21C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_136 0x410C220
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_137 0x410C224
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_138 0x410C228
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_139 0x410C22C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_140 0x410C230
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_141 0x410C234
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_142 0x410C238
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_143 0x410C23C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_144 0x410C240
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_145 0x410C244
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_146 0x410C248
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_147 0x410C24C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_148 0x410C250
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_149 0x410C254
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_150 0x410C258
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_151 0x410C25C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_152 0x410C260
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_153 0x410C264
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_154 0x410C268
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_155 0x410C26C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_156 0x410C270
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_157 0x410C274
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_158 0x410C278
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_159 0x410C27C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_160 0x410C280
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_161 0x410C284
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_162 0x410C288
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_163 0x410C28C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_164 0x410C290
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_165 0x410C294
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_166 0x410C298
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_167 0x410C29C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_168 0x410C2A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_169 0x410C2A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_170 0x410C2A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_171 0x410C2AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_172 0x410C2B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_173 0x410C2B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_174 0x410C2B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_175 0x410C2BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_176 0x410C2C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_177 0x410C2C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_178 0x410C2C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_179 0x410C2CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_180 0x410C2D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_181 0x410C2D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_182 0x410C2D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_183 0x410C2DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_184 0x410C2E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_185 0x410C2E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_186 0x410C2E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_187 0x410C2EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_188 0x410C2F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_189 0x410C2F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_190 0x410C2F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_191 0x410C2FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_192 0x410C300
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_193 0x410C304
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_194 0x410C308
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_195 0x410C30C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_196 0x410C310
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_197 0x410C314
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_198 0x410C318
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_199 0x410C31C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_200 0x410C320
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_201 0x410C324
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_202 0x410C328
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_203 0x410C32C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_204 0x410C330
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_205 0x410C334
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_206 0x410C338
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_207 0x410C33C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_208 0x410C340
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_209 0x410C344
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_210 0x410C348
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_211 0x410C34C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_212 0x410C350
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_213 0x410C354
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_214 0x410C358
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_215 0x410C35C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_216 0x410C360
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_217 0x410C364
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_218 0x410C368
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_219 0x410C36C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_220 0x410C370
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_221 0x410C374
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_222 0x410C378
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_223 0x410C37C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_224 0x410C380
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_225 0x410C384
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_226 0x410C388
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_227 0x410C38C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_228 0x410C390
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_229 0x410C394
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_230 0x410C398
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_231 0x410C39C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_232 0x410C3A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_233 0x410C3A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_234 0x410C3A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_235 0x410C3AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_236 0x410C3B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_237 0x410C3B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_238 0x410C3B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_239 0x410C3BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_240 0x410C3C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_241 0x410C3C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_242 0x410C3C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_243 0x410C3CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_244 0x410C3D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_245 0x410C3D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_246 0x410C3D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_247 0x410C3DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_248 0x410C3E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_249 0x410C3E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_250 0x410C3E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_251 0x410C3EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_252 0x410C3F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_253 0x410C3F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_254 0x410C3F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_255 0x410C3FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_256 0x410C400
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_257 0x410C404
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_258 0x410C408
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_259 0x410C40C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_260 0x410C410
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_261 0x410C414
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_262 0x410C418
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_263 0x410C41C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_264 0x410C420
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_265 0x410C424
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_266 0x410C428
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_267 0x410C42C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_268 0x410C430
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_269 0x410C434
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_270 0x410C438
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_271 0x410C43C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_272 0x410C440
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_273 0x410C444
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_274 0x410C448
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_275 0x410C44C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_276 0x410C450
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_277 0x410C454
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_278 0x410C458
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_279 0x410C45C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_280 0x410C460
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_281 0x410C464
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_282 0x410C468
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_283 0x410C46C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_284 0x410C470
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_285 0x410C474
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_286 0x410C478
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_287 0x410C47C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_288 0x410C480
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_289 0x410C484
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_290 0x410C488
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_291 0x410C48C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_292 0x410C490
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_293 0x410C494
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_294 0x410C498
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_295 0x410C49C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_296 0x410C4A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_297 0x410C4A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_298 0x410C4A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_299 0x410C4AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_300 0x410C4B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_301 0x410C4B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_302 0x410C4B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_303 0x410C4BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_304 0x410C4C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_305 0x410C4C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_306 0x410C4C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_307 0x410C4CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_308 0x410C4D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_309 0x410C4D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_310 0x410C4D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_311 0x410C4DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_312 0x410C4E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_313 0x410C4E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_314 0x410C4E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_315 0x410C4EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_316 0x410C4F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_317 0x410C4F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_318 0x410C4F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_319 0x410C4FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_320 0x410C500
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_321 0x410C504
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_322 0x410C508
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_323 0x410C50C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_324 0x410C510
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_325 0x410C514
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_326 0x410C518
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_327 0x410C51C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_328 0x410C520
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_329 0x410C524
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_330 0x410C528
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_331 0x410C52C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_332 0x410C530
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_333 0x410C534
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_334 0x410C538
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_335 0x410C53C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_336 0x410C540
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_337 0x410C544
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_338 0x410C548
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_339 0x410C54C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_340 0x410C550
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_341 0x410C554
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_342 0x410C558
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_343 0x410C55C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_344 0x410C560
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_345 0x410C564
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_346 0x410C568
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_347 0x410C56C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_348 0x410C570
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_349 0x410C574
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_350 0x410C578
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_351 0x410C57C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_352 0x410C580
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_353 0x410C584
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_354 0x410C588
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_355 0x410C58C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_356 0x410C590
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_357 0x410C594
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_358 0x410C598
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_359 0x410C59C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_360 0x410C5A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_361 0x410C5A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_362 0x410C5A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_363 0x410C5AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_364 0x410C5B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_365 0x410C5B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_366 0x410C5B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_367 0x410C5BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_368 0x410C5C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_369 0x410C5C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_370 0x410C5C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_371 0x410C5CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_372 0x410C5D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_373 0x410C5D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_374 0x410C5D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_375 0x410C5DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_376 0x410C5E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_377 0x410C5E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_378 0x410C5E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_379 0x410C5EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_380 0x410C5F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_381 0x410C5F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_382 0x410C5F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_383 0x410C5FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_384 0x410C600
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_385 0x410C604
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_386 0x410C608
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_387 0x410C60C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_388 0x410C610
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_389 0x410C614
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_390 0x410C618
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_391 0x410C61C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_392 0x410C620
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_393 0x410C624
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_394 0x410C628
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_395 0x410C62C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_396 0x410C630
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_397 0x410C634
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_398 0x410C638
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_399 0x410C63C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_400 0x410C640
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_401 0x410C644
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_402 0x410C648
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_403 0x410C64C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_404 0x410C650
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_405 0x410C654
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_406 0x410C658
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_407 0x410C65C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_408 0x410C660
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_409 0x410C664
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_410 0x410C668
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_411 0x410C66C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_412 0x410C670
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_413 0x410C674
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_414 0x410C678
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_415 0x410C67C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_416 0x410C680
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_417 0x410C684
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_418 0x410C688
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_419 0x410C68C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_420 0x410C690
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_421 0x410C694
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_422 0x410C698
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_423 0x410C69C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_424 0x410C6A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_425 0x410C6A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_426 0x410C6A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_427 0x410C6AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_428 0x410C6B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_429 0x410C6B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_430 0x410C6B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_431 0x410C6BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_432 0x410C6C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_433 0x410C6C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_434 0x410C6C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_435 0x410C6CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_436 0x410C6D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_437 0x410C6D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_438 0x410C6D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_439 0x410C6DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_440 0x410C6E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_441 0x410C6E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_442 0x410C6E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_443 0x410C6EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_444 0x410C6F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_445 0x410C6F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_446 0x410C6F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_447 0x410C6FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_448 0x410C700
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_449 0x410C704
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_450 0x410C708
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_451 0x410C70C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_452 0x410C710
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_453 0x410C714
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_454 0x410C718
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_455 0x410C71C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_456 0x410C720
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_457 0x410C724
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_458 0x410C728
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_459 0x410C72C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_460 0x410C730
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_461 0x410C734
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_462 0x410C738
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_463 0x410C73C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_464 0x410C740
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_465 0x410C744
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_466 0x410C748
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_467 0x410C74C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_468 0x410C750
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_469 0x410C754
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_470 0x410C758
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_471 0x410C75C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_472 0x410C760
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_473 0x410C764
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_474 0x410C768
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_475 0x410C76C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_476 0x410C770
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_477 0x410C774
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_478 0x410C778
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_479 0x410C77C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_480 0x410C780
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_481 0x410C784
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_482 0x410C788
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_483 0x410C78C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_484 0x410C790
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_485 0x410C794
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_486 0x410C798
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_487 0x410C79C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_488 0x410C7A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_489 0x410C7A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_490 0x410C7A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_491 0x410C7AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_492 0x410C7B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_493 0x410C7B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_494 0x410C7B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_495 0x410C7BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_496 0x410C7C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_497 0x410C7C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_498 0x410C7C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_499 0x410C7CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_500 0x410C7D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_501 0x410C7D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_502 0x410C7D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_503 0x410C7DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_504 0x410C7E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_505 0x410C7E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_506 0x410C7E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_507 0x410C7EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_508 0x410C7F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_509 0x410C7F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_510 0x410C7F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_511 0x410C7FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_512 0x410C800
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_513 0x410C804
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_514 0x410C808
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_515 0x410C80C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_516 0x410C810
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_517 0x410C814
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_518 0x410C818
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_519 0x410C81C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_520 0x410C820
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_521 0x410C824
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_522 0x410C828
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_523 0x410C82C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_524 0x410C830
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_525 0x410C834
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_526 0x410C838
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_527 0x410C83C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_528 0x410C840
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_529 0x410C844
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_530 0x410C848
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_531 0x410C84C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_532 0x410C850
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_533 0x410C854
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_534 0x410C858
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_535 0x410C85C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_536 0x410C860
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_537 0x410C864
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_538 0x410C868
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_539 0x410C86C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_540 0x410C870
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_541 0x410C874
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_542 0x410C878
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_543 0x410C87C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_544 0x410C880
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_545 0x410C884
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_546 0x410C888
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_547 0x410C88C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_548 0x410C890
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_549 0x410C894
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_550 0x410C898
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_551 0x410C89C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_552 0x410C8A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_553 0x410C8A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_554 0x410C8A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_555 0x410C8AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_556 0x410C8B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_557 0x410C8B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_558 0x410C8B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_559 0x410C8BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_560 0x410C8C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_561 0x410C8C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_562 0x410C8C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_563 0x410C8CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_564 0x410C8D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_565 0x410C8D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_566 0x410C8D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_567 0x410C8DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_568 0x410C8E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_569 0x410C8E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_570 0x410C8E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_571 0x410C8EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_572 0x410C8F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_573 0x410C8F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_574 0x410C8F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_575 0x410C8FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_576 0x410C900
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_577 0x410C904
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_578 0x410C908
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_579 0x410C90C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_580 0x410C910
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_581 0x410C914
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_582 0x410C918
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_583 0x410C91C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_584 0x410C920
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_585 0x410C924
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_586 0x410C928
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_587 0x410C92C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_588 0x410C930
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_589 0x410C934
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_590 0x410C938
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_591 0x410C93C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_592 0x410C940
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_593 0x410C944
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_594 0x410C948
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_595 0x410C94C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_596 0x410C950
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_597 0x410C954
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_598 0x410C958
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_599 0x410C95C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_600 0x410C960
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_601 0x410C964
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_602 0x410C968
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_603 0x410C96C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_604 0x410C970
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_605 0x410C974
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_606 0x410C978
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_607 0x410C97C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_608 0x410C980
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_609 0x410C984
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_610 0x410C988
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_611 0x410C98C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_612 0x410C990
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_613 0x410C994
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_614 0x410C998
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_615 0x410C99C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_616 0x410C9A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_617 0x410C9A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_618 0x410C9A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_619 0x410C9AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_620 0x410C9B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_621 0x410C9B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_622 0x410C9B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_623 0x410C9BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_624 0x410C9C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_625 0x410C9C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_626 0x410C9C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_627 0x410C9CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_628 0x410C9D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_629 0x410C9D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_630 0x410C9D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_631 0x410C9DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_632 0x410C9E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_633 0x410C9E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_634 0x410C9E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_635 0x410C9EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_636 0x410C9F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_637 0x410C9F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_638 0x410C9F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_639 0x410C9FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_640 0x410CA00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_641 0x410CA04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_642 0x410CA08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_643 0x410CA0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_644 0x410CA10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_645 0x410CA14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_646 0x410CA18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_647 0x410CA1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_648 0x410CA20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_649 0x410CA24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_650 0x410CA28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_651 0x410CA2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_652 0x410CA30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_653 0x410CA34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_654 0x410CA38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_655 0x410CA3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_656 0x410CA40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_657 0x410CA44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_658 0x410CA48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_659 0x410CA4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_660 0x410CA50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_661 0x410CA54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_662 0x410CA58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_663 0x410CA5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_664 0x410CA60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_665 0x410CA64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_666 0x410CA68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_667 0x410CA6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_668 0x410CA70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_669 0x410CA74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_670 0x410CA78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_671 0x410CA7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_672 0x410CA80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_673 0x410CA84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_674 0x410CA88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_675 0x410CA8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_676 0x410CA90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_677 0x410CA94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_678 0x410CA98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_679 0x410CA9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_680 0x410CAA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_681 0x410CAA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_682 0x410CAA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_683 0x410CAAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_684 0x410CAB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_685 0x410CAB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_686 0x410CAB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_687 0x410CABC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_688 0x410CAC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_689 0x410CAC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_690 0x410CAC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_691 0x410CACC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_692 0x410CAD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_693 0x410CAD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_694 0x410CAD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_695 0x410CADC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_696 0x410CAE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_697 0x410CAE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_698 0x410CAE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_699 0x410CAEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_700 0x410CAF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_701 0x410CAF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_702 0x410CAF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_703 0x410CAFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_704 0x410CB00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_705 0x410CB04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_706 0x410CB08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_707 0x410CB0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_708 0x410CB10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_709 0x410CB14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_710 0x410CB18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_711 0x410CB1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_712 0x410CB20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_713 0x410CB24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_714 0x410CB28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_715 0x410CB2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_716 0x410CB30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_717 0x410CB34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_718 0x410CB38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_719 0x410CB3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_720 0x410CB40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_721 0x410CB44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_722 0x410CB48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_723 0x410CB4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_724 0x410CB50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_725 0x410CB54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_726 0x410CB58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_727 0x410CB5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_728 0x410CB60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_729 0x410CB64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_730 0x410CB68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_731 0x410CB6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_732 0x410CB70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_733 0x410CB74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_734 0x410CB78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_735 0x410CB7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_736 0x410CB80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_737 0x410CB84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_738 0x410CB88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_739 0x410CB8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_740 0x410CB90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_741 0x410CB94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_742 0x410CB98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_743 0x410CB9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_744 0x410CBA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_745 0x410CBA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_746 0x410CBA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_747 0x410CBAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_748 0x410CBB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_749 0x410CBB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_750 0x410CBB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_751 0x410CBBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_752 0x410CBC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_753 0x410CBC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_754 0x410CBC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_755 0x410CBCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_756 0x410CBD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_757 0x410CBD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_758 0x410CBD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_759 0x410CBDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_760 0x410CBE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_761 0x410CBE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_762 0x410CBE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_763 0x410CBEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_764 0x410CBF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_765 0x410CBF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_766 0x410CBF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_767 0x410CBFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_768 0x410CC00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_769 0x410CC04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_770 0x410CC08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_771 0x410CC0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_772 0x410CC10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_773 0x410CC14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_774 0x410CC18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_775 0x410CC1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_776 0x410CC20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_777 0x410CC24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_778 0x410CC28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_779 0x410CC2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_780 0x410CC30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_781 0x410CC34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_782 0x410CC38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_783 0x410CC3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_784 0x410CC40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_785 0x410CC44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_786 0x410CC48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_787 0x410CC4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_788 0x410CC50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_789 0x410CC54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_790 0x410CC58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_791 0x410CC5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_792 0x410CC60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_793 0x410CC64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_794 0x410CC68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_795 0x410CC6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_796 0x410CC70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_797 0x410CC74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_798 0x410CC78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_799 0x410CC7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_800 0x410CC80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_801 0x410CC84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_802 0x410CC88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_803 0x410CC8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_804 0x410CC90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_805 0x410CC94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_806 0x410CC98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_807 0x410CC9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_808 0x410CCA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_809 0x410CCA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_810 0x410CCA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_811 0x410CCAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_812 0x410CCB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_813 0x410CCB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_814 0x410CCB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_815 0x410CCBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_816 0x410CCC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_817 0x410CCC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_818 0x410CCC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_819 0x410CCCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_820 0x410CCD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_821 0x410CCD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_822 0x410CCD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_823 0x410CCDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_824 0x410CCE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_825 0x410CCE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_826 0x410CCE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_827 0x410CCEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_828 0x410CCF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_829 0x410CCF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_830 0x410CCF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_831 0x410CCFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_832 0x410CD00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_833 0x410CD04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_834 0x410CD08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_835 0x410CD0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_836 0x410CD10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_837 0x410CD14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_838 0x410CD18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_839 0x410CD1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_840 0x410CD20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_841 0x410CD24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_842 0x410CD28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_843 0x410CD2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_844 0x410CD30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_845 0x410CD34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_846 0x410CD38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_847 0x410CD3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_848 0x410CD40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_849 0x410CD44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_850 0x410CD48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_851 0x410CD4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_852 0x410CD50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_853 0x410CD54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_854 0x410CD58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_855 0x410CD5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_856 0x410CD60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_857 0x410CD64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_858 0x410CD68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_859 0x410CD6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_860 0x410CD70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_861 0x410CD74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_862 0x410CD78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_863 0x410CD7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_864 0x410CD80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_865 0x410CD84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_866 0x410CD88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_867 0x410CD8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_868 0x410CD90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_869 0x410CD94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_870 0x410CD98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_871 0x410CD9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_872 0x410CDA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_873 0x410CDA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_874 0x410CDA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_875 0x410CDAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_876 0x410CDB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_877 0x410CDB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_878 0x410CDB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_879 0x410CDBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_880 0x410CDC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_881 0x410CDC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_882 0x410CDC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_883 0x410CDCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_884 0x410CDD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_885 0x410CDD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_886 0x410CDD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_887 0x410CDDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_888 0x410CDE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_889 0x410CDE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_890 0x410CDE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_891 0x410CDEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_892 0x410CDF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_893 0x410CDF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_894 0x410CDF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_895 0x410CDFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_896 0x410CE00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_897 0x410CE04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_898 0x410CE08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_899 0x410CE0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_900 0x410CE10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_901 0x410CE14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_902 0x410CE18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_903 0x410CE1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_904 0x410CE20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_905 0x410CE24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_906 0x410CE28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_907 0x410CE2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_908 0x410CE30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_909 0x410CE34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_910 0x410CE38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_911 0x410CE3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_912 0x410CE40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_913 0x410CE44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_914 0x410CE48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_915 0x410CE4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_916 0x410CE50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_917 0x410CE54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_918 0x410CE58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_919 0x410CE5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_920 0x410CE60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_921 0x410CE64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_922 0x410CE68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_923 0x410CE6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_924 0x410CE70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_925 0x410CE74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_926 0x410CE78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_927 0x410CE7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_928 0x410CE80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_929 0x410CE84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_930 0x410CE88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_931 0x410CE8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_932 0x410CE90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_933 0x410CE94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_934 0x410CE98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_935 0x410CE9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_936 0x410CEA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_937 0x410CEA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_938 0x410CEA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_939 0x410CEAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_940 0x410CEB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_941 0x410CEB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_942 0x410CEB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_943 0x410CEBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_944 0x410CEC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_945 0x410CEC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_946 0x410CEC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_947 0x410CECC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_948 0x410CED0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_949 0x410CED4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_950 0x410CED8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_951 0x410CEDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_952 0x410CEE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_953 0x410CEE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_954 0x410CEE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_955 0x410CEEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_956 0x410CEF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_957 0x410CEF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_958 0x410CEF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_959 0x410CEFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_960 0x410CF00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_961 0x410CF04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_962 0x410CF08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_963 0x410CF0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_964 0x410CF10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_965 0x410CF14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_966 0x410CF18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_967 0x410CF1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_968 0x410CF20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_969 0x410CF24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_970 0x410CF28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_971 0x410CF2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_972 0x410CF30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_973 0x410CF34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_974 0x410CF38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_975 0x410CF3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_976 0x410CF40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_977 0x410CF44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_978 0x410CF48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_979 0x410CF4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_980 0x410CF50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_981 0x410CF54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_982 0x410CF58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_983 0x410CF5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_984 0x410CF60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_985 0x410CF64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_986 0x410CF68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_987 0x410CF6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_988 0x410CF70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_989 0x410CF74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_990 0x410CF78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_991 0x410CF7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_992 0x410CF80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_993 0x410CF84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_994 0x410CF88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_995 0x410CF8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_996 0x410CF90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_997 0x410CF94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_998 0x410CF98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_999 0x410CF9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1000 0x410CFA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1001 0x410CFA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1002 0x410CFA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1003 0x410CFAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1004 0x410CFB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1005 0x410CFB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1006 0x410CFB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1007 0x410CFBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1008 0x410CFC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1009 0x410CFC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1010 0x410CFC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1011 0x410CFCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1012 0x410CFD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1013 0x410CFD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1014 0x410CFD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1015 0x410CFDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1016 0x410CFE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1017 0x410CFE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1018 0x410CFE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1019 0x410CFEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1020 0x410CFF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1021 0x410CFF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1022 0x410CFF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1023 0x410CFFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1024 0x410D000
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1025 0x410D004
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1026 0x410D008
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1027 0x410D00C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1028 0x410D010
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1029 0x410D014
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1030 0x410D018
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1031 0x410D01C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1032 0x410D020
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1033 0x410D024
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1034 0x410D028
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1035 0x410D02C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1036 0x410D030
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1037 0x410D034
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1038 0x410D038
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1039 0x410D03C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1040 0x410D040
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1041 0x410D044
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1042 0x410D048
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1043 0x410D04C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1044 0x410D050
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1045 0x410D054
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1046 0x410D058
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1047 0x410D05C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1048 0x410D060
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1049 0x410D064
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1050 0x410D068
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1051 0x410D06C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1052 0x410D070
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1053 0x410D074
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1054 0x410D078
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1055 0x410D07C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1056 0x410D080
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1057 0x410D084
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1058 0x410D088
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1059 0x410D08C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1060 0x410D090
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1061 0x410D094
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1062 0x410D098
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1063 0x410D09C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1064 0x410D0A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1065 0x410D0A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1066 0x410D0A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1067 0x410D0AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1068 0x410D0B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1069 0x410D0B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1070 0x410D0B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1071 0x410D0BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1072 0x410D0C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1073 0x410D0C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1074 0x410D0C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1075 0x410D0CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1076 0x410D0D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1077 0x410D0D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1078 0x410D0D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1079 0x410D0DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1080 0x410D0E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1081 0x410D0E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1082 0x410D0E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1083 0x410D0EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1084 0x410D0F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1085 0x410D0F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1086 0x410D0F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1087 0x410D0FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1088 0x410D100
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1089 0x410D104
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1090 0x410D108
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1091 0x410D10C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1092 0x410D110
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1093 0x410D114
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1094 0x410D118
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1095 0x410D11C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1096 0x410D120
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1097 0x410D124
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1098 0x410D128
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1099 0x410D12C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1100 0x410D130
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1101 0x410D134
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1102 0x410D138
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1103 0x410D13C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1104 0x410D140
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1105 0x410D144
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1106 0x410D148
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1107 0x410D14C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1108 0x410D150
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1109 0x410D154
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1110 0x410D158
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1111 0x410D15C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1112 0x410D160
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1113 0x410D164
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1114 0x410D168
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1115 0x410D16C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1116 0x410D170
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1117 0x410D174
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1118 0x410D178
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1119 0x410D17C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1120 0x410D180
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1121 0x410D184
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1122 0x410D188
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1123 0x410D18C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1124 0x410D190
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1125 0x410D194
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1126 0x410D198
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1127 0x410D19C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1128 0x410D1A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1129 0x410D1A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1130 0x410D1A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1131 0x410D1AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1132 0x410D1B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1133 0x410D1B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1134 0x410D1B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1135 0x410D1BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1136 0x410D1C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1137 0x410D1C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1138 0x410D1C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1139 0x410D1CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1140 0x410D1D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1141 0x410D1D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1142 0x410D1D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1143 0x410D1DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1144 0x410D1E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1145 0x410D1E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1146 0x410D1E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1147 0x410D1EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1148 0x410D1F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1149 0x410D1F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1150 0x410D1F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1151 0x410D1FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1152 0x410D200
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1153 0x410D204
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1154 0x410D208
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1155 0x410D20C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1156 0x410D210
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1157 0x410D214
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1158 0x410D218
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1159 0x410D21C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1160 0x410D220
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1161 0x410D224
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1162 0x410D228
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1163 0x410D22C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1164 0x410D230
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1165 0x410D234
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1166 0x410D238
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1167 0x410D23C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1168 0x410D240
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1169 0x410D244
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1170 0x410D248
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1171 0x410D24C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1172 0x410D250
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1173 0x410D254
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1174 0x410D258
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1175 0x410D25C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1176 0x410D260
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1177 0x410D264
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1178 0x410D268
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1179 0x410D26C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1180 0x410D270
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1181 0x410D274
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1182 0x410D278
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1183 0x410D27C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1184 0x410D280
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1185 0x410D284
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1186 0x410D288
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1187 0x410D28C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1188 0x410D290
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1189 0x410D294
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1190 0x410D298
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1191 0x410D29C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1192 0x410D2A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1193 0x410D2A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1194 0x410D2A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1195 0x410D2AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1196 0x410D2B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1197 0x410D2B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1198 0x410D2B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1199 0x410D2BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1200 0x410D2C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1201 0x410D2C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1202 0x410D2C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1203 0x410D2CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1204 0x410D2D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1205 0x410D2D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1206 0x410D2D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1207 0x410D2DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1208 0x410D2E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1209 0x410D2E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1210 0x410D2E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1211 0x410D2EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1212 0x410D2F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1213 0x410D2F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1214 0x410D2F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1215 0x410D2FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1216 0x410D300
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1217 0x410D304
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1218 0x410D308
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1219 0x410D30C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1220 0x410D310
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1221 0x410D314
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1222 0x410D318
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1223 0x410D31C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1224 0x410D320
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1225 0x410D324
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1226 0x410D328
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1227 0x410D32C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1228 0x410D330
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1229 0x410D334
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1230 0x410D338
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1231 0x410D33C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1232 0x410D340
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1233 0x410D344
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1234 0x410D348
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1235 0x410D34C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1236 0x410D350
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1237 0x410D354
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1238 0x410D358
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1239 0x410D35C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1240 0x410D360
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1241 0x410D364
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1242 0x410D368
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1243 0x410D36C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1244 0x410D370
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1245 0x410D374
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1246 0x410D378
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1247 0x410D37C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1248 0x410D380
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1249 0x410D384
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1250 0x410D388
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1251 0x410D38C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1252 0x410D390
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1253 0x410D394
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1254 0x410D398
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1255 0x410D39C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1256 0x410D3A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1257 0x410D3A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1258 0x410D3A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1259 0x410D3AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1260 0x410D3B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1261 0x410D3B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1262 0x410D3B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1263 0x410D3BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1264 0x410D3C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1265 0x410D3C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1266 0x410D3C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1267 0x410D3CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1268 0x410D3D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1269 0x410D3D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1270 0x410D3D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1271 0x410D3DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1272 0x410D3E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1273 0x410D3E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1274 0x410D3E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1275 0x410D3EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1276 0x410D3F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1277 0x410D3F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1278 0x410D3F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1279 0x410D3FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1280 0x410D400
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1281 0x410D404
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1282 0x410D408
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1283 0x410D40C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1284 0x410D410
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1285 0x410D414
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1286 0x410D418
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1287 0x410D41C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1288 0x410D420
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1289 0x410D424
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1290 0x410D428
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1291 0x410D42C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1292 0x410D430
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1293 0x410D434
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1294 0x410D438
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1295 0x410D43C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1296 0x410D440
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1297 0x410D444
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1298 0x410D448
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1299 0x410D44C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1300 0x410D450
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1301 0x410D454
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1302 0x410D458
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1303 0x410D45C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1304 0x410D460
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1305 0x410D464
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1306 0x410D468
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1307 0x410D46C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1308 0x410D470
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1309 0x410D474
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1310 0x410D478
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1311 0x410D47C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1312 0x410D480
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1313 0x410D484
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1314 0x410D488
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1315 0x410D48C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1316 0x410D490
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1317 0x410D494
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1318 0x410D498
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1319 0x410D49C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1320 0x410D4A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1321 0x410D4A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1322 0x410D4A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1323 0x410D4AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1324 0x410D4B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1325 0x410D4B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1326 0x410D4B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1327 0x410D4BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1328 0x410D4C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1329 0x410D4C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1330 0x410D4C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1331 0x410D4CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1332 0x410D4D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1333 0x410D4D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1334 0x410D4D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1335 0x410D4DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1336 0x410D4E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1337 0x410D4E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1338 0x410D4E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1339 0x410D4EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1340 0x410D4F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1341 0x410D4F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1342 0x410D4F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1343 0x410D4FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1344 0x410D500
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1345 0x410D504
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1346 0x410D508
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1347 0x410D50C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1348 0x410D510
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1349 0x410D514
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1350 0x410D518
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1351 0x410D51C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1352 0x410D520
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1353 0x410D524
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1354 0x410D528
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1355 0x410D52C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1356 0x410D530
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1357 0x410D534
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1358 0x410D538
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1359 0x410D53C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1360 0x410D540
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1361 0x410D544
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1362 0x410D548
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1363 0x410D54C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1364 0x410D550
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1365 0x410D554
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1366 0x410D558
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1367 0x410D55C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1368 0x410D560
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1369 0x410D564
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1370 0x410D568
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1371 0x410D56C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1372 0x410D570
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1373 0x410D574
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1374 0x410D578
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1375 0x410D57C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1376 0x410D580
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1377 0x410D584
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1378 0x410D588
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1379 0x410D58C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1380 0x410D590
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1381 0x410D594
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1382 0x410D598
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1383 0x410D59C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1384 0x410D5A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1385 0x410D5A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1386 0x410D5A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1387 0x410D5AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1388 0x410D5B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1389 0x410D5B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1390 0x410D5B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1391 0x410D5BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1392 0x410D5C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1393 0x410D5C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1394 0x410D5C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1395 0x410D5CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1396 0x410D5D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1397 0x410D5D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1398 0x410D5D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1399 0x410D5DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1400 0x410D5E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1401 0x410D5E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1402 0x410D5E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1403 0x410D5EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1404 0x410D5F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1405 0x410D5F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1406 0x410D5F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1407 0x410D5FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1408 0x410D600
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1409 0x410D604
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1410 0x410D608
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1411 0x410D60C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1412 0x410D610
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1413 0x410D614
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1414 0x410D618
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1415 0x410D61C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1416 0x410D620
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1417 0x410D624
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1418 0x410D628
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1419 0x410D62C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1420 0x410D630
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1421 0x410D634
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1422 0x410D638
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1423 0x410D63C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1424 0x410D640
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1425 0x410D644
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1426 0x410D648
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1427 0x410D64C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1428 0x410D650
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1429 0x410D654
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1430 0x410D658
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1431 0x410D65C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1432 0x410D660
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1433 0x410D664
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1434 0x410D668
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1435 0x410D66C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1436 0x410D670
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1437 0x410D674
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1438 0x410D678
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1439 0x410D67C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1440 0x410D680
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1441 0x410D684
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1442 0x410D688
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1443 0x410D68C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1444 0x410D690
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1445 0x410D694
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1446 0x410D698
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1447 0x410D69C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1448 0x410D6A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1449 0x410D6A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1450 0x410D6A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1451 0x410D6AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1452 0x410D6B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1453 0x410D6B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1454 0x410D6B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1455 0x410D6BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1456 0x410D6C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1457 0x410D6C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1458 0x410D6C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1459 0x410D6CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1460 0x410D6D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1461 0x410D6D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1462 0x410D6D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1463 0x410D6DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1464 0x410D6E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1465 0x410D6E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1466 0x410D6E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1467 0x410D6EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1468 0x410D6F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1469 0x410D6F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1470 0x410D6F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1471 0x410D6FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1472 0x410D700
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1473 0x410D704
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1474 0x410D708
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1475 0x410D70C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1476 0x410D710
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1477 0x410D714
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1478 0x410D718
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1479 0x410D71C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1480 0x410D720
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1481 0x410D724
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1482 0x410D728
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1483 0x410D72C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1484 0x410D730
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1485 0x410D734
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1486 0x410D738
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1487 0x410D73C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1488 0x410D740
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1489 0x410D744
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1490 0x410D748
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1491 0x410D74C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1492 0x410D750
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1493 0x410D754
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1494 0x410D758
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1495 0x410D75C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1496 0x410D760
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1497 0x410D764
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1498 0x410D768
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1499 0x410D76C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1500 0x410D770
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1501 0x410D774
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1502 0x410D778
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1503 0x410D77C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1504 0x410D780
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1505 0x410D784
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1506 0x410D788
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1507 0x410D78C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1508 0x410D790
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1509 0x410D794
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1510 0x410D798
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1511 0x410D79C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1512 0x410D7A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1513 0x410D7A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1514 0x410D7A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1515 0x410D7AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1516 0x410D7B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1517 0x410D7B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1518 0x410D7B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1519 0x410D7BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1520 0x410D7C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1521 0x410D7C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1522 0x410D7C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1523 0x410D7CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1524 0x410D7D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1525 0x410D7D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1526 0x410D7D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1527 0x410D7DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1528 0x410D7E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1529 0x410D7E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1530 0x410D7E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1531 0x410D7EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1532 0x410D7F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1533 0x410D7F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1534 0x410D7F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1535 0x410D7FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1536 0x410D800
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1537 0x410D804
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1538 0x410D808
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1539 0x410D80C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1540 0x410D810
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1541 0x410D814
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1542 0x410D818
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1543 0x410D81C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1544 0x410D820
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1545 0x410D824
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1546 0x410D828
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1547 0x410D82C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1548 0x410D830
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1549 0x410D834
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1550 0x410D838
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1551 0x410D83C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1552 0x410D840
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1553 0x410D844
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1554 0x410D848
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1555 0x410D84C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1556 0x410D850
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1557 0x410D854
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1558 0x410D858
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1559 0x410D85C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1560 0x410D860
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1561 0x410D864
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1562 0x410D868
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1563 0x410D86C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1564 0x410D870
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1565 0x410D874
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1566 0x410D878
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1567 0x410D87C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1568 0x410D880
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1569 0x410D884
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1570 0x410D888
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1571 0x410D88C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1572 0x410D890
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1573 0x410D894
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1574 0x410D898
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1575 0x410D89C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1576 0x410D8A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1577 0x410D8A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1578 0x410D8A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1579 0x410D8AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1580 0x410D8B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1581 0x410D8B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1582 0x410D8B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1583 0x410D8BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1584 0x410D8C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1585 0x410D8C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1586 0x410D8C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1587 0x410D8CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1588 0x410D8D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1589 0x410D8D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1590 0x410D8D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1591 0x410D8DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1592 0x410D8E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1593 0x410D8E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1594 0x410D8E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1595 0x410D8EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1596 0x410D8F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1597 0x410D8F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1598 0x410D8F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1599 0x410D8FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1600 0x410D900
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1601 0x410D904
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1602 0x410D908
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1603 0x410D90C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1604 0x410D910
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1605 0x410D914
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1606 0x410D918
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1607 0x410D91C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1608 0x410D920
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1609 0x410D924
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1610 0x410D928
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1611 0x410D92C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1612 0x410D930
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1613 0x410D934
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1614 0x410D938
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1615 0x410D93C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1616 0x410D940
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1617 0x410D944
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1618 0x410D948
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1619 0x410D94C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1620 0x410D950
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1621 0x410D954
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1622 0x410D958
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1623 0x410D95C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1624 0x410D960
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1625 0x410D964
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1626 0x410D968
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1627 0x410D96C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1628 0x410D970
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1629 0x410D974
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1630 0x410D978
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1631 0x410D97C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1632 0x410D980
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1633 0x410D984
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1634 0x410D988
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1635 0x410D98C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1636 0x410D990
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1637 0x410D994
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1638 0x410D998
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1639 0x410D99C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1640 0x410D9A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1641 0x410D9A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1642 0x410D9A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1643 0x410D9AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1644 0x410D9B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1645 0x410D9B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1646 0x410D9B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1647 0x410D9BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1648 0x410D9C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1649 0x410D9C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1650 0x410D9C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1651 0x410D9CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1652 0x410D9D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1653 0x410D9D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1654 0x410D9D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1655 0x410D9DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1656 0x410D9E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1657 0x410D9E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1658 0x410D9E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1659 0x410D9EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1660 0x410D9F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1661 0x410D9F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1662 0x410D9F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1663 0x410D9FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1664 0x410DA00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1665 0x410DA04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1666 0x410DA08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1667 0x410DA0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1668 0x410DA10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1669 0x410DA14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1670 0x410DA18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1671 0x410DA1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1672 0x410DA20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1673 0x410DA24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1674 0x410DA28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1675 0x410DA2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1676 0x410DA30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1677 0x410DA34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1678 0x410DA38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1679 0x410DA3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1680 0x410DA40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1681 0x410DA44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1682 0x410DA48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1683 0x410DA4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1684 0x410DA50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1685 0x410DA54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1686 0x410DA58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1687 0x410DA5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1688 0x410DA60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1689 0x410DA64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1690 0x410DA68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1691 0x410DA6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1692 0x410DA70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1693 0x410DA74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1694 0x410DA78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1695 0x410DA7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1696 0x410DA80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1697 0x410DA84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1698 0x410DA88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1699 0x410DA8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1700 0x410DA90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1701 0x410DA94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1702 0x410DA98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1703 0x410DA9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1704 0x410DAA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1705 0x410DAA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1706 0x410DAA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1707 0x410DAAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1708 0x410DAB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1709 0x410DAB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1710 0x410DAB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1711 0x410DABC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1712 0x410DAC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1713 0x410DAC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1714 0x410DAC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1715 0x410DACC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1716 0x410DAD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1717 0x410DAD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1718 0x410DAD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1719 0x410DADC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1720 0x410DAE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1721 0x410DAE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1722 0x410DAE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1723 0x410DAEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1724 0x410DAF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1725 0x410DAF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1726 0x410DAF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1727 0x410DAFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1728 0x410DB00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1729 0x410DB04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1730 0x410DB08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1731 0x410DB0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1732 0x410DB10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1733 0x410DB14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1734 0x410DB18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1735 0x410DB1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1736 0x410DB20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1737 0x410DB24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1738 0x410DB28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1739 0x410DB2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1740 0x410DB30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1741 0x410DB34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1742 0x410DB38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1743 0x410DB3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1744 0x410DB40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1745 0x410DB44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1746 0x410DB48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1747 0x410DB4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1748 0x410DB50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1749 0x410DB54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1750 0x410DB58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1751 0x410DB5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1752 0x410DB60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1753 0x410DB64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1754 0x410DB68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1755 0x410DB6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1756 0x410DB70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1757 0x410DB74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1758 0x410DB78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1759 0x410DB7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1760 0x410DB80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1761 0x410DB84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1762 0x410DB88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1763 0x410DB8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1764 0x410DB90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1765 0x410DB94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1766 0x410DB98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1767 0x410DB9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1768 0x410DBA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1769 0x410DBA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1770 0x410DBA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1771 0x410DBAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1772 0x410DBB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1773 0x410DBB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1774 0x410DBB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1775 0x410DBBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1776 0x410DBC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1777 0x410DBC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1778 0x410DBC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1779 0x410DBCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1780 0x410DBD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1781 0x410DBD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1782 0x410DBD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1783 0x410DBDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1784 0x410DBE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1785 0x410DBE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1786 0x410DBE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1787 0x410DBEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1788 0x410DBF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1789 0x410DBF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1790 0x410DBF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1791 0x410DBFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1792 0x410DC00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1793 0x410DC04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1794 0x410DC08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1795 0x410DC0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1796 0x410DC10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1797 0x410DC14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1798 0x410DC18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1799 0x410DC1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1800 0x410DC20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1801 0x410DC24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1802 0x410DC28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1803 0x410DC2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1804 0x410DC30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1805 0x410DC34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1806 0x410DC38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1807 0x410DC3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1808 0x410DC40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1809 0x410DC44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1810 0x410DC48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1811 0x410DC4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1812 0x410DC50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1813 0x410DC54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1814 0x410DC58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1815 0x410DC5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1816 0x410DC60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1817 0x410DC64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1818 0x410DC68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1819 0x410DC6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1820 0x410DC70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1821 0x410DC74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1822 0x410DC78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1823 0x410DC7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1824 0x410DC80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1825 0x410DC84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1826 0x410DC88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1827 0x410DC8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1828 0x410DC90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1829 0x410DC94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1830 0x410DC98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1831 0x410DC9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1832 0x410DCA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1833 0x410DCA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1834 0x410DCA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1835 0x410DCAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1836 0x410DCB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1837 0x410DCB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1838 0x410DCB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1839 0x410DCBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1840 0x410DCC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1841 0x410DCC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1842 0x410DCC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1843 0x410DCCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1844 0x410DCD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1845 0x410DCD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1846 0x410DCD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1847 0x410DCDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1848 0x410DCE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1849 0x410DCE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1850 0x410DCE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1851 0x410DCEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1852 0x410DCF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1853 0x410DCF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1854 0x410DCF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1855 0x410DCFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1856 0x410DD00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1857 0x410DD04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1858 0x410DD08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1859 0x410DD0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1860 0x410DD10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1861 0x410DD14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1862 0x410DD18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1863 0x410DD1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1864 0x410DD20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1865 0x410DD24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1866 0x410DD28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1867 0x410DD2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1868 0x410DD30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1869 0x410DD34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1870 0x410DD38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1871 0x410DD3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1872 0x410DD40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1873 0x410DD44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1874 0x410DD48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1875 0x410DD4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1876 0x410DD50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1877 0x410DD54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1878 0x410DD58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1879 0x410DD5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1880 0x410DD60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1881 0x410DD64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1882 0x410DD68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1883 0x410DD6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1884 0x410DD70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1885 0x410DD74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1886 0x410DD78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1887 0x410DD7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1888 0x410DD80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1889 0x410DD84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1890 0x410DD88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1891 0x410DD8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1892 0x410DD90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1893 0x410DD94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1894 0x410DD98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1895 0x410DD9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1896 0x410DDA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1897 0x410DDA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1898 0x410DDA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1899 0x410DDAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1900 0x410DDB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1901 0x410DDB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1902 0x410DDB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1903 0x410DDBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1904 0x410DDC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1905 0x410DDC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1906 0x410DDC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1907 0x410DDCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1908 0x410DDD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1909 0x410DDD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1910 0x410DDD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1911 0x410DDDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1912 0x410DDE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1913 0x410DDE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1914 0x410DDE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1915 0x410DDEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1916 0x410DDF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1917 0x410DDF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1918 0x410DDF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1919 0x410DDFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1920 0x410DE00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1921 0x410DE04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1922 0x410DE08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1923 0x410DE0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1924 0x410DE10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1925 0x410DE14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1926 0x410DE18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1927 0x410DE1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1928 0x410DE20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1929 0x410DE24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1930 0x410DE28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1931 0x410DE2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1932 0x410DE30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1933 0x410DE34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1934 0x410DE38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1935 0x410DE3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1936 0x410DE40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1937 0x410DE44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1938 0x410DE48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1939 0x410DE4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1940 0x410DE50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1941 0x410DE54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1942 0x410DE58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1943 0x410DE5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1944 0x410DE60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1945 0x410DE64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1946 0x410DE68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1947 0x410DE6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1948 0x410DE70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1949 0x410DE74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1950 0x410DE78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1951 0x410DE7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1952 0x410DE80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1953 0x410DE84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1954 0x410DE88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1955 0x410DE8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1956 0x410DE90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1957 0x410DE94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1958 0x410DE98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1959 0x410DE9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1960 0x410DEA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1961 0x410DEA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1962 0x410DEA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1963 0x410DEAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1964 0x410DEB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1965 0x410DEB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1966 0x410DEB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1967 0x410DEBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1968 0x410DEC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1969 0x410DEC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1970 0x410DEC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1971 0x410DECC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1972 0x410DED0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1973 0x410DED4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1974 0x410DED8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1975 0x410DEDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1976 0x410DEE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1977 0x410DEE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1978 0x410DEE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1979 0x410DEEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1980 0x410DEF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1981 0x410DEF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1982 0x410DEF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1983 0x410DEFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1984 0x410DF00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1985 0x410DF04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1986 0x410DF08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1987 0x410DF0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1988 0x410DF10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1989 0x410DF14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1990 0x410DF18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1991 0x410DF1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1992 0x410DF20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1993 0x410DF24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1994 0x410DF28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1995 0x410DF2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1996 0x410DF30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1997 0x410DF34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1998 0x410DF38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1999 0x410DF3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2000 0x410DF40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2001 0x410DF44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2002 0x410DF48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2003 0x410DF4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2004 0x410DF50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2005 0x410DF54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2006 0x410DF58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2007 0x410DF5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2008 0x410DF60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2009 0x410DF64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2010 0x410DF68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2011 0x410DF6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2012 0x410DF70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2013 0x410DF74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2014 0x410DF78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2015 0x410DF7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2016 0x410DF80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2017 0x410DF84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2018 0x410DF88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2019 0x410DF8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2020 0x410DF90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2021 0x410DF94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2022 0x410DF98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2023 0x410DF9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2024 0x410DFA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2025 0x410DFA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2026 0x410DFA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2027 0x410DFAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2028 0x410DFB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2029 0x410DFB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2030 0x410DFB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2031 0x410DFBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2032 0x410DFC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2033 0x410DFC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2034 0x410DFC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2035 0x410DFCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2036 0x410DFD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2037 0x410DFD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2038 0x410DFD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2039 0x410DFDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2040 0x410DFE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2041 0x410DFE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2042 0x410DFE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2043 0x410DFEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2044 0x410DFF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2045 0x410DFF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2046 0x410DFF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2047 0x410DFFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_0 0x410E000
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1 0x410E004
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2 0x410E008
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_3 0x410E00C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_4 0x410E010
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_5 0x410E014
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_6 0x410E018
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_7 0x410E01C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_8 0x410E020
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_9 0x410E024
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_10 0x410E028
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_11 0x410E02C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_12 0x410E030
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_13 0x410E034
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_14 0x410E038
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_15 0x410E03C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_16 0x410E040
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_17 0x410E044
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_18 0x410E048
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_19 0x410E04C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_20 0x410E050
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_21 0x410E054
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_22 0x410E058
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_23 0x410E05C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_24 0x410E060
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_25 0x410E064
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_26 0x410E068
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_27 0x410E06C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_28 0x410E070
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_29 0x410E074
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_30 0x410E078
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_31 0x410E07C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_32 0x410E080
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_33 0x410E084
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_34 0x410E088
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_35 0x410E08C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_36 0x410E090
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_37 0x410E094
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_38 0x410E098
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_39 0x410E09C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_40 0x410E0A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_41 0x410E0A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_42 0x410E0A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_43 0x410E0AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_44 0x410E0B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_45 0x410E0B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_46 0x410E0B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_47 0x410E0BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_48 0x410E0C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_49 0x410E0C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_50 0x410E0C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_51 0x410E0CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_52 0x410E0D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_53 0x410E0D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_54 0x410E0D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_55 0x410E0DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_56 0x410E0E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_57 0x410E0E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_58 0x410E0E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_59 0x410E0EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_60 0x410E0F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_61 0x410E0F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_62 0x410E0F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_63 0x410E0FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_64 0x410E100
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_65 0x410E104
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_66 0x410E108
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_67 0x410E10C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_68 0x410E110
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_69 0x410E114
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_70 0x410E118
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_71 0x410E11C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_72 0x410E120
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_73 0x410E124
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_74 0x410E128
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_75 0x410E12C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_76 0x410E130
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_77 0x410E134
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_78 0x410E138
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_79 0x410E13C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_80 0x410E140
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_81 0x410E144
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_82 0x410E148
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_83 0x410E14C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_84 0x410E150
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_85 0x410E154
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_86 0x410E158
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_87 0x410E15C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_88 0x410E160
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_89 0x410E164
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_90 0x410E168
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_91 0x410E16C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_92 0x410E170
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_93 0x410E174
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_94 0x410E178
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_95 0x410E17C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_96 0x410E180
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_97 0x410E184
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_98 0x410E188
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_99 0x410E18C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_100 0x410E190
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_101 0x410E194
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_102 0x410E198
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_103 0x410E19C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_104 0x410E1A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_105 0x410E1A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_106 0x410E1A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_107 0x410E1AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_108 0x410E1B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_109 0x410E1B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_110 0x410E1B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_111 0x410E1BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_112 0x410E1C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_113 0x410E1C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_114 0x410E1C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_115 0x410E1CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_116 0x410E1D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_117 0x410E1D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_118 0x410E1D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_119 0x410E1DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_120 0x410E1E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_121 0x410E1E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_122 0x410E1E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_123 0x410E1EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_124 0x410E1F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_125 0x410E1F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_126 0x410E1F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_127 0x410E1FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_128 0x410E200
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_129 0x410E204
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_130 0x410E208
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_131 0x410E20C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_132 0x410E210
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_133 0x410E214
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_134 0x410E218
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_135 0x410E21C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_136 0x410E220
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_137 0x410E224
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_138 0x410E228
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_139 0x410E22C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_140 0x410E230
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_141 0x410E234
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_142 0x410E238
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_143 0x410E23C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_144 0x410E240
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_145 0x410E244
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_146 0x410E248
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_147 0x410E24C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_148 0x410E250
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_149 0x410E254
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_150 0x410E258
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_151 0x410E25C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_152 0x410E260
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_153 0x410E264
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_154 0x410E268
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_155 0x410E26C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_156 0x410E270
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_157 0x410E274
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_158 0x410E278
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_159 0x410E27C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_160 0x410E280
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_161 0x410E284
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_162 0x410E288
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_163 0x410E28C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_164 0x410E290
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_165 0x410E294
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_166 0x410E298
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_167 0x410E29C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_168 0x410E2A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_169 0x410E2A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_170 0x410E2A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_171 0x410E2AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_172 0x410E2B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_173 0x410E2B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_174 0x410E2B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_175 0x410E2BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_176 0x410E2C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_177 0x410E2C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_178 0x410E2C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_179 0x410E2CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_180 0x410E2D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_181 0x410E2D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_182 0x410E2D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_183 0x410E2DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_184 0x410E2E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_185 0x410E2E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_186 0x410E2E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_187 0x410E2EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_188 0x410E2F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_189 0x410E2F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_190 0x410E2F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_191 0x410E2FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_192 0x410E300
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_193 0x410E304
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_194 0x410E308
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_195 0x410E30C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_196 0x410E310
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_197 0x410E314
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_198 0x410E318
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_199 0x410E31C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_200 0x410E320
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_201 0x410E324
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_202 0x410E328
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_203 0x410E32C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_204 0x410E330
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_205 0x410E334
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_206 0x410E338
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_207 0x410E33C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_208 0x410E340
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_209 0x410E344
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_210 0x410E348
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_211 0x410E34C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_212 0x410E350
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_213 0x410E354
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_214 0x410E358
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_215 0x410E35C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_216 0x410E360
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_217 0x410E364
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_218 0x410E368
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_219 0x410E36C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_220 0x410E370
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_221 0x410E374
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_222 0x410E378
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_223 0x410E37C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_224 0x410E380
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_225 0x410E384
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_226 0x410E388
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_227 0x410E38C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_228 0x410E390
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_229 0x410E394
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_230 0x410E398
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_231 0x410E39C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_232 0x410E3A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_233 0x410E3A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_234 0x410E3A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_235 0x410E3AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_236 0x410E3B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_237 0x410E3B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_238 0x410E3B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_239 0x410E3BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_240 0x410E3C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_241 0x410E3C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_242 0x410E3C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_243 0x410E3CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_244 0x410E3D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_245 0x410E3D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_246 0x410E3D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_247 0x410E3DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_248 0x410E3E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_249 0x410E3E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_250 0x410E3E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_251 0x410E3EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_252 0x410E3F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_253 0x410E3F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_254 0x410E3F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_255 0x410E3FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_256 0x410E400
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_257 0x410E404
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_258 0x410E408
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_259 0x410E40C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_260 0x410E410
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_261 0x410E414
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_262 0x410E418
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_263 0x410E41C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_264 0x410E420
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_265 0x410E424
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_266 0x410E428
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_267 0x410E42C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_268 0x410E430
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_269 0x410E434
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_270 0x410E438
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_271 0x410E43C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_272 0x410E440
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_273 0x410E444
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_274 0x410E448
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_275 0x410E44C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_276 0x410E450
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_277 0x410E454
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_278 0x410E458
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_279 0x410E45C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_280 0x410E460
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_281 0x410E464
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_282 0x410E468
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_283 0x410E46C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_284 0x410E470
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_285 0x410E474
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_286 0x410E478
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_287 0x410E47C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_288 0x410E480
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_289 0x410E484
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_290 0x410E488
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_291 0x410E48C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_292 0x410E490
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_293 0x410E494
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_294 0x410E498
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_295 0x410E49C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_296 0x410E4A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_297 0x410E4A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_298 0x410E4A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_299 0x410E4AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_300 0x410E4B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_301 0x410E4B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_302 0x410E4B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_303 0x410E4BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_304 0x410E4C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_305 0x410E4C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_306 0x410E4C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_307 0x410E4CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_308 0x410E4D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_309 0x410E4D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_310 0x410E4D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_311 0x410E4DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_312 0x410E4E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_313 0x410E4E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_314 0x410E4E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_315 0x410E4EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_316 0x410E4F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_317 0x410E4F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_318 0x410E4F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_319 0x410E4FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_320 0x410E500
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_321 0x410E504
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_322 0x410E508
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_323 0x410E50C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_324 0x410E510
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_325 0x410E514
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_326 0x410E518
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_327 0x410E51C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_328 0x410E520
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_329 0x410E524
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_330 0x410E528
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_331 0x410E52C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_332 0x410E530
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_333 0x410E534
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_334 0x410E538
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_335 0x410E53C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_336 0x410E540
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_337 0x410E544
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_338 0x410E548
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_339 0x410E54C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_340 0x410E550
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_341 0x410E554
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_342 0x410E558
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_343 0x410E55C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_344 0x410E560
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_345 0x410E564
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_346 0x410E568
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_347 0x410E56C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_348 0x410E570
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_349 0x410E574
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_350 0x410E578
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_351 0x410E57C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_352 0x410E580
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_353 0x410E584
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_354 0x410E588
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_355 0x410E58C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_356 0x410E590
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_357 0x410E594
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_358 0x410E598
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_359 0x410E59C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_360 0x410E5A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_361 0x410E5A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_362 0x410E5A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_363 0x410E5AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_364 0x410E5B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_365 0x410E5B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_366 0x410E5B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_367 0x410E5BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_368 0x410E5C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_369 0x410E5C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_370 0x410E5C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_371 0x410E5CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_372 0x410E5D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_373 0x410E5D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_374 0x410E5D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_375 0x410E5DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_376 0x410E5E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_377 0x410E5E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_378 0x410E5E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_379 0x410E5EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_380 0x410E5F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_381 0x410E5F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_382 0x410E5F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_383 0x410E5FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_384 0x410E600
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_385 0x410E604
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_386 0x410E608
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_387 0x410E60C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_388 0x410E610
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_389 0x410E614
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_390 0x410E618
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_391 0x410E61C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_392 0x410E620
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_393 0x410E624
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_394 0x410E628
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_395 0x410E62C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_396 0x410E630
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_397 0x410E634
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_398 0x410E638
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_399 0x410E63C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_400 0x410E640
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_401 0x410E644
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_402 0x410E648
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_403 0x410E64C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_404 0x410E650
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_405 0x410E654
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_406 0x410E658
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_407 0x410E65C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_408 0x410E660
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_409 0x410E664
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_410 0x410E668
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_411 0x410E66C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_412 0x410E670
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_413 0x410E674
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_414 0x410E678
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_415 0x410E67C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_416 0x410E680
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_417 0x410E684
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_418 0x410E688
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_419 0x410E68C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_420 0x410E690
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_421 0x410E694
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_422 0x410E698
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_423 0x410E69C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_424 0x410E6A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_425 0x410E6A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_426 0x410E6A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_427 0x410E6AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_428 0x410E6B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_429 0x410E6B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_430 0x410E6B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_431 0x410E6BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_432 0x410E6C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_433 0x410E6C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_434 0x410E6C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_435 0x410E6CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_436 0x410E6D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_437 0x410E6D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_438 0x410E6D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_439 0x410E6DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_440 0x410E6E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_441 0x410E6E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_442 0x410E6E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_443 0x410E6EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_444 0x410E6F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_445 0x410E6F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_446 0x410E6F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_447 0x410E6FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_448 0x410E700
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_449 0x410E704
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_450 0x410E708
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_451 0x410E70C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_452 0x410E710
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_453 0x410E714
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_454 0x410E718
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_455 0x410E71C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_456 0x410E720
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_457 0x410E724
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_458 0x410E728
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_459 0x410E72C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_460 0x410E730
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_461 0x410E734
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_462 0x410E738
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_463 0x410E73C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_464 0x410E740
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_465 0x410E744
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_466 0x410E748
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_467 0x410E74C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_468 0x410E750
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_469 0x410E754
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_470 0x410E758
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_471 0x410E75C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_472 0x410E760
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_473 0x410E764
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_474 0x410E768
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_475 0x410E76C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_476 0x410E770
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_477 0x410E774
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_478 0x410E778
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_479 0x410E77C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_480 0x410E780
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_481 0x410E784
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_482 0x410E788
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_483 0x410E78C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_484 0x410E790
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_485 0x410E794
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_486 0x410E798
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_487 0x410E79C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_488 0x410E7A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_489 0x410E7A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_490 0x410E7A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_491 0x410E7AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_492 0x410E7B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_493 0x410E7B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_494 0x410E7B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_495 0x410E7BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_496 0x410E7C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_497 0x410E7C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_498 0x410E7C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_499 0x410E7CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_500 0x410E7D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_501 0x410E7D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_502 0x410E7D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_503 0x410E7DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_504 0x410E7E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_505 0x410E7E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_506 0x410E7E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_507 0x410E7EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_508 0x410E7F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_509 0x410E7F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_510 0x410E7F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_511 0x410E7FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_512 0x410E800
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_513 0x410E804
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_514 0x410E808
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_515 0x410E80C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_516 0x410E810
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_517 0x410E814
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_518 0x410E818
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_519 0x410E81C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_520 0x410E820
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_521 0x410E824
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_522 0x410E828
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_523 0x410E82C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_524 0x410E830
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_525 0x410E834
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_526 0x410E838
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_527 0x410E83C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_528 0x410E840
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_529 0x410E844
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_530 0x410E848
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_531 0x410E84C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_532 0x410E850
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_533 0x410E854
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_534 0x410E858
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_535 0x410E85C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_536 0x410E860
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_537 0x410E864
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_538 0x410E868
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_539 0x410E86C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_540 0x410E870
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_541 0x410E874
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_542 0x410E878
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_543 0x410E87C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_544 0x410E880
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_545 0x410E884
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_546 0x410E888
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_547 0x410E88C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_548 0x410E890
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_549 0x410E894
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_550 0x410E898
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_551 0x410E89C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_552 0x410E8A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_553 0x410E8A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_554 0x410E8A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_555 0x410E8AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_556 0x410E8B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_557 0x410E8B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_558 0x410E8B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_559 0x410E8BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_560 0x410E8C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_561 0x410E8C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_562 0x410E8C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_563 0x410E8CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_564 0x410E8D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_565 0x410E8D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_566 0x410E8D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_567 0x410E8DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_568 0x410E8E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_569 0x410E8E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_570 0x410E8E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_571 0x410E8EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_572 0x410E8F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_573 0x410E8F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_574 0x410E8F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_575 0x410E8FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_576 0x410E900
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_577 0x410E904
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_578 0x410E908
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_579 0x410E90C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_580 0x410E910
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_581 0x410E914
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_582 0x410E918
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_583 0x410E91C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_584 0x410E920
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_585 0x410E924
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_586 0x410E928
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_587 0x410E92C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_588 0x410E930
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_589 0x410E934
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_590 0x410E938
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_591 0x410E93C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_592 0x410E940
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_593 0x410E944
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_594 0x410E948
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_595 0x410E94C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_596 0x410E950
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_597 0x410E954
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_598 0x410E958
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_599 0x410E95C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_600 0x410E960
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_601 0x410E964
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_602 0x410E968
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_603 0x410E96C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_604 0x410E970
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_605 0x410E974
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_606 0x410E978
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_607 0x410E97C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_608 0x410E980
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_609 0x410E984
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_610 0x410E988
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_611 0x410E98C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_612 0x410E990
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_613 0x410E994
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_614 0x410E998
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_615 0x410E99C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_616 0x410E9A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_617 0x410E9A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_618 0x410E9A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_619 0x410E9AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_620 0x410E9B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_621 0x410E9B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_622 0x410E9B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_623 0x410E9BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_624 0x410E9C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_625 0x410E9C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_626 0x410E9C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_627 0x410E9CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_628 0x410E9D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_629 0x410E9D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_630 0x410E9D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_631 0x410E9DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_632 0x410E9E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_633 0x410E9E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_634 0x410E9E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_635 0x410E9EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_636 0x410E9F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_637 0x410E9F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_638 0x410E9F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_639 0x410E9FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_640 0x410EA00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_641 0x410EA04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_642 0x410EA08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_643 0x410EA0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_644 0x410EA10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_645 0x410EA14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_646 0x410EA18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_647 0x410EA1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_648 0x410EA20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_649 0x410EA24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_650 0x410EA28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_651 0x410EA2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_652 0x410EA30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_653 0x410EA34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_654 0x410EA38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_655 0x410EA3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_656 0x410EA40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_657 0x410EA44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_658 0x410EA48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_659 0x410EA4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_660 0x410EA50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_661 0x410EA54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_662 0x410EA58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_663 0x410EA5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_664 0x410EA60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_665 0x410EA64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_666 0x410EA68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_667 0x410EA6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_668 0x410EA70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_669 0x410EA74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_670 0x410EA78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_671 0x410EA7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_672 0x410EA80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_673 0x410EA84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_674 0x410EA88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_675 0x410EA8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_676 0x410EA90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_677 0x410EA94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_678 0x410EA98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_679 0x410EA9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_680 0x410EAA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_681 0x410EAA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_682 0x410EAA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_683 0x410EAAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_684 0x410EAB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_685 0x410EAB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_686 0x410EAB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_687 0x410EABC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_688 0x410EAC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_689 0x410EAC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_690 0x410EAC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_691 0x410EACC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_692 0x410EAD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_693 0x410EAD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_694 0x410EAD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_695 0x410EADC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_696 0x410EAE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_697 0x410EAE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_698 0x410EAE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_699 0x410EAEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_700 0x410EAF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_701 0x410EAF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_702 0x410EAF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_703 0x410EAFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_704 0x410EB00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_705 0x410EB04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_706 0x410EB08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_707 0x410EB0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_708 0x410EB10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_709 0x410EB14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_710 0x410EB18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_711 0x410EB1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_712 0x410EB20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_713 0x410EB24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_714 0x410EB28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_715 0x410EB2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_716 0x410EB30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_717 0x410EB34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_718 0x410EB38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_719 0x410EB3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_720 0x410EB40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_721 0x410EB44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_722 0x410EB48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_723 0x410EB4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_724 0x410EB50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_725 0x410EB54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_726 0x410EB58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_727 0x410EB5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_728 0x410EB60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_729 0x410EB64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_730 0x410EB68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_731 0x410EB6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_732 0x410EB70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_733 0x410EB74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_734 0x410EB78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_735 0x410EB7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_736 0x410EB80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_737 0x410EB84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_738 0x410EB88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_739 0x410EB8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_740 0x410EB90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_741 0x410EB94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_742 0x410EB98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_743 0x410EB9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_744 0x410EBA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_745 0x410EBA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_746 0x410EBA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_747 0x410EBAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_748 0x410EBB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_749 0x410EBB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_750 0x410EBB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_751 0x410EBBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_752 0x410EBC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_753 0x410EBC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_754 0x410EBC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_755 0x410EBCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_756 0x410EBD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_757 0x410EBD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_758 0x410EBD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_759 0x410EBDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_760 0x410EBE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_761 0x410EBE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_762 0x410EBE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_763 0x410EBEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_764 0x410EBF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_765 0x410EBF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_766 0x410EBF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_767 0x410EBFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_768 0x410EC00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_769 0x410EC04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_770 0x410EC08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_771 0x410EC0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_772 0x410EC10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_773 0x410EC14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_774 0x410EC18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_775 0x410EC1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_776 0x410EC20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_777 0x410EC24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_778 0x410EC28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_779 0x410EC2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_780 0x410EC30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_781 0x410EC34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_782 0x410EC38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_783 0x410EC3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_784 0x410EC40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_785 0x410EC44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_786 0x410EC48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_787 0x410EC4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_788 0x410EC50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_789 0x410EC54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_790 0x410EC58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_791 0x410EC5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_792 0x410EC60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_793 0x410EC64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_794 0x410EC68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_795 0x410EC6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_796 0x410EC70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_797 0x410EC74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_798 0x410EC78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_799 0x410EC7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_800 0x410EC80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_801 0x410EC84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_802 0x410EC88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_803 0x410EC8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_804 0x410EC90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_805 0x410EC94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_806 0x410EC98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_807 0x410EC9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_808 0x410ECA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_809 0x410ECA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_810 0x410ECA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_811 0x410ECAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_812 0x410ECB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_813 0x410ECB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_814 0x410ECB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_815 0x410ECBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_816 0x410ECC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_817 0x410ECC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_818 0x410ECC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_819 0x410ECCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_820 0x410ECD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_821 0x410ECD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_822 0x410ECD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_823 0x410ECDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_824 0x410ECE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_825 0x410ECE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_826 0x410ECE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_827 0x410ECEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_828 0x410ECF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_829 0x410ECF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_830 0x410ECF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_831 0x410ECFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_832 0x410ED00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_833 0x410ED04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_834 0x410ED08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_835 0x410ED0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_836 0x410ED10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_837 0x410ED14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_838 0x410ED18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_839 0x410ED1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_840 0x410ED20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_841 0x410ED24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_842 0x410ED28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_843 0x410ED2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_844 0x410ED30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_845 0x410ED34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_846 0x410ED38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_847 0x410ED3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_848 0x410ED40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_849 0x410ED44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_850 0x410ED48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_851 0x410ED4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_852 0x410ED50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_853 0x410ED54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_854 0x410ED58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_855 0x410ED5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_856 0x410ED60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_857 0x410ED64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_858 0x410ED68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_859 0x410ED6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_860 0x410ED70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_861 0x410ED74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_862 0x410ED78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_863 0x410ED7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_864 0x410ED80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_865 0x410ED84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_866 0x410ED88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_867 0x410ED8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_868 0x410ED90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_869 0x410ED94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_870 0x410ED98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_871 0x410ED9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_872 0x410EDA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_873 0x410EDA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_874 0x410EDA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_875 0x410EDAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_876 0x410EDB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_877 0x410EDB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_878 0x410EDB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_879 0x410EDBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_880 0x410EDC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_881 0x410EDC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_882 0x410EDC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_883 0x410EDCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_884 0x410EDD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_885 0x410EDD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_886 0x410EDD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_887 0x410EDDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_888 0x410EDE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_889 0x410EDE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_890 0x410EDE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_891 0x410EDEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_892 0x410EDF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_893 0x410EDF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_894 0x410EDF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_895 0x410EDFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_896 0x410EE00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_897 0x410EE04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_898 0x410EE08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_899 0x410EE0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_900 0x410EE10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_901 0x410EE14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_902 0x410EE18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_903 0x410EE1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_904 0x410EE20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_905 0x410EE24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_906 0x410EE28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_907 0x410EE2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_908 0x410EE30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_909 0x410EE34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_910 0x410EE38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_911 0x410EE3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_912 0x410EE40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_913 0x410EE44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_914 0x410EE48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_915 0x410EE4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_916 0x410EE50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_917 0x410EE54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_918 0x410EE58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_919 0x410EE5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_920 0x410EE60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_921 0x410EE64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_922 0x410EE68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_923 0x410EE6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_924 0x410EE70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_925 0x410EE74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_926 0x410EE78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_927 0x410EE7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_928 0x410EE80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_929 0x410EE84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_930 0x410EE88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_931 0x410EE8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_932 0x410EE90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_933 0x410EE94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_934 0x410EE98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_935 0x410EE9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_936 0x410EEA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_937 0x410EEA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_938 0x410EEA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_939 0x410EEAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_940 0x410EEB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_941 0x410EEB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_942 0x410EEB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_943 0x410EEBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_944 0x410EEC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_945 0x410EEC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_946 0x410EEC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_947 0x410EECC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_948 0x410EED0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_949 0x410EED4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_950 0x410EED8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_951 0x410EEDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_952 0x410EEE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_953 0x410EEE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_954 0x410EEE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_955 0x410EEEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_956 0x410EEF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_957 0x410EEF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_958 0x410EEF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_959 0x410EEFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_960 0x410EF00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_961 0x410EF04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_962 0x410EF08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_963 0x410EF0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_964 0x410EF10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_965 0x410EF14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_966 0x410EF18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_967 0x410EF1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_968 0x410EF20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_969 0x410EF24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_970 0x410EF28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_971 0x410EF2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_972 0x410EF30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_973 0x410EF34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_974 0x410EF38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_975 0x410EF3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_976 0x410EF40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_977 0x410EF44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_978 0x410EF48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_979 0x410EF4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_980 0x410EF50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_981 0x410EF54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_982 0x410EF58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_983 0x410EF5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_984 0x410EF60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_985 0x410EF64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_986 0x410EF68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_987 0x410EF6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_988 0x410EF70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_989 0x410EF74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_990 0x410EF78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_991 0x410EF7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_992 0x410EF80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_993 0x410EF84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_994 0x410EF88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_995 0x410EF8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_996 0x410EF90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_997 0x410EF94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_998 0x410EF98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_999 0x410EF9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1000 0x410EFA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1001 0x410EFA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1002 0x410EFA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1003 0x410EFAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1004 0x410EFB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1005 0x410EFB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1006 0x410EFB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1007 0x410EFBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1008 0x410EFC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1009 0x410EFC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1010 0x410EFC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1011 0x410EFCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1012 0x410EFD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1013 0x410EFD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1014 0x410EFD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1015 0x410EFDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1016 0x410EFE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1017 0x410EFE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1018 0x410EFE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1019 0x410EFEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1020 0x410EFF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1021 0x410EFF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1022 0x410EFF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1023 0x410EFFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1024 0x410F000
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1025 0x410F004
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1026 0x410F008
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1027 0x410F00C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1028 0x410F010
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1029 0x410F014
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1030 0x410F018
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1031 0x410F01C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1032 0x410F020
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1033 0x410F024
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1034 0x410F028
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1035 0x410F02C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1036 0x410F030
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1037 0x410F034
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1038 0x410F038
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1039 0x410F03C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1040 0x410F040
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1041 0x410F044
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1042 0x410F048
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1043 0x410F04C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1044 0x410F050
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1045 0x410F054
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1046 0x410F058
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1047 0x410F05C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1048 0x410F060
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1049 0x410F064
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1050 0x410F068
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1051 0x410F06C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1052 0x410F070
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1053 0x410F074
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1054 0x410F078
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1055 0x410F07C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1056 0x410F080
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1057 0x410F084
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1058 0x410F088
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1059 0x410F08C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1060 0x410F090
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1061 0x410F094
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1062 0x410F098
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1063 0x410F09C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1064 0x410F0A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1065 0x410F0A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1066 0x410F0A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1067 0x410F0AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1068 0x410F0B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1069 0x410F0B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1070 0x410F0B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1071 0x410F0BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1072 0x410F0C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1073 0x410F0C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1074 0x410F0C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1075 0x410F0CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1076 0x410F0D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1077 0x410F0D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1078 0x410F0D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1079 0x410F0DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1080 0x410F0E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1081 0x410F0E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1082 0x410F0E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1083 0x410F0EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1084 0x410F0F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1085 0x410F0F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1086 0x410F0F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1087 0x410F0FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1088 0x410F100
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1089 0x410F104
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1090 0x410F108
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1091 0x410F10C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1092 0x410F110
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1093 0x410F114
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1094 0x410F118
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1095 0x410F11C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1096 0x410F120
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1097 0x410F124
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1098 0x410F128
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1099 0x410F12C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1100 0x410F130
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1101 0x410F134
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1102 0x410F138
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1103 0x410F13C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1104 0x410F140
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1105 0x410F144
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1106 0x410F148
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1107 0x410F14C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1108 0x410F150
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1109 0x410F154
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1110 0x410F158
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1111 0x410F15C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1112 0x410F160
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1113 0x410F164
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1114 0x410F168
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1115 0x410F16C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1116 0x410F170
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1117 0x410F174
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1118 0x410F178
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1119 0x410F17C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1120 0x410F180
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1121 0x410F184
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1122 0x410F188
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1123 0x410F18C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1124 0x410F190
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1125 0x410F194
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1126 0x410F198
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1127 0x410F19C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1128 0x410F1A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1129 0x410F1A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1130 0x410F1A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1131 0x410F1AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1132 0x410F1B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1133 0x410F1B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1134 0x410F1B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1135 0x410F1BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1136 0x410F1C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1137 0x410F1C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1138 0x410F1C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1139 0x410F1CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1140 0x410F1D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1141 0x410F1D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1142 0x410F1D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1143 0x410F1DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1144 0x410F1E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1145 0x410F1E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1146 0x410F1E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1147 0x410F1EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1148 0x410F1F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1149 0x410F1F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1150 0x410F1F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1151 0x410F1FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1152 0x410F200
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1153 0x410F204
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1154 0x410F208
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1155 0x410F20C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1156 0x410F210
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1157 0x410F214
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1158 0x410F218
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1159 0x410F21C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1160 0x410F220
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1161 0x410F224
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1162 0x410F228
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1163 0x410F22C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1164 0x410F230
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1165 0x410F234
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1166 0x410F238
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1167 0x410F23C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1168 0x410F240
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1169 0x410F244
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1170 0x410F248
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1171 0x410F24C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1172 0x410F250
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1173 0x410F254
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1174 0x410F258
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1175 0x410F25C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1176 0x410F260
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1177 0x410F264
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1178 0x410F268
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1179 0x410F26C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1180 0x410F270
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1181 0x410F274
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1182 0x410F278
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1183 0x410F27C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1184 0x410F280
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1185 0x410F284
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1186 0x410F288
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1187 0x410F28C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1188 0x410F290
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1189 0x410F294
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1190 0x410F298
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1191 0x410F29C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1192 0x410F2A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1193 0x410F2A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1194 0x410F2A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1195 0x410F2AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1196 0x410F2B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1197 0x410F2B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1198 0x410F2B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1199 0x410F2BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1200 0x410F2C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1201 0x410F2C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1202 0x410F2C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1203 0x410F2CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1204 0x410F2D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1205 0x410F2D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1206 0x410F2D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1207 0x410F2DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1208 0x410F2E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1209 0x410F2E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1210 0x410F2E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1211 0x410F2EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1212 0x410F2F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1213 0x410F2F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1214 0x410F2F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1215 0x410F2FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1216 0x410F300
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1217 0x410F304
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1218 0x410F308
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1219 0x410F30C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1220 0x410F310
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1221 0x410F314
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1222 0x410F318
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1223 0x410F31C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1224 0x410F320
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1225 0x410F324
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1226 0x410F328
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1227 0x410F32C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1228 0x410F330
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1229 0x410F334
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1230 0x410F338
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1231 0x410F33C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1232 0x410F340
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1233 0x410F344
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1234 0x410F348
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1235 0x410F34C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1236 0x410F350
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1237 0x410F354
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1238 0x410F358
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1239 0x410F35C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1240 0x410F360
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1241 0x410F364
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1242 0x410F368
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1243 0x410F36C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1244 0x410F370
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1245 0x410F374
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1246 0x410F378
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1247 0x410F37C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1248 0x410F380
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1249 0x410F384
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1250 0x410F388
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1251 0x410F38C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1252 0x410F390
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1253 0x410F394
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1254 0x410F398
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1255 0x410F39C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1256 0x410F3A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1257 0x410F3A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1258 0x410F3A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1259 0x410F3AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1260 0x410F3B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1261 0x410F3B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1262 0x410F3B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1263 0x410F3BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1264 0x410F3C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1265 0x410F3C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1266 0x410F3C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1267 0x410F3CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1268 0x410F3D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1269 0x410F3D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1270 0x410F3D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1271 0x410F3DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1272 0x410F3E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1273 0x410F3E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1274 0x410F3E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1275 0x410F3EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1276 0x410F3F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1277 0x410F3F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1278 0x410F3F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1279 0x410F3FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1280 0x410F400
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1281 0x410F404
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1282 0x410F408
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1283 0x410F40C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1284 0x410F410
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1285 0x410F414
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1286 0x410F418
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1287 0x410F41C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1288 0x410F420
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1289 0x410F424
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1290 0x410F428
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1291 0x410F42C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1292 0x410F430
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1293 0x410F434
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1294 0x410F438
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1295 0x410F43C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1296 0x410F440
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1297 0x410F444
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1298 0x410F448
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1299 0x410F44C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1300 0x410F450
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1301 0x410F454
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1302 0x410F458
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1303 0x410F45C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1304 0x410F460
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1305 0x410F464
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1306 0x410F468
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1307 0x410F46C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1308 0x410F470
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1309 0x410F474
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1310 0x410F478
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1311 0x410F47C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1312 0x410F480
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1313 0x410F484
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1314 0x410F488
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1315 0x410F48C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1316 0x410F490
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1317 0x410F494
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1318 0x410F498
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1319 0x410F49C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1320 0x410F4A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1321 0x410F4A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1322 0x410F4A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1323 0x410F4AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1324 0x410F4B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1325 0x410F4B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1326 0x410F4B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1327 0x410F4BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1328 0x410F4C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1329 0x410F4C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1330 0x410F4C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1331 0x410F4CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1332 0x410F4D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1333 0x410F4D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1334 0x410F4D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1335 0x410F4DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1336 0x410F4E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1337 0x410F4E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1338 0x410F4E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1339 0x410F4EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1340 0x410F4F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1341 0x410F4F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1342 0x410F4F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1343 0x410F4FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1344 0x410F500
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1345 0x410F504
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1346 0x410F508
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1347 0x410F50C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1348 0x410F510
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1349 0x410F514
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1350 0x410F518
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1351 0x410F51C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1352 0x410F520
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1353 0x410F524
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1354 0x410F528
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1355 0x410F52C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1356 0x410F530
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1357 0x410F534
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1358 0x410F538
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1359 0x410F53C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1360 0x410F540
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1361 0x410F544
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1362 0x410F548
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1363 0x410F54C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1364 0x410F550
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1365 0x410F554
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1366 0x410F558
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1367 0x410F55C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1368 0x410F560
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1369 0x410F564
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1370 0x410F568
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1371 0x410F56C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1372 0x410F570
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1373 0x410F574
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1374 0x410F578
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1375 0x410F57C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1376 0x410F580
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1377 0x410F584
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1378 0x410F588
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1379 0x410F58C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1380 0x410F590
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1381 0x410F594
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1382 0x410F598
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1383 0x410F59C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1384 0x410F5A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1385 0x410F5A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1386 0x410F5A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1387 0x410F5AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1388 0x410F5B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1389 0x410F5B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1390 0x410F5B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1391 0x410F5BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1392 0x410F5C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1393 0x410F5C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1394 0x410F5C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1395 0x410F5CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1396 0x410F5D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1397 0x410F5D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1398 0x410F5D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1399 0x410F5DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1400 0x410F5E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1401 0x410F5E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1402 0x410F5E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1403 0x410F5EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1404 0x410F5F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1405 0x410F5F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1406 0x410F5F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1407 0x410F5FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1408 0x410F600
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1409 0x410F604
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1410 0x410F608
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1411 0x410F60C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1412 0x410F610
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1413 0x410F614
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1414 0x410F618
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1415 0x410F61C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1416 0x410F620
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1417 0x410F624
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1418 0x410F628
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1419 0x410F62C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1420 0x410F630
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1421 0x410F634
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1422 0x410F638
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1423 0x410F63C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1424 0x410F640
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1425 0x410F644
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1426 0x410F648
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1427 0x410F64C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1428 0x410F650
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1429 0x410F654
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1430 0x410F658
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1431 0x410F65C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1432 0x410F660
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1433 0x410F664
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1434 0x410F668
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1435 0x410F66C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1436 0x410F670
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1437 0x410F674
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1438 0x410F678
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1439 0x410F67C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1440 0x410F680
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1441 0x410F684
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1442 0x410F688
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1443 0x410F68C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1444 0x410F690
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1445 0x410F694
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1446 0x410F698
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1447 0x410F69C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1448 0x410F6A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1449 0x410F6A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1450 0x410F6A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1451 0x410F6AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1452 0x410F6B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1453 0x410F6B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1454 0x410F6B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1455 0x410F6BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1456 0x410F6C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1457 0x410F6C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1458 0x410F6C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1459 0x410F6CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1460 0x410F6D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1461 0x410F6D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1462 0x410F6D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1463 0x410F6DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1464 0x410F6E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1465 0x410F6E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1466 0x410F6E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1467 0x410F6EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1468 0x410F6F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1469 0x410F6F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1470 0x410F6F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1471 0x410F6FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1472 0x410F700
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1473 0x410F704
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1474 0x410F708
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1475 0x410F70C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1476 0x410F710
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1477 0x410F714
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1478 0x410F718
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1479 0x410F71C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1480 0x410F720
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1481 0x410F724
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1482 0x410F728
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1483 0x410F72C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1484 0x410F730
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1485 0x410F734
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1486 0x410F738
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1487 0x410F73C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1488 0x410F740
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1489 0x410F744
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1490 0x410F748
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1491 0x410F74C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1492 0x410F750
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1493 0x410F754
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1494 0x410F758
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1495 0x410F75C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1496 0x410F760
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1497 0x410F764
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1498 0x410F768
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1499 0x410F76C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1500 0x410F770
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1501 0x410F774
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1502 0x410F778
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1503 0x410F77C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1504 0x410F780
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1505 0x410F784
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1506 0x410F788
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1507 0x410F78C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1508 0x410F790
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1509 0x410F794
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1510 0x410F798
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1511 0x410F79C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1512 0x410F7A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1513 0x410F7A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1514 0x410F7A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1515 0x410F7AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1516 0x410F7B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1517 0x410F7B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1518 0x410F7B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1519 0x410F7BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1520 0x410F7C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1521 0x410F7C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1522 0x410F7C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1523 0x410F7CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1524 0x410F7D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1525 0x410F7D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1526 0x410F7D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1527 0x410F7DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1528 0x410F7E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1529 0x410F7E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1530 0x410F7E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1531 0x410F7EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1532 0x410F7F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1533 0x410F7F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1534 0x410F7F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1535 0x410F7FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1536 0x410F800
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1537 0x410F804
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1538 0x410F808
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1539 0x410F80C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1540 0x410F810
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1541 0x410F814
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1542 0x410F818
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1543 0x410F81C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1544 0x410F820
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1545 0x410F824
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1546 0x410F828
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1547 0x410F82C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1548 0x410F830
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1549 0x410F834
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1550 0x410F838
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1551 0x410F83C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1552 0x410F840
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1553 0x410F844
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1554 0x410F848
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1555 0x410F84C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1556 0x410F850
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1557 0x410F854
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1558 0x410F858
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1559 0x410F85C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1560 0x410F860
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1561 0x410F864
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1562 0x410F868
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1563 0x410F86C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1564 0x410F870
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1565 0x410F874
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1566 0x410F878
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1567 0x410F87C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1568 0x410F880
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1569 0x410F884
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1570 0x410F888
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1571 0x410F88C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1572 0x410F890
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1573 0x410F894
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1574 0x410F898
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1575 0x410F89C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1576 0x410F8A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1577 0x410F8A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1578 0x410F8A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1579 0x410F8AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1580 0x410F8B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1581 0x410F8B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1582 0x410F8B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1583 0x410F8BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1584 0x410F8C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1585 0x410F8C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1586 0x410F8C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1587 0x410F8CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1588 0x410F8D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1589 0x410F8D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1590 0x410F8D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1591 0x410F8DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1592 0x410F8E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1593 0x410F8E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1594 0x410F8E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1595 0x410F8EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1596 0x410F8F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1597 0x410F8F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1598 0x410F8F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1599 0x410F8FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1600 0x410F900
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1601 0x410F904
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1602 0x410F908
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1603 0x410F90C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1604 0x410F910
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1605 0x410F914
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1606 0x410F918
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1607 0x410F91C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1608 0x410F920
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1609 0x410F924
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1610 0x410F928
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1611 0x410F92C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1612 0x410F930
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1613 0x410F934
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1614 0x410F938
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1615 0x410F93C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1616 0x410F940
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1617 0x410F944
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1618 0x410F948
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1619 0x410F94C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1620 0x410F950
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1621 0x410F954
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1622 0x410F958
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1623 0x410F95C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1624 0x410F960
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1625 0x410F964
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1626 0x410F968
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1627 0x410F96C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1628 0x410F970
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1629 0x410F974
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1630 0x410F978
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1631 0x410F97C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1632 0x410F980
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1633 0x410F984
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1634 0x410F988
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1635 0x410F98C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1636 0x410F990
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1637 0x410F994
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1638 0x410F998
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1639 0x410F99C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1640 0x410F9A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1641 0x410F9A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1642 0x410F9A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1643 0x410F9AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1644 0x410F9B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1645 0x410F9B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1646 0x410F9B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1647 0x410F9BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1648 0x410F9C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1649 0x410F9C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1650 0x410F9C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1651 0x410F9CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1652 0x410F9D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1653 0x410F9D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1654 0x410F9D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1655 0x410F9DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1656 0x410F9E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1657 0x410F9E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1658 0x410F9E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1659 0x410F9EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1660 0x410F9F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1661 0x410F9F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1662 0x410F9F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1663 0x410F9FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1664 0x410FA00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1665 0x410FA04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1666 0x410FA08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1667 0x410FA0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1668 0x410FA10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1669 0x410FA14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1670 0x410FA18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1671 0x410FA1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1672 0x410FA20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1673 0x410FA24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1674 0x410FA28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1675 0x410FA2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1676 0x410FA30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1677 0x410FA34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1678 0x410FA38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1679 0x410FA3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1680 0x410FA40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1681 0x410FA44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1682 0x410FA48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1683 0x410FA4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1684 0x410FA50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1685 0x410FA54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1686 0x410FA58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1687 0x410FA5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1688 0x410FA60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1689 0x410FA64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1690 0x410FA68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1691 0x410FA6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1692 0x410FA70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1693 0x410FA74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1694 0x410FA78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1695 0x410FA7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1696 0x410FA80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1697 0x410FA84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1698 0x410FA88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1699 0x410FA8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1700 0x410FA90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1701 0x410FA94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1702 0x410FA98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1703 0x410FA9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1704 0x410FAA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1705 0x410FAA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1706 0x410FAA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1707 0x410FAAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1708 0x410FAB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1709 0x410FAB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1710 0x410FAB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1711 0x410FABC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1712 0x410FAC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1713 0x410FAC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1714 0x410FAC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1715 0x410FACC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1716 0x410FAD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1717 0x410FAD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1718 0x410FAD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1719 0x410FADC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1720 0x410FAE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1721 0x410FAE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1722 0x410FAE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1723 0x410FAEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1724 0x410FAF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1725 0x410FAF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1726 0x410FAF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1727 0x410FAFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1728 0x410FB00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1729 0x410FB04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1730 0x410FB08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1731 0x410FB0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1732 0x410FB10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1733 0x410FB14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1734 0x410FB18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1735 0x410FB1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1736 0x410FB20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1737 0x410FB24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1738 0x410FB28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1739 0x410FB2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1740 0x410FB30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1741 0x410FB34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1742 0x410FB38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1743 0x410FB3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1744 0x410FB40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1745 0x410FB44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1746 0x410FB48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1747 0x410FB4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1748 0x410FB50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1749 0x410FB54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1750 0x410FB58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1751 0x410FB5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1752 0x410FB60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1753 0x410FB64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1754 0x410FB68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1755 0x410FB6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1756 0x410FB70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1757 0x410FB74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1758 0x410FB78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1759 0x410FB7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1760 0x410FB80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1761 0x410FB84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1762 0x410FB88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1763 0x410FB8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1764 0x410FB90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1765 0x410FB94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1766 0x410FB98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1767 0x410FB9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1768 0x410FBA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1769 0x410FBA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1770 0x410FBA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1771 0x410FBAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1772 0x410FBB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1773 0x410FBB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1774 0x410FBB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1775 0x410FBBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1776 0x410FBC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1777 0x410FBC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1778 0x410FBC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1779 0x410FBCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1780 0x410FBD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1781 0x410FBD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1782 0x410FBD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1783 0x410FBDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1784 0x410FBE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1785 0x410FBE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1786 0x410FBE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1787 0x410FBEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1788 0x410FBF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1789 0x410FBF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1790 0x410FBF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1791 0x410FBFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1792 0x410FC00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1793 0x410FC04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1794 0x410FC08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1795 0x410FC0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1796 0x410FC10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1797 0x410FC14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1798 0x410FC18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1799 0x410FC1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1800 0x410FC20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1801 0x410FC24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1802 0x410FC28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1803 0x410FC2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1804 0x410FC30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1805 0x410FC34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1806 0x410FC38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1807 0x410FC3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1808 0x410FC40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1809 0x410FC44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1810 0x410FC48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1811 0x410FC4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1812 0x410FC50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1813 0x410FC54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1814 0x410FC58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1815 0x410FC5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1816 0x410FC60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1817 0x410FC64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1818 0x410FC68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1819 0x410FC6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1820 0x410FC70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1821 0x410FC74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1822 0x410FC78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1823 0x410FC7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1824 0x410FC80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1825 0x410FC84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1826 0x410FC88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1827 0x410FC8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1828 0x410FC90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1829 0x410FC94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1830 0x410FC98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1831 0x410FC9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1832 0x410FCA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1833 0x410FCA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1834 0x410FCA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1835 0x410FCAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1836 0x410FCB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1837 0x410FCB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1838 0x410FCB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1839 0x410FCBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1840 0x410FCC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1841 0x410FCC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1842 0x410FCC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1843 0x410FCCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1844 0x410FCD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1845 0x410FCD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1846 0x410FCD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1847 0x410FCDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1848 0x410FCE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1849 0x410FCE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1850 0x410FCE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1851 0x410FCEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1852 0x410FCF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1853 0x410FCF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1854 0x410FCF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1855 0x410FCFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1856 0x410FD00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1857 0x410FD04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1858 0x410FD08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1859 0x410FD0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1860 0x410FD10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1861 0x410FD14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1862 0x410FD18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1863 0x410FD1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1864 0x410FD20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1865 0x410FD24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1866 0x410FD28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1867 0x410FD2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1868 0x410FD30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1869 0x410FD34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1870 0x410FD38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1871 0x410FD3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1872 0x410FD40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1873 0x410FD44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1874 0x410FD48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1875 0x410FD4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1876 0x410FD50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1877 0x410FD54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1878 0x410FD58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1879 0x410FD5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1880 0x410FD60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1881 0x410FD64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1882 0x410FD68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1883 0x410FD6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1884 0x410FD70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1885 0x410FD74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1886 0x410FD78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1887 0x410FD7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1888 0x410FD80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1889 0x410FD84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1890 0x410FD88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1891 0x410FD8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1892 0x410FD90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1893 0x410FD94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1894 0x410FD98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1895 0x410FD9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1896 0x410FDA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1897 0x410FDA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1898 0x410FDA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1899 0x410FDAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1900 0x410FDB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1901 0x410FDB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1902 0x410FDB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1903 0x410FDBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1904 0x410FDC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1905 0x410FDC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1906 0x410FDC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1907 0x410FDCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1908 0x410FDD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1909 0x410FDD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1910 0x410FDD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1911 0x410FDDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1912 0x410FDE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1913 0x410FDE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1914 0x410FDE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1915 0x410FDEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1916 0x410FDF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1917 0x410FDF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1918 0x410FDF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1919 0x410FDFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1920 0x410FE00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1921 0x410FE04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1922 0x410FE08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1923 0x410FE0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1924 0x410FE10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1925 0x410FE14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1926 0x410FE18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1927 0x410FE1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1928 0x410FE20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1929 0x410FE24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1930 0x410FE28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1931 0x410FE2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1932 0x410FE30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1933 0x410FE34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1934 0x410FE38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1935 0x410FE3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1936 0x410FE40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1937 0x410FE44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1938 0x410FE48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1939 0x410FE4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1940 0x410FE50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1941 0x410FE54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1942 0x410FE58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1943 0x410FE5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1944 0x410FE60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1945 0x410FE64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1946 0x410FE68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1947 0x410FE6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1948 0x410FE70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1949 0x410FE74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1950 0x410FE78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1951 0x410FE7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1952 0x410FE80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1953 0x410FE84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1954 0x410FE88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1955 0x410FE8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1956 0x410FE90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1957 0x410FE94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1958 0x410FE98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1959 0x410FE9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1960 0x410FEA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1961 0x410FEA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1962 0x410FEA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1963 0x410FEAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1964 0x410FEB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1965 0x410FEB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1966 0x410FEB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1967 0x410FEBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1968 0x410FEC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1969 0x410FEC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1970 0x410FEC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1971 0x410FECC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1972 0x410FED0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1973 0x410FED4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1974 0x410FED8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1975 0x410FEDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1976 0x410FEE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1977 0x410FEE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1978 0x410FEE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1979 0x410FEEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1980 0x410FEF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1981 0x410FEF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1982 0x410FEF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1983 0x410FEFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1984 0x410FF00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1985 0x410FF04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1986 0x410FF08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1987 0x410FF0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1988 0x410FF10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1989 0x410FF14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1990 0x410FF18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1991 0x410FF1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1992 0x410FF20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1993 0x410FF24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1994 0x410FF28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1995 0x410FF2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1996 0x410FF30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1997 0x410FF34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1998 0x410FF38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_1999 0x410FF3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2000 0x410FF40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2001 0x410FF44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2002 0x410FF48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2003 0x410FF4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2004 0x410FF50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2005 0x410FF54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2006 0x410FF58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2007 0x410FF5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2008 0x410FF60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2009 0x410FF64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2010 0x410FF68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2011 0x410FF6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2012 0x410FF70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2013 0x410FF74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2014 0x410FF78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2015 0x410FF7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2016 0x410FF80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2017 0x410FF84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2018 0x410FF88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2019 0x410FF8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2020 0x410FF90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2021 0x410FF94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2022 0x410FF98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2023 0x410FF9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2024 0x410FFA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2025 0x410FFA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2026 0x410FFA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2027 0x410FFAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2028 0x410FFB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2029 0x410FFB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2030 0x410FFB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2031 0x410FFBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2032 0x410FFC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2033 0x410FFC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2034 0x410FFC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2035 0x410FFCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2036 0x410FFD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2037 0x410FFD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2038 0x410FFD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2039 0x410FFDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2040 0x410FFE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2041 0x410FFE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2042 0x410FFE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2043 0x410FFEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2044 0x410FFF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2045 0x410FFF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2046 0x410FFF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_2047 0x410FFFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 0x4110000
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1 0x4110004
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2 0x4110008
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_3 0x411000C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_4 0x4110010
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_5 0x4110014
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_6 0x4110018
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_7 0x411001C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_8 0x4110020
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_9 0x4110024
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_10 0x4110028
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_11 0x411002C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_12 0x4110030
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_13 0x4110034
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_14 0x4110038
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_15 0x411003C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_16 0x4110040
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_17 0x4110044
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_18 0x4110048
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_19 0x411004C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_20 0x4110050
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_21 0x4110054
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_22 0x4110058
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_23 0x411005C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_24 0x4110060
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_25 0x4110064
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_26 0x4110068
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_27 0x411006C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_28 0x4110070
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_29 0x4110074
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_30 0x4110078
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_31 0x411007C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_32 0x4110080
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_33 0x4110084
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_34 0x4110088
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_35 0x411008C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_36 0x4110090
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_37 0x4110094
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_38 0x4110098
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_39 0x411009C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_40 0x41100A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_41 0x41100A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_42 0x41100A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_43 0x41100AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_44 0x41100B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_45 0x41100B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_46 0x41100B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_47 0x41100BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_48 0x41100C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_49 0x41100C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_50 0x41100C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_51 0x41100CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_52 0x41100D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_53 0x41100D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_54 0x41100D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_55 0x41100DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_56 0x41100E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_57 0x41100E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_58 0x41100E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_59 0x41100EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_60 0x41100F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_61 0x41100F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_62 0x41100F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_63 0x41100FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_64 0x4110100
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_65 0x4110104
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_66 0x4110108
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_67 0x411010C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_68 0x4110110
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_69 0x4110114
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_70 0x4110118
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_71 0x411011C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_72 0x4110120
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_73 0x4110124
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_74 0x4110128
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_75 0x411012C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_76 0x4110130
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_77 0x4110134
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_78 0x4110138
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_79 0x411013C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_80 0x4110140
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_81 0x4110144
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_82 0x4110148
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_83 0x411014C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_84 0x4110150
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_85 0x4110154
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_86 0x4110158
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_87 0x411015C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_88 0x4110160
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_89 0x4110164
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_90 0x4110168
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_91 0x411016C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_92 0x4110170
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_93 0x4110174
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_94 0x4110178
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_95 0x411017C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_96 0x4110180
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_97 0x4110184
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_98 0x4110188
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_99 0x411018C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_100 0x4110190
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_101 0x4110194
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_102 0x4110198
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_103 0x411019C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_104 0x41101A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_105 0x41101A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_106 0x41101A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_107 0x41101AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_108 0x41101B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_109 0x41101B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_110 0x41101B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_111 0x41101BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_112 0x41101C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_113 0x41101C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_114 0x41101C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_115 0x41101CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_116 0x41101D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_117 0x41101D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_118 0x41101D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_119 0x41101DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_120 0x41101E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_121 0x41101E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_122 0x41101E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_123 0x41101EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_124 0x41101F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_125 0x41101F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_126 0x41101F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_127 0x41101FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_128 0x4110200
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_129 0x4110204
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_130 0x4110208
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_131 0x411020C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_132 0x4110210
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_133 0x4110214
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_134 0x4110218
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_135 0x411021C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_136 0x4110220
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_137 0x4110224
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_138 0x4110228
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_139 0x411022C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_140 0x4110230
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_141 0x4110234
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_142 0x4110238
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_143 0x411023C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_144 0x4110240
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_145 0x4110244
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_146 0x4110248
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_147 0x411024C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_148 0x4110250
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_149 0x4110254
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_150 0x4110258
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_151 0x411025C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_152 0x4110260
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_153 0x4110264
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_154 0x4110268
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_155 0x411026C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_156 0x4110270
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_157 0x4110274
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_158 0x4110278
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_159 0x411027C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_160 0x4110280
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_161 0x4110284
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_162 0x4110288
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_163 0x411028C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_164 0x4110290
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_165 0x4110294
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_166 0x4110298
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_167 0x411029C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_168 0x41102A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_169 0x41102A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_170 0x41102A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_171 0x41102AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_172 0x41102B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_173 0x41102B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_174 0x41102B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_175 0x41102BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_176 0x41102C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_177 0x41102C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_178 0x41102C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_179 0x41102CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_180 0x41102D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_181 0x41102D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_182 0x41102D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_183 0x41102DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_184 0x41102E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_185 0x41102E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_186 0x41102E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_187 0x41102EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_188 0x41102F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_189 0x41102F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_190 0x41102F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_191 0x41102FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_192 0x4110300
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_193 0x4110304
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_194 0x4110308
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_195 0x411030C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_196 0x4110310
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_197 0x4110314
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_198 0x4110318
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_199 0x411031C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_200 0x4110320
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_201 0x4110324
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_202 0x4110328
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_203 0x411032C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_204 0x4110330
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_205 0x4110334
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_206 0x4110338
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_207 0x411033C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_208 0x4110340
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_209 0x4110344
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_210 0x4110348
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_211 0x411034C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_212 0x4110350
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_213 0x4110354
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_214 0x4110358
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_215 0x411035C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_216 0x4110360
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_217 0x4110364
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_218 0x4110368
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_219 0x411036C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_220 0x4110370
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_221 0x4110374
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_222 0x4110378
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_223 0x411037C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_224 0x4110380
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_225 0x4110384
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_226 0x4110388
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_227 0x411038C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_228 0x4110390
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_229 0x4110394
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_230 0x4110398
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_231 0x411039C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_232 0x41103A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_233 0x41103A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_234 0x41103A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_235 0x41103AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_236 0x41103B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_237 0x41103B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_238 0x41103B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_239 0x41103BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_240 0x41103C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_241 0x41103C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_242 0x41103C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_243 0x41103CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_244 0x41103D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_245 0x41103D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_246 0x41103D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_247 0x41103DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_248 0x41103E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_249 0x41103E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_250 0x41103E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_251 0x41103EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_252 0x41103F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_253 0x41103F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_254 0x41103F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_255 0x41103FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_256 0x4110400
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_257 0x4110404
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_258 0x4110408
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_259 0x411040C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_260 0x4110410
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_261 0x4110414
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_262 0x4110418
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_263 0x411041C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_264 0x4110420
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_265 0x4110424
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_266 0x4110428
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_267 0x411042C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_268 0x4110430
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_269 0x4110434
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_270 0x4110438
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_271 0x411043C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_272 0x4110440
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_273 0x4110444
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_274 0x4110448
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_275 0x411044C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_276 0x4110450
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_277 0x4110454
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_278 0x4110458
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_279 0x411045C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_280 0x4110460
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_281 0x4110464
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_282 0x4110468
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_283 0x411046C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_284 0x4110470
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_285 0x4110474
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_286 0x4110478
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_287 0x411047C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_288 0x4110480
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_289 0x4110484
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_290 0x4110488
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_291 0x411048C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_292 0x4110490
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_293 0x4110494
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_294 0x4110498
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_295 0x411049C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_296 0x41104A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_297 0x41104A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_298 0x41104A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_299 0x41104AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_300 0x41104B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_301 0x41104B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_302 0x41104B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_303 0x41104BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_304 0x41104C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_305 0x41104C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_306 0x41104C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_307 0x41104CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_308 0x41104D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_309 0x41104D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_310 0x41104D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_311 0x41104DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_312 0x41104E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_313 0x41104E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_314 0x41104E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_315 0x41104EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_316 0x41104F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_317 0x41104F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_318 0x41104F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_319 0x41104FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_320 0x4110500
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_321 0x4110504
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_322 0x4110508
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_323 0x411050C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_324 0x4110510
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_325 0x4110514
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_326 0x4110518
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_327 0x411051C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_328 0x4110520
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_329 0x4110524
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_330 0x4110528
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_331 0x411052C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_332 0x4110530
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_333 0x4110534
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_334 0x4110538
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_335 0x411053C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_336 0x4110540
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_337 0x4110544
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_338 0x4110548
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_339 0x411054C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_340 0x4110550
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_341 0x4110554
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_342 0x4110558
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_343 0x411055C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_344 0x4110560
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_345 0x4110564
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_346 0x4110568
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_347 0x411056C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_348 0x4110570
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_349 0x4110574
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_350 0x4110578
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_351 0x411057C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_352 0x4110580
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_353 0x4110584
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_354 0x4110588
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_355 0x411058C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_356 0x4110590
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_357 0x4110594
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_358 0x4110598
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_359 0x411059C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_360 0x41105A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_361 0x41105A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_362 0x41105A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_363 0x41105AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_364 0x41105B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_365 0x41105B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_366 0x41105B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_367 0x41105BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_368 0x41105C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_369 0x41105C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_370 0x41105C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_371 0x41105CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_372 0x41105D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_373 0x41105D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_374 0x41105D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_375 0x41105DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_376 0x41105E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_377 0x41105E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_378 0x41105E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_379 0x41105EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_380 0x41105F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_381 0x41105F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_382 0x41105F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_383 0x41105FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_384 0x4110600
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_385 0x4110604
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_386 0x4110608
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_387 0x411060C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_388 0x4110610
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_389 0x4110614
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_390 0x4110618
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_391 0x411061C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_392 0x4110620
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_393 0x4110624
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_394 0x4110628
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_395 0x411062C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_396 0x4110630
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_397 0x4110634
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_398 0x4110638
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_399 0x411063C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_400 0x4110640
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_401 0x4110644
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_402 0x4110648
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_403 0x411064C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_404 0x4110650
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_405 0x4110654
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_406 0x4110658
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_407 0x411065C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_408 0x4110660
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_409 0x4110664
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_410 0x4110668
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_411 0x411066C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_412 0x4110670
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_413 0x4110674
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_414 0x4110678
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_415 0x411067C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_416 0x4110680
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_417 0x4110684
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_418 0x4110688
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_419 0x411068C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_420 0x4110690
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_421 0x4110694
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_422 0x4110698
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_423 0x411069C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_424 0x41106A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_425 0x41106A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_426 0x41106A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_427 0x41106AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_428 0x41106B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_429 0x41106B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_430 0x41106B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_431 0x41106BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_432 0x41106C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_433 0x41106C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_434 0x41106C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_435 0x41106CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_436 0x41106D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_437 0x41106D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_438 0x41106D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_439 0x41106DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_440 0x41106E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_441 0x41106E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_442 0x41106E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_443 0x41106EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_444 0x41106F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_445 0x41106F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_446 0x41106F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_447 0x41106FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_448 0x4110700
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_449 0x4110704
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_450 0x4110708
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_451 0x411070C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_452 0x4110710
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_453 0x4110714
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_454 0x4110718
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_455 0x411071C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_456 0x4110720
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_457 0x4110724
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_458 0x4110728
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_459 0x411072C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_460 0x4110730
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_461 0x4110734
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_462 0x4110738
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_463 0x411073C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_464 0x4110740
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_465 0x4110744
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_466 0x4110748
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_467 0x411074C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_468 0x4110750
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_469 0x4110754
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_470 0x4110758
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_471 0x411075C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_472 0x4110760
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_473 0x4110764
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_474 0x4110768
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_475 0x411076C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_476 0x4110770
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_477 0x4110774
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_478 0x4110778
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_479 0x411077C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_480 0x4110780
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_481 0x4110784
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_482 0x4110788
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_483 0x411078C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_484 0x4110790
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_485 0x4110794
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_486 0x4110798
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_487 0x411079C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_488 0x41107A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_489 0x41107A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_490 0x41107A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_491 0x41107AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_492 0x41107B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_493 0x41107B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_494 0x41107B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_495 0x41107BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_496 0x41107C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_497 0x41107C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_498 0x41107C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_499 0x41107CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_500 0x41107D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_501 0x41107D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_502 0x41107D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_503 0x41107DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_504 0x41107E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_505 0x41107E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_506 0x41107E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_507 0x41107EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_508 0x41107F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_509 0x41107F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_510 0x41107F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_511 0x41107FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_512 0x4110800
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_513 0x4110804
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_514 0x4110808
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_515 0x411080C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_516 0x4110810
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_517 0x4110814
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_518 0x4110818
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_519 0x411081C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_520 0x4110820
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_521 0x4110824
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_522 0x4110828
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_523 0x411082C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_524 0x4110830
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_525 0x4110834
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_526 0x4110838
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_527 0x411083C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_528 0x4110840
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_529 0x4110844
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_530 0x4110848
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_531 0x411084C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_532 0x4110850
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_533 0x4110854
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_534 0x4110858
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_535 0x411085C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_536 0x4110860
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_537 0x4110864
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_538 0x4110868
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_539 0x411086C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_540 0x4110870
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_541 0x4110874
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_542 0x4110878
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_543 0x411087C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_544 0x4110880
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_545 0x4110884
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_546 0x4110888
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_547 0x411088C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_548 0x4110890
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_549 0x4110894
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_550 0x4110898
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_551 0x411089C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_552 0x41108A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_553 0x41108A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_554 0x41108A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_555 0x41108AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_556 0x41108B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_557 0x41108B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_558 0x41108B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_559 0x41108BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_560 0x41108C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_561 0x41108C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_562 0x41108C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_563 0x41108CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_564 0x41108D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_565 0x41108D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_566 0x41108D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_567 0x41108DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_568 0x41108E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_569 0x41108E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_570 0x41108E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_571 0x41108EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_572 0x41108F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_573 0x41108F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_574 0x41108F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_575 0x41108FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_576 0x4110900
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_577 0x4110904
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_578 0x4110908
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_579 0x411090C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_580 0x4110910
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_581 0x4110914
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_582 0x4110918
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_583 0x411091C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_584 0x4110920
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_585 0x4110924
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_586 0x4110928
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_587 0x411092C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_588 0x4110930
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_589 0x4110934
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_590 0x4110938
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_591 0x411093C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_592 0x4110940
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_593 0x4110944
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_594 0x4110948
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_595 0x411094C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_596 0x4110950
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_597 0x4110954
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_598 0x4110958
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_599 0x411095C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_600 0x4110960
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_601 0x4110964
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_602 0x4110968
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_603 0x411096C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_604 0x4110970
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_605 0x4110974
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_606 0x4110978
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_607 0x411097C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_608 0x4110980
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_609 0x4110984
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_610 0x4110988
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_611 0x411098C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_612 0x4110990
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_613 0x4110994
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_614 0x4110998
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_615 0x411099C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_616 0x41109A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_617 0x41109A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_618 0x41109A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_619 0x41109AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_620 0x41109B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_621 0x41109B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_622 0x41109B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_623 0x41109BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_624 0x41109C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_625 0x41109C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_626 0x41109C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_627 0x41109CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_628 0x41109D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_629 0x41109D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_630 0x41109D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_631 0x41109DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_632 0x41109E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_633 0x41109E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_634 0x41109E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_635 0x41109EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_636 0x41109F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_637 0x41109F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_638 0x41109F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_639 0x41109FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_640 0x4110A00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_641 0x4110A04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_642 0x4110A08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_643 0x4110A0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_644 0x4110A10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_645 0x4110A14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_646 0x4110A18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_647 0x4110A1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_648 0x4110A20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_649 0x4110A24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_650 0x4110A28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_651 0x4110A2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_652 0x4110A30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_653 0x4110A34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_654 0x4110A38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_655 0x4110A3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_656 0x4110A40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_657 0x4110A44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_658 0x4110A48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_659 0x4110A4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_660 0x4110A50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_661 0x4110A54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_662 0x4110A58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_663 0x4110A5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_664 0x4110A60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_665 0x4110A64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_666 0x4110A68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_667 0x4110A6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_668 0x4110A70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_669 0x4110A74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_670 0x4110A78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_671 0x4110A7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_672 0x4110A80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_673 0x4110A84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_674 0x4110A88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_675 0x4110A8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_676 0x4110A90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_677 0x4110A94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_678 0x4110A98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_679 0x4110A9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_680 0x4110AA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_681 0x4110AA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_682 0x4110AA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_683 0x4110AAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_684 0x4110AB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_685 0x4110AB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_686 0x4110AB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_687 0x4110ABC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_688 0x4110AC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_689 0x4110AC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_690 0x4110AC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_691 0x4110ACC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_692 0x4110AD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_693 0x4110AD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_694 0x4110AD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_695 0x4110ADC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_696 0x4110AE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_697 0x4110AE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_698 0x4110AE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_699 0x4110AEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_700 0x4110AF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_701 0x4110AF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_702 0x4110AF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_703 0x4110AFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_704 0x4110B00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_705 0x4110B04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_706 0x4110B08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_707 0x4110B0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_708 0x4110B10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_709 0x4110B14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_710 0x4110B18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_711 0x4110B1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_712 0x4110B20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_713 0x4110B24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_714 0x4110B28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_715 0x4110B2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_716 0x4110B30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_717 0x4110B34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_718 0x4110B38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_719 0x4110B3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_720 0x4110B40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_721 0x4110B44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_722 0x4110B48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_723 0x4110B4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_724 0x4110B50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_725 0x4110B54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_726 0x4110B58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_727 0x4110B5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_728 0x4110B60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_729 0x4110B64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_730 0x4110B68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_731 0x4110B6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_732 0x4110B70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_733 0x4110B74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_734 0x4110B78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_735 0x4110B7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_736 0x4110B80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_737 0x4110B84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_738 0x4110B88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_739 0x4110B8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_740 0x4110B90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_741 0x4110B94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_742 0x4110B98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_743 0x4110B9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_744 0x4110BA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_745 0x4110BA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_746 0x4110BA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_747 0x4110BAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_748 0x4110BB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_749 0x4110BB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_750 0x4110BB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_751 0x4110BBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_752 0x4110BC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_753 0x4110BC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_754 0x4110BC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_755 0x4110BCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_756 0x4110BD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_757 0x4110BD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_758 0x4110BD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_759 0x4110BDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_760 0x4110BE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_761 0x4110BE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_762 0x4110BE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_763 0x4110BEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_764 0x4110BF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_765 0x4110BF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_766 0x4110BF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_767 0x4110BFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_768 0x4110C00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_769 0x4110C04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_770 0x4110C08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_771 0x4110C0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_772 0x4110C10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_773 0x4110C14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_774 0x4110C18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_775 0x4110C1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_776 0x4110C20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_777 0x4110C24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_778 0x4110C28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_779 0x4110C2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_780 0x4110C30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_781 0x4110C34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_782 0x4110C38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_783 0x4110C3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_784 0x4110C40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_785 0x4110C44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_786 0x4110C48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_787 0x4110C4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_788 0x4110C50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_789 0x4110C54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_790 0x4110C58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_791 0x4110C5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_792 0x4110C60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_793 0x4110C64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_794 0x4110C68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_795 0x4110C6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_796 0x4110C70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_797 0x4110C74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_798 0x4110C78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_799 0x4110C7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_800 0x4110C80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_801 0x4110C84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_802 0x4110C88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_803 0x4110C8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_804 0x4110C90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_805 0x4110C94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_806 0x4110C98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_807 0x4110C9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_808 0x4110CA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_809 0x4110CA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_810 0x4110CA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_811 0x4110CAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_812 0x4110CB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_813 0x4110CB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_814 0x4110CB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_815 0x4110CBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_816 0x4110CC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_817 0x4110CC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_818 0x4110CC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_819 0x4110CCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_820 0x4110CD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_821 0x4110CD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_822 0x4110CD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_823 0x4110CDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_824 0x4110CE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_825 0x4110CE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_826 0x4110CE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_827 0x4110CEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_828 0x4110CF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_829 0x4110CF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_830 0x4110CF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_831 0x4110CFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_832 0x4110D00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_833 0x4110D04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_834 0x4110D08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_835 0x4110D0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_836 0x4110D10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_837 0x4110D14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_838 0x4110D18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_839 0x4110D1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_840 0x4110D20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_841 0x4110D24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_842 0x4110D28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_843 0x4110D2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_844 0x4110D30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_845 0x4110D34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_846 0x4110D38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_847 0x4110D3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_848 0x4110D40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_849 0x4110D44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_850 0x4110D48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_851 0x4110D4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_852 0x4110D50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_853 0x4110D54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_854 0x4110D58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_855 0x4110D5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_856 0x4110D60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_857 0x4110D64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_858 0x4110D68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_859 0x4110D6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_860 0x4110D70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_861 0x4110D74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_862 0x4110D78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_863 0x4110D7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_864 0x4110D80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_865 0x4110D84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_866 0x4110D88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_867 0x4110D8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_868 0x4110D90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_869 0x4110D94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_870 0x4110D98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_871 0x4110D9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_872 0x4110DA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_873 0x4110DA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_874 0x4110DA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_875 0x4110DAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_876 0x4110DB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_877 0x4110DB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_878 0x4110DB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_879 0x4110DBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_880 0x4110DC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_881 0x4110DC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_882 0x4110DC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_883 0x4110DCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_884 0x4110DD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_885 0x4110DD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_886 0x4110DD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_887 0x4110DDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_888 0x4110DE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_889 0x4110DE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_890 0x4110DE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_891 0x4110DEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_892 0x4110DF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_893 0x4110DF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_894 0x4110DF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_895 0x4110DFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_896 0x4110E00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_897 0x4110E04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_898 0x4110E08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_899 0x4110E0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_900 0x4110E10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_901 0x4110E14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_902 0x4110E18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_903 0x4110E1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_904 0x4110E20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_905 0x4110E24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_906 0x4110E28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_907 0x4110E2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_908 0x4110E30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_909 0x4110E34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_910 0x4110E38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_911 0x4110E3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_912 0x4110E40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_913 0x4110E44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_914 0x4110E48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_915 0x4110E4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_916 0x4110E50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_917 0x4110E54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_918 0x4110E58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_919 0x4110E5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_920 0x4110E60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_921 0x4110E64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_922 0x4110E68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_923 0x4110E6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_924 0x4110E70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_925 0x4110E74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_926 0x4110E78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_927 0x4110E7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_928 0x4110E80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_929 0x4110E84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_930 0x4110E88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_931 0x4110E8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_932 0x4110E90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_933 0x4110E94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_934 0x4110E98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_935 0x4110E9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_936 0x4110EA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_937 0x4110EA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_938 0x4110EA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_939 0x4110EAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_940 0x4110EB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_941 0x4110EB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_942 0x4110EB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_943 0x4110EBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_944 0x4110EC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_945 0x4110EC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_946 0x4110EC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_947 0x4110ECC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_948 0x4110ED0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_949 0x4110ED4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_950 0x4110ED8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_951 0x4110EDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_952 0x4110EE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_953 0x4110EE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_954 0x4110EE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_955 0x4110EEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_956 0x4110EF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_957 0x4110EF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_958 0x4110EF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_959 0x4110EFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_960 0x4110F00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_961 0x4110F04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_962 0x4110F08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_963 0x4110F0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_964 0x4110F10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_965 0x4110F14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_966 0x4110F18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_967 0x4110F1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_968 0x4110F20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_969 0x4110F24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_970 0x4110F28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_971 0x4110F2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_972 0x4110F30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_973 0x4110F34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_974 0x4110F38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_975 0x4110F3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_976 0x4110F40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_977 0x4110F44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_978 0x4110F48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_979 0x4110F4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_980 0x4110F50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_981 0x4110F54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_982 0x4110F58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_983 0x4110F5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_984 0x4110F60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_985 0x4110F64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_986 0x4110F68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_987 0x4110F6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_988 0x4110F70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_989 0x4110F74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_990 0x4110F78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_991 0x4110F7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_992 0x4110F80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_993 0x4110F84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_994 0x4110F88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_995 0x4110F8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_996 0x4110F90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_997 0x4110F94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_998 0x4110F98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_999 0x4110F9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1000 0x4110FA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1001 0x4110FA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1002 0x4110FA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1003 0x4110FAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1004 0x4110FB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1005 0x4110FB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1006 0x4110FB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1007 0x4110FBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1008 0x4110FC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1009 0x4110FC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1010 0x4110FC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1011 0x4110FCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1012 0x4110FD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1013 0x4110FD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1014 0x4110FD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1015 0x4110FDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1016 0x4110FE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1017 0x4110FE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1018 0x4110FE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1019 0x4110FEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1020 0x4110FF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1021 0x4110FF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1022 0x4110FF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1023 0x4110FFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1024 0x4111000
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1025 0x4111004
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1026 0x4111008
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1027 0x411100C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1028 0x4111010
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1029 0x4111014
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1030 0x4111018
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1031 0x411101C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1032 0x4111020
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1033 0x4111024
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1034 0x4111028
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1035 0x411102C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1036 0x4111030
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1037 0x4111034
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1038 0x4111038
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1039 0x411103C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1040 0x4111040
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1041 0x4111044
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1042 0x4111048
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1043 0x411104C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1044 0x4111050
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1045 0x4111054
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1046 0x4111058
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1047 0x411105C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1048 0x4111060
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1049 0x4111064
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1050 0x4111068
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1051 0x411106C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1052 0x4111070
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1053 0x4111074
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1054 0x4111078
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1055 0x411107C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1056 0x4111080
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1057 0x4111084
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1058 0x4111088
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1059 0x411108C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1060 0x4111090
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1061 0x4111094
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1062 0x4111098
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1063 0x411109C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1064 0x41110A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1065 0x41110A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1066 0x41110A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1067 0x41110AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1068 0x41110B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1069 0x41110B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1070 0x41110B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1071 0x41110BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1072 0x41110C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1073 0x41110C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1074 0x41110C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1075 0x41110CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1076 0x41110D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1077 0x41110D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1078 0x41110D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1079 0x41110DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1080 0x41110E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1081 0x41110E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1082 0x41110E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1083 0x41110EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1084 0x41110F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1085 0x41110F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1086 0x41110F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1087 0x41110FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1088 0x4111100
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1089 0x4111104
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1090 0x4111108
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1091 0x411110C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1092 0x4111110
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1093 0x4111114
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1094 0x4111118
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1095 0x411111C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1096 0x4111120
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1097 0x4111124
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1098 0x4111128
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1099 0x411112C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1100 0x4111130
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1101 0x4111134
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1102 0x4111138
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1103 0x411113C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1104 0x4111140
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1105 0x4111144
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1106 0x4111148
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1107 0x411114C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1108 0x4111150
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1109 0x4111154
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1110 0x4111158
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1111 0x411115C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1112 0x4111160
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1113 0x4111164
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1114 0x4111168
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1115 0x411116C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1116 0x4111170
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1117 0x4111174
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1118 0x4111178
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1119 0x411117C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1120 0x4111180
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1121 0x4111184
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1122 0x4111188
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1123 0x411118C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1124 0x4111190
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1125 0x4111194
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1126 0x4111198
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1127 0x411119C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1128 0x41111A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1129 0x41111A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1130 0x41111A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1131 0x41111AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1132 0x41111B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1133 0x41111B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1134 0x41111B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1135 0x41111BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1136 0x41111C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1137 0x41111C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1138 0x41111C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1139 0x41111CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1140 0x41111D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1141 0x41111D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1142 0x41111D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1143 0x41111DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1144 0x41111E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1145 0x41111E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1146 0x41111E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1147 0x41111EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1148 0x41111F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1149 0x41111F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1150 0x41111F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1151 0x41111FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1152 0x4111200
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1153 0x4111204
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1154 0x4111208
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1155 0x411120C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1156 0x4111210
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1157 0x4111214
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1158 0x4111218
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1159 0x411121C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1160 0x4111220
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1161 0x4111224
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1162 0x4111228
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1163 0x411122C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1164 0x4111230
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1165 0x4111234
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1166 0x4111238
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1167 0x411123C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1168 0x4111240
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1169 0x4111244
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1170 0x4111248
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1171 0x411124C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1172 0x4111250
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1173 0x4111254
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1174 0x4111258
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1175 0x411125C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1176 0x4111260
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1177 0x4111264
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1178 0x4111268
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1179 0x411126C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1180 0x4111270
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1181 0x4111274
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1182 0x4111278
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1183 0x411127C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1184 0x4111280
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1185 0x4111284
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1186 0x4111288
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1187 0x411128C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1188 0x4111290
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1189 0x4111294
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1190 0x4111298
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1191 0x411129C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1192 0x41112A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1193 0x41112A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1194 0x41112A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1195 0x41112AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1196 0x41112B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1197 0x41112B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1198 0x41112B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1199 0x41112BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1200 0x41112C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1201 0x41112C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1202 0x41112C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1203 0x41112CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1204 0x41112D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1205 0x41112D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1206 0x41112D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1207 0x41112DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1208 0x41112E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1209 0x41112E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1210 0x41112E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1211 0x41112EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1212 0x41112F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1213 0x41112F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1214 0x41112F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1215 0x41112FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1216 0x4111300
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1217 0x4111304
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1218 0x4111308
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1219 0x411130C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1220 0x4111310
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1221 0x4111314
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1222 0x4111318
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1223 0x411131C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1224 0x4111320
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1225 0x4111324
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1226 0x4111328
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1227 0x411132C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1228 0x4111330
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1229 0x4111334
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1230 0x4111338
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1231 0x411133C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1232 0x4111340
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1233 0x4111344
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1234 0x4111348
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1235 0x411134C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1236 0x4111350
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1237 0x4111354
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1238 0x4111358
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1239 0x411135C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1240 0x4111360
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1241 0x4111364
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1242 0x4111368
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1243 0x411136C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1244 0x4111370
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1245 0x4111374
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1246 0x4111378
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1247 0x411137C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1248 0x4111380
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1249 0x4111384
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1250 0x4111388
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1251 0x411138C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1252 0x4111390
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1253 0x4111394
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1254 0x4111398
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1255 0x411139C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1256 0x41113A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1257 0x41113A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1258 0x41113A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1259 0x41113AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1260 0x41113B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1261 0x41113B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1262 0x41113B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1263 0x41113BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1264 0x41113C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1265 0x41113C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1266 0x41113C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1267 0x41113CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1268 0x41113D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1269 0x41113D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1270 0x41113D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1271 0x41113DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1272 0x41113E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1273 0x41113E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1274 0x41113E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1275 0x41113EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1276 0x41113F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1277 0x41113F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1278 0x41113F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1279 0x41113FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1280 0x4111400
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1281 0x4111404
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1282 0x4111408
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1283 0x411140C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1284 0x4111410
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1285 0x4111414
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1286 0x4111418
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1287 0x411141C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1288 0x4111420
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1289 0x4111424
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1290 0x4111428
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1291 0x411142C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1292 0x4111430
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1293 0x4111434
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1294 0x4111438
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1295 0x411143C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1296 0x4111440
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1297 0x4111444
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1298 0x4111448
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1299 0x411144C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1300 0x4111450
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1301 0x4111454
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1302 0x4111458
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1303 0x411145C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1304 0x4111460
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1305 0x4111464
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1306 0x4111468
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1307 0x411146C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1308 0x4111470
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1309 0x4111474
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1310 0x4111478
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1311 0x411147C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1312 0x4111480
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1313 0x4111484
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1314 0x4111488
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1315 0x411148C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1316 0x4111490
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1317 0x4111494
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1318 0x4111498
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1319 0x411149C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1320 0x41114A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1321 0x41114A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1322 0x41114A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1323 0x41114AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1324 0x41114B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1325 0x41114B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1326 0x41114B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1327 0x41114BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1328 0x41114C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1329 0x41114C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1330 0x41114C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1331 0x41114CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1332 0x41114D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1333 0x41114D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1334 0x41114D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1335 0x41114DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1336 0x41114E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1337 0x41114E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1338 0x41114E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1339 0x41114EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1340 0x41114F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1341 0x41114F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1342 0x41114F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1343 0x41114FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1344 0x4111500
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1345 0x4111504
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1346 0x4111508
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1347 0x411150C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1348 0x4111510
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1349 0x4111514
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1350 0x4111518
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1351 0x411151C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1352 0x4111520
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1353 0x4111524
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1354 0x4111528
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1355 0x411152C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1356 0x4111530
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1357 0x4111534
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1358 0x4111538
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1359 0x411153C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1360 0x4111540
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1361 0x4111544
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1362 0x4111548
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1363 0x411154C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1364 0x4111550
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1365 0x4111554
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1366 0x4111558
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1367 0x411155C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1368 0x4111560
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1369 0x4111564
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1370 0x4111568
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1371 0x411156C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1372 0x4111570
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1373 0x4111574
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1374 0x4111578
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1375 0x411157C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1376 0x4111580
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1377 0x4111584
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1378 0x4111588
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1379 0x411158C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1380 0x4111590
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1381 0x4111594
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1382 0x4111598
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1383 0x411159C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1384 0x41115A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1385 0x41115A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1386 0x41115A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1387 0x41115AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1388 0x41115B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1389 0x41115B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1390 0x41115B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1391 0x41115BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1392 0x41115C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1393 0x41115C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1394 0x41115C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1395 0x41115CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1396 0x41115D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1397 0x41115D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1398 0x41115D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1399 0x41115DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1400 0x41115E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1401 0x41115E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1402 0x41115E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1403 0x41115EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1404 0x41115F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1405 0x41115F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1406 0x41115F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1407 0x41115FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1408 0x4111600
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1409 0x4111604
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1410 0x4111608
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1411 0x411160C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1412 0x4111610
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1413 0x4111614
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1414 0x4111618
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1415 0x411161C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1416 0x4111620
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1417 0x4111624
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1418 0x4111628
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1419 0x411162C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1420 0x4111630
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1421 0x4111634
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1422 0x4111638
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1423 0x411163C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1424 0x4111640
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1425 0x4111644
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1426 0x4111648
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1427 0x411164C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1428 0x4111650
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1429 0x4111654
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1430 0x4111658
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1431 0x411165C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1432 0x4111660
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1433 0x4111664
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1434 0x4111668
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1435 0x411166C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1436 0x4111670
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1437 0x4111674
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1438 0x4111678
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1439 0x411167C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1440 0x4111680
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1441 0x4111684
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1442 0x4111688
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1443 0x411168C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1444 0x4111690
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1445 0x4111694
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1446 0x4111698
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1447 0x411169C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1448 0x41116A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1449 0x41116A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1450 0x41116A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1451 0x41116AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1452 0x41116B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1453 0x41116B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1454 0x41116B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1455 0x41116BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1456 0x41116C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1457 0x41116C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1458 0x41116C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1459 0x41116CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1460 0x41116D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1461 0x41116D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1462 0x41116D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1463 0x41116DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1464 0x41116E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1465 0x41116E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1466 0x41116E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1467 0x41116EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1468 0x41116F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1469 0x41116F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1470 0x41116F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1471 0x41116FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1472 0x4111700
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1473 0x4111704
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1474 0x4111708
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1475 0x411170C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1476 0x4111710
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1477 0x4111714
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1478 0x4111718
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1479 0x411171C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1480 0x4111720
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1481 0x4111724
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1482 0x4111728
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1483 0x411172C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1484 0x4111730
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1485 0x4111734
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1486 0x4111738
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1487 0x411173C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1488 0x4111740
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1489 0x4111744
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1490 0x4111748
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1491 0x411174C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1492 0x4111750
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1493 0x4111754
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1494 0x4111758
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1495 0x411175C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1496 0x4111760
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1497 0x4111764
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1498 0x4111768
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1499 0x411176C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1500 0x4111770
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1501 0x4111774
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1502 0x4111778
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1503 0x411177C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1504 0x4111780
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1505 0x4111784
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1506 0x4111788
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1507 0x411178C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1508 0x4111790
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1509 0x4111794
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1510 0x4111798
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1511 0x411179C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1512 0x41117A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1513 0x41117A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1514 0x41117A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1515 0x41117AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1516 0x41117B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1517 0x41117B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1518 0x41117B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1519 0x41117BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1520 0x41117C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1521 0x41117C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1522 0x41117C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1523 0x41117CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1524 0x41117D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1525 0x41117D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1526 0x41117D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1527 0x41117DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1528 0x41117E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1529 0x41117E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1530 0x41117E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1531 0x41117EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1532 0x41117F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1533 0x41117F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1534 0x41117F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1535 0x41117FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1536 0x4111800
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1537 0x4111804
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1538 0x4111808
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1539 0x411180C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1540 0x4111810
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1541 0x4111814
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1542 0x4111818
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1543 0x411181C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1544 0x4111820
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1545 0x4111824
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1546 0x4111828
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1547 0x411182C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1548 0x4111830
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1549 0x4111834
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1550 0x4111838
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1551 0x411183C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1552 0x4111840
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1553 0x4111844
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1554 0x4111848
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1555 0x411184C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1556 0x4111850
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1557 0x4111854
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1558 0x4111858
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1559 0x411185C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1560 0x4111860
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1561 0x4111864
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1562 0x4111868
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1563 0x411186C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1564 0x4111870
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1565 0x4111874
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1566 0x4111878
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1567 0x411187C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1568 0x4111880
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1569 0x4111884
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1570 0x4111888
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1571 0x411188C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1572 0x4111890
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1573 0x4111894
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1574 0x4111898
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1575 0x411189C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1576 0x41118A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1577 0x41118A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1578 0x41118A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1579 0x41118AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1580 0x41118B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1581 0x41118B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1582 0x41118B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1583 0x41118BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1584 0x41118C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1585 0x41118C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1586 0x41118C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1587 0x41118CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1588 0x41118D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1589 0x41118D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1590 0x41118D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1591 0x41118DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1592 0x41118E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1593 0x41118E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1594 0x41118E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1595 0x41118EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1596 0x41118F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1597 0x41118F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1598 0x41118F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1599 0x41118FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1600 0x4111900
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1601 0x4111904
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1602 0x4111908
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1603 0x411190C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1604 0x4111910
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1605 0x4111914
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1606 0x4111918
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1607 0x411191C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1608 0x4111920
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1609 0x4111924
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1610 0x4111928
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1611 0x411192C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1612 0x4111930
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1613 0x4111934
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1614 0x4111938
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1615 0x411193C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1616 0x4111940
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1617 0x4111944
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1618 0x4111948
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1619 0x411194C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1620 0x4111950
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1621 0x4111954
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1622 0x4111958
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1623 0x411195C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1624 0x4111960
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1625 0x4111964
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1626 0x4111968
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1627 0x411196C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1628 0x4111970
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1629 0x4111974
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1630 0x4111978
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1631 0x411197C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1632 0x4111980
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1633 0x4111984
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1634 0x4111988
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1635 0x411198C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1636 0x4111990
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1637 0x4111994
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1638 0x4111998
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1639 0x411199C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1640 0x41119A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1641 0x41119A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1642 0x41119A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1643 0x41119AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1644 0x41119B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1645 0x41119B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1646 0x41119B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1647 0x41119BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1648 0x41119C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1649 0x41119C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1650 0x41119C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1651 0x41119CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1652 0x41119D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1653 0x41119D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1654 0x41119D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1655 0x41119DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1656 0x41119E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1657 0x41119E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1658 0x41119E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1659 0x41119EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1660 0x41119F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1661 0x41119F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1662 0x41119F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1663 0x41119FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1664 0x4111A00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1665 0x4111A04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1666 0x4111A08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1667 0x4111A0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1668 0x4111A10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1669 0x4111A14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1670 0x4111A18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1671 0x4111A1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1672 0x4111A20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1673 0x4111A24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1674 0x4111A28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1675 0x4111A2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1676 0x4111A30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1677 0x4111A34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1678 0x4111A38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1679 0x4111A3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1680 0x4111A40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1681 0x4111A44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1682 0x4111A48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1683 0x4111A4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1684 0x4111A50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1685 0x4111A54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1686 0x4111A58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1687 0x4111A5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1688 0x4111A60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1689 0x4111A64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1690 0x4111A68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1691 0x4111A6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1692 0x4111A70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1693 0x4111A74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1694 0x4111A78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1695 0x4111A7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1696 0x4111A80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1697 0x4111A84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1698 0x4111A88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1699 0x4111A8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1700 0x4111A90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1701 0x4111A94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1702 0x4111A98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1703 0x4111A9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1704 0x4111AA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1705 0x4111AA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1706 0x4111AA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1707 0x4111AAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1708 0x4111AB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1709 0x4111AB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1710 0x4111AB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1711 0x4111ABC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1712 0x4111AC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1713 0x4111AC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1714 0x4111AC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1715 0x4111ACC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1716 0x4111AD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1717 0x4111AD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1718 0x4111AD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1719 0x4111ADC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1720 0x4111AE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1721 0x4111AE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1722 0x4111AE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1723 0x4111AEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1724 0x4111AF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1725 0x4111AF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1726 0x4111AF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1727 0x4111AFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1728 0x4111B00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1729 0x4111B04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1730 0x4111B08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1731 0x4111B0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1732 0x4111B10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1733 0x4111B14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1734 0x4111B18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1735 0x4111B1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1736 0x4111B20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1737 0x4111B24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1738 0x4111B28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1739 0x4111B2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1740 0x4111B30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1741 0x4111B34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1742 0x4111B38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1743 0x4111B3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1744 0x4111B40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1745 0x4111B44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1746 0x4111B48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1747 0x4111B4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1748 0x4111B50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1749 0x4111B54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1750 0x4111B58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1751 0x4111B5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1752 0x4111B60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1753 0x4111B64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1754 0x4111B68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1755 0x4111B6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1756 0x4111B70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1757 0x4111B74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1758 0x4111B78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1759 0x4111B7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1760 0x4111B80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1761 0x4111B84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1762 0x4111B88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1763 0x4111B8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1764 0x4111B90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1765 0x4111B94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1766 0x4111B98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1767 0x4111B9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1768 0x4111BA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1769 0x4111BA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1770 0x4111BA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1771 0x4111BAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1772 0x4111BB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1773 0x4111BB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1774 0x4111BB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1775 0x4111BBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1776 0x4111BC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1777 0x4111BC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1778 0x4111BC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1779 0x4111BCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1780 0x4111BD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1781 0x4111BD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1782 0x4111BD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1783 0x4111BDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1784 0x4111BE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1785 0x4111BE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1786 0x4111BE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1787 0x4111BEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1788 0x4111BF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1789 0x4111BF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1790 0x4111BF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1791 0x4111BFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1792 0x4111C00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1793 0x4111C04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1794 0x4111C08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1795 0x4111C0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1796 0x4111C10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1797 0x4111C14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1798 0x4111C18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1799 0x4111C1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1800 0x4111C20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1801 0x4111C24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1802 0x4111C28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1803 0x4111C2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1804 0x4111C30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1805 0x4111C34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1806 0x4111C38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1807 0x4111C3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1808 0x4111C40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1809 0x4111C44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1810 0x4111C48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1811 0x4111C4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1812 0x4111C50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1813 0x4111C54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1814 0x4111C58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1815 0x4111C5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1816 0x4111C60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1817 0x4111C64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1818 0x4111C68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1819 0x4111C6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1820 0x4111C70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1821 0x4111C74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1822 0x4111C78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1823 0x4111C7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1824 0x4111C80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1825 0x4111C84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1826 0x4111C88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1827 0x4111C8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1828 0x4111C90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1829 0x4111C94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1830 0x4111C98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1831 0x4111C9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1832 0x4111CA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1833 0x4111CA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1834 0x4111CA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1835 0x4111CAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1836 0x4111CB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1837 0x4111CB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1838 0x4111CB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1839 0x4111CBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1840 0x4111CC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1841 0x4111CC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1842 0x4111CC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1843 0x4111CCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1844 0x4111CD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1845 0x4111CD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1846 0x4111CD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1847 0x4111CDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1848 0x4111CE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1849 0x4111CE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1850 0x4111CE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1851 0x4111CEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1852 0x4111CF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1853 0x4111CF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1854 0x4111CF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1855 0x4111CFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1856 0x4111D00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1857 0x4111D04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1858 0x4111D08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1859 0x4111D0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1860 0x4111D10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1861 0x4111D14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1862 0x4111D18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1863 0x4111D1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1864 0x4111D20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1865 0x4111D24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1866 0x4111D28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1867 0x4111D2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1868 0x4111D30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1869 0x4111D34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1870 0x4111D38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1871 0x4111D3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1872 0x4111D40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1873 0x4111D44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1874 0x4111D48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1875 0x4111D4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1876 0x4111D50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1877 0x4111D54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1878 0x4111D58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1879 0x4111D5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1880 0x4111D60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1881 0x4111D64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1882 0x4111D68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1883 0x4111D6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1884 0x4111D70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1885 0x4111D74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1886 0x4111D78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1887 0x4111D7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1888 0x4111D80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1889 0x4111D84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1890 0x4111D88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1891 0x4111D8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1892 0x4111D90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1893 0x4111D94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1894 0x4111D98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1895 0x4111D9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1896 0x4111DA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1897 0x4111DA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1898 0x4111DA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1899 0x4111DAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1900 0x4111DB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1901 0x4111DB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1902 0x4111DB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1903 0x4111DBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1904 0x4111DC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1905 0x4111DC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1906 0x4111DC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1907 0x4111DCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1908 0x4111DD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1909 0x4111DD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1910 0x4111DD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1911 0x4111DDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1912 0x4111DE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1913 0x4111DE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1914 0x4111DE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1915 0x4111DEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1916 0x4111DF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1917 0x4111DF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1918 0x4111DF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1919 0x4111DFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1920 0x4111E00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1921 0x4111E04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1922 0x4111E08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1923 0x4111E0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1924 0x4111E10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1925 0x4111E14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1926 0x4111E18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1927 0x4111E1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1928 0x4111E20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1929 0x4111E24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1930 0x4111E28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1931 0x4111E2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1932 0x4111E30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1933 0x4111E34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1934 0x4111E38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1935 0x4111E3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1936 0x4111E40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1937 0x4111E44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1938 0x4111E48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1939 0x4111E4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1940 0x4111E50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1941 0x4111E54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1942 0x4111E58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1943 0x4111E5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1944 0x4111E60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1945 0x4111E64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1946 0x4111E68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1947 0x4111E6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1948 0x4111E70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1949 0x4111E74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1950 0x4111E78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1951 0x4111E7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1952 0x4111E80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1953 0x4111E84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1954 0x4111E88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1955 0x4111E8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1956 0x4111E90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1957 0x4111E94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1958 0x4111E98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1959 0x4111E9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1960 0x4111EA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1961 0x4111EA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1962 0x4111EA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1963 0x4111EAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1964 0x4111EB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1965 0x4111EB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1966 0x4111EB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1967 0x4111EBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1968 0x4111EC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1969 0x4111EC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1970 0x4111EC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1971 0x4111ECC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1972 0x4111ED0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1973 0x4111ED4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1974 0x4111ED8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1975 0x4111EDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1976 0x4111EE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1977 0x4111EE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1978 0x4111EE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1979 0x4111EEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1980 0x4111EF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1981 0x4111EF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1982 0x4111EF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1983 0x4111EFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1984 0x4111F00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1985 0x4111F04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1986 0x4111F08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1987 0x4111F0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1988 0x4111F10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1989 0x4111F14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1990 0x4111F18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1991 0x4111F1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1992 0x4111F20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1993 0x4111F24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1994 0x4111F28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1995 0x4111F2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1996 0x4111F30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1997 0x4111F34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1998 0x4111F38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1999 0x4111F3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2000 0x4111F40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2001 0x4111F44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2002 0x4111F48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2003 0x4111F4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2004 0x4111F50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2005 0x4111F54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2006 0x4111F58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2007 0x4111F5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2008 0x4111F60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2009 0x4111F64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2010 0x4111F68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2011 0x4111F6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2012 0x4111F70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2013 0x4111F74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2014 0x4111F78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2015 0x4111F7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2016 0x4111F80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2017 0x4111F84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2018 0x4111F88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2019 0x4111F8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2020 0x4111F90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2021 0x4111F94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2022 0x4111F98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2023 0x4111F9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2024 0x4111FA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2025 0x4111FA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2026 0x4111FA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2027 0x4111FAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2028 0x4111FB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2029 0x4111FB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2030 0x4111FB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2031 0x4111FBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2032 0x4111FC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2033 0x4111FC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2034 0x4111FC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2035 0x4111FCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2036 0x4111FD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2037 0x4111FD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2038 0x4111FD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2039 0x4111FDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2040 0x4111FE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2041 0x4111FE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2042 0x4111FE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2043 0x4111FEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2044 0x4111FF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2045 0x4111FF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2046 0x4111FF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2047 0x4111FFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_0 0x4112000
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1 0x4112004
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2 0x4112008
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_3 0x411200C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_4 0x4112010
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_5 0x4112014
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_6 0x4112018
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_7 0x411201C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_8 0x4112020
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_9 0x4112024
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_10 0x4112028
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_11 0x411202C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_12 0x4112030
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_13 0x4112034
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_14 0x4112038
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_15 0x411203C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_16 0x4112040
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_17 0x4112044
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_18 0x4112048
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_19 0x411204C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_20 0x4112050
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_21 0x4112054
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_22 0x4112058
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_23 0x411205C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_24 0x4112060
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_25 0x4112064
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_26 0x4112068
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_27 0x411206C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_28 0x4112070
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_29 0x4112074
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_30 0x4112078
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_31 0x411207C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_32 0x4112080
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_33 0x4112084
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_34 0x4112088
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_35 0x411208C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_36 0x4112090
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_37 0x4112094
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_38 0x4112098
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_39 0x411209C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_40 0x41120A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_41 0x41120A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_42 0x41120A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_43 0x41120AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_44 0x41120B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_45 0x41120B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_46 0x41120B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_47 0x41120BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_48 0x41120C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_49 0x41120C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_50 0x41120C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_51 0x41120CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_52 0x41120D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_53 0x41120D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_54 0x41120D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_55 0x41120DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_56 0x41120E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_57 0x41120E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_58 0x41120E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_59 0x41120EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_60 0x41120F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_61 0x41120F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_62 0x41120F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_63 0x41120FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_64 0x4112100
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_65 0x4112104
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_66 0x4112108
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_67 0x411210C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_68 0x4112110
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_69 0x4112114
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_70 0x4112118
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_71 0x411211C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_72 0x4112120
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_73 0x4112124
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_74 0x4112128
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_75 0x411212C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_76 0x4112130
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_77 0x4112134
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_78 0x4112138
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_79 0x411213C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_80 0x4112140
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_81 0x4112144
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_82 0x4112148
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_83 0x411214C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_84 0x4112150
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_85 0x4112154
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_86 0x4112158
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_87 0x411215C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_88 0x4112160
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_89 0x4112164
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_90 0x4112168
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_91 0x411216C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_92 0x4112170
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_93 0x4112174
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_94 0x4112178
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_95 0x411217C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_96 0x4112180
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_97 0x4112184
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_98 0x4112188
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_99 0x411218C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_100 0x4112190
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_101 0x4112194
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_102 0x4112198
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_103 0x411219C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_104 0x41121A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_105 0x41121A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_106 0x41121A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_107 0x41121AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_108 0x41121B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_109 0x41121B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_110 0x41121B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_111 0x41121BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_112 0x41121C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_113 0x41121C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_114 0x41121C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_115 0x41121CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_116 0x41121D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_117 0x41121D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_118 0x41121D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_119 0x41121DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_120 0x41121E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_121 0x41121E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_122 0x41121E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_123 0x41121EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_124 0x41121F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_125 0x41121F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_126 0x41121F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_127 0x41121FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_128 0x4112200
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_129 0x4112204
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_130 0x4112208
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_131 0x411220C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_132 0x4112210
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_133 0x4112214
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_134 0x4112218
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_135 0x411221C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_136 0x4112220
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_137 0x4112224
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_138 0x4112228
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_139 0x411222C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_140 0x4112230
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_141 0x4112234
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_142 0x4112238
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_143 0x411223C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_144 0x4112240
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_145 0x4112244
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_146 0x4112248
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_147 0x411224C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_148 0x4112250
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_149 0x4112254
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_150 0x4112258
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_151 0x411225C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_152 0x4112260
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_153 0x4112264
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_154 0x4112268
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_155 0x411226C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_156 0x4112270
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_157 0x4112274
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_158 0x4112278
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_159 0x411227C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_160 0x4112280
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_161 0x4112284
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_162 0x4112288
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_163 0x411228C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_164 0x4112290
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_165 0x4112294
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_166 0x4112298
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_167 0x411229C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_168 0x41122A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_169 0x41122A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_170 0x41122A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_171 0x41122AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_172 0x41122B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_173 0x41122B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_174 0x41122B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_175 0x41122BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_176 0x41122C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_177 0x41122C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_178 0x41122C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_179 0x41122CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_180 0x41122D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_181 0x41122D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_182 0x41122D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_183 0x41122DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_184 0x41122E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_185 0x41122E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_186 0x41122E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_187 0x41122EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_188 0x41122F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_189 0x41122F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_190 0x41122F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_191 0x41122FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_192 0x4112300
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_193 0x4112304
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_194 0x4112308
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_195 0x411230C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_196 0x4112310
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_197 0x4112314
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_198 0x4112318
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_199 0x411231C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_200 0x4112320
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_201 0x4112324
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_202 0x4112328
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_203 0x411232C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_204 0x4112330
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_205 0x4112334
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_206 0x4112338
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_207 0x411233C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_208 0x4112340
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_209 0x4112344
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_210 0x4112348
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_211 0x411234C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_212 0x4112350
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_213 0x4112354
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_214 0x4112358
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_215 0x411235C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_216 0x4112360
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_217 0x4112364
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_218 0x4112368
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_219 0x411236C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_220 0x4112370
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_221 0x4112374
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_222 0x4112378
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_223 0x411237C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_224 0x4112380
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_225 0x4112384
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_226 0x4112388
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_227 0x411238C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_228 0x4112390
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_229 0x4112394
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_230 0x4112398
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_231 0x411239C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_232 0x41123A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_233 0x41123A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_234 0x41123A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_235 0x41123AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_236 0x41123B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_237 0x41123B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_238 0x41123B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_239 0x41123BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_240 0x41123C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_241 0x41123C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_242 0x41123C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_243 0x41123CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_244 0x41123D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_245 0x41123D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_246 0x41123D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_247 0x41123DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_248 0x41123E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_249 0x41123E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_250 0x41123E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_251 0x41123EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_252 0x41123F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_253 0x41123F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_254 0x41123F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_255 0x41123FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_256 0x4112400
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_257 0x4112404
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_258 0x4112408
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_259 0x411240C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_260 0x4112410
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_261 0x4112414
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_262 0x4112418
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_263 0x411241C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_264 0x4112420
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_265 0x4112424
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_266 0x4112428
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_267 0x411242C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_268 0x4112430
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_269 0x4112434
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_270 0x4112438
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_271 0x411243C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_272 0x4112440
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_273 0x4112444
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_274 0x4112448
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_275 0x411244C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_276 0x4112450
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_277 0x4112454
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_278 0x4112458
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_279 0x411245C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_280 0x4112460
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_281 0x4112464
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_282 0x4112468
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_283 0x411246C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_284 0x4112470
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_285 0x4112474
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_286 0x4112478
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_287 0x411247C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_288 0x4112480
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_289 0x4112484
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_290 0x4112488
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_291 0x411248C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_292 0x4112490
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_293 0x4112494
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_294 0x4112498
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_295 0x411249C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_296 0x41124A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_297 0x41124A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_298 0x41124A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_299 0x41124AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_300 0x41124B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_301 0x41124B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_302 0x41124B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_303 0x41124BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_304 0x41124C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_305 0x41124C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_306 0x41124C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_307 0x41124CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_308 0x41124D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_309 0x41124D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_310 0x41124D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_311 0x41124DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_312 0x41124E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_313 0x41124E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_314 0x41124E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_315 0x41124EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_316 0x41124F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_317 0x41124F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_318 0x41124F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_319 0x41124FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_320 0x4112500
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_321 0x4112504
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_322 0x4112508
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_323 0x411250C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_324 0x4112510
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_325 0x4112514
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_326 0x4112518
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_327 0x411251C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_328 0x4112520
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_329 0x4112524
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_330 0x4112528
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_331 0x411252C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_332 0x4112530
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_333 0x4112534
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_334 0x4112538
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_335 0x411253C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_336 0x4112540
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_337 0x4112544
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_338 0x4112548
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_339 0x411254C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_340 0x4112550
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_341 0x4112554
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_342 0x4112558
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_343 0x411255C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_344 0x4112560
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_345 0x4112564
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_346 0x4112568
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_347 0x411256C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_348 0x4112570
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_349 0x4112574
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_350 0x4112578
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_351 0x411257C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_352 0x4112580
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_353 0x4112584
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_354 0x4112588
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_355 0x411258C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_356 0x4112590
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_357 0x4112594
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_358 0x4112598
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_359 0x411259C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_360 0x41125A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_361 0x41125A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_362 0x41125A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_363 0x41125AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_364 0x41125B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_365 0x41125B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_366 0x41125B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_367 0x41125BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_368 0x41125C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_369 0x41125C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_370 0x41125C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_371 0x41125CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_372 0x41125D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_373 0x41125D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_374 0x41125D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_375 0x41125DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_376 0x41125E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_377 0x41125E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_378 0x41125E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_379 0x41125EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_380 0x41125F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_381 0x41125F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_382 0x41125F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_383 0x41125FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_384 0x4112600
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_385 0x4112604
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_386 0x4112608
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_387 0x411260C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_388 0x4112610
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_389 0x4112614
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_390 0x4112618
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_391 0x411261C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_392 0x4112620
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_393 0x4112624
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_394 0x4112628
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_395 0x411262C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_396 0x4112630
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_397 0x4112634
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_398 0x4112638
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_399 0x411263C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_400 0x4112640
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_401 0x4112644
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_402 0x4112648
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_403 0x411264C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_404 0x4112650
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_405 0x4112654
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_406 0x4112658
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_407 0x411265C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_408 0x4112660
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_409 0x4112664
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_410 0x4112668
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_411 0x411266C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_412 0x4112670
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_413 0x4112674
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_414 0x4112678
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_415 0x411267C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_416 0x4112680
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_417 0x4112684
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_418 0x4112688
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_419 0x411268C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_420 0x4112690
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_421 0x4112694
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_422 0x4112698
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_423 0x411269C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_424 0x41126A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_425 0x41126A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_426 0x41126A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_427 0x41126AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_428 0x41126B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_429 0x41126B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_430 0x41126B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_431 0x41126BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_432 0x41126C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_433 0x41126C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_434 0x41126C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_435 0x41126CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_436 0x41126D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_437 0x41126D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_438 0x41126D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_439 0x41126DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_440 0x41126E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_441 0x41126E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_442 0x41126E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_443 0x41126EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_444 0x41126F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_445 0x41126F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_446 0x41126F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_447 0x41126FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_448 0x4112700
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_449 0x4112704
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_450 0x4112708
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_451 0x411270C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_452 0x4112710
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_453 0x4112714
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_454 0x4112718
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_455 0x411271C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_456 0x4112720
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_457 0x4112724
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_458 0x4112728
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_459 0x411272C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_460 0x4112730
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_461 0x4112734
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_462 0x4112738
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_463 0x411273C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_464 0x4112740
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_465 0x4112744
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_466 0x4112748
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_467 0x411274C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_468 0x4112750
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_469 0x4112754
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_470 0x4112758
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_471 0x411275C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_472 0x4112760
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_473 0x4112764
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_474 0x4112768
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_475 0x411276C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_476 0x4112770
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_477 0x4112774
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_478 0x4112778
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_479 0x411277C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_480 0x4112780
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_481 0x4112784
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_482 0x4112788
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_483 0x411278C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_484 0x4112790
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_485 0x4112794
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_486 0x4112798
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_487 0x411279C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_488 0x41127A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_489 0x41127A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_490 0x41127A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_491 0x41127AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_492 0x41127B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_493 0x41127B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_494 0x41127B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_495 0x41127BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_496 0x41127C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_497 0x41127C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_498 0x41127C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_499 0x41127CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_500 0x41127D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_501 0x41127D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_502 0x41127D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_503 0x41127DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_504 0x41127E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_505 0x41127E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_506 0x41127E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_507 0x41127EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_508 0x41127F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_509 0x41127F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_510 0x41127F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_511 0x41127FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_512 0x4112800
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_513 0x4112804
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_514 0x4112808
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_515 0x411280C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_516 0x4112810
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_517 0x4112814
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_518 0x4112818
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_519 0x411281C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_520 0x4112820
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_521 0x4112824
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_522 0x4112828
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_523 0x411282C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_524 0x4112830
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_525 0x4112834
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_526 0x4112838
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_527 0x411283C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_528 0x4112840
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_529 0x4112844
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_530 0x4112848
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_531 0x411284C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_532 0x4112850
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_533 0x4112854
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_534 0x4112858
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_535 0x411285C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_536 0x4112860
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_537 0x4112864
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_538 0x4112868
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_539 0x411286C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_540 0x4112870
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_541 0x4112874
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_542 0x4112878
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_543 0x411287C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_544 0x4112880
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_545 0x4112884
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_546 0x4112888
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_547 0x411288C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_548 0x4112890
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_549 0x4112894
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_550 0x4112898
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_551 0x411289C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_552 0x41128A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_553 0x41128A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_554 0x41128A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_555 0x41128AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_556 0x41128B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_557 0x41128B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_558 0x41128B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_559 0x41128BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_560 0x41128C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_561 0x41128C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_562 0x41128C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_563 0x41128CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_564 0x41128D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_565 0x41128D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_566 0x41128D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_567 0x41128DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_568 0x41128E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_569 0x41128E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_570 0x41128E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_571 0x41128EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_572 0x41128F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_573 0x41128F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_574 0x41128F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_575 0x41128FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_576 0x4112900
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_577 0x4112904
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_578 0x4112908
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_579 0x411290C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_580 0x4112910
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_581 0x4112914
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_582 0x4112918
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_583 0x411291C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_584 0x4112920
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_585 0x4112924
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_586 0x4112928
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_587 0x411292C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_588 0x4112930
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_589 0x4112934
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_590 0x4112938
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_591 0x411293C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_592 0x4112940
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_593 0x4112944
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_594 0x4112948
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_595 0x411294C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_596 0x4112950
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_597 0x4112954
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_598 0x4112958
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_599 0x411295C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_600 0x4112960
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_601 0x4112964
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_602 0x4112968
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_603 0x411296C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_604 0x4112970
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_605 0x4112974
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_606 0x4112978
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_607 0x411297C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_608 0x4112980
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_609 0x4112984
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_610 0x4112988
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_611 0x411298C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_612 0x4112990
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_613 0x4112994
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_614 0x4112998
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_615 0x411299C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_616 0x41129A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_617 0x41129A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_618 0x41129A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_619 0x41129AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_620 0x41129B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_621 0x41129B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_622 0x41129B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_623 0x41129BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_624 0x41129C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_625 0x41129C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_626 0x41129C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_627 0x41129CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_628 0x41129D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_629 0x41129D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_630 0x41129D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_631 0x41129DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_632 0x41129E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_633 0x41129E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_634 0x41129E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_635 0x41129EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_636 0x41129F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_637 0x41129F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_638 0x41129F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_639 0x41129FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_640 0x4112A00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_641 0x4112A04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_642 0x4112A08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_643 0x4112A0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_644 0x4112A10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_645 0x4112A14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_646 0x4112A18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_647 0x4112A1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_648 0x4112A20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_649 0x4112A24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_650 0x4112A28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_651 0x4112A2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_652 0x4112A30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_653 0x4112A34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_654 0x4112A38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_655 0x4112A3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_656 0x4112A40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_657 0x4112A44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_658 0x4112A48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_659 0x4112A4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_660 0x4112A50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_661 0x4112A54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_662 0x4112A58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_663 0x4112A5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_664 0x4112A60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_665 0x4112A64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_666 0x4112A68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_667 0x4112A6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_668 0x4112A70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_669 0x4112A74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_670 0x4112A78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_671 0x4112A7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_672 0x4112A80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_673 0x4112A84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_674 0x4112A88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_675 0x4112A8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_676 0x4112A90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_677 0x4112A94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_678 0x4112A98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_679 0x4112A9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_680 0x4112AA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_681 0x4112AA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_682 0x4112AA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_683 0x4112AAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_684 0x4112AB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_685 0x4112AB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_686 0x4112AB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_687 0x4112ABC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_688 0x4112AC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_689 0x4112AC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_690 0x4112AC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_691 0x4112ACC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_692 0x4112AD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_693 0x4112AD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_694 0x4112AD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_695 0x4112ADC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_696 0x4112AE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_697 0x4112AE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_698 0x4112AE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_699 0x4112AEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_700 0x4112AF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_701 0x4112AF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_702 0x4112AF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_703 0x4112AFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_704 0x4112B00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_705 0x4112B04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_706 0x4112B08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_707 0x4112B0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_708 0x4112B10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_709 0x4112B14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_710 0x4112B18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_711 0x4112B1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_712 0x4112B20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_713 0x4112B24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_714 0x4112B28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_715 0x4112B2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_716 0x4112B30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_717 0x4112B34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_718 0x4112B38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_719 0x4112B3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_720 0x4112B40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_721 0x4112B44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_722 0x4112B48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_723 0x4112B4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_724 0x4112B50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_725 0x4112B54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_726 0x4112B58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_727 0x4112B5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_728 0x4112B60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_729 0x4112B64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_730 0x4112B68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_731 0x4112B6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_732 0x4112B70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_733 0x4112B74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_734 0x4112B78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_735 0x4112B7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_736 0x4112B80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_737 0x4112B84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_738 0x4112B88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_739 0x4112B8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_740 0x4112B90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_741 0x4112B94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_742 0x4112B98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_743 0x4112B9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_744 0x4112BA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_745 0x4112BA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_746 0x4112BA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_747 0x4112BAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_748 0x4112BB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_749 0x4112BB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_750 0x4112BB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_751 0x4112BBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_752 0x4112BC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_753 0x4112BC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_754 0x4112BC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_755 0x4112BCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_756 0x4112BD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_757 0x4112BD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_758 0x4112BD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_759 0x4112BDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_760 0x4112BE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_761 0x4112BE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_762 0x4112BE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_763 0x4112BEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_764 0x4112BF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_765 0x4112BF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_766 0x4112BF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_767 0x4112BFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_768 0x4112C00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_769 0x4112C04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_770 0x4112C08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_771 0x4112C0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_772 0x4112C10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_773 0x4112C14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_774 0x4112C18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_775 0x4112C1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_776 0x4112C20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_777 0x4112C24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_778 0x4112C28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_779 0x4112C2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_780 0x4112C30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_781 0x4112C34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_782 0x4112C38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_783 0x4112C3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_784 0x4112C40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_785 0x4112C44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_786 0x4112C48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_787 0x4112C4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_788 0x4112C50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_789 0x4112C54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_790 0x4112C58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_791 0x4112C5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_792 0x4112C60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_793 0x4112C64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_794 0x4112C68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_795 0x4112C6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_796 0x4112C70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_797 0x4112C74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_798 0x4112C78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_799 0x4112C7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_800 0x4112C80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_801 0x4112C84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_802 0x4112C88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_803 0x4112C8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_804 0x4112C90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_805 0x4112C94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_806 0x4112C98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_807 0x4112C9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_808 0x4112CA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_809 0x4112CA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_810 0x4112CA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_811 0x4112CAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_812 0x4112CB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_813 0x4112CB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_814 0x4112CB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_815 0x4112CBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_816 0x4112CC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_817 0x4112CC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_818 0x4112CC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_819 0x4112CCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_820 0x4112CD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_821 0x4112CD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_822 0x4112CD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_823 0x4112CDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_824 0x4112CE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_825 0x4112CE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_826 0x4112CE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_827 0x4112CEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_828 0x4112CF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_829 0x4112CF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_830 0x4112CF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_831 0x4112CFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_832 0x4112D00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_833 0x4112D04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_834 0x4112D08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_835 0x4112D0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_836 0x4112D10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_837 0x4112D14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_838 0x4112D18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_839 0x4112D1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_840 0x4112D20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_841 0x4112D24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_842 0x4112D28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_843 0x4112D2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_844 0x4112D30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_845 0x4112D34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_846 0x4112D38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_847 0x4112D3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_848 0x4112D40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_849 0x4112D44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_850 0x4112D48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_851 0x4112D4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_852 0x4112D50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_853 0x4112D54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_854 0x4112D58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_855 0x4112D5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_856 0x4112D60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_857 0x4112D64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_858 0x4112D68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_859 0x4112D6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_860 0x4112D70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_861 0x4112D74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_862 0x4112D78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_863 0x4112D7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_864 0x4112D80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_865 0x4112D84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_866 0x4112D88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_867 0x4112D8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_868 0x4112D90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_869 0x4112D94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_870 0x4112D98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_871 0x4112D9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_872 0x4112DA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_873 0x4112DA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_874 0x4112DA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_875 0x4112DAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_876 0x4112DB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_877 0x4112DB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_878 0x4112DB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_879 0x4112DBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_880 0x4112DC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_881 0x4112DC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_882 0x4112DC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_883 0x4112DCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_884 0x4112DD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_885 0x4112DD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_886 0x4112DD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_887 0x4112DDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_888 0x4112DE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_889 0x4112DE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_890 0x4112DE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_891 0x4112DEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_892 0x4112DF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_893 0x4112DF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_894 0x4112DF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_895 0x4112DFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_896 0x4112E00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_897 0x4112E04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_898 0x4112E08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_899 0x4112E0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_900 0x4112E10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_901 0x4112E14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_902 0x4112E18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_903 0x4112E1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_904 0x4112E20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_905 0x4112E24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_906 0x4112E28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_907 0x4112E2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_908 0x4112E30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_909 0x4112E34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_910 0x4112E38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_911 0x4112E3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_912 0x4112E40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_913 0x4112E44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_914 0x4112E48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_915 0x4112E4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_916 0x4112E50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_917 0x4112E54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_918 0x4112E58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_919 0x4112E5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_920 0x4112E60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_921 0x4112E64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_922 0x4112E68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_923 0x4112E6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_924 0x4112E70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_925 0x4112E74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_926 0x4112E78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_927 0x4112E7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_928 0x4112E80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_929 0x4112E84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_930 0x4112E88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_931 0x4112E8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_932 0x4112E90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_933 0x4112E94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_934 0x4112E98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_935 0x4112E9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_936 0x4112EA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_937 0x4112EA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_938 0x4112EA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_939 0x4112EAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_940 0x4112EB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_941 0x4112EB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_942 0x4112EB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_943 0x4112EBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_944 0x4112EC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_945 0x4112EC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_946 0x4112EC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_947 0x4112ECC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_948 0x4112ED0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_949 0x4112ED4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_950 0x4112ED8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_951 0x4112EDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_952 0x4112EE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_953 0x4112EE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_954 0x4112EE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_955 0x4112EEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_956 0x4112EF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_957 0x4112EF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_958 0x4112EF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_959 0x4112EFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_960 0x4112F00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_961 0x4112F04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_962 0x4112F08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_963 0x4112F0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_964 0x4112F10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_965 0x4112F14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_966 0x4112F18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_967 0x4112F1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_968 0x4112F20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_969 0x4112F24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_970 0x4112F28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_971 0x4112F2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_972 0x4112F30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_973 0x4112F34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_974 0x4112F38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_975 0x4112F3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_976 0x4112F40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_977 0x4112F44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_978 0x4112F48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_979 0x4112F4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_980 0x4112F50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_981 0x4112F54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_982 0x4112F58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_983 0x4112F5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_984 0x4112F60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_985 0x4112F64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_986 0x4112F68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_987 0x4112F6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_988 0x4112F70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_989 0x4112F74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_990 0x4112F78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_991 0x4112F7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_992 0x4112F80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_993 0x4112F84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_994 0x4112F88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_995 0x4112F8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_996 0x4112F90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_997 0x4112F94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_998 0x4112F98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_999 0x4112F9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1000 0x4112FA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1001 0x4112FA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1002 0x4112FA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1003 0x4112FAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1004 0x4112FB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1005 0x4112FB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1006 0x4112FB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1007 0x4112FBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1008 0x4112FC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1009 0x4112FC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1010 0x4112FC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1011 0x4112FCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1012 0x4112FD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1013 0x4112FD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1014 0x4112FD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1015 0x4112FDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1016 0x4112FE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1017 0x4112FE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1018 0x4112FE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1019 0x4112FEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1020 0x4112FF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1021 0x4112FF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1022 0x4112FF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1023 0x4112FFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1024 0x4113000
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1025 0x4113004
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1026 0x4113008
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1027 0x411300C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1028 0x4113010
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1029 0x4113014
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1030 0x4113018
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1031 0x411301C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1032 0x4113020
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1033 0x4113024
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1034 0x4113028
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1035 0x411302C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1036 0x4113030
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1037 0x4113034
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1038 0x4113038
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1039 0x411303C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1040 0x4113040
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1041 0x4113044
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1042 0x4113048
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1043 0x411304C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1044 0x4113050
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1045 0x4113054
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1046 0x4113058
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1047 0x411305C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1048 0x4113060
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1049 0x4113064
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1050 0x4113068
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1051 0x411306C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1052 0x4113070
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1053 0x4113074
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1054 0x4113078
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1055 0x411307C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1056 0x4113080
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1057 0x4113084
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1058 0x4113088
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1059 0x411308C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1060 0x4113090
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1061 0x4113094
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1062 0x4113098
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1063 0x411309C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1064 0x41130A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1065 0x41130A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1066 0x41130A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1067 0x41130AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1068 0x41130B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1069 0x41130B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1070 0x41130B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1071 0x41130BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1072 0x41130C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1073 0x41130C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1074 0x41130C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1075 0x41130CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1076 0x41130D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1077 0x41130D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1078 0x41130D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1079 0x41130DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1080 0x41130E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1081 0x41130E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1082 0x41130E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1083 0x41130EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1084 0x41130F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1085 0x41130F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1086 0x41130F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1087 0x41130FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1088 0x4113100
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1089 0x4113104
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1090 0x4113108
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1091 0x411310C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1092 0x4113110
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1093 0x4113114
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1094 0x4113118
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1095 0x411311C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1096 0x4113120
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1097 0x4113124
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1098 0x4113128
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1099 0x411312C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1100 0x4113130
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1101 0x4113134
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1102 0x4113138
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1103 0x411313C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1104 0x4113140
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1105 0x4113144
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1106 0x4113148
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1107 0x411314C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1108 0x4113150
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1109 0x4113154
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1110 0x4113158
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1111 0x411315C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1112 0x4113160
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1113 0x4113164
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1114 0x4113168
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1115 0x411316C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1116 0x4113170
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1117 0x4113174
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1118 0x4113178
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1119 0x411317C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1120 0x4113180
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1121 0x4113184
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1122 0x4113188
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1123 0x411318C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1124 0x4113190
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1125 0x4113194
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1126 0x4113198
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1127 0x411319C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1128 0x41131A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1129 0x41131A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1130 0x41131A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1131 0x41131AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1132 0x41131B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1133 0x41131B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1134 0x41131B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1135 0x41131BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1136 0x41131C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1137 0x41131C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1138 0x41131C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1139 0x41131CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1140 0x41131D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1141 0x41131D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1142 0x41131D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1143 0x41131DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1144 0x41131E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1145 0x41131E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1146 0x41131E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1147 0x41131EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1148 0x41131F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1149 0x41131F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1150 0x41131F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1151 0x41131FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1152 0x4113200
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1153 0x4113204
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1154 0x4113208
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1155 0x411320C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1156 0x4113210
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1157 0x4113214
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1158 0x4113218
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1159 0x411321C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1160 0x4113220
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1161 0x4113224
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1162 0x4113228
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1163 0x411322C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1164 0x4113230
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1165 0x4113234
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1166 0x4113238
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1167 0x411323C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1168 0x4113240
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1169 0x4113244
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1170 0x4113248
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1171 0x411324C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1172 0x4113250
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1173 0x4113254
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1174 0x4113258
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1175 0x411325C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1176 0x4113260
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1177 0x4113264
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1178 0x4113268
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1179 0x411326C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1180 0x4113270
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1181 0x4113274
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1182 0x4113278
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1183 0x411327C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1184 0x4113280
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1185 0x4113284
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1186 0x4113288
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1187 0x411328C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1188 0x4113290
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1189 0x4113294
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1190 0x4113298
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1191 0x411329C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1192 0x41132A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1193 0x41132A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1194 0x41132A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1195 0x41132AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1196 0x41132B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1197 0x41132B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1198 0x41132B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1199 0x41132BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1200 0x41132C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1201 0x41132C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1202 0x41132C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1203 0x41132CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1204 0x41132D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1205 0x41132D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1206 0x41132D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1207 0x41132DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1208 0x41132E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1209 0x41132E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1210 0x41132E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1211 0x41132EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1212 0x41132F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1213 0x41132F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1214 0x41132F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1215 0x41132FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1216 0x4113300
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1217 0x4113304
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1218 0x4113308
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1219 0x411330C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1220 0x4113310
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1221 0x4113314
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1222 0x4113318
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1223 0x411331C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1224 0x4113320
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1225 0x4113324
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1226 0x4113328
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1227 0x411332C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1228 0x4113330
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1229 0x4113334
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1230 0x4113338
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1231 0x411333C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1232 0x4113340
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1233 0x4113344
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1234 0x4113348
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1235 0x411334C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1236 0x4113350
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1237 0x4113354
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1238 0x4113358
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1239 0x411335C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1240 0x4113360
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1241 0x4113364
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1242 0x4113368
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1243 0x411336C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1244 0x4113370
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1245 0x4113374
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1246 0x4113378
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1247 0x411337C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1248 0x4113380
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1249 0x4113384
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1250 0x4113388
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1251 0x411338C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1252 0x4113390
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1253 0x4113394
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1254 0x4113398
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1255 0x411339C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1256 0x41133A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1257 0x41133A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1258 0x41133A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1259 0x41133AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1260 0x41133B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1261 0x41133B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1262 0x41133B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1263 0x41133BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1264 0x41133C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1265 0x41133C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1266 0x41133C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1267 0x41133CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1268 0x41133D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1269 0x41133D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1270 0x41133D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1271 0x41133DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1272 0x41133E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1273 0x41133E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1274 0x41133E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1275 0x41133EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1276 0x41133F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1277 0x41133F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1278 0x41133F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1279 0x41133FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1280 0x4113400
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1281 0x4113404
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1282 0x4113408
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1283 0x411340C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1284 0x4113410
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1285 0x4113414
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1286 0x4113418
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1287 0x411341C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1288 0x4113420
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1289 0x4113424
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1290 0x4113428
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1291 0x411342C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1292 0x4113430
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1293 0x4113434
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1294 0x4113438
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1295 0x411343C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1296 0x4113440
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1297 0x4113444
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1298 0x4113448
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1299 0x411344C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1300 0x4113450
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1301 0x4113454
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1302 0x4113458
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1303 0x411345C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1304 0x4113460
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1305 0x4113464
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1306 0x4113468
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1307 0x411346C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1308 0x4113470
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1309 0x4113474
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1310 0x4113478
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1311 0x411347C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1312 0x4113480
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1313 0x4113484
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1314 0x4113488
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1315 0x411348C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1316 0x4113490
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1317 0x4113494
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1318 0x4113498
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1319 0x411349C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1320 0x41134A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1321 0x41134A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1322 0x41134A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1323 0x41134AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1324 0x41134B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1325 0x41134B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1326 0x41134B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1327 0x41134BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1328 0x41134C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1329 0x41134C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1330 0x41134C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1331 0x41134CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1332 0x41134D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1333 0x41134D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1334 0x41134D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1335 0x41134DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1336 0x41134E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1337 0x41134E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1338 0x41134E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1339 0x41134EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1340 0x41134F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1341 0x41134F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1342 0x41134F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1343 0x41134FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1344 0x4113500
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1345 0x4113504
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1346 0x4113508
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1347 0x411350C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1348 0x4113510
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1349 0x4113514
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1350 0x4113518
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1351 0x411351C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1352 0x4113520
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1353 0x4113524
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1354 0x4113528
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1355 0x411352C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1356 0x4113530
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1357 0x4113534
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1358 0x4113538
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1359 0x411353C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1360 0x4113540
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1361 0x4113544
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1362 0x4113548
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1363 0x411354C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1364 0x4113550
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1365 0x4113554
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1366 0x4113558
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1367 0x411355C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1368 0x4113560
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1369 0x4113564
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1370 0x4113568
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1371 0x411356C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1372 0x4113570
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1373 0x4113574
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1374 0x4113578
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1375 0x411357C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1376 0x4113580
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1377 0x4113584
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1378 0x4113588
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1379 0x411358C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1380 0x4113590
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1381 0x4113594
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1382 0x4113598
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1383 0x411359C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1384 0x41135A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1385 0x41135A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1386 0x41135A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1387 0x41135AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1388 0x41135B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1389 0x41135B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1390 0x41135B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1391 0x41135BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1392 0x41135C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1393 0x41135C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1394 0x41135C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1395 0x41135CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1396 0x41135D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1397 0x41135D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1398 0x41135D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1399 0x41135DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1400 0x41135E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1401 0x41135E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1402 0x41135E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1403 0x41135EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1404 0x41135F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1405 0x41135F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1406 0x41135F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1407 0x41135FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1408 0x4113600
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1409 0x4113604
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1410 0x4113608
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1411 0x411360C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1412 0x4113610
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1413 0x4113614
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1414 0x4113618
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1415 0x411361C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1416 0x4113620
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1417 0x4113624
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1418 0x4113628
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1419 0x411362C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1420 0x4113630
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1421 0x4113634
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1422 0x4113638
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1423 0x411363C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1424 0x4113640
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1425 0x4113644
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1426 0x4113648
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1427 0x411364C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1428 0x4113650
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1429 0x4113654
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1430 0x4113658
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1431 0x411365C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1432 0x4113660
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1433 0x4113664
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1434 0x4113668
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1435 0x411366C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1436 0x4113670
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1437 0x4113674
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1438 0x4113678
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1439 0x411367C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1440 0x4113680
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1441 0x4113684
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1442 0x4113688
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1443 0x411368C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1444 0x4113690
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1445 0x4113694
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1446 0x4113698
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1447 0x411369C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1448 0x41136A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1449 0x41136A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1450 0x41136A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1451 0x41136AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1452 0x41136B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1453 0x41136B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1454 0x41136B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1455 0x41136BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1456 0x41136C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1457 0x41136C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1458 0x41136C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1459 0x41136CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1460 0x41136D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1461 0x41136D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1462 0x41136D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1463 0x41136DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1464 0x41136E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1465 0x41136E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1466 0x41136E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1467 0x41136EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1468 0x41136F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1469 0x41136F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1470 0x41136F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1471 0x41136FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1472 0x4113700
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1473 0x4113704
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1474 0x4113708
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1475 0x411370C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1476 0x4113710
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1477 0x4113714
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1478 0x4113718
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1479 0x411371C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1480 0x4113720
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1481 0x4113724
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1482 0x4113728
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1483 0x411372C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1484 0x4113730
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1485 0x4113734
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1486 0x4113738
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1487 0x411373C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1488 0x4113740
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1489 0x4113744
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1490 0x4113748
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1491 0x411374C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1492 0x4113750
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1493 0x4113754
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1494 0x4113758
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1495 0x411375C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1496 0x4113760
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1497 0x4113764
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1498 0x4113768
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1499 0x411376C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1500 0x4113770
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1501 0x4113774
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1502 0x4113778
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1503 0x411377C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1504 0x4113780
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1505 0x4113784
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1506 0x4113788
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1507 0x411378C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1508 0x4113790
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1509 0x4113794
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1510 0x4113798
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1511 0x411379C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1512 0x41137A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1513 0x41137A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1514 0x41137A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1515 0x41137AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1516 0x41137B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1517 0x41137B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1518 0x41137B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1519 0x41137BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1520 0x41137C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1521 0x41137C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1522 0x41137C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1523 0x41137CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1524 0x41137D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1525 0x41137D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1526 0x41137D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1527 0x41137DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1528 0x41137E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1529 0x41137E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1530 0x41137E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1531 0x41137EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1532 0x41137F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1533 0x41137F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1534 0x41137F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1535 0x41137FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1536 0x4113800
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1537 0x4113804
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1538 0x4113808
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1539 0x411380C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1540 0x4113810
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1541 0x4113814
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1542 0x4113818
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1543 0x411381C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1544 0x4113820
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1545 0x4113824
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1546 0x4113828
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1547 0x411382C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1548 0x4113830
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1549 0x4113834
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1550 0x4113838
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1551 0x411383C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1552 0x4113840
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1553 0x4113844
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1554 0x4113848
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1555 0x411384C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1556 0x4113850
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1557 0x4113854
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1558 0x4113858
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1559 0x411385C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1560 0x4113860
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1561 0x4113864
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1562 0x4113868
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1563 0x411386C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1564 0x4113870
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1565 0x4113874
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1566 0x4113878
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1567 0x411387C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1568 0x4113880
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1569 0x4113884
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1570 0x4113888
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1571 0x411388C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1572 0x4113890
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1573 0x4113894
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1574 0x4113898
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1575 0x411389C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1576 0x41138A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1577 0x41138A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1578 0x41138A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1579 0x41138AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1580 0x41138B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1581 0x41138B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1582 0x41138B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1583 0x41138BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1584 0x41138C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1585 0x41138C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1586 0x41138C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1587 0x41138CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1588 0x41138D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1589 0x41138D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1590 0x41138D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1591 0x41138DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1592 0x41138E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1593 0x41138E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1594 0x41138E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1595 0x41138EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1596 0x41138F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1597 0x41138F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1598 0x41138F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1599 0x41138FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1600 0x4113900
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1601 0x4113904
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1602 0x4113908
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1603 0x411390C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1604 0x4113910
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1605 0x4113914
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1606 0x4113918
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1607 0x411391C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1608 0x4113920
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1609 0x4113924
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1610 0x4113928
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1611 0x411392C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1612 0x4113930
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1613 0x4113934
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1614 0x4113938
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1615 0x411393C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1616 0x4113940
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1617 0x4113944
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1618 0x4113948
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1619 0x411394C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1620 0x4113950
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1621 0x4113954
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1622 0x4113958
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1623 0x411395C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1624 0x4113960
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1625 0x4113964
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1626 0x4113968
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1627 0x411396C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1628 0x4113970
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1629 0x4113974
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1630 0x4113978
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1631 0x411397C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1632 0x4113980
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1633 0x4113984
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1634 0x4113988
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1635 0x411398C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1636 0x4113990
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1637 0x4113994
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1638 0x4113998
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1639 0x411399C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1640 0x41139A0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1641 0x41139A4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1642 0x41139A8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1643 0x41139AC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1644 0x41139B0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1645 0x41139B4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1646 0x41139B8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1647 0x41139BC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1648 0x41139C0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1649 0x41139C4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1650 0x41139C8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1651 0x41139CC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1652 0x41139D0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1653 0x41139D4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1654 0x41139D8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1655 0x41139DC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1656 0x41139E0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1657 0x41139E4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1658 0x41139E8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1659 0x41139EC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1660 0x41139F0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1661 0x41139F4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1662 0x41139F8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1663 0x41139FC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1664 0x4113A00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1665 0x4113A04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1666 0x4113A08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1667 0x4113A0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1668 0x4113A10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1669 0x4113A14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1670 0x4113A18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1671 0x4113A1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1672 0x4113A20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1673 0x4113A24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1674 0x4113A28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1675 0x4113A2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1676 0x4113A30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1677 0x4113A34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1678 0x4113A38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1679 0x4113A3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1680 0x4113A40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1681 0x4113A44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1682 0x4113A48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1683 0x4113A4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1684 0x4113A50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1685 0x4113A54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1686 0x4113A58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1687 0x4113A5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1688 0x4113A60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1689 0x4113A64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1690 0x4113A68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1691 0x4113A6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1692 0x4113A70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1693 0x4113A74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1694 0x4113A78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1695 0x4113A7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1696 0x4113A80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1697 0x4113A84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1698 0x4113A88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1699 0x4113A8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1700 0x4113A90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1701 0x4113A94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1702 0x4113A98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1703 0x4113A9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1704 0x4113AA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1705 0x4113AA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1706 0x4113AA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1707 0x4113AAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1708 0x4113AB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1709 0x4113AB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1710 0x4113AB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1711 0x4113ABC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1712 0x4113AC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1713 0x4113AC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1714 0x4113AC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1715 0x4113ACC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1716 0x4113AD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1717 0x4113AD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1718 0x4113AD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1719 0x4113ADC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1720 0x4113AE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1721 0x4113AE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1722 0x4113AE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1723 0x4113AEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1724 0x4113AF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1725 0x4113AF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1726 0x4113AF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1727 0x4113AFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1728 0x4113B00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1729 0x4113B04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1730 0x4113B08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1731 0x4113B0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1732 0x4113B10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1733 0x4113B14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1734 0x4113B18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1735 0x4113B1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1736 0x4113B20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1737 0x4113B24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1738 0x4113B28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1739 0x4113B2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1740 0x4113B30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1741 0x4113B34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1742 0x4113B38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1743 0x4113B3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1744 0x4113B40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1745 0x4113B44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1746 0x4113B48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1747 0x4113B4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1748 0x4113B50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1749 0x4113B54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1750 0x4113B58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1751 0x4113B5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1752 0x4113B60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1753 0x4113B64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1754 0x4113B68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1755 0x4113B6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1756 0x4113B70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1757 0x4113B74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1758 0x4113B78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1759 0x4113B7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1760 0x4113B80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1761 0x4113B84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1762 0x4113B88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1763 0x4113B8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1764 0x4113B90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1765 0x4113B94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1766 0x4113B98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1767 0x4113B9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1768 0x4113BA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1769 0x4113BA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1770 0x4113BA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1771 0x4113BAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1772 0x4113BB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1773 0x4113BB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1774 0x4113BB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1775 0x4113BBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1776 0x4113BC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1777 0x4113BC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1778 0x4113BC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1779 0x4113BCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1780 0x4113BD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1781 0x4113BD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1782 0x4113BD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1783 0x4113BDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1784 0x4113BE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1785 0x4113BE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1786 0x4113BE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1787 0x4113BEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1788 0x4113BF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1789 0x4113BF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1790 0x4113BF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1791 0x4113BFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1792 0x4113C00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1793 0x4113C04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1794 0x4113C08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1795 0x4113C0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1796 0x4113C10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1797 0x4113C14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1798 0x4113C18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1799 0x4113C1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1800 0x4113C20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1801 0x4113C24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1802 0x4113C28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1803 0x4113C2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1804 0x4113C30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1805 0x4113C34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1806 0x4113C38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1807 0x4113C3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1808 0x4113C40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1809 0x4113C44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1810 0x4113C48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1811 0x4113C4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1812 0x4113C50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1813 0x4113C54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1814 0x4113C58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1815 0x4113C5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1816 0x4113C60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1817 0x4113C64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1818 0x4113C68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1819 0x4113C6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1820 0x4113C70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1821 0x4113C74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1822 0x4113C78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1823 0x4113C7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1824 0x4113C80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1825 0x4113C84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1826 0x4113C88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1827 0x4113C8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1828 0x4113C90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1829 0x4113C94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1830 0x4113C98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1831 0x4113C9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1832 0x4113CA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1833 0x4113CA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1834 0x4113CA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1835 0x4113CAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1836 0x4113CB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1837 0x4113CB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1838 0x4113CB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1839 0x4113CBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1840 0x4113CC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1841 0x4113CC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1842 0x4113CC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1843 0x4113CCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1844 0x4113CD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1845 0x4113CD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1846 0x4113CD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1847 0x4113CDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1848 0x4113CE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1849 0x4113CE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1850 0x4113CE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1851 0x4113CEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1852 0x4113CF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1853 0x4113CF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1854 0x4113CF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1855 0x4113CFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1856 0x4113D00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1857 0x4113D04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1858 0x4113D08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1859 0x4113D0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1860 0x4113D10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1861 0x4113D14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1862 0x4113D18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1863 0x4113D1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1864 0x4113D20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1865 0x4113D24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1866 0x4113D28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1867 0x4113D2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1868 0x4113D30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1869 0x4113D34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1870 0x4113D38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1871 0x4113D3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1872 0x4113D40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1873 0x4113D44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1874 0x4113D48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1875 0x4113D4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1876 0x4113D50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1877 0x4113D54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1878 0x4113D58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1879 0x4113D5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1880 0x4113D60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1881 0x4113D64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1882 0x4113D68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1883 0x4113D6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1884 0x4113D70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1885 0x4113D74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1886 0x4113D78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1887 0x4113D7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1888 0x4113D80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1889 0x4113D84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1890 0x4113D88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1891 0x4113D8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1892 0x4113D90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1893 0x4113D94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1894 0x4113D98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1895 0x4113D9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1896 0x4113DA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1897 0x4113DA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1898 0x4113DA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1899 0x4113DAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1900 0x4113DB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1901 0x4113DB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1902 0x4113DB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1903 0x4113DBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1904 0x4113DC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1905 0x4113DC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1906 0x4113DC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1907 0x4113DCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1908 0x4113DD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1909 0x4113DD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1910 0x4113DD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1911 0x4113DDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1912 0x4113DE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1913 0x4113DE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1914 0x4113DE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1915 0x4113DEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1916 0x4113DF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1917 0x4113DF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1918 0x4113DF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1919 0x4113DFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1920 0x4113E00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1921 0x4113E04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1922 0x4113E08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1923 0x4113E0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1924 0x4113E10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1925 0x4113E14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1926 0x4113E18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1927 0x4113E1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1928 0x4113E20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1929 0x4113E24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1930 0x4113E28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1931 0x4113E2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1932 0x4113E30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1933 0x4113E34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1934 0x4113E38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1935 0x4113E3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1936 0x4113E40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1937 0x4113E44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1938 0x4113E48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1939 0x4113E4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1940 0x4113E50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1941 0x4113E54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1942 0x4113E58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1943 0x4113E5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1944 0x4113E60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1945 0x4113E64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1946 0x4113E68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1947 0x4113E6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1948 0x4113E70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1949 0x4113E74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1950 0x4113E78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1951 0x4113E7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1952 0x4113E80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1953 0x4113E84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1954 0x4113E88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1955 0x4113E8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1956 0x4113E90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1957 0x4113E94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1958 0x4113E98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1959 0x4113E9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1960 0x4113EA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1961 0x4113EA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1962 0x4113EA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1963 0x4113EAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1964 0x4113EB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1965 0x4113EB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1966 0x4113EB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1967 0x4113EBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1968 0x4113EC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1969 0x4113EC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1970 0x4113EC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1971 0x4113ECC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1972 0x4113ED0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1973 0x4113ED4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1974 0x4113ED8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1975 0x4113EDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1976 0x4113EE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1977 0x4113EE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1978 0x4113EE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1979 0x4113EEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1980 0x4113EF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1981 0x4113EF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1982 0x4113EF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1983 0x4113EFC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1984 0x4113F00
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1985 0x4113F04
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1986 0x4113F08
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1987 0x4113F0C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1988 0x4113F10
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1989 0x4113F14
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1990 0x4113F18
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1991 0x4113F1C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1992 0x4113F20
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1993 0x4113F24
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1994 0x4113F28
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1995 0x4113F2C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1996 0x4113F30
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1997 0x4113F34
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1998 0x4113F38
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_1999 0x4113F3C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2000 0x4113F40
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2001 0x4113F44
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2002 0x4113F48
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2003 0x4113F4C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2004 0x4113F50
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2005 0x4113F54
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2006 0x4113F58
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2007 0x4113F5C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2008 0x4113F60
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2009 0x4113F64
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2010 0x4113F68
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2011 0x4113F6C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2012 0x4113F70
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2013 0x4113F74
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2014 0x4113F78
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2015 0x4113F7C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2016 0x4113F80
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2017 0x4113F84
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2018 0x4113F88
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2019 0x4113F8C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2020 0x4113F90
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2021 0x4113F94
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2022 0x4113F98
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2023 0x4113F9C
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2024 0x4113FA0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2025 0x4113FA4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2026 0x4113FA8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2027 0x4113FAC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2028 0x4113FB0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2029 0x4113FB4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2030 0x4113FB8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2031 0x4113FBC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2032 0x4113FC0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2033 0x4113FC4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2034 0x4113FC8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2035 0x4113FCC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2036 0x4113FD0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2037 0x4113FD4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2038 0x4113FD8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2039 0x4113FDC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2040 0x4113FE0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2041 0x4113FE4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2042 0x4113FE8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2043 0x4113FEC
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2044 0x4113FF0
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2045 0x4113FF4
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2046 0x4113FF8
+
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 0x4113FFC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_0 0x4114000
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_1 0x4114004
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_2 0x4114008
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_3 0x411400C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_4 0x4114010
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_5 0x4114014
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_6 0x4114018
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_7 0x411401C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_8 0x4114020
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_9 0x4114024
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_10 0x4114028
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_11 0x411402C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_12 0x4114030
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_13 0x4114034
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_14 0x4114038
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_15 0x411403C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_16 0x4114040
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_17 0x4114044
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_18 0x4114048
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_19 0x411404C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_20 0x4114050
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_21 0x4114054
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_22 0x4114058
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_23 0x411405C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_24 0x4114060
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_25 0x4114064
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_26 0x4114068
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_27 0x411406C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_28 0x4114070
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_29 0x4114074
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_30 0x4114078
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_31 0x411407C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_32 0x4114080
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_33 0x4114084
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_34 0x4114088
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_35 0x411408C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_36 0x4114090
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_37 0x4114094
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_38 0x4114098
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_39 0x411409C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_40 0x41140A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_41 0x41140A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_42 0x41140A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_43 0x41140AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_44 0x41140B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_45 0x41140B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_46 0x41140B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_47 0x41140BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_48 0x41140C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_49 0x41140C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_50 0x41140C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_51 0x41140CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_52 0x41140D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_53 0x41140D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_54 0x41140D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_55 0x41140DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_56 0x41140E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_57 0x41140E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_58 0x41140E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_59 0x41140EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_60 0x41140F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_61 0x41140F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_62 0x41140F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_63 0x41140FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_64 0x4114100
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_65 0x4114104
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_66 0x4114108
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_67 0x411410C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_68 0x4114110
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_69 0x4114114
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_70 0x4114118
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_71 0x411411C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_72 0x4114120
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_73 0x4114124
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_74 0x4114128
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_75 0x411412C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_76 0x4114130
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_77 0x4114134
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_78 0x4114138
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_79 0x411413C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_80 0x4114140
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_81 0x4114144
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_82 0x4114148
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_83 0x411414C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_84 0x4114150
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_85 0x4114154
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_86 0x4114158
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_87 0x411415C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_88 0x4114160
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_89 0x4114164
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_90 0x4114168
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_91 0x411416C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_92 0x4114170
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_93 0x4114174
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_94 0x4114178
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_95 0x411417C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_96 0x4114180
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_97 0x4114184
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_98 0x4114188
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_99 0x411418C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_100 0x4114190
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_101 0x4114194
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_102 0x4114198
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_103 0x411419C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_104 0x41141A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_105 0x41141A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_106 0x41141A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_107 0x41141AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_108 0x41141B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_109 0x41141B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_110 0x41141B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_111 0x41141BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_112 0x41141C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_113 0x41141C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_114 0x41141C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_115 0x41141CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_116 0x41141D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_117 0x41141D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_118 0x41141D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_119 0x41141DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_120 0x41141E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_121 0x41141E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_122 0x41141E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_123 0x41141EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_124 0x41141F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_125 0x41141F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_126 0x41141F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_127 0x41141FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_128 0x4114200
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_129 0x4114204
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_130 0x4114208
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_131 0x411420C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_132 0x4114210
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_133 0x4114214
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_134 0x4114218
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_135 0x411421C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_136 0x4114220
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_137 0x4114224
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_138 0x4114228
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_139 0x411422C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_140 0x4114230
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_141 0x4114234
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_142 0x4114238
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_143 0x411423C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_144 0x4114240
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_145 0x4114244
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_146 0x4114248
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_147 0x411424C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_148 0x4114250
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_149 0x4114254
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_150 0x4114258
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_151 0x411425C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_152 0x4114260
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_153 0x4114264
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_154 0x4114268
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_155 0x411426C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_156 0x4114270
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_157 0x4114274
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_158 0x4114278
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_159 0x411427C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_160 0x4114280
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_161 0x4114284
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_162 0x4114288
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_163 0x411428C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_164 0x4114290
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_165 0x4114294
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_166 0x4114298
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_167 0x411429C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_168 0x41142A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_169 0x41142A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_170 0x41142A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_171 0x41142AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_172 0x41142B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_173 0x41142B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_174 0x41142B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_175 0x41142BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_176 0x41142C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_177 0x41142C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_178 0x41142C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_179 0x41142CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_180 0x41142D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_181 0x41142D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_182 0x41142D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_183 0x41142DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_184 0x41142E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_185 0x41142E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_186 0x41142E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_187 0x41142EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_188 0x41142F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_189 0x41142F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_190 0x41142F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_191 0x41142FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_192 0x4114300
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_193 0x4114304
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_194 0x4114308
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_195 0x411430C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_196 0x4114310
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_197 0x4114314
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_198 0x4114318
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_199 0x411431C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_200 0x4114320
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_201 0x4114324
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_202 0x4114328
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_203 0x411432C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_204 0x4114330
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_205 0x4114334
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_206 0x4114338
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_207 0x411433C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_208 0x4114340
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_209 0x4114344
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_210 0x4114348
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_211 0x411434C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_212 0x4114350
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_213 0x4114354
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_214 0x4114358
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_215 0x411435C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_216 0x4114360
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_217 0x4114364
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_218 0x4114368
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_219 0x411436C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_220 0x4114370
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_221 0x4114374
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_222 0x4114378
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_223 0x411437C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_224 0x4114380
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_225 0x4114384
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_226 0x4114388
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_227 0x411438C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_228 0x4114390
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_229 0x4114394
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_230 0x4114398
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_231 0x411439C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_232 0x41143A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_233 0x41143A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_234 0x41143A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_235 0x41143AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_236 0x41143B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_237 0x41143B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_238 0x41143B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_239 0x41143BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_240 0x41143C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_241 0x41143C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_242 0x41143C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_243 0x41143CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_244 0x41143D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_245 0x41143D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_246 0x41143D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_247 0x41143DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_248 0x41143E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_249 0x41143E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_250 0x41143E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_251 0x41143EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_252 0x41143F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_253 0x41143F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_254 0x41143F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_255 0x41143FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_256 0x4114400
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_257 0x4114404
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_258 0x4114408
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_259 0x411440C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_260 0x4114410
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_261 0x4114414
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_262 0x4114418
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_263 0x411441C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_264 0x4114420
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_265 0x4114424
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_266 0x4114428
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_267 0x411442C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_268 0x4114430
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_269 0x4114434
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_270 0x4114438
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_271 0x411443C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_272 0x4114440
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_273 0x4114444
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_274 0x4114448
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_275 0x411444C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_276 0x4114450
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_277 0x4114454
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_278 0x4114458
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_279 0x411445C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_280 0x4114460
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_281 0x4114464
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_282 0x4114468
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_283 0x411446C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_284 0x4114470
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_285 0x4114474
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_286 0x4114478
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_287 0x411447C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_288 0x4114480
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_289 0x4114484
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_290 0x4114488
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_291 0x411448C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_292 0x4114490
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_293 0x4114494
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_294 0x4114498
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_295 0x411449C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_296 0x41144A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_297 0x41144A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_298 0x41144A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_299 0x41144AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_300 0x41144B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_301 0x41144B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_302 0x41144B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_303 0x41144BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_304 0x41144C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_305 0x41144C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_306 0x41144C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_307 0x41144CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_308 0x41144D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_309 0x41144D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_310 0x41144D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_311 0x41144DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_312 0x41144E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_313 0x41144E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_314 0x41144E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_315 0x41144EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_316 0x41144F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_317 0x41144F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_318 0x41144F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_319 0x41144FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_320 0x4114500
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_321 0x4114504
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_322 0x4114508
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_323 0x411450C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_324 0x4114510
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_325 0x4114514
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_326 0x4114518
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_327 0x411451C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_328 0x4114520
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_329 0x4114524
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_330 0x4114528
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_331 0x411452C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_332 0x4114530
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_333 0x4114534
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_334 0x4114538
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_335 0x411453C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_336 0x4114540
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_337 0x4114544
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_338 0x4114548
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_339 0x411454C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_340 0x4114550
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_341 0x4114554
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_342 0x4114558
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_343 0x411455C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_344 0x4114560
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_345 0x4114564
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_346 0x4114568
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_347 0x411456C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_348 0x4114570
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_349 0x4114574
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_350 0x4114578
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_351 0x411457C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_352 0x4114580
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_353 0x4114584
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_354 0x4114588
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_355 0x411458C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_356 0x4114590
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_357 0x4114594
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_358 0x4114598
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_359 0x411459C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_360 0x41145A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_361 0x41145A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_362 0x41145A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_363 0x41145AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_364 0x41145B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_365 0x41145B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_366 0x41145B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_367 0x41145BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_368 0x41145C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_369 0x41145C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_370 0x41145C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_371 0x41145CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_372 0x41145D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_373 0x41145D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_374 0x41145D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_375 0x41145DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_376 0x41145E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_377 0x41145E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_378 0x41145E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_379 0x41145EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_380 0x41145F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_381 0x41145F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_382 0x41145F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_383 0x41145FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_384 0x4114600
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_385 0x4114604
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_386 0x4114608
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_387 0x411460C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_388 0x4114610
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_389 0x4114614
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_390 0x4114618
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_391 0x411461C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_392 0x4114620
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_393 0x4114624
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_394 0x4114628
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_395 0x411462C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_396 0x4114630
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_397 0x4114634
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_398 0x4114638
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_399 0x411463C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_400 0x4114640
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_401 0x4114644
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_402 0x4114648
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_403 0x411464C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_404 0x4114650
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_405 0x4114654
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_406 0x4114658
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_407 0x411465C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_408 0x4114660
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_409 0x4114664
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_410 0x4114668
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_411 0x411466C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_412 0x4114670
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_413 0x4114674
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_414 0x4114678
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_415 0x411467C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_416 0x4114680
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_417 0x4114684
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_418 0x4114688
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_419 0x411468C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_420 0x4114690
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_421 0x4114694
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_422 0x4114698
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_423 0x411469C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_424 0x41146A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_425 0x41146A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_426 0x41146A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_427 0x41146AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_428 0x41146B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_429 0x41146B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_430 0x41146B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_431 0x41146BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_432 0x41146C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_433 0x41146C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_434 0x41146C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_435 0x41146CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_436 0x41146D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_437 0x41146D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_438 0x41146D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_439 0x41146DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_440 0x41146E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_441 0x41146E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_442 0x41146E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_443 0x41146EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_444 0x41146F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_445 0x41146F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_446 0x41146F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_447 0x41146FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_448 0x4114700
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_449 0x4114704
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_450 0x4114708
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_451 0x411470C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_452 0x4114710
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_453 0x4114714
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_454 0x4114718
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_455 0x411471C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_456 0x4114720
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_457 0x4114724
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_458 0x4114728
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_459 0x411472C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_460 0x4114730
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_461 0x4114734
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_462 0x4114738
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_463 0x411473C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_464 0x4114740
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_465 0x4114744
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_466 0x4114748
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_467 0x411474C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_468 0x4114750
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_469 0x4114754
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_470 0x4114758
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_471 0x411475C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_472 0x4114760
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_473 0x4114764
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_474 0x4114768
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_475 0x411476C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_476 0x4114770
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_477 0x4114774
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_478 0x4114778
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_479 0x411477C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_480 0x4114780
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_481 0x4114784
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_482 0x4114788
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_483 0x411478C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_484 0x4114790
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_485 0x4114794
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_486 0x4114798
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_487 0x411479C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_488 0x41147A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_489 0x41147A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_490 0x41147A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_491 0x41147AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_492 0x41147B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_493 0x41147B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_494 0x41147B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_495 0x41147BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_496 0x41147C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_497 0x41147C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_498 0x41147C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_499 0x41147CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_500 0x41147D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_501 0x41147D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_502 0x41147D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_503 0x41147DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_504 0x41147E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_505 0x41147E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_506 0x41147E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_507 0x41147EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_508 0x41147F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_509 0x41147F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_510 0x41147F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_511 0x41147FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_512 0x4114800
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_513 0x4114804
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_514 0x4114808
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_515 0x411480C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_516 0x4114810
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_517 0x4114814
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_518 0x4114818
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_519 0x411481C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_520 0x4114820
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_521 0x4114824
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_522 0x4114828
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_523 0x411482C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_524 0x4114830
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_525 0x4114834
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_526 0x4114838
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_527 0x411483C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_528 0x4114840
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_529 0x4114844
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_530 0x4114848
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_531 0x411484C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_532 0x4114850
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_533 0x4114854
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_534 0x4114858
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_535 0x411485C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_536 0x4114860
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_537 0x4114864
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_538 0x4114868
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_539 0x411486C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_540 0x4114870
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_541 0x4114874
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_542 0x4114878
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_543 0x411487C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_544 0x4114880
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_545 0x4114884
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_546 0x4114888
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_547 0x411488C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_548 0x4114890
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_549 0x4114894
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_550 0x4114898
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_551 0x411489C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_552 0x41148A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_553 0x41148A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_554 0x41148A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_555 0x41148AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_556 0x41148B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_557 0x41148B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_558 0x41148B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_559 0x41148BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_560 0x41148C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_561 0x41148C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_562 0x41148C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_563 0x41148CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_564 0x41148D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_565 0x41148D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_566 0x41148D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_567 0x41148DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_568 0x41148E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_569 0x41148E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_570 0x41148E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_571 0x41148EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_572 0x41148F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_573 0x41148F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_574 0x41148F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_575 0x41148FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_576 0x4114900
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_577 0x4114904
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_578 0x4114908
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_579 0x411490C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_580 0x4114910
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_581 0x4114914
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_582 0x4114918
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_583 0x411491C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_584 0x4114920
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_585 0x4114924
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_586 0x4114928
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_587 0x411492C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_588 0x4114930
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_589 0x4114934
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_590 0x4114938
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_591 0x411493C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_592 0x4114940
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_593 0x4114944
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_594 0x4114948
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_595 0x411494C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_596 0x4114950
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_597 0x4114954
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_598 0x4114958
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_599 0x411495C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_600 0x4114960
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_601 0x4114964
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_602 0x4114968
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_603 0x411496C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_604 0x4114970
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_605 0x4114974
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_606 0x4114978
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_607 0x411497C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_608 0x4114980
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_609 0x4114984
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_610 0x4114988
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_611 0x411498C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_612 0x4114990
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_613 0x4114994
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_614 0x4114998
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_615 0x411499C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_616 0x41149A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_617 0x41149A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_618 0x41149A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_619 0x41149AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_620 0x41149B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_621 0x41149B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_622 0x41149B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_623 0x41149BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_624 0x41149C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_625 0x41149C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_626 0x41149C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_627 0x41149CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_628 0x41149D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_629 0x41149D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_630 0x41149D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_631 0x41149DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_632 0x41149E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_633 0x41149E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_634 0x41149E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_635 0x41149EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_636 0x41149F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_637 0x41149F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_638 0x41149F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_639 0x41149FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_0 0x4115000
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_1 0x4115004
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_2 0x4115008
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_3 0x411500C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_4 0x4115010
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_5 0x4115014
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_6 0x4115018
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_7 0x411501C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_8 0x4115020
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_9 0x4115024
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_10 0x4115028
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_11 0x411502C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_12 0x4115030
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_13 0x4115034
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_14 0x4115038
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_15 0x411503C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_16 0x4115040
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_17 0x4115044
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_18 0x4115048
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_19 0x411504C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_20 0x4115050
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_21 0x4115054
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_22 0x4115058
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_23 0x411505C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_24 0x4115060
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_25 0x4115064
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_26 0x4115068
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_27 0x411506C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_28 0x4115070
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_29 0x4115074
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_30 0x4115078
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_31 0x411507C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_32 0x4115080
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_33 0x4115084
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_34 0x4115088
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_35 0x411508C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_36 0x4115090
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_37 0x4115094
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_38 0x4115098
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_39 0x411509C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_40 0x41150A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_41 0x41150A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_42 0x41150A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_43 0x41150AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_44 0x41150B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_45 0x41150B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_46 0x41150B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_47 0x41150BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_48 0x41150C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_49 0x41150C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_50 0x41150C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_51 0x41150CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_52 0x41150D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_53 0x41150D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_54 0x41150D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_55 0x41150DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_56 0x41150E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_57 0x41150E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_58 0x41150E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_59 0x41150EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_60 0x41150F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_61 0x41150F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_62 0x41150F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_63 0x41150FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_64 0x4115100
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_65 0x4115104
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_66 0x4115108
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_67 0x411510C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_68 0x4115110
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_69 0x4115114
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_70 0x4115118
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_71 0x411511C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_72 0x4115120
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_73 0x4115124
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_74 0x4115128
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_75 0x411512C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_76 0x4115130
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_77 0x4115134
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_78 0x4115138
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_79 0x411513C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_80 0x4115140
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_81 0x4115144
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_82 0x4115148
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_83 0x411514C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_84 0x4115150
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_85 0x4115154
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_86 0x4115158
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_87 0x411515C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_88 0x4115160
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_89 0x4115164
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_90 0x4115168
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_91 0x411516C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_92 0x4115170
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_93 0x4115174
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_94 0x4115178
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_95 0x411517C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_96 0x4115180
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_97 0x4115184
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_98 0x4115188
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_99 0x411518C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_100 0x4115190
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_101 0x4115194
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_102 0x4115198
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_103 0x411519C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_104 0x41151A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_105 0x41151A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_106 0x41151A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_107 0x41151AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_108 0x41151B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_109 0x41151B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_110 0x41151B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_111 0x41151BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_112 0x41151C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_113 0x41151C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_114 0x41151C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_115 0x41151CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_116 0x41151D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_117 0x41151D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_118 0x41151D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_119 0x41151DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_120 0x41151E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_121 0x41151E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_122 0x41151E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_123 0x41151EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_124 0x41151F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_125 0x41151F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_126 0x41151F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_127 0x41151FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_128 0x4115200
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_129 0x4115204
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_130 0x4115208
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_131 0x411520C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_132 0x4115210
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_133 0x4115214
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_134 0x4115218
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_135 0x411521C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_136 0x4115220
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_137 0x4115224
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_138 0x4115228
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_139 0x411522C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_140 0x4115230
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_141 0x4115234
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_142 0x4115238
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_143 0x411523C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_144 0x4115240
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_145 0x4115244
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_146 0x4115248
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_147 0x411524C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_148 0x4115250
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_149 0x4115254
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_150 0x4115258
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_151 0x411525C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_152 0x4115260
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_153 0x4115264
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_154 0x4115268
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_155 0x411526C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_156 0x4115270
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_157 0x4115274
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_158 0x4115278
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_159 0x411527C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_160 0x4115280
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_161 0x4115284
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_162 0x4115288
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_163 0x411528C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_164 0x4115290
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_165 0x4115294
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_166 0x4115298
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_167 0x411529C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_168 0x41152A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_169 0x41152A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_170 0x41152A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_171 0x41152AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_172 0x41152B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_173 0x41152B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_174 0x41152B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_175 0x41152BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_176 0x41152C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_177 0x41152C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_178 0x41152C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_179 0x41152CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_180 0x41152D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_181 0x41152D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_182 0x41152D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_183 0x41152DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_184 0x41152E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_185 0x41152E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_186 0x41152E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_187 0x41152EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_188 0x41152F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_189 0x41152F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_190 0x41152F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_191 0x41152FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_192 0x4115300
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_193 0x4115304
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_194 0x4115308
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_195 0x411530C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_196 0x4115310
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_197 0x4115314
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_198 0x4115318
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_199 0x411531C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_200 0x4115320
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_201 0x4115324
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_202 0x4115328
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_203 0x411532C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_204 0x4115330
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_205 0x4115334
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_206 0x4115338
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_207 0x411533C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_208 0x4115340
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_209 0x4115344
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_210 0x4115348
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_211 0x411534C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_212 0x4115350
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_213 0x4115354
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_214 0x4115358
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_215 0x411535C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_216 0x4115360
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_217 0x4115364
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_218 0x4115368
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_219 0x411536C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_220 0x4115370
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_221 0x4115374
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_222 0x4115378
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_223 0x411537C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_224 0x4115380
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_225 0x4115384
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_226 0x4115388
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_227 0x411538C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_228 0x4115390
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_229 0x4115394
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_230 0x4115398
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_231 0x411539C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_232 0x41153A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_233 0x41153A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_234 0x41153A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_235 0x41153AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_236 0x41153B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_237 0x41153B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_238 0x41153B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_239 0x41153BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_240 0x41153C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_241 0x41153C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_242 0x41153C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_243 0x41153CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_244 0x41153D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_245 0x41153D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_246 0x41153D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_247 0x41153DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_248 0x41153E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_249 0x41153E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_250 0x41153E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_251 0x41153EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_252 0x41153F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_253 0x41153F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_254 0x41153F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_255 0x41153FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_256 0x4115400
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_257 0x4115404
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_258 0x4115408
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_259 0x411540C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_260 0x4115410
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_261 0x4115414
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_262 0x4115418
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_263 0x411541C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_264 0x4115420
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_265 0x4115424
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_266 0x4115428
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_267 0x411542C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_268 0x4115430
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_269 0x4115434
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_270 0x4115438
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_271 0x411543C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_272 0x4115440
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_273 0x4115444
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_274 0x4115448
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_275 0x411544C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_276 0x4115450
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_277 0x4115454
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_278 0x4115458
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_279 0x411545C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_280 0x4115460
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_281 0x4115464
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_282 0x4115468
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_283 0x411546C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_284 0x4115470
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_285 0x4115474
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_286 0x4115478
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_287 0x411547C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_288 0x4115480
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_289 0x4115484
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_290 0x4115488
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_291 0x411548C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_292 0x4115490
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_293 0x4115494
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_294 0x4115498
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_295 0x411549C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_296 0x41154A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_297 0x41154A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_298 0x41154A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_299 0x41154AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_300 0x41154B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_301 0x41154B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_302 0x41154B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_303 0x41154BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_304 0x41154C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_305 0x41154C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_306 0x41154C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_307 0x41154CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_308 0x41154D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_309 0x41154D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_310 0x41154D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_311 0x41154DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_312 0x41154E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_313 0x41154E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_314 0x41154E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_315 0x41154EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_316 0x41154F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_317 0x41154F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_318 0x41154F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_319 0x41154FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_320 0x4115500
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_321 0x4115504
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_322 0x4115508
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_323 0x411550C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_324 0x4115510
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_325 0x4115514
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_326 0x4115518
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_327 0x411551C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_328 0x4115520
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_329 0x4115524
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_330 0x4115528
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_331 0x411552C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_332 0x4115530
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_333 0x4115534
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_334 0x4115538
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_335 0x411553C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_336 0x4115540
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_337 0x4115544
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_338 0x4115548
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_339 0x411554C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_340 0x4115550
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_341 0x4115554
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_342 0x4115558
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_343 0x411555C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_344 0x4115560
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_345 0x4115564
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_346 0x4115568
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_347 0x411556C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_348 0x4115570
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_349 0x4115574
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_350 0x4115578
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_351 0x411557C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_352 0x4115580
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_353 0x4115584
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_354 0x4115588
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_355 0x411558C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_356 0x4115590
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_357 0x4115594
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_358 0x4115598
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_359 0x411559C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_360 0x41155A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_361 0x41155A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_362 0x41155A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_363 0x41155AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_364 0x41155B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_365 0x41155B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_366 0x41155B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_367 0x41155BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_368 0x41155C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_369 0x41155C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_370 0x41155C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_371 0x41155CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_372 0x41155D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_373 0x41155D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_374 0x41155D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_375 0x41155DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_376 0x41155E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_377 0x41155E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_378 0x41155E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_379 0x41155EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_380 0x41155F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_381 0x41155F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_382 0x41155F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_383 0x41155FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_384 0x4115600
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_385 0x4115604
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_386 0x4115608
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_387 0x411560C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_388 0x4115610
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_389 0x4115614
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_390 0x4115618
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_391 0x411561C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_392 0x4115620
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_393 0x4115624
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_394 0x4115628
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_395 0x411562C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_396 0x4115630
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_397 0x4115634
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_398 0x4115638
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_399 0x411563C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_400 0x4115640
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_401 0x4115644
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_402 0x4115648
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_403 0x411564C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_404 0x4115650
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_405 0x4115654
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_406 0x4115658
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_407 0x411565C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_408 0x4115660
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_409 0x4115664
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_410 0x4115668
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_411 0x411566C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_412 0x4115670
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_413 0x4115674
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_414 0x4115678
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_415 0x411567C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_416 0x4115680
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_417 0x4115684
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_418 0x4115688
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_419 0x411568C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_420 0x4115690
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_421 0x4115694
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_422 0x4115698
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_423 0x411569C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_424 0x41156A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_425 0x41156A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_426 0x41156A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_427 0x41156AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_428 0x41156B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_429 0x41156B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_430 0x41156B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_431 0x41156BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_432 0x41156C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_433 0x41156C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_434 0x41156C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_435 0x41156CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_436 0x41156D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_437 0x41156D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_438 0x41156D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_439 0x41156DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_440 0x41156E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_441 0x41156E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_442 0x41156E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_443 0x41156EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_444 0x41156F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_445 0x41156F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_446 0x41156F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_447 0x41156FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_448 0x4115700
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_449 0x4115704
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_450 0x4115708
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_451 0x411570C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_452 0x4115710
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_453 0x4115714
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_454 0x4115718
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_455 0x411571C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_456 0x4115720
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_457 0x4115724
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_458 0x4115728
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_459 0x411572C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_460 0x4115730
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_461 0x4115734
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_462 0x4115738
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_463 0x411573C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_464 0x4115740
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_465 0x4115744
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_466 0x4115748
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_467 0x411574C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_468 0x4115750
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_469 0x4115754
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_470 0x4115758
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_471 0x411575C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_472 0x4115760
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_473 0x4115764
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_474 0x4115768
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_475 0x411576C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_476 0x4115770
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_477 0x4115774
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_478 0x4115778
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_479 0x411577C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_480 0x4115780
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_481 0x4115784
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_482 0x4115788
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_483 0x411578C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_484 0x4115790
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_485 0x4115794
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_486 0x4115798
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_487 0x411579C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_488 0x41157A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_489 0x41157A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_490 0x41157A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_491 0x41157AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_492 0x41157B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_493 0x41157B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_494 0x41157B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_495 0x41157BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_496 0x41157C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_497 0x41157C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_498 0x41157C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_499 0x41157CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_500 0x41157D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_501 0x41157D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_502 0x41157D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_503 0x41157DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_504 0x41157E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_505 0x41157E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_506 0x41157E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_507 0x41157EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_508 0x41157F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_509 0x41157F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_510 0x41157F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_511 0x41157FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_512 0x4115800
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_513 0x4115804
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_514 0x4115808
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_515 0x411580C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_516 0x4115810
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_517 0x4115814
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_518 0x4115818
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_519 0x411581C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_520 0x4115820
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_521 0x4115824
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_522 0x4115828
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_523 0x411582C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_524 0x4115830
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_525 0x4115834
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_526 0x4115838
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_527 0x411583C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_528 0x4115840
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_529 0x4115844
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_530 0x4115848
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_531 0x411584C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_532 0x4115850
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_533 0x4115854
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_534 0x4115858
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_535 0x411585C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_536 0x4115860
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_537 0x4115864
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_538 0x4115868
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_539 0x411586C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_540 0x4115870
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_541 0x4115874
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_542 0x4115878
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_543 0x411587C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_544 0x4115880
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_545 0x4115884
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_546 0x4115888
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_547 0x411588C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_548 0x4115890
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_549 0x4115894
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_550 0x4115898
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_551 0x411589C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_552 0x41158A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_553 0x41158A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_554 0x41158A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_555 0x41158AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_556 0x41158B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_557 0x41158B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_558 0x41158B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_559 0x41158BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_560 0x41158C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_561 0x41158C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_562 0x41158C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_563 0x41158CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_564 0x41158D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_565 0x41158D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_566 0x41158D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_567 0x41158DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_568 0x41158E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_569 0x41158E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_570 0x41158E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_571 0x41158EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_572 0x41158F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_573 0x41158F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_574 0x41158F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_575 0x41158FC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_576 0x4115900
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_577 0x4115904
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_578 0x4115908
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_579 0x411590C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_580 0x4115910
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_581 0x4115914
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_582 0x4115918
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_583 0x411591C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_584 0x4115920
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_585 0x4115924
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_586 0x4115928
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_587 0x411592C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_588 0x4115930
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_589 0x4115934
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_590 0x4115938
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_591 0x411593C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_592 0x4115940
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_593 0x4115944
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_594 0x4115948
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_595 0x411594C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_596 0x4115950
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_597 0x4115954
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_598 0x4115958
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_599 0x411595C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_600 0x4115960
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_601 0x4115964
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_602 0x4115968
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_603 0x411596C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_604 0x4115970
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_605 0x4115974
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_606 0x4115978
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_607 0x411597C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_608 0x4115980
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_609 0x4115984
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_610 0x4115988
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_611 0x411598C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_612 0x4115990
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_613 0x4115994
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_614 0x4115998
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_615 0x411599C
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_616 0x41159A0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_617 0x41159A4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_618 0x41159A8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_619 0x41159AC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_620 0x41159B0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_621 0x41159B4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_622 0x41159B8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_623 0x41159BC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_624 0x41159C0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_625 0x41159C4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_626 0x41159C8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_627 0x41159CC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_628 0x41159D0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_629 0x41159D4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_630 0x41159D8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_631 0x41159DC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_632 0x41159E0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_633 0x41159E4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_634 0x41159E8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_635 0x41159EC
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_636 0x41159F0
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_637 0x41159F4
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_638 0x41159F8
+
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_639 0x41159FC
+
+#endif /* ASIC_REG_DCORE0_SYNC_MNGR_OBJS_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h
new file mode 100644
index 000000000000..204055964204
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h
@@ -0,0 +1,45068 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef GAUDI2_BLOCKS_LINUX_DRIVER_H_
+#define GAUDI2_BLOCKS_LINUX_DRIVER_H_
+
+#define DCORE0_TPC0_ROM_TABLE_BASE 0x0ull
+#define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
+#define DCORE0_TPC0_EML_SPMU_BASE 0x1000ull
+#define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
+#define DCORE0_TPC0_EML_ETF_BASE 0x2000ull
+#define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_ETF_SECTION 0x1000
+#define DCORE0_TPC0_EML_STM_BASE 0x3000ull
+#define DCORE0_TPC0_EML_STM_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_STM_SECTION 0x2000
+#define DCORE0_TPC0_EML_CTI_BASE 0x5000ull
+#define DCORE0_TPC0_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_CTI_SECTION 0x1000
+#define DCORE0_TPC0_EML_FUNNEL_BASE 0x6000ull
+#define DCORE0_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_FUNNEL_SECTION 0x1000
+#define DCORE0_TPC0_EML_BUSMON_0_BASE 0x7000ull
+#define DCORE0_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_BUSMON_0_SECTION 0x1000
+#define DCORE0_TPC0_EML_BUSMON_1_BASE 0x8000ull
+#define DCORE0_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_BUSMON_1_SECTION 0x1000
+#define DCORE0_TPC0_EML_BUSMON_2_BASE 0x9000ull
+#define DCORE0_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_BUSMON_2_SECTION 0x1000
+#define DCORE0_TPC0_EML_BUSMON_3_BASE 0xA000ull
+#define DCORE0_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_BUSMON_3_SECTION 0x1000
+#define DCORE0_TPC0_QM_ARC_RTT_BASE 0xB000ull
+#define DCORE0_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_TPC0_QM_ARC_RTT_SECTION 0x35000
+#define DCORE0_TPC0_EML_CFG_BASE 0x40000ull
+#define DCORE0_TPC0_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_CFG_SECTION 0xE800
+#define DCORE0_TPC0_EML_CFG_SPECIAL_BASE 0x40E80ull
+#define DCORE0_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x41000ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC0_EML_TPC_CFG_BASE 0x41000ull
+#define DCORE0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_TPC_CFG_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x41050ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x410A0ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x410F0ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x41140ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x41190ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x411E0ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x41230ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x41280ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x412D0ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x41320ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x41370ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x413C0ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x41410ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x41460ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x414B0ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x41500ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_BASE 0x41508ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x415DCull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x4162Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x4167Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x416CCull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x4171Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x4176Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x417BCull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x4180Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x4185Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x418ACull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x418FCull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x4194Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x4199Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x419ECull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x41A3Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x41A8Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x41ADCull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_BASE 0x41AE4ull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE0_TPC0_EML_TPC_CFG_AXUSER_BASE 0x41E00ull
+#define DCORE0_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x41E80ull
+#define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC0_EML_QM_DCCM_BASE 0x42000ull
+#define DCORE0_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC0_EML_QM_DCCM_SECTION 0x8000
+#define DCORE0_TPC0_EML_QM_ARCAUX_BASE 0x4A000ull
+#define DCORE0_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x4AE80ull
+#define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE0_TPC0_EML_TPC_QM_BASE 0x4C000ull
+#define DCORE0_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_TPC_QM_SECTION 0x9000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C900ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C908ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C910ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C918ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C920ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C928ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C930ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C938ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C940ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C948ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C950ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C958ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C960ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C968ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C970ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C978ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x4CB00ull
+#define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x4CB80ull
+#define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x4CC00ull
+#define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x4CC80ull
+#define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_TPC0_EML_TPC_QM_CGM_BASE 0x4CD80ull
+#define DCORE0_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC0_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE0_TPC0_EML_TPC_QM_SPECIAL_BASE 0x4CE80ull
+#define DCORE0_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE0_TPC0_EML_CS_BASE 0x1FF000ull
+#define DCORE0_TPC0_EML_CS_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_CS_SECTION 0x1000
+#define DCORE0_TPC1_ROM_TABLE_BASE 0x200000ull
+#define DCORE0_TPC1_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_ROM_TABLE_SECTION 0x1000
+#define DCORE0_TPC1_EML_SPMU_BASE 0x201000ull
+#define DCORE0_TPC1_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_SPMU_SECTION 0x1000
+#define DCORE0_TPC1_EML_ETF_BASE 0x202000ull
+#define DCORE0_TPC1_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_ETF_SECTION 0x1000
+#define DCORE0_TPC1_EML_STM_BASE 0x203000ull
+#define DCORE0_TPC1_EML_STM_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_STM_SECTION 0x2000
+#define DCORE0_TPC1_EML_CTI_BASE 0x205000ull
+#define DCORE0_TPC1_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_CTI_SECTION 0x1000
+#define DCORE0_TPC1_EML_FUNNEL_BASE 0x206000ull
+#define DCORE0_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_FUNNEL_SECTION 0x1000
+#define DCORE0_TPC1_EML_BUSMON_0_BASE 0x207000ull
+#define DCORE0_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_BUSMON_0_SECTION 0x1000
+#define DCORE0_TPC1_EML_BUSMON_1_BASE 0x208000ull
+#define DCORE0_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_BUSMON_1_SECTION 0x1000
+#define DCORE0_TPC1_EML_BUSMON_2_BASE 0x209000ull
+#define DCORE0_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_BUSMON_2_SECTION 0x1000
+#define DCORE0_TPC1_EML_BUSMON_3_BASE 0x20A000ull
+#define DCORE0_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_BUSMON_3_SECTION 0x1000
+#define DCORE0_TPC1_QM_ARC_RTT_BASE 0x20B000ull
+#define DCORE0_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_TPC1_QM_ARC_RTT_SECTION 0x35000
+#define DCORE0_TPC1_EML_CFG_BASE 0x240000ull
+#define DCORE0_TPC1_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_CFG_SECTION 0xE800
+#define DCORE0_TPC1_EML_CFG_SPECIAL_BASE 0x240E80ull
+#define DCORE0_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x241000ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC1_EML_TPC_CFG_BASE 0x241000ull
+#define DCORE0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_TPC_CFG_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x241050ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x2410A0ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x2410F0ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x241140ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x241190ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x2411E0ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x241230ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x241280ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x2412D0ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x241320ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x241370ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x2413C0ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x241410ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x241460ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x2414B0ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x241500ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_BASE 0x241508ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x2415DCull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x24162Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x24167Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x2416CCull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x24171Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x24176Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x2417BCull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x24180Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x24185Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x2418ACull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x2418FCull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x24194Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x24199Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x2419ECull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x241A3Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x241A8Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x241ADCull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_BASE 0x241AE4ull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE0_TPC1_EML_TPC_CFG_AXUSER_BASE 0x241E00ull
+#define DCORE0_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x241E80ull
+#define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC1_EML_QM_DCCM_BASE 0x242000ull
+#define DCORE0_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC1_EML_QM_DCCM_SECTION 0x8000
+#define DCORE0_TPC1_EML_QM_ARCAUX_BASE 0x24A000ull
+#define DCORE0_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x24AE80ull
+#define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE0_TPC1_EML_TPC_QM_BASE 0x24C000ull
+#define DCORE0_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_TPC_QM_SECTION 0x9000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x24C900ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x24C908ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x24C910ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x24C918ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x24C920ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x24C928ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x24C930ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x24C938ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x24C940ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x24C948ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x24C950ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x24C958ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x24C960ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x24C968ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x24C970ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x24C978ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x24CB00ull
+#define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x24CB80ull
+#define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x24CC00ull
+#define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x24CC80ull
+#define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_TPC1_EML_TPC_QM_CGM_BASE 0x24CD80ull
+#define DCORE0_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC1_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE0_TPC1_EML_TPC_QM_SPECIAL_BASE 0x24CE80ull
+#define DCORE0_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE0_TPC1_EML_CS_BASE 0x3FF000ull
+#define DCORE0_TPC1_EML_CS_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_CS_SECTION 0x1000
+#define DCORE0_TPC2_ROM_TABLE_BASE 0x400000ull
+#define DCORE0_TPC2_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_ROM_TABLE_SECTION 0x1000
+#define DCORE0_TPC2_EML_SPMU_BASE 0x401000ull
+#define DCORE0_TPC2_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_SPMU_SECTION 0x1000
+#define DCORE0_TPC2_EML_ETF_BASE 0x402000ull
+#define DCORE0_TPC2_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_ETF_SECTION 0x1000
+#define DCORE0_TPC2_EML_STM_BASE 0x403000ull
+#define DCORE0_TPC2_EML_STM_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_STM_SECTION 0x2000
+#define DCORE0_TPC2_EML_CTI_BASE 0x405000ull
+#define DCORE0_TPC2_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_CTI_SECTION 0x1000
+#define DCORE0_TPC2_EML_FUNNEL_BASE 0x406000ull
+#define DCORE0_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_FUNNEL_SECTION 0x1000
+#define DCORE0_TPC2_EML_BUSMON_0_BASE 0x407000ull
+#define DCORE0_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_BUSMON_0_SECTION 0x1000
+#define DCORE0_TPC2_EML_BUSMON_1_BASE 0x408000ull
+#define DCORE0_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_BUSMON_1_SECTION 0x1000
+#define DCORE0_TPC2_EML_BUSMON_2_BASE 0x409000ull
+#define DCORE0_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_BUSMON_2_SECTION 0x1000
+#define DCORE0_TPC2_EML_BUSMON_3_BASE 0x40A000ull
+#define DCORE0_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_BUSMON_3_SECTION 0x1000
+#define DCORE0_TPC2_QM_ARC_RTT_BASE 0x40B000ull
+#define DCORE0_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_TPC2_QM_ARC_RTT_SECTION 0x35000
+#define DCORE0_TPC2_EML_CFG_BASE 0x440000ull
+#define DCORE0_TPC2_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_CFG_SECTION 0xE800
+#define DCORE0_TPC2_EML_CFG_SPECIAL_BASE 0x440E80ull
+#define DCORE0_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x441000ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC2_EML_TPC_CFG_BASE 0x441000ull
+#define DCORE0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_TPC_CFG_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x441050ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x4410A0ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x4410F0ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x441140ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x441190ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x4411E0ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x441230ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x441280ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x4412D0ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x441320ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x441370ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x4413C0ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x441410ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x441460ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x4414B0ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x441500ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_BASE 0x441508ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x4415DCull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x44162Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x44167Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x4416CCull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x44171Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x44176Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x4417BCull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x44180Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x44185Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x4418ACull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x4418FCull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x44194Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x44199Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x4419ECull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x441A3Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x441A8Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x441ADCull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_BASE 0x441AE4ull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE0_TPC2_EML_TPC_CFG_AXUSER_BASE 0x441E00ull
+#define DCORE0_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x441E80ull
+#define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC2_EML_QM_DCCM_BASE 0x442000ull
+#define DCORE0_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC2_EML_QM_DCCM_SECTION 0x8000
+#define DCORE0_TPC2_EML_QM_ARCAUX_BASE 0x44A000ull
+#define DCORE0_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x44AE80ull
+#define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE0_TPC2_EML_TPC_QM_BASE 0x44C000ull
+#define DCORE0_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_TPC_QM_SECTION 0x9000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x44C900ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x44C908ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x44C910ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x44C918ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x44C920ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x44C928ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x44C930ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x44C938ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x44C940ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x44C948ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x44C950ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x44C958ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x44C960ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x44C968ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x44C970ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x44C978ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x44CB00ull
+#define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x44CB80ull
+#define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x44CC00ull
+#define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x44CC80ull
+#define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_TPC2_EML_TPC_QM_CGM_BASE 0x44CD80ull
+#define DCORE0_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC2_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE0_TPC2_EML_TPC_QM_SPECIAL_BASE 0x44CE80ull
+#define DCORE0_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE0_TPC2_EML_CS_BASE 0x5FF000ull
+#define DCORE0_TPC2_EML_CS_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_CS_SECTION 0x1000
+#define DCORE0_TPC3_ROM_TABLE_BASE 0x600000ull
+#define DCORE0_TPC3_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_ROM_TABLE_SECTION 0x1000
+#define DCORE0_TPC3_EML_SPMU_BASE 0x601000ull
+#define DCORE0_TPC3_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_SPMU_SECTION 0x1000
+#define DCORE0_TPC3_EML_ETF_BASE 0x602000ull
+#define DCORE0_TPC3_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_ETF_SECTION 0x1000
+#define DCORE0_TPC3_EML_STM_BASE 0x603000ull
+#define DCORE0_TPC3_EML_STM_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_STM_SECTION 0x2000
+#define DCORE0_TPC3_EML_CTI_BASE 0x605000ull
+#define DCORE0_TPC3_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_CTI_SECTION 0x1000
+#define DCORE0_TPC3_EML_FUNNEL_BASE 0x606000ull
+#define DCORE0_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_FUNNEL_SECTION 0x1000
+#define DCORE0_TPC3_EML_BUSMON_0_BASE 0x607000ull
+#define DCORE0_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_BUSMON_0_SECTION 0x1000
+#define DCORE0_TPC3_EML_BUSMON_1_BASE 0x608000ull
+#define DCORE0_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_BUSMON_1_SECTION 0x1000
+#define DCORE0_TPC3_EML_BUSMON_2_BASE 0x609000ull
+#define DCORE0_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_BUSMON_2_SECTION 0x1000
+#define DCORE0_TPC3_EML_BUSMON_3_BASE 0x60A000ull
+#define DCORE0_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_BUSMON_3_SECTION 0x1000
+#define DCORE0_TPC3_QM_ARC_RTT_BASE 0x60B000ull
+#define DCORE0_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_TPC3_QM_ARC_RTT_SECTION 0x35000
+#define DCORE0_TPC3_EML_CFG_BASE 0x640000ull
+#define DCORE0_TPC3_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_CFG_SECTION 0xE800
+#define DCORE0_TPC3_EML_CFG_SPECIAL_BASE 0x640E80ull
+#define DCORE0_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x641000ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC3_EML_TPC_CFG_BASE 0x641000ull
+#define DCORE0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_TPC_CFG_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x641050ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x6410A0ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x6410F0ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x641140ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x641190ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x6411E0ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x641230ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x641280ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x6412D0ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x641320ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x641370ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x6413C0ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x641410ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x641460ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x6414B0ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x641500ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_BASE 0x641508ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x6415DCull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x64162Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x64167Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x6416CCull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x64171Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x64176Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x6417BCull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x64180Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x64185Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x6418ACull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x6418FCull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x64194Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x64199Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x6419ECull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x641A3Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x641A8Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x641ADCull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_BASE 0x641AE4ull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE0_TPC3_EML_TPC_CFG_AXUSER_BASE 0x641E00ull
+#define DCORE0_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x641E80ull
+#define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC3_EML_QM_DCCM_BASE 0x642000ull
+#define DCORE0_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC3_EML_QM_DCCM_SECTION 0x8000
+#define DCORE0_TPC3_EML_QM_ARCAUX_BASE 0x64A000ull
+#define DCORE0_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x64AE80ull
+#define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE0_TPC3_EML_TPC_QM_BASE 0x64C000ull
+#define DCORE0_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_TPC_QM_SECTION 0x9000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x64C900ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x64C908ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x64C910ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x64C918ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x64C920ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x64C928ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x64C930ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x64C938ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x64C940ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x64C948ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x64C950ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x64C958ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x64C960ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x64C968ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x64C970ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x64C978ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x64CB00ull
+#define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x64CB80ull
+#define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x64CC00ull
+#define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x64CC80ull
+#define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_TPC3_EML_TPC_QM_CGM_BASE 0x64CD80ull
+#define DCORE0_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC3_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE0_TPC3_EML_TPC_QM_SPECIAL_BASE 0x64CE80ull
+#define DCORE0_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE0_TPC3_EML_CS_BASE 0x7FF000ull
+#define DCORE0_TPC3_EML_CS_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_CS_SECTION 0x1000
+#define DCORE0_TPC4_ROM_TABLE_BASE 0x800000ull
+#define DCORE0_TPC4_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_ROM_TABLE_SECTION 0x1000
+#define DCORE0_TPC4_EML_SPMU_BASE 0x801000ull
+#define DCORE0_TPC4_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_SPMU_SECTION 0x1000
+#define DCORE0_TPC4_EML_ETF_BASE 0x802000ull
+#define DCORE0_TPC4_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_ETF_SECTION 0x1000
+#define DCORE0_TPC4_EML_STM_BASE 0x803000ull
+#define DCORE0_TPC4_EML_STM_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_STM_SECTION 0x2000
+#define DCORE0_TPC4_EML_CTI_BASE 0x805000ull
+#define DCORE0_TPC4_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_CTI_SECTION 0x1000
+#define DCORE0_TPC4_EML_FUNNEL_BASE 0x806000ull
+#define DCORE0_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_FUNNEL_SECTION 0x1000
+#define DCORE0_TPC4_EML_BUSMON_0_BASE 0x807000ull
+#define DCORE0_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_BUSMON_0_SECTION 0x1000
+#define DCORE0_TPC4_EML_BUSMON_1_BASE 0x808000ull
+#define DCORE0_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_BUSMON_1_SECTION 0x1000
+#define DCORE0_TPC4_EML_BUSMON_2_BASE 0x809000ull
+#define DCORE0_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_BUSMON_2_SECTION 0x1000
+#define DCORE0_TPC4_EML_BUSMON_3_BASE 0x80A000ull
+#define DCORE0_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_BUSMON_3_SECTION 0x1000
+#define DCORE0_TPC4_QM_ARC_RTT_BASE 0x80B000ull
+#define DCORE0_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_TPC4_QM_ARC_RTT_SECTION 0x35000
+#define DCORE0_TPC4_EML_CFG_BASE 0x840000ull
+#define DCORE0_TPC4_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_CFG_SECTION 0xE800
+#define DCORE0_TPC4_EML_CFG_SPECIAL_BASE 0x840E80ull
+#define DCORE0_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x841000ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC4_EML_TPC_CFG_BASE 0x841000ull
+#define DCORE0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_TPC_CFG_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x841050ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x8410A0ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x8410F0ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x841140ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x841190ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x8411E0ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x841230ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x841280ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x8412D0ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x841320ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x841370ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x8413C0ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x841410ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x841460ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x8414B0ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x841500ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_BASE 0x841508ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x8415DCull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x84162Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x84167Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x8416CCull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x84171Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x84176Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x8417BCull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x84180Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x84185Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x8418ACull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x8418FCull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x84194Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x84199Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x8419ECull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x841A3Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x841A8Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x841ADCull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_BASE 0x841AE4ull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE0_TPC4_EML_TPC_CFG_AXUSER_BASE 0x841E00ull
+#define DCORE0_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x841E80ull
+#define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC4_EML_QM_DCCM_BASE 0x842000ull
+#define DCORE0_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC4_EML_QM_DCCM_SECTION 0x8000
+#define DCORE0_TPC4_EML_QM_ARCAUX_BASE 0x84A000ull
+#define DCORE0_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x84AE80ull
+#define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE0_TPC4_EML_TPC_QM_BASE 0x84C000ull
+#define DCORE0_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_TPC_QM_SECTION 0x9000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x84C900ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x84C908ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x84C910ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x84C918ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x84C920ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x84C928ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x84C930ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x84C938ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x84C940ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x84C948ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x84C950ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x84C958ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x84C960ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x84C968ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x84C970ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x84C978ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x84CB00ull
+#define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x84CB80ull
+#define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x84CC00ull
+#define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x84CC80ull
+#define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_TPC4_EML_TPC_QM_CGM_BASE 0x84CD80ull
+#define DCORE0_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC4_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE0_TPC4_EML_TPC_QM_SPECIAL_BASE 0x84CE80ull
+#define DCORE0_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE0_TPC4_EML_CS_BASE 0x9FF000ull
+#define DCORE0_TPC4_EML_CS_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_CS_SECTION 0x1000
+#define DCORE0_TPC5_ROM_TABLE_BASE 0xA00000ull
+#define DCORE0_TPC5_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_ROM_TABLE_SECTION 0x1000
+#define DCORE0_TPC5_EML_SPMU_BASE 0xA01000ull
+#define DCORE0_TPC5_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_SPMU_SECTION 0x1000
+#define DCORE0_TPC5_EML_ETF_BASE 0xA02000ull
+#define DCORE0_TPC5_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_ETF_SECTION 0x1000
+#define DCORE0_TPC5_EML_STM_BASE 0xA03000ull
+#define DCORE0_TPC5_EML_STM_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_STM_SECTION 0x2000
+#define DCORE0_TPC5_EML_CTI_BASE 0xA05000ull
+#define DCORE0_TPC5_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_CTI_SECTION 0x1000
+#define DCORE0_TPC5_EML_FUNNEL_BASE 0xA06000ull
+#define DCORE0_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_FUNNEL_SECTION 0x1000
+#define DCORE0_TPC5_EML_BUSMON_0_BASE 0xA07000ull
+#define DCORE0_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_BUSMON_0_SECTION 0x1000
+#define DCORE0_TPC5_EML_BUSMON_1_BASE 0xA08000ull
+#define DCORE0_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_BUSMON_1_SECTION 0x1000
+#define DCORE0_TPC5_EML_BUSMON_2_BASE 0xA09000ull
+#define DCORE0_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_BUSMON_2_SECTION 0x1000
+#define DCORE0_TPC5_EML_BUSMON_3_BASE 0xA0A000ull
+#define DCORE0_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_BUSMON_3_SECTION 0x1000
+#define DCORE0_TPC5_QM_ARC_RTT_BASE 0xA0B000ull
+#define DCORE0_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_TPC5_QM_ARC_RTT_SECTION 0x35000
+#define DCORE0_TPC5_EML_CFG_BASE 0xA40000ull
+#define DCORE0_TPC5_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_CFG_SECTION 0xE800
+#define DCORE0_TPC5_EML_CFG_SPECIAL_BASE 0xA40E80ull
+#define DCORE0_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0xA41000ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC5_EML_TPC_CFG_BASE 0xA41000ull
+#define DCORE0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_TPC_CFG_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0xA41050ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0xA410A0ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0xA410F0ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0xA41140ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0xA41190ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0xA411E0ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0xA41230ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0xA41280ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0xA412D0ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0xA41320ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0xA41370ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0xA413C0ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0xA41410ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0xA41460ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0xA414B0ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0xA41500ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_BASE 0xA41508ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0xA415DCull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0xA4162Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0xA4167Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0xA416CCull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0xA4171Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0xA4176Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0xA417BCull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0xA4180Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0xA4185Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0xA418ACull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0xA418FCull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0xA4194Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0xA4199Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0xA419ECull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0xA41A3Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0xA41A8Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0xA41ADCull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_BASE 0xA41AE4ull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE0_TPC5_EML_TPC_CFG_AXUSER_BASE 0xA41E00ull
+#define DCORE0_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_BASE 0xA41E80ull
+#define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC5_EML_QM_DCCM_BASE 0xA42000ull
+#define DCORE0_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC5_EML_QM_DCCM_SECTION 0x8000
+#define DCORE0_TPC5_EML_QM_ARCAUX_BASE 0xA4A000ull
+#define DCORE0_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0xA4AE80ull
+#define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE0_TPC5_EML_TPC_QM_BASE 0xA4C000ull
+#define DCORE0_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_TPC_QM_SECTION 0x9000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0xA4C900ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0xA4C908ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0xA4C910ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0xA4C918ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0xA4C920ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0xA4C928ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0xA4C930ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0xA4C938ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0xA4C940ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0xA4C948ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0xA4C950ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0xA4C958ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0xA4C960ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0xA4C968ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0xA4C970ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0xA4C978ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0xA4CB00ull
+#define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0xA4CB80ull
+#define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_BASE 0xA4CC00ull
+#define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_BASE 0xA4CC80ull
+#define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_TPC5_EML_TPC_QM_CGM_BASE 0xA4CD80ull
+#define DCORE0_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC5_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE0_TPC5_EML_TPC_QM_SPECIAL_BASE 0xA4CE80ull
+#define DCORE0_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE0_TPC5_EML_CS_BASE 0xBFF000ull
+#define DCORE0_TPC5_EML_CS_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_CS_SECTION 0x1000
+#define DCORE0_TPC6_ROM_TABLE_BASE 0xC00000ull
+#define DCORE0_TPC6_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_ROM_TABLE_SECTION 0x1000
+#define DCORE0_TPC6_EML_SPMU_BASE 0xC01000ull
+#define DCORE0_TPC6_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_SPMU_SECTION 0x1000
+#define DCORE0_TPC6_EML_ETF_BASE 0xC02000ull
+#define DCORE0_TPC6_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_ETF_SECTION 0x1000
+#define DCORE0_TPC6_EML_STM_BASE 0xC03000ull
+#define DCORE0_TPC6_EML_STM_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_STM_SECTION 0x2000
+#define DCORE0_TPC6_EML_CTI_BASE 0xC05000ull
+#define DCORE0_TPC6_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_CTI_SECTION 0x1000
+#define DCORE0_TPC6_EML_FUNNEL_BASE 0xC06000ull
+#define DCORE0_TPC6_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_FUNNEL_SECTION 0x1000
+#define DCORE0_TPC6_EML_BUSMON_0_BASE 0xC07000ull
+#define DCORE0_TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_BUSMON_0_SECTION 0x1000
+#define DCORE0_TPC6_EML_BUSMON_1_BASE 0xC08000ull
+#define DCORE0_TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_BUSMON_1_SECTION 0x1000
+#define DCORE0_TPC6_EML_BUSMON_2_BASE 0xC09000ull
+#define DCORE0_TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_BUSMON_2_SECTION 0x1000
+#define DCORE0_TPC6_EML_BUSMON_3_BASE 0xC0A000ull
+#define DCORE0_TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_BUSMON_3_SECTION 0x1000
+#define DCORE0_TPC6_QM_ARC_RTT_BASE 0xC0B000ull
+#define DCORE0_TPC6_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_TPC6_QM_ARC_RTT_SECTION 0x35000
+#define DCORE0_TPC6_EML_CFG_BASE 0xC40000ull
+#define DCORE0_TPC6_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_CFG_SECTION 0xE800
+#define DCORE0_TPC6_EML_CFG_SPECIAL_BASE 0xC40E80ull
+#define DCORE0_TPC6_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0xC41000ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC6_EML_TPC_CFG_BASE 0xC41000ull
+#define DCORE0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_TPC_CFG_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0xC41050ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0xC410A0ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0xC410F0ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0xC41140ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0xC41190ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0xC411E0ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0xC41230ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0xC41280ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0xC412D0ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0xC41320ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0xC41370ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0xC413C0ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0xC41410ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0xC41460ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0xC414B0ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0xC41500ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_BASE 0xC41508ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_BASE 0xC415DCull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_BASE 0xC4162Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_BASE 0xC4167Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_BASE 0xC416CCull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_BASE 0xC4171Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_BASE 0xC4176Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_BASE 0xC417BCull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_BASE 0xC4180Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_BASE 0xC4185Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_BASE 0xC418ACull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_BASE 0xC418FCull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_BASE 0xC4194Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_BASE 0xC4199Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_BASE 0xC419ECull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_BASE 0xC41A3Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_BASE 0xC41A8Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0xC41ADCull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_BASE 0xC41AE4ull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC6_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE0_TPC6_EML_TPC_CFG_AXUSER_BASE 0xC41E00ull
+#define DCORE0_TPC6_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_BASE 0xC41E80ull
+#define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC6_EML_QM_DCCM_BASE 0xC42000ull
+#define DCORE0_TPC6_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC6_EML_QM_DCCM_SECTION 0x8000
+#define DCORE0_TPC6_EML_QM_ARCAUX_BASE 0xC4A000ull
+#define DCORE0_TPC6_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_BASE 0xC4AE80ull
+#define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE0_TPC6_EML_TPC_QM_BASE 0xC4C000ull
+#define DCORE0_TPC6_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_TPC_QM_SECTION 0x9000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0xC4C900ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0xC4C908ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0xC4C910ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0xC4C918ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0xC4C920ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0xC4C928ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0xC4C930ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0xC4C938ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0xC4C940ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0xC4C948ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0xC4C950ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0xC4C958ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0xC4C960ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0xC4C968ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0xC4C970ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0xC4C978ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_BASE 0xC4CB00ull
+#define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_BASE 0xC4CB80ull
+#define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_BASE 0xC4CC00ull
+#define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_BASE 0xC4CC80ull
+#define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_TPC6_EML_TPC_QM_CGM_BASE 0xC4CD80ull
+#define DCORE0_TPC6_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC6_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE0_TPC6_EML_TPC_QM_SPECIAL_BASE 0xC4CE80ull
+#define DCORE0_TPC6_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE0_TPC6_EML_CS_BASE 0xDFF000ull
+#define DCORE0_TPC6_EML_CS_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_CS_SECTION 0x201000
+#define DCORE1_TPC0_ROM_TABLE_BASE 0x1000000ull
+#define DCORE1_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_ROM_TABLE_SECTION 0x1000
+#define DCORE1_TPC0_EML_SPMU_BASE 0x1001000ull
+#define DCORE1_TPC0_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_SPMU_SECTION 0x1000
+#define DCORE1_TPC0_EML_ETF_BASE 0x1002000ull
+#define DCORE1_TPC0_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_ETF_SECTION 0x1000
+#define DCORE1_TPC0_EML_STM_BASE 0x1003000ull
+#define DCORE1_TPC0_EML_STM_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_STM_SECTION 0x2000
+#define DCORE1_TPC0_EML_CTI_BASE 0x1005000ull
+#define DCORE1_TPC0_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_CTI_SECTION 0x1000
+#define DCORE1_TPC0_EML_FUNNEL_BASE 0x1006000ull
+#define DCORE1_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_FUNNEL_SECTION 0x1000
+#define DCORE1_TPC0_EML_BUSMON_0_BASE 0x1007000ull
+#define DCORE1_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_BUSMON_0_SECTION 0x1000
+#define DCORE1_TPC0_EML_BUSMON_1_BASE 0x1008000ull
+#define DCORE1_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_BUSMON_1_SECTION 0x1000
+#define DCORE1_TPC0_EML_BUSMON_2_BASE 0x1009000ull
+#define DCORE1_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_BUSMON_2_SECTION 0x1000
+#define DCORE1_TPC0_EML_BUSMON_3_BASE 0x100A000ull
+#define DCORE1_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_BUSMON_3_SECTION 0x1000
+#define DCORE1_TPC0_QM_ARC_RTT_BASE 0x100B000ull
+#define DCORE1_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_TPC0_QM_ARC_RTT_SECTION 0x35000
+#define DCORE1_TPC0_EML_CFG_BASE 0x1040000ull
+#define DCORE1_TPC0_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_CFG_SECTION 0xE800
+#define DCORE1_TPC0_EML_CFG_SPECIAL_BASE 0x1040E80ull
+#define DCORE1_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1041000ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC0_EML_TPC_CFG_BASE 0x1041000ull
+#define DCORE1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_TPC_CFG_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1041050ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x10410A0ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x10410F0ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1041140ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1041190ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x10411E0ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1041230ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1041280ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x10412D0ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1041320ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1041370ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x10413C0ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1041410ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1041460ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x10414B0ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1041500ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_BASE 0x1041508ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x10415DCull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x104162Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x104167Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x10416CCull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x104171Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x104176Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x10417BCull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x104180Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x104185Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x10418ACull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x10418FCull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x104194Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x104199Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x10419ECull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1041A3Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1041A8Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1041ADCull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_BASE 0x1041AE4ull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE1_TPC0_EML_TPC_CFG_AXUSER_BASE 0x1041E00ull
+#define DCORE1_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x1041E80ull
+#define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC0_EML_QM_DCCM_BASE 0x1042000ull
+#define DCORE1_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC0_EML_QM_DCCM_SECTION 0x8000
+#define DCORE1_TPC0_EML_QM_ARCAUX_BASE 0x104A000ull
+#define DCORE1_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x104AE80ull
+#define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE1_TPC0_EML_TPC_QM_BASE 0x104C000ull
+#define DCORE1_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_TPC_QM_SECTION 0x9000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x104C900ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x104C908ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x104C910ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x104C918ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x104C920ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x104C928ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x104C930ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x104C938ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x104C940ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x104C948ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x104C950ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x104C958ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x104C960ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x104C968ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x104C970ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x104C978ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x104CB00ull
+#define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x104CB80ull
+#define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x104CC00ull
+#define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x104CC80ull
+#define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_TPC0_EML_TPC_QM_CGM_BASE 0x104CD80ull
+#define DCORE1_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC0_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE1_TPC0_EML_TPC_QM_SPECIAL_BASE 0x104CE80ull
+#define DCORE1_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE1_TPC0_EML_CS_BASE 0x11FF000ull
+#define DCORE1_TPC0_EML_CS_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_CS_SECTION 0x1000
+#define DCORE1_TPC1_ROM_TABLE_BASE 0x1200000ull
+#define DCORE1_TPC1_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_ROM_TABLE_SECTION 0x1000
+#define DCORE1_TPC1_EML_SPMU_BASE 0x1201000ull
+#define DCORE1_TPC1_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_SPMU_SECTION 0x1000
+#define DCORE1_TPC1_EML_ETF_BASE 0x1202000ull
+#define DCORE1_TPC1_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_ETF_SECTION 0x1000
+#define DCORE1_TPC1_EML_STM_BASE 0x1203000ull
+#define DCORE1_TPC1_EML_STM_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_STM_SECTION 0x2000
+#define DCORE1_TPC1_EML_CTI_BASE 0x1205000ull
+#define DCORE1_TPC1_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_CTI_SECTION 0x1000
+#define DCORE1_TPC1_EML_FUNNEL_BASE 0x1206000ull
+#define DCORE1_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_FUNNEL_SECTION 0x1000
+#define DCORE1_TPC1_EML_BUSMON_0_BASE 0x1207000ull
+#define DCORE1_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_BUSMON_0_SECTION 0x1000
+#define DCORE1_TPC1_EML_BUSMON_1_BASE 0x1208000ull
+#define DCORE1_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_BUSMON_1_SECTION 0x1000
+#define DCORE1_TPC1_EML_BUSMON_2_BASE 0x1209000ull
+#define DCORE1_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_BUSMON_2_SECTION 0x1000
+#define DCORE1_TPC1_EML_BUSMON_3_BASE 0x120A000ull
+#define DCORE1_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_BUSMON_3_SECTION 0x1000
+#define DCORE1_TPC1_QM_ARC_RTT_BASE 0x120B000ull
+#define DCORE1_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_TPC1_QM_ARC_RTT_SECTION 0x35000
+#define DCORE1_TPC1_EML_CFG_BASE 0x1240000ull
+#define DCORE1_TPC1_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_CFG_SECTION 0xE800
+#define DCORE1_TPC1_EML_CFG_SPECIAL_BASE 0x1240E80ull
+#define DCORE1_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1241000ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC1_EML_TPC_CFG_BASE 0x1241000ull
+#define DCORE1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_TPC_CFG_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1241050ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x12410A0ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x12410F0ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1241140ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1241190ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x12411E0ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1241230ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1241280ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x12412D0ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1241320ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1241370ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x12413C0ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1241410ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1241460ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x12414B0ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1241500ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_BASE 0x1241508ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x12415DCull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x124162Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x124167Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x12416CCull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x124171Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x124176Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x12417BCull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x124180Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x124185Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x12418ACull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x12418FCull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x124194Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x124199Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x12419ECull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1241A3Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1241A8Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1241ADCull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_BASE 0x1241AE4ull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE1_TPC1_EML_TPC_CFG_AXUSER_BASE 0x1241E00ull
+#define DCORE1_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x1241E80ull
+#define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC1_EML_QM_DCCM_BASE 0x1242000ull
+#define DCORE1_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC1_EML_QM_DCCM_SECTION 0x8000
+#define DCORE1_TPC1_EML_QM_ARCAUX_BASE 0x124A000ull
+#define DCORE1_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x124AE80ull
+#define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE1_TPC1_EML_TPC_QM_BASE 0x124C000ull
+#define DCORE1_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_TPC_QM_SECTION 0x9000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x124C900ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x124C908ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x124C910ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x124C918ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x124C920ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x124C928ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x124C930ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x124C938ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x124C940ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x124C948ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x124C950ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x124C958ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x124C960ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x124C968ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x124C970ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x124C978ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x124CB00ull
+#define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x124CB80ull
+#define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x124CC00ull
+#define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x124CC80ull
+#define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_TPC1_EML_TPC_QM_CGM_BASE 0x124CD80ull
+#define DCORE1_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC1_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE1_TPC1_EML_TPC_QM_SPECIAL_BASE 0x124CE80ull
+#define DCORE1_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE1_TPC1_EML_CS_BASE 0x13FF000ull
+#define DCORE1_TPC1_EML_CS_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_CS_SECTION 0x1000
+#define DCORE1_TPC2_ROM_TABLE_BASE 0x1400000ull
+#define DCORE1_TPC2_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_ROM_TABLE_SECTION 0x1000
+#define DCORE1_TPC2_EML_SPMU_BASE 0x1401000ull
+#define DCORE1_TPC2_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_SPMU_SECTION 0x1000
+#define DCORE1_TPC2_EML_ETF_BASE 0x1402000ull
+#define DCORE1_TPC2_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_ETF_SECTION 0x1000
+#define DCORE1_TPC2_EML_STM_BASE 0x1403000ull
+#define DCORE1_TPC2_EML_STM_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_STM_SECTION 0x2000
+#define DCORE1_TPC2_EML_CTI_BASE 0x1405000ull
+#define DCORE1_TPC2_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_CTI_SECTION 0x1000
+#define DCORE1_TPC2_EML_FUNNEL_BASE 0x1406000ull
+#define DCORE1_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_FUNNEL_SECTION 0x1000
+#define DCORE1_TPC2_EML_BUSMON_0_BASE 0x1407000ull
+#define DCORE1_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_BUSMON_0_SECTION 0x1000
+#define DCORE1_TPC2_EML_BUSMON_1_BASE 0x1408000ull
+#define DCORE1_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_BUSMON_1_SECTION 0x1000
+#define DCORE1_TPC2_EML_BUSMON_2_BASE 0x1409000ull
+#define DCORE1_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_BUSMON_2_SECTION 0x1000
+#define DCORE1_TPC2_EML_BUSMON_3_BASE 0x140A000ull
+#define DCORE1_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_BUSMON_3_SECTION 0x1000
+#define DCORE1_TPC2_QM_ARC_RTT_BASE 0x140B000ull
+#define DCORE1_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_TPC2_QM_ARC_RTT_SECTION 0x35000
+#define DCORE1_TPC2_EML_CFG_BASE 0x1440000ull
+#define DCORE1_TPC2_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_CFG_SECTION 0xE800
+#define DCORE1_TPC2_EML_CFG_SPECIAL_BASE 0x1440E80ull
+#define DCORE1_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1441000ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC2_EML_TPC_CFG_BASE 0x1441000ull
+#define DCORE1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_TPC_CFG_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1441050ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x14410A0ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x14410F0ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1441140ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1441190ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x14411E0ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1441230ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1441280ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x14412D0ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1441320ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1441370ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x14413C0ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1441410ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1441460ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x14414B0ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1441500ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_BASE 0x1441508ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x14415DCull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x144162Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x144167Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x14416CCull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x144171Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x144176Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x14417BCull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x144180Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x144185Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x14418ACull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x14418FCull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x144194Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x144199Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x14419ECull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1441A3Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1441A8Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1441ADCull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_BASE 0x1441AE4ull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE1_TPC2_EML_TPC_CFG_AXUSER_BASE 0x1441E00ull
+#define DCORE1_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x1441E80ull
+#define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC2_EML_QM_DCCM_BASE 0x1442000ull
+#define DCORE1_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC2_EML_QM_DCCM_SECTION 0x8000
+#define DCORE1_TPC2_EML_QM_ARCAUX_BASE 0x144A000ull
+#define DCORE1_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x144AE80ull
+#define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE1_TPC2_EML_TPC_QM_BASE 0x144C000ull
+#define DCORE1_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_TPC_QM_SECTION 0x9000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x144C900ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x144C908ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x144C910ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x144C918ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x144C920ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x144C928ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x144C930ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x144C938ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x144C940ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x144C948ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x144C950ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x144C958ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x144C960ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x144C968ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x144C970ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x144C978ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x144CB00ull
+#define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x144CB80ull
+#define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x144CC00ull
+#define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x144CC80ull
+#define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_TPC2_EML_TPC_QM_CGM_BASE 0x144CD80ull
+#define DCORE1_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC2_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE1_TPC2_EML_TPC_QM_SPECIAL_BASE 0x144CE80ull
+#define DCORE1_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE1_TPC2_EML_CS_BASE 0x15FF000ull
+#define DCORE1_TPC2_EML_CS_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_CS_SECTION 0x1000
+#define DCORE1_TPC3_ROM_TABLE_BASE 0x1600000ull
+#define DCORE1_TPC3_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_ROM_TABLE_SECTION 0x1000
+#define DCORE1_TPC3_EML_SPMU_BASE 0x1601000ull
+#define DCORE1_TPC3_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_SPMU_SECTION 0x1000
+#define DCORE1_TPC3_EML_ETF_BASE 0x1602000ull
+#define DCORE1_TPC3_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_ETF_SECTION 0x1000
+#define DCORE1_TPC3_EML_STM_BASE 0x1603000ull
+#define DCORE1_TPC3_EML_STM_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_STM_SECTION 0x2000
+#define DCORE1_TPC3_EML_CTI_BASE 0x1605000ull
+#define DCORE1_TPC3_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_CTI_SECTION 0x1000
+#define DCORE1_TPC3_EML_FUNNEL_BASE 0x1606000ull
+#define DCORE1_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_FUNNEL_SECTION 0x1000
+#define DCORE1_TPC3_EML_BUSMON_0_BASE 0x1607000ull
+#define DCORE1_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_BUSMON_0_SECTION 0x1000
+#define DCORE1_TPC3_EML_BUSMON_1_BASE 0x1608000ull
+#define DCORE1_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_BUSMON_1_SECTION 0x1000
+#define DCORE1_TPC3_EML_BUSMON_2_BASE 0x1609000ull
+#define DCORE1_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_BUSMON_2_SECTION 0x1000
+#define DCORE1_TPC3_EML_BUSMON_3_BASE 0x160A000ull
+#define DCORE1_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_BUSMON_3_SECTION 0x1000
+#define DCORE1_TPC3_QM_ARC_RTT_BASE 0x160B000ull
+#define DCORE1_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_TPC3_QM_ARC_RTT_SECTION 0x35000
+#define DCORE1_TPC3_EML_CFG_BASE 0x1640000ull
+#define DCORE1_TPC3_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_CFG_SECTION 0xE800
+#define DCORE1_TPC3_EML_CFG_SPECIAL_BASE 0x1640E80ull
+#define DCORE1_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1641000ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC3_EML_TPC_CFG_BASE 0x1641000ull
+#define DCORE1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_TPC_CFG_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1641050ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x16410A0ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x16410F0ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1641140ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1641190ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x16411E0ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1641230ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1641280ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x16412D0ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1641320ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1641370ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x16413C0ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1641410ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1641460ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x16414B0ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1641500ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_BASE 0x1641508ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x16415DCull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x164162Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x164167Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x16416CCull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x164171Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x164176Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x16417BCull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x164180Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x164185Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x16418ACull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x16418FCull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x164194Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x164199Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x16419ECull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1641A3Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1641A8Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1641ADCull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_BASE 0x1641AE4ull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE1_TPC3_EML_TPC_CFG_AXUSER_BASE 0x1641E00ull
+#define DCORE1_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x1641E80ull
+#define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC3_EML_QM_DCCM_BASE 0x1642000ull
+#define DCORE1_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC3_EML_QM_DCCM_SECTION 0x8000
+#define DCORE1_TPC3_EML_QM_ARCAUX_BASE 0x164A000ull
+#define DCORE1_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x164AE80ull
+#define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE1_TPC3_EML_TPC_QM_BASE 0x164C000ull
+#define DCORE1_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_TPC_QM_SECTION 0x9000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x164C900ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x164C908ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x164C910ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x164C918ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x164C920ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x164C928ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x164C930ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x164C938ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x164C940ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x164C948ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x164C950ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x164C958ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x164C960ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x164C968ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x164C970ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x164C978ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x164CB00ull
+#define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x164CB80ull
+#define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x164CC00ull
+#define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x164CC80ull
+#define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_TPC3_EML_TPC_QM_CGM_BASE 0x164CD80ull
+#define DCORE1_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC3_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE1_TPC3_EML_TPC_QM_SPECIAL_BASE 0x164CE80ull
+#define DCORE1_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE1_TPC3_EML_CS_BASE 0x17FF000ull
+#define DCORE1_TPC3_EML_CS_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_CS_SECTION 0x1000
+#define DCORE1_TPC4_ROM_TABLE_BASE 0x1800000ull
+#define DCORE1_TPC4_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_ROM_TABLE_SECTION 0x1000
+#define DCORE1_TPC4_EML_SPMU_BASE 0x1801000ull
+#define DCORE1_TPC4_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_SPMU_SECTION 0x1000
+#define DCORE1_TPC4_EML_ETF_BASE 0x1802000ull
+#define DCORE1_TPC4_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_ETF_SECTION 0x1000
+#define DCORE1_TPC4_EML_STM_BASE 0x1803000ull
+#define DCORE1_TPC4_EML_STM_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_STM_SECTION 0x2000
+#define DCORE1_TPC4_EML_CTI_BASE 0x1805000ull
+#define DCORE1_TPC4_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_CTI_SECTION 0x1000
+#define DCORE1_TPC4_EML_FUNNEL_BASE 0x1806000ull
+#define DCORE1_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_FUNNEL_SECTION 0x1000
+#define DCORE1_TPC4_EML_BUSMON_0_BASE 0x1807000ull
+#define DCORE1_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_BUSMON_0_SECTION 0x1000
+#define DCORE1_TPC4_EML_BUSMON_1_BASE 0x1808000ull
+#define DCORE1_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_BUSMON_1_SECTION 0x1000
+#define DCORE1_TPC4_EML_BUSMON_2_BASE 0x1809000ull
+#define DCORE1_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_BUSMON_2_SECTION 0x1000
+#define DCORE1_TPC4_EML_BUSMON_3_BASE 0x180A000ull
+#define DCORE1_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_BUSMON_3_SECTION 0x1000
+#define DCORE1_TPC4_QM_ARC_RTT_BASE 0x180B000ull
+#define DCORE1_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_TPC4_QM_ARC_RTT_SECTION 0x35000
+#define DCORE1_TPC4_EML_CFG_BASE 0x1840000ull
+#define DCORE1_TPC4_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_CFG_SECTION 0xE800
+#define DCORE1_TPC4_EML_CFG_SPECIAL_BASE 0x1840E80ull
+#define DCORE1_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1841000ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC4_EML_TPC_CFG_BASE 0x1841000ull
+#define DCORE1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_TPC_CFG_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1841050ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x18410A0ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x18410F0ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1841140ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1841190ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x18411E0ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1841230ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1841280ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x18412D0ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1841320ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1841370ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x18413C0ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1841410ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1841460ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x18414B0ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1841500ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_BASE 0x1841508ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x18415DCull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x184162Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x184167Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x18416CCull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x184171Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x184176Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x18417BCull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x184180Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x184185Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x18418ACull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x18418FCull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x184194Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x184199Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x18419ECull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1841A3Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1841A8Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1841ADCull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_BASE 0x1841AE4ull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE1_TPC4_EML_TPC_CFG_AXUSER_BASE 0x1841E00ull
+#define DCORE1_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x1841E80ull
+#define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC4_EML_QM_DCCM_BASE 0x1842000ull
+#define DCORE1_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC4_EML_QM_DCCM_SECTION 0x8000
+#define DCORE1_TPC4_EML_QM_ARCAUX_BASE 0x184A000ull
+#define DCORE1_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x184AE80ull
+#define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE1_TPC4_EML_TPC_QM_BASE 0x184C000ull
+#define DCORE1_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_TPC_QM_SECTION 0x9000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x184C900ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x184C908ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x184C910ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x184C918ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x184C920ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x184C928ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x184C930ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x184C938ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x184C940ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x184C948ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x184C950ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x184C958ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x184C960ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x184C968ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x184C970ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x184C978ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x184CB00ull
+#define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x184CB80ull
+#define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x184CC00ull
+#define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x184CC80ull
+#define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_TPC4_EML_TPC_QM_CGM_BASE 0x184CD80ull
+#define DCORE1_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC4_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE1_TPC4_EML_TPC_QM_SPECIAL_BASE 0x184CE80ull
+#define DCORE1_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE1_TPC4_EML_CS_BASE 0x19FF000ull
+#define DCORE1_TPC4_EML_CS_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_CS_SECTION 0x1000
+#define DCORE1_TPC5_ROM_TABLE_BASE 0x1A00000ull
+#define DCORE1_TPC5_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_ROM_TABLE_SECTION 0x1000
+#define DCORE1_TPC5_EML_SPMU_BASE 0x1A01000ull
+#define DCORE1_TPC5_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_SPMU_SECTION 0x1000
+#define DCORE1_TPC5_EML_ETF_BASE 0x1A02000ull
+#define DCORE1_TPC5_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_ETF_SECTION 0x1000
+#define DCORE1_TPC5_EML_STM_BASE 0x1A03000ull
+#define DCORE1_TPC5_EML_STM_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_STM_SECTION 0x2000
+#define DCORE1_TPC5_EML_CTI_BASE 0x1A05000ull
+#define DCORE1_TPC5_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_CTI_SECTION 0x1000
+#define DCORE1_TPC5_EML_FUNNEL_BASE 0x1A06000ull
+#define DCORE1_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_FUNNEL_SECTION 0x1000
+#define DCORE1_TPC5_EML_BUSMON_0_BASE 0x1A07000ull
+#define DCORE1_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_BUSMON_0_SECTION 0x1000
+#define DCORE1_TPC5_EML_BUSMON_1_BASE 0x1A08000ull
+#define DCORE1_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_BUSMON_1_SECTION 0x1000
+#define DCORE1_TPC5_EML_BUSMON_2_BASE 0x1A09000ull
+#define DCORE1_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_BUSMON_2_SECTION 0x1000
+#define DCORE1_TPC5_EML_BUSMON_3_BASE 0x1A0A000ull
+#define DCORE1_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_BUSMON_3_SECTION 0x1000
+#define DCORE1_TPC5_QM_ARC_RTT_BASE 0x1A0B000ull
+#define DCORE1_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_TPC5_QM_ARC_RTT_SECTION 0x35000
+#define DCORE1_TPC5_EML_CFG_BASE 0x1A40000ull
+#define DCORE1_TPC5_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_CFG_SECTION 0xE800
+#define DCORE1_TPC5_EML_CFG_SPECIAL_BASE 0x1A40E80ull
+#define DCORE1_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1A41000ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC5_EML_TPC_CFG_BASE 0x1A41000ull
+#define DCORE1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_TPC_CFG_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1A41050ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1A410A0ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1A410F0ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1A41140ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1A41190ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1A411E0ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1A41230ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1A41280ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1A412D0ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1A41320ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1A41370ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1A413C0ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1A41410ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1A41460ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1A414B0ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1A41500ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_BASE 0x1A41508ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1A415DCull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1A4162Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1A4167Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1A416CCull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1A4171Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1A4176Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1A417BCull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1A4180Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1A4185Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1A418ACull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1A418FCull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1A4194Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1A4199Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1A419ECull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1A41A3Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1A41A8Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1A41ADCull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_BASE 0x1A41AE4ull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE1_TPC5_EML_TPC_CFG_AXUSER_BASE 0x1A41E00ull
+#define DCORE1_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x1A41E80ull
+#define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC5_EML_QM_DCCM_BASE 0x1A42000ull
+#define DCORE1_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC5_EML_QM_DCCM_SECTION 0x8000
+#define DCORE1_TPC5_EML_QM_ARCAUX_BASE 0x1A4A000ull
+#define DCORE1_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x1A4AE80ull
+#define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE1_TPC5_EML_TPC_QM_BASE 0x1A4C000ull
+#define DCORE1_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_TPC_QM_SECTION 0x9000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1A4C900ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1A4C908ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1A4C910ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1A4C918ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1A4C920ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1A4C928ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1A4C930ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1A4C938ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1A4C940ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1A4C948ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1A4C950ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1A4C958ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1A4C960ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1A4C968ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1A4C970ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1A4C978ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x1A4CB00ull
+#define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1A4CB80ull
+#define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x1A4CC00ull
+#define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x1A4CC80ull
+#define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_TPC5_EML_TPC_QM_CGM_BASE 0x1A4CD80ull
+#define DCORE1_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC5_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE1_TPC5_EML_TPC_QM_SPECIAL_BASE 0x1A4CE80ull
+#define DCORE1_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE1_TPC5_EML_CS_BASE 0x1BFF000ull
+#define DCORE1_TPC5_EML_CS_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_CS_SECTION 0x401000
+#define DCORE2_TPC0_ROM_TABLE_BASE 0x2000000ull
+#define DCORE2_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_ROM_TABLE_SECTION 0x1000
+#define DCORE2_TPC0_EML_SPMU_BASE 0x2001000ull
+#define DCORE2_TPC0_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_SPMU_SECTION 0x1000
+#define DCORE2_TPC0_EML_ETF_BASE 0x2002000ull
+#define DCORE2_TPC0_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_ETF_SECTION 0x1000
+#define DCORE2_TPC0_EML_STM_BASE 0x2003000ull
+#define DCORE2_TPC0_EML_STM_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_STM_SECTION 0x2000
+#define DCORE2_TPC0_EML_CTI_BASE 0x2005000ull
+#define DCORE2_TPC0_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_CTI_SECTION 0x1000
+#define DCORE2_TPC0_EML_FUNNEL_BASE 0x2006000ull
+#define DCORE2_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_FUNNEL_SECTION 0x1000
+#define DCORE2_TPC0_EML_BUSMON_0_BASE 0x2007000ull
+#define DCORE2_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_BUSMON_0_SECTION 0x1000
+#define DCORE2_TPC0_EML_BUSMON_1_BASE 0x2008000ull
+#define DCORE2_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_BUSMON_1_SECTION 0x1000
+#define DCORE2_TPC0_EML_BUSMON_2_BASE 0x2009000ull
+#define DCORE2_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_BUSMON_2_SECTION 0x1000
+#define DCORE2_TPC0_EML_BUSMON_3_BASE 0x200A000ull
+#define DCORE2_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_BUSMON_3_SECTION 0x1000
+#define DCORE2_TPC0_QM_ARC_RTT_BASE 0x200B000ull
+#define DCORE2_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_TPC0_QM_ARC_RTT_SECTION 0x35000
+#define DCORE2_TPC0_EML_CFG_BASE 0x2040000ull
+#define DCORE2_TPC0_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_CFG_SECTION 0xE800
+#define DCORE2_TPC0_EML_CFG_SPECIAL_BASE 0x2040E80ull
+#define DCORE2_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2041000ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC0_EML_TPC_CFG_BASE 0x2041000ull
+#define DCORE2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_TPC_CFG_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2041050ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x20410A0ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x20410F0ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2041140ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2041190ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x20411E0ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2041230ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2041280ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x20412D0ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2041320ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2041370ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x20413C0ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2041410ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2041460ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x20414B0ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2041500ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_BASE 0x2041508ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x20415DCull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x204162Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x204167Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x20416CCull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x204171Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x204176Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x20417BCull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x204180Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x204185Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x20418ACull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x20418FCull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x204194Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x204199Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x20419ECull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2041A3Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2041A8Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2041ADCull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_BASE 0x2041AE4ull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE2_TPC0_EML_TPC_CFG_AXUSER_BASE 0x2041E00ull
+#define DCORE2_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x2041E80ull
+#define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC0_EML_QM_DCCM_BASE 0x2042000ull
+#define DCORE2_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC0_EML_QM_DCCM_SECTION 0x8000
+#define DCORE2_TPC0_EML_QM_ARCAUX_BASE 0x204A000ull
+#define DCORE2_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x204AE80ull
+#define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE2_TPC0_EML_TPC_QM_BASE 0x204C000ull
+#define DCORE2_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_TPC_QM_SECTION 0x9000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x204C900ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x204C908ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x204C910ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x204C918ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x204C920ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x204C928ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x204C930ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x204C938ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x204C940ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x204C948ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x204C950ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x204C958ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x204C960ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x204C968ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x204C970ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x204C978ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x204CB00ull
+#define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x204CB80ull
+#define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x204CC00ull
+#define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x204CC80ull
+#define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_TPC0_EML_TPC_QM_CGM_BASE 0x204CD80ull
+#define DCORE2_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC0_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE2_TPC0_EML_TPC_QM_SPECIAL_BASE 0x204CE80ull
+#define DCORE2_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE2_TPC0_EML_CS_BASE 0x21FF000ull
+#define DCORE2_TPC0_EML_CS_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_CS_SECTION 0x1000
+#define DCORE2_TPC1_ROM_TABLE_BASE 0x2200000ull
+#define DCORE2_TPC1_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_ROM_TABLE_SECTION 0x1000
+#define DCORE2_TPC1_EML_SPMU_BASE 0x2201000ull
+#define DCORE2_TPC1_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_SPMU_SECTION 0x1000
+#define DCORE2_TPC1_EML_ETF_BASE 0x2202000ull
+#define DCORE2_TPC1_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_ETF_SECTION 0x1000
+#define DCORE2_TPC1_EML_STM_BASE 0x2203000ull
+#define DCORE2_TPC1_EML_STM_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_STM_SECTION 0x2000
+#define DCORE2_TPC1_EML_CTI_BASE 0x2205000ull
+#define DCORE2_TPC1_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_CTI_SECTION 0x1000
+#define DCORE2_TPC1_EML_FUNNEL_BASE 0x2206000ull
+#define DCORE2_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_FUNNEL_SECTION 0x1000
+#define DCORE2_TPC1_EML_BUSMON_0_BASE 0x2207000ull
+#define DCORE2_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_BUSMON_0_SECTION 0x1000
+#define DCORE2_TPC1_EML_BUSMON_1_BASE 0x2208000ull
+#define DCORE2_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_BUSMON_1_SECTION 0x1000
+#define DCORE2_TPC1_EML_BUSMON_2_BASE 0x2209000ull
+#define DCORE2_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_BUSMON_2_SECTION 0x1000
+#define DCORE2_TPC1_EML_BUSMON_3_BASE 0x220A000ull
+#define DCORE2_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_BUSMON_3_SECTION 0x1000
+#define DCORE2_TPC1_QM_ARC_RTT_BASE 0x220B000ull
+#define DCORE2_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_TPC1_QM_ARC_RTT_SECTION 0x35000
+#define DCORE2_TPC1_EML_CFG_BASE 0x2240000ull
+#define DCORE2_TPC1_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_CFG_SECTION 0xE800
+#define DCORE2_TPC1_EML_CFG_SPECIAL_BASE 0x2240E80ull
+#define DCORE2_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2241000ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC1_EML_TPC_CFG_BASE 0x2241000ull
+#define DCORE2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_TPC_CFG_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2241050ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x22410A0ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x22410F0ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2241140ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2241190ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x22411E0ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2241230ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2241280ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x22412D0ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2241320ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2241370ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x22413C0ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2241410ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2241460ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x22414B0ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2241500ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_BASE 0x2241508ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x22415DCull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x224162Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x224167Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x22416CCull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x224171Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x224176Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x22417BCull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x224180Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x224185Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x22418ACull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x22418FCull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x224194Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x224199Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x22419ECull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2241A3Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2241A8Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2241ADCull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_BASE 0x2241AE4ull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE2_TPC1_EML_TPC_CFG_AXUSER_BASE 0x2241E00ull
+#define DCORE2_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x2241E80ull
+#define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC1_EML_QM_DCCM_BASE 0x2242000ull
+#define DCORE2_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC1_EML_QM_DCCM_SECTION 0x8000
+#define DCORE2_TPC1_EML_QM_ARCAUX_BASE 0x224A000ull
+#define DCORE2_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x224AE80ull
+#define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE2_TPC1_EML_TPC_QM_BASE 0x224C000ull
+#define DCORE2_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_TPC_QM_SECTION 0x9000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x224C900ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x224C908ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x224C910ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x224C918ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x224C920ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x224C928ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x224C930ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x224C938ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x224C940ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x224C948ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x224C950ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x224C958ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x224C960ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x224C968ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x224C970ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x224C978ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x224CB00ull
+#define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x224CB80ull
+#define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x224CC00ull
+#define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x224CC80ull
+#define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_TPC1_EML_TPC_QM_CGM_BASE 0x224CD80ull
+#define DCORE2_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC1_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE2_TPC1_EML_TPC_QM_SPECIAL_BASE 0x224CE80ull
+#define DCORE2_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE2_TPC1_EML_CS_BASE 0x23FF000ull
+#define DCORE2_TPC1_EML_CS_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_CS_SECTION 0x1000
+#define DCORE2_TPC2_ROM_TABLE_BASE 0x2400000ull
+#define DCORE2_TPC2_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_ROM_TABLE_SECTION 0x1000
+#define DCORE2_TPC2_EML_SPMU_BASE 0x2401000ull
+#define DCORE2_TPC2_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_SPMU_SECTION 0x1000
+#define DCORE2_TPC2_EML_ETF_BASE 0x2402000ull
+#define DCORE2_TPC2_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_ETF_SECTION 0x1000
+#define DCORE2_TPC2_EML_STM_BASE 0x2403000ull
+#define DCORE2_TPC2_EML_STM_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_STM_SECTION 0x2000
+#define DCORE2_TPC2_EML_CTI_BASE 0x2405000ull
+#define DCORE2_TPC2_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_CTI_SECTION 0x1000
+#define DCORE2_TPC2_EML_FUNNEL_BASE 0x2406000ull
+#define DCORE2_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_FUNNEL_SECTION 0x1000
+#define DCORE2_TPC2_EML_BUSMON_0_BASE 0x2407000ull
+#define DCORE2_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_BUSMON_0_SECTION 0x1000
+#define DCORE2_TPC2_EML_BUSMON_1_BASE 0x2408000ull
+#define DCORE2_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_BUSMON_1_SECTION 0x1000
+#define DCORE2_TPC2_EML_BUSMON_2_BASE 0x2409000ull
+#define DCORE2_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_BUSMON_2_SECTION 0x1000
+#define DCORE2_TPC2_EML_BUSMON_3_BASE 0x240A000ull
+#define DCORE2_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_BUSMON_3_SECTION 0x1000
+#define DCORE2_TPC2_QM_ARC_RTT_BASE 0x240B000ull
+#define DCORE2_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_TPC2_QM_ARC_RTT_SECTION 0x35000
+#define DCORE2_TPC2_EML_CFG_BASE 0x2440000ull
+#define DCORE2_TPC2_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_CFG_SECTION 0xE800
+#define DCORE2_TPC2_EML_CFG_SPECIAL_BASE 0x2440E80ull
+#define DCORE2_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2441000ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC2_EML_TPC_CFG_BASE 0x2441000ull
+#define DCORE2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_TPC_CFG_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2441050ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x24410A0ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x24410F0ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2441140ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2441190ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x24411E0ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2441230ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2441280ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x24412D0ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2441320ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2441370ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x24413C0ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2441410ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2441460ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x24414B0ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2441500ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_BASE 0x2441508ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x24415DCull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x244162Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x244167Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x24416CCull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x244171Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x244176Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x24417BCull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x244180Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x244185Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x24418ACull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x24418FCull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x244194Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x244199Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x24419ECull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2441A3Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2441A8Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2441ADCull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_BASE 0x2441AE4ull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE2_TPC2_EML_TPC_CFG_AXUSER_BASE 0x2441E00ull
+#define DCORE2_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x2441E80ull
+#define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC2_EML_QM_DCCM_BASE 0x2442000ull
+#define DCORE2_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC2_EML_QM_DCCM_SECTION 0x8000
+#define DCORE2_TPC2_EML_QM_ARCAUX_BASE 0x244A000ull
+#define DCORE2_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x244AE80ull
+#define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE2_TPC2_EML_TPC_QM_BASE 0x244C000ull
+#define DCORE2_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_TPC_QM_SECTION 0x9000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x244C900ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x244C908ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x244C910ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x244C918ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x244C920ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x244C928ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x244C930ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x244C938ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x244C940ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x244C948ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x244C950ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x244C958ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x244C960ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x244C968ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x244C970ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x244C978ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x244CB00ull
+#define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x244CB80ull
+#define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x244CC00ull
+#define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x244CC80ull
+#define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_TPC2_EML_TPC_QM_CGM_BASE 0x244CD80ull
+#define DCORE2_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC2_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE2_TPC2_EML_TPC_QM_SPECIAL_BASE 0x244CE80ull
+#define DCORE2_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE2_TPC2_EML_CS_BASE 0x25FF000ull
+#define DCORE2_TPC2_EML_CS_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_CS_SECTION 0x1000
+#define DCORE2_TPC3_ROM_TABLE_BASE 0x2600000ull
+#define DCORE2_TPC3_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_ROM_TABLE_SECTION 0x1000
+#define DCORE2_TPC3_EML_SPMU_BASE 0x2601000ull
+#define DCORE2_TPC3_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_SPMU_SECTION 0x1000
+#define DCORE2_TPC3_EML_ETF_BASE 0x2602000ull
+#define DCORE2_TPC3_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_ETF_SECTION 0x1000
+#define DCORE2_TPC3_EML_STM_BASE 0x2603000ull
+#define DCORE2_TPC3_EML_STM_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_STM_SECTION 0x2000
+#define DCORE2_TPC3_EML_CTI_BASE 0x2605000ull
+#define DCORE2_TPC3_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_CTI_SECTION 0x1000
+#define DCORE2_TPC3_EML_FUNNEL_BASE 0x2606000ull
+#define DCORE2_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_FUNNEL_SECTION 0x1000
+#define DCORE2_TPC3_EML_BUSMON_0_BASE 0x2607000ull
+#define DCORE2_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_BUSMON_0_SECTION 0x1000
+#define DCORE2_TPC3_EML_BUSMON_1_BASE 0x2608000ull
+#define DCORE2_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_BUSMON_1_SECTION 0x1000
+#define DCORE2_TPC3_EML_BUSMON_2_BASE 0x2609000ull
+#define DCORE2_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_BUSMON_2_SECTION 0x1000
+#define DCORE2_TPC3_EML_BUSMON_3_BASE 0x260A000ull
+#define DCORE2_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_BUSMON_3_SECTION 0x1000
+#define DCORE2_TPC3_QM_ARC_RTT_BASE 0x260B000ull
+#define DCORE2_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_TPC3_QM_ARC_RTT_SECTION 0x35000
+#define DCORE2_TPC3_EML_CFG_BASE 0x2640000ull
+#define DCORE2_TPC3_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_CFG_SECTION 0xE800
+#define DCORE2_TPC3_EML_CFG_SPECIAL_BASE 0x2640E80ull
+#define DCORE2_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2641000ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC3_EML_TPC_CFG_BASE 0x2641000ull
+#define DCORE2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_TPC_CFG_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2641050ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x26410A0ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x26410F0ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2641140ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2641190ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x26411E0ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2641230ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2641280ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x26412D0ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2641320ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2641370ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x26413C0ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2641410ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2641460ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x26414B0ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2641500ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_BASE 0x2641508ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x26415DCull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x264162Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x264167Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x26416CCull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x264171Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x264176Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x26417BCull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x264180Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x264185Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x26418ACull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x26418FCull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x264194Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x264199Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x26419ECull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2641A3Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2641A8Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2641ADCull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_BASE 0x2641AE4ull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE2_TPC3_EML_TPC_CFG_AXUSER_BASE 0x2641E00ull
+#define DCORE2_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x2641E80ull
+#define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC3_EML_QM_DCCM_BASE 0x2642000ull
+#define DCORE2_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC3_EML_QM_DCCM_SECTION 0x8000
+#define DCORE2_TPC3_EML_QM_ARCAUX_BASE 0x264A000ull
+#define DCORE2_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x264AE80ull
+#define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE2_TPC3_EML_TPC_QM_BASE 0x264C000ull
+#define DCORE2_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_TPC_QM_SECTION 0x9000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x264C900ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x264C908ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x264C910ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x264C918ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x264C920ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x264C928ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x264C930ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x264C938ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x264C940ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x264C948ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x264C950ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x264C958ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x264C960ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x264C968ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x264C970ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x264C978ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x264CB00ull
+#define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x264CB80ull
+#define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x264CC00ull
+#define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x264CC80ull
+#define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_TPC3_EML_TPC_QM_CGM_BASE 0x264CD80ull
+#define DCORE2_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC3_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE2_TPC3_EML_TPC_QM_SPECIAL_BASE 0x264CE80ull
+#define DCORE2_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE2_TPC3_EML_CS_BASE 0x27FF000ull
+#define DCORE2_TPC3_EML_CS_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_CS_SECTION 0x1000
+#define DCORE2_TPC4_ROM_TABLE_BASE 0x2800000ull
+#define DCORE2_TPC4_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_ROM_TABLE_SECTION 0x1000
+#define DCORE2_TPC4_EML_SPMU_BASE 0x2801000ull
+#define DCORE2_TPC4_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_SPMU_SECTION 0x1000
+#define DCORE2_TPC4_EML_ETF_BASE 0x2802000ull
+#define DCORE2_TPC4_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_ETF_SECTION 0x1000
+#define DCORE2_TPC4_EML_STM_BASE 0x2803000ull
+#define DCORE2_TPC4_EML_STM_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_STM_SECTION 0x2000
+#define DCORE2_TPC4_EML_CTI_BASE 0x2805000ull
+#define DCORE2_TPC4_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_CTI_SECTION 0x1000
+#define DCORE2_TPC4_EML_FUNNEL_BASE 0x2806000ull
+#define DCORE2_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_FUNNEL_SECTION 0x1000
+#define DCORE2_TPC4_EML_BUSMON_0_BASE 0x2807000ull
+#define DCORE2_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_BUSMON_0_SECTION 0x1000
+#define DCORE2_TPC4_EML_BUSMON_1_BASE 0x2808000ull
+#define DCORE2_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_BUSMON_1_SECTION 0x1000
+#define DCORE2_TPC4_EML_BUSMON_2_BASE 0x2809000ull
+#define DCORE2_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_BUSMON_2_SECTION 0x1000
+#define DCORE2_TPC4_EML_BUSMON_3_BASE 0x280A000ull
+#define DCORE2_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_BUSMON_3_SECTION 0x1000
+#define DCORE2_TPC4_QM_ARC_RTT_BASE 0x280B000ull
+#define DCORE2_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_TPC4_QM_ARC_RTT_SECTION 0x35000
+#define DCORE2_TPC4_EML_CFG_BASE 0x2840000ull
+#define DCORE2_TPC4_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_CFG_SECTION 0xE800
+#define DCORE2_TPC4_EML_CFG_SPECIAL_BASE 0x2840E80ull
+#define DCORE2_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2841000ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC4_EML_TPC_CFG_BASE 0x2841000ull
+#define DCORE2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_TPC_CFG_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2841050ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x28410A0ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x28410F0ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2841140ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2841190ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x28411E0ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2841230ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2841280ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x28412D0ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2841320ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2841370ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x28413C0ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2841410ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2841460ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x28414B0ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2841500ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_BASE 0x2841508ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x28415DCull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x284162Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x284167Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x28416CCull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x284171Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x284176Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x28417BCull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x284180Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x284185Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x28418ACull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x28418FCull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x284194Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x284199Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x28419ECull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2841A3Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2841A8Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2841ADCull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_BASE 0x2841AE4ull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE2_TPC4_EML_TPC_CFG_AXUSER_BASE 0x2841E00ull
+#define DCORE2_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x2841E80ull
+#define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC4_EML_QM_DCCM_BASE 0x2842000ull
+#define DCORE2_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC4_EML_QM_DCCM_SECTION 0x8000
+#define DCORE2_TPC4_EML_QM_ARCAUX_BASE 0x284A000ull
+#define DCORE2_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x284AE80ull
+#define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE2_TPC4_EML_TPC_QM_BASE 0x284C000ull
+#define DCORE2_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_TPC_QM_SECTION 0x9000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x284C900ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x284C908ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x284C910ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x284C918ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x284C920ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x284C928ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x284C930ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x284C938ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x284C940ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x284C948ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x284C950ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x284C958ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x284C960ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x284C968ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x284C970ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x284C978ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x284CB00ull
+#define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x284CB80ull
+#define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x284CC00ull
+#define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x284CC80ull
+#define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_TPC4_EML_TPC_QM_CGM_BASE 0x284CD80ull
+#define DCORE2_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC4_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE2_TPC4_EML_TPC_QM_SPECIAL_BASE 0x284CE80ull
+#define DCORE2_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE2_TPC4_EML_CS_BASE 0x29FF000ull
+#define DCORE2_TPC4_EML_CS_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_CS_SECTION 0x1000
+#define DCORE2_TPC5_ROM_TABLE_BASE 0x2A00000ull
+#define DCORE2_TPC5_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_ROM_TABLE_SECTION 0x1000
+#define DCORE2_TPC5_EML_SPMU_BASE 0x2A01000ull
+#define DCORE2_TPC5_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_SPMU_SECTION 0x1000
+#define DCORE2_TPC5_EML_ETF_BASE 0x2A02000ull
+#define DCORE2_TPC5_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_ETF_SECTION 0x1000
+#define DCORE2_TPC5_EML_STM_BASE 0x2A03000ull
+#define DCORE2_TPC5_EML_STM_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_STM_SECTION 0x2000
+#define DCORE2_TPC5_EML_CTI_BASE 0x2A05000ull
+#define DCORE2_TPC5_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_CTI_SECTION 0x1000
+#define DCORE2_TPC5_EML_FUNNEL_BASE 0x2A06000ull
+#define DCORE2_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_FUNNEL_SECTION 0x1000
+#define DCORE2_TPC5_EML_BUSMON_0_BASE 0x2A07000ull
+#define DCORE2_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_BUSMON_0_SECTION 0x1000
+#define DCORE2_TPC5_EML_BUSMON_1_BASE 0x2A08000ull
+#define DCORE2_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_BUSMON_1_SECTION 0x1000
+#define DCORE2_TPC5_EML_BUSMON_2_BASE 0x2A09000ull
+#define DCORE2_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_BUSMON_2_SECTION 0x1000
+#define DCORE2_TPC5_EML_BUSMON_3_BASE 0x2A0A000ull
+#define DCORE2_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_BUSMON_3_SECTION 0x1000
+#define DCORE2_TPC5_QM_ARC_RTT_BASE 0x2A0B000ull
+#define DCORE2_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_TPC5_QM_ARC_RTT_SECTION 0x35000
+#define DCORE2_TPC5_EML_CFG_BASE 0x2A40000ull
+#define DCORE2_TPC5_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_CFG_SECTION 0xE800
+#define DCORE2_TPC5_EML_CFG_SPECIAL_BASE 0x2A40E80ull
+#define DCORE2_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2A41000ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC5_EML_TPC_CFG_BASE 0x2A41000ull
+#define DCORE2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_TPC_CFG_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2A41050ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x2A410A0ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x2A410F0ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2A41140ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2A41190ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x2A411E0ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2A41230ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2A41280ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x2A412D0ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2A41320ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2A41370ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x2A413C0ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2A41410ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2A41460ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x2A414B0ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2A41500ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_BASE 0x2A41508ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x2A415DCull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x2A4162Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x2A4167Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x2A416CCull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x2A4171Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x2A4176Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x2A417BCull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x2A4180Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x2A4185Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x2A418ACull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x2A418FCull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x2A4194Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x2A4199Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x2A419ECull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2A41A3Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2A41A8Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2A41ADCull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_BASE 0x2A41AE4ull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE2_TPC5_EML_TPC_CFG_AXUSER_BASE 0x2A41E00ull
+#define DCORE2_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x2A41E80ull
+#define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC5_EML_QM_DCCM_BASE 0x2A42000ull
+#define DCORE2_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC5_EML_QM_DCCM_SECTION 0x8000
+#define DCORE2_TPC5_EML_QM_ARCAUX_BASE 0x2A4A000ull
+#define DCORE2_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x2A4AE80ull
+#define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE2_TPC5_EML_TPC_QM_BASE 0x2A4C000ull
+#define DCORE2_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_TPC_QM_SECTION 0x9000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x2A4C900ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x2A4C908ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x2A4C910ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x2A4C918ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x2A4C920ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x2A4C928ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x2A4C930ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x2A4C938ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x2A4C940ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x2A4C948ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x2A4C950ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x2A4C958ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x2A4C960ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x2A4C968ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x2A4C970ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x2A4C978ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x2A4CB00ull
+#define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x2A4CB80ull
+#define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x2A4CC00ull
+#define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x2A4CC80ull
+#define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_TPC5_EML_TPC_QM_CGM_BASE 0x2A4CD80ull
+#define DCORE2_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC5_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE2_TPC5_EML_TPC_QM_SPECIAL_BASE 0x2A4CE80ull
+#define DCORE2_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE2_TPC5_EML_CS_BASE 0x2BFF000ull
+#define DCORE2_TPC5_EML_CS_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_CS_SECTION 0x401000
+#define DCORE3_TPC0_ROM_TABLE_BASE 0x3000000ull
+#define DCORE3_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_ROM_TABLE_SECTION 0x1000
+#define DCORE3_TPC0_EML_SPMU_BASE 0x3001000ull
+#define DCORE3_TPC0_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_SPMU_SECTION 0x1000
+#define DCORE3_TPC0_EML_ETF_BASE 0x3002000ull
+#define DCORE3_TPC0_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_ETF_SECTION 0x1000
+#define DCORE3_TPC0_EML_STM_BASE 0x3003000ull
+#define DCORE3_TPC0_EML_STM_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_STM_SECTION 0x2000
+#define DCORE3_TPC0_EML_CTI_BASE 0x3005000ull
+#define DCORE3_TPC0_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_CTI_SECTION 0x1000
+#define DCORE3_TPC0_EML_FUNNEL_BASE 0x3006000ull
+#define DCORE3_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_FUNNEL_SECTION 0x1000
+#define DCORE3_TPC0_EML_BUSMON_0_BASE 0x3007000ull
+#define DCORE3_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_BUSMON_0_SECTION 0x1000
+#define DCORE3_TPC0_EML_BUSMON_1_BASE 0x3008000ull
+#define DCORE3_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_BUSMON_1_SECTION 0x1000
+#define DCORE3_TPC0_EML_BUSMON_2_BASE 0x3009000ull
+#define DCORE3_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_BUSMON_2_SECTION 0x1000
+#define DCORE3_TPC0_EML_BUSMON_3_BASE 0x300A000ull
+#define DCORE3_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_BUSMON_3_SECTION 0x1000
+#define DCORE3_TPC0_QM_ARC_RTT_BASE 0x300B000ull
+#define DCORE3_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_TPC0_QM_ARC_RTT_SECTION 0x35000
+#define DCORE3_TPC0_EML_CFG_BASE 0x3040000ull
+#define DCORE3_TPC0_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_CFG_SECTION 0xE800
+#define DCORE3_TPC0_EML_CFG_SPECIAL_BASE 0x3040E80ull
+#define DCORE3_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3041000ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC0_EML_TPC_CFG_BASE 0x3041000ull
+#define DCORE3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_TPC_CFG_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3041050ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x30410A0ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x30410F0ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3041140ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3041190ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x30411E0ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3041230ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3041280ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x30412D0ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3041320ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3041370ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x30413C0ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3041410ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3041460ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x30414B0ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3041500ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_BASE 0x3041508ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x30415DCull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x304162Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x304167Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x30416CCull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x304171Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x304176Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x30417BCull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x304180Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x304185Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x30418ACull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x30418FCull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x304194Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x304199Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x30419ECull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3041A3Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3041A8Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3041ADCull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_BASE 0x3041AE4ull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE3_TPC0_EML_TPC_CFG_AXUSER_BASE 0x3041E00ull
+#define DCORE3_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x3041E80ull
+#define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC0_EML_QM_DCCM_BASE 0x3042000ull
+#define DCORE3_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC0_EML_QM_DCCM_SECTION 0x8000
+#define DCORE3_TPC0_EML_QM_ARCAUX_BASE 0x304A000ull
+#define DCORE3_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x304AE80ull
+#define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE3_TPC0_EML_TPC_QM_BASE 0x304C000ull
+#define DCORE3_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_TPC_QM_SECTION 0x9000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x304C900ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x304C908ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x304C910ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x304C918ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x304C920ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x304C928ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x304C930ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x304C938ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x304C940ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x304C948ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x304C950ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x304C958ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x304C960ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x304C968ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x304C970ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x304C978ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x304CB00ull
+#define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x304CB80ull
+#define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x304CC00ull
+#define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x304CC80ull
+#define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_TPC0_EML_TPC_QM_CGM_BASE 0x304CD80ull
+#define DCORE3_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC0_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE3_TPC0_EML_TPC_QM_SPECIAL_BASE 0x304CE80ull
+#define DCORE3_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE3_TPC0_EML_CS_BASE 0x31FF000ull
+#define DCORE3_TPC0_EML_CS_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_CS_SECTION 0x1000
+#define DCORE3_TPC1_ROM_TABLE_BASE 0x3200000ull
+#define DCORE3_TPC1_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_ROM_TABLE_SECTION 0x1000
+#define DCORE3_TPC1_EML_SPMU_BASE 0x3201000ull
+#define DCORE3_TPC1_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_SPMU_SECTION 0x1000
+#define DCORE3_TPC1_EML_ETF_BASE 0x3202000ull
+#define DCORE3_TPC1_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_ETF_SECTION 0x1000
+#define DCORE3_TPC1_EML_STM_BASE 0x3203000ull
+#define DCORE3_TPC1_EML_STM_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_STM_SECTION 0x2000
+#define DCORE3_TPC1_EML_CTI_BASE 0x3205000ull
+#define DCORE3_TPC1_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_CTI_SECTION 0x1000
+#define DCORE3_TPC1_EML_FUNNEL_BASE 0x3206000ull
+#define DCORE3_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_FUNNEL_SECTION 0x1000
+#define DCORE3_TPC1_EML_BUSMON_0_BASE 0x3207000ull
+#define DCORE3_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_BUSMON_0_SECTION 0x1000
+#define DCORE3_TPC1_EML_BUSMON_1_BASE 0x3208000ull
+#define DCORE3_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_BUSMON_1_SECTION 0x1000
+#define DCORE3_TPC1_EML_BUSMON_2_BASE 0x3209000ull
+#define DCORE3_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_BUSMON_2_SECTION 0x1000
+#define DCORE3_TPC1_EML_BUSMON_3_BASE 0x320A000ull
+#define DCORE3_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_BUSMON_3_SECTION 0x1000
+#define DCORE3_TPC1_QM_ARC_RTT_BASE 0x320B000ull
+#define DCORE3_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_TPC1_QM_ARC_RTT_SECTION 0x35000
+#define DCORE3_TPC1_EML_CFG_BASE 0x3240000ull
+#define DCORE3_TPC1_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_CFG_SECTION 0xE800
+#define DCORE3_TPC1_EML_CFG_SPECIAL_BASE 0x3240E80ull
+#define DCORE3_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3241000ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC1_EML_TPC_CFG_BASE 0x3241000ull
+#define DCORE3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_TPC_CFG_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3241050ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x32410A0ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x32410F0ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3241140ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3241190ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x32411E0ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3241230ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3241280ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x32412D0ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3241320ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3241370ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x32413C0ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3241410ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3241460ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x32414B0ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3241500ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_BASE 0x3241508ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x32415DCull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x324162Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x324167Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x32416CCull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x324171Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x324176Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x32417BCull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x324180Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x324185Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x32418ACull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x32418FCull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x324194Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x324199Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x32419ECull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3241A3Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3241A8Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3241ADCull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_BASE 0x3241AE4ull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE3_TPC1_EML_TPC_CFG_AXUSER_BASE 0x3241E00ull
+#define DCORE3_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x3241E80ull
+#define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC1_EML_QM_DCCM_BASE 0x3242000ull
+#define DCORE3_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC1_EML_QM_DCCM_SECTION 0x8000
+#define DCORE3_TPC1_EML_QM_ARCAUX_BASE 0x324A000ull
+#define DCORE3_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x324AE80ull
+#define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE3_TPC1_EML_TPC_QM_BASE 0x324C000ull
+#define DCORE3_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_TPC_QM_SECTION 0x9000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x324C900ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x324C908ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x324C910ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x324C918ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x324C920ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x324C928ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x324C930ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x324C938ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x324C940ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x324C948ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x324C950ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x324C958ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x324C960ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x324C968ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x324C970ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x324C978ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x324CB00ull
+#define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x324CB80ull
+#define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x324CC00ull
+#define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x324CC80ull
+#define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_TPC1_EML_TPC_QM_CGM_BASE 0x324CD80ull
+#define DCORE3_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC1_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE3_TPC1_EML_TPC_QM_SPECIAL_BASE 0x324CE80ull
+#define DCORE3_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE3_TPC1_EML_CS_BASE 0x33FF000ull
+#define DCORE3_TPC1_EML_CS_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_CS_SECTION 0x1000
+#define DCORE3_TPC2_ROM_TABLE_BASE 0x3400000ull
+#define DCORE3_TPC2_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_ROM_TABLE_SECTION 0x1000
+#define DCORE3_TPC2_EML_SPMU_BASE 0x3401000ull
+#define DCORE3_TPC2_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_SPMU_SECTION 0x1000
+#define DCORE3_TPC2_EML_ETF_BASE 0x3402000ull
+#define DCORE3_TPC2_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_ETF_SECTION 0x1000
+#define DCORE3_TPC2_EML_STM_BASE 0x3403000ull
+#define DCORE3_TPC2_EML_STM_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_STM_SECTION 0x2000
+#define DCORE3_TPC2_EML_CTI_BASE 0x3405000ull
+#define DCORE3_TPC2_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_CTI_SECTION 0x1000
+#define DCORE3_TPC2_EML_FUNNEL_BASE 0x3406000ull
+#define DCORE3_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_FUNNEL_SECTION 0x1000
+#define DCORE3_TPC2_EML_BUSMON_0_BASE 0x3407000ull
+#define DCORE3_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_BUSMON_0_SECTION 0x1000
+#define DCORE3_TPC2_EML_BUSMON_1_BASE 0x3408000ull
+#define DCORE3_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_BUSMON_1_SECTION 0x1000
+#define DCORE3_TPC2_EML_BUSMON_2_BASE 0x3409000ull
+#define DCORE3_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_BUSMON_2_SECTION 0x1000
+#define DCORE3_TPC2_EML_BUSMON_3_BASE 0x340A000ull
+#define DCORE3_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_BUSMON_3_SECTION 0x1000
+#define DCORE3_TPC2_QM_ARC_RTT_BASE 0x340B000ull
+#define DCORE3_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_TPC2_QM_ARC_RTT_SECTION 0x35000
+#define DCORE3_TPC2_EML_CFG_BASE 0x3440000ull
+#define DCORE3_TPC2_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_CFG_SECTION 0xE800
+#define DCORE3_TPC2_EML_CFG_SPECIAL_BASE 0x3440E80ull
+#define DCORE3_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3441000ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC2_EML_TPC_CFG_BASE 0x3441000ull
+#define DCORE3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_TPC_CFG_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3441050ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x34410A0ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x34410F0ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3441140ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3441190ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x34411E0ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3441230ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3441280ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x34412D0ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3441320ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3441370ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x34413C0ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3441410ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3441460ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x34414B0ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3441500ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_BASE 0x3441508ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x34415DCull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x344162Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x344167Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x34416CCull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x344171Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x344176Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x34417BCull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x344180Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x344185Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x34418ACull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x34418FCull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x344194Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x344199Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x34419ECull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3441A3Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3441A8Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3441ADCull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_BASE 0x3441AE4ull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE3_TPC2_EML_TPC_CFG_AXUSER_BASE 0x3441E00ull
+#define DCORE3_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x3441E80ull
+#define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC2_EML_QM_DCCM_BASE 0x3442000ull
+#define DCORE3_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC2_EML_QM_DCCM_SECTION 0x8000
+#define DCORE3_TPC2_EML_QM_ARCAUX_BASE 0x344A000ull
+#define DCORE3_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x344AE80ull
+#define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE3_TPC2_EML_TPC_QM_BASE 0x344C000ull
+#define DCORE3_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_TPC_QM_SECTION 0x9000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x344C900ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x344C908ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x344C910ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x344C918ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x344C920ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x344C928ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x344C930ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x344C938ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x344C940ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x344C948ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x344C950ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x344C958ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x344C960ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x344C968ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x344C970ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x344C978ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x344CB00ull
+#define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x344CB80ull
+#define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x344CC00ull
+#define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x344CC80ull
+#define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_TPC2_EML_TPC_QM_CGM_BASE 0x344CD80ull
+#define DCORE3_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC2_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE3_TPC2_EML_TPC_QM_SPECIAL_BASE 0x344CE80ull
+#define DCORE3_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE3_TPC2_EML_CS_BASE 0x35FF000ull
+#define DCORE3_TPC2_EML_CS_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_CS_SECTION 0x1000
+#define DCORE3_TPC3_ROM_TABLE_BASE 0x3600000ull
+#define DCORE3_TPC3_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_ROM_TABLE_SECTION 0x1000
+#define DCORE3_TPC3_EML_SPMU_BASE 0x3601000ull
+#define DCORE3_TPC3_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_SPMU_SECTION 0x1000
+#define DCORE3_TPC3_EML_ETF_BASE 0x3602000ull
+#define DCORE3_TPC3_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_ETF_SECTION 0x1000
+#define DCORE3_TPC3_EML_STM_BASE 0x3603000ull
+#define DCORE3_TPC3_EML_STM_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_STM_SECTION 0x2000
+#define DCORE3_TPC3_EML_CTI_BASE 0x3605000ull
+#define DCORE3_TPC3_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_CTI_SECTION 0x1000
+#define DCORE3_TPC3_EML_FUNNEL_BASE 0x3606000ull
+#define DCORE3_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_FUNNEL_SECTION 0x1000
+#define DCORE3_TPC3_EML_BUSMON_0_BASE 0x3607000ull
+#define DCORE3_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_BUSMON_0_SECTION 0x1000
+#define DCORE3_TPC3_EML_BUSMON_1_BASE 0x3608000ull
+#define DCORE3_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_BUSMON_1_SECTION 0x1000
+#define DCORE3_TPC3_EML_BUSMON_2_BASE 0x3609000ull
+#define DCORE3_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_BUSMON_2_SECTION 0x1000
+#define DCORE3_TPC3_EML_BUSMON_3_BASE 0x360A000ull
+#define DCORE3_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_BUSMON_3_SECTION 0x1000
+#define DCORE3_TPC3_QM_ARC_RTT_BASE 0x360B000ull
+#define DCORE3_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_TPC3_QM_ARC_RTT_SECTION 0x35000
+#define DCORE3_TPC3_EML_CFG_BASE 0x3640000ull
+#define DCORE3_TPC3_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_CFG_SECTION 0xE800
+#define DCORE3_TPC3_EML_CFG_SPECIAL_BASE 0x3640E80ull
+#define DCORE3_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3641000ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC3_EML_TPC_CFG_BASE 0x3641000ull
+#define DCORE3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_TPC_CFG_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3641050ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x36410A0ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x36410F0ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3641140ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3641190ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x36411E0ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3641230ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3641280ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x36412D0ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3641320ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3641370ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x36413C0ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3641410ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3641460ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x36414B0ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3641500ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_BASE 0x3641508ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x36415DCull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x364162Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x364167Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x36416CCull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x364171Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x364176Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x36417BCull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x364180Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x364185Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x36418ACull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x36418FCull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x364194Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x364199Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x36419ECull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3641A3Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3641A8Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3641ADCull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_BASE 0x3641AE4ull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE3_TPC3_EML_TPC_CFG_AXUSER_BASE 0x3641E00ull
+#define DCORE3_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x3641E80ull
+#define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC3_EML_QM_DCCM_BASE 0x3642000ull
+#define DCORE3_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC3_EML_QM_DCCM_SECTION 0x8000
+#define DCORE3_TPC3_EML_QM_ARCAUX_BASE 0x364A000ull
+#define DCORE3_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x364AE80ull
+#define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE3_TPC3_EML_TPC_QM_BASE 0x364C000ull
+#define DCORE3_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_TPC_QM_SECTION 0x9000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x364C900ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x364C908ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x364C910ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x364C918ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x364C920ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x364C928ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x364C930ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x364C938ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x364C940ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x364C948ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x364C950ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x364C958ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x364C960ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x364C968ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x364C970ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x364C978ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x364CB00ull
+#define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x364CB80ull
+#define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x364CC00ull
+#define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x364CC80ull
+#define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_TPC3_EML_TPC_QM_CGM_BASE 0x364CD80ull
+#define DCORE3_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC3_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE3_TPC3_EML_TPC_QM_SPECIAL_BASE 0x364CE80ull
+#define DCORE3_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE3_TPC3_EML_CS_BASE 0x37FF000ull
+#define DCORE3_TPC3_EML_CS_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_CS_SECTION 0x1000
+#define DCORE3_TPC4_ROM_TABLE_BASE 0x3800000ull
+#define DCORE3_TPC4_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_ROM_TABLE_SECTION 0x1000
+#define DCORE3_TPC4_EML_SPMU_BASE 0x3801000ull
+#define DCORE3_TPC4_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_SPMU_SECTION 0x1000
+#define DCORE3_TPC4_EML_ETF_BASE 0x3802000ull
+#define DCORE3_TPC4_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_ETF_SECTION 0x1000
+#define DCORE3_TPC4_EML_STM_BASE 0x3803000ull
+#define DCORE3_TPC4_EML_STM_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_STM_SECTION 0x2000
+#define DCORE3_TPC4_EML_CTI_BASE 0x3805000ull
+#define DCORE3_TPC4_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_CTI_SECTION 0x1000
+#define DCORE3_TPC4_EML_FUNNEL_BASE 0x3806000ull
+#define DCORE3_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_FUNNEL_SECTION 0x1000
+#define DCORE3_TPC4_EML_BUSMON_0_BASE 0x3807000ull
+#define DCORE3_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_BUSMON_0_SECTION 0x1000
+#define DCORE3_TPC4_EML_BUSMON_1_BASE 0x3808000ull
+#define DCORE3_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_BUSMON_1_SECTION 0x1000
+#define DCORE3_TPC4_EML_BUSMON_2_BASE 0x3809000ull
+#define DCORE3_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_BUSMON_2_SECTION 0x1000
+#define DCORE3_TPC4_EML_BUSMON_3_BASE 0x380A000ull
+#define DCORE3_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_BUSMON_3_SECTION 0x1000
+#define DCORE3_TPC4_QM_ARC_RTT_BASE 0x380B000ull
+#define DCORE3_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_TPC4_QM_ARC_RTT_SECTION 0x35000
+#define DCORE3_TPC4_EML_CFG_BASE 0x3840000ull
+#define DCORE3_TPC4_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_CFG_SECTION 0xE800
+#define DCORE3_TPC4_EML_CFG_SPECIAL_BASE 0x3840E80ull
+#define DCORE3_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3841000ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC4_EML_TPC_CFG_BASE 0x3841000ull
+#define DCORE3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_TPC_CFG_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3841050ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x38410A0ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x38410F0ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3841140ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3841190ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x38411E0ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3841230ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3841280ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x38412D0ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3841320ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3841370ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x38413C0ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3841410ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3841460ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x38414B0ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3841500ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_BASE 0x3841508ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x38415DCull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x384162Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x384167Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x38416CCull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x384171Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x384176Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x38417BCull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x384180Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x384185Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x38418ACull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x38418FCull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x384194Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x384199Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x38419ECull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3841A3Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3841A8Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3841ADCull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_BASE 0x3841AE4ull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE3_TPC4_EML_TPC_CFG_AXUSER_BASE 0x3841E00ull
+#define DCORE3_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x3841E80ull
+#define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC4_EML_QM_DCCM_BASE 0x3842000ull
+#define DCORE3_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC4_EML_QM_DCCM_SECTION 0x8000
+#define DCORE3_TPC4_EML_QM_ARCAUX_BASE 0x384A000ull
+#define DCORE3_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x384AE80ull
+#define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE3_TPC4_EML_TPC_QM_BASE 0x384C000ull
+#define DCORE3_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_TPC_QM_SECTION 0x9000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x384C900ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x384C908ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x384C910ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x384C918ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x384C920ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x384C928ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x384C930ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x384C938ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x384C940ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x384C948ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x384C950ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x384C958ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x384C960ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x384C968ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x384C970ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x384C978ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x384CB00ull
+#define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x384CB80ull
+#define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x384CC00ull
+#define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x384CC80ull
+#define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_TPC4_EML_TPC_QM_CGM_BASE 0x384CD80ull
+#define DCORE3_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC4_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE3_TPC4_EML_TPC_QM_SPECIAL_BASE 0x384CE80ull
+#define DCORE3_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE3_TPC4_EML_CS_BASE 0x39FF000ull
+#define DCORE3_TPC4_EML_CS_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_CS_SECTION 0x1000
+#define DCORE3_TPC5_ROM_TABLE_BASE 0x3A00000ull
+#define DCORE3_TPC5_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_ROM_TABLE_SECTION 0x1000
+#define DCORE3_TPC5_EML_SPMU_BASE 0x3A01000ull
+#define DCORE3_TPC5_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_SPMU_SECTION 0x1000
+#define DCORE3_TPC5_EML_ETF_BASE 0x3A02000ull
+#define DCORE3_TPC5_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_ETF_SECTION 0x1000
+#define DCORE3_TPC5_EML_STM_BASE 0x3A03000ull
+#define DCORE3_TPC5_EML_STM_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_STM_SECTION 0x2000
+#define DCORE3_TPC5_EML_CTI_BASE 0x3A05000ull
+#define DCORE3_TPC5_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_CTI_SECTION 0x1000
+#define DCORE3_TPC5_EML_FUNNEL_BASE 0x3A06000ull
+#define DCORE3_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_FUNNEL_SECTION 0x1000
+#define DCORE3_TPC5_EML_BUSMON_0_BASE 0x3A07000ull
+#define DCORE3_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_BUSMON_0_SECTION 0x1000
+#define DCORE3_TPC5_EML_BUSMON_1_BASE 0x3A08000ull
+#define DCORE3_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_BUSMON_1_SECTION 0x1000
+#define DCORE3_TPC5_EML_BUSMON_2_BASE 0x3A09000ull
+#define DCORE3_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_BUSMON_2_SECTION 0x1000
+#define DCORE3_TPC5_EML_BUSMON_3_BASE 0x3A0A000ull
+#define DCORE3_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_BUSMON_3_SECTION 0x1000
+#define DCORE3_TPC5_QM_ARC_RTT_BASE 0x3A0B000ull
+#define DCORE3_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_TPC5_QM_ARC_RTT_SECTION 0x35000
+#define DCORE3_TPC5_EML_CFG_BASE 0x3A40000ull
+#define DCORE3_TPC5_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_CFG_SECTION 0xE800
+#define DCORE3_TPC5_EML_CFG_SPECIAL_BASE 0x3A40E80ull
+#define DCORE3_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3A41000ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC5_EML_TPC_CFG_BASE 0x3A41000ull
+#define DCORE3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_TPC_CFG_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3A41050ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x3A410A0ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x3A410F0ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3A41140ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3A41190ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x3A411E0ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3A41230ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3A41280ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x3A412D0ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3A41320ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3A41370ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x3A413C0ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3A41410ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3A41460ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x3A414B0ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3A41500ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_BASE 0x3A41508ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x3A415DCull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x3A4162Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x3A4167Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x3A416CCull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x3A4171Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x3A4176Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x3A417BCull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x3A4180Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x3A4185Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x3A418ACull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x3A418FCull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x3A4194Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x3A4199Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x3A419ECull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3A41A3Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3A41A8Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3A41ADCull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_BASE 0x3A41AE4ull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0
+#define DCORE3_TPC5_EML_TPC_CFG_AXUSER_BASE 0x3A41E00ull
+#define DCORE3_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x3A41E80ull
+#define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC5_EML_QM_DCCM_BASE 0x3A42000ull
+#define DCORE3_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC5_EML_QM_DCCM_SECTION 0x8000
+#define DCORE3_TPC5_EML_QM_ARCAUX_BASE 0x3A4A000ull
+#define DCORE3_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_QM_ARCAUX_SECTION 0xE800
+#define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x3A4AE80ull
+#define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define DCORE3_TPC5_EML_TPC_QM_BASE 0x3A4C000ull
+#define DCORE3_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_TPC_QM_SECTION 0x9000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x3A4C900ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x3A4C908ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x3A4C910ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x3A4C918ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x3A4C920ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x3A4C928ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x3A4C930ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x3A4C938ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x3A4C940ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x3A4C948ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x3A4C950ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x3A4C958ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x3A4C960ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x3A4C968ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x3A4C970ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x3A4C978ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x3A4CB00ull
+#define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x3A4CB80ull
+#define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x3A4CC00ull
+#define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x3A4CC80ull
+#define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_TPC5_EML_TPC_QM_CGM_BASE 0x3A4CD80ull
+#define DCORE3_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC5_EML_TPC_QM_CGM_SECTION 0x1000
+#define DCORE3_TPC5_EML_TPC_QM_SPECIAL_BASE 0x3A4CE80ull
+#define DCORE3_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define DCORE3_TPC5_EML_CS_BASE 0x3BFF000ull
+#define DCORE3_TPC5_EML_CS_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_CS_SECTION 0x401000
+#define DCORE0_TPC0_QM_DCCM_BASE 0x4000000ull
+#define DCORE0_TPC0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC0_QM_DCCM_SECTION 0x8000
+#define DCORE0_TPC0_QM_ARC_AUX_BASE 0x4008000ull
+#define DCORE0_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_QM_ARC_AUX_SECTION 0xE800
+#define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4008E80ull
+#define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE0_TPC0_QM_BASE 0x400A000ull
+#define DCORE0_TPC0_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_QM_SECTION 0x9000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x400A900ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x400A908ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x400A910ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x400A918ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x400A920ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x400A928ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x400A930ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x400A938ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x400A940ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x400A948ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x400A950ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x400A958ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x400A960ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x400A968ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x400A970ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x400A978ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_TPC0_QM_AXUSER_SECURED_BASE 0x400AB00ull
+#define DCORE0_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_TPC0_QM_AXUSER_NONSECURED_BASE 0x400AB80ull
+#define DCORE0_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_TPC0_QM_DBG_HBW_BASE 0x400AC00ull
+#define DCORE0_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC0_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC0_QM_DBG_LBW_BASE 0x400AC80ull
+#define DCORE0_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC0_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_TPC0_QM_CGM_BASE 0x400AD80ull
+#define DCORE0_TPC0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC0_QM_CGM_SECTION 0x1000
+#define DCORE0_TPC0_QM_SPECIAL_BASE 0x400AE80ull
+#define DCORE0_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x400B000ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC0_CFG_BASE 0x400B000ull
+#define DCORE0_TPC0_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_CFG_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x400B050ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x400B0A0ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x400B0F0ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x400B140ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x400B190ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x400B1E0ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x400B230ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x400B280ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x400B2D0ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x400B320ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x400B370ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x400B3C0ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x400B410ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x400B460ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x400B4B0ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x400B500ull
+#define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC0_CFG_KERNEL_BASE 0x400B508ull
+#define DCORE0_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC0_CFG_KERNEL_SECTION 0xD400
+#define DCORE0_TPC0_CFG_QM_TENSOR_0_BASE 0x400B5DCull
+#define DCORE0_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_1_BASE 0x400B62Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_2_BASE 0x400B67Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_3_BASE 0x400B6CCull
+#define DCORE0_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_4_BASE 0x400B71Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_5_BASE 0x400B76Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_6_BASE 0x400B7BCull
+#define DCORE0_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_7_BASE 0x400B80Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_8_BASE 0x400B85Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_9_BASE 0x400B8ACull
+#define DCORE0_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_10_BASE 0x400B8FCull
+#define DCORE0_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_11_BASE 0x400B94Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_12_BASE 0x400B99Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_13_BASE 0x400B9ECull
+#define DCORE0_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_14_BASE 0x400BA3Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_15_BASE 0x400BA8Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x400BADCull
+#define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC0_CFG_QM_BASE 0x400BAE4ull
+#define DCORE0_TPC0_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC0_CFG_QM_SECTION 0x31C0
+#define DCORE0_TPC0_CFG_AXUSER_BASE 0x400BE00ull
+#define DCORE0_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_AXUSER_SECTION 0x8000
+#define DCORE0_TPC0_CFG_SPECIAL_BASE 0x400BE80ull
+#define DCORE0_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x400C000ull
+#define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x400C200ull
+#define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x400C400ull
+#define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x400C600ull
+#define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_TPC0_MSTR_IF_E2E_CRDT_BASE 0x400C800ull
+#define DCORE0_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_TPC0_MSTR_IF_AXUSER_BASE 0x400CA80ull
+#define DCORE0_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_TPC0_MSTR_IF_DBG_HBW_BASE 0x400CB00ull
+#define DCORE0_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC0_MSTR_IF_DBG_LBW_BASE 0x400CB80ull
+#define DCORE0_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_TPC0_MSTR_IF_CORE_HBW_BASE 0x400CC00ull
+#define DCORE0_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_TPC0_MSTR_IF_CORE_LBW_BASE 0x400CD80ull
+#define DCORE0_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_TPC0_MSTR_IF_SPECIAL_BASE 0x400CE80ull
+#define DCORE0_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE0_TPC1_QM_DCCM_BASE 0x4010000ull
+#define DCORE0_TPC1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC1_QM_DCCM_SECTION 0x8000
+#define DCORE0_TPC1_QM_ARC_AUX_BASE 0x4018000ull
+#define DCORE0_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_QM_ARC_AUX_SECTION 0xE800
+#define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4018E80ull
+#define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE0_TPC1_QM_BASE 0x401A000ull
+#define DCORE0_TPC1_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_QM_SECTION 0x9000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x401A900ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x401A908ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x401A910ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x401A918ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x401A920ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x401A928ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x401A930ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x401A938ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x401A940ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x401A948ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x401A950ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x401A958ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x401A960ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x401A968ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x401A970ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x401A978ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_TPC1_QM_AXUSER_SECURED_BASE 0x401AB00ull
+#define DCORE0_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_TPC1_QM_AXUSER_NONSECURED_BASE 0x401AB80ull
+#define DCORE0_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_TPC1_QM_DBG_HBW_BASE 0x401AC00ull
+#define DCORE0_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC1_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC1_QM_DBG_LBW_BASE 0x401AC80ull
+#define DCORE0_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC1_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_TPC1_QM_CGM_BASE 0x401AD80ull
+#define DCORE0_TPC1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC1_QM_CGM_SECTION 0x1000
+#define DCORE0_TPC1_QM_SPECIAL_BASE 0x401AE80ull
+#define DCORE0_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x401B000ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC1_CFG_BASE 0x401B000ull
+#define DCORE0_TPC1_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_CFG_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x401B050ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x401B0A0ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x401B0F0ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x401B140ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x401B190ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x401B1E0ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x401B230ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x401B280ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x401B2D0ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x401B320ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x401B370ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x401B3C0ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x401B410ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x401B460ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x401B4B0ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x401B500ull
+#define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC1_CFG_KERNEL_BASE 0x401B508ull
+#define DCORE0_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC1_CFG_KERNEL_SECTION 0xD400
+#define DCORE0_TPC1_CFG_QM_TENSOR_0_BASE 0x401B5DCull
+#define DCORE0_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_1_BASE 0x401B62Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_2_BASE 0x401B67Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_3_BASE 0x401B6CCull
+#define DCORE0_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_4_BASE 0x401B71Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_5_BASE 0x401B76Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_6_BASE 0x401B7BCull
+#define DCORE0_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_7_BASE 0x401B80Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_8_BASE 0x401B85Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_9_BASE 0x401B8ACull
+#define DCORE0_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_10_BASE 0x401B8FCull
+#define DCORE0_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_11_BASE 0x401B94Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_12_BASE 0x401B99Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_13_BASE 0x401B9ECull
+#define DCORE0_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_14_BASE 0x401BA3Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_15_BASE 0x401BA8Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x401BADCull
+#define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC1_CFG_QM_BASE 0x401BAE4ull
+#define DCORE0_TPC1_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC1_CFG_QM_SECTION 0x31C0
+#define DCORE0_TPC1_CFG_AXUSER_BASE 0x401BE00ull
+#define DCORE0_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_AXUSER_SECTION 0x8000
+#define DCORE0_TPC1_CFG_SPECIAL_BASE 0x401BE80ull
+#define DCORE0_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x401C000ull
+#define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x401C200ull
+#define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x401C400ull
+#define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x401C600ull
+#define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_TPC1_MSTR_IF_E2E_CRDT_BASE 0x401C800ull
+#define DCORE0_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_TPC1_MSTR_IF_AXUSER_BASE 0x401CA80ull
+#define DCORE0_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_TPC1_MSTR_IF_DBG_HBW_BASE 0x401CB00ull
+#define DCORE0_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC1_MSTR_IF_DBG_LBW_BASE 0x401CB80ull
+#define DCORE0_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_TPC1_MSTR_IF_CORE_HBW_BASE 0x401CC00ull
+#define DCORE0_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_TPC1_MSTR_IF_CORE_LBW_BASE 0x401CD80ull
+#define DCORE0_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_TPC1_MSTR_IF_SPECIAL_BASE 0x401CE80ull
+#define DCORE0_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE0_TPC2_QM_DCCM_BASE 0x4020000ull
+#define DCORE0_TPC2_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC2_QM_DCCM_SECTION 0x8000
+#define DCORE0_TPC2_QM_ARC_AUX_BASE 0x4028000ull
+#define DCORE0_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_QM_ARC_AUX_SECTION 0xE800
+#define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4028E80ull
+#define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE0_TPC2_QM_BASE 0x402A000ull
+#define DCORE0_TPC2_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_QM_SECTION 0x9000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x402A900ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x402A908ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x402A910ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x402A918ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x402A920ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x402A928ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x402A930ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x402A938ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x402A940ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x402A948ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x402A950ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x402A958ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x402A960ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x402A968ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x402A970ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x402A978ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_TPC2_QM_AXUSER_SECURED_BASE 0x402AB00ull
+#define DCORE0_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_TPC2_QM_AXUSER_NONSECURED_BASE 0x402AB80ull
+#define DCORE0_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_TPC2_QM_DBG_HBW_BASE 0x402AC00ull
+#define DCORE0_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC2_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC2_QM_DBG_LBW_BASE 0x402AC80ull
+#define DCORE0_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC2_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_TPC2_QM_CGM_BASE 0x402AD80ull
+#define DCORE0_TPC2_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC2_QM_CGM_SECTION 0x1000
+#define DCORE0_TPC2_QM_SPECIAL_BASE 0x402AE80ull
+#define DCORE0_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x402B000ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC2_CFG_BASE 0x402B000ull
+#define DCORE0_TPC2_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_CFG_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x402B050ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x402B0A0ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x402B0F0ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x402B140ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x402B190ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x402B1E0ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x402B230ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x402B280ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x402B2D0ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x402B320ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x402B370ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x402B3C0ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x402B410ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x402B460ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x402B4B0ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x402B500ull
+#define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC2_CFG_KERNEL_BASE 0x402B508ull
+#define DCORE0_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC2_CFG_KERNEL_SECTION 0xD400
+#define DCORE0_TPC2_CFG_QM_TENSOR_0_BASE 0x402B5DCull
+#define DCORE0_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_1_BASE 0x402B62Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_2_BASE 0x402B67Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_3_BASE 0x402B6CCull
+#define DCORE0_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_4_BASE 0x402B71Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_5_BASE 0x402B76Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_6_BASE 0x402B7BCull
+#define DCORE0_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_7_BASE 0x402B80Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_8_BASE 0x402B85Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_9_BASE 0x402B8ACull
+#define DCORE0_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_10_BASE 0x402B8FCull
+#define DCORE0_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_11_BASE 0x402B94Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_12_BASE 0x402B99Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_13_BASE 0x402B9ECull
+#define DCORE0_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_14_BASE 0x402BA3Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_15_BASE 0x402BA8Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x402BADCull
+#define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC2_CFG_QM_BASE 0x402BAE4ull
+#define DCORE0_TPC2_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC2_CFG_QM_SECTION 0x31C0
+#define DCORE0_TPC2_CFG_AXUSER_BASE 0x402BE00ull
+#define DCORE0_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_AXUSER_SECTION 0x8000
+#define DCORE0_TPC2_CFG_SPECIAL_BASE 0x402BE80ull
+#define DCORE0_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x402C000ull
+#define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x402C200ull
+#define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x402C400ull
+#define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x402C600ull
+#define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_TPC2_MSTR_IF_E2E_CRDT_BASE 0x402C800ull
+#define DCORE0_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_TPC2_MSTR_IF_AXUSER_BASE 0x402CA80ull
+#define DCORE0_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_TPC2_MSTR_IF_DBG_HBW_BASE 0x402CB00ull
+#define DCORE0_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC2_MSTR_IF_DBG_LBW_BASE 0x402CB80ull
+#define DCORE0_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_TPC2_MSTR_IF_CORE_HBW_BASE 0x402CC00ull
+#define DCORE0_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_TPC2_MSTR_IF_CORE_LBW_BASE 0x402CD80ull
+#define DCORE0_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_TPC2_MSTR_IF_SPECIAL_BASE 0x402CE80ull
+#define DCORE0_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE0_TPC3_QM_DCCM_BASE 0x4030000ull
+#define DCORE0_TPC3_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC3_QM_DCCM_SECTION 0x8000
+#define DCORE0_TPC3_QM_ARC_AUX_BASE 0x4038000ull
+#define DCORE0_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_QM_ARC_AUX_SECTION 0xE800
+#define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4038E80ull
+#define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE0_TPC3_QM_BASE 0x403A000ull
+#define DCORE0_TPC3_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_QM_SECTION 0x9000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x403A900ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x403A908ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x403A910ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x403A918ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x403A920ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x403A928ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x403A930ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x403A938ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x403A940ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x403A948ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x403A950ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x403A958ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x403A960ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x403A968ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x403A970ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x403A978ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_TPC3_QM_AXUSER_SECURED_BASE 0x403AB00ull
+#define DCORE0_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_TPC3_QM_AXUSER_NONSECURED_BASE 0x403AB80ull
+#define DCORE0_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_TPC3_QM_DBG_HBW_BASE 0x403AC00ull
+#define DCORE0_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC3_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC3_QM_DBG_LBW_BASE 0x403AC80ull
+#define DCORE0_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC3_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_TPC3_QM_CGM_BASE 0x403AD80ull
+#define DCORE0_TPC3_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC3_QM_CGM_SECTION 0x1000
+#define DCORE0_TPC3_QM_SPECIAL_BASE 0x403AE80ull
+#define DCORE0_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x403B000ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC3_CFG_BASE 0x403B000ull
+#define DCORE0_TPC3_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_CFG_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x403B050ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x403B0A0ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x403B0F0ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x403B140ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x403B190ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x403B1E0ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x403B230ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x403B280ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x403B2D0ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x403B320ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x403B370ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x403B3C0ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x403B410ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x403B460ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x403B4B0ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x403B500ull
+#define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC3_CFG_KERNEL_BASE 0x403B508ull
+#define DCORE0_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC3_CFG_KERNEL_SECTION 0xD400
+#define DCORE0_TPC3_CFG_QM_TENSOR_0_BASE 0x403B5DCull
+#define DCORE0_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_1_BASE 0x403B62Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_2_BASE 0x403B67Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_3_BASE 0x403B6CCull
+#define DCORE0_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_4_BASE 0x403B71Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_5_BASE 0x403B76Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_6_BASE 0x403B7BCull
+#define DCORE0_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_7_BASE 0x403B80Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_8_BASE 0x403B85Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_9_BASE 0x403B8ACull
+#define DCORE0_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_10_BASE 0x403B8FCull
+#define DCORE0_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_11_BASE 0x403B94Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_12_BASE 0x403B99Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_13_BASE 0x403B9ECull
+#define DCORE0_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_14_BASE 0x403BA3Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_15_BASE 0x403BA8Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x403BADCull
+#define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC3_CFG_QM_BASE 0x403BAE4ull
+#define DCORE0_TPC3_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC3_CFG_QM_SECTION 0x31C0
+#define DCORE0_TPC3_CFG_AXUSER_BASE 0x403BE00ull
+#define DCORE0_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_AXUSER_SECTION 0x8000
+#define DCORE0_TPC3_CFG_SPECIAL_BASE 0x403BE80ull
+#define DCORE0_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x403C000ull
+#define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x403C200ull
+#define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x403C400ull
+#define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x403C600ull
+#define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_TPC3_MSTR_IF_E2E_CRDT_BASE 0x403C800ull
+#define DCORE0_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_TPC3_MSTR_IF_AXUSER_BASE 0x403CA80ull
+#define DCORE0_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_TPC3_MSTR_IF_DBG_HBW_BASE 0x403CB00ull
+#define DCORE0_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC3_MSTR_IF_DBG_LBW_BASE 0x403CB80ull
+#define DCORE0_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_TPC3_MSTR_IF_CORE_HBW_BASE 0x403CC00ull
+#define DCORE0_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_TPC3_MSTR_IF_CORE_LBW_BASE 0x403CD80ull
+#define DCORE0_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_TPC3_MSTR_IF_SPECIAL_BASE 0x403CE80ull
+#define DCORE0_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE0_TPC4_QM_DCCM_BASE 0x4040000ull
+#define DCORE0_TPC4_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC4_QM_DCCM_SECTION 0x8000
+#define DCORE0_TPC4_QM_ARC_AUX_BASE 0x4048000ull
+#define DCORE0_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_QM_ARC_AUX_SECTION 0xE800
+#define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4048E80ull
+#define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE0_TPC4_QM_BASE 0x404A000ull
+#define DCORE0_TPC4_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_QM_SECTION 0x9000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x404A900ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x404A908ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x404A910ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x404A918ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x404A920ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x404A928ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x404A930ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x404A938ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x404A940ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x404A948ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x404A950ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x404A958ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x404A960ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x404A968ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x404A970ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x404A978ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_TPC4_QM_AXUSER_SECURED_BASE 0x404AB00ull
+#define DCORE0_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_TPC4_QM_AXUSER_NONSECURED_BASE 0x404AB80ull
+#define DCORE0_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_TPC4_QM_DBG_HBW_BASE 0x404AC00ull
+#define DCORE0_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC4_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC4_QM_DBG_LBW_BASE 0x404AC80ull
+#define DCORE0_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC4_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_TPC4_QM_CGM_BASE 0x404AD80ull
+#define DCORE0_TPC4_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC4_QM_CGM_SECTION 0x1000
+#define DCORE0_TPC4_QM_SPECIAL_BASE 0x404AE80ull
+#define DCORE0_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x404B000ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC4_CFG_BASE 0x404B000ull
+#define DCORE0_TPC4_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_CFG_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x404B050ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x404B0A0ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x404B0F0ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x404B140ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x404B190ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x404B1E0ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x404B230ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x404B280ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x404B2D0ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x404B320ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x404B370ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x404B3C0ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x404B410ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x404B460ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x404B4B0ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x404B500ull
+#define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC4_CFG_KERNEL_BASE 0x404B508ull
+#define DCORE0_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC4_CFG_KERNEL_SECTION 0xD400
+#define DCORE0_TPC4_CFG_QM_TENSOR_0_BASE 0x404B5DCull
+#define DCORE0_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_1_BASE 0x404B62Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_2_BASE 0x404B67Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_3_BASE 0x404B6CCull
+#define DCORE0_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_4_BASE 0x404B71Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_5_BASE 0x404B76Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_6_BASE 0x404B7BCull
+#define DCORE0_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_7_BASE 0x404B80Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_8_BASE 0x404B85Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_9_BASE 0x404B8ACull
+#define DCORE0_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_10_BASE 0x404B8FCull
+#define DCORE0_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_11_BASE 0x404B94Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_12_BASE 0x404B99Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_13_BASE 0x404B9ECull
+#define DCORE0_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_14_BASE 0x404BA3Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_15_BASE 0x404BA8Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x404BADCull
+#define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC4_CFG_QM_BASE 0x404BAE4ull
+#define DCORE0_TPC4_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC4_CFG_QM_SECTION 0x31C0
+#define DCORE0_TPC4_CFG_AXUSER_BASE 0x404BE00ull
+#define DCORE0_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_AXUSER_SECTION 0x8000
+#define DCORE0_TPC4_CFG_SPECIAL_BASE 0x404BE80ull
+#define DCORE0_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x404C000ull
+#define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x404C200ull
+#define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x404C400ull
+#define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x404C600ull
+#define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_TPC4_MSTR_IF_E2E_CRDT_BASE 0x404C800ull
+#define DCORE0_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_TPC4_MSTR_IF_AXUSER_BASE 0x404CA80ull
+#define DCORE0_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_TPC4_MSTR_IF_DBG_HBW_BASE 0x404CB00ull
+#define DCORE0_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC4_MSTR_IF_DBG_LBW_BASE 0x404CB80ull
+#define DCORE0_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_TPC4_MSTR_IF_CORE_HBW_BASE 0x404CC00ull
+#define DCORE0_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_TPC4_MSTR_IF_CORE_LBW_BASE 0x404CD80ull
+#define DCORE0_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_TPC4_MSTR_IF_SPECIAL_BASE 0x404CE80ull
+#define DCORE0_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE0_TPC5_QM_DCCM_BASE 0x4050000ull
+#define DCORE0_TPC5_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC5_QM_DCCM_SECTION 0x8000
+#define DCORE0_TPC5_QM_ARC_AUX_BASE 0x4058000ull
+#define DCORE0_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_QM_ARC_AUX_SECTION 0xE800
+#define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4058E80ull
+#define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE0_TPC5_QM_BASE 0x405A000ull
+#define DCORE0_TPC5_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_QM_SECTION 0x9000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x405A900ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x405A908ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x405A910ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x405A918ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x405A920ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x405A928ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x405A930ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x405A938ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x405A940ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x405A948ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x405A950ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x405A958ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x405A960ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x405A968ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x405A970ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x405A978ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_TPC5_QM_AXUSER_SECURED_BASE 0x405AB00ull
+#define DCORE0_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_TPC5_QM_AXUSER_NONSECURED_BASE 0x405AB80ull
+#define DCORE0_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_TPC5_QM_DBG_HBW_BASE 0x405AC00ull
+#define DCORE0_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC5_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC5_QM_DBG_LBW_BASE 0x405AC80ull
+#define DCORE0_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC5_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_TPC5_QM_CGM_BASE 0x405AD80ull
+#define DCORE0_TPC5_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC5_QM_CGM_SECTION 0x1000
+#define DCORE0_TPC5_QM_SPECIAL_BASE 0x405AE80ull
+#define DCORE0_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x405B000ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC5_CFG_BASE 0x405B000ull
+#define DCORE0_TPC5_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_CFG_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x405B050ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x405B0A0ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x405B0F0ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x405B140ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x405B190ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x405B1E0ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x405B230ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x405B280ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x405B2D0ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x405B320ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x405B370ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x405B3C0ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x405B410ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x405B460ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x405B4B0ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x405B500ull
+#define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC5_CFG_KERNEL_BASE 0x405B508ull
+#define DCORE0_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC5_CFG_KERNEL_SECTION 0xD400
+#define DCORE0_TPC5_CFG_QM_TENSOR_0_BASE 0x405B5DCull
+#define DCORE0_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_1_BASE 0x405B62Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_2_BASE 0x405B67Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_3_BASE 0x405B6CCull
+#define DCORE0_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_4_BASE 0x405B71Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_5_BASE 0x405B76Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_6_BASE 0x405B7BCull
+#define DCORE0_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_7_BASE 0x405B80Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_8_BASE 0x405B85Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_9_BASE 0x405B8ACull
+#define DCORE0_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_10_BASE 0x405B8FCull
+#define DCORE0_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_11_BASE 0x405B94Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_12_BASE 0x405B99Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_13_BASE 0x405B9ECull
+#define DCORE0_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_14_BASE 0x405BA3Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_15_BASE 0x405BA8Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x405BADCull
+#define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC5_CFG_QM_BASE 0x405BAE4ull
+#define DCORE0_TPC5_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC5_CFG_QM_SECTION 0x31C0
+#define DCORE0_TPC5_CFG_AXUSER_BASE 0x405BE00ull
+#define DCORE0_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_AXUSER_SECTION 0x8000
+#define DCORE0_TPC5_CFG_SPECIAL_BASE 0x405BE80ull
+#define DCORE0_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x405C000ull
+#define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x405C200ull
+#define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x405C400ull
+#define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x405C600ull
+#define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_TPC5_MSTR_IF_E2E_CRDT_BASE 0x405C800ull
+#define DCORE0_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_TPC5_MSTR_IF_AXUSER_BASE 0x405CA80ull
+#define DCORE0_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_TPC5_MSTR_IF_DBG_HBW_BASE 0x405CB00ull
+#define DCORE0_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC5_MSTR_IF_DBG_LBW_BASE 0x405CB80ull
+#define DCORE0_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_TPC5_MSTR_IF_CORE_HBW_BASE 0x405CC00ull
+#define DCORE0_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_TPC5_MSTR_IF_CORE_LBW_BASE 0x405CD80ull
+#define DCORE0_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_TPC5_MSTR_IF_SPECIAL_BASE 0x405CE80ull
+#define DCORE0_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE0_TPC6_QM_DCCM_BASE 0x4060000ull
+#define DCORE0_TPC6_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC6_QM_DCCM_SECTION 0x8000
+#define DCORE0_TPC6_QM_ARC_AUX_BASE 0x4068000ull
+#define DCORE0_TPC6_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_QM_ARC_AUX_SECTION 0xE800
+#define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_BASE 0x4068E80ull
+#define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE0_TPC6_QM_BASE 0x406A000ull
+#define DCORE0_TPC6_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_QM_SECTION 0x9000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_BASE 0x406A900ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_BASE 0x406A908ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_BASE 0x406A910ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_BASE 0x406A918ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_BASE 0x406A920ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_BASE 0x406A928ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_BASE 0x406A930ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_BASE 0x406A938ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_BASE 0x406A940ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_BASE 0x406A948ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_BASE 0x406A950ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_BASE 0x406A958ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_BASE 0x406A960ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_BASE 0x406A968ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_BASE 0x406A970ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_BASE 0x406A978ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_TPC6_QM_AXUSER_SECURED_BASE 0x406AB00ull
+#define DCORE0_TPC6_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_TPC6_QM_AXUSER_NONSECURED_BASE 0x406AB80ull
+#define DCORE0_TPC6_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_TPC6_QM_DBG_HBW_BASE 0x406AC00ull
+#define DCORE0_TPC6_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC6_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC6_QM_DBG_LBW_BASE 0x406AC80ull
+#define DCORE0_TPC6_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC6_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_TPC6_QM_CGM_BASE 0x406AD80ull
+#define DCORE0_TPC6_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC6_QM_CGM_SECTION 0x1000
+#define DCORE0_TPC6_QM_SPECIAL_BASE 0x406AE80ull
+#define DCORE0_TPC6_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_0_BASE 0x406B000ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC6_CFG_BASE 0x406B000ull
+#define DCORE0_TPC6_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_CFG_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_BASE 0x406B050ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_BASE 0x406B0A0ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_BASE 0x406B0F0ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_BASE 0x406B140ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_BASE 0x406B190ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_BASE 0x406B1E0ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_BASE 0x406B230ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_BASE 0x406B280ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_BASE 0x406B2D0ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_BASE 0x406B320ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_BASE 0x406B370ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_BASE 0x406B3C0ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_BASE 0x406B410ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_BASE 0x406B460ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_BASE 0x406B4B0ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_BASE 0x406B500ull
+#define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC6_CFG_KERNEL_BASE 0x406B508ull
+#define DCORE0_TPC6_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC6_CFG_KERNEL_SECTION 0xD400
+#define DCORE0_TPC6_CFG_QM_TENSOR_0_BASE 0x406B5DCull
+#define DCORE0_TPC6_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_1_BASE 0x406B62Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_2_BASE 0x406B67Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_3_BASE 0x406B6CCull
+#define DCORE0_TPC6_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_4_BASE 0x406B71Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_5_BASE 0x406B76Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_6_BASE 0x406B7BCull
+#define DCORE0_TPC6_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_7_BASE 0x406B80Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_8_BASE 0x406B85Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_9_BASE 0x406B8ACull
+#define DCORE0_TPC6_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_10_BASE 0x406B8FCull
+#define DCORE0_TPC6_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_11_BASE 0x406B94Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_12_BASE 0x406B99Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_13_BASE 0x406B9ECull
+#define DCORE0_TPC6_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_14_BASE 0x406BA3Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_15_BASE 0x406BA8Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_BASE 0x406BADCull
+#define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE0_TPC6_CFG_QM_BASE 0x406BAE4ull
+#define DCORE0_TPC6_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC6_CFG_QM_SECTION 0x31C0
+#define DCORE0_TPC6_CFG_AXUSER_BASE 0x406BE00ull
+#define DCORE0_TPC6_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_AXUSER_SECTION 0x8000
+#define DCORE0_TPC6_CFG_SPECIAL_BASE 0x406BE80ull
+#define DCORE0_TPC6_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_CFG_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_BASE 0x406C000ull
+#define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_BASE 0x406C200ull
+#define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_BASE 0x406C400ull
+#define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_BASE 0x406C600ull
+#define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_TPC6_MSTR_IF_E2E_CRDT_BASE 0x406C800ull
+#define DCORE0_TPC6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_TPC6_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_TPC6_MSTR_IF_AXUSER_BASE 0x406CA80ull
+#define DCORE0_TPC6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_TPC6_MSTR_IF_DBG_HBW_BASE 0x406CB00ull
+#define DCORE0_TPC6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC6_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_TPC6_MSTR_IF_DBG_LBW_BASE 0x406CB80ull
+#define DCORE0_TPC6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC6_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_TPC6_MSTR_IF_CORE_HBW_BASE 0x406CC00ull
+#define DCORE0_TPC6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_TPC6_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_TPC6_MSTR_IF_CORE_LBW_BASE 0x406CD80ull
+#define DCORE0_TPC6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_TPC6_MSTR_IF_SPECIAL_BASE 0x406CE80ull
+#define DCORE0_TPC6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_MSTR_IF_SPECIAL_SECTION 0x13180
+#define DCORE0_HMMU0_MMU_BASE 0x4080000ull
+#define DCORE0_HMMU0_MMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_MMU_SECTION 0xE800
+#define DCORE0_HMMU0_MMU_SPECIAL_BASE 0x4080E80ull
+#define DCORE0_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU0_MMU_SPECIAL_SECTION 0x1800
+#define DCORE0_HMMU0_STLB_BASE 0x4081000ull
+#define DCORE0_HMMU0_STLB_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_STLB_SECTION 0xE800
+#define DCORE0_HMMU0_STLB_SPECIAL_BASE 0x4081E80ull
+#define DCORE0_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU0_STLB_SPECIAL_SECTION 0x1180
+#define DCORE0_HMMU0_SCRAMB_OUT_BASE 0x4083000ull
+#define DCORE0_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_SCRAMB_OUT_SECTION 0xE800
+#define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4083E80ull
+#define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4084000ull
+#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4084200ull
+#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4084400ull
+#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4084600ull
+#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4084800ull
+#define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_HMMU0_MSTR_IF_AXUSER_BASE 0x4084A80ull
+#define DCORE0_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4084B00ull
+#define DCORE0_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4084B80ull
+#define DCORE0_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4084C00ull
+#define DCORE0_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4084D80ull
+#define DCORE0_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_HMMU0_MSTR_IF_SPECIAL_BASE 0x4084E80ull
+#define DCORE0_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE0_HMMU1_MMU_BASE 0x4090000ull
+#define DCORE0_HMMU1_MMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_MMU_SECTION 0xE800
+#define DCORE0_HMMU1_MMU_SPECIAL_BASE 0x4090E80ull
+#define DCORE0_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU1_MMU_SPECIAL_SECTION 0x1800
+#define DCORE0_HMMU1_STLB_BASE 0x4091000ull
+#define DCORE0_HMMU1_STLB_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_STLB_SECTION 0xE800
+#define DCORE0_HMMU1_STLB_SPECIAL_BASE 0x4091E80ull
+#define DCORE0_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU1_STLB_SPECIAL_SECTION 0x1180
+#define DCORE0_HMMU1_SCRAMB_OUT_BASE 0x4093000ull
+#define DCORE0_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_SCRAMB_OUT_SECTION 0xE800
+#define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4093E80ull
+#define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4094000ull
+#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4094200ull
+#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4094400ull
+#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4094600ull
+#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4094800ull
+#define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_HMMU1_MSTR_IF_AXUSER_BASE 0x4094A80ull
+#define DCORE0_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4094B00ull
+#define DCORE0_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4094B80ull
+#define DCORE0_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4094C00ull
+#define DCORE0_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4094D80ull
+#define DCORE0_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_HMMU1_MSTR_IF_SPECIAL_BASE 0x4094E80ull
+#define DCORE0_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE0_HMMU2_MMU_BASE 0x40A0000ull
+#define DCORE0_HMMU2_MMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_MMU_SECTION 0xE800
+#define DCORE0_HMMU2_MMU_SPECIAL_BASE 0x40A0E80ull
+#define DCORE0_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU2_MMU_SPECIAL_SECTION 0x1800
+#define DCORE0_HMMU2_STLB_BASE 0x40A1000ull
+#define DCORE0_HMMU2_STLB_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_STLB_SECTION 0xE800
+#define DCORE0_HMMU2_STLB_SPECIAL_BASE 0x40A1E80ull
+#define DCORE0_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU2_STLB_SPECIAL_SECTION 0x1180
+#define DCORE0_HMMU2_SCRAMB_OUT_BASE 0x40A3000ull
+#define DCORE0_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_SCRAMB_OUT_SECTION 0xE800
+#define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x40A3E80ull
+#define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x40A4000ull
+#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x40A4200ull
+#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x40A4400ull
+#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x40A4600ull
+#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x40A4800ull
+#define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_HMMU2_MSTR_IF_AXUSER_BASE 0x40A4A80ull
+#define DCORE0_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_HMMU2_MSTR_IF_DBG_HBW_BASE 0x40A4B00ull
+#define DCORE0_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_HMMU2_MSTR_IF_DBG_LBW_BASE 0x40A4B80ull
+#define DCORE0_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_HMMU2_MSTR_IF_CORE_HBW_BASE 0x40A4C00ull
+#define DCORE0_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_HMMU2_MSTR_IF_CORE_LBW_BASE 0x40A4D80ull
+#define DCORE0_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_HMMU2_MSTR_IF_SPECIAL_BASE 0x40A4E80ull
+#define DCORE0_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE0_HMMU3_MMU_BASE 0x40B0000ull
+#define DCORE0_HMMU3_MMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_MMU_SECTION 0xE800
+#define DCORE0_HMMU3_MMU_SPECIAL_BASE 0x40B0E80ull
+#define DCORE0_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU3_MMU_SPECIAL_SECTION 0x1800
+#define DCORE0_HMMU3_STLB_BASE 0x40B1000ull
+#define DCORE0_HMMU3_STLB_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_STLB_SECTION 0xE800
+#define DCORE0_HMMU3_STLB_SPECIAL_BASE 0x40B1E80ull
+#define DCORE0_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU3_STLB_SPECIAL_SECTION 0x1180
+#define DCORE0_HMMU3_SCRAMB_OUT_BASE 0x40B3000ull
+#define DCORE0_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_SCRAMB_OUT_SECTION 0xE800
+#define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x40B3E80ull
+#define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x40B4000ull
+#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x40B4200ull
+#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x40B4400ull
+#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x40B4600ull
+#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x40B4800ull
+#define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_HMMU3_MSTR_IF_AXUSER_BASE 0x40B4A80ull
+#define DCORE0_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_HMMU3_MSTR_IF_DBG_HBW_BASE 0x40B4B00ull
+#define DCORE0_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_HMMU3_MSTR_IF_DBG_LBW_BASE 0x40B4B80ull
+#define DCORE0_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_HMMU3_MSTR_IF_CORE_HBW_BASE 0x40B4C00ull
+#define DCORE0_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_HMMU3_MSTR_IF_CORE_LBW_BASE 0x40B4D80ull
+#define DCORE0_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_HMMU3_MSTR_IF_SPECIAL_BASE 0x40B4E80ull
+#define DCORE0_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE0_MME_QM_ARC_DCCM_BASE 0x40C0000ull
+#define DCORE0_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_MME_QM_ARC_DCCM_SECTION 0x8000
+#define DCORE0_MME_QM_ARC_AUX_BASE 0x40C8000ull
+#define DCORE0_MME_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_MME_QM_ARC_AUX_SECTION 0xE800
+#define DCORE0_MME_QM_ARC_AUX_SPECIAL_BASE 0x40C8E80ull
+#define DCORE0_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_QM_ARC_DUP_ENG_BASE 0x40C9000ull
+#define DCORE0_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000
+#define DCORE0_MME_QM_ARC_DUP_ENG_SECTION 0x9000
+#define DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x40C9900ull
+#define DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800
+#define DCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x40C9E80ull
+#define DCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_QM_BASE 0x40CA000ull
+#define DCORE0_MME_QM_MAX_OFFSET 0x1000
+#define DCORE0_MME_QM_SECTION 0x9000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x40CA900ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x40CA908ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x40CA910ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x40CA918ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x40CA920ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x40CA928ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x40CA930ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x40CA938ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x40CA940ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x40CA948ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x40CA950ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x40CA958ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x40CA960ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x40CA968ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x40CA970ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x40CA978ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_MME_QM_AXUSER_SECURED_BASE 0x40CAB00ull
+#define DCORE0_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_MME_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_MME_QM_AXUSER_NONSECURED_BASE 0x40CAB80ull
+#define DCORE0_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_MME_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_MME_QM_DBG_HBW_BASE 0x40CAC00ull
+#define DCORE0_MME_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_MME_QM_DBG_LBW_BASE 0x40CAC80ull
+#define DCORE0_MME_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_MME_QM_CGM_BASE 0x40CAD80ull
+#define DCORE0_MME_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_MME_QM_CGM_SECTION 0x1000
+#define DCORE0_MME_QM_SPECIAL_BASE 0x40CAE80ull
+#define DCORE0_MME_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_CTRL_LO_BASE 0x40CB000ull
+#define DCORE0_MME_CTRL_LO_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_LO_SECTION 0x8000
+#define DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x40CB008ull
+#define DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000
+#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x40CB028ull
+#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x40CB040ull
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x40CB098ull
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x40CB0F0ull
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x40CB15Cull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x40CB170ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x40CB184ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x40CB198ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x40CB1ACull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x40CB1C0ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x40CB1D4ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x40CB1E8ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x40CB1FCull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x40CB210ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x40CB22Cull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x40CB240ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x40CB254ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x40CB268ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x40CB280ull
+#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800
+#define DCORE0_MME_CTRL_LO_MME_AXUSER_BASE 0x40CBE00ull
+#define DCORE0_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000
+#define DCORE0_MME_CTRL_LO_SPECIAL_BASE 0x40CBE80ull
+#define DCORE0_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_LO_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_CTRL_HI_BASE 0x40CC000ull
+#define DCORE0_MME_CTRL_HI_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_HI_SECTION 0x8000
+#define DCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x40CC008ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000
+#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x40CC028ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x40CC040ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x40CC098ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x40CC0F0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x40CC15Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x40CC170ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x40CC184ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x40CC198ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x40CC1ACull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x40CC1C0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x40CC1D4ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x40CC1E8ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x40CC1FCull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x40CC210ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x40CC22Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x40CC240ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x40CC254ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x40CC268ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x40CC280ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800
+#define DCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x40CC308ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000
+#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x40CC328ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x40CC340ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x40CC398ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x40CC3F0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x40CC45Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x40CC470ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x40CC484ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x40CC498ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x40CC4ACull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x40CC4C0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x40CC4D4ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x40CC4E8ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x40CC4FCull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x40CC510ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x40CC52Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x40CC540ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x40CC554ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x40CC568ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x40CC580ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800
+#define DCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x40CC608ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000
+#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x40CC628ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x40CC640ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x40CC698ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x40CC6F0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x40CC75Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x40CC770ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x40CC784ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x40CC798ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x40CC7ACull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x40CC7C0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x40CC7D4ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x40CC7E8ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x40CC7FCull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x40CC810ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x40CC82Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x40CC840ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x40CC854ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x40CC868ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x40CC880ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800
+#define DCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x40CC908ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000
+#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x40CC928ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x40CC940ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x40CC998ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x40CC9F0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x40CCA5Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x40CCA70ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x40CCA84ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x40CCA98ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x40CCAACull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x40CCAC0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x40CCAD4ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x40CCAE8ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x40CCAFCull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x40CCB10ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x40CCB2Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x40CCB40ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x40CCB54ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x40CCB68ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x40CCB80ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000
+#define DCORE0_MME_CTRL_HI_SPECIAL_BASE 0x40CCE80ull
+#define DCORE0_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_HI_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_EU_BIST_BASE 0x40CD000ull
+#define DCORE0_MME_EU_BIST_MAX_OFFSET 0x1000
+#define DCORE0_MME_EU_BIST_SECTION 0xE800
+#define DCORE0_MME_EU_BIST_SPECIAL_BASE 0x40CDE80ull
+#define DCORE0_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_EU_BIST_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x40CE000ull
+#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x40CE200ull
+#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x40CE400ull
+#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x40CE600ull
+#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x40CE800ull
+#define DCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_MME_CTRL_MSTR_IF_AXUSER_BASE 0x40CEA80ull
+#define DCORE0_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x40CEB00ull
+#define DCORE0_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x40CEB80ull
+#define DCORE0_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x40CEC00ull
+#define DCORE0_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x40CED80ull
+#define DCORE0_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x40CEE80ull
+#define DCORE0_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_QM_ARC_ACP_ENG_BASE 0x40CF000ull
+#define DCORE0_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000
+#define DCORE0_MME_QM_ARC_ACP_ENG_SECTION 0xE800
+#define DCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x40CFE80ull
+#define DCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_SBTE0_BASE 0x40D0000ull
+#define DCORE0_MME_SBTE0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_SECTION 0xE800
+#define DCORE0_MME_SBTE0_SPECIAL_BASE 0x40D0E80ull
+#define DCORE0_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE0_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x40D1000ull
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x40D1200ull
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x40D1400ull
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x40D1600ull
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x40D1800ull
+#define DCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x40D1A80ull
+#define DCORE0_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x40D1B00ull
+#define DCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x40D1B80ull
+#define DCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x40D1C00ull
+#define DCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x40D1D80ull
+#define DCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x40D1E80ull
+#define DCORE0_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE0_MME_SBTE1_BASE 0x40D8000ull
+#define DCORE0_MME_SBTE1_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_SECTION 0xE800
+#define DCORE0_MME_SBTE1_SPECIAL_BASE 0x40D8E80ull
+#define DCORE0_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE1_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x40D9000ull
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x40D9200ull
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x40D9400ull
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x40D9600ull
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x40D9800ull
+#define DCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x40D9A80ull
+#define DCORE0_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x40D9B00ull
+#define DCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x40D9B80ull
+#define DCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x40D9C00ull
+#define DCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x40D9D80ull
+#define DCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x40D9E80ull
+#define DCORE0_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE0_MME_SBTE2_BASE 0x40E0000ull
+#define DCORE0_MME_SBTE2_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_SECTION 0xE800
+#define DCORE0_MME_SBTE2_SPECIAL_BASE 0x40E0E80ull
+#define DCORE0_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE2_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x40E1000ull
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x40E1200ull
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x40E1400ull
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x40E1600ull
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x40E1800ull
+#define DCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x40E1A80ull
+#define DCORE0_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x40E1B00ull
+#define DCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x40E1B80ull
+#define DCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x40E1C00ull
+#define DCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x40E1D80ull
+#define DCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x40E1E80ull
+#define DCORE0_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE0_MME_SBTE3_BASE 0x40E8000ull
+#define DCORE0_MME_SBTE3_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_SECTION 0xE800
+#define DCORE0_MME_SBTE3_SPECIAL_BASE 0x40E8E80ull
+#define DCORE0_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE3_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x40E9000ull
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x40E9200ull
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x40E9400ull
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x40E9600ull
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x40E9800ull
+#define DCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x40E9A80ull
+#define DCORE0_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x40E9B00ull
+#define DCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x40E9B80ull
+#define DCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x40E9C00ull
+#define DCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x40E9D80ull
+#define DCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x40E9E80ull
+#define DCORE0_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE0_MME_SBTE4_BASE 0x40F0000ull
+#define DCORE0_MME_SBTE4_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_SECTION 0xE800
+#define DCORE0_MME_SBTE4_SPECIAL_BASE 0x40F0E80ull
+#define DCORE0_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE4_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x40F1000ull
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x40F1200ull
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x40F1400ull
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x40F1600ull
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x40F1800ull
+#define DCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x40F1A80ull
+#define DCORE0_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x40F1B00ull
+#define DCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x40F1B80ull
+#define DCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x40F1C00ull
+#define DCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x40F1D80ull
+#define DCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x40F1E80ull
+#define DCORE0_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE0_MME_ACC_BASE 0x40F8000ull
+#define DCORE0_MME_ACC_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_SECTION 0xE800
+#define DCORE0_MME_ACC_SPECIAL_BASE 0x40F8E80ull
+#define DCORE0_MME_ACC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_ACC_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x40F9000ull
+#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x40F9200ull
+#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x40F9400ull
+#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x40F9600ull
+#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x40F9800ull
+#define DCORE0_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_MME_WB0_MSTR_IF_AXUSER_BASE 0x40F9A80ull
+#define DCORE0_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x40F9B00ull
+#define DCORE0_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x40F9B80ull
+#define DCORE0_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x40F9C00ull
+#define DCORE0_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x40F9D80ull
+#define DCORE0_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_MME_WB0_MSTR_IF_SPECIAL_BASE 0x40F9E80ull
+#define DCORE0_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x40FA000ull
+#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x40FA200ull
+#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x40FA400ull
+#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x40FA600ull
+#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x40FA800ull
+#define DCORE0_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_MME_WB1_MSTR_IF_AXUSER_BASE 0x40FAA80ull
+#define DCORE0_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x40FAB00ull
+#define DCORE0_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x40FAB80ull
+#define DCORE0_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x40FAC00ull
+#define DCORE0_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x40FAD80ull
+#define DCORE0_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_MME_WB1_MSTR_IF_SPECIAL_BASE 0x40FAE80ull
+#define DCORE0_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180
+#define DCORE0_SYNC_MNGR_OBJS_BASE 0x4100000ull
+#define DCORE0_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00
+#define DCORE0_SYNC_MNGR_OBJS_SECTION 0x1E000
+#define DCORE0_SYNC_MNGR_GLBL_BASE 0x411E000ull
+#define DCORE0_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000
+#define DCORE0_SYNC_MNGR_GLBL_SECTION 0xE800
+#define DCORE0_SYNC_MNGR_GLBL_SPECIAL_BASE 0x411EE80ull
+#define DCORE0_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x411F000ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x411F200ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x411F400ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x411F600ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x411F800ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x411FA80ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x411FB00ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x411FB80ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x411FC00ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x411FD80ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x411FE80ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE0_HIF0_BASE 0x4120000ull
+#define DCORE0_HIF0_MAX_OFFSET 0x1000
+#define DCORE0_HIF0_SECTION 0xE800
+#define DCORE0_HIF0_SPECIAL_BASE 0x4120E80ull
+#define DCORE0_HIF0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HIF0_SPECIAL_SECTION 0x3180
+#define DCORE0_HIF1_BASE 0x4124000ull
+#define DCORE0_HIF1_MAX_OFFSET 0x1000
+#define DCORE0_HIF1_SECTION 0xE800
+#define DCORE0_HIF1_SPECIAL_BASE 0x4124E80ull
+#define DCORE0_HIF1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HIF1_SPECIAL_SECTION 0x3180
+#define DCORE0_HIF2_BASE 0x4128000ull
+#define DCORE0_HIF2_MAX_OFFSET 0x1000
+#define DCORE0_HIF2_SECTION 0xE800
+#define DCORE0_HIF2_SPECIAL_BASE 0x4128E80ull
+#define DCORE0_HIF2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HIF2_SPECIAL_SECTION 0x3180
+#define DCORE0_HIF3_BASE 0x412C000ull
+#define DCORE0_HIF3_MAX_OFFSET 0x1000
+#define DCORE0_HIF3_SECTION 0xE800
+#define DCORE0_HIF3_SPECIAL_BASE 0x412CE80ull
+#define DCORE0_HIF3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HIF3_SPECIAL_SECTION 0x13180
+#define DCORE0_RTR0_CTRL_BASE 0x4140000ull
+#define DCORE0_RTR0_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR0_CTRL_SECTION 0xE800
+#define DCORE0_RTR0_CTRL_SPECIAL_BASE 0x4140E80ull
+#define DCORE0_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR0_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR0_H3_BASE 0x4141000ull
+#define DCORE0_RTR0_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR0_H3_SECTION 0xE800
+#define DCORE0_RTR0_H3_SPECIAL_BASE 0x4141E80ull
+#define DCORE0_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR0_H3_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4142000ull
+#define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4142200ull
+#define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4142400ull
+#define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4142600ull
+#define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4142800ull
+#define DCORE0_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_RTR0_MSTR_IF_AXUSER_BASE 0x4142A80ull
+#define DCORE0_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_RTR0_MSTR_IF_DBG_HBW_BASE 0x4142B00ull
+#define DCORE0_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_RTR0_MSTR_IF_DBG_LBW_BASE 0x4142B80ull
+#define DCORE0_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_RTR0_MSTR_IF_CORE_HBW_BASE 0x4142C00ull
+#define DCORE0_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_RTR0_MSTR_IF_CORE_LBW_BASE 0x4142D80ull
+#define DCORE0_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_RTR0_MSTR_IF_SPECIAL_BASE 0x4142E80ull
+#define DCORE0_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR0_ADD_DEC_HBW_BASE 0x4143000ull
+#define DCORE0_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR0_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE0_RTR0_ADD_DEC_LBW_BASE 0x4143400ull
+#define DCORE0_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR0_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE0_RTR0_ADD_DEC_SPECIAL_BASE 0x4143E80ull
+#define DCORE0_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR0_BASE 0x4144000ull
+#define DCORE0_RTR0_MAX_OFFSET 0x1000
+#define DCORE0_RTR0_SECTION 0x3000
+#define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4144300ull
+#define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4144340ull
+#define DCORE0_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4144380ull
+#define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR0_HBW_WR_RS_LL_STAT_BASE 0x41443C0ull
+#define DCORE0_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4144400ull
+#define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4144440ull
+#define DCORE0_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4144480ull
+#define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR0_LBW_WR_RS_LL_STAT_BASE 0x41444C0ull
+#define DCORE0_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR0_HBW_MFIFO_BASE 0x4144500ull
+#define DCORE0_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_HBW_MFIFO_SECTION 0x4000
+#define DCORE0_RTR0_E2E_RD_LL_STAT_BASE 0x4144540ull
+#define DCORE0_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR0_E2E_WR_LL_STAT_BASE 0x4144580ull
+#define DCORE0_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE0_RTR0_RTR_HBW_XACT_STAT_BASE 0x4144600ull
+#define DCORE0_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR0_RTR_LBW_XACT_STAT_BASE 0x4144680ull
+#define DCORE0_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR0_RTR_E2E_XACT_STAT_BASE 0x4144700ull
+#define DCORE0_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE0_RTR0_SPECIAL_BASE 0x4144E80ull
+#define DCORE0_RTR0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR0_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR0_DBG_ADDR_BASE 0x4145000ull
+#define DCORE0_RTR0_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR0_DBG_ADDR_SECTION 0xE800
+#define DCORE0_RTR0_DBG_ADDR_SPECIAL_BASE 0x4145E80ull
+#define DCORE0_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE0_RTR1_CTRL_BASE 0x4148000ull
+#define DCORE0_RTR1_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR1_CTRL_SECTION 0xE800
+#define DCORE0_RTR1_CTRL_SPECIAL_BASE 0x4148E80ull
+#define DCORE0_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR1_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR1_H3_BASE 0x4149000ull
+#define DCORE0_RTR1_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR1_H3_SECTION 0xE800
+#define DCORE0_RTR1_H3_SPECIAL_BASE 0x4149E80ull
+#define DCORE0_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR1_H3_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x414A000ull
+#define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x414A200ull
+#define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x414A400ull
+#define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x414A600ull
+#define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_RTR1_MSTR_IF_E2E_CRDT_BASE 0x414A800ull
+#define DCORE0_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_RTR1_MSTR_IF_AXUSER_BASE 0x414AA80ull
+#define DCORE0_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_RTR1_MSTR_IF_DBG_HBW_BASE 0x414AB00ull
+#define DCORE0_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_RTR1_MSTR_IF_DBG_LBW_BASE 0x414AB80ull
+#define DCORE0_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_RTR1_MSTR_IF_CORE_HBW_BASE 0x414AC00ull
+#define DCORE0_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_RTR1_MSTR_IF_CORE_LBW_BASE 0x414AD80ull
+#define DCORE0_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_RTR1_MSTR_IF_SPECIAL_BASE 0x414AE80ull
+#define DCORE0_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR1_ADD_DEC_HBW_BASE 0x414B000ull
+#define DCORE0_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR1_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE0_RTR1_ADD_DEC_LBW_BASE 0x414B400ull
+#define DCORE0_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR1_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE0_RTR1_ADD_DEC_SPECIAL_BASE 0x414BE80ull
+#define DCORE0_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR1_BASE 0x414C000ull
+#define DCORE0_RTR1_MAX_OFFSET 0x1000
+#define DCORE0_RTR1_SECTION 0x3000
+#define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x414C300ull
+#define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR1_HBW_RD_RS_LL_STAT_BASE 0x414C340ull
+#define DCORE0_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x414C380ull
+#define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR1_HBW_WR_RS_LL_STAT_BASE 0x414C3C0ull
+#define DCORE0_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x414C400ull
+#define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR1_LBW_RD_RS_LL_STAT_BASE 0x414C440ull
+#define DCORE0_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x414C480ull
+#define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR1_LBW_WR_RS_LL_STAT_BASE 0x414C4C0ull
+#define DCORE0_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR1_HBW_MFIFO_BASE 0x414C500ull
+#define DCORE0_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_HBW_MFIFO_SECTION 0x4000
+#define DCORE0_RTR1_E2E_RD_LL_STAT_BASE 0x414C540ull
+#define DCORE0_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR1_E2E_WR_LL_STAT_BASE 0x414C580ull
+#define DCORE0_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE0_RTR1_RTR_HBW_XACT_STAT_BASE 0x414C600ull
+#define DCORE0_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR1_RTR_LBW_XACT_STAT_BASE 0x414C680ull
+#define DCORE0_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR1_RTR_E2E_XACT_STAT_BASE 0x414C700ull
+#define DCORE0_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE0_RTR1_SPECIAL_BASE 0x414CE80ull
+#define DCORE0_RTR1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR1_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR1_DBG_ADDR_BASE 0x414D000ull
+#define DCORE0_RTR1_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR1_DBG_ADDR_SECTION 0xE800
+#define DCORE0_RTR1_DBG_ADDR_SPECIAL_BASE 0x414DE80ull
+#define DCORE0_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE0_RTR2_CTRL_BASE 0x4150000ull
+#define DCORE0_RTR2_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR2_CTRL_SECTION 0xE800
+#define DCORE0_RTR2_CTRL_SPECIAL_BASE 0x4150E80ull
+#define DCORE0_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR2_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR2_H3_BASE 0x4151000ull
+#define DCORE0_RTR2_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR2_H3_SECTION 0xE800
+#define DCORE0_RTR2_H3_SPECIAL_BASE 0x4151E80ull
+#define DCORE0_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR2_H3_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4152000ull
+#define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4152200ull
+#define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4152400ull
+#define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4152600ull
+#define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4152800ull
+#define DCORE0_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_RTR2_MSTR_IF_AXUSER_BASE 0x4152A80ull
+#define DCORE0_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_RTR2_MSTR_IF_DBG_HBW_BASE 0x4152B00ull
+#define DCORE0_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_RTR2_MSTR_IF_DBG_LBW_BASE 0x4152B80ull
+#define DCORE0_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_RTR2_MSTR_IF_CORE_HBW_BASE 0x4152C00ull
+#define DCORE0_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_RTR2_MSTR_IF_CORE_LBW_BASE 0x4152D80ull
+#define DCORE0_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_RTR2_MSTR_IF_SPECIAL_BASE 0x4152E80ull
+#define DCORE0_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR2_ADD_DEC_HBW_BASE 0x4153000ull
+#define DCORE0_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR2_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE0_RTR2_ADD_DEC_LBW_BASE 0x4153400ull
+#define DCORE0_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR2_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE0_RTR2_ADD_DEC_SPECIAL_BASE 0x4153E80ull
+#define DCORE0_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR2_BASE 0x4154000ull
+#define DCORE0_RTR2_MAX_OFFSET 0x1000
+#define DCORE0_RTR2_SECTION 0x3000
+#define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4154300ull
+#define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4154340ull
+#define DCORE0_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4154380ull
+#define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR2_HBW_WR_RS_LL_STAT_BASE 0x41543C0ull
+#define DCORE0_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4154400ull
+#define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4154440ull
+#define DCORE0_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4154480ull
+#define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR2_LBW_WR_RS_LL_STAT_BASE 0x41544C0ull
+#define DCORE0_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR2_HBW_MFIFO_BASE 0x4154500ull
+#define DCORE0_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_HBW_MFIFO_SECTION 0x4000
+#define DCORE0_RTR2_E2E_RD_LL_STAT_BASE 0x4154540ull
+#define DCORE0_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR2_E2E_WR_LL_STAT_BASE 0x4154580ull
+#define DCORE0_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE0_RTR2_RTR_HBW_XACT_STAT_BASE 0x4154600ull
+#define DCORE0_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR2_RTR_LBW_XACT_STAT_BASE 0x4154680ull
+#define DCORE0_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR2_RTR_E2E_XACT_STAT_BASE 0x4154700ull
+#define DCORE0_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE0_RTR2_SPECIAL_BASE 0x4154E80ull
+#define DCORE0_RTR2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR2_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR2_DBG_ADDR_BASE 0x4155000ull
+#define DCORE0_RTR2_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR2_DBG_ADDR_SECTION 0xE800
+#define DCORE0_RTR2_DBG_ADDR_SPECIAL_BASE 0x4155E80ull
+#define DCORE0_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE0_RTR3_CTRL_BASE 0x4158000ull
+#define DCORE0_RTR3_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR3_CTRL_SECTION 0xE800
+#define DCORE0_RTR3_CTRL_SPECIAL_BASE 0x4158E80ull
+#define DCORE0_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR3_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR3_H3_BASE 0x4159000ull
+#define DCORE0_RTR3_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR3_H3_SECTION 0xE800
+#define DCORE0_RTR3_H3_SPECIAL_BASE 0x4159E80ull
+#define DCORE0_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR3_H3_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x415A000ull
+#define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x415A200ull
+#define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x415A400ull
+#define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x415A600ull
+#define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_RTR3_MSTR_IF_E2E_CRDT_BASE 0x415A800ull
+#define DCORE0_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_RTR3_MSTR_IF_AXUSER_BASE 0x415AA80ull
+#define DCORE0_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_RTR3_MSTR_IF_DBG_HBW_BASE 0x415AB00ull
+#define DCORE0_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_RTR3_MSTR_IF_DBG_LBW_BASE 0x415AB80ull
+#define DCORE0_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_RTR3_MSTR_IF_CORE_HBW_BASE 0x415AC00ull
+#define DCORE0_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_RTR3_MSTR_IF_CORE_LBW_BASE 0x415AD80ull
+#define DCORE0_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_RTR3_MSTR_IF_SPECIAL_BASE 0x415AE80ull
+#define DCORE0_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR3_ADD_DEC_HBW_BASE 0x415B000ull
+#define DCORE0_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR3_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE0_RTR3_ADD_DEC_LBW_BASE 0x415B400ull
+#define DCORE0_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR3_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE0_RTR3_ADD_DEC_SPECIAL_BASE 0x415BE80ull
+#define DCORE0_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR3_BASE 0x415C000ull
+#define DCORE0_RTR3_MAX_OFFSET 0x1000
+#define DCORE0_RTR3_SECTION 0x3000
+#define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x415C300ull
+#define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR3_HBW_RD_RS_LL_STAT_BASE 0x415C340ull
+#define DCORE0_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x415C380ull
+#define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR3_HBW_WR_RS_LL_STAT_BASE 0x415C3C0ull
+#define DCORE0_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x415C400ull
+#define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR3_LBW_RD_RS_LL_STAT_BASE 0x415C440ull
+#define DCORE0_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x415C480ull
+#define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR3_LBW_WR_RS_LL_STAT_BASE 0x415C4C0ull
+#define DCORE0_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR3_HBW_MFIFO_BASE 0x415C500ull
+#define DCORE0_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_HBW_MFIFO_SECTION 0x4000
+#define DCORE0_RTR3_E2E_RD_LL_STAT_BASE 0x415C540ull
+#define DCORE0_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR3_E2E_WR_LL_STAT_BASE 0x415C580ull
+#define DCORE0_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE0_RTR3_RTR_HBW_XACT_STAT_BASE 0x415C600ull
+#define DCORE0_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR3_RTR_LBW_XACT_STAT_BASE 0x415C680ull
+#define DCORE0_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR3_RTR_E2E_XACT_STAT_BASE 0x415C700ull
+#define DCORE0_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE0_RTR3_SPECIAL_BASE 0x415CE80ull
+#define DCORE0_RTR3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR3_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR3_DBG_ADDR_BASE 0x415D000ull
+#define DCORE0_RTR3_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR3_DBG_ADDR_SECTION 0xE800
+#define DCORE0_RTR3_DBG_ADDR_SPECIAL_BASE 0x415DE80ull
+#define DCORE0_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE0_RTR4_CTRL_BASE 0x4160000ull
+#define DCORE0_RTR4_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR4_CTRL_SECTION 0xE800
+#define DCORE0_RTR4_CTRL_SPECIAL_BASE 0x4160E80ull
+#define DCORE0_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR4_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR4_H3_BASE 0x4161000ull
+#define DCORE0_RTR4_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR4_H3_SECTION 0xE800
+#define DCORE0_RTR4_H3_SPECIAL_BASE 0x4161E80ull
+#define DCORE0_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR4_H3_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4162000ull
+#define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4162200ull
+#define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4162400ull
+#define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4162600ull
+#define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4162800ull
+#define DCORE0_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_RTR4_MSTR_IF_AXUSER_BASE 0x4162A80ull
+#define DCORE0_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR4_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_RTR4_MSTR_IF_DBG_HBW_BASE 0x4162B00ull
+#define DCORE0_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_RTR4_MSTR_IF_DBG_LBW_BASE 0x4162B80ull
+#define DCORE0_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_RTR4_MSTR_IF_CORE_HBW_BASE 0x4162C00ull
+#define DCORE0_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_RTR4_MSTR_IF_CORE_LBW_BASE 0x4162D80ull
+#define DCORE0_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_RTR4_MSTR_IF_SPECIAL_BASE 0x4162E80ull
+#define DCORE0_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR4_ADD_DEC_HBW_BASE 0x4163000ull
+#define DCORE0_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR4_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE0_RTR4_ADD_DEC_LBW_BASE 0x4163400ull
+#define DCORE0_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR4_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE0_RTR4_ADD_DEC_SPECIAL_BASE 0x4163E80ull
+#define DCORE0_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR4_BASE 0x4164000ull
+#define DCORE0_RTR4_MAX_OFFSET 0x1000
+#define DCORE0_RTR4_SECTION 0x3000
+#define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4164300ull
+#define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4164340ull
+#define DCORE0_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4164380ull
+#define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR4_HBW_WR_RS_LL_STAT_BASE 0x41643C0ull
+#define DCORE0_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4164400ull
+#define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4164440ull
+#define DCORE0_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4164480ull
+#define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR4_LBW_WR_RS_LL_STAT_BASE 0x41644C0ull
+#define DCORE0_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR4_HBW_MFIFO_BASE 0x4164500ull
+#define DCORE0_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_HBW_MFIFO_SECTION 0x4000
+#define DCORE0_RTR4_E2E_RD_LL_STAT_BASE 0x4164540ull
+#define DCORE0_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR4_E2E_WR_LL_STAT_BASE 0x4164580ull
+#define DCORE0_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE0_RTR4_RTR_HBW_XACT_STAT_BASE 0x4164600ull
+#define DCORE0_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR4_RTR_LBW_XACT_STAT_BASE 0x4164680ull
+#define DCORE0_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR4_RTR_E2E_XACT_STAT_BASE 0x4164700ull
+#define DCORE0_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE0_RTR4_SPECIAL_BASE 0x4164E80ull
+#define DCORE0_RTR4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR4_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR4_DBG_ADDR_BASE 0x4165000ull
+#define DCORE0_RTR4_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR4_DBG_ADDR_SECTION 0xE800
+#define DCORE0_RTR4_DBG_ADDR_SPECIAL_BASE 0x4165E80ull
+#define DCORE0_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE0_RTR5_CTRL_BASE 0x4168000ull
+#define DCORE0_RTR5_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR5_CTRL_SECTION 0xE800
+#define DCORE0_RTR5_CTRL_SPECIAL_BASE 0x4168E80ull
+#define DCORE0_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR5_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR5_H3_BASE 0x4169000ull
+#define DCORE0_RTR5_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR5_H3_SECTION 0xE800
+#define DCORE0_RTR5_H3_SPECIAL_BASE 0x4169E80ull
+#define DCORE0_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR5_H3_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x416A000ull
+#define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x416A200ull
+#define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x416A400ull
+#define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x416A600ull
+#define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_RTR5_MSTR_IF_E2E_CRDT_BASE 0x416A800ull
+#define DCORE0_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_RTR5_MSTR_IF_AXUSER_BASE 0x416AA80ull
+#define DCORE0_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR5_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_RTR5_MSTR_IF_DBG_HBW_BASE 0x416AB00ull
+#define DCORE0_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_RTR5_MSTR_IF_DBG_LBW_BASE 0x416AB80ull
+#define DCORE0_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_RTR5_MSTR_IF_CORE_HBW_BASE 0x416AC00ull
+#define DCORE0_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_RTR5_MSTR_IF_CORE_LBW_BASE 0x416AD80ull
+#define DCORE0_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_RTR5_MSTR_IF_SPECIAL_BASE 0x416AE80ull
+#define DCORE0_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR5_ADD_DEC_HBW_BASE 0x416B000ull
+#define DCORE0_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR5_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE0_RTR5_ADD_DEC_LBW_BASE 0x416B400ull
+#define DCORE0_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR5_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE0_RTR5_ADD_DEC_SPECIAL_BASE 0x416BE80ull
+#define DCORE0_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR5_BASE 0x416C000ull
+#define DCORE0_RTR5_MAX_OFFSET 0x1000
+#define DCORE0_RTR5_SECTION 0x3000
+#define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x416C300ull
+#define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR5_HBW_RD_RS_LL_STAT_BASE 0x416C340ull
+#define DCORE0_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x416C380ull
+#define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR5_HBW_WR_RS_LL_STAT_BASE 0x416C3C0ull
+#define DCORE0_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x416C400ull
+#define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR5_LBW_RD_RS_LL_STAT_BASE 0x416C440ull
+#define DCORE0_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x416C480ull
+#define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR5_LBW_WR_RS_LL_STAT_BASE 0x416C4C0ull
+#define DCORE0_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR5_HBW_MFIFO_BASE 0x416C500ull
+#define DCORE0_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_HBW_MFIFO_SECTION 0x4000
+#define DCORE0_RTR5_E2E_RD_LL_STAT_BASE 0x416C540ull
+#define DCORE0_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR5_E2E_WR_LL_STAT_BASE 0x416C580ull
+#define DCORE0_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE0_RTR5_RTR_HBW_XACT_STAT_BASE 0x416C600ull
+#define DCORE0_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR5_RTR_LBW_XACT_STAT_BASE 0x416C680ull
+#define DCORE0_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR5_RTR_E2E_XACT_STAT_BASE 0x416C700ull
+#define DCORE0_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE0_RTR5_SPECIAL_BASE 0x416CE80ull
+#define DCORE0_RTR5_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR5_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR5_DBG_ADDR_BASE 0x416D000ull
+#define DCORE0_RTR5_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR5_DBG_ADDR_SECTION 0xE800
+#define DCORE0_RTR5_DBG_ADDR_SPECIAL_BASE 0x416DE80ull
+#define DCORE0_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE0_RTR6_CTRL_BASE 0x4170000ull
+#define DCORE0_RTR6_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR6_CTRL_SECTION 0xE800
+#define DCORE0_RTR6_CTRL_SPECIAL_BASE 0x4170E80ull
+#define DCORE0_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR6_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR6_H3_BASE 0x4171000ull
+#define DCORE0_RTR6_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR6_H3_SECTION 0xE800
+#define DCORE0_RTR6_H3_SPECIAL_BASE 0x4171E80ull
+#define DCORE0_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR6_H3_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4172000ull
+#define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4172200ull
+#define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4172400ull
+#define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4172600ull
+#define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4172800ull
+#define DCORE0_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_RTR6_MSTR_IF_AXUSER_BASE 0x4172A80ull
+#define DCORE0_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR6_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_RTR6_MSTR_IF_DBG_HBW_BASE 0x4172B00ull
+#define DCORE0_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_RTR6_MSTR_IF_DBG_LBW_BASE 0x4172B80ull
+#define DCORE0_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_RTR6_MSTR_IF_CORE_HBW_BASE 0x4172C00ull
+#define DCORE0_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_RTR6_MSTR_IF_CORE_LBW_BASE 0x4172D80ull
+#define DCORE0_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_RTR6_MSTR_IF_SPECIAL_BASE 0x4172E80ull
+#define DCORE0_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR6_ADD_DEC_HBW_BASE 0x4173000ull
+#define DCORE0_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR6_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE0_RTR6_ADD_DEC_LBW_BASE 0x4173400ull
+#define DCORE0_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR6_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE0_RTR6_ADD_DEC_SPECIAL_BASE 0x4173E80ull
+#define DCORE0_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR6_BASE 0x4174000ull
+#define DCORE0_RTR6_MAX_OFFSET 0x1000
+#define DCORE0_RTR6_SECTION 0x3000
+#define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4174300ull
+#define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4174340ull
+#define DCORE0_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4174380ull
+#define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR6_HBW_WR_RS_LL_STAT_BASE 0x41743C0ull
+#define DCORE0_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4174400ull
+#define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4174440ull
+#define DCORE0_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4174480ull
+#define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR6_LBW_WR_RS_LL_STAT_BASE 0x41744C0ull
+#define DCORE0_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR6_HBW_MFIFO_BASE 0x4174500ull
+#define DCORE0_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_HBW_MFIFO_SECTION 0x4000
+#define DCORE0_RTR6_E2E_RD_LL_STAT_BASE 0x4174540ull
+#define DCORE0_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR6_E2E_WR_LL_STAT_BASE 0x4174580ull
+#define DCORE0_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE0_RTR6_RTR_HBW_XACT_STAT_BASE 0x4174600ull
+#define DCORE0_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR6_RTR_LBW_XACT_STAT_BASE 0x4174680ull
+#define DCORE0_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR6_RTR_E2E_XACT_STAT_BASE 0x4174700ull
+#define DCORE0_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE0_RTR6_SPECIAL_BASE 0x4174E80ull
+#define DCORE0_RTR6_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR6_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR6_DBG_ADDR_BASE 0x4175000ull
+#define DCORE0_RTR6_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR6_DBG_ADDR_SECTION 0xE800
+#define DCORE0_RTR6_DBG_ADDR_SPECIAL_BASE 0x4175E80ull
+#define DCORE0_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE0_RTR7_CTRL_BASE 0x4178000ull
+#define DCORE0_RTR7_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR7_CTRL_SECTION 0xE800
+#define DCORE0_RTR7_CTRL_SPECIAL_BASE 0x4178E80ull
+#define DCORE0_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR7_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR7_H3_BASE 0x4179000ull
+#define DCORE0_RTR7_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR7_H3_SECTION 0xE800
+#define DCORE0_RTR7_H3_SPECIAL_BASE 0x4179E80ull
+#define DCORE0_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR7_H3_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x417A000ull
+#define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x417A200ull
+#define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x417A400ull
+#define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x417A600ull
+#define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_RTR7_MSTR_IF_E2E_CRDT_BASE 0x417A800ull
+#define DCORE0_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_RTR7_MSTR_IF_AXUSER_BASE 0x417AA80ull
+#define DCORE0_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR7_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_RTR7_MSTR_IF_DBG_HBW_BASE 0x417AB00ull
+#define DCORE0_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_RTR7_MSTR_IF_DBG_LBW_BASE 0x417AB80ull
+#define DCORE0_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_RTR7_MSTR_IF_CORE_HBW_BASE 0x417AC00ull
+#define DCORE0_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_RTR7_MSTR_IF_CORE_LBW_BASE 0x417AD80ull
+#define DCORE0_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_RTR7_MSTR_IF_SPECIAL_BASE 0x417AE80ull
+#define DCORE0_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR7_ADD_DEC_HBW_BASE 0x417B000ull
+#define DCORE0_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR7_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE0_RTR7_ADD_DEC_LBW_BASE 0x417B400ull
+#define DCORE0_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR7_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE0_RTR7_ADD_DEC_SPECIAL_BASE 0x417BE80ull
+#define DCORE0_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR7_BASE 0x417C000ull
+#define DCORE0_RTR7_MAX_OFFSET 0x1000
+#define DCORE0_RTR7_SECTION 0x3000
+#define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x417C300ull
+#define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR7_HBW_RD_RS_LL_STAT_BASE 0x417C340ull
+#define DCORE0_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x417C380ull
+#define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR7_HBW_WR_RS_LL_STAT_BASE 0x417C3C0ull
+#define DCORE0_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x417C400ull
+#define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR7_LBW_RD_RS_LL_STAT_BASE 0x417C440ull
+#define DCORE0_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x417C480ull
+#define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR7_LBW_WR_RS_LL_STAT_BASE 0x417C4C0ull
+#define DCORE0_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR7_HBW_MFIFO_BASE 0x417C500ull
+#define DCORE0_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_HBW_MFIFO_SECTION 0x4000
+#define DCORE0_RTR7_E2E_RD_LL_STAT_BASE 0x417C540ull
+#define DCORE0_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE0_RTR7_E2E_WR_LL_STAT_BASE 0x417C580ull
+#define DCORE0_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE0_RTR7_RTR_HBW_XACT_STAT_BASE 0x417C600ull
+#define DCORE0_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR7_RTR_LBW_XACT_STAT_BASE 0x417C680ull
+#define DCORE0_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE0_RTR7_RTR_E2E_XACT_STAT_BASE 0x417C700ull
+#define DCORE0_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE0_RTR7_SPECIAL_BASE 0x417CE80ull
+#define DCORE0_RTR7_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR7_SPECIAL_SECTION 0x1800
+#define DCORE0_RTR7_DBG_ADDR_BASE 0x417D000ull
+#define DCORE0_RTR7_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR7_DBG_ADDR_SECTION 0xE800
+#define DCORE0_RTR7_DBG_ADDR_SPECIAL_BASE 0x417DE80ull
+#define DCORE0_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE0_SRAM0_BANK_BASE 0x4180000ull
+#define DCORE0_SRAM0_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM0_BANK_SECTION 0xE800
+#define DCORE0_SRAM0_BANK_SPECIAL_BASE 0x4180E80ull
+#define DCORE0_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM0_BANK_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM0_RTR_BASE 0x4181000ull
+#define DCORE0_SRAM0_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM0_RTR_SECTION 0xE800
+#define DCORE0_SRAM0_RTR_SPECIAL_BASE 0x4181E80ull
+#define DCORE0_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM0_RTR_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4182000ull
+#define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4182100ull
+#define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4182200ull
+#define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4182300ull
+#define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4182400ull
+#define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4182500ull
+#define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4182600ull
+#define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4182700ull
+#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4182780ull
+#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4182800ull
+#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4182880ull
+#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4182900ull
+#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4182980ull
+#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4182A00ull
+#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4182A80ull
+#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE0_SRAM0_DBG_CNT_SPECIAL_BASE 0x4182E80ull
+#define DCORE0_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE0_SRAM1_BANK_BASE 0x4188000ull
+#define DCORE0_SRAM1_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM1_BANK_SECTION 0xE800
+#define DCORE0_SRAM1_BANK_SPECIAL_BASE 0x4188E80ull
+#define DCORE0_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM1_BANK_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM1_RTR_BASE 0x4189000ull
+#define DCORE0_SRAM1_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM1_RTR_SECTION 0xE800
+#define DCORE0_SRAM1_RTR_SPECIAL_BASE 0x4189E80ull
+#define DCORE0_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM1_RTR_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x418A000ull
+#define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x418A100ull
+#define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x418A200ull
+#define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x418A300ull
+#define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x418A400ull
+#define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x418A500ull
+#define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x418A600ull
+#define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x418A700ull
+#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x418A780ull
+#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x418A800ull
+#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x418A880ull
+#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x418A900ull
+#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x418A980ull
+#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x418AA00ull
+#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x418AA80ull
+#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE0_SRAM1_DBG_CNT_SPECIAL_BASE 0x418AE80ull
+#define DCORE0_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE0_SRAM2_BANK_BASE 0x4190000ull
+#define DCORE0_SRAM2_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM2_BANK_SECTION 0xE800
+#define DCORE0_SRAM2_BANK_SPECIAL_BASE 0x4190E80ull
+#define DCORE0_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM2_BANK_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM2_RTR_BASE 0x4191000ull
+#define DCORE0_SRAM2_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM2_RTR_SECTION 0xE800
+#define DCORE0_SRAM2_RTR_SPECIAL_BASE 0x4191E80ull
+#define DCORE0_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM2_RTR_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4192000ull
+#define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4192100ull
+#define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4192200ull
+#define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4192300ull
+#define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4192400ull
+#define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4192500ull
+#define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4192600ull
+#define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4192700ull
+#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4192780ull
+#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4192800ull
+#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4192880ull
+#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4192900ull
+#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4192980ull
+#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4192A00ull
+#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4192A80ull
+#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE0_SRAM2_DBG_CNT_SPECIAL_BASE 0x4192E80ull
+#define DCORE0_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE0_SRAM3_BANK_BASE 0x4198000ull
+#define DCORE0_SRAM3_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM3_BANK_SECTION 0xE800
+#define DCORE0_SRAM3_BANK_SPECIAL_BASE 0x4198E80ull
+#define DCORE0_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM3_BANK_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM3_RTR_BASE 0x4199000ull
+#define DCORE0_SRAM3_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM3_RTR_SECTION 0xE800
+#define DCORE0_SRAM3_RTR_SPECIAL_BASE 0x4199E80ull
+#define DCORE0_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM3_RTR_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x419A000ull
+#define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x419A100ull
+#define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x419A200ull
+#define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x419A300ull
+#define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x419A400ull
+#define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x419A500ull
+#define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x419A600ull
+#define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x419A700ull
+#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x419A780ull
+#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x419A800ull
+#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x419A880ull
+#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x419A900ull
+#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x419A980ull
+#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x419AA00ull
+#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x419AA80ull
+#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE0_SRAM3_DBG_CNT_SPECIAL_BASE 0x419AE80ull
+#define DCORE0_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE0_SRAM4_BANK_BASE 0x41A0000ull
+#define DCORE0_SRAM4_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM4_BANK_SECTION 0xE800
+#define DCORE0_SRAM4_BANK_SPECIAL_BASE 0x41A0E80ull
+#define DCORE0_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM4_BANK_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM4_RTR_BASE 0x41A1000ull
+#define DCORE0_SRAM4_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM4_RTR_SECTION 0xE800
+#define DCORE0_SRAM4_RTR_SPECIAL_BASE 0x41A1E80ull
+#define DCORE0_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM4_RTR_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41A2000ull
+#define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41A2100ull
+#define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41A2200ull
+#define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41A2300ull
+#define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41A2400ull
+#define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41A2500ull
+#define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41A2600ull
+#define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41A2700ull
+#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41A2780ull
+#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41A2800ull
+#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41A2880ull
+#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41A2900ull
+#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41A2980ull
+#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41A2A00ull
+#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41A2A80ull
+#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE0_SRAM4_DBG_CNT_SPECIAL_BASE 0x41A2E80ull
+#define DCORE0_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE0_SRAM5_BANK_BASE 0x41A8000ull
+#define DCORE0_SRAM5_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM5_BANK_SECTION 0xE800
+#define DCORE0_SRAM5_BANK_SPECIAL_BASE 0x41A8E80ull
+#define DCORE0_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM5_BANK_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM5_RTR_BASE 0x41A9000ull
+#define DCORE0_SRAM5_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM5_RTR_SECTION 0xE800
+#define DCORE0_SRAM5_RTR_SPECIAL_BASE 0x41A9E80ull
+#define DCORE0_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM5_RTR_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41AA000ull
+#define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41AA100ull
+#define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41AA200ull
+#define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41AA300ull
+#define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41AA400ull
+#define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41AA500ull
+#define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41AA600ull
+#define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41AA700ull
+#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41AA780ull
+#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41AA800ull
+#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41AA880ull
+#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41AA900ull
+#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41AA980ull
+#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41AAA00ull
+#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41AAA80ull
+#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE0_SRAM5_DBG_CNT_SPECIAL_BASE 0x41AAE80ull
+#define DCORE0_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE0_SRAM6_BANK_BASE 0x41B0000ull
+#define DCORE0_SRAM6_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM6_BANK_SECTION 0xE800
+#define DCORE0_SRAM6_BANK_SPECIAL_BASE 0x41B0E80ull
+#define DCORE0_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM6_BANK_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM6_RTR_BASE 0x41B1000ull
+#define DCORE0_SRAM6_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM6_RTR_SECTION 0xE800
+#define DCORE0_SRAM6_RTR_SPECIAL_BASE 0x41B1E80ull
+#define DCORE0_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM6_RTR_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41B2000ull
+#define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41B2100ull
+#define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41B2200ull
+#define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41B2300ull
+#define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41B2400ull
+#define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41B2500ull
+#define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41B2600ull
+#define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41B2700ull
+#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41B2780ull
+#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41B2800ull
+#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41B2880ull
+#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41B2900ull
+#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41B2980ull
+#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41B2A00ull
+#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41B2A80ull
+#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE0_SRAM6_DBG_CNT_SPECIAL_BASE 0x41B2E80ull
+#define DCORE0_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE0_SRAM7_BANK_BASE 0x41B8000ull
+#define DCORE0_SRAM7_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM7_BANK_SECTION 0xE800
+#define DCORE0_SRAM7_BANK_SPECIAL_BASE 0x41B8E80ull
+#define DCORE0_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM7_BANK_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM7_RTR_BASE 0x41B9000ull
+#define DCORE0_SRAM7_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM7_RTR_SECTION 0xE800
+#define DCORE0_SRAM7_RTR_SPECIAL_BASE 0x41B9E80ull
+#define DCORE0_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM7_RTR_SPECIAL_SECTION 0x1800
+#define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41BA000ull
+#define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41BA100ull
+#define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41BA200ull
+#define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41BA300ull
+#define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41BA400ull
+#define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41BA500ull
+#define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41BA600ull
+#define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41BA700ull
+#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41BA780ull
+#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41BA800ull
+#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41BA880ull
+#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41BA900ull
+#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41BA980ull
+#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41BAA00ull
+#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41BAA80ull
+#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE0_SRAM7_DBG_CNT_SPECIAL_BASE 0x41BAE80ull
+#define DCORE0_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE0_EDMA0_QM_DCCM_BASE 0x41C0000ull
+#define DCORE0_EDMA0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_EDMA0_QM_DCCM_SECTION 0x8000
+#define DCORE0_EDMA0_QM_ARC_AUX_BASE 0x41C8000ull
+#define DCORE0_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_QM_ARC_AUX_SECTION 0xE800
+#define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x41C8E80ull
+#define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE0_EDMA0_QM_BASE 0x41CA000ull
+#define DCORE0_EDMA0_QM_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_QM_SECTION 0x9000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x41CA900ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x41CA908ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x41CA910ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x41CA918ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x41CA920ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x41CA928ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x41CA930ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x41CA938ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x41CA940ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x41CA948ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x41CA950ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x41CA958ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x41CA960ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x41CA968ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x41CA970ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x41CA978ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_EDMA0_QM_AXUSER_SECURED_BASE 0x41CAB00ull
+#define DCORE0_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_EDMA0_QM_AXUSER_NONSECURED_BASE 0x41CAB80ull
+#define DCORE0_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_EDMA0_QM_DBG_HBW_BASE 0x41CAC00ull
+#define DCORE0_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA0_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_EDMA0_QM_DBG_LBW_BASE 0x41CAC80ull
+#define DCORE0_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA0_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_EDMA0_QM_CGM_BASE 0x41CAD80ull
+#define DCORE0_EDMA0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_EDMA0_QM_CGM_SECTION 0x1000
+#define DCORE0_EDMA0_QM_SPECIAL_BASE 0x41CAE80ull
+#define DCORE0_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA0_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_EDMA0_CORE_BASE 0x41CB000ull
+#define DCORE0_EDMA0_CORE_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_CORE_SECTION 0x8000
+#define DCORE0_EDMA0_CORE_CTX_AXUSER_BASE 0x41CB800ull
+#define DCORE0_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000
+#define DCORE0_EDMA0_CORE_CTX_BASE 0x41CB860ull
+#define DCORE0_EDMA0_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE0_EDMA0_CORE_CTX_SECTION 0x5A00
+#define DCORE0_EDMA0_CORE_KDMA_CGM_BASE 0x41CBE00ull
+#define DCORE0_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE0_EDMA0_CORE_KDMA_CGM_SECTION 0x8000
+#define DCORE0_EDMA0_CORE_SPECIAL_BASE 0x41CBE80ull
+#define DCORE0_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA0_CORE_SPECIAL_SECTION 0x1800
+#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x41CC000ull
+#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x41CC200ull
+#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x41CC400ull
+#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x41CC600ull
+#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x41CC800ull
+#define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_EDMA0_MSTR_IF_AXUSER_BASE 0x41CCA80ull
+#define DCORE0_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_EDMA0_MSTR_IF_DBG_HBW_BASE 0x41CCB00ull
+#define DCORE0_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_EDMA0_MSTR_IF_DBG_LBW_BASE 0x41CCB80ull
+#define DCORE0_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_EDMA0_MSTR_IF_CORE_HBW_BASE 0x41CCC00ull
+#define DCORE0_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_EDMA0_MSTR_IF_CORE_LBW_BASE 0x41CCD80ull
+#define DCORE0_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_EDMA0_MSTR_IF_SPECIAL_BASE 0x41CCE80ull
+#define DCORE0_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE0_EDMA1_QM_DCCM_BASE 0x41D0000ull
+#define DCORE0_EDMA1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_EDMA1_QM_DCCM_SECTION 0x8000
+#define DCORE0_EDMA1_QM_ARC_AUX_BASE 0x41D8000ull
+#define DCORE0_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_QM_ARC_AUX_SECTION 0xE800
+#define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x41D8E80ull
+#define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE0_EDMA1_QM_BASE 0x41DA000ull
+#define DCORE0_EDMA1_QM_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_QM_SECTION 0x9000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x41DA900ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x41DA908ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x41DA910ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x41DA918ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x41DA920ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x41DA928ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x41DA930ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x41DA938ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x41DA940ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x41DA948ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x41DA950ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x41DA958ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x41DA960ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x41DA968ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x41DA970ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x41DA978ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE0_EDMA1_QM_AXUSER_SECURED_BASE 0x41DAB00ull
+#define DCORE0_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE0_EDMA1_QM_AXUSER_NONSECURED_BASE 0x41DAB80ull
+#define DCORE0_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE0_EDMA1_QM_DBG_HBW_BASE 0x41DAC00ull
+#define DCORE0_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA1_QM_DBG_HBW_SECTION 0x8000
+#define DCORE0_EDMA1_QM_DBG_LBW_BASE 0x41DAC80ull
+#define DCORE0_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA1_QM_DBG_LBW_SECTION 0x1000
+#define DCORE0_EDMA1_QM_CGM_BASE 0x41DAD80ull
+#define DCORE0_EDMA1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_EDMA1_QM_CGM_SECTION 0x1000
+#define DCORE0_EDMA1_QM_SPECIAL_BASE 0x41DAE80ull
+#define DCORE0_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA1_QM_SPECIAL_SECTION 0x1800
+#define DCORE0_EDMA1_CORE_BASE 0x41DB000ull
+#define DCORE0_EDMA1_CORE_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_CORE_SECTION 0x8000
+#define DCORE0_EDMA1_CORE_CTX_AXUSER_BASE 0x41DB800ull
+#define DCORE0_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000
+#define DCORE0_EDMA1_CORE_CTX_BASE 0x41DB860ull
+#define DCORE0_EDMA1_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE0_EDMA1_CORE_CTX_SECTION 0x5A00
+#define DCORE0_EDMA1_CORE_KDMA_CGM_BASE 0x41DBE00ull
+#define DCORE0_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE0_EDMA1_CORE_KDMA_CGM_SECTION 0x8000
+#define DCORE0_EDMA1_CORE_SPECIAL_BASE 0x41DBE80ull
+#define DCORE0_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA1_CORE_SPECIAL_SECTION 0x1800
+#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x41DC000ull
+#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x41DC200ull
+#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x41DC400ull
+#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x41DC600ull
+#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x41DC800ull
+#define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_EDMA1_MSTR_IF_AXUSER_BASE 0x41DCA80ull
+#define DCORE0_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_EDMA1_MSTR_IF_DBG_HBW_BASE 0x41DCB00ull
+#define DCORE0_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_EDMA1_MSTR_IF_DBG_LBW_BASE 0x41DCB80ull
+#define DCORE0_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_EDMA1_MSTR_IF_CORE_HBW_BASE 0x41DCC00ull
+#define DCORE0_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_EDMA1_MSTR_IF_CORE_LBW_BASE 0x41DCD80ull
+#define DCORE0_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_EDMA1_MSTR_IF_SPECIAL_BASE 0x41DCE80ull
+#define DCORE0_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE0_DEC0_CMD_BASE 0x41E0000ull
+#define DCORE0_DEC0_CMD_MAX_OFFSET 0x1100
+#define DCORE0_DEC0_CMD_SECTION 0x1000
+#define DCORE0_DEC0_VSI_BASE 0x41E1000ull
+#define DCORE0_DEC0_VSI_MAX_OFFSET 0x6FC0
+#define DCORE0_DEC0_VSI_SECTION 0x1000
+#define DCORE0_DEC0_L2C_BASE 0x41E2000ull
+#define DCORE0_DEC0_L2C_MAX_OFFSET 0x39C0
+#define DCORE0_DEC0_L2C_SECTION 0x1000
+#define DCORE0_VDEC0_BRDG_CTRL_BASE 0x41E3000ull
+#define DCORE0_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_BRDG_CTRL_SECTION 0x8000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x41E3800ull
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x41E3900ull
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x41E3A00ull
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x41E3B00ull
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x41E3C00ull
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x41E3E80ull
+#define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE0_VDEC0_CTRL_BASE 0x41E4000ull
+#define DCORE0_VDEC0_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_CTRL_SECTION 0xE800
+#define DCORE0_VDEC0_CTRL_SPECIAL_BASE 0x41E4E80ull
+#define DCORE0_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_VDEC0_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x41E5000ull
+#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x41E5200ull
+#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x41E5400ull
+#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x41E5600ull
+#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x41E5800ull
+#define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_VDEC0_MSTR_IF_AXUSER_BASE 0x41E5A80ull
+#define DCORE0_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_VDEC0_MSTR_IF_DBG_HBW_BASE 0x41E5B00ull
+#define DCORE0_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_VDEC0_MSTR_IF_DBG_LBW_BASE 0x41E5B80ull
+#define DCORE0_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_VDEC0_MSTR_IF_CORE_HBW_BASE 0x41E5C00ull
+#define DCORE0_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_VDEC0_MSTR_IF_CORE_LBW_BASE 0x41E5D80ull
+#define DCORE0_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_VDEC0_MSTR_IF_SPECIAL_BASE 0x41E5E80ull
+#define DCORE0_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
+#define DCORE0_DEC1_CMD_BASE 0x41F0000ull
+#define DCORE0_DEC1_CMD_MAX_OFFSET 0x1100
+#define DCORE0_DEC1_CMD_SECTION 0x1000
+#define DCORE0_DEC1_VSI_BASE 0x41F1000ull
+#define DCORE0_DEC1_VSI_MAX_OFFSET 0x6FC0
+#define DCORE0_DEC1_VSI_SECTION 0x1000
+#define DCORE0_DEC1_L2C_BASE 0x41F2000ull
+#define DCORE0_DEC1_L2C_MAX_OFFSET 0x39C0
+#define DCORE0_DEC1_L2C_SECTION 0x1000
+#define DCORE0_VDEC1_BRDG_CTRL_BASE 0x41F3000ull
+#define DCORE0_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_BRDG_CTRL_SECTION 0x8000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x41F3800ull
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x41F3900ull
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x41F3A00ull
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x41F3B00ull
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x41F3C00ull
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x41F3E80ull
+#define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE0_VDEC1_CTRL_BASE 0x41F4000ull
+#define DCORE0_VDEC1_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_CTRL_SECTION 0xE800
+#define DCORE0_VDEC1_CTRL_SPECIAL_BASE 0x41F4E80ull
+#define DCORE0_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_VDEC1_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x41F5000ull
+#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x41F5200ull
+#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x41F5400ull
+#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x41F5600ull
+#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x41F5800ull
+#define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE0_VDEC1_MSTR_IF_AXUSER_BASE 0x41F5A80ull
+#define DCORE0_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE0_VDEC1_MSTR_IF_DBG_HBW_BASE 0x41F5B00ull
+#define DCORE0_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE0_VDEC1_MSTR_IF_DBG_LBW_BASE 0x41F5B80ull
+#define DCORE0_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE0_VDEC1_MSTR_IF_CORE_HBW_BASE 0x41F5C00ull
+#define DCORE0_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE0_VDEC1_MSTR_IF_CORE_LBW_BASE 0x41F5D80ull
+#define DCORE0_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE0_VDEC1_MSTR_IF_SPECIAL_BASE 0x41F5E80ull
+#define DCORE0_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180
+#define DCORE1_TPC0_QM_DCCM_BASE 0x4200000ull
+#define DCORE1_TPC0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC0_QM_DCCM_SECTION 0x8000
+#define DCORE1_TPC0_QM_ARC_AUX_BASE 0x4208000ull
+#define DCORE1_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_QM_ARC_AUX_SECTION 0xE800
+#define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4208E80ull
+#define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE1_TPC0_QM_BASE 0x420A000ull
+#define DCORE1_TPC0_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_QM_SECTION 0x9000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x420A900ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x420A908ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x420A910ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x420A918ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x420A920ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x420A928ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x420A930ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x420A938ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x420A940ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x420A948ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x420A950ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x420A958ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x420A960ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x420A968ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x420A970ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x420A978ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_TPC0_QM_AXUSER_SECURED_BASE 0x420AB00ull
+#define DCORE1_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_TPC0_QM_AXUSER_NONSECURED_BASE 0x420AB80ull
+#define DCORE1_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_TPC0_QM_DBG_HBW_BASE 0x420AC00ull
+#define DCORE1_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC0_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC0_QM_DBG_LBW_BASE 0x420AC80ull
+#define DCORE1_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC0_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_TPC0_QM_CGM_BASE 0x420AD80ull
+#define DCORE1_TPC0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC0_QM_CGM_SECTION 0x1000
+#define DCORE1_TPC0_QM_SPECIAL_BASE 0x420AE80ull
+#define DCORE1_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x420B000ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC0_CFG_BASE 0x420B000ull
+#define DCORE1_TPC0_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_CFG_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x420B050ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x420B0A0ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x420B0F0ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x420B140ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x420B190ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x420B1E0ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x420B230ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x420B280ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x420B2D0ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x420B320ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x420B370ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x420B3C0ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x420B410ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x420B460ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x420B4B0ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x420B500ull
+#define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC0_CFG_KERNEL_BASE 0x420B508ull
+#define DCORE1_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC0_CFG_KERNEL_SECTION 0xD400
+#define DCORE1_TPC0_CFG_QM_TENSOR_0_BASE 0x420B5DCull
+#define DCORE1_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_1_BASE 0x420B62Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_2_BASE 0x420B67Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_3_BASE 0x420B6CCull
+#define DCORE1_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_4_BASE 0x420B71Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_5_BASE 0x420B76Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_6_BASE 0x420B7BCull
+#define DCORE1_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_7_BASE 0x420B80Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_8_BASE 0x420B85Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_9_BASE 0x420B8ACull
+#define DCORE1_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_10_BASE 0x420B8FCull
+#define DCORE1_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_11_BASE 0x420B94Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_12_BASE 0x420B99Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_13_BASE 0x420B9ECull
+#define DCORE1_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_14_BASE 0x420BA3Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_15_BASE 0x420BA8Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x420BADCull
+#define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC0_CFG_QM_BASE 0x420BAE4ull
+#define DCORE1_TPC0_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC0_CFG_QM_SECTION 0x31C0
+#define DCORE1_TPC0_CFG_AXUSER_BASE 0x420BE00ull
+#define DCORE1_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_AXUSER_SECTION 0x8000
+#define DCORE1_TPC0_CFG_SPECIAL_BASE 0x420BE80ull
+#define DCORE1_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x420C000ull
+#define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x420C200ull
+#define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x420C400ull
+#define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x420C600ull
+#define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_TPC0_MSTR_IF_E2E_CRDT_BASE 0x420C800ull
+#define DCORE1_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_TPC0_MSTR_IF_AXUSER_BASE 0x420CA80ull
+#define DCORE1_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_TPC0_MSTR_IF_DBG_HBW_BASE 0x420CB00ull
+#define DCORE1_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC0_MSTR_IF_DBG_LBW_BASE 0x420CB80ull
+#define DCORE1_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_TPC0_MSTR_IF_CORE_HBW_BASE 0x420CC00ull
+#define DCORE1_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_TPC0_MSTR_IF_CORE_LBW_BASE 0x420CD80ull
+#define DCORE1_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_TPC0_MSTR_IF_SPECIAL_BASE 0x420CE80ull
+#define DCORE1_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE1_TPC1_QM_DCCM_BASE 0x4210000ull
+#define DCORE1_TPC1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC1_QM_DCCM_SECTION 0x8000
+#define DCORE1_TPC1_QM_ARC_AUX_BASE 0x4218000ull
+#define DCORE1_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_QM_ARC_AUX_SECTION 0xE800
+#define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4218E80ull
+#define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE1_TPC1_QM_BASE 0x421A000ull
+#define DCORE1_TPC1_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_QM_SECTION 0x9000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x421A900ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x421A908ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x421A910ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x421A918ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x421A920ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x421A928ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x421A930ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x421A938ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x421A940ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x421A948ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x421A950ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x421A958ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x421A960ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x421A968ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x421A970ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x421A978ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_TPC1_QM_AXUSER_SECURED_BASE 0x421AB00ull
+#define DCORE1_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_TPC1_QM_AXUSER_NONSECURED_BASE 0x421AB80ull
+#define DCORE1_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_TPC1_QM_DBG_HBW_BASE 0x421AC00ull
+#define DCORE1_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC1_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC1_QM_DBG_LBW_BASE 0x421AC80ull
+#define DCORE1_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC1_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_TPC1_QM_CGM_BASE 0x421AD80ull
+#define DCORE1_TPC1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC1_QM_CGM_SECTION 0x1000
+#define DCORE1_TPC1_QM_SPECIAL_BASE 0x421AE80ull
+#define DCORE1_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x421B000ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC1_CFG_BASE 0x421B000ull
+#define DCORE1_TPC1_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_CFG_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x421B050ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x421B0A0ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x421B0F0ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x421B140ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x421B190ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x421B1E0ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x421B230ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x421B280ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x421B2D0ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x421B320ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x421B370ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x421B3C0ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x421B410ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x421B460ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x421B4B0ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x421B500ull
+#define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC1_CFG_KERNEL_BASE 0x421B508ull
+#define DCORE1_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC1_CFG_KERNEL_SECTION 0xD400
+#define DCORE1_TPC1_CFG_QM_TENSOR_0_BASE 0x421B5DCull
+#define DCORE1_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_1_BASE 0x421B62Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_2_BASE 0x421B67Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_3_BASE 0x421B6CCull
+#define DCORE1_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_4_BASE 0x421B71Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_5_BASE 0x421B76Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_6_BASE 0x421B7BCull
+#define DCORE1_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_7_BASE 0x421B80Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_8_BASE 0x421B85Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_9_BASE 0x421B8ACull
+#define DCORE1_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_10_BASE 0x421B8FCull
+#define DCORE1_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_11_BASE 0x421B94Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_12_BASE 0x421B99Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_13_BASE 0x421B9ECull
+#define DCORE1_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_14_BASE 0x421BA3Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_15_BASE 0x421BA8Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x421BADCull
+#define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC1_CFG_QM_BASE 0x421BAE4ull
+#define DCORE1_TPC1_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC1_CFG_QM_SECTION 0x31C0
+#define DCORE1_TPC1_CFG_AXUSER_BASE 0x421BE00ull
+#define DCORE1_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_AXUSER_SECTION 0x8000
+#define DCORE1_TPC1_CFG_SPECIAL_BASE 0x421BE80ull
+#define DCORE1_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x421C000ull
+#define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x421C200ull
+#define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x421C400ull
+#define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x421C600ull
+#define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_TPC1_MSTR_IF_E2E_CRDT_BASE 0x421C800ull
+#define DCORE1_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_TPC1_MSTR_IF_AXUSER_BASE 0x421CA80ull
+#define DCORE1_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_TPC1_MSTR_IF_DBG_HBW_BASE 0x421CB00ull
+#define DCORE1_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC1_MSTR_IF_DBG_LBW_BASE 0x421CB80ull
+#define DCORE1_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_TPC1_MSTR_IF_CORE_HBW_BASE 0x421CC00ull
+#define DCORE1_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_TPC1_MSTR_IF_CORE_LBW_BASE 0x421CD80ull
+#define DCORE1_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_TPC1_MSTR_IF_SPECIAL_BASE 0x421CE80ull
+#define DCORE1_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE1_TPC2_QM_DCCM_BASE 0x4220000ull
+#define DCORE1_TPC2_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC2_QM_DCCM_SECTION 0x8000
+#define DCORE1_TPC2_QM_ARC_AUX_BASE 0x4228000ull
+#define DCORE1_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_QM_ARC_AUX_SECTION 0xE800
+#define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4228E80ull
+#define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE1_TPC2_QM_BASE 0x422A000ull
+#define DCORE1_TPC2_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_QM_SECTION 0x9000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x422A900ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x422A908ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x422A910ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x422A918ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x422A920ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x422A928ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x422A930ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x422A938ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x422A940ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x422A948ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x422A950ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x422A958ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x422A960ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x422A968ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x422A970ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x422A978ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_TPC2_QM_AXUSER_SECURED_BASE 0x422AB00ull
+#define DCORE1_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_TPC2_QM_AXUSER_NONSECURED_BASE 0x422AB80ull
+#define DCORE1_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_TPC2_QM_DBG_HBW_BASE 0x422AC00ull
+#define DCORE1_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC2_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC2_QM_DBG_LBW_BASE 0x422AC80ull
+#define DCORE1_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC2_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_TPC2_QM_CGM_BASE 0x422AD80ull
+#define DCORE1_TPC2_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC2_QM_CGM_SECTION 0x1000
+#define DCORE1_TPC2_QM_SPECIAL_BASE 0x422AE80ull
+#define DCORE1_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x422B000ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC2_CFG_BASE 0x422B000ull
+#define DCORE1_TPC2_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_CFG_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x422B050ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x422B0A0ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x422B0F0ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x422B140ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x422B190ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x422B1E0ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x422B230ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x422B280ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x422B2D0ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x422B320ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x422B370ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x422B3C0ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x422B410ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x422B460ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x422B4B0ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x422B500ull
+#define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC2_CFG_KERNEL_BASE 0x422B508ull
+#define DCORE1_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC2_CFG_KERNEL_SECTION 0xD400
+#define DCORE1_TPC2_CFG_QM_TENSOR_0_BASE 0x422B5DCull
+#define DCORE1_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_1_BASE 0x422B62Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_2_BASE 0x422B67Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_3_BASE 0x422B6CCull
+#define DCORE1_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_4_BASE 0x422B71Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_5_BASE 0x422B76Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_6_BASE 0x422B7BCull
+#define DCORE1_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_7_BASE 0x422B80Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_8_BASE 0x422B85Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_9_BASE 0x422B8ACull
+#define DCORE1_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_10_BASE 0x422B8FCull
+#define DCORE1_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_11_BASE 0x422B94Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_12_BASE 0x422B99Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_13_BASE 0x422B9ECull
+#define DCORE1_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_14_BASE 0x422BA3Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_15_BASE 0x422BA8Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x422BADCull
+#define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC2_CFG_QM_BASE 0x422BAE4ull
+#define DCORE1_TPC2_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC2_CFG_QM_SECTION 0x31C0
+#define DCORE1_TPC2_CFG_AXUSER_BASE 0x422BE00ull
+#define DCORE1_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_AXUSER_SECTION 0x8000
+#define DCORE1_TPC2_CFG_SPECIAL_BASE 0x422BE80ull
+#define DCORE1_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x422C000ull
+#define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x422C200ull
+#define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x422C400ull
+#define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x422C600ull
+#define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_TPC2_MSTR_IF_E2E_CRDT_BASE 0x422C800ull
+#define DCORE1_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_TPC2_MSTR_IF_AXUSER_BASE 0x422CA80ull
+#define DCORE1_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_TPC2_MSTR_IF_DBG_HBW_BASE 0x422CB00ull
+#define DCORE1_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC2_MSTR_IF_DBG_LBW_BASE 0x422CB80ull
+#define DCORE1_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_TPC2_MSTR_IF_CORE_HBW_BASE 0x422CC00ull
+#define DCORE1_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_TPC2_MSTR_IF_CORE_LBW_BASE 0x422CD80ull
+#define DCORE1_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_TPC2_MSTR_IF_SPECIAL_BASE 0x422CE80ull
+#define DCORE1_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE1_TPC3_QM_DCCM_BASE 0x4230000ull
+#define DCORE1_TPC3_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC3_QM_DCCM_SECTION 0x8000
+#define DCORE1_TPC3_QM_ARC_AUX_BASE 0x4238000ull
+#define DCORE1_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_QM_ARC_AUX_SECTION 0xE800
+#define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4238E80ull
+#define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE1_TPC3_QM_BASE 0x423A000ull
+#define DCORE1_TPC3_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_QM_SECTION 0x9000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x423A900ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x423A908ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x423A910ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x423A918ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x423A920ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x423A928ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x423A930ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x423A938ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x423A940ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x423A948ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x423A950ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x423A958ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x423A960ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x423A968ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x423A970ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x423A978ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_TPC3_QM_AXUSER_SECURED_BASE 0x423AB00ull
+#define DCORE1_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_TPC3_QM_AXUSER_NONSECURED_BASE 0x423AB80ull
+#define DCORE1_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_TPC3_QM_DBG_HBW_BASE 0x423AC00ull
+#define DCORE1_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC3_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC3_QM_DBG_LBW_BASE 0x423AC80ull
+#define DCORE1_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC3_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_TPC3_QM_CGM_BASE 0x423AD80ull
+#define DCORE1_TPC3_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC3_QM_CGM_SECTION 0x1000
+#define DCORE1_TPC3_QM_SPECIAL_BASE 0x423AE80ull
+#define DCORE1_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x423B000ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC3_CFG_BASE 0x423B000ull
+#define DCORE1_TPC3_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_CFG_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x423B050ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x423B0A0ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x423B0F0ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x423B140ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x423B190ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x423B1E0ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x423B230ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x423B280ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x423B2D0ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x423B320ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x423B370ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x423B3C0ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x423B410ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x423B460ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x423B4B0ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x423B500ull
+#define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC3_CFG_KERNEL_BASE 0x423B508ull
+#define DCORE1_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC3_CFG_KERNEL_SECTION 0xD400
+#define DCORE1_TPC3_CFG_QM_TENSOR_0_BASE 0x423B5DCull
+#define DCORE1_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_1_BASE 0x423B62Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_2_BASE 0x423B67Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_3_BASE 0x423B6CCull
+#define DCORE1_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_4_BASE 0x423B71Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_5_BASE 0x423B76Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_6_BASE 0x423B7BCull
+#define DCORE1_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_7_BASE 0x423B80Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_8_BASE 0x423B85Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_9_BASE 0x423B8ACull
+#define DCORE1_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_10_BASE 0x423B8FCull
+#define DCORE1_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_11_BASE 0x423B94Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_12_BASE 0x423B99Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_13_BASE 0x423B9ECull
+#define DCORE1_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_14_BASE 0x423BA3Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_15_BASE 0x423BA8Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x423BADCull
+#define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC3_CFG_QM_BASE 0x423BAE4ull
+#define DCORE1_TPC3_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC3_CFG_QM_SECTION 0x31C0
+#define DCORE1_TPC3_CFG_AXUSER_BASE 0x423BE00ull
+#define DCORE1_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_AXUSER_SECTION 0x8000
+#define DCORE1_TPC3_CFG_SPECIAL_BASE 0x423BE80ull
+#define DCORE1_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x423C000ull
+#define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x423C200ull
+#define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x423C400ull
+#define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x423C600ull
+#define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_TPC3_MSTR_IF_E2E_CRDT_BASE 0x423C800ull
+#define DCORE1_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_TPC3_MSTR_IF_AXUSER_BASE 0x423CA80ull
+#define DCORE1_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_TPC3_MSTR_IF_DBG_HBW_BASE 0x423CB00ull
+#define DCORE1_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC3_MSTR_IF_DBG_LBW_BASE 0x423CB80ull
+#define DCORE1_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_TPC3_MSTR_IF_CORE_HBW_BASE 0x423CC00ull
+#define DCORE1_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_TPC3_MSTR_IF_CORE_LBW_BASE 0x423CD80ull
+#define DCORE1_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_TPC3_MSTR_IF_SPECIAL_BASE 0x423CE80ull
+#define DCORE1_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE1_TPC4_QM_DCCM_BASE 0x4240000ull
+#define DCORE1_TPC4_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC4_QM_DCCM_SECTION 0x8000
+#define DCORE1_TPC4_QM_ARC_AUX_BASE 0x4248000ull
+#define DCORE1_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_QM_ARC_AUX_SECTION 0xE800
+#define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4248E80ull
+#define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE1_TPC4_QM_BASE 0x424A000ull
+#define DCORE1_TPC4_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_QM_SECTION 0x9000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x424A900ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x424A908ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x424A910ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x424A918ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x424A920ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x424A928ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x424A930ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x424A938ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x424A940ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x424A948ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x424A950ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x424A958ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x424A960ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x424A968ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x424A970ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x424A978ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_TPC4_QM_AXUSER_SECURED_BASE 0x424AB00ull
+#define DCORE1_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_TPC4_QM_AXUSER_NONSECURED_BASE 0x424AB80ull
+#define DCORE1_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_TPC4_QM_DBG_HBW_BASE 0x424AC00ull
+#define DCORE1_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC4_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC4_QM_DBG_LBW_BASE 0x424AC80ull
+#define DCORE1_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC4_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_TPC4_QM_CGM_BASE 0x424AD80ull
+#define DCORE1_TPC4_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC4_QM_CGM_SECTION 0x1000
+#define DCORE1_TPC4_QM_SPECIAL_BASE 0x424AE80ull
+#define DCORE1_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x424B000ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC4_CFG_BASE 0x424B000ull
+#define DCORE1_TPC4_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_CFG_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x424B050ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x424B0A0ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x424B0F0ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x424B140ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x424B190ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x424B1E0ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x424B230ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x424B280ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x424B2D0ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x424B320ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x424B370ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x424B3C0ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x424B410ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x424B460ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x424B4B0ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x424B500ull
+#define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC4_CFG_KERNEL_BASE 0x424B508ull
+#define DCORE1_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC4_CFG_KERNEL_SECTION 0xD400
+#define DCORE1_TPC4_CFG_QM_TENSOR_0_BASE 0x424B5DCull
+#define DCORE1_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_1_BASE 0x424B62Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_2_BASE 0x424B67Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_3_BASE 0x424B6CCull
+#define DCORE1_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_4_BASE 0x424B71Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_5_BASE 0x424B76Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_6_BASE 0x424B7BCull
+#define DCORE1_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_7_BASE 0x424B80Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_8_BASE 0x424B85Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_9_BASE 0x424B8ACull
+#define DCORE1_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_10_BASE 0x424B8FCull
+#define DCORE1_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_11_BASE 0x424B94Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_12_BASE 0x424B99Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_13_BASE 0x424B9ECull
+#define DCORE1_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_14_BASE 0x424BA3Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_15_BASE 0x424BA8Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x424BADCull
+#define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC4_CFG_QM_BASE 0x424BAE4ull
+#define DCORE1_TPC4_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC4_CFG_QM_SECTION 0x31C0
+#define DCORE1_TPC4_CFG_AXUSER_BASE 0x424BE00ull
+#define DCORE1_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_AXUSER_SECTION 0x8000
+#define DCORE1_TPC4_CFG_SPECIAL_BASE 0x424BE80ull
+#define DCORE1_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x424C000ull
+#define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x424C200ull
+#define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x424C400ull
+#define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x424C600ull
+#define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_TPC4_MSTR_IF_E2E_CRDT_BASE 0x424C800ull
+#define DCORE1_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_TPC4_MSTR_IF_AXUSER_BASE 0x424CA80ull
+#define DCORE1_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_TPC4_MSTR_IF_DBG_HBW_BASE 0x424CB00ull
+#define DCORE1_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC4_MSTR_IF_DBG_LBW_BASE 0x424CB80ull
+#define DCORE1_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_TPC4_MSTR_IF_CORE_HBW_BASE 0x424CC00ull
+#define DCORE1_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_TPC4_MSTR_IF_CORE_LBW_BASE 0x424CD80ull
+#define DCORE1_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_TPC4_MSTR_IF_SPECIAL_BASE 0x424CE80ull
+#define DCORE1_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE1_TPC5_QM_DCCM_BASE 0x4250000ull
+#define DCORE1_TPC5_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC5_QM_DCCM_SECTION 0x8000
+#define DCORE1_TPC5_QM_ARC_AUX_BASE 0x4258000ull
+#define DCORE1_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_QM_ARC_AUX_SECTION 0xE800
+#define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4258E80ull
+#define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE1_TPC5_QM_BASE 0x425A000ull
+#define DCORE1_TPC5_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_QM_SECTION 0x9000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x425A900ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x425A908ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x425A910ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x425A918ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x425A920ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x425A928ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x425A930ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x425A938ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x425A940ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x425A948ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x425A950ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x425A958ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x425A960ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x425A968ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x425A970ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x425A978ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_TPC5_QM_AXUSER_SECURED_BASE 0x425AB00ull
+#define DCORE1_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_TPC5_QM_AXUSER_NONSECURED_BASE 0x425AB80ull
+#define DCORE1_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_TPC5_QM_DBG_HBW_BASE 0x425AC00ull
+#define DCORE1_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC5_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC5_QM_DBG_LBW_BASE 0x425AC80ull
+#define DCORE1_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC5_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_TPC5_QM_CGM_BASE 0x425AD80ull
+#define DCORE1_TPC5_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC5_QM_CGM_SECTION 0x1000
+#define DCORE1_TPC5_QM_SPECIAL_BASE 0x425AE80ull
+#define DCORE1_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x425B000ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC5_CFG_BASE 0x425B000ull
+#define DCORE1_TPC5_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_CFG_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x425B050ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x425B0A0ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x425B0F0ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x425B140ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x425B190ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x425B1E0ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x425B230ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x425B280ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x425B2D0ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x425B320ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x425B370ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x425B3C0ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x425B410ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x425B460ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x425B4B0ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x425B500ull
+#define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC5_CFG_KERNEL_BASE 0x425B508ull
+#define DCORE1_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC5_CFG_KERNEL_SECTION 0xD400
+#define DCORE1_TPC5_CFG_QM_TENSOR_0_BASE 0x425B5DCull
+#define DCORE1_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_1_BASE 0x425B62Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_2_BASE 0x425B67Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_3_BASE 0x425B6CCull
+#define DCORE1_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_4_BASE 0x425B71Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_5_BASE 0x425B76Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_6_BASE 0x425B7BCull
+#define DCORE1_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_7_BASE 0x425B80Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_8_BASE 0x425B85Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_9_BASE 0x425B8ACull
+#define DCORE1_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_10_BASE 0x425B8FCull
+#define DCORE1_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_11_BASE 0x425B94Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_12_BASE 0x425B99Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_13_BASE 0x425B9ECull
+#define DCORE1_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_14_BASE 0x425BA3Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_15_BASE 0x425BA8Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x425BADCull
+#define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE1_TPC5_CFG_QM_BASE 0x425BAE4ull
+#define DCORE1_TPC5_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC5_CFG_QM_SECTION 0x31C0
+#define DCORE1_TPC5_CFG_AXUSER_BASE 0x425BE00ull
+#define DCORE1_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_AXUSER_SECTION 0x8000
+#define DCORE1_TPC5_CFG_SPECIAL_BASE 0x425BE80ull
+#define DCORE1_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_CFG_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x425C000ull
+#define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x425C200ull
+#define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x425C400ull
+#define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x425C600ull
+#define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_TPC5_MSTR_IF_E2E_CRDT_BASE 0x425C800ull
+#define DCORE1_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_TPC5_MSTR_IF_AXUSER_BASE 0x425CA80ull
+#define DCORE1_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_TPC5_MSTR_IF_DBG_HBW_BASE 0x425CB00ull
+#define DCORE1_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_TPC5_MSTR_IF_DBG_LBW_BASE 0x425CB80ull
+#define DCORE1_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_TPC5_MSTR_IF_CORE_HBW_BASE 0x425CC00ull
+#define DCORE1_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_TPC5_MSTR_IF_CORE_LBW_BASE 0x425CD80ull
+#define DCORE1_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_TPC5_MSTR_IF_SPECIAL_BASE 0x425CE80ull
+#define DCORE1_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180
+#define DCORE1_HMMU0_MMU_BASE 0x4280000ull
+#define DCORE1_HMMU0_MMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_MMU_SECTION 0xE800
+#define DCORE1_HMMU0_MMU_SPECIAL_BASE 0x4280E80ull
+#define DCORE1_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU0_MMU_SPECIAL_SECTION 0x1800
+#define DCORE1_HMMU0_STLB_BASE 0x4281000ull
+#define DCORE1_HMMU0_STLB_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_STLB_SECTION 0xE800
+#define DCORE1_HMMU0_STLB_SPECIAL_BASE 0x4281E80ull
+#define DCORE1_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU0_STLB_SPECIAL_SECTION 0x1180
+#define DCORE1_HMMU0_SCRAMB_OUT_BASE 0x4283000ull
+#define DCORE1_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_SCRAMB_OUT_SECTION 0xE800
+#define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4283E80ull
+#define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4284000ull
+#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4284200ull
+#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4284400ull
+#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4284600ull
+#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4284800ull
+#define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_HMMU0_MSTR_IF_AXUSER_BASE 0x4284A80ull
+#define DCORE1_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4284B00ull
+#define DCORE1_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4284B80ull
+#define DCORE1_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4284C00ull
+#define DCORE1_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4284D80ull
+#define DCORE1_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_HMMU0_MSTR_IF_SPECIAL_BASE 0x4284E80ull
+#define DCORE1_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE1_HMMU1_MMU_BASE 0x4290000ull
+#define DCORE1_HMMU1_MMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_MMU_SECTION 0xE800
+#define DCORE1_HMMU1_MMU_SPECIAL_BASE 0x4290E80ull
+#define DCORE1_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU1_MMU_SPECIAL_SECTION 0x1800
+#define DCORE1_HMMU1_STLB_BASE 0x4291000ull
+#define DCORE1_HMMU1_STLB_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_STLB_SECTION 0xE800
+#define DCORE1_HMMU1_STLB_SPECIAL_BASE 0x4291E80ull
+#define DCORE1_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU1_STLB_SPECIAL_SECTION 0x1180
+#define DCORE1_HMMU1_SCRAMB_OUT_BASE 0x4293000ull
+#define DCORE1_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_SCRAMB_OUT_SECTION 0xE800
+#define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4293E80ull
+#define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4294000ull
+#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4294200ull
+#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4294400ull
+#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4294600ull
+#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4294800ull
+#define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_HMMU1_MSTR_IF_AXUSER_BASE 0x4294A80ull
+#define DCORE1_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4294B00ull
+#define DCORE1_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4294B80ull
+#define DCORE1_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4294C00ull
+#define DCORE1_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4294D80ull
+#define DCORE1_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_HMMU1_MSTR_IF_SPECIAL_BASE 0x4294E80ull
+#define DCORE1_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE1_HMMU2_MMU_BASE 0x42A0000ull
+#define DCORE1_HMMU2_MMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_MMU_SECTION 0xE800
+#define DCORE1_HMMU2_MMU_SPECIAL_BASE 0x42A0E80ull
+#define DCORE1_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU2_MMU_SPECIAL_SECTION 0x1800
+#define DCORE1_HMMU2_STLB_BASE 0x42A1000ull
+#define DCORE1_HMMU2_STLB_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_STLB_SECTION 0xE800
+#define DCORE1_HMMU2_STLB_SPECIAL_BASE 0x42A1E80ull
+#define DCORE1_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU2_STLB_SPECIAL_SECTION 0x1180
+#define DCORE1_HMMU2_SCRAMB_OUT_BASE 0x42A3000ull
+#define DCORE1_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_SCRAMB_OUT_SECTION 0xE800
+#define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x42A3E80ull
+#define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x42A4000ull
+#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x42A4200ull
+#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x42A4400ull
+#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x42A4600ull
+#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x42A4800ull
+#define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_HMMU2_MSTR_IF_AXUSER_BASE 0x42A4A80ull
+#define DCORE1_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_HMMU2_MSTR_IF_DBG_HBW_BASE 0x42A4B00ull
+#define DCORE1_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_HMMU2_MSTR_IF_DBG_LBW_BASE 0x42A4B80ull
+#define DCORE1_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_HMMU2_MSTR_IF_CORE_HBW_BASE 0x42A4C00ull
+#define DCORE1_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_HMMU2_MSTR_IF_CORE_LBW_BASE 0x42A4D80ull
+#define DCORE1_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_HMMU2_MSTR_IF_SPECIAL_BASE 0x42A4E80ull
+#define DCORE1_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE1_HMMU3_MMU_BASE 0x42B0000ull
+#define DCORE1_HMMU3_MMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_MMU_SECTION 0xE800
+#define DCORE1_HMMU3_MMU_SPECIAL_BASE 0x42B0E80ull
+#define DCORE1_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU3_MMU_SPECIAL_SECTION 0x1800
+#define DCORE1_HMMU3_STLB_BASE 0x42B1000ull
+#define DCORE1_HMMU3_STLB_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_STLB_SECTION 0xE800
+#define DCORE1_HMMU3_STLB_SPECIAL_BASE 0x42B1E80ull
+#define DCORE1_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU3_STLB_SPECIAL_SECTION 0x1180
+#define DCORE1_HMMU3_SCRAMB_OUT_BASE 0x42B3000ull
+#define DCORE1_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_SCRAMB_OUT_SECTION 0xE800
+#define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x42B3E80ull
+#define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x42B4000ull
+#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x42B4200ull
+#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x42B4400ull
+#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x42B4600ull
+#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x42B4800ull
+#define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_HMMU3_MSTR_IF_AXUSER_BASE 0x42B4A80ull
+#define DCORE1_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_HMMU3_MSTR_IF_DBG_HBW_BASE 0x42B4B00ull
+#define DCORE1_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_HMMU3_MSTR_IF_DBG_LBW_BASE 0x42B4B80ull
+#define DCORE1_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_HMMU3_MSTR_IF_CORE_HBW_BASE 0x42B4C00ull
+#define DCORE1_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_HMMU3_MSTR_IF_CORE_LBW_BASE 0x42B4D80ull
+#define DCORE1_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_HMMU3_MSTR_IF_SPECIAL_BASE 0x42B4E80ull
+#define DCORE1_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE1_MME_QM_ARC_DCCM_BASE 0x42C0000ull
+#define DCORE1_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_MME_QM_ARC_DCCM_SECTION 0x8000
+#define DCORE1_MME_QM_ARC_AUX_BASE 0x42C8000ull
+#define DCORE1_MME_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_MME_QM_ARC_AUX_SECTION 0xE800
+#define DCORE1_MME_QM_ARC_AUX_SPECIAL_BASE 0x42C8E80ull
+#define DCORE1_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_QM_ARC_DUP_ENG_BASE 0x42C9000ull
+#define DCORE1_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000
+#define DCORE1_MME_QM_ARC_DUP_ENG_SECTION 0x9000
+#define DCORE1_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x42C9900ull
+#define DCORE1_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800
+#define DCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x42C9E80ull
+#define DCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_QM_BASE 0x42CA000ull
+#define DCORE1_MME_QM_MAX_OFFSET 0x1000
+#define DCORE1_MME_QM_SECTION 0x9000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x42CA900ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x42CA908ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x42CA910ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x42CA918ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x42CA920ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x42CA928ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x42CA930ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x42CA938ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x42CA940ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x42CA948ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x42CA950ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x42CA958ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x42CA960ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x42CA968ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x42CA970ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x42CA978ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_MME_QM_AXUSER_SECURED_BASE 0x42CAB00ull
+#define DCORE1_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_MME_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_MME_QM_AXUSER_NONSECURED_BASE 0x42CAB80ull
+#define DCORE1_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_MME_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_MME_QM_DBG_HBW_BASE 0x42CAC00ull
+#define DCORE1_MME_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_MME_QM_DBG_LBW_BASE 0x42CAC80ull
+#define DCORE1_MME_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_MME_QM_CGM_BASE 0x42CAD80ull
+#define DCORE1_MME_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_MME_QM_CGM_SECTION 0x1000
+#define DCORE1_MME_QM_SPECIAL_BASE 0x42CAE80ull
+#define DCORE1_MME_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_CTRL_LO_BASE 0x42CB000ull
+#define DCORE1_MME_CTRL_LO_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_LO_SECTION 0x8000
+#define DCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x42CB008ull
+#define DCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000
+#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x42CB028ull
+#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x42CB040ull
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x42CB098ull
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x42CB0F0ull
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x42CB15Cull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x42CB170ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x42CB184ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x42CB198ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x42CB1ACull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x42CB1C0ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x42CB1D4ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x42CB1E8ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x42CB1FCull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x42CB210ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x42CB22Cull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x42CB240ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x42CB254ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x42CB268ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x42CB280ull
+#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800
+#define DCORE1_MME_CTRL_LO_MME_AXUSER_BASE 0x42CBE00ull
+#define DCORE1_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000
+#define DCORE1_MME_CTRL_LO_SPECIAL_BASE 0x42CBE80ull
+#define DCORE1_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_LO_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_CTRL_HI_BASE 0x42CC000ull
+#define DCORE1_MME_CTRL_HI_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_HI_SECTION 0x8000
+#define DCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x42CC008ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000
+#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x42CC028ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x42CC040ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x42CC098ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x42CC0F0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x42CC15Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x42CC170ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x42CC184ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x42CC198ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x42CC1ACull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x42CC1C0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x42CC1D4ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x42CC1E8ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x42CC1FCull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x42CC210ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x42CC22Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x42CC240ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x42CC254ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x42CC268ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x42CC280ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800
+#define DCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x42CC308ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000
+#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x42CC328ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x42CC340ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x42CC398ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x42CC3F0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x42CC45Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x42CC470ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x42CC484ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x42CC498ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x42CC4ACull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x42CC4C0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x42CC4D4ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x42CC4E8ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x42CC4FCull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x42CC510ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x42CC52Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x42CC540ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x42CC554ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x42CC568ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x42CC580ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800
+#define DCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x42CC608ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000
+#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x42CC628ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x42CC640ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x42CC698ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x42CC6F0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x42CC75Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x42CC770ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x42CC784ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x42CC798ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x42CC7ACull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x42CC7C0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x42CC7D4ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x42CC7E8ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x42CC7FCull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x42CC810ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x42CC82Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x42CC840ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x42CC854ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x42CC868ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x42CC880ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800
+#define DCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x42CC908ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000
+#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x42CC928ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x42CC940ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x42CC998ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x42CC9F0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x42CCA5Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x42CCA70ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x42CCA84ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x42CCA98ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x42CCAACull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x42CCAC0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x42CCAD4ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x42CCAE8ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x42CCAFCull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x42CCB10ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x42CCB2Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x42CCB40ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x42CCB54ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x42CCB68ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x42CCB80ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000
+#define DCORE1_MME_CTRL_HI_SPECIAL_BASE 0x42CCE80ull
+#define DCORE1_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_HI_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_EU_BIST_BASE 0x42CD000ull
+#define DCORE1_MME_EU_BIST_MAX_OFFSET 0x1000
+#define DCORE1_MME_EU_BIST_SECTION 0xE800
+#define DCORE1_MME_EU_BIST_SPECIAL_BASE 0x42CDE80ull
+#define DCORE1_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_EU_BIST_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x42CE000ull
+#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x42CE200ull
+#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x42CE400ull
+#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x42CE600ull
+#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x42CE800ull
+#define DCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_MME_CTRL_MSTR_IF_AXUSER_BASE 0x42CEA80ull
+#define DCORE1_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x42CEB00ull
+#define DCORE1_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x42CEB80ull
+#define DCORE1_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x42CEC00ull
+#define DCORE1_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x42CED80ull
+#define DCORE1_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x42CEE80ull
+#define DCORE1_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_QM_ARC_ACP_ENG_BASE 0x42CF000ull
+#define DCORE1_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000
+#define DCORE1_MME_QM_ARC_ACP_ENG_SECTION 0xE800
+#define DCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x42CFE80ull
+#define DCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_SBTE0_BASE 0x42D0000ull
+#define DCORE1_MME_SBTE0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_SECTION 0xE800
+#define DCORE1_MME_SBTE0_SPECIAL_BASE 0x42D0E80ull
+#define DCORE1_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE0_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x42D1000ull
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x42D1200ull
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x42D1400ull
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x42D1600ull
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x42D1800ull
+#define DCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x42D1A80ull
+#define DCORE1_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x42D1B00ull
+#define DCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x42D1B80ull
+#define DCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x42D1C00ull
+#define DCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x42D1D80ull
+#define DCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x42D1E80ull
+#define DCORE1_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE1_MME_SBTE1_BASE 0x42D8000ull
+#define DCORE1_MME_SBTE1_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_SECTION 0xE800
+#define DCORE1_MME_SBTE1_SPECIAL_BASE 0x42D8E80ull
+#define DCORE1_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE1_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x42D9000ull
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x42D9200ull
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x42D9400ull
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x42D9600ull
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x42D9800ull
+#define DCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x42D9A80ull
+#define DCORE1_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x42D9B00ull
+#define DCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x42D9B80ull
+#define DCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x42D9C00ull
+#define DCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x42D9D80ull
+#define DCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x42D9E80ull
+#define DCORE1_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE1_MME_SBTE2_BASE 0x42E0000ull
+#define DCORE1_MME_SBTE2_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_SECTION 0xE800
+#define DCORE1_MME_SBTE2_SPECIAL_BASE 0x42E0E80ull
+#define DCORE1_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE2_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x42E1000ull
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x42E1200ull
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x42E1400ull
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x42E1600ull
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x42E1800ull
+#define DCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x42E1A80ull
+#define DCORE1_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x42E1B00ull
+#define DCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x42E1B80ull
+#define DCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x42E1C00ull
+#define DCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x42E1D80ull
+#define DCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x42E1E80ull
+#define DCORE1_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE1_MME_SBTE3_BASE 0x42E8000ull
+#define DCORE1_MME_SBTE3_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_SECTION 0xE800
+#define DCORE1_MME_SBTE3_SPECIAL_BASE 0x42E8E80ull
+#define DCORE1_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE3_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x42E9000ull
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x42E9200ull
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x42E9400ull
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x42E9600ull
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x42E9800ull
+#define DCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x42E9A80ull
+#define DCORE1_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x42E9B00ull
+#define DCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x42E9B80ull
+#define DCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x42E9C00ull
+#define DCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x42E9D80ull
+#define DCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x42E9E80ull
+#define DCORE1_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE1_MME_SBTE4_BASE 0x42F0000ull
+#define DCORE1_MME_SBTE4_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_SECTION 0xE800
+#define DCORE1_MME_SBTE4_SPECIAL_BASE 0x42F0E80ull
+#define DCORE1_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE4_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x42F1000ull
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x42F1200ull
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x42F1400ull
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x42F1600ull
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x42F1800ull
+#define DCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x42F1A80ull
+#define DCORE1_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x42F1B00ull
+#define DCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x42F1B80ull
+#define DCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x42F1C00ull
+#define DCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x42F1D80ull
+#define DCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x42F1E80ull
+#define DCORE1_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE1_MME_ACC_BASE 0x42F8000ull
+#define DCORE1_MME_ACC_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_SECTION 0xE800
+#define DCORE1_MME_ACC_SPECIAL_BASE 0x42F8E80ull
+#define DCORE1_MME_ACC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_ACC_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x42F9000ull
+#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x42F9200ull
+#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x42F9400ull
+#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x42F9600ull
+#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x42F9800ull
+#define DCORE1_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_MME_WB0_MSTR_IF_AXUSER_BASE 0x42F9A80ull
+#define DCORE1_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x42F9B00ull
+#define DCORE1_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x42F9B80ull
+#define DCORE1_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x42F9C00ull
+#define DCORE1_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x42F9D80ull
+#define DCORE1_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_MME_WB0_MSTR_IF_SPECIAL_BASE 0x42F9E80ull
+#define DCORE1_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x42FA000ull
+#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x42FA200ull
+#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x42FA400ull
+#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x42FA600ull
+#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x42FA800ull
+#define DCORE1_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_MME_WB1_MSTR_IF_AXUSER_BASE 0x42FAA80ull
+#define DCORE1_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x42FAB00ull
+#define DCORE1_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x42FAB80ull
+#define DCORE1_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x42FAC00ull
+#define DCORE1_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x42FAD80ull
+#define DCORE1_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_MME_WB1_MSTR_IF_SPECIAL_BASE 0x42FAE80ull
+#define DCORE1_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180
+#define DCORE1_SYNC_MNGR_OBJS_BASE 0x4300000ull
+#define DCORE1_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00
+#define DCORE1_SYNC_MNGR_OBJS_SECTION 0x1E000
+#define DCORE1_SYNC_MNGR_GLBL_BASE 0x431E000ull
+#define DCORE1_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000
+#define DCORE1_SYNC_MNGR_GLBL_SECTION 0xE800
+#define DCORE1_SYNC_MNGR_GLBL_SPECIAL_BASE 0x431EE80ull
+#define DCORE1_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x431F000ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x431F200ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x431F400ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x431F600ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x431F800ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x431FA80ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x431FB00ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x431FB80ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x431FC00ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x431FD80ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x431FE80ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE1_HIF0_BASE 0x4320000ull
+#define DCORE1_HIF0_MAX_OFFSET 0x1000
+#define DCORE1_HIF0_SECTION 0xE800
+#define DCORE1_HIF0_SPECIAL_BASE 0x4320E80ull
+#define DCORE1_HIF0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HIF0_SPECIAL_SECTION 0x3180
+#define DCORE1_HIF1_BASE 0x4324000ull
+#define DCORE1_HIF1_MAX_OFFSET 0x1000
+#define DCORE1_HIF1_SECTION 0xE800
+#define DCORE1_HIF1_SPECIAL_BASE 0x4324E80ull
+#define DCORE1_HIF1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HIF1_SPECIAL_SECTION 0x3180
+#define DCORE1_HIF2_BASE 0x4328000ull
+#define DCORE1_HIF2_MAX_OFFSET 0x1000
+#define DCORE1_HIF2_SECTION 0xE800
+#define DCORE1_HIF2_SPECIAL_BASE 0x4328E80ull
+#define DCORE1_HIF2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HIF2_SPECIAL_SECTION 0x3180
+#define DCORE1_HIF3_BASE 0x432C000ull
+#define DCORE1_HIF3_MAX_OFFSET 0x1000
+#define DCORE1_HIF3_SECTION 0xE800
+#define DCORE1_HIF3_SPECIAL_BASE 0x432CE80ull
+#define DCORE1_HIF3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HIF3_SPECIAL_SECTION 0x13180
+#define DCORE1_RTR0_CTRL_BASE 0x4340000ull
+#define DCORE1_RTR0_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR0_CTRL_SECTION 0xE800
+#define DCORE1_RTR0_CTRL_SPECIAL_BASE 0x4340E80ull
+#define DCORE1_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR0_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR0_H3_BASE 0x4341000ull
+#define DCORE1_RTR0_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR0_H3_SECTION 0xE800
+#define DCORE1_RTR0_H3_SPECIAL_BASE 0x4341E80ull
+#define DCORE1_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR0_H3_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4342000ull
+#define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4342200ull
+#define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4342400ull
+#define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4342600ull
+#define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4342800ull
+#define DCORE1_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_RTR0_MSTR_IF_AXUSER_BASE 0x4342A80ull
+#define DCORE1_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_RTR0_MSTR_IF_DBG_HBW_BASE 0x4342B00ull
+#define DCORE1_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_RTR0_MSTR_IF_DBG_LBW_BASE 0x4342B80ull
+#define DCORE1_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_RTR0_MSTR_IF_CORE_HBW_BASE 0x4342C00ull
+#define DCORE1_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_RTR0_MSTR_IF_CORE_LBW_BASE 0x4342D80ull
+#define DCORE1_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_RTR0_MSTR_IF_SPECIAL_BASE 0x4342E80ull
+#define DCORE1_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR0_ADD_DEC_HBW_BASE 0x4343000ull
+#define DCORE1_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR0_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE1_RTR0_ADD_DEC_LBW_BASE 0x4343400ull
+#define DCORE1_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR0_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE1_RTR0_ADD_DEC_SPECIAL_BASE 0x4343E80ull
+#define DCORE1_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR0_BASE 0x4344000ull
+#define DCORE1_RTR0_MAX_OFFSET 0x1000
+#define DCORE1_RTR0_SECTION 0x3000
+#define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4344300ull
+#define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4344340ull
+#define DCORE1_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4344380ull
+#define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR0_HBW_WR_RS_LL_STAT_BASE 0x43443C0ull
+#define DCORE1_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4344400ull
+#define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4344440ull
+#define DCORE1_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4344480ull
+#define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR0_LBW_WR_RS_LL_STAT_BASE 0x43444C0ull
+#define DCORE1_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR0_HBW_MFIFO_BASE 0x4344500ull
+#define DCORE1_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_HBW_MFIFO_SECTION 0x4000
+#define DCORE1_RTR0_E2E_RD_LL_STAT_BASE 0x4344540ull
+#define DCORE1_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR0_E2E_WR_LL_STAT_BASE 0x4344580ull
+#define DCORE1_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE1_RTR0_RTR_HBW_XACT_STAT_BASE 0x4344600ull
+#define DCORE1_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR0_RTR_LBW_XACT_STAT_BASE 0x4344680ull
+#define DCORE1_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR0_RTR_E2E_XACT_STAT_BASE 0x4344700ull
+#define DCORE1_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE1_RTR0_SPECIAL_BASE 0x4344E80ull
+#define DCORE1_RTR0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR0_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR0_DBG_ADDR_BASE 0x4345000ull
+#define DCORE1_RTR0_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR0_DBG_ADDR_SECTION 0xE800
+#define DCORE1_RTR0_DBG_ADDR_SPECIAL_BASE 0x4345E80ull
+#define DCORE1_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE1_RTR1_CTRL_BASE 0x4348000ull
+#define DCORE1_RTR1_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR1_CTRL_SECTION 0xE800
+#define DCORE1_RTR1_CTRL_SPECIAL_BASE 0x4348E80ull
+#define DCORE1_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR1_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR1_H3_BASE 0x4349000ull
+#define DCORE1_RTR1_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR1_H3_SECTION 0xE800
+#define DCORE1_RTR1_H3_SPECIAL_BASE 0x4349E80ull
+#define DCORE1_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR1_H3_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x434A000ull
+#define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x434A200ull
+#define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x434A400ull
+#define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x434A600ull
+#define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_RTR1_MSTR_IF_E2E_CRDT_BASE 0x434A800ull
+#define DCORE1_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_RTR1_MSTR_IF_AXUSER_BASE 0x434AA80ull
+#define DCORE1_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_RTR1_MSTR_IF_DBG_HBW_BASE 0x434AB00ull
+#define DCORE1_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_RTR1_MSTR_IF_DBG_LBW_BASE 0x434AB80ull
+#define DCORE1_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_RTR1_MSTR_IF_CORE_HBW_BASE 0x434AC00ull
+#define DCORE1_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_RTR1_MSTR_IF_CORE_LBW_BASE 0x434AD80ull
+#define DCORE1_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_RTR1_MSTR_IF_SPECIAL_BASE 0x434AE80ull
+#define DCORE1_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR1_ADD_DEC_HBW_BASE 0x434B000ull
+#define DCORE1_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR1_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE1_RTR1_ADD_DEC_LBW_BASE 0x434B400ull
+#define DCORE1_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR1_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE1_RTR1_ADD_DEC_SPECIAL_BASE 0x434BE80ull
+#define DCORE1_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR1_BASE 0x434C000ull
+#define DCORE1_RTR1_MAX_OFFSET 0x1000
+#define DCORE1_RTR1_SECTION 0x3000
+#define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x434C300ull
+#define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR1_HBW_RD_RS_LL_STAT_BASE 0x434C340ull
+#define DCORE1_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x434C380ull
+#define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR1_HBW_WR_RS_LL_STAT_BASE 0x434C3C0ull
+#define DCORE1_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x434C400ull
+#define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR1_LBW_RD_RS_LL_STAT_BASE 0x434C440ull
+#define DCORE1_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x434C480ull
+#define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR1_LBW_WR_RS_LL_STAT_BASE 0x434C4C0ull
+#define DCORE1_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR1_HBW_MFIFO_BASE 0x434C500ull
+#define DCORE1_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_HBW_MFIFO_SECTION 0x4000
+#define DCORE1_RTR1_E2E_RD_LL_STAT_BASE 0x434C540ull
+#define DCORE1_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR1_E2E_WR_LL_STAT_BASE 0x434C580ull
+#define DCORE1_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE1_RTR1_RTR_HBW_XACT_STAT_BASE 0x434C600ull
+#define DCORE1_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR1_RTR_LBW_XACT_STAT_BASE 0x434C680ull
+#define DCORE1_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR1_RTR_E2E_XACT_STAT_BASE 0x434C700ull
+#define DCORE1_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE1_RTR1_SPECIAL_BASE 0x434CE80ull
+#define DCORE1_RTR1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR1_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR1_DBG_ADDR_BASE 0x434D000ull
+#define DCORE1_RTR1_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR1_DBG_ADDR_SECTION 0xE800
+#define DCORE1_RTR1_DBG_ADDR_SPECIAL_BASE 0x434DE80ull
+#define DCORE1_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE1_RTR2_CTRL_BASE 0x4350000ull
+#define DCORE1_RTR2_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR2_CTRL_SECTION 0xE800
+#define DCORE1_RTR2_CTRL_SPECIAL_BASE 0x4350E80ull
+#define DCORE1_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR2_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR2_H3_BASE 0x4351000ull
+#define DCORE1_RTR2_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR2_H3_SECTION 0xE800
+#define DCORE1_RTR2_H3_SPECIAL_BASE 0x4351E80ull
+#define DCORE1_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR2_H3_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4352000ull
+#define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4352200ull
+#define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4352400ull
+#define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4352600ull
+#define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4352800ull
+#define DCORE1_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_RTR2_MSTR_IF_AXUSER_BASE 0x4352A80ull
+#define DCORE1_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_RTR2_MSTR_IF_DBG_HBW_BASE 0x4352B00ull
+#define DCORE1_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_RTR2_MSTR_IF_DBG_LBW_BASE 0x4352B80ull
+#define DCORE1_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_RTR2_MSTR_IF_CORE_HBW_BASE 0x4352C00ull
+#define DCORE1_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_RTR2_MSTR_IF_CORE_LBW_BASE 0x4352D80ull
+#define DCORE1_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_RTR2_MSTR_IF_SPECIAL_BASE 0x4352E80ull
+#define DCORE1_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR2_ADD_DEC_HBW_BASE 0x4353000ull
+#define DCORE1_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR2_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE1_RTR2_ADD_DEC_LBW_BASE 0x4353400ull
+#define DCORE1_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR2_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE1_RTR2_ADD_DEC_SPECIAL_BASE 0x4353E80ull
+#define DCORE1_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR2_BASE 0x4354000ull
+#define DCORE1_RTR2_MAX_OFFSET 0x1000
+#define DCORE1_RTR2_SECTION 0x3000
+#define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4354300ull
+#define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4354340ull
+#define DCORE1_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4354380ull
+#define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR2_HBW_WR_RS_LL_STAT_BASE 0x43543C0ull
+#define DCORE1_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4354400ull
+#define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4354440ull
+#define DCORE1_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4354480ull
+#define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR2_LBW_WR_RS_LL_STAT_BASE 0x43544C0ull
+#define DCORE1_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR2_HBW_MFIFO_BASE 0x4354500ull
+#define DCORE1_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_HBW_MFIFO_SECTION 0x4000
+#define DCORE1_RTR2_E2E_RD_LL_STAT_BASE 0x4354540ull
+#define DCORE1_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR2_E2E_WR_LL_STAT_BASE 0x4354580ull
+#define DCORE1_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE1_RTR2_RTR_HBW_XACT_STAT_BASE 0x4354600ull
+#define DCORE1_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR2_RTR_LBW_XACT_STAT_BASE 0x4354680ull
+#define DCORE1_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR2_RTR_E2E_XACT_STAT_BASE 0x4354700ull
+#define DCORE1_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE1_RTR2_SPECIAL_BASE 0x4354E80ull
+#define DCORE1_RTR2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR2_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR2_DBG_ADDR_BASE 0x4355000ull
+#define DCORE1_RTR2_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR2_DBG_ADDR_SECTION 0xE800
+#define DCORE1_RTR2_DBG_ADDR_SPECIAL_BASE 0x4355E80ull
+#define DCORE1_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE1_RTR3_CTRL_BASE 0x4358000ull
+#define DCORE1_RTR3_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR3_CTRL_SECTION 0xE800
+#define DCORE1_RTR3_CTRL_SPECIAL_BASE 0x4358E80ull
+#define DCORE1_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR3_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR3_H3_BASE 0x4359000ull
+#define DCORE1_RTR3_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR3_H3_SECTION 0xE800
+#define DCORE1_RTR3_H3_SPECIAL_BASE 0x4359E80ull
+#define DCORE1_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR3_H3_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x435A000ull
+#define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x435A200ull
+#define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x435A400ull
+#define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x435A600ull
+#define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_RTR3_MSTR_IF_E2E_CRDT_BASE 0x435A800ull
+#define DCORE1_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_RTR3_MSTR_IF_AXUSER_BASE 0x435AA80ull
+#define DCORE1_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_RTR3_MSTR_IF_DBG_HBW_BASE 0x435AB00ull
+#define DCORE1_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_RTR3_MSTR_IF_DBG_LBW_BASE 0x435AB80ull
+#define DCORE1_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_RTR3_MSTR_IF_CORE_HBW_BASE 0x435AC00ull
+#define DCORE1_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_RTR3_MSTR_IF_CORE_LBW_BASE 0x435AD80ull
+#define DCORE1_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_RTR3_MSTR_IF_SPECIAL_BASE 0x435AE80ull
+#define DCORE1_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR3_ADD_DEC_HBW_BASE 0x435B000ull
+#define DCORE1_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR3_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE1_RTR3_ADD_DEC_LBW_BASE 0x435B400ull
+#define DCORE1_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR3_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE1_RTR3_ADD_DEC_SPECIAL_BASE 0x435BE80ull
+#define DCORE1_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR3_BASE 0x435C000ull
+#define DCORE1_RTR3_MAX_OFFSET 0x1000
+#define DCORE1_RTR3_SECTION 0x3000
+#define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x435C300ull
+#define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR3_HBW_RD_RS_LL_STAT_BASE 0x435C340ull
+#define DCORE1_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x435C380ull
+#define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR3_HBW_WR_RS_LL_STAT_BASE 0x435C3C0ull
+#define DCORE1_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x435C400ull
+#define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR3_LBW_RD_RS_LL_STAT_BASE 0x435C440ull
+#define DCORE1_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x435C480ull
+#define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR3_LBW_WR_RS_LL_STAT_BASE 0x435C4C0ull
+#define DCORE1_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR3_HBW_MFIFO_BASE 0x435C500ull
+#define DCORE1_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_HBW_MFIFO_SECTION 0x4000
+#define DCORE1_RTR3_E2E_RD_LL_STAT_BASE 0x435C540ull
+#define DCORE1_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR3_E2E_WR_LL_STAT_BASE 0x435C580ull
+#define DCORE1_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE1_RTR3_RTR_HBW_XACT_STAT_BASE 0x435C600ull
+#define DCORE1_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR3_RTR_LBW_XACT_STAT_BASE 0x435C680ull
+#define DCORE1_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR3_RTR_E2E_XACT_STAT_BASE 0x435C700ull
+#define DCORE1_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE1_RTR3_SPECIAL_BASE 0x435CE80ull
+#define DCORE1_RTR3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR3_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR3_DBG_ADDR_BASE 0x435D000ull
+#define DCORE1_RTR3_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR3_DBG_ADDR_SECTION 0xE800
+#define DCORE1_RTR3_DBG_ADDR_SPECIAL_BASE 0x435DE80ull
+#define DCORE1_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE1_RTR4_CTRL_BASE 0x4360000ull
+#define DCORE1_RTR4_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR4_CTRL_SECTION 0xE800
+#define DCORE1_RTR4_CTRL_SPECIAL_BASE 0x4360E80ull
+#define DCORE1_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR4_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR4_H3_BASE 0x4361000ull
+#define DCORE1_RTR4_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR4_H3_SECTION 0xE800
+#define DCORE1_RTR4_H3_SPECIAL_BASE 0x4361E80ull
+#define DCORE1_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR4_H3_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4362000ull
+#define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4362200ull
+#define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4362400ull
+#define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4362600ull
+#define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4362800ull
+#define DCORE1_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_RTR4_MSTR_IF_AXUSER_BASE 0x4362A80ull
+#define DCORE1_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR4_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_RTR4_MSTR_IF_DBG_HBW_BASE 0x4362B00ull
+#define DCORE1_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_RTR4_MSTR_IF_DBG_LBW_BASE 0x4362B80ull
+#define DCORE1_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_RTR4_MSTR_IF_CORE_HBW_BASE 0x4362C00ull
+#define DCORE1_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_RTR4_MSTR_IF_CORE_LBW_BASE 0x4362D80ull
+#define DCORE1_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_RTR4_MSTR_IF_SPECIAL_BASE 0x4362E80ull
+#define DCORE1_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR4_ADD_DEC_HBW_BASE 0x4363000ull
+#define DCORE1_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR4_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE1_RTR4_ADD_DEC_LBW_BASE 0x4363400ull
+#define DCORE1_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR4_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE1_RTR4_ADD_DEC_SPECIAL_BASE 0x4363E80ull
+#define DCORE1_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR4_BASE 0x4364000ull
+#define DCORE1_RTR4_MAX_OFFSET 0x1000
+#define DCORE1_RTR4_SECTION 0x3000
+#define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4364300ull
+#define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4364340ull
+#define DCORE1_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4364380ull
+#define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR4_HBW_WR_RS_LL_STAT_BASE 0x43643C0ull
+#define DCORE1_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4364400ull
+#define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4364440ull
+#define DCORE1_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4364480ull
+#define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR4_LBW_WR_RS_LL_STAT_BASE 0x43644C0ull
+#define DCORE1_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR4_HBW_MFIFO_BASE 0x4364500ull
+#define DCORE1_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_HBW_MFIFO_SECTION 0x4000
+#define DCORE1_RTR4_E2E_RD_LL_STAT_BASE 0x4364540ull
+#define DCORE1_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR4_E2E_WR_LL_STAT_BASE 0x4364580ull
+#define DCORE1_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE1_RTR4_RTR_HBW_XACT_STAT_BASE 0x4364600ull
+#define DCORE1_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR4_RTR_LBW_XACT_STAT_BASE 0x4364680ull
+#define DCORE1_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR4_RTR_E2E_XACT_STAT_BASE 0x4364700ull
+#define DCORE1_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE1_RTR4_SPECIAL_BASE 0x4364E80ull
+#define DCORE1_RTR4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR4_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR4_DBG_ADDR_BASE 0x4365000ull
+#define DCORE1_RTR4_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR4_DBG_ADDR_SECTION 0xE800
+#define DCORE1_RTR4_DBG_ADDR_SPECIAL_BASE 0x4365E80ull
+#define DCORE1_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE1_RTR5_CTRL_BASE 0x4368000ull
+#define DCORE1_RTR5_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR5_CTRL_SECTION 0xE800
+#define DCORE1_RTR5_CTRL_SPECIAL_BASE 0x4368E80ull
+#define DCORE1_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR5_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR5_H3_BASE 0x4369000ull
+#define DCORE1_RTR5_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR5_H3_SECTION 0xE800
+#define DCORE1_RTR5_H3_SPECIAL_BASE 0x4369E80ull
+#define DCORE1_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR5_H3_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x436A000ull
+#define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x436A200ull
+#define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x436A400ull
+#define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x436A600ull
+#define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_RTR5_MSTR_IF_E2E_CRDT_BASE 0x436A800ull
+#define DCORE1_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_RTR5_MSTR_IF_AXUSER_BASE 0x436AA80ull
+#define DCORE1_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR5_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_RTR5_MSTR_IF_DBG_HBW_BASE 0x436AB00ull
+#define DCORE1_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_RTR5_MSTR_IF_DBG_LBW_BASE 0x436AB80ull
+#define DCORE1_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_RTR5_MSTR_IF_CORE_HBW_BASE 0x436AC00ull
+#define DCORE1_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_RTR5_MSTR_IF_CORE_LBW_BASE 0x436AD80ull
+#define DCORE1_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_RTR5_MSTR_IF_SPECIAL_BASE 0x436AE80ull
+#define DCORE1_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR5_ADD_DEC_HBW_BASE 0x436B000ull
+#define DCORE1_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR5_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE1_RTR5_ADD_DEC_LBW_BASE 0x436B400ull
+#define DCORE1_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR5_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE1_RTR5_ADD_DEC_SPECIAL_BASE 0x436BE80ull
+#define DCORE1_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR5_BASE 0x436C000ull
+#define DCORE1_RTR5_MAX_OFFSET 0x1000
+#define DCORE1_RTR5_SECTION 0x3000
+#define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x436C300ull
+#define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR5_HBW_RD_RS_LL_STAT_BASE 0x436C340ull
+#define DCORE1_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x436C380ull
+#define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR5_HBW_WR_RS_LL_STAT_BASE 0x436C3C0ull
+#define DCORE1_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x436C400ull
+#define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR5_LBW_RD_RS_LL_STAT_BASE 0x436C440ull
+#define DCORE1_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x436C480ull
+#define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR5_LBW_WR_RS_LL_STAT_BASE 0x436C4C0ull
+#define DCORE1_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR5_HBW_MFIFO_BASE 0x436C500ull
+#define DCORE1_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_HBW_MFIFO_SECTION 0x4000
+#define DCORE1_RTR5_E2E_RD_LL_STAT_BASE 0x436C540ull
+#define DCORE1_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR5_E2E_WR_LL_STAT_BASE 0x436C580ull
+#define DCORE1_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE1_RTR5_RTR_HBW_XACT_STAT_BASE 0x436C600ull
+#define DCORE1_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR5_RTR_LBW_XACT_STAT_BASE 0x436C680ull
+#define DCORE1_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR5_RTR_E2E_XACT_STAT_BASE 0x436C700ull
+#define DCORE1_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE1_RTR5_SPECIAL_BASE 0x436CE80ull
+#define DCORE1_RTR5_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR5_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR5_DBG_ADDR_BASE 0x436D000ull
+#define DCORE1_RTR5_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR5_DBG_ADDR_SECTION 0xE800
+#define DCORE1_RTR5_DBG_ADDR_SPECIAL_BASE 0x436DE80ull
+#define DCORE1_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE1_RTR6_CTRL_BASE 0x4370000ull
+#define DCORE1_RTR6_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR6_CTRL_SECTION 0xE800
+#define DCORE1_RTR6_CTRL_SPECIAL_BASE 0x4370E80ull
+#define DCORE1_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR6_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR6_H3_BASE 0x4371000ull
+#define DCORE1_RTR6_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR6_H3_SECTION 0xE800
+#define DCORE1_RTR6_H3_SPECIAL_BASE 0x4371E80ull
+#define DCORE1_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR6_H3_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4372000ull
+#define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4372200ull
+#define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4372400ull
+#define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4372600ull
+#define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4372800ull
+#define DCORE1_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_RTR6_MSTR_IF_AXUSER_BASE 0x4372A80ull
+#define DCORE1_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR6_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_RTR6_MSTR_IF_DBG_HBW_BASE 0x4372B00ull
+#define DCORE1_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_RTR6_MSTR_IF_DBG_LBW_BASE 0x4372B80ull
+#define DCORE1_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_RTR6_MSTR_IF_CORE_HBW_BASE 0x4372C00ull
+#define DCORE1_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_RTR6_MSTR_IF_CORE_LBW_BASE 0x4372D80ull
+#define DCORE1_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_RTR6_MSTR_IF_SPECIAL_BASE 0x4372E80ull
+#define DCORE1_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR6_ADD_DEC_HBW_BASE 0x4373000ull
+#define DCORE1_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR6_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE1_RTR6_ADD_DEC_LBW_BASE 0x4373400ull
+#define DCORE1_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR6_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE1_RTR6_ADD_DEC_SPECIAL_BASE 0x4373E80ull
+#define DCORE1_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR6_BASE 0x4374000ull
+#define DCORE1_RTR6_MAX_OFFSET 0x1000
+#define DCORE1_RTR6_SECTION 0x3000
+#define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4374300ull
+#define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4374340ull
+#define DCORE1_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4374380ull
+#define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR6_HBW_WR_RS_LL_STAT_BASE 0x43743C0ull
+#define DCORE1_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4374400ull
+#define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4374440ull
+#define DCORE1_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4374480ull
+#define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR6_LBW_WR_RS_LL_STAT_BASE 0x43744C0ull
+#define DCORE1_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR6_HBW_MFIFO_BASE 0x4374500ull
+#define DCORE1_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_HBW_MFIFO_SECTION 0x4000
+#define DCORE1_RTR6_E2E_RD_LL_STAT_BASE 0x4374540ull
+#define DCORE1_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR6_E2E_WR_LL_STAT_BASE 0x4374580ull
+#define DCORE1_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE1_RTR6_RTR_HBW_XACT_STAT_BASE 0x4374600ull
+#define DCORE1_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR6_RTR_LBW_XACT_STAT_BASE 0x4374680ull
+#define DCORE1_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR6_RTR_E2E_XACT_STAT_BASE 0x4374700ull
+#define DCORE1_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE1_RTR6_SPECIAL_BASE 0x4374E80ull
+#define DCORE1_RTR6_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR6_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR6_DBG_ADDR_BASE 0x4375000ull
+#define DCORE1_RTR6_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR6_DBG_ADDR_SECTION 0xE800
+#define DCORE1_RTR6_DBG_ADDR_SPECIAL_BASE 0x4375E80ull
+#define DCORE1_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE1_RTR7_CTRL_BASE 0x4378000ull
+#define DCORE1_RTR7_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR7_CTRL_SECTION 0xE800
+#define DCORE1_RTR7_CTRL_SPECIAL_BASE 0x4378E80ull
+#define DCORE1_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR7_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR7_H3_BASE 0x4379000ull
+#define DCORE1_RTR7_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR7_H3_SECTION 0xE800
+#define DCORE1_RTR7_H3_SPECIAL_BASE 0x4379E80ull
+#define DCORE1_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR7_H3_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x437A000ull
+#define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x437A200ull
+#define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x437A400ull
+#define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x437A600ull
+#define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_RTR7_MSTR_IF_E2E_CRDT_BASE 0x437A800ull
+#define DCORE1_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_RTR7_MSTR_IF_AXUSER_BASE 0x437AA80ull
+#define DCORE1_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR7_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_RTR7_MSTR_IF_DBG_HBW_BASE 0x437AB00ull
+#define DCORE1_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_RTR7_MSTR_IF_DBG_LBW_BASE 0x437AB80ull
+#define DCORE1_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_RTR7_MSTR_IF_CORE_HBW_BASE 0x437AC00ull
+#define DCORE1_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_RTR7_MSTR_IF_CORE_LBW_BASE 0x437AD80ull
+#define DCORE1_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_RTR7_MSTR_IF_SPECIAL_BASE 0x437AE80ull
+#define DCORE1_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR7_ADD_DEC_HBW_BASE 0x437B000ull
+#define DCORE1_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR7_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE1_RTR7_ADD_DEC_LBW_BASE 0x437B400ull
+#define DCORE1_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR7_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE1_RTR7_ADD_DEC_SPECIAL_BASE 0x437BE80ull
+#define DCORE1_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR7_BASE 0x437C000ull
+#define DCORE1_RTR7_MAX_OFFSET 0x1000
+#define DCORE1_RTR7_SECTION 0x3000
+#define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x437C300ull
+#define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR7_HBW_RD_RS_LL_STAT_BASE 0x437C340ull
+#define DCORE1_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x437C380ull
+#define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR7_HBW_WR_RS_LL_STAT_BASE 0x437C3C0ull
+#define DCORE1_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x437C400ull
+#define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR7_LBW_RD_RS_LL_STAT_BASE 0x437C440ull
+#define DCORE1_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x437C480ull
+#define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR7_LBW_WR_RS_LL_STAT_BASE 0x437C4C0ull
+#define DCORE1_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR7_HBW_MFIFO_BASE 0x437C500ull
+#define DCORE1_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_HBW_MFIFO_SECTION 0x4000
+#define DCORE1_RTR7_E2E_RD_LL_STAT_BASE 0x437C540ull
+#define DCORE1_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE1_RTR7_E2E_WR_LL_STAT_BASE 0x437C580ull
+#define DCORE1_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE1_RTR7_RTR_HBW_XACT_STAT_BASE 0x437C600ull
+#define DCORE1_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR7_RTR_LBW_XACT_STAT_BASE 0x437C680ull
+#define DCORE1_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE1_RTR7_RTR_E2E_XACT_STAT_BASE 0x437C700ull
+#define DCORE1_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE1_RTR7_SPECIAL_BASE 0x437CE80ull
+#define DCORE1_RTR7_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR7_SPECIAL_SECTION 0x1800
+#define DCORE1_RTR7_DBG_ADDR_BASE 0x437D000ull
+#define DCORE1_RTR7_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR7_DBG_ADDR_SECTION 0xE800
+#define DCORE1_RTR7_DBG_ADDR_SPECIAL_BASE 0x437DE80ull
+#define DCORE1_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE1_SRAM0_BANK_BASE 0x4380000ull
+#define DCORE1_SRAM0_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM0_BANK_SECTION 0xE800
+#define DCORE1_SRAM0_BANK_SPECIAL_BASE 0x4380E80ull
+#define DCORE1_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM0_BANK_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM0_RTR_BASE 0x4381000ull
+#define DCORE1_SRAM0_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM0_RTR_SECTION 0xE800
+#define DCORE1_SRAM0_RTR_SPECIAL_BASE 0x4381E80ull
+#define DCORE1_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM0_RTR_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4382000ull
+#define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4382100ull
+#define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4382200ull
+#define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4382300ull
+#define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4382400ull
+#define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4382500ull
+#define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4382600ull
+#define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4382700ull
+#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4382780ull
+#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4382800ull
+#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4382880ull
+#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4382900ull
+#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4382980ull
+#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4382A00ull
+#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4382A80ull
+#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE1_SRAM0_DBG_CNT_SPECIAL_BASE 0x4382E80ull
+#define DCORE1_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE1_SRAM1_BANK_BASE 0x4388000ull
+#define DCORE1_SRAM1_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM1_BANK_SECTION 0xE800
+#define DCORE1_SRAM1_BANK_SPECIAL_BASE 0x4388E80ull
+#define DCORE1_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM1_BANK_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM1_RTR_BASE 0x4389000ull
+#define DCORE1_SRAM1_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM1_RTR_SECTION 0xE800
+#define DCORE1_SRAM1_RTR_SPECIAL_BASE 0x4389E80ull
+#define DCORE1_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM1_RTR_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x438A000ull
+#define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x438A100ull
+#define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x438A200ull
+#define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x438A300ull
+#define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x438A400ull
+#define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x438A500ull
+#define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x438A600ull
+#define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x438A700ull
+#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x438A780ull
+#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x438A800ull
+#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x438A880ull
+#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x438A900ull
+#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x438A980ull
+#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x438AA00ull
+#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x438AA80ull
+#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE1_SRAM1_DBG_CNT_SPECIAL_BASE 0x438AE80ull
+#define DCORE1_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE1_SRAM2_BANK_BASE 0x4390000ull
+#define DCORE1_SRAM2_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM2_BANK_SECTION 0xE800
+#define DCORE1_SRAM2_BANK_SPECIAL_BASE 0x4390E80ull
+#define DCORE1_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM2_BANK_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM2_RTR_BASE 0x4391000ull
+#define DCORE1_SRAM2_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM2_RTR_SECTION 0xE800
+#define DCORE1_SRAM2_RTR_SPECIAL_BASE 0x4391E80ull
+#define DCORE1_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM2_RTR_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4392000ull
+#define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4392100ull
+#define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4392200ull
+#define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4392300ull
+#define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4392400ull
+#define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4392500ull
+#define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4392600ull
+#define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4392700ull
+#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4392780ull
+#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4392800ull
+#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4392880ull
+#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4392900ull
+#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4392980ull
+#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4392A00ull
+#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4392A80ull
+#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE1_SRAM2_DBG_CNT_SPECIAL_BASE 0x4392E80ull
+#define DCORE1_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE1_SRAM3_BANK_BASE 0x4398000ull
+#define DCORE1_SRAM3_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM3_BANK_SECTION 0xE800
+#define DCORE1_SRAM3_BANK_SPECIAL_BASE 0x4398E80ull
+#define DCORE1_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM3_BANK_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM3_RTR_BASE 0x4399000ull
+#define DCORE1_SRAM3_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM3_RTR_SECTION 0xE800
+#define DCORE1_SRAM3_RTR_SPECIAL_BASE 0x4399E80ull
+#define DCORE1_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM3_RTR_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x439A000ull
+#define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x439A100ull
+#define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x439A200ull
+#define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x439A300ull
+#define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x439A400ull
+#define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x439A500ull
+#define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x439A600ull
+#define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x439A700ull
+#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x439A780ull
+#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x439A800ull
+#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x439A880ull
+#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x439A900ull
+#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x439A980ull
+#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x439AA00ull
+#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x439AA80ull
+#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE1_SRAM3_DBG_CNT_SPECIAL_BASE 0x439AE80ull
+#define DCORE1_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE1_SRAM4_BANK_BASE 0x43A0000ull
+#define DCORE1_SRAM4_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM4_BANK_SECTION 0xE800
+#define DCORE1_SRAM4_BANK_SPECIAL_BASE 0x43A0E80ull
+#define DCORE1_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM4_BANK_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM4_RTR_BASE 0x43A1000ull
+#define DCORE1_SRAM4_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM4_RTR_SECTION 0xE800
+#define DCORE1_SRAM4_RTR_SPECIAL_BASE 0x43A1E80ull
+#define DCORE1_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM4_RTR_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43A2000ull
+#define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43A2100ull
+#define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43A2200ull
+#define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43A2300ull
+#define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43A2400ull
+#define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43A2500ull
+#define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43A2600ull
+#define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43A2700ull
+#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43A2780ull
+#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43A2800ull
+#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43A2880ull
+#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43A2900ull
+#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43A2980ull
+#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43A2A00ull
+#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43A2A80ull
+#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE1_SRAM4_DBG_CNT_SPECIAL_BASE 0x43A2E80ull
+#define DCORE1_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE1_SRAM5_BANK_BASE 0x43A8000ull
+#define DCORE1_SRAM5_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM5_BANK_SECTION 0xE800
+#define DCORE1_SRAM5_BANK_SPECIAL_BASE 0x43A8E80ull
+#define DCORE1_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM5_BANK_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM5_RTR_BASE 0x43A9000ull
+#define DCORE1_SRAM5_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM5_RTR_SECTION 0xE800
+#define DCORE1_SRAM5_RTR_SPECIAL_BASE 0x43A9E80ull
+#define DCORE1_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM5_RTR_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43AA000ull
+#define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43AA100ull
+#define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43AA200ull
+#define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43AA300ull
+#define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43AA400ull
+#define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43AA500ull
+#define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43AA600ull
+#define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43AA700ull
+#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43AA780ull
+#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43AA800ull
+#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43AA880ull
+#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43AA900ull
+#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43AA980ull
+#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43AAA00ull
+#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43AAA80ull
+#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE1_SRAM5_DBG_CNT_SPECIAL_BASE 0x43AAE80ull
+#define DCORE1_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE1_SRAM6_BANK_BASE 0x43B0000ull
+#define DCORE1_SRAM6_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM6_BANK_SECTION 0xE800
+#define DCORE1_SRAM6_BANK_SPECIAL_BASE 0x43B0E80ull
+#define DCORE1_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM6_BANK_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM6_RTR_BASE 0x43B1000ull
+#define DCORE1_SRAM6_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM6_RTR_SECTION 0xE800
+#define DCORE1_SRAM6_RTR_SPECIAL_BASE 0x43B1E80ull
+#define DCORE1_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM6_RTR_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43B2000ull
+#define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43B2100ull
+#define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43B2200ull
+#define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43B2300ull
+#define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43B2400ull
+#define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43B2500ull
+#define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43B2600ull
+#define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43B2700ull
+#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43B2780ull
+#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43B2800ull
+#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43B2880ull
+#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43B2900ull
+#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43B2980ull
+#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43B2A00ull
+#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43B2A80ull
+#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE1_SRAM6_DBG_CNT_SPECIAL_BASE 0x43B2E80ull
+#define DCORE1_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE1_SRAM7_BANK_BASE 0x43B8000ull
+#define DCORE1_SRAM7_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM7_BANK_SECTION 0xE800
+#define DCORE1_SRAM7_BANK_SPECIAL_BASE 0x43B8E80ull
+#define DCORE1_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM7_BANK_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM7_RTR_BASE 0x43B9000ull
+#define DCORE1_SRAM7_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM7_RTR_SECTION 0xE800
+#define DCORE1_SRAM7_RTR_SPECIAL_BASE 0x43B9E80ull
+#define DCORE1_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM7_RTR_SPECIAL_SECTION 0x1800
+#define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43BA000ull
+#define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43BA100ull
+#define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43BA200ull
+#define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43BA300ull
+#define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43BA400ull
+#define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43BA500ull
+#define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43BA600ull
+#define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43BA700ull
+#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43BA780ull
+#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43BA800ull
+#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43BA880ull
+#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43BA900ull
+#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43BA980ull
+#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43BAA00ull
+#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43BAA80ull
+#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE1_SRAM7_DBG_CNT_SPECIAL_BASE 0x43BAE80ull
+#define DCORE1_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE1_EDMA0_QM_DCCM_BASE 0x43C0000ull
+#define DCORE1_EDMA0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_EDMA0_QM_DCCM_SECTION 0x8000
+#define DCORE1_EDMA0_QM_ARC_AUX_BASE 0x43C8000ull
+#define DCORE1_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_QM_ARC_AUX_SECTION 0xE800
+#define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x43C8E80ull
+#define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE1_EDMA0_QM_BASE 0x43CA000ull
+#define DCORE1_EDMA0_QM_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_QM_SECTION 0x9000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x43CA900ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x43CA908ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x43CA910ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x43CA918ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x43CA920ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x43CA928ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x43CA930ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x43CA938ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x43CA940ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x43CA948ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x43CA950ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x43CA958ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x43CA960ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x43CA968ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x43CA970ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x43CA978ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_EDMA0_QM_AXUSER_SECURED_BASE 0x43CAB00ull
+#define DCORE1_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_EDMA0_QM_AXUSER_NONSECURED_BASE 0x43CAB80ull
+#define DCORE1_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_EDMA0_QM_DBG_HBW_BASE 0x43CAC00ull
+#define DCORE1_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA0_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_EDMA0_QM_DBG_LBW_BASE 0x43CAC80ull
+#define DCORE1_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA0_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_EDMA0_QM_CGM_BASE 0x43CAD80ull
+#define DCORE1_EDMA0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_EDMA0_QM_CGM_SECTION 0x1000
+#define DCORE1_EDMA0_QM_SPECIAL_BASE 0x43CAE80ull
+#define DCORE1_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA0_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_EDMA0_CORE_BASE 0x43CB000ull
+#define DCORE1_EDMA0_CORE_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_CORE_SECTION 0x8000
+#define DCORE1_EDMA0_CORE_CTX_AXUSER_BASE 0x43CB800ull
+#define DCORE1_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000
+#define DCORE1_EDMA0_CORE_CTX_BASE 0x43CB860ull
+#define DCORE1_EDMA0_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE1_EDMA0_CORE_CTX_SECTION 0x5A00
+#define DCORE1_EDMA0_CORE_KDMA_CGM_BASE 0x43CBE00ull
+#define DCORE1_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE1_EDMA0_CORE_KDMA_CGM_SECTION 0x8000
+#define DCORE1_EDMA0_CORE_SPECIAL_BASE 0x43CBE80ull
+#define DCORE1_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA0_CORE_SPECIAL_SECTION 0x1800
+#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x43CC000ull
+#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x43CC200ull
+#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x43CC400ull
+#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x43CC600ull
+#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x43CC800ull
+#define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_EDMA0_MSTR_IF_AXUSER_BASE 0x43CCA80ull
+#define DCORE1_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_EDMA0_MSTR_IF_DBG_HBW_BASE 0x43CCB00ull
+#define DCORE1_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_EDMA0_MSTR_IF_DBG_LBW_BASE 0x43CCB80ull
+#define DCORE1_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_EDMA0_MSTR_IF_CORE_HBW_BASE 0x43CCC00ull
+#define DCORE1_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_EDMA0_MSTR_IF_CORE_LBW_BASE 0x43CCD80ull
+#define DCORE1_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_EDMA0_MSTR_IF_SPECIAL_BASE 0x43CCE80ull
+#define DCORE1_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE1_EDMA1_QM_DCCM_BASE 0x43D0000ull
+#define DCORE1_EDMA1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_EDMA1_QM_DCCM_SECTION 0x8000
+#define DCORE1_EDMA1_QM_ARC_AUX_BASE 0x43D8000ull
+#define DCORE1_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_QM_ARC_AUX_SECTION 0xE800
+#define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x43D8E80ull
+#define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE1_EDMA1_QM_BASE 0x43DA000ull
+#define DCORE1_EDMA1_QM_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_QM_SECTION 0x9000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x43DA900ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x43DA908ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x43DA910ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x43DA918ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x43DA920ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x43DA928ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x43DA930ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x43DA938ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x43DA940ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x43DA948ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x43DA950ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x43DA958ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x43DA960ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x43DA968ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x43DA970ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x43DA978ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE1_EDMA1_QM_AXUSER_SECURED_BASE 0x43DAB00ull
+#define DCORE1_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE1_EDMA1_QM_AXUSER_NONSECURED_BASE 0x43DAB80ull
+#define DCORE1_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE1_EDMA1_QM_DBG_HBW_BASE 0x43DAC00ull
+#define DCORE1_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA1_QM_DBG_HBW_SECTION 0x8000
+#define DCORE1_EDMA1_QM_DBG_LBW_BASE 0x43DAC80ull
+#define DCORE1_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA1_QM_DBG_LBW_SECTION 0x1000
+#define DCORE1_EDMA1_QM_CGM_BASE 0x43DAD80ull
+#define DCORE1_EDMA1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_EDMA1_QM_CGM_SECTION 0x1000
+#define DCORE1_EDMA1_QM_SPECIAL_BASE 0x43DAE80ull
+#define DCORE1_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA1_QM_SPECIAL_SECTION 0x1800
+#define DCORE1_EDMA1_CORE_BASE 0x43DB000ull
+#define DCORE1_EDMA1_CORE_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_CORE_SECTION 0x8000
+#define DCORE1_EDMA1_CORE_CTX_AXUSER_BASE 0x43DB800ull
+#define DCORE1_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000
+#define DCORE1_EDMA1_CORE_CTX_BASE 0x43DB860ull
+#define DCORE1_EDMA1_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE1_EDMA1_CORE_CTX_SECTION 0x5A00
+#define DCORE1_EDMA1_CORE_KDMA_CGM_BASE 0x43DBE00ull
+#define DCORE1_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE1_EDMA1_CORE_KDMA_CGM_SECTION 0x8000
+#define DCORE1_EDMA1_CORE_SPECIAL_BASE 0x43DBE80ull
+#define DCORE1_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA1_CORE_SPECIAL_SECTION 0x1800
+#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x43DC000ull
+#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x43DC200ull
+#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x43DC400ull
+#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x43DC600ull
+#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x43DC800ull
+#define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_EDMA1_MSTR_IF_AXUSER_BASE 0x43DCA80ull
+#define DCORE1_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_EDMA1_MSTR_IF_DBG_HBW_BASE 0x43DCB00ull
+#define DCORE1_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_EDMA1_MSTR_IF_DBG_LBW_BASE 0x43DCB80ull
+#define DCORE1_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_EDMA1_MSTR_IF_CORE_HBW_BASE 0x43DCC00ull
+#define DCORE1_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_EDMA1_MSTR_IF_CORE_LBW_BASE 0x43DCD80ull
+#define DCORE1_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_EDMA1_MSTR_IF_SPECIAL_BASE 0x43DCE80ull
+#define DCORE1_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE1_DEC0_CMD_BASE 0x43E0000ull
+#define DCORE1_DEC0_CMD_MAX_OFFSET 0x1100
+#define DCORE1_DEC0_CMD_SECTION 0x1000
+#define DCORE1_DEC0_VSI_BASE 0x43E1000ull
+#define DCORE1_DEC0_VSI_MAX_OFFSET 0x6FC0
+#define DCORE1_DEC0_VSI_SECTION 0x1000
+#define DCORE1_DEC0_L2C_BASE 0x43E2000ull
+#define DCORE1_DEC0_L2C_MAX_OFFSET 0x39C0
+#define DCORE1_DEC0_L2C_SECTION 0x1000
+#define DCORE1_VDEC0_BRDG_CTRL_BASE 0x43E3000ull
+#define DCORE1_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_BRDG_CTRL_SECTION 0x8000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x43E3800ull
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x43E3900ull
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x43E3A00ull
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x43E3B00ull
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x43E3C00ull
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x43E3E80ull
+#define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE1_VDEC0_CTRL_BASE 0x43E4000ull
+#define DCORE1_VDEC0_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_CTRL_SECTION 0xE800
+#define DCORE1_VDEC0_CTRL_SPECIAL_BASE 0x43E4E80ull
+#define DCORE1_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_VDEC0_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x43E5000ull
+#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x43E5200ull
+#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x43E5400ull
+#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x43E5600ull
+#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x43E5800ull
+#define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_VDEC0_MSTR_IF_AXUSER_BASE 0x43E5A80ull
+#define DCORE1_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_VDEC0_MSTR_IF_DBG_HBW_BASE 0x43E5B00ull
+#define DCORE1_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_VDEC0_MSTR_IF_DBG_LBW_BASE 0x43E5B80ull
+#define DCORE1_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_VDEC0_MSTR_IF_CORE_HBW_BASE 0x43E5C00ull
+#define DCORE1_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_VDEC0_MSTR_IF_CORE_LBW_BASE 0x43E5D80ull
+#define DCORE1_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_VDEC0_MSTR_IF_SPECIAL_BASE 0x43E5E80ull
+#define DCORE1_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
+#define DCORE1_DEC1_CMD_BASE 0x43F0000ull
+#define DCORE1_DEC1_CMD_MAX_OFFSET 0x1100
+#define DCORE1_DEC1_CMD_SECTION 0x1000
+#define DCORE1_DEC1_VSI_BASE 0x43F1000ull
+#define DCORE1_DEC1_VSI_MAX_OFFSET 0x6FC0
+#define DCORE1_DEC1_VSI_SECTION 0x1000
+#define DCORE1_DEC1_L2C_BASE 0x43F2000ull
+#define DCORE1_DEC1_L2C_MAX_OFFSET 0x39C0
+#define DCORE1_DEC1_L2C_SECTION 0x1000
+#define DCORE1_VDEC1_BRDG_CTRL_BASE 0x43F3000ull
+#define DCORE1_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_BRDG_CTRL_SECTION 0x8000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x43F3800ull
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x43F3900ull
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x43F3A00ull
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x43F3B00ull
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x43F3C00ull
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x43F3E80ull
+#define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE1_VDEC1_CTRL_BASE 0x43F4000ull
+#define DCORE1_VDEC1_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_CTRL_SECTION 0xE800
+#define DCORE1_VDEC1_CTRL_SPECIAL_BASE 0x43F4E80ull
+#define DCORE1_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_VDEC1_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x43F5000ull
+#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x43F5200ull
+#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x43F5400ull
+#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x43F5600ull
+#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x43F5800ull
+#define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE1_VDEC1_MSTR_IF_AXUSER_BASE 0x43F5A80ull
+#define DCORE1_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE1_VDEC1_MSTR_IF_DBG_HBW_BASE 0x43F5B00ull
+#define DCORE1_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE1_VDEC1_MSTR_IF_DBG_LBW_BASE 0x43F5B80ull
+#define DCORE1_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE1_VDEC1_MSTR_IF_CORE_HBW_BASE 0x43F5C00ull
+#define DCORE1_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE1_VDEC1_MSTR_IF_CORE_LBW_BASE 0x43F5D80ull
+#define DCORE1_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE1_VDEC1_MSTR_IF_SPECIAL_BASE 0x43F5E80ull
+#define DCORE1_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180
+#define DCORE2_TPC0_QM_DCCM_BASE 0x4400000ull
+#define DCORE2_TPC0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC0_QM_DCCM_SECTION 0x8000
+#define DCORE2_TPC0_QM_ARC_AUX_BASE 0x4408000ull
+#define DCORE2_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_QM_ARC_AUX_SECTION 0xE800
+#define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4408E80ull
+#define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE2_TPC0_QM_BASE 0x440A000ull
+#define DCORE2_TPC0_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_QM_SECTION 0x9000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x440A900ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x440A908ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x440A910ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x440A918ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x440A920ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x440A928ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x440A930ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x440A938ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x440A940ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x440A948ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x440A950ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x440A958ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x440A960ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x440A968ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x440A970ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x440A978ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_TPC0_QM_AXUSER_SECURED_BASE 0x440AB00ull
+#define DCORE2_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_TPC0_QM_AXUSER_NONSECURED_BASE 0x440AB80ull
+#define DCORE2_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_TPC0_QM_DBG_HBW_BASE 0x440AC00ull
+#define DCORE2_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC0_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC0_QM_DBG_LBW_BASE 0x440AC80ull
+#define DCORE2_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC0_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_TPC0_QM_CGM_BASE 0x440AD80ull
+#define DCORE2_TPC0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC0_QM_CGM_SECTION 0x1000
+#define DCORE2_TPC0_QM_SPECIAL_BASE 0x440AE80ull
+#define DCORE2_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x440B000ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC0_CFG_BASE 0x440B000ull
+#define DCORE2_TPC0_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_CFG_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x440B050ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x440B0A0ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x440B0F0ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x440B140ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x440B190ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x440B1E0ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x440B230ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x440B280ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x440B2D0ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x440B320ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x440B370ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x440B3C0ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x440B410ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x440B460ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x440B4B0ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x440B500ull
+#define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC0_CFG_KERNEL_BASE 0x440B508ull
+#define DCORE2_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC0_CFG_KERNEL_SECTION 0xD400
+#define DCORE2_TPC0_CFG_QM_TENSOR_0_BASE 0x440B5DCull
+#define DCORE2_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_1_BASE 0x440B62Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_2_BASE 0x440B67Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_3_BASE 0x440B6CCull
+#define DCORE2_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_4_BASE 0x440B71Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_5_BASE 0x440B76Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_6_BASE 0x440B7BCull
+#define DCORE2_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_7_BASE 0x440B80Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_8_BASE 0x440B85Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_9_BASE 0x440B8ACull
+#define DCORE2_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_10_BASE 0x440B8FCull
+#define DCORE2_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_11_BASE 0x440B94Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_12_BASE 0x440B99Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_13_BASE 0x440B9ECull
+#define DCORE2_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_14_BASE 0x440BA3Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_15_BASE 0x440BA8Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x440BADCull
+#define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC0_CFG_QM_BASE 0x440BAE4ull
+#define DCORE2_TPC0_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC0_CFG_QM_SECTION 0x31C0
+#define DCORE2_TPC0_CFG_AXUSER_BASE 0x440BE00ull
+#define DCORE2_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_AXUSER_SECTION 0x8000
+#define DCORE2_TPC0_CFG_SPECIAL_BASE 0x440BE80ull
+#define DCORE2_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x440C000ull
+#define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x440C200ull
+#define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x440C400ull
+#define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x440C600ull
+#define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_TPC0_MSTR_IF_E2E_CRDT_BASE 0x440C800ull
+#define DCORE2_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_TPC0_MSTR_IF_AXUSER_BASE 0x440CA80ull
+#define DCORE2_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_TPC0_MSTR_IF_DBG_HBW_BASE 0x440CB00ull
+#define DCORE2_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC0_MSTR_IF_DBG_LBW_BASE 0x440CB80ull
+#define DCORE2_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_TPC0_MSTR_IF_CORE_HBW_BASE 0x440CC00ull
+#define DCORE2_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_TPC0_MSTR_IF_CORE_LBW_BASE 0x440CD80ull
+#define DCORE2_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_TPC0_MSTR_IF_SPECIAL_BASE 0x440CE80ull
+#define DCORE2_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE2_TPC1_QM_DCCM_BASE 0x4410000ull
+#define DCORE2_TPC1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC1_QM_DCCM_SECTION 0x8000
+#define DCORE2_TPC1_QM_ARC_AUX_BASE 0x4418000ull
+#define DCORE2_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_QM_ARC_AUX_SECTION 0xE800
+#define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4418E80ull
+#define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE2_TPC1_QM_BASE 0x441A000ull
+#define DCORE2_TPC1_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_QM_SECTION 0x9000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x441A900ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x441A908ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x441A910ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x441A918ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x441A920ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x441A928ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x441A930ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x441A938ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x441A940ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x441A948ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x441A950ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x441A958ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x441A960ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x441A968ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x441A970ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x441A978ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_TPC1_QM_AXUSER_SECURED_BASE 0x441AB00ull
+#define DCORE2_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_TPC1_QM_AXUSER_NONSECURED_BASE 0x441AB80ull
+#define DCORE2_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_TPC1_QM_DBG_HBW_BASE 0x441AC00ull
+#define DCORE2_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC1_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC1_QM_DBG_LBW_BASE 0x441AC80ull
+#define DCORE2_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC1_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_TPC1_QM_CGM_BASE 0x441AD80ull
+#define DCORE2_TPC1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC1_QM_CGM_SECTION 0x1000
+#define DCORE2_TPC1_QM_SPECIAL_BASE 0x441AE80ull
+#define DCORE2_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x441B000ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC1_CFG_BASE 0x441B000ull
+#define DCORE2_TPC1_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_CFG_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x441B050ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x441B0A0ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x441B0F0ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x441B140ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x441B190ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x441B1E0ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x441B230ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x441B280ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x441B2D0ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x441B320ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x441B370ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x441B3C0ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x441B410ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x441B460ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x441B4B0ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x441B500ull
+#define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC1_CFG_KERNEL_BASE 0x441B508ull
+#define DCORE2_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC1_CFG_KERNEL_SECTION 0xD400
+#define DCORE2_TPC1_CFG_QM_TENSOR_0_BASE 0x441B5DCull
+#define DCORE2_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_1_BASE 0x441B62Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_2_BASE 0x441B67Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_3_BASE 0x441B6CCull
+#define DCORE2_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_4_BASE 0x441B71Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_5_BASE 0x441B76Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_6_BASE 0x441B7BCull
+#define DCORE2_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_7_BASE 0x441B80Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_8_BASE 0x441B85Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_9_BASE 0x441B8ACull
+#define DCORE2_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_10_BASE 0x441B8FCull
+#define DCORE2_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_11_BASE 0x441B94Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_12_BASE 0x441B99Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_13_BASE 0x441B9ECull
+#define DCORE2_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_14_BASE 0x441BA3Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_15_BASE 0x441BA8Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x441BADCull
+#define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC1_CFG_QM_BASE 0x441BAE4ull
+#define DCORE2_TPC1_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC1_CFG_QM_SECTION 0x31C0
+#define DCORE2_TPC1_CFG_AXUSER_BASE 0x441BE00ull
+#define DCORE2_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_AXUSER_SECTION 0x8000
+#define DCORE2_TPC1_CFG_SPECIAL_BASE 0x441BE80ull
+#define DCORE2_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x441C000ull
+#define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x441C200ull
+#define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x441C400ull
+#define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x441C600ull
+#define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_TPC1_MSTR_IF_E2E_CRDT_BASE 0x441C800ull
+#define DCORE2_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_TPC1_MSTR_IF_AXUSER_BASE 0x441CA80ull
+#define DCORE2_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_TPC1_MSTR_IF_DBG_HBW_BASE 0x441CB00ull
+#define DCORE2_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC1_MSTR_IF_DBG_LBW_BASE 0x441CB80ull
+#define DCORE2_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_TPC1_MSTR_IF_CORE_HBW_BASE 0x441CC00ull
+#define DCORE2_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_TPC1_MSTR_IF_CORE_LBW_BASE 0x441CD80ull
+#define DCORE2_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_TPC1_MSTR_IF_SPECIAL_BASE 0x441CE80ull
+#define DCORE2_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE2_TPC2_QM_DCCM_BASE 0x4420000ull
+#define DCORE2_TPC2_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC2_QM_DCCM_SECTION 0x8000
+#define DCORE2_TPC2_QM_ARC_AUX_BASE 0x4428000ull
+#define DCORE2_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_QM_ARC_AUX_SECTION 0xE800
+#define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4428E80ull
+#define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE2_TPC2_QM_BASE 0x442A000ull
+#define DCORE2_TPC2_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_QM_SECTION 0x9000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x442A900ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x442A908ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x442A910ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x442A918ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x442A920ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x442A928ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x442A930ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x442A938ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x442A940ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x442A948ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x442A950ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x442A958ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x442A960ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x442A968ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x442A970ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x442A978ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_TPC2_QM_AXUSER_SECURED_BASE 0x442AB00ull
+#define DCORE2_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_TPC2_QM_AXUSER_NONSECURED_BASE 0x442AB80ull
+#define DCORE2_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_TPC2_QM_DBG_HBW_BASE 0x442AC00ull
+#define DCORE2_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC2_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC2_QM_DBG_LBW_BASE 0x442AC80ull
+#define DCORE2_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC2_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_TPC2_QM_CGM_BASE 0x442AD80ull
+#define DCORE2_TPC2_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC2_QM_CGM_SECTION 0x1000
+#define DCORE2_TPC2_QM_SPECIAL_BASE 0x442AE80ull
+#define DCORE2_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x442B000ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC2_CFG_BASE 0x442B000ull
+#define DCORE2_TPC2_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_CFG_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x442B050ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x442B0A0ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x442B0F0ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x442B140ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x442B190ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x442B1E0ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x442B230ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x442B280ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x442B2D0ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x442B320ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x442B370ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x442B3C0ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x442B410ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x442B460ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x442B4B0ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x442B500ull
+#define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC2_CFG_KERNEL_BASE 0x442B508ull
+#define DCORE2_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC2_CFG_KERNEL_SECTION 0xD400
+#define DCORE2_TPC2_CFG_QM_TENSOR_0_BASE 0x442B5DCull
+#define DCORE2_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_1_BASE 0x442B62Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_2_BASE 0x442B67Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_3_BASE 0x442B6CCull
+#define DCORE2_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_4_BASE 0x442B71Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_5_BASE 0x442B76Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_6_BASE 0x442B7BCull
+#define DCORE2_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_7_BASE 0x442B80Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_8_BASE 0x442B85Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_9_BASE 0x442B8ACull
+#define DCORE2_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_10_BASE 0x442B8FCull
+#define DCORE2_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_11_BASE 0x442B94Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_12_BASE 0x442B99Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_13_BASE 0x442B9ECull
+#define DCORE2_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_14_BASE 0x442BA3Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_15_BASE 0x442BA8Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x442BADCull
+#define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC2_CFG_QM_BASE 0x442BAE4ull
+#define DCORE2_TPC2_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC2_CFG_QM_SECTION 0x31C0
+#define DCORE2_TPC2_CFG_AXUSER_BASE 0x442BE00ull
+#define DCORE2_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_AXUSER_SECTION 0x8000
+#define DCORE2_TPC2_CFG_SPECIAL_BASE 0x442BE80ull
+#define DCORE2_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x442C000ull
+#define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x442C200ull
+#define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x442C400ull
+#define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x442C600ull
+#define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_TPC2_MSTR_IF_E2E_CRDT_BASE 0x442C800ull
+#define DCORE2_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_TPC2_MSTR_IF_AXUSER_BASE 0x442CA80ull
+#define DCORE2_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_TPC2_MSTR_IF_DBG_HBW_BASE 0x442CB00ull
+#define DCORE2_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC2_MSTR_IF_DBG_LBW_BASE 0x442CB80ull
+#define DCORE2_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_TPC2_MSTR_IF_CORE_HBW_BASE 0x442CC00ull
+#define DCORE2_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_TPC2_MSTR_IF_CORE_LBW_BASE 0x442CD80ull
+#define DCORE2_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_TPC2_MSTR_IF_SPECIAL_BASE 0x442CE80ull
+#define DCORE2_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE2_TPC3_QM_DCCM_BASE 0x4430000ull
+#define DCORE2_TPC3_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC3_QM_DCCM_SECTION 0x8000
+#define DCORE2_TPC3_QM_ARC_AUX_BASE 0x4438000ull
+#define DCORE2_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_QM_ARC_AUX_SECTION 0xE800
+#define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4438E80ull
+#define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE2_TPC3_QM_BASE 0x443A000ull
+#define DCORE2_TPC3_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_QM_SECTION 0x9000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x443A900ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x443A908ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x443A910ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x443A918ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x443A920ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x443A928ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x443A930ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x443A938ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x443A940ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x443A948ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x443A950ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x443A958ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x443A960ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x443A968ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x443A970ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x443A978ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_TPC3_QM_AXUSER_SECURED_BASE 0x443AB00ull
+#define DCORE2_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_TPC3_QM_AXUSER_NONSECURED_BASE 0x443AB80ull
+#define DCORE2_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_TPC3_QM_DBG_HBW_BASE 0x443AC00ull
+#define DCORE2_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC3_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC3_QM_DBG_LBW_BASE 0x443AC80ull
+#define DCORE2_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC3_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_TPC3_QM_CGM_BASE 0x443AD80ull
+#define DCORE2_TPC3_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC3_QM_CGM_SECTION 0x1000
+#define DCORE2_TPC3_QM_SPECIAL_BASE 0x443AE80ull
+#define DCORE2_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x443B000ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC3_CFG_BASE 0x443B000ull
+#define DCORE2_TPC3_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_CFG_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x443B050ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x443B0A0ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x443B0F0ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x443B140ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x443B190ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x443B1E0ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x443B230ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x443B280ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x443B2D0ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x443B320ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x443B370ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x443B3C0ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x443B410ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x443B460ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x443B4B0ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x443B500ull
+#define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC3_CFG_KERNEL_BASE 0x443B508ull
+#define DCORE2_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC3_CFG_KERNEL_SECTION 0xD400
+#define DCORE2_TPC3_CFG_QM_TENSOR_0_BASE 0x443B5DCull
+#define DCORE2_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_1_BASE 0x443B62Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_2_BASE 0x443B67Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_3_BASE 0x443B6CCull
+#define DCORE2_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_4_BASE 0x443B71Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_5_BASE 0x443B76Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_6_BASE 0x443B7BCull
+#define DCORE2_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_7_BASE 0x443B80Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_8_BASE 0x443B85Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_9_BASE 0x443B8ACull
+#define DCORE2_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_10_BASE 0x443B8FCull
+#define DCORE2_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_11_BASE 0x443B94Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_12_BASE 0x443B99Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_13_BASE 0x443B9ECull
+#define DCORE2_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_14_BASE 0x443BA3Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_15_BASE 0x443BA8Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x443BADCull
+#define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC3_CFG_QM_BASE 0x443BAE4ull
+#define DCORE2_TPC3_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC3_CFG_QM_SECTION 0x31C0
+#define DCORE2_TPC3_CFG_AXUSER_BASE 0x443BE00ull
+#define DCORE2_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_AXUSER_SECTION 0x8000
+#define DCORE2_TPC3_CFG_SPECIAL_BASE 0x443BE80ull
+#define DCORE2_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x443C000ull
+#define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x443C200ull
+#define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x443C400ull
+#define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x443C600ull
+#define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_TPC3_MSTR_IF_E2E_CRDT_BASE 0x443C800ull
+#define DCORE2_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_TPC3_MSTR_IF_AXUSER_BASE 0x443CA80ull
+#define DCORE2_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_TPC3_MSTR_IF_DBG_HBW_BASE 0x443CB00ull
+#define DCORE2_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC3_MSTR_IF_DBG_LBW_BASE 0x443CB80ull
+#define DCORE2_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_TPC3_MSTR_IF_CORE_HBW_BASE 0x443CC00ull
+#define DCORE2_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_TPC3_MSTR_IF_CORE_LBW_BASE 0x443CD80ull
+#define DCORE2_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_TPC3_MSTR_IF_SPECIAL_BASE 0x443CE80ull
+#define DCORE2_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE2_TPC4_QM_DCCM_BASE 0x4440000ull
+#define DCORE2_TPC4_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC4_QM_DCCM_SECTION 0x8000
+#define DCORE2_TPC4_QM_ARC_AUX_BASE 0x4448000ull
+#define DCORE2_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_QM_ARC_AUX_SECTION 0xE800
+#define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4448E80ull
+#define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE2_TPC4_QM_BASE 0x444A000ull
+#define DCORE2_TPC4_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_QM_SECTION 0x9000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x444A900ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x444A908ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x444A910ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x444A918ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x444A920ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x444A928ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x444A930ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x444A938ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x444A940ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x444A948ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x444A950ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x444A958ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x444A960ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x444A968ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x444A970ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x444A978ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_TPC4_QM_AXUSER_SECURED_BASE 0x444AB00ull
+#define DCORE2_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_TPC4_QM_AXUSER_NONSECURED_BASE 0x444AB80ull
+#define DCORE2_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_TPC4_QM_DBG_HBW_BASE 0x444AC00ull
+#define DCORE2_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC4_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC4_QM_DBG_LBW_BASE 0x444AC80ull
+#define DCORE2_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC4_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_TPC4_QM_CGM_BASE 0x444AD80ull
+#define DCORE2_TPC4_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC4_QM_CGM_SECTION 0x1000
+#define DCORE2_TPC4_QM_SPECIAL_BASE 0x444AE80ull
+#define DCORE2_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x444B000ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC4_CFG_BASE 0x444B000ull
+#define DCORE2_TPC4_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_CFG_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x444B050ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x444B0A0ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x444B0F0ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x444B140ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x444B190ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x444B1E0ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x444B230ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x444B280ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x444B2D0ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x444B320ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x444B370ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x444B3C0ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x444B410ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x444B460ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x444B4B0ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x444B500ull
+#define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC4_CFG_KERNEL_BASE 0x444B508ull
+#define DCORE2_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC4_CFG_KERNEL_SECTION 0xD400
+#define DCORE2_TPC4_CFG_QM_TENSOR_0_BASE 0x444B5DCull
+#define DCORE2_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_1_BASE 0x444B62Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_2_BASE 0x444B67Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_3_BASE 0x444B6CCull
+#define DCORE2_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_4_BASE 0x444B71Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_5_BASE 0x444B76Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_6_BASE 0x444B7BCull
+#define DCORE2_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_7_BASE 0x444B80Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_8_BASE 0x444B85Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_9_BASE 0x444B8ACull
+#define DCORE2_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_10_BASE 0x444B8FCull
+#define DCORE2_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_11_BASE 0x444B94Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_12_BASE 0x444B99Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_13_BASE 0x444B9ECull
+#define DCORE2_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_14_BASE 0x444BA3Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_15_BASE 0x444BA8Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x444BADCull
+#define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC4_CFG_QM_BASE 0x444BAE4ull
+#define DCORE2_TPC4_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC4_CFG_QM_SECTION 0x31C0
+#define DCORE2_TPC4_CFG_AXUSER_BASE 0x444BE00ull
+#define DCORE2_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_AXUSER_SECTION 0x8000
+#define DCORE2_TPC4_CFG_SPECIAL_BASE 0x444BE80ull
+#define DCORE2_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x444C000ull
+#define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x444C200ull
+#define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x444C400ull
+#define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x444C600ull
+#define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_TPC4_MSTR_IF_E2E_CRDT_BASE 0x444C800ull
+#define DCORE2_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_TPC4_MSTR_IF_AXUSER_BASE 0x444CA80ull
+#define DCORE2_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_TPC4_MSTR_IF_DBG_HBW_BASE 0x444CB00ull
+#define DCORE2_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC4_MSTR_IF_DBG_LBW_BASE 0x444CB80ull
+#define DCORE2_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_TPC4_MSTR_IF_CORE_HBW_BASE 0x444CC00ull
+#define DCORE2_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_TPC4_MSTR_IF_CORE_LBW_BASE 0x444CD80ull
+#define DCORE2_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_TPC4_MSTR_IF_SPECIAL_BASE 0x444CE80ull
+#define DCORE2_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE2_TPC5_QM_DCCM_BASE 0x4450000ull
+#define DCORE2_TPC5_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC5_QM_DCCM_SECTION 0x8000
+#define DCORE2_TPC5_QM_ARC_AUX_BASE 0x4458000ull
+#define DCORE2_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_QM_ARC_AUX_SECTION 0xE800
+#define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4458E80ull
+#define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE2_TPC5_QM_BASE 0x445A000ull
+#define DCORE2_TPC5_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_QM_SECTION 0x9000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x445A900ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x445A908ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x445A910ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x445A918ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x445A920ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x445A928ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x445A930ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x445A938ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x445A940ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x445A948ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x445A950ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x445A958ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x445A960ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x445A968ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x445A970ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x445A978ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_TPC5_QM_AXUSER_SECURED_BASE 0x445AB00ull
+#define DCORE2_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_TPC5_QM_AXUSER_NONSECURED_BASE 0x445AB80ull
+#define DCORE2_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_TPC5_QM_DBG_HBW_BASE 0x445AC00ull
+#define DCORE2_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC5_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC5_QM_DBG_LBW_BASE 0x445AC80ull
+#define DCORE2_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC5_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_TPC5_QM_CGM_BASE 0x445AD80ull
+#define DCORE2_TPC5_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC5_QM_CGM_SECTION 0x1000
+#define DCORE2_TPC5_QM_SPECIAL_BASE 0x445AE80ull
+#define DCORE2_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x445B000ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC5_CFG_BASE 0x445B000ull
+#define DCORE2_TPC5_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_CFG_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x445B050ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x445B0A0ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x445B0F0ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x445B140ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x445B190ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x445B1E0ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x445B230ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x445B280ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x445B2D0ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x445B320ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x445B370ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x445B3C0ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x445B410ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x445B460ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x445B4B0ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x445B500ull
+#define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC5_CFG_KERNEL_BASE 0x445B508ull
+#define DCORE2_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC5_CFG_KERNEL_SECTION 0xD400
+#define DCORE2_TPC5_CFG_QM_TENSOR_0_BASE 0x445B5DCull
+#define DCORE2_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_1_BASE 0x445B62Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_2_BASE 0x445B67Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_3_BASE 0x445B6CCull
+#define DCORE2_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_4_BASE 0x445B71Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_5_BASE 0x445B76Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_6_BASE 0x445B7BCull
+#define DCORE2_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_7_BASE 0x445B80Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_8_BASE 0x445B85Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_9_BASE 0x445B8ACull
+#define DCORE2_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_10_BASE 0x445B8FCull
+#define DCORE2_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_11_BASE 0x445B94Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_12_BASE 0x445B99Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_13_BASE 0x445B9ECull
+#define DCORE2_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_14_BASE 0x445BA3Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_15_BASE 0x445BA8Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x445BADCull
+#define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE2_TPC5_CFG_QM_BASE 0x445BAE4ull
+#define DCORE2_TPC5_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC5_CFG_QM_SECTION 0x31C0
+#define DCORE2_TPC5_CFG_AXUSER_BASE 0x445BE00ull
+#define DCORE2_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_AXUSER_SECTION 0x8000
+#define DCORE2_TPC5_CFG_SPECIAL_BASE 0x445BE80ull
+#define DCORE2_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_CFG_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x445C000ull
+#define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x445C200ull
+#define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x445C400ull
+#define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x445C600ull
+#define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_TPC5_MSTR_IF_E2E_CRDT_BASE 0x445C800ull
+#define DCORE2_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_TPC5_MSTR_IF_AXUSER_BASE 0x445CA80ull
+#define DCORE2_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_TPC5_MSTR_IF_DBG_HBW_BASE 0x445CB00ull
+#define DCORE2_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_TPC5_MSTR_IF_DBG_LBW_BASE 0x445CB80ull
+#define DCORE2_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_TPC5_MSTR_IF_CORE_HBW_BASE 0x445CC00ull
+#define DCORE2_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_TPC5_MSTR_IF_CORE_LBW_BASE 0x445CD80ull
+#define DCORE2_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_TPC5_MSTR_IF_SPECIAL_BASE 0x445CE80ull
+#define DCORE2_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180
+#define DCORE2_HMMU0_MMU_BASE 0x4480000ull
+#define DCORE2_HMMU0_MMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_MMU_SECTION 0xE800
+#define DCORE2_HMMU0_MMU_SPECIAL_BASE 0x4480E80ull
+#define DCORE2_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU0_MMU_SPECIAL_SECTION 0x1800
+#define DCORE2_HMMU0_STLB_BASE 0x4481000ull
+#define DCORE2_HMMU0_STLB_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_STLB_SECTION 0xE800
+#define DCORE2_HMMU0_STLB_SPECIAL_BASE 0x4481E80ull
+#define DCORE2_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU0_STLB_SPECIAL_SECTION 0x1180
+#define DCORE2_HMMU0_SCRAMB_OUT_BASE 0x4483000ull
+#define DCORE2_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_SCRAMB_OUT_SECTION 0xE800
+#define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4483E80ull
+#define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4484000ull
+#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4484200ull
+#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4484400ull
+#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4484600ull
+#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4484800ull
+#define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_HMMU0_MSTR_IF_AXUSER_BASE 0x4484A80ull
+#define DCORE2_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4484B00ull
+#define DCORE2_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4484B80ull
+#define DCORE2_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4484C00ull
+#define DCORE2_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4484D80ull
+#define DCORE2_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_HMMU0_MSTR_IF_SPECIAL_BASE 0x4484E80ull
+#define DCORE2_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE2_HMMU1_MMU_BASE 0x4490000ull
+#define DCORE2_HMMU1_MMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_MMU_SECTION 0xE800
+#define DCORE2_HMMU1_MMU_SPECIAL_BASE 0x4490E80ull
+#define DCORE2_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU1_MMU_SPECIAL_SECTION 0x1800
+#define DCORE2_HMMU1_STLB_BASE 0x4491000ull
+#define DCORE2_HMMU1_STLB_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_STLB_SECTION 0xE800
+#define DCORE2_HMMU1_STLB_SPECIAL_BASE 0x4491E80ull
+#define DCORE2_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU1_STLB_SPECIAL_SECTION 0x1180
+#define DCORE2_HMMU1_SCRAMB_OUT_BASE 0x4493000ull
+#define DCORE2_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_SCRAMB_OUT_SECTION 0xE800
+#define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4493E80ull
+#define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4494000ull
+#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4494200ull
+#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4494400ull
+#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4494600ull
+#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4494800ull
+#define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_HMMU1_MSTR_IF_AXUSER_BASE 0x4494A80ull
+#define DCORE2_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4494B00ull
+#define DCORE2_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4494B80ull
+#define DCORE2_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4494C00ull
+#define DCORE2_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4494D80ull
+#define DCORE2_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_HMMU1_MSTR_IF_SPECIAL_BASE 0x4494E80ull
+#define DCORE2_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE2_HMMU2_MMU_BASE 0x44A0000ull
+#define DCORE2_HMMU2_MMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_MMU_SECTION 0xE800
+#define DCORE2_HMMU2_MMU_SPECIAL_BASE 0x44A0E80ull
+#define DCORE2_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU2_MMU_SPECIAL_SECTION 0x1800
+#define DCORE2_HMMU2_STLB_BASE 0x44A1000ull
+#define DCORE2_HMMU2_STLB_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_STLB_SECTION 0xE800
+#define DCORE2_HMMU2_STLB_SPECIAL_BASE 0x44A1E80ull
+#define DCORE2_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU2_STLB_SPECIAL_SECTION 0x1180
+#define DCORE2_HMMU2_SCRAMB_OUT_BASE 0x44A3000ull
+#define DCORE2_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_SCRAMB_OUT_SECTION 0xE800
+#define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x44A3E80ull
+#define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x44A4000ull
+#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x44A4200ull
+#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x44A4400ull
+#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x44A4600ull
+#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x44A4800ull
+#define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_HMMU2_MSTR_IF_AXUSER_BASE 0x44A4A80ull
+#define DCORE2_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_HMMU2_MSTR_IF_DBG_HBW_BASE 0x44A4B00ull
+#define DCORE2_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_HMMU2_MSTR_IF_DBG_LBW_BASE 0x44A4B80ull
+#define DCORE2_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_HMMU2_MSTR_IF_CORE_HBW_BASE 0x44A4C00ull
+#define DCORE2_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_HMMU2_MSTR_IF_CORE_LBW_BASE 0x44A4D80ull
+#define DCORE2_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_HMMU2_MSTR_IF_SPECIAL_BASE 0x44A4E80ull
+#define DCORE2_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE2_HMMU3_MMU_BASE 0x44B0000ull
+#define DCORE2_HMMU3_MMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_MMU_SECTION 0xE800
+#define DCORE2_HMMU3_MMU_SPECIAL_BASE 0x44B0E80ull
+#define DCORE2_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU3_MMU_SPECIAL_SECTION 0x1800
+#define DCORE2_HMMU3_STLB_BASE 0x44B1000ull
+#define DCORE2_HMMU3_STLB_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_STLB_SECTION 0xE800
+#define DCORE2_HMMU3_STLB_SPECIAL_BASE 0x44B1E80ull
+#define DCORE2_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU3_STLB_SPECIAL_SECTION 0x1180
+#define DCORE2_HMMU3_SCRAMB_OUT_BASE 0x44B3000ull
+#define DCORE2_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_SCRAMB_OUT_SECTION 0xE800
+#define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x44B3E80ull
+#define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x44B4000ull
+#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x44B4200ull
+#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x44B4400ull
+#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x44B4600ull
+#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x44B4800ull
+#define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_HMMU3_MSTR_IF_AXUSER_BASE 0x44B4A80ull
+#define DCORE2_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_HMMU3_MSTR_IF_DBG_HBW_BASE 0x44B4B00ull
+#define DCORE2_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_HMMU3_MSTR_IF_DBG_LBW_BASE 0x44B4B80ull
+#define DCORE2_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_HMMU3_MSTR_IF_CORE_HBW_BASE 0x44B4C00ull
+#define DCORE2_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_HMMU3_MSTR_IF_CORE_LBW_BASE 0x44B4D80ull
+#define DCORE2_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_HMMU3_MSTR_IF_SPECIAL_BASE 0x44B4E80ull
+#define DCORE2_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE2_MME_QM_ARC_DCCM_BASE 0x44C0000ull
+#define DCORE2_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_MME_QM_ARC_DCCM_SECTION 0x8000
+#define DCORE2_MME_QM_ARC_AUX_BASE 0x44C8000ull
+#define DCORE2_MME_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_MME_QM_ARC_AUX_SECTION 0xE800
+#define DCORE2_MME_QM_ARC_AUX_SPECIAL_BASE 0x44C8E80ull
+#define DCORE2_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_QM_ARC_DUP_ENG_BASE 0x44C9000ull
+#define DCORE2_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000
+#define DCORE2_MME_QM_ARC_DUP_ENG_SECTION 0x9000
+#define DCORE2_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x44C9900ull
+#define DCORE2_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800
+#define DCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x44C9E80ull
+#define DCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_QM_BASE 0x44CA000ull
+#define DCORE2_MME_QM_MAX_OFFSET 0x1000
+#define DCORE2_MME_QM_SECTION 0x9000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x44CA900ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x44CA908ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x44CA910ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x44CA918ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x44CA920ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x44CA928ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x44CA930ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x44CA938ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x44CA940ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x44CA948ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x44CA950ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x44CA958ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x44CA960ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x44CA968ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x44CA970ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x44CA978ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_MME_QM_AXUSER_SECURED_BASE 0x44CAB00ull
+#define DCORE2_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_MME_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_MME_QM_AXUSER_NONSECURED_BASE 0x44CAB80ull
+#define DCORE2_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_MME_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_MME_QM_DBG_HBW_BASE 0x44CAC00ull
+#define DCORE2_MME_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_MME_QM_DBG_LBW_BASE 0x44CAC80ull
+#define DCORE2_MME_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_MME_QM_CGM_BASE 0x44CAD80ull
+#define DCORE2_MME_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_MME_QM_CGM_SECTION 0x1000
+#define DCORE2_MME_QM_SPECIAL_BASE 0x44CAE80ull
+#define DCORE2_MME_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_CTRL_LO_BASE 0x44CB000ull
+#define DCORE2_MME_CTRL_LO_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_LO_SECTION 0x8000
+#define DCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x44CB008ull
+#define DCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000
+#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x44CB028ull
+#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x44CB040ull
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x44CB098ull
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x44CB0F0ull
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x44CB15Cull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x44CB170ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x44CB184ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x44CB198ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x44CB1ACull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x44CB1C0ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x44CB1D4ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x44CB1E8ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x44CB1FCull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x44CB210ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x44CB22Cull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x44CB240ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x44CB254ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x44CB268ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x44CB280ull
+#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800
+#define DCORE2_MME_CTRL_LO_MME_AXUSER_BASE 0x44CBE00ull
+#define DCORE2_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000
+#define DCORE2_MME_CTRL_LO_SPECIAL_BASE 0x44CBE80ull
+#define DCORE2_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_LO_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_CTRL_HI_BASE 0x44CC000ull
+#define DCORE2_MME_CTRL_HI_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_HI_SECTION 0x8000
+#define DCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x44CC008ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000
+#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x44CC028ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x44CC040ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x44CC098ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x44CC0F0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x44CC15Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x44CC170ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x44CC184ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x44CC198ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x44CC1ACull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x44CC1C0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x44CC1D4ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x44CC1E8ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x44CC1FCull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x44CC210ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x44CC22Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x44CC240ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x44CC254ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x44CC268ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x44CC280ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800
+#define DCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x44CC308ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000
+#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x44CC328ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x44CC340ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x44CC398ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x44CC3F0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x44CC45Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x44CC470ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x44CC484ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x44CC498ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x44CC4ACull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x44CC4C0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x44CC4D4ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x44CC4E8ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x44CC4FCull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x44CC510ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x44CC52Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x44CC540ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x44CC554ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x44CC568ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x44CC580ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800
+#define DCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x44CC608ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000
+#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x44CC628ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x44CC640ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x44CC698ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x44CC6F0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x44CC75Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x44CC770ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x44CC784ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x44CC798ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x44CC7ACull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x44CC7C0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x44CC7D4ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x44CC7E8ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x44CC7FCull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x44CC810ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x44CC82Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x44CC840ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x44CC854ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x44CC868ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x44CC880ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800
+#define DCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x44CC908ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000
+#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x44CC928ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x44CC940ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x44CC998ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x44CC9F0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x44CCA5Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x44CCA70ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x44CCA84ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x44CCA98ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x44CCAACull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x44CCAC0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x44CCAD4ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x44CCAE8ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x44CCAFCull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x44CCB10ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x44CCB2Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x44CCB40ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x44CCB54ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x44CCB68ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x44CCB80ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000
+#define DCORE2_MME_CTRL_HI_SPECIAL_BASE 0x44CCE80ull
+#define DCORE2_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_HI_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_EU_BIST_BASE 0x44CD000ull
+#define DCORE2_MME_EU_BIST_MAX_OFFSET 0x1000
+#define DCORE2_MME_EU_BIST_SECTION 0xE800
+#define DCORE2_MME_EU_BIST_SPECIAL_BASE 0x44CDE80ull
+#define DCORE2_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_EU_BIST_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x44CE000ull
+#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x44CE200ull
+#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x44CE400ull
+#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x44CE600ull
+#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x44CE800ull
+#define DCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_MME_CTRL_MSTR_IF_AXUSER_BASE 0x44CEA80ull
+#define DCORE2_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x44CEB00ull
+#define DCORE2_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x44CEB80ull
+#define DCORE2_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x44CEC00ull
+#define DCORE2_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x44CED80ull
+#define DCORE2_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x44CEE80ull
+#define DCORE2_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_QM_ARC_ACP_ENG_BASE 0x44CF000ull
+#define DCORE2_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000
+#define DCORE2_MME_QM_ARC_ACP_ENG_SECTION 0xE800
+#define DCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x44CFE80ull
+#define DCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_SBTE0_BASE 0x44D0000ull
+#define DCORE2_MME_SBTE0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_SECTION 0xE800
+#define DCORE2_MME_SBTE0_SPECIAL_BASE 0x44D0E80ull
+#define DCORE2_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE0_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x44D1000ull
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x44D1200ull
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x44D1400ull
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x44D1600ull
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x44D1800ull
+#define DCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x44D1A80ull
+#define DCORE2_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x44D1B00ull
+#define DCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x44D1B80ull
+#define DCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x44D1C00ull
+#define DCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x44D1D80ull
+#define DCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x44D1E80ull
+#define DCORE2_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE2_MME_SBTE1_BASE 0x44D8000ull
+#define DCORE2_MME_SBTE1_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_SECTION 0xE800
+#define DCORE2_MME_SBTE1_SPECIAL_BASE 0x44D8E80ull
+#define DCORE2_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE1_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x44D9000ull
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x44D9200ull
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x44D9400ull
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x44D9600ull
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x44D9800ull
+#define DCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x44D9A80ull
+#define DCORE2_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x44D9B00ull
+#define DCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x44D9B80ull
+#define DCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x44D9C00ull
+#define DCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x44D9D80ull
+#define DCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x44D9E80ull
+#define DCORE2_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE2_MME_SBTE2_BASE 0x44E0000ull
+#define DCORE2_MME_SBTE2_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_SECTION 0xE800
+#define DCORE2_MME_SBTE2_SPECIAL_BASE 0x44E0E80ull
+#define DCORE2_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE2_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x44E1000ull
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x44E1200ull
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x44E1400ull
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x44E1600ull
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x44E1800ull
+#define DCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x44E1A80ull
+#define DCORE2_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x44E1B00ull
+#define DCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x44E1B80ull
+#define DCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x44E1C00ull
+#define DCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x44E1D80ull
+#define DCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x44E1E80ull
+#define DCORE2_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE2_MME_SBTE3_BASE 0x44E8000ull
+#define DCORE2_MME_SBTE3_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_SECTION 0xE800
+#define DCORE2_MME_SBTE3_SPECIAL_BASE 0x44E8E80ull
+#define DCORE2_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE3_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x44E9000ull
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x44E9200ull
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x44E9400ull
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x44E9600ull
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x44E9800ull
+#define DCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x44E9A80ull
+#define DCORE2_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x44E9B00ull
+#define DCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x44E9B80ull
+#define DCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x44E9C00ull
+#define DCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x44E9D80ull
+#define DCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x44E9E80ull
+#define DCORE2_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE2_MME_SBTE4_BASE 0x44F0000ull
+#define DCORE2_MME_SBTE4_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_SECTION 0xE800
+#define DCORE2_MME_SBTE4_SPECIAL_BASE 0x44F0E80ull
+#define DCORE2_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE4_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x44F1000ull
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x44F1200ull
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x44F1400ull
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x44F1600ull
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x44F1800ull
+#define DCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x44F1A80ull
+#define DCORE2_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x44F1B00ull
+#define DCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x44F1B80ull
+#define DCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x44F1C00ull
+#define DCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x44F1D80ull
+#define DCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x44F1E80ull
+#define DCORE2_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE2_MME_ACC_BASE 0x44F8000ull
+#define DCORE2_MME_ACC_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_SECTION 0xE800
+#define DCORE2_MME_ACC_SPECIAL_BASE 0x44F8E80ull
+#define DCORE2_MME_ACC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_ACC_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x44F9000ull
+#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x44F9200ull
+#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x44F9400ull
+#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x44F9600ull
+#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x44F9800ull
+#define DCORE2_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_MME_WB0_MSTR_IF_AXUSER_BASE 0x44F9A80ull
+#define DCORE2_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x44F9B00ull
+#define DCORE2_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x44F9B80ull
+#define DCORE2_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x44F9C00ull
+#define DCORE2_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x44F9D80ull
+#define DCORE2_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_MME_WB0_MSTR_IF_SPECIAL_BASE 0x44F9E80ull
+#define DCORE2_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x44FA000ull
+#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x44FA200ull
+#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x44FA400ull
+#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x44FA600ull
+#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x44FA800ull
+#define DCORE2_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_MME_WB1_MSTR_IF_AXUSER_BASE 0x44FAA80ull
+#define DCORE2_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x44FAB00ull
+#define DCORE2_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x44FAB80ull
+#define DCORE2_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x44FAC00ull
+#define DCORE2_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x44FAD80ull
+#define DCORE2_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_MME_WB1_MSTR_IF_SPECIAL_BASE 0x44FAE80ull
+#define DCORE2_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180
+#define DCORE2_SYNC_MNGR_OBJS_BASE 0x4500000ull
+#define DCORE2_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00
+#define DCORE2_SYNC_MNGR_OBJS_SECTION 0x1E000
+#define DCORE2_SYNC_MNGR_GLBL_BASE 0x451E000ull
+#define DCORE2_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000
+#define DCORE2_SYNC_MNGR_GLBL_SECTION 0xE800
+#define DCORE2_SYNC_MNGR_GLBL_SPECIAL_BASE 0x451EE80ull
+#define DCORE2_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x451F000ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x451F200ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x451F400ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x451F600ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x451F800ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x451FA80ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x451FB00ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x451FB80ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x451FC00ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x451FD80ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x451FE80ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE2_HIF0_BASE 0x4520000ull
+#define DCORE2_HIF0_MAX_OFFSET 0x1000
+#define DCORE2_HIF0_SECTION 0xE800
+#define DCORE2_HIF0_SPECIAL_BASE 0x4520E80ull
+#define DCORE2_HIF0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HIF0_SPECIAL_SECTION 0x3180
+#define DCORE2_HIF1_BASE 0x4524000ull
+#define DCORE2_HIF1_MAX_OFFSET 0x1000
+#define DCORE2_HIF1_SECTION 0xE800
+#define DCORE2_HIF1_SPECIAL_BASE 0x4524E80ull
+#define DCORE2_HIF1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HIF1_SPECIAL_SECTION 0x3180
+#define DCORE2_HIF2_BASE 0x4528000ull
+#define DCORE2_HIF2_MAX_OFFSET 0x1000
+#define DCORE2_HIF2_SECTION 0xE800
+#define DCORE2_HIF2_SPECIAL_BASE 0x4528E80ull
+#define DCORE2_HIF2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HIF2_SPECIAL_SECTION 0x3180
+#define DCORE2_HIF3_BASE 0x452C000ull
+#define DCORE2_HIF3_MAX_OFFSET 0x1000
+#define DCORE2_HIF3_SECTION 0xE800
+#define DCORE2_HIF3_SPECIAL_BASE 0x452CE80ull
+#define DCORE2_HIF3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HIF3_SPECIAL_SECTION 0x13180
+#define DCORE2_RTR0_CTRL_BASE 0x4540000ull
+#define DCORE2_RTR0_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR0_CTRL_SECTION 0xE800
+#define DCORE2_RTR0_CTRL_SPECIAL_BASE 0x4540E80ull
+#define DCORE2_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR0_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR0_H3_BASE 0x4541000ull
+#define DCORE2_RTR0_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR0_H3_SECTION 0xE800
+#define DCORE2_RTR0_H3_SPECIAL_BASE 0x4541E80ull
+#define DCORE2_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR0_H3_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4542000ull
+#define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4542200ull
+#define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4542400ull
+#define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4542600ull
+#define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4542800ull
+#define DCORE2_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_RTR0_MSTR_IF_AXUSER_BASE 0x4542A80ull
+#define DCORE2_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_RTR0_MSTR_IF_DBG_HBW_BASE 0x4542B00ull
+#define DCORE2_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_RTR0_MSTR_IF_DBG_LBW_BASE 0x4542B80ull
+#define DCORE2_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_RTR0_MSTR_IF_CORE_HBW_BASE 0x4542C00ull
+#define DCORE2_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_RTR0_MSTR_IF_CORE_LBW_BASE 0x4542D80ull
+#define DCORE2_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_RTR0_MSTR_IF_SPECIAL_BASE 0x4542E80ull
+#define DCORE2_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR0_ADD_DEC_HBW_BASE 0x4543000ull
+#define DCORE2_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR0_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE2_RTR0_ADD_DEC_LBW_BASE 0x4543400ull
+#define DCORE2_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR0_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE2_RTR0_ADD_DEC_SPECIAL_BASE 0x4543E80ull
+#define DCORE2_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR0_BASE 0x4544000ull
+#define DCORE2_RTR0_MAX_OFFSET 0x1000
+#define DCORE2_RTR0_SECTION 0x3000
+#define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4544300ull
+#define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4544340ull
+#define DCORE2_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4544380ull
+#define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR0_HBW_WR_RS_LL_STAT_BASE 0x45443C0ull
+#define DCORE2_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4544400ull
+#define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4544440ull
+#define DCORE2_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4544480ull
+#define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR0_LBW_WR_RS_LL_STAT_BASE 0x45444C0ull
+#define DCORE2_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR0_HBW_MFIFO_BASE 0x4544500ull
+#define DCORE2_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_HBW_MFIFO_SECTION 0x4000
+#define DCORE2_RTR0_E2E_RD_LL_STAT_BASE 0x4544540ull
+#define DCORE2_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR0_E2E_WR_LL_STAT_BASE 0x4544580ull
+#define DCORE2_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE2_RTR0_RTR_HBW_XACT_STAT_BASE 0x4544600ull
+#define DCORE2_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR0_RTR_LBW_XACT_STAT_BASE 0x4544680ull
+#define DCORE2_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR0_RTR_E2E_XACT_STAT_BASE 0x4544700ull
+#define DCORE2_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE2_RTR0_SPECIAL_BASE 0x4544E80ull
+#define DCORE2_RTR0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR0_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR0_DBG_ADDR_BASE 0x4545000ull
+#define DCORE2_RTR0_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR0_DBG_ADDR_SECTION 0xE800
+#define DCORE2_RTR0_DBG_ADDR_SPECIAL_BASE 0x4545E80ull
+#define DCORE2_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE2_RTR1_CTRL_BASE 0x4548000ull
+#define DCORE2_RTR1_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR1_CTRL_SECTION 0xE800
+#define DCORE2_RTR1_CTRL_SPECIAL_BASE 0x4548E80ull
+#define DCORE2_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR1_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR1_H3_BASE 0x4549000ull
+#define DCORE2_RTR1_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR1_H3_SECTION 0xE800
+#define DCORE2_RTR1_H3_SPECIAL_BASE 0x4549E80ull
+#define DCORE2_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR1_H3_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x454A000ull
+#define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x454A200ull
+#define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x454A400ull
+#define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x454A600ull
+#define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_RTR1_MSTR_IF_E2E_CRDT_BASE 0x454A800ull
+#define DCORE2_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_RTR1_MSTR_IF_AXUSER_BASE 0x454AA80ull
+#define DCORE2_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_RTR1_MSTR_IF_DBG_HBW_BASE 0x454AB00ull
+#define DCORE2_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_RTR1_MSTR_IF_DBG_LBW_BASE 0x454AB80ull
+#define DCORE2_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_RTR1_MSTR_IF_CORE_HBW_BASE 0x454AC00ull
+#define DCORE2_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_RTR1_MSTR_IF_CORE_LBW_BASE 0x454AD80ull
+#define DCORE2_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_RTR1_MSTR_IF_SPECIAL_BASE 0x454AE80ull
+#define DCORE2_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR1_ADD_DEC_HBW_BASE 0x454B000ull
+#define DCORE2_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR1_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE2_RTR1_ADD_DEC_LBW_BASE 0x454B400ull
+#define DCORE2_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR1_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE2_RTR1_ADD_DEC_SPECIAL_BASE 0x454BE80ull
+#define DCORE2_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR1_BASE 0x454C000ull
+#define DCORE2_RTR1_MAX_OFFSET 0x1000
+#define DCORE2_RTR1_SECTION 0x3000
+#define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x454C300ull
+#define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR1_HBW_RD_RS_LL_STAT_BASE 0x454C340ull
+#define DCORE2_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x454C380ull
+#define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR1_HBW_WR_RS_LL_STAT_BASE 0x454C3C0ull
+#define DCORE2_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x454C400ull
+#define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR1_LBW_RD_RS_LL_STAT_BASE 0x454C440ull
+#define DCORE2_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x454C480ull
+#define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR1_LBW_WR_RS_LL_STAT_BASE 0x454C4C0ull
+#define DCORE2_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR1_HBW_MFIFO_BASE 0x454C500ull
+#define DCORE2_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_HBW_MFIFO_SECTION 0x4000
+#define DCORE2_RTR1_E2E_RD_LL_STAT_BASE 0x454C540ull
+#define DCORE2_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR1_E2E_WR_LL_STAT_BASE 0x454C580ull
+#define DCORE2_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE2_RTR1_RTR_HBW_XACT_STAT_BASE 0x454C600ull
+#define DCORE2_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR1_RTR_LBW_XACT_STAT_BASE 0x454C680ull
+#define DCORE2_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR1_RTR_E2E_XACT_STAT_BASE 0x454C700ull
+#define DCORE2_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE2_RTR1_SPECIAL_BASE 0x454CE80ull
+#define DCORE2_RTR1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR1_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR1_DBG_ADDR_BASE 0x454D000ull
+#define DCORE2_RTR1_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR1_DBG_ADDR_SECTION 0xE800
+#define DCORE2_RTR1_DBG_ADDR_SPECIAL_BASE 0x454DE80ull
+#define DCORE2_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE2_RTR2_CTRL_BASE 0x4550000ull
+#define DCORE2_RTR2_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR2_CTRL_SECTION 0xE800
+#define DCORE2_RTR2_CTRL_SPECIAL_BASE 0x4550E80ull
+#define DCORE2_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR2_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR2_H3_BASE 0x4551000ull
+#define DCORE2_RTR2_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR2_H3_SECTION 0xE800
+#define DCORE2_RTR2_H3_SPECIAL_BASE 0x4551E80ull
+#define DCORE2_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR2_H3_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4552000ull
+#define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4552200ull
+#define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4552400ull
+#define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4552600ull
+#define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4552800ull
+#define DCORE2_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_RTR2_MSTR_IF_AXUSER_BASE 0x4552A80ull
+#define DCORE2_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_RTR2_MSTR_IF_DBG_HBW_BASE 0x4552B00ull
+#define DCORE2_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_RTR2_MSTR_IF_DBG_LBW_BASE 0x4552B80ull
+#define DCORE2_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_RTR2_MSTR_IF_CORE_HBW_BASE 0x4552C00ull
+#define DCORE2_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_RTR2_MSTR_IF_CORE_LBW_BASE 0x4552D80ull
+#define DCORE2_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_RTR2_MSTR_IF_SPECIAL_BASE 0x4552E80ull
+#define DCORE2_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR2_ADD_DEC_HBW_BASE 0x4553000ull
+#define DCORE2_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR2_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE2_RTR2_ADD_DEC_LBW_BASE 0x4553400ull
+#define DCORE2_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR2_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE2_RTR2_ADD_DEC_SPECIAL_BASE 0x4553E80ull
+#define DCORE2_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR2_BASE 0x4554000ull
+#define DCORE2_RTR2_MAX_OFFSET 0x1000
+#define DCORE2_RTR2_SECTION 0x3000
+#define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4554300ull
+#define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4554340ull
+#define DCORE2_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4554380ull
+#define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR2_HBW_WR_RS_LL_STAT_BASE 0x45543C0ull
+#define DCORE2_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4554400ull
+#define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4554440ull
+#define DCORE2_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4554480ull
+#define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR2_LBW_WR_RS_LL_STAT_BASE 0x45544C0ull
+#define DCORE2_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR2_HBW_MFIFO_BASE 0x4554500ull
+#define DCORE2_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_HBW_MFIFO_SECTION 0x4000
+#define DCORE2_RTR2_E2E_RD_LL_STAT_BASE 0x4554540ull
+#define DCORE2_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR2_E2E_WR_LL_STAT_BASE 0x4554580ull
+#define DCORE2_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE2_RTR2_RTR_HBW_XACT_STAT_BASE 0x4554600ull
+#define DCORE2_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR2_RTR_LBW_XACT_STAT_BASE 0x4554680ull
+#define DCORE2_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR2_RTR_E2E_XACT_STAT_BASE 0x4554700ull
+#define DCORE2_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE2_RTR2_SPECIAL_BASE 0x4554E80ull
+#define DCORE2_RTR2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR2_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR2_DBG_ADDR_BASE 0x4555000ull
+#define DCORE2_RTR2_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR2_DBG_ADDR_SECTION 0xE800
+#define DCORE2_RTR2_DBG_ADDR_SPECIAL_BASE 0x4555E80ull
+#define DCORE2_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE2_RTR3_CTRL_BASE 0x4558000ull
+#define DCORE2_RTR3_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR3_CTRL_SECTION 0xE800
+#define DCORE2_RTR3_CTRL_SPECIAL_BASE 0x4558E80ull
+#define DCORE2_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR3_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR3_H3_BASE 0x4559000ull
+#define DCORE2_RTR3_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR3_H3_SECTION 0xE800
+#define DCORE2_RTR3_H3_SPECIAL_BASE 0x4559E80ull
+#define DCORE2_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR3_H3_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x455A000ull
+#define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x455A200ull
+#define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x455A400ull
+#define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x455A600ull
+#define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_RTR3_MSTR_IF_E2E_CRDT_BASE 0x455A800ull
+#define DCORE2_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_RTR3_MSTR_IF_AXUSER_BASE 0x455AA80ull
+#define DCORE2_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_RTR3_MSTR_IF_DBG_HBW_BASE 0x455AB00ull
+#define DCORE2_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_RTR3_MSTR_IF_DBG_LBW_BASE 0x455AB80ull
+#define DCORE2_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_RTR3_MSTR_IF_CORE_HBW_BASE 0x455AC00ull
+#define DCORE2_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_RTR3_MSTR_IF_CORE_LBW_BASE 0x455AD80ull
+#define DCORE2_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_RTR3_MSTR_IF_SPECIAL_BASE 0x455AE80ull
+#define DCORE2_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR3_ADD_DEC_HBW_BASE 0x455B000ull
+#define DCORE2_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR3_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE2_RTR3_ADD_DEC_LBW_BASE 0x455B400ull
+#define DCORE2_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR3_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE2_RTR3_ADD_DEC_SPECIAL_BASE 0x455BE80ull
+#define DCORE2_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR3_BASE 0x455C000ull
+#define DCORE2_RTR3_MAX_OFFSET 0x1000
+#define DCORE2_RTR3_SECTION 0x3000
+#define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x455C300ull
+#define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR3_HBW_RD_RS_LL_STAT_BASE 0x455C340ull
+#define DCORE2_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x455C380ull
+#define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR3_HBW_WR_RS_LL_STAT_BASE 0x455C3C0ull
+#define DCORE2_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x455C400ull
+#define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR3_LBW_RD_RS_LL_STAT_BASE 0x455C440ull
+#define DCORE2_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x455C480ull
+#define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR3_LBW_WR_RS_LL_STAT_BASE 0x455C4C0ull
+#define DCORE2_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR3_HBW_MFIFO_BASE 0x455C500ull
+#define DCORE2_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_HBW_MFIFO_SECTION 0x4000
+#define DCORE2_RTR3_E2E_RD_LL_STAT_BASE 0x455C540ull
+#define DCORE2_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR3_E2E_WR_LL_STAT_BASE 0x455C580ull
+#define DCORE2_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE2_RTR3_RTR_HBW_XACT_STAT_BASE 0x455C600ull
+#define DCORE2_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR3_RTR_LBW_XACT_STAT_BASE 0x455C680ull
+#define DCORE2_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR3_RTR_E2E_XACT_STAT_BASE 0x455C700ull
+#define DCORE2_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE2_RTR3_SPECIAL_BASE 0x455CE80ull
+#define DCORE2_RTR3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR3_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR3_DBG_ADDR_BASE 0x455D000ull
+#define DCORE2_RTR3_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR3_DBG_ADDR_SECTION 0xE800
+#define DCORE2_RTR3_DBG_ADDR_SPECIAL_BASE 0x455DE80ull
+#define DCORE2_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE2_RTR4_CTRL_BASE 0x4560000ull
+#define DCORE2_RTR4_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR4_CTRL_SECTION 0xE800
+#define DCORE2_RTR4_CTRL_SPECIAL_BASE 0x4560E80ull
+#define DCORE2_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR4_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR4_H3_BASE 0x4561000ull
+#define DCORE2_RTR4_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR4_H3_SECTION 0xE800
+#define DCORE2_RTR4_H3_SPECIAL_BASE 0x4561E80ull
+#define DCORE2_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR4_H3_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4562000ull
+#define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4562200ull
+#define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4562400ull
+#define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4562600ull
+#define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4562800ull
+#define DCORE2_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_RTR4_MSTR_IF_AXUSER_BASE 0x4562A80ull
+#define DCORE2_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR4_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_RTR4_MSTR_IF_DBG_HBW_BASE 0x4562B00ull
+#define DCORE2_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_RTR4_MSTR_IF_DBG_LBW_BASE 0x4562B80ull
+#define DCORE2_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_RTR4_MSTR_IF_CORE_HBW_BASE 0x4562C00ull
+#define DCORE2_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_RTR4_MSTR_IF_CORE_LBW_BASE 0x4562D80ull
+#define DCORE2_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_RTR4_MSTR_IF_SPECIAL_BASE 0x4562E80ull
+#define DCORE2_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR4_ADD_DEC_HBW_BASE 0x4563000ull
+#define DCORE2_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR4_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE2_RTR4_ADD_DEC_LBW_BASE 0x4563400ull
+#define DCORE2_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR4_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE2_RTR4_ADD_DEC_SPECIAL_BASE 0x4563E80ull
+#define DCORE2_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR4_BASE 0x4564000ull
+#define DCORE2_RTR4_MAX_OFFSET 0x1000
+#define DCORE2_RTR4_SECTION 0x3000
+#define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4564300ull
+#define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4564340ull
+#define DCORE2_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4564380ull
+#define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR4_HBW_WR_RS_LL_STAT_BASE 0x45643C0ull
+#define DCORE2_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4564400ull
+#define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4564440ull
+#define DCORE2_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4564480ull
+#define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR4_LBW_WR_RS_LL_STAT_BASE 0x45644C0ull
+#define DCORE2_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR4_HBW_MFIFO_BASE 0x4564500ull
+#define DCORE2_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_HBW_MFIFO_SECTION 0x4000
+#define DCORE2_RTR4_E2E_RD_LL_STAT_BASE 0x4564540ull
+#define DCORE2_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR4_E2E_WR_LL_STAT_BASE 0x4564580ull
+#define DCORE2_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE2_RTR4_RTR_HBW_XACT_STAT_BASE 0x4564600ull
+#define DCORE2_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR4_RTR_LBW_XACT_STAT_BASE 0x4564680ull
+#define DCORE2_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR4_RTR_E2E_XACT_STAT_BASE 0x4564700ull
+#define DCORE2_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE2_RTR4_SPECIAL_BASE 0x4564E80ull
+#define DCORE2_RTR4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR4_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR4_DBG_ADDR_BASE 0x4565000ull
+#define DCORE2_RTR4_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR4_DBG_ADDR_SECTION 0xE800
+#define DCORE2_RTR4_DBG_ADDR_SPECIAL_BASE 0x4565E80ull
+#define DCORE2_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE2_RTR5_CTRL_BASE 0x4568000ull
+#define DCORE2_RTR5_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR5_CTRL_SECTION 0xE800
+#define DCORE2_RTR5_CTRL_SPECIAL_BASE 0x4568E80ull
+#define DCORE2_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR5_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR5_H3_BASE 0x4569000ull
+#define DCORE2_RTR5_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR5_H3_SECTION 0xE800
+#define DCORE2_RTR5_H3_SPECIAL_BASE 0x4569E80ull
+#define DCORE2_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR5_H3_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x456A000ull
+#define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x456A200ull
+#define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x456A400ull
+#define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x456A600ull
+#define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_RTR5_MSTR_IF_E2E_CRDT_BASE 0x456A800ull
+#define DCORE2_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_RTR5_MSTR_IF_AXUSER_BASE 0x456AA80ull
+#define DCORE2_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR5_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_RTR5_MSTR_IF_DBG_HBW_BASE 0x456AB00ull
+#define DCORE2_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_RTR5_MSTR_IF_DBG_LBW_BASE 0x456AB80ull
+#define DCORE2_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_RTR5_MSTR_IF_CORE_HBW_BASE 0x456AC00ull
+#define DCORE2_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_RTR5_MSTR_IF_CORE_LBW_BASE 0x456AD80ull
+#define DCORE2_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_RTR5_MSTR_IF_SPECIAL_BASE 0x456AE80ull
+#define DCORE2_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR5_ADD_DEC_HBW_BASE 0x456B000ull
+#define DCORE2_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR5_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE2_RTR5_ADD_DEC_LBW_BASE 0x456B400ull
+#define DCORE2_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR5_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE2_RTR5_ADD_DEC_SPECIAL_BASE 0x456BE80ull
+#define DCORE2_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR5_BASE 0x456C000ull
+#define DCORE2_RTR5_MAX_OFFSET 0x1000
+#define DCORE2_RTR5_SECTION 0x3000
+#define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x456C300ull
+#define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR5_HBW_RD_RS_LL_STAT_BASE 0x456C340ull
+#define DCORE2_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x456C380ull
+#define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR5_HBW_WR_RS_LL_STAT_BASE 0x456C3C0ull
+#define DCORE2_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x456C400ull
+#define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR5_LBW_RD_RS_LL_STAT_BASE 0x456C440ull
+#define DCORE2_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x456C480ull
+#define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR5_LBW_WR_RS_LL_STAT_BASE 0x456C4C0ull
+#define DCORE2_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR5_HBW_MFIFO_BASE 0x456C500ull
+#define DCORE2_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_HBW_MFIFO_SECTION 0x4000
+#define DCORE2_RTR5_E2E_RD_LL_STAT_BASE 0x456C540ull
+#define DCORE2_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR5_E2E_WR_LL_STAT_BASE 0x456C580ull
+#define DCORE2_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE2_RTR5_RTR_HBW_XACT_STAT_BASE 0x456C600ull
+#define DCORE2_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR5_RTR_LBW_XACT_STAT_BASE 0x456C680ull
+#define DCORE2_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR5_RTR_E2E_XACT_STAT_BASE 0x456C700ull
+#define DCORE2_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE2_RTR5_SPECIAL_BASE 0x456CE80ull
+#define DCORE2_RTR5_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR5_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR5_DBG_ADDR_BASE 0x456D000ull
+#define DCORE2_RTR5_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR5_DBG_ADDR_SECTION 0xE800
+#define DCORE2_RTR5_DBG_ADDR_SPECIAL_BASE 0x456DE80ull
+#define DCORE2_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE2_RTR6_CTRL_BASE 0x4570000ull
+#define DCORE2_RTR6_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR6_CTRL_SECTION 0xE800
+#define DCORE2_RTR6_CTRL_SPECIAL_BASE 0x4570E80ull
+#define DCORE2_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR6_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR6_H3_BASE 0x4571000ull
+#define DCORE2_RTR6_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR6_H3_SECTION 0xE800
+#define DCORE2_RTR6_H3_SPECIAL_BASE 0x4571E80ull
+#define DCORE2_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR6_H3_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4572000ull
+#define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4572200ull
+#define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4572400ull
+#define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4572600ull
+#define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4572800ull
+#define DCORE2_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_RTR6_MSTR_IF_AXUSER_BASE 0x4572A80ull
+#define DCORE2_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR6_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_RTR6_MSTR_IF_DBG_HBW_BASE 0x4572B00ull
+#define DCORE2_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_RTR6_MSTR_IF_DBG_LBW_BASE 0x4572B80ull
+#define DCORE2_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_RTR6_MSTR_IF_CORE_HBW_BASE 0x4572C00ull
+#define DCORE2_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_RTR6_MSTR_IF_CORE_LBW_BASE 0x4572D80ull
+#define DCORE2_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_RTR6_MSTR_IF_SPECIAL_BASE 0x4572E80ull
+#define DCORE2_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR6_ADD_DEC_HBW_BASE 0x4573000ull
+#define DCORE2_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR6_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE2_RTR6_ADD_DEC_LBW_BASE 0x4573400ull
+#define DCORE2_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR6_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE2_RTR6_ADD_DEC_SPECIAL_BASE 0x4573E80ull
+#define DCORE2_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR6_BASE 0x4574000ull
+#define DCORE2_RTR6_MAX_OFFSET 0x1000
+#define DCORE2_RTR6_SECTION 0x3000
+#define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4574300ull
+#define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4574340ull
+#define DCORE2_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4574380ull
+#define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR6_HBW_WR_RS_LL_STAT_BASE 0x45743C0ull
+#define DCORE2_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4574400ull
+#define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4574440ull
+#define DCORE2_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4574480ull
+#define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR6_LBW_WR_RS_LL_STAT_BASE 0x45744C0ull
+#define DCORE2_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR6_HBW_MFIFO_BASE 0x4574500ull
+#define DCORE2_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_HBW_MFIFO_SECTION 0x4000
+#define DCORE2_RTR6_E2E_RD_LL_STAT_BASE 0x4574540ull
+#define DCORE2_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR6_E2E_WR_LL_STAT_BASE 0x4574580ull
+#define DCORE2_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE2_RTR6_RTR_HBW_XACT_STAT_BASE 0x4574600ull
+#define DCORE2_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR6_RTR_LBW_XACT_STAT_BASE 0x4574680ull
+#define DCORE2_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR6_RTR_E2E_XACT_STAT_BASE 0x4574700ull
+#define DCORE2_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE2_RTR6_SPECIAL_BASE 0x4574E80ull
+#define DCORE2_RTR6_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR6_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR6_DBG_ADDR_BASE 0x4575000ull
+#define DCORE2_RTR6_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR6_DBG_ADDR_SECTION 0xE800
+#define DCORE2_RTR6_DBG_ADDR_SPECIAL_BASE 0x4575E80ull
+#define DCORE2_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE2_RTR7_CTRL_BASE 0x4578000ull
+#define DCORE2_RTR7_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR7_CTRL_SECTION 0xE800
+#define DCORE2_RTR7_CTRL_SPECIAL_BASE 0x4578E80ull
+#define DCORE2_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR7_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR7_H3_BASE 0x4579000ull
+#define DCORE2_RTR7_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR7_H3_SECTION 0xE800
+#define DCORE2_RTR7_H3_SPECIAL_BASE 0x4579E80ull
+#define DCORE2_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR7_H3_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x457A000ull
+#define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x457A200ull
+#define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x457A400ull
+#define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x457A600ull
+#define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_RTR7_MSTR_IF_E2E_CRDT_BASE 0x457A800ull
+#define DCORE2_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_RTR7_MSTR_IF_AXUSER_BASE 0x457AA80ull
+#define DCORE2_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR7_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_RTR7_MSTR_IF_DBG_HBW_BASE 0x457AB00ull
+#define DCORE2_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_RTR7_MSTR_IF_DBG_LBW_BASE 0x457AB80ull
+#define DCORE2_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_RTR7_MSTR_IF_CORE_HBW_BASE 0x457AC00ull
+#define DCORE2_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_RTR7_MSTR_IF_CORE_LBW_BASE 0x457AD80ull
+#define DCORE2_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_RTR7_MSTR_IF_SPECIAL_BASE 0x457AE80ull
+#define DCORE2_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR7_ADD_DEC_HBW_BASE 0x457B000ull
+#define DCORE2_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR7_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE2_RTR7_ADD_DEC_LBW_BASE 0x457B400ull
+#define DCORE2_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR7_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE2_RTR7_ADD_DEC_SPECIAL_BASE 0x457BE80ull
+#define DCORE2_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR7_BASE 0x457C000ull
+#define DCORE2_RTR7_MAX_OFFSET 0x1000
+#define DCORE2_RTR7_SECTION 0x3000
+#define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x457C300ull
+#define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR7_HBW_RD_RS_LL_STAT_BASE 0x457C340ull
+#define DCORE2_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x457C380ull
+#define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR7_HBW_WR_RS_LL_STAT_BASE 0x457C3C0ull
+#define DCORE2_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x457C400ull
+#define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR7_LBW_RD_RS_LL_STAT_BASE 0x457C440ull
+#define DCORE2_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x457C480ull
+#define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR7_LBW_WR_RS_LL_STAT_BASE 0x457C4C0ull
+#define DCORE2_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR7_HBW_MFIFO_BASE 0x457C500ull
+#define DCORE2_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_HBW_MFIFO_SECTION 0x4000
+#define DCORE2_RTR7_E2E_RD_LL_STAT_BASE 0x457C540ull
+#define DCORE2_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE2_RTR7_E2E_WR_LL_STAT_BASE 0x457C580ull
+#define DCORE2_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE2_RTR7_RTR_HBW_XACT_STAT_BASE 0x457C600ull
+#define DCORE2_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR7_RTR_LBW_XACT_STAT_BASE 0x457C680ull
+#define DCORE2_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE2_RTR7_RTR_E2E_XACT_STAT_BASE 0x457C700ull
+#define DCORE2_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE2_RTR7_SPECIAL_BASE 0x457CE80ull
+#define DCORE2_RTR7_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR7_SPECIAL_SECTION 0x1800
+#define DCORE2_RTR7_DBG_ADDR_BASE 0x457D000ull
+#define DCORE2_RTR7_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR7_DBG_ADDR_SECTION 0xE800
+#define DCORE2_RTR7_DBG_ADDR_SPECIAL_BASE 0x457DE80ull
+#define DCORE2_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE2_SRAM0_BANK_BASE 0x4580000ull
+#define DCORE2_SRAM0_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM0_BANK_SECTION 0xE800
+#define DCORE2_SRAM0_BANK_SPECIAL_BASE 0x4580E80ull
+#define DCORE2_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM0_BANK_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM0_RTR_BASE 0x4581000ull
+#define DCORE2_SRAM0_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM0_RTR_SECTION 0xE800
+#define DCORE2_SRAM0_RTR_SPECIAL_BASE 0x4581E80ull
+#define DCORE2_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM0_RTR_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4582000ull
+#define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4582100ull
+#define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4582200ull
+#define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4582300ull
+#define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4582400ull
+#define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4582500ull
+#define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4582600ull
+#define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4582700ull
+#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4582780ull
+#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4582800ull
+#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4582880ull
+#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4582900ull
+#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4582980ull
+#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4582A00ull
+#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4582A80ull
+#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE2_SRAM0_DBG_CNT_SPECIAL_BASE 0x4582E80ull
+#define DCORE2_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE2_SRAM1_BANK_BASE 0x4588000ull
+#define DCORE2_SRAM1_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM1_BANK_SECTION 0xE800
+#define DCORE2_SRAM1_BANK_SPECIAL_BASE 0x4588E80ull
+#define DCORE2_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM1_BANK_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM1_RTR_BASE 0x4589000ull
+#define DCORE2_SRAM1_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM1_RTR_SECTION 0xE800
+#define DCORE2_SRAM1_RTR_SPECIAL_BASE 0x4589E80ull
+#define DCORE2_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM1_RTR_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x458A000ull
+#define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x458A100ull
+#define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x458A200ull
+#define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x458A300ull
+#define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x458A400ull
+#define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x458A500ull
+#define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x458A600ull
+#define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x458A700ull
+#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x458A780ull
+#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x458A800ull
+#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x458A880ull
+#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x458A900ull
+#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x458A980ull
+#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x458AA00ull
+#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x458AA80ull
+#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE2_SRAM1_DBG_CNT_SPECIAL_BASE 0x458AE80ull
+#define DCORE2_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE2_SRAM2_BANK_BASE 0x4590000ull
+#define DCORE2_SRAM2_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM2_BANK_SECTION 0xE800
+#define DCORE2_SRAM2_BANK_SPECIAL_BASE 0x4590E80ull
+#define DCORE2_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM2_BANK_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM2_RTR_BASE 0x4591000ull
+#define DCORE2_SRAM2_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM2_RTR_SECTION 0xE800
+#define DCORE2_SRAM2_RTR_SPECIAL_BASE 0x4591E80ull
+#define DCORE2_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM2_RTR_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4592000ull
+#define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4592100ull
+#define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4592200ull
+#define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4592300ull
+#define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4592400ull
+#define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4592500ull
+#define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4592600ull
+#define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4592700ull
+#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4592780ull
+#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4592800ull
+#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4592880ull
+#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4592900ull
+#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4592980ull
+#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4592A00ull
+#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4592A80ull
+#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE2_SRAM2_DBG_CNT_SPECIAL_BASE 0x4592E80ull
+#define DCORE2_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE2_SRAM3_BANK_BASE 0x4598000ull
+#define DCORE2_SRAM3_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM3_BANK_SECTION 0xE800
+#define DCORE2_SRAM3_BANK_SPECIAL_BASE 0x4598E80ull
+#define DCORE2_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM3_BANK_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM3_RTR_BASE 0x4599000ull
+#define DCORE2_SRAM3_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM3_RTR_SECTION 0xE800
+#define DCORE2_SRAM3_RTR_SPECIAL_BASE 0x4599E80ull
+#define DCORE2_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM3_RTR_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x459A000ull
+#define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x459A100ull
+#define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x459A200ull
+#define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x459A300ull
+#define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x459A400ull
+#define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x459A500ull
+#define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x459A600ull
+#define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x459A700ull
+#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x459A780ull
+#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x459A800ull
+#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x459A880ull
+#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x459A900ull
+#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x459A980ull
+#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x459AA00ull
+#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x459AA80ull
+#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE2_SRAM3_DBG_CNT_SPECIAL_BASE 0x459AE80ull
+#define DCORE2_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE2_SRAM4_BANK_BASE 0x45A0000ull
+#define DCORE2_SRAM4_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM4_BANK_SECTION 0xE800
+#define DCORE2_SRAM4_BANK_SPECIAL_BASE 0x45A0E80ull
+#define DCORE2_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM4_BANK_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM4_RTR_BASE 0x45A1000ull
+#define DCORE2_SRAM4_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM4_RTR_SECTION 0xE800
+#define DCORE2_SRAM4_RTR_SPECIAL_BASE 0x45A1E80ull
+#define DCORE2_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM4_RTR_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45A2000ull
+#define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45A2100ull
+#define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45A2200ull
+#define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45A2300ull
+#define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45A2400ull
+#define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45A2500ull
+#define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45A2600ull
+#define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45A2700ull
+#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45A2780ull
+#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45A2800ull
+#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45A2880ull
+#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45A2900ull
+#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45A2980ull
+#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45A2A00ull
+#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45A2A80ull
+#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE2_SRAM4_DBG_CNT_SPECIAL_BASE 0x45A2E80ull
+#define DCORE2_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE2_SRAM5_BANK_BASE 0x45A8000ull
+#define DCORE2_SRAM5_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM5_BANK_SECTION 0xE800
+#define DCORE2_SRAM5_BANK_SPECIAL_BASE 0x45A8E80ull
+#define DCORE2_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM5_BANK_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM5_RTR_BASE 0x45A9000ull
+#define DCORE2_SRAM5_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM5_RTR_SECTION 0xE800
+#define DCORE2_SRAM5_RTR_SPECIAL_BASE 0x45A9E80ull
+#define DCORE2_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM5_RTR_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45AA000ull
+#define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45AA100ull
+#define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45AA200ull
+#define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45AA300ull
+#define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45AA400ull
+#define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45AA500ull
+#define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45AA600ull
+#define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45AA700ull
+#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45AA780ull
+#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45AA800ull
+#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45AA880ull
+#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45AA900ull
+#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45AA980ull
+#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45AAA00ull
+#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45AAA80ull
+#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE2_SRAM5_DBG_CNT_SPECIAL_BASE 0x45AAE80ull
+#define DCORE2_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE2_SRAM6_BANK_BASE 0x45B0000ull
+#define DCORE2_SRAM6_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM6_BANK_SECTION 0xE800
+#define DCORE2_SRAM6_BANK_SPECIAL_BASE 0x45B0E80ull
+#define DCORE2_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM6_BANK_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM6_RTR_BASE 0x45B1000ull
+#define DCORE2_SRAM6_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM6_RTR_SECTION 0xE800
+#define DCORE2_SRAM6_RTR_SPECIAL_BASE 0x45B1E80ull
+#define DCORE2_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM6_RTR_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45B2000ull
+#define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45B2100ull
+#define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45B2200ull
+#define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45B2300ull
+#define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45B2400ull
+#define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45B2500ull
+#define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45B2600ull
+#define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45B2700ull
+#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45B2780ull
+#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45B2800ull
+#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45B2880ull
+#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45B2900ull
+#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45B2980ull
+#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45B2A00ull
+#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45B2A80ull
+#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE2_SRAM6_DBG_CNT_SPECIAL_BASE 0x45B2E80ull
+#define DCORE2_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE2_SRAM7_BANK_BASE 0x45B8000ull
+#define DCORE2_SRAM7_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM7_BANK_SECTION 0xE800
+#define DCORE2_SRAM7_BANK_SPECIAL_BASE 0x45B8E80ull
+#define DCORE2_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM7_BANK_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM7_RTR_BASE 0x45B9000ull
+#define DCORE2_SRAM7_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM7_RTR_SECTION 0xE800
+#define DCORE2_SRAM7_RTR_SPECIAL_BASE 0x45B9E80ull
+#define DCORE2_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM7_RTR_SPECIAL_SECTION 0x1800
+#define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45BA000ull
+#define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45BA100ull
+#define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45BA200ull
+#define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45BA300ull
+#define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45BA400ull
+#define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45BA500ull
+#define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45BA600ull
+#define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45BA700ull
+#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45BA780ull
+#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45BA800ull
+#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45BA880ull
+#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45BA900ull
+#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45BA980ull
+#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45BAA00ull
+#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45BAA80ull
+#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE2_SRAM7_DBG_CNT_SPECIAL_BASE 0x45BAE80ull
+#define DCORE2_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE2_EDMA0_QM_DCCM_BASE 0x45C0000ull
+#define DCORE2_EDMA0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_EDMA0_QM_DCCM_SECTION 0x8000
+#define DCORE2_EDMA0_QM_ARC_AUX_BASE 0x45C8000ull
+#define DCORE2_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_QM_ARC_AUX_SECTION 0xE800
+#define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x45C8E80ull
+#define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE2_EDMA0_QM_BASE 0x45CA000ull
+#define DCORE2_EDMA0_QM_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_QM_SECTION 0x9000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x45CA900ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x45CA908ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x45CA910ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x45CA918ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x45CA920ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x45CA928ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x45CA930ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x45CA938ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x45CA940ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x45CA948ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x45CA950ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x45CA958ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x45CA960ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x45CA968ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x45CA970ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x45CA978ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_EDMA0_QM_AXUSER_SECURED_BASE 0x45CAB00ull
+#define DCORE2_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_EDMA0_QM_AXUSER_NONSECURED_BASE 0x45CAB80ull
+#define DCORE2_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_EDMA0_QM_DBG_HBW_BASE 0x45CAC00ull
+#define DCORE2_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA0_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_EDMA0_QM_DBG_LBW_BASE 0x45CAC80ull
+#define DCORE2_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA0_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_EDMA0_QM_CGM_BASE 0x45CAD80ull
+#define DCORE2_EDMA0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_EDMA0_QM_CGM_SECTION 0x1000
+#define DCORE2_EDMA0_QM_SPECIAL_BASE 0x45CAE80ull
+#define DCORE2_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA0_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_EDMA0_CORE_BASE 0x45CB000ull
+#define DCORE2_EDMA0_CORE_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_CORE_SECTION 0x8000
+#define DCORE2_EDMA0_CORE_CTX_AXUSER_BASE 0x45CB800ull
+#define DCORE2_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000
+#define DCORE2_EDMA0_CORE_CTX_BASE 0x45CB860ull
+#define DCORE2_EDMA0_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE2_EDMA0_CORE_CTX_SECTION 0x5A00
+#define DCORE2_EDMA0_CORE_KDMA_CGM_BASE 0x45CBE00ull
+#define DCORE2_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE2_EDMA0_CORE_KDMA_CGM_SECTION 0x8000
+#define DCORE2_EDMA0_CORE_SPECIAL_BASE 0x45CBE80ull
+#define DCORE2_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA0_CORE_SPECIAL_SECTION 0x1800
+#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x45CC000ull
+#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x45CC200ull
+#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x45CC400ull
+#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x45CC600ull
+#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x45CC800ull
+#define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_EDMA0_MSTR_IF_AXUSER_BASE 0x45CCA80ull
+#define DCORE2_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_EDMA0_MSTR_IF_DBG_HBW_BASE 0x45CCB00ull
+#define DCORE2_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_EDMA0_MSTR_IF_DBG_LBW_BASE 0x45CCB80ull
+#define DCORE2_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_EDMA0_MSTR_IF_CORE_HBW_BASE 0x45CCC00ull
+#define DCORE2_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_EDMA0_MSTR_IF_CORE_LBW_BASE 0x45CCD80ull
+#define DCORE2_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_EDMA0_MSTR_IF_SPECIAL_BASE 0x45CCE80ull
+#define DCORE2_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE2_EDMA1_QM_DCCM_BASE 0x45D0000ull
+#define DCORE2_EDMA1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_EDMA1_QM_DCCM_SECTION 0x8000
+#define DCORE2_EDMA1_QM_ARC_AUX_BASE 0x45D8000ull
+#define DCORE2_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_QM_ARC_AUX_SECTION 0xE800
+#define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x45D8E80ull
+#define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE2_EDMA1_QM_BASE 0x45DA000ull
+#define DCORE2_EDMA1_QM_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_QM_SECTION 0x9000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x45DA900ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x45DA908ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x45DA910ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x45DA918ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x45DA920ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x45DA928ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x45DA930ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x45DA938ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x45DA940ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x45DA948ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x45DA950ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x45DA958ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x45DA960ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x45DA968ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x45DA970ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x45DA978ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE2_EDMA1_QM_AXUSER_SECURED_BASE 0x45DAB00ull
+#define DCORE2_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE2_EDMA1_QM_AXUSER_NONSECURED_BASE 0x45DAB80ull
+#define DCORE2_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE2_EDMA1_QM_DBG_HBW_BASE 0x45DAC00ull
+#define DCORE2_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA1_QM_DBG_HBW_SECTION 0x8000
+#define DCORE2_EDMA1_QM_DBG_LBW_BASE 0x45DAC80ull
+#define DCORE2_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA1_QM_DBG_LBW_SECTION 0x1000
+#define DCORE2_EDMA1_QM_CGM_BASE 0x45DAD80ull
+#define DCORE2_EDMA1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_EDMA1_QM_CGM_SECTION 0x1000
+#define DCORE2_EDMA1_QM_SPECIAL_BASE 0x45DAE80ull
+#define DCORE2_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA1_QM_SPECIAL_SECTION 0x1800
+#define DCORE2_EDMA1_CORE_BASE 0x45DB000ull
+#define DCORE2_EDMA1_CORE_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_CORE_SECTION 0x8000
+#define DCORE2_EDMA1_CORE_CTX_AXUSER_BASE 0x45DB800ull
+#define DCORE2_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000
+#define DCORE2_EDMA1_CORE_CTX_BASE 0x45DB860ull
+#define DCORE2_EDMA1_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE2_EDMA1_CORE_CTX_SECTION 0x5A00
+#define DCORE2_EDMA1_CORE_KDMA_CGM_BASE 0x45DBE00ull
+#define DCORE2_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE2_EDMA1_CORE_KDMA_CGM_SECTION 0x8000
+#define DCORE2_EDMA1_CORE_SPECIAL_BASE 0x45DBE80ull
+#define DCORE2_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA1_CORE_SPECIAL_SECTION 0x1800
+#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x45DC000ull
+#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x45DC200ull
+#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x45DC400ull
+#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x45DC600ull
+#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x45DC800ull
+#define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_EDMA1_MSTR_IF_AXUSER_BASE 0x45DCA80ull
+#define DCORE2_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_EDMA1_MSTR_IF_DBG_HBW_BASE 0x45DCB00ull
+#define DCORE2_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_EDMA1_MSTR_IF_DBG_LBW_BASE 0x45DCB80ull
+#define DCORE2_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_EDMA1_MSTR_IF_CORE_HBW_BASE 0x45DCC00ull
+#define DCORE2_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_EDMA1_MSTR_IF_CORE_LBW_BASE 0x45DCD80ull
+#define DCORE2_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_EDMA1_MSTR_IF_SPECIAL_BASE 0x45DCE80ull
+#define DCORE2_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE2_DEC0_CMD_BASE 0x45E0000ull
+#define DCORE2_DEC0_CMD_MAX_OFFSET 0x1100
+#define DCORE2_DEC0_CMD_SECTION 0x1000
+#define DCORE2_DEC0_VSI_BASE 0x45E1000ull
+#define DCORE2_DEC0_VSI_MAX_OFFSET 0x6FC0
+#define DCORE2_DEC0_VSI_SECTION 0x1000
+#define DCORE2_DEC0_L2C_BASE 0x45E2000ull
+#define DCORE2_DEC0_L2C_MAX_OFFSET 0x39C0
+#define DCORE2_DEC0_L2C_SECTION 0x1000
+#define DCORE2_VDEC0_BRDG_CTRL_BASE 0x45E3000ull
+#define DCORE2_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_BRDG_CTRL_SECTION 0x8000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x45E3800ull
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x45E3900ull
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x45E3A00ull
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x45E3B00ull
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x45E3C00ull
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x45E3E80ull
+#define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE2_VDEC0_CTRL_BASE 0x45E4000ull
+#define DCORE2_VDEC0_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_CTRL_SECTION 0xE800
+#define DCORE2_VDEC0_CTRL_SPECIAL_BASE 0x45E4E80ull
+#define DCORE2_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_VDEC0_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x45E5000ull
+#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x45E5200ull
+#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x45E5400ull
+#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x45E5600ull
+#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x45E5800ull
+#define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_VDEC0_MSTR_IF_AXUSER_BASE 0x45E5A80ull
+#define DCORE2_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_VDEC0_MSTR_IF_DBG_HBW_BASE 0x45E5B00ull
+#define DCORE2_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_VDEC0_MSTR_IF_DBG_LBW_BASE 0x45E5B80ull
+#define DCORE2_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_VDEC0_MSTR_IF_CORE_HBW_BASE 0x45E5C00ull
+#define DCORE2_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_VDEC0_MSTR_IF_CORE_LBW_BASE 0x45E5D80ull
+#define DCORE2_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_VDEC0_MSTR_IF_SPECIAL_BASE 0x45E5E80ull
+#define DCORE2_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
+#define DCORE2_DEC1_CMD_BASE 0x45F0000ull
+#define DCORE2_DEC1_CMD_MAX_OFFSET 0x1100
+#define DCORE2_DEC1_CMD_SECTION 0x1000
+#define DCORE2_DEC1_VSI_BASE 0x45F1000ull
+#define DCORE2_DEC1_VSI_MAX_OFFSET 0x6FC0
+#define DCORE2_DEC1_VSI_SECTION 0x1000
+#define DCORE2_DEC1_L2C_BASE 0x45F2000ull
+#define DCORE2_DEC1_L2C_MAX_OFFSET 0x39C0
+#define DCORE2_DEC1_L2C_SECTION 0x1000
+#define DCORE2_VDEC1_BRDG_CTRL_BASE 0x45F3000ull
+#define DCORE2_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_BRDG_CTRL_SECTION 0x8000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x45F3800ull
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x45F3900ull
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x45F3A00ull
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x45F3B00ull
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x45F3C00ull
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x45F3E80ull
+#define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE2_VDEC1_CTRL_BASE 0x45F4000ull
+#define DCORE2_VDEC1_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_CTRL_SECTION 0xE800
+#define DCORE2_VDEC1_CTRL_SPECIAL_BASE 0x45F4E80ull
+#define DCORE2_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_VDEC1_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x45F5000ull
+#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x45F5200ull
+#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x45F5400ull
+#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x45F5600ull
+#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x45F5800ull
+#define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE2_VDEC1_MSTR_IF_AXUSER_BASE 0x45F5A80ull
+#define DCORE2_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE2_VDEC1_MSTR_IF_DBG_HBW_BASE 0x45F5B00ull
+#define DCORE2_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE2_VDEC1_MSTR_IF_DBG_LBW_BASE 0x45F5B80ull
+#define DCORE2_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE2_VDEC1_MSTR_IF_CORE_HBW_BASE 0x45F5C00ull
+#define DCORE2_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE2_VDEC1_MSTR_IF_CORE_LBW_BASE 0x45F5D80ull
+#define DCORE2_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE2_VDEC1_MSTR_IF_SPECIAL_BASE 0x45F5E80ull
+#define DCORE2_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180
+#define DCORE3_TPC0_QM_DCCM_BASE 0x4600000ull
+#define DCORE3_TPC0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC0_QM_DCCM_SECTION 0x8000
+#define DCORE3_TPC0_QM_ARC_AUX_BASE 0x4608000ull
+#define DCORE3_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_QM_ARC_AUX_SECTION 0xE800
+#define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4608E80ull
+#define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE3_TPC0_QM_BASE 0x460A000ull
+#define DCORE3_TPC0_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_QM_SECTION 0x9000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x460A900ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x460A908ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x460A910ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x460A918ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x460A920ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x460A928ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x460A930ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x460A938ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x460A940ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x460A948ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x460A950ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x460A958ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x460A960ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x460A968ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x460A970ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x460A978ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_TPC0_QM_AXUSER_SECURED_BASE 0x460AB00ull
+#define DCORE3_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_TPC0_QM_AXUSER_NONSECURED_BASE 0x460AB80ull
+#define DCORE3_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_TPC0_QM_DBG_HBW_BASE 0x460AC00ull
+#define DCORE3_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC0_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC0_QM_DBG_LBW_BASE 0x460AC80ull
+#define DCORE3_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC0_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_TPC0_QM_CGM_BASE 0x460AD80ull
+#define DCORE3_TPC0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC0_QM_CGM_SECTION 0x1000
+#define DCORE3_TPC0_QM_SPECIAL_BASE 0x460AE80ull
+#define DCORE3_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x460B000ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC0_CFG_BASE 0x460B000ull
+#define DCORE3_TPC0_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_CFG_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x460B050ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x460B0A0ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x460B0F0ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x460B140ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x460B190ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x460B1E0ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x460B230ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x460B280ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x460B2D0ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x460B320ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x460B370ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x460B3C0ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x460B410ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x460B460ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x460B4B0ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x460B500ull
+#define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC0_CFG_KERNEL_BASE 0x460B508ull
+#define DCORE3_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC0_CFG_KERNEL_SECTION 0xD400
+#define DCORE3_TPC0_CFG_QM_TENSOR_0_BASE 0x460B5DCull
+#define DCORE3_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_1_BASE 0x460B62Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_2_BASE 0x460B67Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_3_BASE 0x460B6CCull
+#define DCORE3_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_4_BASE 0x460B71Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_5_BASE 0x460B76Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_6_BASE 0x460B7BCull
+#define DCORE3_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_7_BASE 0x460B80Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_8_BASE 0x460B85Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_9_BASE 0x460B8ACull
+#define DCORE3_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_10_BASE 0x460B8FCull
+#define DCORE3_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_11_BASE 0x460B94Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_12_BASE 0x460B99Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_13_BASE 0x460B9ECull
+#define DCORE3_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_14_BASE 0x460BA3Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_15_BASE 0x460BA8Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x460BADCull
+#define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC0_CFG_QM_BASE 0x460BAE4ull
+#define DCORE3_TPC0_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC0_CFG_QM_SECTION 0x31C0
+#define DCORE3_TPC0_CFG_AXUSER_BASE 0x460BE00ull
+#define DCORE3_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_AXUSER_SECTION 0x8000
+#define DCORE3_TPC0_CFG_SPECIAL_BASE 0x460BE80ull
+#define DCORE3_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x460C000ull
+#define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x460C200ull
+#define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x460C400ull
+#define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x460C600ull
+#define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_TPC0_MSTR_IF_E2E_CRDT_BASE 0x460C800ull
+#define DCORE3_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_TPC0_MSTR_IF_AXUSER_BASE 0x460CA80ull
+#define DCORE3_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_TPC0_MSTR_IF_DBG_HBW_BASE 0x460CB00ull
+#define DCORE3_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC0_MSTR_IF_DBG_LBW_BASE 0x460CB80ull
+#define DCORE3_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_TPC0_MSTR_IF_CORE_HBW_BASE 0x460CC00ull
+#define DCORE3_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_TPC0_MSTR_IF_CORE_LBW_BASE 0x460CD80ull
+#define DCORE3_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_TPC0_MSTR_IF_SPECIAL_BASE 0x460CE80ull
+#define DCORE3_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE3_TPC1_QM_DCCM_BASE 0x4610000ull
+#define DCORE3_TPC1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC1_QM_DCCM_SECTION 0x8000
+#define DCORE3_TPC1_QM_ARC_AUX_BASE 0x4618000ull
+#define DCORE3_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_QM_ARC_AUX_SECTION 0xE800
+#define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4618E80ull
+#define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE3_TPC1_QM_BASE 0x461A000ull
+#define DCORE3_TPC1_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_QM_SECTION 0x9000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x461A900ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x461A908ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x461A910ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x461A918ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x461A920ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x461A928ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x461A930ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x461A938ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x461A940ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x461A948ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x461A950ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x461A958ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x461A960ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x461A968ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x461A970ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x461A978ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_TPC1_QM_AXUSER_SECURED_BASE 0x461AB00ull
+#define DCORE3_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_TPC1_QM_AXUSER_NONSECURED_BASE 0x461AB80ull
+#define DCORE3_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_TPC1_QM_DBG_HBW_BASE 0x461AC00ull
+#define DCORE3_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC1_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC1_QM_DBG_LBW_BASE 0x461AC80ull
+#define DCORE3_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC1_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_TPC1_QM_CGM_BASE 0x461AD80ull
+#define DCORE3_TPC1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC1_QM_CGM_SECTION 0x1000
+#define DCORE3_TPC1_QM_SPECIAL_BASE 0x461AE80ull
+#define DCORE3_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x461B000ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC1_CFG_BASE 0x461B000ull
+#define DCORE3_TPC1_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_CFG_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x461B050ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x461B0A0ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x461B0F0ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x461B140ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x461B190ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x461B1E0ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x461B230ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x461B280ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x461B2D0ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x461B320ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x461B370ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x461B3C0ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x461B410ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x461B460ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x461B4B0ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x461B500ull
+#define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC1_CFG_KERNEL_BASE 0x461B508ull
+#define DCORE3_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC1_CFG_KERNEL_SECTION 0xD400
+#define DCORE3_TPC1_CFG_QM_TENSOR_0_BASE 0x461B5DCull
+#define DCORE3_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_1_BASE 0x461B62Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_2_BASE 0x461B67Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_3_BASE 0x461B6CCull
+#define DCORE3_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_4_BASE 0x461B71Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_5_BASE 0x461B76Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_6_BASE 0x461B7BCull
+#define DCORE3_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_7_BASE 0x461B80Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_8_BASE 0x461B85Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_9_BASE 0x461B8ACull
+#define DCORE3_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_10_BASE 0x461B8FCull
+#define DCORE3_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_11_BASE 0x461B94Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_12_BASE 0x461B99Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_13_BASE 0x461B9ECull
+#define DCORE3_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_14_BASE 0x461BA3Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_15_BASE 0x461BA8Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x461BADCull
+#define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC1_CFG_QM_BASE 0x461BAE4ull
+#define DCORE3_TPC1_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC1_CFG_QM_SECTION 0x31C0
+#define DCORE3_TPC1_CFG_AXUSER_BASE 0x461BE00ull
+#define DCORE3_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_AXUSER_SECTION 0x8000
+#define DCORE3_TPC1_CFG_SPECIAL_BASE 0x461BE80ull
+#define DCORE3_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x461C000ull
+#define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x461C200ull
+#define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x461C400ull
+#define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x461C600ull
+#define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_TPC1_MSTR_IF_E2E_CRDT_BASE 0x461C800ull
+#define DCORE3_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_TPC1_MSTR_IF_AXUSER_BASE 0x461CA80ull
+#define DCORE3_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_TPC1_MSTR_IF_DBG_HBW_BASE 0x461CB00ull
+#define DCORE3_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC1_MSTR_IF_DBG_LBW_BASE 0x461CB80ull
+#define DCORE3_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_TPC1_MSTR_IF_CORE_HBW_BASE 0x461CC00ull
+#define DCORE3_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_TPC1_MSTR_IF_CORE_LBW_BASE 0x461CD80ull
+#define DCORE3_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_TPC1_MSTR_IF_SPECIAL_BASE 0x461CE80ull
+#define DCORE3_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE3_TPC2_QM_DCCM_BASE 0x4620000ull
+#define DCORE3_TPC2_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC2_QM_DCCM_SECTION 0x8000
+#define DCORE3_TPC2_QM_ARC_AUX_BASE 0x4628000ull
+#define DCORE3_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_QM_ARC_AUX_SECTION 0xE800
+#define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4628E80ull
+#define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE3_TPC2_QM_BASE 0x462A000ull
+#define DCORE3_TPC2_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_QM_SECTION 0x9000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x462A900ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x462A908ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x462A910ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x462A918ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x462A920ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x462A928ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x462A930ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x462A938ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x462A940ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x462A948ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x462A950ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x462A958ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x462A960ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x462A968ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x462A970ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x462A978ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_TPC2_QM_AXUSER_SECURED_BASE 0x462AB00ull
+#define DCORE3_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_TPC2_QM_AXUSER_NONSECURED_BASE 0x462AB80ull
+#define DCORE3_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_TPC2_QM_DBG_HBW_BASE 0x462AC00ull
+#define DCORE3_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC2_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC2_QM_DBG_LBW_BASE 0x462AC80ull
+#define DCORE3_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC2_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_TPC2_QM_CGM_BASE 0x462AD80ull
+#define DCORE3_TPC2_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC2_QM_CGM_SECTION 0x1000
+#define DCORE3_TPC2_QM_SPECIAL_BASE 0x462AE80ull
+#define DCORE3_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x462B000ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC2_CFG_BASE 0x462B000ull
+#define DCORE3_TPC2_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_CFG_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x462B050ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x462B0A0ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x462B0F0ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x462B140ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x462B190ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x462B1E0ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x462B230ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x462B280ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x462B2D0ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x462B320ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x462B370ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x462B3C0ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x462B410ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x462B460ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x462B4B0ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x462B500ull
+#define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC2_CFG_KERNEL_BASE 0x462B508ull
+#define DCORE3_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC2_CFG_KERNEL_SECTION 0xD400
+#define DCORE3_TPC2_CFG_QM_TENSOR_0_BASE 0x462B5DCull
+#define DCORE3_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_1_BASE 0x462B62Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_2_BASE 0x462B67Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_3_BASE 0x462B6CCull
+#define DCORE3_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_4_BASE 0x462B71Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_5_BASE 0x462B76Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_6_BASE 0x462B7BCull
+#define DCORE3_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_7_BASE 0x462B80Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_8_BASE 0x462B85Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_9_BASE 0x462B8ACull
+#define DCORE3_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_10_BASE 0x462B8FCull
+#define DCORE3_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_11_BASE 0x462B94Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_12_BASE 0x462B99Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_13_BASE 0x462B9ECull
+#define DCORE3_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_14_BASE 0x462BA3Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_15_BASE 0x462BA8Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x462BADCull
+#define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC2_CFG_QM_BASE 0x462BAE4ull
+#define DCORE3_TPC2_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC2_CFG_QM_SECTION 0x31C0
+#define DCORE3_TPC2_CFG_AXUSER_BASE 0x462BE00ull
+#define DCORE3_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_AXUSER_SECTION 0x8000
+#define DCORE3_TPC2_CFG_SPECIAL_BASE 0x462BE80ull
+#define DCORE3_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x462C000ull
+#define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x462C200ull
+#define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x462C400ull
+#define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x462C600ull
+#define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_TPC2_MSTR_IF_E2E_CRDT_BASE 0x462C800ull
+#define DCORE3_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_TPC2_MSTR_IF_AXUSER_BASE 0x462CA80ull
+#define DCORE3_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_TPC2_MSTR_IF_DBG_HBW_BASE 0x462CB00ull
+#define DCORE3_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC2_MSTR_IF_DBG_LBW_BASE 0x462CB80ull
+#define DCORE3_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_TPC2_MSTR_IF_CORE_HBW_BASE 0x462CC00ull
+#define DCORE3_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_TPC2_MSTR_IF_CORE_LBW_BASE 0x462CD80ull
+#define DCORE3_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_TPC2_MSTR_IF_SPECIAL_BASE 0x462CE80ull
+#define DCORE3_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE3_TPC3_QM_DCCM_BASE 0x4630000ull
+#define DCORE3_TPC3_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC3_QM_DCCM_SECTION 0x8000
+#define DCORE3_TPC3_QM_ARC_AUX_BASE 0x4638000ull
+#define DCORE3_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_QM_ARC_AUX_SECTION 0xE800
+#define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4638E80ull
+#define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE3_TPC3_QM_BASE 0x463A000ull
+#define DCORE3_TPC3_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_QM_SECTION 0x9000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x463A900ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x463A908ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x463A910ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x463A918ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x463A920ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x463A928ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x463A930ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x463A938ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x463A940ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x463A948ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x463A950ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x463A958ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x463A960ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x463A968ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x463A970ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x463A978ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_TPC3_QM_AXUSER_SECURED_BASE 0x463AB00ull
+#define DCORE3_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_TPC3_QM_AXUSER_NONSECURED_BASE 0x463AB80ull
+#define DCORE3_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_TPC3_QM_DBG_HBW_BASE 0x463AC00ull
+#define DCORE3_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC3_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC3_QM_DBG_LBW_BASE 0x463AC80ull
+#define DCORE3_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC3_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_TPC3_QM_CGM_BASE 0x463AD80ull
+#define DCORE3_TPC3_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC3_QM_CGM_SECTION 0x1000
+#define DCORE3_TPC3_QM_SPECIAL_BASE 0x463AE80ull
+#define DCORE3_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x463B000ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC3_CFG_BASE 0x463B000ull
+#define DCORE3_TPC3_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_CFG_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x463B050ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x463B0A0ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x463B0F0ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x463B140ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x463B190ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x463B1E0ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x463B230ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x463B280ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x463B2D0ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x463B320ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x463B370ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x463B3C0ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x463B410ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x463B460ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x463B4B0ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x463B500ull
+#define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC3_CFG_KERNEL_BASE 0x463B508ull
+#define DCORE3_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC3_CFG_KERNEL_SECTION 0xD400
+#define DCORE3_TPC3_CFG_QM_TENSOR_0_BASE 0x463B5DCull
+#define DCORE3_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_1_BASE 0x463B62Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_2_BASE 0x463B67Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_3_BASE 0x463B6CCull
+#define DCORE3_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_4_BASE 0x463B71Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_5_BASE 0x463B76Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_6_BASE 0x463B7BCull
+#define DCORE3_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_7_BASE 0x463B80Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_8_BASE 0x463B85Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_9_BASE 0x463B8ACull
+#define DCORE3_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_10_BASE 0x463B8FCull
+#define DCORE3_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_11_BASE 0x463B94Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_12_BASE 0x463B99Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_13_BASE 0x463B9ECull
+#define DCORE3_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_14_BASE 0x463BA3Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_15_BASE 0x463BA8Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x463BADCull
+#define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC3_CFG_QM_BASE 0x463BAE4ull
+#define DCORE3_TPC3_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC3_CFG_QM_SECTION 0x31C0
+#define DCORE3_TPC3_CFG_AXUSER_BASE 0x463BE00ull
+#define DCORE3_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_AXUSER_SECTION 0x8000
+#define DCORE3_TPC3_CFG_SPECIAL_BASE 0x463BE80ull
+#define DCORE3_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x463C000ull
+#define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x463C200ull
+#define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x463C400ull
+#define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x463C600ull
+#define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_TPC3_MSTR_IF_E2E_CRDT_BASE 0x463C800ull
+#define DCORE3_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_TPC3_MSTR_IF_AXUSER_BASE 0x463CA80ull
+#define DCORE3_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_TPC3_MSTR_IF_DBG_HBW_BASE 0x463CB00ull
+#define DCORE3_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC3_MSTR_IF_DBG_LBW_BASE 0x463CB80ull
+#define DCORE3_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_TPC3_MSTR_IF_CORE_HBW_BASE 0x463CC00ull
+#define DCORE3_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_TPC3_MSTR_IF_CORE_LBW_BASE 0x463CD80ull
+#define DCORE3_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_TPC3_MSTR_IF_SPECIAL_BASE 0x463CE80ull
+#define DCORE3_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE3_TPC4_QM_DCCM_BASE 0x4640000ull
+#define DCORE3_TPC4_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC4_QM_DCCM_SECTION 0x8000
+#define DCORE3_TPC4_QM_ARC_AUX_BASE 0x4648000ull
+#define DCORE3_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_QM_ARC_AUX_SECTION 0xE800
+#define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4648E80ull
+#define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE3_TPC4_QM_BASE 0x464A000ull
+#define DCORE3_TPC4_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_QM_SECTION 0x9000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x464A900ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x464A908ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x464A910ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x464A918ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x464A920ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x464A928ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x464A930ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x464A938ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x464A940ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x464A948ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x464A950ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x464A958ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x464A960ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x464A968ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x464A970ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x464A978ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_TPC4_QM_AXUSER_SECURED_BASE 0x464AB00ull
+#define DCORE3_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_TPC4_QM_AXUSER_NONSECURED_BASE 0x464AB80ull
+#define DCORE3_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_TPC4_QM_DBG_HBW_BASE 0x464AC00ull
+#define DCORE3_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC4_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC4_QM_DBG_LBW_BASE 0x464AC80ull
+#define DCORE3_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC4_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_TPC4_QM_CGM_BASE 0x464AD80ull
+#define DCORE3_TPC4_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC4_QM_CGM_SECTION 0x1000
+#define DCORE3_TPC4_QM_SPECIAL_BASE 0x464AE80ull
+#define DCORE3_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x464B000ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC4_CFG_BASE 0x464B000ull
+#define DCORE3_TPC4_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_CFG_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x464B050ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x464B0A0ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x464B0F0ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x464B140ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x464B190ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x464B1E0ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x464B230ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x464B280ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x464B2D0ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x464B320ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x464B370ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x464B3C0ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x464B410ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x464B460ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x464B4B0ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x464B500ull
+#define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC4_CFG_KERNEL_BASE 0x464B508ull
+#define DCORE3_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC4_CFG_KERNEL_SECTION 0xD400
+#define DCORE3_TPC4_CFG_QM_TENSOR_0_BASE 0x464B5DCull
+#define DCORE3_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_1_BASE 0x464B62Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_2_BASE 0x464B67Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_3_BASE 0x464B6CCull
+#define DCORE3_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_4_BASE 0x464B71Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_5_BASE 0x464B76Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_6_BASE 0x464B7BCull
+#define DCORE3_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_7_BASE 0x464B80Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_8_BASE 0x464B85Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_9_BASE 0x464B8ACull
+#define DCORE3_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_10_BASE 0x464B8FCull
+#define DCORE3_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_11_BASE 0x464B94Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_12_BASE 0x464B99Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_13_BASE 0x464B9ECull
+#define DCORE3_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_14_BASE 0x464BA3Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_15_BASE 0x464BA8Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x464BADCull
+#define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC4_CFG_QM_BASE 0x464BAE4ull
+#define DCORE3_TPC4_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC4_CFG_QM_SECTION 0x31C0
+#define DCORE3_TPC4_CFG_AXUSER_BASE 0x464BE00ull
+#define DCORE3_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_AXUSER_SECTION 0x8000
+#define DCORE3_TPC4_CFG_SPECIAL_BASE 0x464BE80ull
+#define DCORE3_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x464C000ull
+#define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x464C200ull
+#define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x464C400ull
+#define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x464C600ull
+#define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_TPC4_MSTR_IF_E2E_CRDT_BASE 0x464C800ull
+#define DCORE3_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_TPC4_MSTR_IF_AXUSER_BASE 0x464CA80ull
+#define DCORE3_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_TPC4_MSTR_IF_DBG_HBW_BASE 0x464CB00ull
+#define DCORE3_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC4_MSTR_IF_DBG_LBW_BASE 0x464CB80ull
+#define DCORE3_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_TPC4_MSTR_IF_CORE_HBW_BASE 0x464CC00ull
+#define DCORE3_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_TPC4_MSTR_IF_CORE_LBW_BASE 0x464CD80ull
+#define DCORE3_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_TPC4_MSTR_IF_SPECIAL_BASE 0x464CE80ull
+#define DCORE3_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE3_TPC5_QM_DCCM_BASE 0x4650000ull
+#define DCORE3_TPC5_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC5_QM_DCCM_SECTION 0x8000
+#define DCORE3_TPC5_QM_ARC_AUX_BASE 0x4658000ull
+#define DCORE3_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_QM_ARC_AUX_SECTION 0xE800
+#define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4658E80ull
+#define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE3_TPC5_QM_BASE 0x465A000ull
+#define DCORE3_TPC5_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_QM_SECTION 0x9000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x465A900ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x465A908ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x465A910ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x465A918ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x465A920ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x465A928ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x465A930ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x465A938ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x465A940ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x465A948ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x465A950ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x465A958ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x465A960ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x465A968ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x465A970ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x465A978ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_TPC5_QM_AXUSER_SECURED_BASE 0x465AB00ull
+#define DCORE3_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_TPC5_QM_AXUSER_NONSECURED_BASE 0x465AB80ull
+#define DCORE3_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_TPC5_QM_DBG_HBW_BASE 0x465AC00ull
+#define DCORE3_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC5_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC5_QM_DBG_LBW_BASE 0x465AC80ull
+#define DCORE3_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC5_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_TPC5_QM_CGM_BASE 0x465AD80ull
+#define DCORE3_TPC5_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC5_QM_CGM_SECTION 0x1000
+#define DCORE3_TPC5_QM_SPECIAL_BASE 0x465AE80ull
+#define DCORE3_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x465B000ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC5_CFG_BASE 0x465B000ull
+#define DCORE3_TPC5_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_CFG_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x465B050ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x465B0A0ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x465B0F0ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x465B140ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x465B190ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x465B1E0ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x465B230ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x465B280ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x465B2D0ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x465B320ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x465B370ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x465B3C0ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x465B410ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x465B460ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x465B4B0ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x465B500ull
+#define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC5_CFG_KERNEL_BASE 0x465B508ull
+#define DCORE3_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC5_CFG_KERNEL_SECTION 0xD400
+#define DCORE3_TPC5_CFG_QM_TENSOR_0_BASE 0x465B5DCull
+#define DCORE3_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_1_BASE 0x465B62Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_2_BASE 0x465B67Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_3_BASE 0x465B6CCull
+#define DCORE3_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_4_BASE 0x465B71Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_5_BASE 0x465B76Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_6_BASE 0x465B7BCull
+#define DCORE3_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_7_BASE 0x465B80Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_8_BASE 0x465B85Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_9_BASE 0x465B8ACull
+#define DCORE3_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_10_BASE 0x465B8FCull
+#define DCORE3_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_11_BASE 0x465B94Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_12_BASE 0x465B99Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_13_BASE 0x465B9ECull
+#define DCORE3_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_14_BASE 0x465BA3Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_15_BASE 0x465BA8Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000
+#define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x465BADCull
+#define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define DCORE3_TPC5_CFG_QM_BASE 0x465BAE4ull
+#define DCORE3_TPC5_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC5_CFG_QM_SECTION 0x31C0
+#define DCORE3_TPC5_CFG_AXUSER_BASE 0x465BE00ull
+#define DCORE3_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_AXUSER_SECTION 0x8000
+#define DCORE3_TPC5_CFG_SPECIAL_BASE 0x465BE80ull
+#define DCORE3_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_CFG_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x465C000ull
+#define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x465C200ull
+#define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x465C400ull
+#define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x465C600ull
+#define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_TPC5_MSTR_IF_E2E_CRDT_BASE 0x465C800ull
+#define DCORE3_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_TPC5_MSTR_IF_AXUSER_BASE 0x465CA80ull
+#define DCORE3_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_TPC5_MSTR_IF_DBG_HBW_BASE 0x465CB00ull
+#define DCORE3_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_TPC5_MSTR_IF_DBG_LBW_BASE 0x465CB80ull
+#define DCORE3_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_TPC5_MSTR_IF_CORE_HBW_BASE 0x465CC00ull
+#define DCORE3_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_TPC5_MSTR_IF_CORE_LBW_BASE 0x465CD80ull
+#define DCORE3_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_TPC5_MSTR_IF_SPECIAL_BASE 0x465CE80ull
+#define DCORE3_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180
+#define DCORE3_HMMU0_MMU_BASE 0x4680000ull
+#define DCORE3_HMMU0_MMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_MMU_SECTION 0xE800
+#define DCORE3_HMMU0_MMU_SPECIAL_BASE 0x4680E80ull
+#define DCORE3_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU0_MMU_SPECIAL_SECTION 0x1800
+#define DCORE3_HMMU0_STLB_BASE 0x4681000ull
+#define DCORE3_HMMU0_STLB_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_STLB_SECTION 0xE800
+#define DCORE3_HMMU0_STLB_SPECIAL_BASE 0x4681E80ull
+#define DCORE3_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU0_STLB_SPECIAL_SECTION 0x1180
+#define DCORE3_HMMU0_SCRAMB_OUT_BASE 0x4683000ull
+#define DCORE3_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_SCRAMB_OUT_SECTION 0xE800
+#define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4683E80ull
+#define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4684000ull
+#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4684200ull
+#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4684400ull
+#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4684600ull
+#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4684800ull
+#define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_HMMU0_MSTR_IF_AXUSER_BASE 0x4684A80ull
+#define DCORE3_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4684B00ull
+#define DCORE3_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4684B80ull
+#define DCORE3_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4684C00ull
+#define DCORE3_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4684D80ull
+#define DCORE3_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_HMMU0_MSTR_IF_SPECIAL_BASE 0x4684E80ull
+#define DCORE3_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE3_HMMU1_MMU_BASE 0x4690000ull
+#define DCORE3_HMMU1_MMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_MMU_SECTION 0xE800
+#define DCORE3_HMMU1_MMU_SPECIAL_BASE 0x4690E80ull
+#define DCORE3_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU1_MMU_SPECIAL_SECTION 0x1800
+#define DCORE3_HMMU1_STLB_BASE 0x4691000ull
+#define DCORE3_HMMU1_STLB_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_STLB_SECTION 0xE800
+#define DCORE3_HMMU1_STLB_SPECIAL_BASE 0x4691E80ull
+#define DCORE3_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU1_STLB_SPECIAL_SECTION 0x1180
+#define DCORE3_HMMU1_SCRAMB_OUT_BASE 0x4693000ull
+#define DCORE3_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_SCRAMB_OUT_SECTION 0xE800
+#define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4693E80ull
+#define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4694000ull
+#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4694200ull
+#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4694400ull
+#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4694600ull
+#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4694800ull
+#define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_HMMU1_MSTR_IF_AXUSER_BASE 0x4694A80ull
+#define DCORE3_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4694B00ull
+#define DCORE3_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4694B80ull
+#define DCORE3_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4694C00ull
+#define DCORE3_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4694D80ull
+#define DCORE3_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_HMMU1_MSTR_IF_SPECIAL_BASE 0x4694E80ull
+#define DCORE3_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE3_HMMU2_MMU_BASE 0x46A0000ull
+#define DCORE3_HMMU2_MMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_MMU_SECTION 0xE800
+#define DCORE3_HMMU2_MMU_SPECIAL_BASE 0x46A0E80ull
+#define DCORE3_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU2_MMU_SPECIAL_SECTION 0x1800
+#define DCORE3_HMMU2_STLB_BASE 0x46A1000ull
+#define DCORE3_HMMU2_STLB_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_STLB_SECTION 0xE800
+#define DCORE3_HMMU2_STLB_SPECIAL_BASE 0x46A1E80ull
+#define DCORE3_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU2_STLB_SPECIAL_SECTION 0x1180
+#define DCORE3_HMMU2_SCRAMB_OUT_BASE 0x46A3000ull
+#define DCORE3_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_SCRAMB_OUT_SECTION 0xE800
+#define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x46A3E80ull
+#define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x46A4000ull
+#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x46A4200ull
+#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x46A4400ull
+#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x46A4600ull
+#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x46A4800ull
+#define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_HMMU2_MSTR_IF_AXUSER_BASE 0x46A4A80ull
+#define DCORE3_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_HMMU2_MSTR_IF_DBG_HBW_BASE 0x46A4B00ull
+#define DCORE3_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_HMMU2_MSTR_IF_DBG_LBW_BASE 0x46A4B80ull
+#define DCORE3_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_HMMU2_MSTR_IF_CORE_HBW_BASE 0x46A4C00ull
+#define DCORE3_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_HMMU2_MSTR_IF_CORE_LBW_BASE 0x46A4D80ull
+#define DCORE3_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_HMMU2_MSTR_IF_SPECIAL_BASE 0x46A4E80ull
+#define DCORE3_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE3_HMMU3_MMU_BASE 0x46B0000ull
+#define DCORE3_HMMU3_MMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_MMU_SECTION 0xE800
+#define DCORE3_HMMU3_MMU_SPECIAL_BASE 0x46B0E80ull
+#define DCORE3_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU3_MMU_SPECIAL_SECTION 0x1800
+#define DCORE3_HMMU3_STLB_BASE 0x46B1000ull
+#define DCORE3_HMMU3_STLB_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_STLB_SECTION 0xE800
+#define DCORE3_HMMU3_STLB_SPECIAL_BASE 0x46B1E80ull
+#define DCORE3_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU3_STLB_SPECIAL_SECTION 0x1180
+#define DCORE3_HMMU3_SCRAMB_OUT_BASE 0x46B3000ull
+#define DCORE3_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_SCRAMB_OUT_SECTION 0xE800
+#define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x46B3E80ull
+#define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x46B4000ull
+#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x46B4200ull
+#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x46B4400ull
+#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x46B4600ull
+#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x46B4800ull
+#define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_HMMU3_MSTR_IF_AXUSER_BASE 0x46B4A80ull
+#define DCORE3_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_HMMU3_MSTR_IF_DBG_HBW_BASE 0x46B4B00ull
+#define DCORE3_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_HMMU3_MSTR_IF_DBG_LBW_BASE 0x46B4B80ull
+#define DCORE3_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_HMMU3_MSTR_IF_CORE_HBW_BASE 0x46B4C00ull
+#define DCORE3_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_HMMU3_MSTR_IF_CORE_LBW_BASE 0x46B4D80ull
+#define DCORE3_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_HMMU3_MSTR_IF_SPECIAL_BASE 0x46B4E80ull
+#define DCORE3_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180
+#define DCORE3_MME_QM_ARC_DCCM_BASE 0x46C0000ull
+#define DCORE3_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_MME_QM_ARC_DCCM_SECTION 0x8000
+#define DCORE3_MME_QM_ARC_AUX_BASE 0x46C8000ull
+#define DCORE3_MME_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_MME_QM_ARC_AUX_SECTION 0xE800
+#define DCORE3_MME_QM_ARC_AUX_SPECIAL_BASE 0x46C8E80ull
+#define DCORE3_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_QM_ARC_DUP_ENG_BASE 0x46C9000ull
+#define DCORE3_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000
+#define DCORE3_MME_QM_ARC_DUP_ENG_SECTION 0x9000
+#define DCORE3_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x46C9900ull
+#define DCORE3_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800
+#define DCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x46C9E80ull
+#define DCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_QM_BASE 0x46CA000ull
+#define DCORE3_MME_QM_MAX_OFFSET 0x1000
+#define DCORE3_MME_QM_SECTION 0x9000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x46CA900ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x46CA908ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x46CA910ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x46CA918ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x46CA920ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x46CA928ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x46CA930ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x46CA938ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x46CA940ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x46CA948ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x46CA950ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x46CA958ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x46CA960ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x46CA968ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x46CA970ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x46CA978ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_MME_QM_AXUSER_SECURED_BASE 0x46CAB00ull
+#define DCORE3_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_MME_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_MME_QM_AXUSER_NONSECURED_BASE 0x46CAB80ull
+#define DCORE3_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_MME_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_MME_QM_DBG_HBW_BASE 0x46CAC00ull
+#define DCORE3_MME_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_MME_QM_DBG_LBW_BASE 0x46CAC80ull
+#define DCORE3_MME_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_MME_QM_CGM_BASE 0x46CAD80ull
+#define DCORE3_MME_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_MME_QM_CGM_SECTION 0x1000
+#define DCORE3_MME_QM_SPECIAL_BASE 0x46CAE80ull
+#define DCORE3_MME_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_CTRL_LO_BASE 0x46CB000ull
+#define DCORE3_MME_CTRL_LO_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_LO_SECTION 0x8000
+#define DCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x46CB008ull
+#define DCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000
+#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x46CB028ull
+#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x46CB040ull
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x46CB098ull
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x46CB0F0ull
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x46CB15Cull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x46CB170ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x46CB184ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x46CB198ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x46CB1ACull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x46CB1C0ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x46CB1D4ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x46CB1E8ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x46CB1FCull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x46CB210ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x46CB22Cull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x46CB240ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x46CB254ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x46CB268ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x46CB280ull
+#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800
+#define DCORE3_MME_CTRL_LO_MME_AXUSER_BASE 0x46CBE00ull
+#define DCORE3_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000
+#define DCORE3_MME_CTRL_LO_SPECIAL_BASE 0x46CBE80ull
+#define DCORE3_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_LO_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_CTRL_HI_BASE 0x46CC000ull
+#define DCORE3_MME_CTRL_HI_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_HI_SECTION 0x8000
+#define DCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x46CC008ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000
+#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x46CC028ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x46CC040ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x46CC098ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x46CC0F0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x46CC15Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x46CC170ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x46CC184ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x46CC198ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x46CC1ACull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x46CC1C0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x46CC1D4ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x46CC1E8ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x46CC1FCull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x46CC210ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x46CC22Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x46CC240ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x46CC254ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x46CC268ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x46CC280ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800
+#define DCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x46CC308ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000
+#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x46CC328ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x46CC340ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x46CC398ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x46CC3F0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x46CC45Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x46CC470ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x46CC484ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x46CC498ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x46CC4ACull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x46CC4C0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x46CC4D4ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x46CC4E8ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x46CC4FCull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x46CC510ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x46CC52Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x46CC540ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x46CC554ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x46CC568ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x46CC580ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800
+#define DCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x46CC608ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000
+#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x46CC628ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x46CC640ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x46CC698ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x46CC6F0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x46CC75Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x46CC770ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x46CC784ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x46CC798ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x46CC7ACull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x46CC7C0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x46CC7D4ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x46CC7E8ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x46CC7FCull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x46CC810ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x46CC82Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x46CC840ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x46CC854ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x46CC868ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x46CC880ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800
+#define DCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x46CC908ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000
+#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x46CC928ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x46CC940ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x46CC998ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x46CC9F0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x46CCA5Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x46CCA70ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x46CCA84ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x46CCA98ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x46CCAACull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x46CCAC0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x46CCAD4ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x46CCAE8ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x46CCAFCull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x46CCB10ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x46CCB2Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x46CCB40ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x46CCB54ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x46CCB68ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x46CCB80ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000
+#define DCORE3_MME_CTRL_HI_SPECIAL_BASE 0x46CCE80ull
+#define DCORE3_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_HI_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_EU_BIST_BASE 0x46CD000ull
+#define DCORE3_MME_EU_BIST_MAX_OFFSET 0x1000
+#define DCORE3_MME_EU_BIST_SECTION 0xE800
+#define DCORE3_MME_EU_BIST_SPECIAL_BASE 0x46CDE80ull
+#define DCORE3_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_EU_BIST_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x46CE000ull
+#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x46CE200ull
+#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x46CE400ull
+#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x46CE600ull
+#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x46CE800ull
+#define DCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_MME_CTRL_MSTR_IF_AXUSER_BASE 0x46CEA80ull
+#define DCORE3_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x46CEB00ull
+#define DCORE3_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x46CEB80ull
+#define DCORE3_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x46CEC00ull
+#define DCORE3_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x46CED80ull
+#define DCORE3_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x46CEE80ull
+#define DCORE3_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_QM_ARC_ACP_ENG_BASE 0x46CF000ull
+#define DCORE3_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000
+#define DCORE3_MME_QM_ARC_ACP_ENG_SECTION 0xE800
+#define DCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x46CFE80ull
+#define DCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_SBTE0_BASE 0x46D0000ull
+#define DCORE3_MME_SBTE0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_SECTION 0xE800
+#define DCORE3_MME_SBTE0_SPECIAL_BASE 0x46D0E80ull
+#define DCORE3_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE0_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x46D1000ull
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x46D1200ull
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x46D1400ull
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x46D1600ull
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x46D1800ull
+#define DCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x46D1A80ull
+#define DCORE3_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x46D1B00ull
+#define DCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x46D1B80ull
+#define DCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x46D1C00ull
+#define DCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x46D1D80ull
+#define DCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x46D1E80ull
+#define DCORE3_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE3_MME_SBTE1_BASE 0x46D8000ull
+#define DCORE3_MME_SBTE1_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_SECTION 0xE800
+#define DCORE3_MME_SBTE1_SPECIAL_BASE 0x46D8E80ull
+#define DCORE3_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE1_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x46D9000ull
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x46D9200ull
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x46D9400ull
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x46D9600ull
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x46D9800ull
+#define DCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x46D9A80ull
+#define DCORE3_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x46D9B00ull
+#define DCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x46D9B80ull
+#define DCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x46D9C00ull
+#define DCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x46D9D80ull
+#define DCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x46D9E80ull
+#define DCORE3_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE3_MME_SBTE2_BASE 0x46E0000ull
+#define DCORE3_MME_SBTE2_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_SECTION 0xE800
+#define DCORE3_MME_SBTE2_SPECIAL_BASE 0x46E0E80ull
+#define DCORE3_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE2_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x46E1000ull
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x46E1200ull
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x46E1400ull
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x46E1600ull
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x46E1800ull
+#define DCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x46E1A80ull
+#define DCORE3_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x46E1B00ull
+#define DCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x46E1B80ull
+#define DCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x46E1C00ull
+#define DCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x46E1D80ull
+#define DCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x46E1E80ull
+#define DCORE3_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE3_MME_SBTE3_BASE 0x46E8000ull
+#define DCORE3_MME_SBTE3_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_SECTION 0xE800
+#define DCORE3_MME_SBTE3_SPECIAL_BASE 0x46E8E80ull
+#define DCORE3_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE3_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x46E9000ull
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x46E9200ull
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x46E9400ull
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x46E9600ull
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x46E9800ull
+#define DCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x46E9A80ull
+#define DCORE3_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x46E9B00ull
+#define DCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x46E9B80ull
+#define DCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x46E9C00ull
+#define DCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x46E9D80ull
+#define DCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x46E9E80ull
+#define DCORE3_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE3_MME_SBTE4_BASE 0x46F0000ull
+#define DCORE3_MME_SBTE4_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_SECTION 0xE800
+#define DCORE3_MME_SBTE4_SPECIAL_BASE 0x46F0E80ull
+#define DCORE3_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE4_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x46F1000ull
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x46F1200ull
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x46F1400ull
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x46F1600ull
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x46F1800ull
+#define DCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x46F1A80ull
+#define DCORE3_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x46F1B00ull
+#define DCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x46F1B80ull
+#define DCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x46F1C00ull
+#define DCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x46F1D80ull
+#define DCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x46F1E80ull
+#define DCORE3_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180
+#define DCORE3_MME_ACC_BASE 0x46F8000ull
+#define DCORE3_MME_ACC_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_SECTION 0xE800
+#define DCORE3_MME_ACC_SPECIAL_BASE 0x46F8E80ull
+#define DCORE3_MME_ACC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_ACC_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x46F9000ull
+#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x46F9200ull
+#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x46F9400ull
+#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x46F9600ull
+#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x46F9800ull
+#define DCORE3_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_MME_WB0_MSTR_IF_AXUSER_BASE 0x46F9A80ull
+#define DCORE3_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x46F9B00ull
+#define DCORE3_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x46F9B80ull
+#define DCORE3_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x46F9C00ull
+#define DCORE3_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x46F9D80ull
+#define DCORE3_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_MME_WB0_MSTR_IF_SPECIAL_BASE 0x46F9E80ull
+#define DCORE3_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x46FA000ull
+#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x46FA200ull
+#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x46FA400ull
+#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x46FA600ull
+#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x46FA800ull
+#define DCORE3_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_MME_WB1_MSTR_IF_AXUSER_BASE 0x46FAA80ull
+#define DCORE3_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x46FAB00ull
+#define DCORE3_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x46FAB80ull
+#define DCORE3_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x46FAC00ull
+#define DCORE3_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x46FAD80ull
+#define DCORE3_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_MME_WB1_MSTR_IF_SPECIAL_BASE 0x46FAE80ull
+#define DCORE3_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180
+#define DCORE3_SYNC_MNGR_OBJS_BASE 0x4700000ull
+#define DCORE3_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00
+#define DCORE3_SYNC_MNGR_OBJS_SECTION 0x1E000
+#define DCORE3_SYNC_MNGR_GLBL_BASE 0x471E000ull
+#define DCORE3_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000
+#define DCORE3_SYNC_MNGR_GLBL_SECTION 0xE800
+#define DCORE3_SYNC_MNGR_GLBL_SPECIAL_BASE 0x471EE80ull
+#define DCORE3_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x471F000ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x471F200ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x471F400ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x471F600ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x471F800ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x471FA80ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x471FB00ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x471FB80ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x471FC00ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x471FD80ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x471FE80ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE3_HIF0_BASE 0x4720000ull
+#define DCORE3_HIF0_MAX_OFFSET 0x1000
+#define DCORE3_HIF0_SECTION 0xE800
+#define DCORE3_HIF0_SPECIAL_BASE 0x4720E80ull
+#define DCORE3_HIF0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HIF0_SPECIAL_SECTION 0x3180
+#define DCORE3_HIF1_BASE 0x4724000ull
+#define DCORE3_HIF1_MAX_OFFSET 0x1000
+#define DCORE3_HIF1_SECTION 0xE800
+#define DCORE3_HIF1_SPECIAL_BASE 0x4724E80ull
+#define DCORE3_HIF1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HIF1_SPECIAL_SECTION 0x3180
+#define DCORE3_HIF2_BASE 0x4728000ull
+#define DCORE3_HIF2_MAX_OFFSET 0x1000
+#define DCORE3_HIF2_SECTION 0xE800
+#define DCORE3_HIF2_SPECIAL_BASE 0x4728E80ull
+#define DCORE3_HIF2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HIF2_SPECIAL_SECTION 0x3180
+#define DCORE3_HIF3_BASE 0x472C000ull
+#define DCORE3_HIF3_MAX_OFFSET 0x1000
+#define DCORE3_HIF3_SECTION 0xE800
+#define DCORE3_HIF3_SPECIAL_BASE 0x472CE80ull
+#define DCORE3_HIF3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HIF3_SPECIAL_SECTION 0x13180
+#define DCORE3_RTR0_CTRL_BASE 0x4740000ull
+#define DCORE3_RTR0_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR0_CTRL_SECTION 0xE800
+#define DCORE3_RTR0_CTRL_SPECIAL_BASE 0x4740E80ull
+#define DCORE3_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR0_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR0_H3_BASE 0x4741000ull
+#define DCORE3_RTR0_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR0_H3_SECTION 0xE800
+#define DCORE3_RTR0_H3_SPECIAL_BASE 0x4741E80ull
+#define DCORE3_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR0_H3_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4742000ull
+#define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4742200ull
+#define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4742400ull
+#define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4742600ull
+#define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4742800ull
+#define DCORE3_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_RTR0_MSTR_IF_AXUSER_BASE 0x4742A80ull
+#define DCORE3_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_RTR0_MSTR_IF_DBG_HBW_BASE 0x4742B00ull
+#define DCORE3_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_RTR0_MSTR_IF_DBG_LBW_BASE 0x4742B80ull
+#define DCORE3_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_RTR0_MSTR_IF_CORE_HBW_BASE 0x4742C00ull
+#define DCORE3_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_RTR0_MSTR_IF_CORE_LBW_BASE 0x4742D80ull
+#define DCORE3_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_RTR0_MSTR_IF_SPECIAL_BASE 0x4742E80ull
+#define DCORE3_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR0_ADD_DEC_HBW_BASE 0x4743000ull
+#define DCORE3_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR0_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE3_RTR0_ADD_DEC_LBW_BASE 0x4743400ull
+#define DCORE3_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR0_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE3_RTR0_ADD_DEC_SPECIAL_BASE 0x4743E80ull
+#define DCORE3_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR0_BASE 0x4744000ull
+#define DCORE3_RTR0_MAX_OFFSET 0x1000
+#define DCORE3_RTR0_SECTION 0x3000
+#define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4744300ull
+#define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4744340ull
+#define DCORE3_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4744380ull
+#define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR0_HBW_WR_RS_LL_STAT_BASE 0x47443C0ull
+#define DCORE3_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4744400ull
+#define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4744440ull
+#define DCORE3_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4744480ull
+#define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR0_LBW_WR_RS_LL_STAT_BASE 0x47444C0ull
+#define DCORE3_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR0_HBW_MFIFO_BASE 0x4744500ull
+#define DCORE3_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_HBW_MFIFO_SECTION 0x4000
+#define DCORE3_RTR0_E2E_RD_LL_STAT_BASE 0x4744540ull
+#define DCORE3_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR0_E2E_WR_LL_STAT_BASE 0x4744580ull
+#define DCORE3_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE3_RTR0_RTR_HBW_XACT_STAT_BASE 0x4744600ull
+#define DCORE3_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR0_RTR_LBW_XACT_STAT_BASE 0x4744680ull
+#define DCORE3_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR0_RTR_E2E_XACT_STAT_BASE 0x4744700ull
+#define DCORE3_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE3_RTR0_SPECIAL_BASE 0x4744E80ull
+#define DCORE3_RTR0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR0_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR0_DBG_ADDR_BASE 0x4745000ull
+#define DCORE3_RTR0_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR0_DBG_ADDR_SECTION 0xE800
+#define DCORE3_RTR0_DBG_ADDR_SPECIAL_BASE 0x4745E80ull
+#define DCORE3_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE3_RTR1_CTRL_BASE 0x4748000ull
+#define DCORE3_RTR1_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR1_CTRL_SECTION 0xE800
+#define DCORE3_RTR1_CTRL_SPECIAL_BASE 0x4748E80ull
+#define DCORE3_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR1_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR1_H3_BASE 0x4749000ull
+#define DCORE3_RTR1_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR1_H3_SECTION 0xE800
+#define DCORE3_RTR1_H3_SPECIAL_BASE 0x4749E80ull
+#define DCORE3_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR1_H3_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x474A000ull
+#define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x474A200ull
+#define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x474A400ull
+#define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x474A600ull
+#define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_RTR1_MSTR_IF_E2E_CRDT_BASE 0x474A800ull
+#define DCORE3_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_RTR1_MSTR_IF_AXUSER_BASE 0x474AA80ull
+#define DCORE3_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_RTR1_MSTR_IF_DBG_HBW_BASE 0x474AB00ull
+#define DCORE3_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_RTR1_MSTR_IF_DBG_LBW_BASE 0x474AB80ull
+#define DCORE3_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_RTR1_MSTR_IF_CORE_HBW_BASE 0x474AC00ull
+#define DCORE3_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_RTR1_MSTR_IF_CORE_LBW_BASE 0x474AD80ull
+#define DCORE3_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_RTR1_MSTR_IF_SPECIAL_BASE 0x474AE80ull
+#define DCORE3_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR1_ADD_DEC_HBW_BASE 0x474B000ull
+#define DCORE3_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR1_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE3_RTR1_ADD_DEC_LBW_BASE 0x474B400ull
+#define DCORE3_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR1_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE3_RTR1_ADD_DEC_SPECIAL_BASE 0x474BE80ull
+#define DCORE3_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR1_BASE 0x474C000ull
+#define DCORE3_RTR1_MAX_OFFSET 0x1000
+#define DCORE3_RTR1_SECTION 0x3000
+#define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x474C300ull
+#define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR1_HBW_RD_RS_LL_STAT_BASE 0x474C340ull
+#define DCORE3_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x474C380ull
+#define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR1_HBW_WR_RS_LL_STAT_BASE 0x474C3C0ull
+#define DCORE3_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x474C400ull
+#define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR1_LBW_RD_RS_LL_STAT_BASE 0x474C440ull
+#define DCORE3_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x474C480ull
+#define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR1_LBW_WR_RS_LL_STAT_BASE 0x474C4C0ull
+#define DCORE3_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR1_HBW_MFIFO_BASE 0x474C500ull
+#define DCORE3_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_HBW_MFIFO_SECTION 0x4000
+#define DCORE3_RTR1_E2E_RD_LL_STAT_BASE 0x474C540ull
+#define DCORE3_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR1_E2E_WR_LL_STAT_BASE 0x474C580ull
+#define DCORE3_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE3_RTR1_RTR_HBW_XACT_STAT_BASE 0x474C600ull
+#define DCORE3_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR1_RTR_LBW_XACT_STAT_BASE 0x474C680ull
+#define DCORE3_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR1_RTR_E2E_XACT_STAT_BASE 0x474C700ull
+#define DCORE3_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE3_RTR1_SPECIAL_BASE 0x474CE80ull
+#define DCORE3_RTR1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR1_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR1_DBG_ADDR_BASE 0x474D000ull
+#define DCORE3_RTR1_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR1_DBG_ADDR_SECTION 0xE800
+#define DCORE3_RTR1_DBG_ADDR_SPECIAL_BASE 0x474DE80ull
+#define DCORE3_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE3_RTR2_CTRL_BASE 0x4750000ull
+#define DCORE3_RTR2_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR2_CTRL_SECTION 0xE800
+#define DCORE3_RTR2_CTRL_SPECIAL_BASE 0x4750E80ull
+#define DCORE3_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR2_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR2_H3_BASE 0x4751000ull
+#define DCORE3_RTR2_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR2_H3_SECTION 0xE800
+#define DCORE3_RTR2_H3_SPECIAL_BASE 0x4751E80ull
+#define DCORE3_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR2_H3_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4752000ull
+#define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4752200ull
+#define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4752400ull
+#define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4752600ull
+#define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4752800ull
+#define DCORE3_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_RTR2_MSTR_IF_AXUSER_BASE 0x4752A80ull
+#define DCORE3_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR2_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_RTR2_MSTR_IF_DBG_HBW_BASE 0x4752B00ull
+#define DCORE3_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_RTR2_MSTR_IF_DBG_LBW_BASE 0x4752B80ull
+#define DCORE3_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_RTR2_MSTR_IF_CORE_HBW_BASE 0x4752C00ull
+#define DCORE3_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_RTR2_MSTR_IF_CORE_LBW_BASE 0x4752D80ull
+#define DCORE3_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_RTR2_MSTR_IF_SPECIAL_BASE 0x4752E80ull
+#define DCORE3_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR2_ADD_DEC_HBW_BASE 0x4753000ull
+#define DCORE3_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR2_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE3_RTR2_ADD_DEC_LBW_BASE 0x4753400ull
+#define DCORE3_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR2_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE3_RTR2_ADD_DEC_SPECIAL_BASE 0x4753E80ull
+#define DCORE3_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR2_BASE 0x4754000ull
+#define DCORE3_RTR2_MAX_OFFSET 0x1000
+#define DCORE3_RTR2_SECTION 0x3000
+#define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4754300ull
+#define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4754340ull
+#define DCORE3_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4754380ull
+#define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR2_HBW_WR_RS_LL_STAT_BASE 0x47543C0ull
+#define DCORE3_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4754400ull
+#define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4754440ull
+#define DCORE3_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4754480ull
+#define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR2_LBW_WR_RS_LL_STAT_BASE 0x47544C0ull
+#define DCORE3_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR2_HBW_MFIFO_BASE 0x4754500ull
+#define DCORE3_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_HBW_MFIFO_SECTION 0x4000
+#define DCORE3_RTR2_E2E_RD_LL_STAT_BASE 0x4754540ull
+#define DCORE3_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR2_E2E_WR_LL_STAT_BASE 0x4754580ull
+#define DCORE3_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE3_RTR2_RTR_HBW_XACT_STAT_BASE 0x4754600ull
+#define DCORE3_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR2_RTR_LBW_XACT_STAT_BASE 0x4754680ull
+#define DCORE3_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR2_RTR_E2E_XACT_STAT_BASE 0x4754700ull
+#define DCORE3_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE3_RTR2_SPECIAL_BASE 0x4754E80ull
+#define DCORE3_RTR2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR2_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR2_DBG_ADDR_BASE 0x4755000ull
+#define DCORE3_RTR2_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR2_DBG_ADDR_SECTION 0xE800
+#define DCORE3_RTR2_DBG_ADDR_SPECIAL_BASE 0x4755E80ull
+#define DCORE3_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE3_RTR3_CTRL_BASE 0x4758000ull
+#define DCORE3_RTR3_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR3_CTRL_SECTION 0xE800
+#define DCORE3_RTR3_CTRL_SPECIAL_BASE 0x4758E80ull
+#define DCORE3_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR3_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR3_H3_BASE 0x4759000ull
+#define DCORE3_RTR3_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR3_H3_SECTION 0xE800
+#define DCORE3_RTR3_H3_SPECIAL_BASE 0x4759E80ull
+#define DCORE3_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR3_H3_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x475A000ull
+#define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x475A200ull
+#define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x475A400ull
+#define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x475A600ull
+#define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_RTR3_MSTR_IF_E2E_CRDT_BASE 0x475A800ull
+#define DCORE3_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_RTR3_MSTR_IF_AXUSER_BASE 0x475AA80ull
+#define DCORE3_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR3_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_RTR3_MSTR_IF_DBG_HBW_BASE 0x475AB00ull
+#define DCORE3_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_RTR3_MSTR_IF_DBG_LBW_BASE 0x475AB80ull
+#define DCORE3_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_RTR3_MSTR_IF_CORE_HBW_BASE 0x475AC00ull
+#define DCORE3_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_RTR3_MSTR_IF_CORE_LBW_BASE 0x475AD80ull
+#define DCORE3_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_RTR3_MSTR_IF_SPECIAL_BASE 0x475AE80ull
+#define DCORE3_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR3_ADD_DEC_HBW_BASE 0x475B000ull
+#define DCORE3_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR3_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE3_RTR3_ADD_DEC_LBW_BASE 0x475B400ull
+#define DCORE3_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR3_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE3_RTR3_ADD_DEC_SPECIAL_BASE 0x475BE80ull
+#define DCORE3_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR3_BASE 0x475C000ull
+#define DCORE3_RTR3_MAX_OFFSET 0x1000
+#define DCORE3_RTR3_SECTION 0x3000
+#define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x475C300ull
+#define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR3_HBW_RD_RS_LL_STAT_BASE 0x475C340ull
+#define DCORE3_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x475C380ull
+#define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR3_HBW_WR_RS_LL_STAT_BASE 0x475C3C0ull
+#define DCORE3_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x475C400ull
+#define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR3_LBW_RD_RS_LL_STAT_BASE 0x475C440ull
+#define DCORE3_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x475C480ull
+#define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR3_LBW_WR_RS_LL_STAT_BASE 0x475C4C0ull
+#define DCORE3_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR3_HBW_MFIFO_BASE 0x475C500ull
+#define DCORE3_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_HBW_MFIFO_SECTION 0x4000
+#define DCORE3_RTR3_E2E_RD_LL_STAT_BASE 0x475C540ull
+#define DCORE3_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR3_E2E_WR_LL_STAT_BASE 0x475C580ull
+#define DCORE3_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE3_RTR3_RTR_HBW_XACT_STAT_BASE 0x475C600ull
+#define DCORE3_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR3_RTR_LBW_XACT_STAT_BASE 0x475C680ull
+#define DCORE3_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR3_RTR_E2E_XACT_STAT_BASE 0x475C700ull
+#define DCORE3_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE3_RTR3_SPECIAL_BASE 0x475CE80ull
+#define DCORE3_RTR3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR3_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR3_DBG_ADDR_BASE 0x475D000ull
+#define DCORE3_RTR3_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR3_DBG_ADDR_SECTION 0xE800
+#define DCORE3_RTR3_DBG_ADDR_SPECIAL_BASE 0x475DE80ull
+#define DCORE3_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE3_RTR4_CTRL_BASE 0x4760000ull
+#define DCORE3_RTR4_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR4_CTRL_SECTION 0xE800
+#define DCORE3_RTR4_CTRL_SPECIAL_BASE 0x4760E80ull
+#define DCORE3_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR4_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR4_H3_BASE 0x4761000ull
+#define DCORE3_RTR4_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR4_H3_SECTION 0xE800
+#define DCORE3_RTR4_H3_SPECIAL_BASE 0x4761E80ull
+#define DCORE3_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR4_H3_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4762000ull
+#define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4762200ull
+#define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4762400ull
+#define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4762600ull
+#define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4762800ull
+#define DCORE3_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_RTR4_MSTR_IF_AXUSER_BASE 0x4762A80ull
+#define DCORE3_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR4_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_RTR4_MSTR_IF_DBG_HBW_BASE 0x4762B00ull
+#define DCORE3_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_RTR4_MSTR_IF_DBG_LBW_BASE 0x4762B80ull
+#define DCORE3_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_RTR4_MSTR_IF_CORE_HBW_BASE 0x4762C00ull
+#define DCORE3_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_RTR4_MSTR_IF_CORE_LBW_BASE 0x4762D80ull
+#define DCORE3_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_RTR4_MSTR_IF_SPECIAL_BASE 0x4762E80ull
+#define DCORE3_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR4_ADD_DEC_HBW_BASE 0x4763000ull
+#define DCORE3_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR4_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE3_RTR4_ADD_DEC_LBW_BASE 0x4763400ull
+#define DCORE3_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR4_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE3_RTR4_ADD_DEC_SPECIAL_BASE 0x4763E80ull
+#define DCORE3_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR4_BASE 0x4764000ull
+#define DCORE3_RTR4_MAX_OFFSET 0x1000
+#define DCORE3_RTR4_SECTION 0x3000
+#define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4764300ull
+#define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4764340ull
+#define DCORE3_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4764380ull
+#define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR4_HBW_WR_RS_LL_STAT_BASE 0x47643C0ull
+#define DCORE3_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4764400ull
+#define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4764440ull
+#define DCORE3_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4764480ull
+#define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR4_LBW_WR_RS_LL_STAT_BASE 0x47644C0ull
+#define DCORE3_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR4_HBW_MFIFO_BASE 0x4764500ull
+#define DCORE3_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_HBW_MFIFO_SECTION 0x4000
+#define DCORE3_RTR4_E2E_RD_LL_STAT_BASE 0x4764540ull
+#define DCORE3_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR4_E2E_WR_LL_STAT_BASE 0x4764580ull
+#define DCORE3_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE3_RTR4_RTR_HBW_XACT_STAT_BASE 0x4764600ull
+#define DCORE3_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR4_RTR_LBW_XACT_STAT_BASE 0x4764680ull
+#define DCORE3_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR4_RTR_E2E_XACT_STAT_BASE 0x4764700ull
+#define DCORE3_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE3_RTR4_SPECIAL_BASE 0x4764E80ull
+#define DCORE3_RTR4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR4_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR4_DBG_ADDR_BASE 0x4765000ull
+#define DCORE3_RTR4_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR4_DBG_ADDR_SECTION 0xE800
+#define DCORE3_RTR4_DBG_ADDR_SPECIAL_BASE 0x4765E80ull
+#define DCORE3_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE3_RTR5_CTRL_BASE 0x4768000ull
+#define DCORE3_RTR5_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR5_CTRL_SECTION 0xE800
+#define DCORE3_RTR5_CTRL_SPECIAL_BASE 0x4768E80ull
+#define DCORE3_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR5_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR5_H3_BASE 0x4769000ull
+#define DCORE3_RTR5_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR5_H3_SECTION 0xE800
+#define DCORE3_RTR5_H3_SPECIAL_BASE 0x4769E80ull
+#define DCORE3_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR5_H3_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x476A000ull
+#define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x476A200ull
+#define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x476A400ull
+#define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x476A600ull
+#define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_RTR5_MSTR_IF_E2E_CRDT_BASE 0x476A800ull
+#define DCORE3_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_RTR5_MSTR_IF_AXUSER_BASE 0x476AA80ull
+#define DCORE3_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR5_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_RTR5_MSTR_IF_DBG_HBW_BASE 0x476AB00ull
+#define DCORE3_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_RTR5_MSTR_IF_DBG_LBW_BASE 0x476AB80ull
+#define DCORE3_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_RTR5_MSTR_IF_CORE_HBW_BASE 0x476AC00ull
+#define DCORE3_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_RTR5_MSTR_IF_CORE_LBW_BASE 0x476AD80ull
+#define DCORE3_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_RTR5_MSTR_IF_SPECIAL_BASE 0x476AE80ull
+#define DCORE3_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR5_ADD_DEC_HBW_BASE 0x476B000ull
+#define DCORE3_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR5_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE3_RTR5_ADD_DEC_LBW_BASE 0x476B400ull
+#define DCORE3_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR5_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE3_RTR5_ADD_DEC_SPECIAL_BASE 0x476BE80ull
+#define DCORE3_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR5_BASE 0x476C000ull
+#define DCORE3_RTR5_MAX_OFFSET 0x1000
+#define DCORE3_RTR5_SECTION 0x3000
+#define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x476C300ull
+#define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR5_HBW_RD_RS_LL_STAT_BASE 0x476C340ull
+#define DCORE3_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x476C380ull
+#define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR5_HBW_WR_RS_LL_STAT_BASE 0x476C3C0ull
+#define DCORE3_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x476C400ull
+#define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR5_LBW_RD_RS_LL_STAT_BASE 0x476C440ull
+#define DCORE3_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x476C480ull
+#define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR5_LBW_WR_RS_LL_STAT_BASE 0x476C4C0ull
+#define DCORE3_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR5_HBW_MFIFO_BASE 0x476C500ull
+#define DCORE3_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_HBW_MFIFO_SECTION 0x4000
+#define DCORE3_RTR5_E2E_RD_LL_STAT_BASE 0x476C540ull
+#define DCORE3_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR5_E2E_WR_LL_STAT_BASE 0x476C580ull
+#define DCORE3_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE3_RTR5_RTR_HBW_XACT_STAT_BASE 0x476C600ull
+#define DCORE3_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR5_RTR_LBW_XACT_STAT_BASE 0x476C680ull
+#define DCORE3_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR5_RTR_E2E_XACT_STAT_BASE 0x476C700ull
+#define DCORE3_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE3_RTR5_SPECIAL_BASE 0x476CE80ull
+#define DCORE3_RTR5_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR5_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR5_DBG_ADDR_BASE 0x476D000ull
+#define DCORE3_RTR5_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR5_DBG_ADDR_SECTION 0xE800
+#define DCORE3_RTR5_DBG_ADDR_SPECIAL_BASE 0x476DE80ull
+#define DCORE3_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE3_RTR6_CTRL_BASE 0x4770000ull
+#define DCORE3_RTR6_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR6_CTRL_SECTION 0xE800
+#define DCORE3_RTR6_CTRL_SPECIAL_BASE 0x4770E80ull
+#define DCORE3_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR6_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR6_H3_BASE 0x4771000ull
+#define DCORE3_RTR6_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR6_H3_SECTION 0xE800
+#define DCORE3_RTR6_H3_SPECIAL_BASE 0x4771E80ull
+#define DCORE3_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR6_H3_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4772000ull
+#define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4772200ull
+#define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4772400ull
+#define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4772600ull
+#define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4772800ull
+#define DCORE3_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_RTR6_MSTR_IF_AXUSER_BASE 0x4772A80ull
+#define DCORE3_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR6_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_RTR6_MSTR_IF_DBG_HBW_BASE 0x4772B00ull
+#define DCORE3_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_RTR6_MSTR_IF_DBG_LBW_BASE 0x4772B80ull
+#define DCORE3_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_RTR6_MSTR_IF_CORE_HBW_BASE 0x4772C00ull
+#define DCORE3_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_RTR6_MSTR_IF_CORE_LBW_BASE 0x4772D80ull
+#define DCORE3_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_RTR6_MSTR_IF_SPECIAL_BASE 0x4772E80ull
+#define DCORE3_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR6_ADD_DEC_HBW_BASE 0x4773000ull
+#define DCORE3_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR6_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE3_RTR6_ADD_DEC_LBW_BASE 0x4773400ull
+#define DCORE3_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR6_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE3_RTR6_ADD_DEC_SPECIAL_BASE 0x4773E80ull
+#define DCORE3_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR6_BASE 0x4774000ull
+#define DCORE3_RTR6_MAX_OFFSET 0x1000
+#define DCORE3_RTR6_SECTION 0x3000
+#define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4774300ull
+#define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4774340ull
+#define DCORE3_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4774380ull
+#define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR6_HBW_WR_RS_LL_STAT_BASE 0x47743C0ull
+#define DCORE3_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4774400ull
+#define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4774440ull
+#define DCORE3_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4774480ull
+#define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR6_LBW_WR_RS_LL_STAT_BASE 0x47744C0ull
+#define DCORE3_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR6_HBW_MFIFO_BASE 0x4774500ull
+#define DCORE3_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_HBW_MFIFO_SECTION 0x4000
+#define DCORE3_RTR6_E2E_RD_LL_STAT_BASE 0x4774540ull
+#define DCORE3_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR6_E2E_WR_LL_STAT_BASE 0x4774580ull
+#define DCORE3_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE3_RTR6_RTR_HBW_XACT_STAT_BASE 0x4774600ull
+#define DCORE3_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR6_RTR_LBW_XACT_STAT_BASE 0x4774680ull
+#define DCORE3_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR6_RTR_E2E_XACT_STAT_BASE 0x4774700ull
+#define DCORE3_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE3_RTR6_SPECIAL_BASE 0x4774E80ull
+#define DCORE3_RTR6_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR6_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR6_DBG_ADDR_BASE 0x4775000ull
+#define DCORE3_RTR6_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR6_DBG_ADDR_SECTION 0xE800
+#define DCORE3_RTR6_DBG_ADDR_SPECIAL_BASE 0x4775E80ull
+#define DCORE3_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE3_RTR7_CTRL_BASE 0x4778000ull
+#define DCORE3_RTR7_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR7_CTRL_SECTION 0xE800
+#define DCORE3_RTR7_CTRL_SPECIAL_BASE 0x4778E80ull
+#define DCORE3_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR7_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR7_H3_BASE 0x4779000ull
+#define DCORE3_RTR7_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR7_H3_SECTION 0xE800
+#define DCORE3_RTR7_H3_SPECIAL_BASE 0x4779E80ull
+#define DCORE3_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR7_H3_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x477A000ull
+#define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x477A200ull
+#define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x477A400ull
+#define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x477A600ull
+#define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_RTR7_MSTR_IF_E2E_CRDT_BASE 0x477A800ull
+#define DCORE3_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_RTR7_MSTR_IF_AXUSER_BASE 0x477AA80ull
+#define DCORE3_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR7_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_RTR7_MSTR_IF_DBG_HBW_BASE 0x477AB00ull
+#define DCORE3_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_RTR7_MSTR_IF_DBG_LBW_BASE 0x477AB80ull
+#define DCORE3_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_RTR7_MSTR_IF_CORE_HBW_BASE 0x477AC00ull
+#define DCORE3_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_RTR7_MSTR_IF_CORE_LBW_BASE 0x477AD80ull
+#define DCORE3_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_RTR7_MSTR_IF_SPECIAL_BASE 0x477AE80ull
+#define DCORE3_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR7_ADD_DEC_HBW_BASE 0x477B000ull
+#define DCORE3_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR7_ADD_DEC_HBW_SECTION 0x4000
+#define DCORE3_RTR7_ADD_DEC_LBW_BASE 0x477B400ull
+#define DCORE3_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR7_ADD_DEC_LBW_SECTION 0xA800
+#define DCORE3_RTR7_ADD_DEC_SPECIAL_BASE 0x477BE80ull
+#define DCORE3_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR7_BASE 0x477C000ull
+#define DCORE3_RTR7_MAX_OFFSET 0x1000
+#define DCORE3_RTR7_SECTION 0x3000
+#define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x477C300ull
+#define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR7_HBW_RD_RS_LL_STAT_BASE 0x477C340ull
+#define DCORE3_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x477C380ull
+#define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR7_HBW_WR_RS_LL_STAT_BASE 0x477C3C0ull
+#define DCORE3_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x477C400ull
+#define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR7_LBW_RD_RS_LL_STAT_BASE 0x477C440ull
+#define DCORE3_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x477C480ull
+#define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR7_LBW_WR_RS_LL_STAT_BASE 0x477C4C0ull
+#define DCORE3_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR7_HBW_MFIFO_BASE 0x477C500ull
+#define DCORE3_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_HBW_MFIFO_SECTION 0x4000
+#define DCORE3_RTR7_E2E_RD_LL_STAT_BASE 0x477C540ull
+#define DCORE3_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_E2E_RD_LL_STAT_SECTION 0x4000
+#define DCORE3_RTR7_E2E_WR_LL_STAT_BASE 0x477C580ull
+#define DCORE3_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_E2E_WR_LL_STAT_SECTION 0x8000
+#define DCORE3_RTR7_RTR_HBW_XACT_STAT_BASE 0x477C600ull
+#define DCORE3_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR7_RTR_LBW_XACT_STAT_BASE 0x477C680ull
+#define DCORE3_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define DCORE3_RTR7_RTR_E2E_XACT_STAT_BASE 0x477C700ull
+#define DCORE3_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define DCORE3_RTR7_SPECIAL_BASE 0x477CE80ull
+#define DCORE3_RTR7_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR7_SPECIAL_SECTION 0x1800
+#define DCORE3_RTR7_DBG_ADDR_BASE 0x477D000ull
+#define DCORE3_RTR7_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR7_DBG_ADDR_SECTION 0xE800
+#define DCORE3_RTR7_DBG_ADDR_SPECIAL_BASE 0x477DE80ull
+#define DCORE3_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define DCORE3_SRAM0_BANK_BASE 0x4780000ull
+#define DCORE3_SRAM0_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM0_BANK_SECTION 0xE800
+#define DCORE3_SRAM0_BANK_SPECIAL_BASE 0x4780E80ull
+#define DCORE3_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM0_BANK_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM0_RTR_BASE 0x4781000ull
+#define DCORE3_SRAM0_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM0_RTR_SECTION 0xE800
+#define DCORE3_SRAM0_RTR_SPECIAL_BASE 0x4781E80ull
+#define DCORE3_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM0_RTR_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4782000ull
+#define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4782100ull
+#define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4782200ull
+#define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4782300ull
+#define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4782400ull
+#define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4782500ull
+#define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4782600ull
+#define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4782700ull
+#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4782780ull
+#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4782800ull
+#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4782880ull
+#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4782900ull
+#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4782980ull
+#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4782A00ull
+#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4782A80ull
+#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE3_SRAM0_DBG_CNT_SPECIAL_BASE 0x4782E80ull
+#define DCORE3_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE3_SRAM1_BANK_BASE 0x4788000ull
+#define DCORE3_SRAM1_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM1_BANK_SECTION 0xE800
+#define DCORE3_SRAM1_BANK_SPECIAL_BASE 0x4788E80ull
+#define DCORE3_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM1_BANK_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM1_RTR_BASE 0x4789000ull
+#define DCORE3_SRAM1_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM1_RTR_SECTION 0xE800
+#define DCORE3_SRAM1_RTR_SPECIAL_BASE 0x4789E80ull
+#define DCORE3_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM1_RTR_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x478A000ull
+#define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x478A100ull
+#define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x478A200ull
+#define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x478A300ull
+#define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x478A400ull
+#define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x478A500ull
+#define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x478A600ull
+#define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x478A700ull
+#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x478A780ull
+#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x478A800ull
+#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x478A880ull
+#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x478A900ull
+#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x478A980ull
+#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x478AA00ull
+#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x478AA80ull
+#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE3_SRAM1_DBG_CNT_SPECIAL_BASE 0x478AE80ull
+#define DCORE3_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE3_SRAM2_BANK_BASE 0x4790000ull
+#define DCORE3_SRAM2_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM2_BANK_SECTION 0xE800
+#define DCORE3_SRAM2_BANK_SPECIAL_BASE 0x4790E80ull
+#define DCORE3_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM2_BANK_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM2_RTR_BASE 0x4791000ull
+#define DCORE3_SRAM2_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM2_RTR_SECTION 0xE800
+#define DCORE3_SRAM2_RTR_SPECIAL_BASE 0x4791E80ull
+#define DCORE3_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM2_RTR_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4792000ull
+#define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4792100ull
+#define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4792200ull
+#define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4792300ull
+#define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4792400ull
+#define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4792500ull
+#define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4792600ull
+#define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4792700ull
+#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4792780ull
+#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4792800ull
+#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4792880ull
+#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4792900ull
+#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4792980ull
+#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4792A00ull
+#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4792A80ull
+#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE3_SRAM2_DBG_CNT_SPECIAL_BASE 0x4792E80ull
+#define DCORE3_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE3_SRAM3_BANK_BASE 0x4798000ull
+#define DCORE3_SRAM3_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM3_BANK_SECTION 0xE800
+#define DCORE3_SRAM3_BANK_SPECIAL_BASE 0x4798E80ull
+#define DCORE3_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM3_BANK_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM3_RTR_BASE 0x4799000ull
+#define DCORE3_SRAM3_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM3_RTR_SECTION 0xE800
+#define DCORE3_SRAM3_RTR_SPECIAL_BASE 0x4799E80ull
+#define DCORE3_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM3_RTR_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x479A000ull
+#define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x479A100ull
+#define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x479A200ull
+#define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x479A300ull
+#define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x479A400ull
+#define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x479A500ull
+#define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x479A600ull
+#define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x479A700ull
+#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x479A780ull
+#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x479A800ull
+#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x479A880ull
+#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x479A900ull
+#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x479A980ull
+#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x479AA00ull
+#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x479AA80ull
+#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE3_SRAM3_DBG_CNT_SPECIAL_BASE 0x479AE80ull
+#define DCORE3_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE3_SRAM4_BANK_BASE 0x47A0000ull
+#define DCORE3_SRAM4_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM4_BANK_SECTION 0xE800
+#define DCORE3_SRAM4_BANK_SPECIAL_BASE 0x47A0E80ull
+#define DCORE3_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM4_BANK_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM4_RTR_BASE 0x47A1000ull
+#define DCORE3_SRAM4_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM4_RTR_SECTION 0xE800
+#define DCORE3_SRAM4_RTR_SPECIAL_BASE 0x47A1E80ull
+#define DCORE3_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM4_RTR_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47A2000ull
+#define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47A2100ull
+#define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47A2200ull
+#define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47A2300ull
+#define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47A2400ull
+#define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47A2500ull
+#define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47A2600ull
+#define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47A2700ull
+#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47A2780ull
+#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47A2800ull
+#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47A2880ull
+#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47A2900ull
+#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47A2980ull
+#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47A2A00ull
+#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47A2A80ull
+#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE3_SRAM4_DBG_CNT_SPECIAL_BASE 0x47A2E80ull
+#define DCORE3_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE3_SRAM5_BANK_BASE 0x47A8000ull
+#define DCORE3_SRAM5_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM5_BANK_SECTION 0xE800
+#define DCORE3_SRAM5_BANK_SPECIAL_BASE 0x47A8E80ull
+#define DCORE3_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM5_BANK_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM5_RTR_BASE 0x47A9000ull
+#define DCORE3_SRAM5_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM5_RTR_SECTION 0xE800
+#define DCORE3_SRAM5_RTR_SPECIAL_BASE 0x47A9E80ull
+#define DCORE3_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM5_RTR_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47AA000ull
+#define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47AA100ull
+#define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47AA200ull
+#define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47AA300ull
+#define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47AA400ull
+#define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47AA500ull
+#define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47AA600ull
+#define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47AA700ull
+#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47AA780ull
+#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47AA800ull
+#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47AA880ull
+#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47AA900ull
+#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47AA980ull
+#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47AAA00ull
+#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47AAA80ull
+#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE3_SRAM5_DBG_CNT_SPECIAL_BASE 0x47AAE80ull
+#define DCORE3_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE3_SRAM6_BANK_BASE 0x47B0000ull
+#define DCORE3_SRAM6_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM6_BANK_SECTION 0xE800
+#define DCORE3_SRAM6_BANK_SPECIAL_BASE 0x47B0E80ull
+#define DCORE3_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM6_BANK_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM6_RTR_BASE 0x47B1000ull
+#define DCORE3_SRAM6_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM6_RTR_SECTION 0xE800
+#define DCORE3_SRAM6_RTR_SPECIAL_BASE 0x47B1E80ull
+#define DCORE3_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM6_RTR_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47B2000ull
+#define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47B2100ull
+#define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47B2200ull
+#define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47B2300ull
+#define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47B2400ull
+#define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47B2500ull
+#define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47B2600ull
+#define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47B2700ull
+#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47B2780ull
+#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47B2800ull
+#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47B2880ull
+#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47B2900ull
+#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47B2980ull
+#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47B2A00ull
+#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47B2A80ull
+#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE3_SRAM6_DBG_CNT_SPECIAL_BASE 0x47B2E80ull
+#define DCORE3_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE3_SRAM7_BANK_BASE 0x47B8000ull
+#define DCORE3_SRAM7_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM7_BANK_SECTION 0xE800
+#define DCORE3_SRAM7_BANK_SPECIAL_BASE 0x47B8E80ull
+#define DCORE3_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM7_BANK_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM7_RTR_BASE 0x47B9000ull
+#define DCORE3_SRAM7_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM7_RTR_SECTION 0xE800
+#define DCORE3_SRAM7_RTR_SPECIAL_BASE 0x47B9E80ull
+#define DCORE3_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM7_RTR_SPECIAL_SECTION 0x1800
+#define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47BA000ull
+#define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47BA100ull
+#define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47BA200ull
+#define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47BA300ull
+#define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47BA400ull
+#define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47BA500ull
+#define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47BA600ull
+#define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47BA700ull
+#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47BA780ull
+#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47BA800ull
+#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47BA880ull
+#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47BA900ull
+#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47BA980ull
+#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47BAA00ull
+#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47BAA80ull
+#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define DCORE3_SRAM7_DBG_CNT_SPECIAL_BASE 0x47BAE80ull
+#define DCORE3_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180
+#define DCORE3_EDMA0_QM_DCCM_BASE 0x47C0000ull
+#define DCORE3_EDMA0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_EDMA0_QM_DCCM_SECTION 0x8000
+#define DCORE3_EDMA0_QM_ARC_AUX_BASE 0x47C8000ull
+#define DCORE3_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_QM_ARC_AUX_SECTION 0xE800
+#define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x47C8E80ull
+#define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE3_EDMA0_QM_BASE 0x47CA000ull
+#define DCORE3_EDMA0_QM_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_QM_SECTION 0x9000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x47CA900ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x47CA908ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x47CA910ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x47CA918ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x47CA920ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x47CA928ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x47CA930ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x47CA938ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x47CA940ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x47CA948ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x47CA950ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x47CA958ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x47CA960ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x47CA968ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x47CA970ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x47CA978ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_EDMA0_QM_AXUSER_SECURED_BASE 0x47CAB00ull
+#define DCORE3_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_EDMA0_QM_AXUSER_NONSECURED_BASE 0x47CAB80ull
+#define DCORE3_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_EDMA0_QM_DBG_HBW_BASE 0x47CAC00ull
+#define DCORE3_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA0_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_EDMA0_QM_DBG_LBW_BASE 0x47CAC80ull
+#define DCORE3_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA0_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_EDMA0_QM_CGM_BASE 0x47CAD80ull
+#define DCORE3_EDMA0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_EDMA0_QM_CGM_SECTION 0x1000
+#define DCORE3_EDMA0_QM_SPECIAL_BASE 0x47CAE80ull
+#define DCORE3_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA0_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_EDMA0_CORE_BASE 0x47CB000ull
+#define DCORE3_EDMA0_CORE_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_CORE_SECTION 0x8000
+#define DCORE3_EDMA0_CORE_CTX_AXUSER_BASE 0x47CB800ull
+#define DCORE3_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000
+#define DCORE3_EDMA0_CORE_CTX_BASE 0x47CB860ull
+#define DCORE3_EDMA0_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE3_EDMA0_CORE_CTX_SECTION 0x5A00
+#define DCORE3_EDMA0_CORE_KDMA_CGM_BASE 0x47CBE00ull
+#define DCORE3_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE3_EDMA0_CORE_KDMA_CGM_SECTION 0x8000
+#define DCORE3_EDMA0_CORE_SPECIAL_BASE 0x47CBE80ull
+#define DCORE3_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA0_CORE_SPECIAL_SECTION 0x1800
+#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x47CC000ull
+#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x47CC200ull
+#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x47CC400ull
+#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x47CC600ull
+#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x47CC800ull
+#define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_EDMA0_MSTR_IF_AXUSER_BASE 0x47CCA80ull
+#define DCORE3_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_EDMA0_MSTR_IF_DBG_HBW_BASE 0x47CCB00ull
+#define DCORE3_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_EDMA0_MSTR_IF_DBG_LBW_BASE 0x47CCB80ull
+#define DCORE3_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_EDMA0_MSTR_IF_CORE_HBW_BASE 0x47CCC00ull
+#define DCORE3_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_EDMA0_MSTR_IF_CORE_LBW_BASE 0x47CCD80ull
+#define DCORE3_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_EDMA0_MSTR_IF_SPECIAL_BASE 0x47CCE80ull
+#define DCORE3_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE3_EDMA1_QM_DCCM_BASE 0x47D0000ull
+#define DCORE3_EDMA1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_EDMA1_QM_DCCM_SECTION 0x8000
+#define DCORE3_EDMA1_QM_ARC_AUX_BASE 0x47D8000ull
+#define DCORE3_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_QM_ARC_AUX_SECTION 0xE800
+#define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x47D8E80ull
+#define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define DCORE3_EDMA1_QM_BASE 0x47DA000ull
+#define DCORE3_EDMA1_QM_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_QM_SECTION 0x9000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x47DA900ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x47DA908ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x47DA910ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x47DA918ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x47DA920ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x47DA928ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x47DA930ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x47DA938ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x47DA940ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x47DA948ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x47DA950ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x47DA958ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x47DA960ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x47DA968ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x47DA970ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x47DA978ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define DCORE3_EDMA1_QM_AXUSER_SECURED_BASE 0x47DAB00ull
+#define DCORE3_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000
+#define DCORE3_EDMA1_QM_AXUSER_NONSECURED_BASE 0x47DAB80ull
+#define DCORE3_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define DCORE3_EDMA1_QM_DBG_HBW_BASE 0x47DAC00ull
+#define DCORE3_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA1_QM_DBG_HBW_SECTION 0x8000
+#define DCORE3_EDMA1_QM_DBG_LBW_BASE 0x47DAC80ull
+#define DCORE3_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA1_QM_DBG_LBW_SECTION 0x1000
+#define DCORE3_EDMA1_QM_CGM_BASE 0x47DAD80ull
+#define DCORE3_EDMA1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_EDMA1_QM_CGM_SECTION 0x1000
+#define DCORE3_EDMA1_QM_SPECIAL_BASE 0x47DAE80ull
+#define DCORE3_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA1_QM_SPECIAL_SECTION 0x1800
+#define DCORE3_EDMA1_CORE_BASE 0x47DB000ull
+#define DCORE3_EDMA1_CORE_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_CORE_SECTION 0x8000
+#define DCORE3_EDMA1_CORE_CTX_AXUSER_BASE 0x47DB800ull
+#define DCORE3_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000
+#define DCORE3_EDMA1_CORE_CTX_BASE 0x47DB860ull
+#define DCORE3_EDMA1_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE3_EDMA1_CORE_CTX_SECTION 0x5A00
+#define DCORE3_EDMA1_CORE_KDMA_CGM_BASE 0x47DBE00ull
+#define DCORE3_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE3_EDMA1_CORE_KDMA_CGM_SECTION 0x8000
+#define DCORE3_EDMA1_CORE_SPECIAL_BASE 0x47DBE80ull
+#define DCORE3_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA1_CORE_SPECIAL_SECTION 0x1800
+#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x47DC000ull
+#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x47DC200ull
+#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x47DC400ull
+#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x47DC600ull
+#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x47DC800ull
+#define DCORE3_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_EDMA1_MSTR_IF_AXUSER_BASE 0x47DCA80ull
+#define DCORE3_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_EDMA1_MSTR_IF_DBG_HBW_BASE 0x47DCB00ull
+#define DCORE3_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_EDMA1_MSTR_IF_DBG_LBW_BASE 0x47DCB80ull
+#define DCORE3_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_EDMA1_MSTR_IF_CORE_HBW_BASE 0x47DCC00ull
+#define DCORE3_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_EDMA1_MSTR_IF_CORE_LBW_BASE 0x47DCD80ull
+#define DCORE3_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_EDMA1_MSTR_IF_SPECIAL_BASE 0x47DCE80ull
+#define DCORE3_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define DCORE3_DEC0_CMD_BASE 0x47E0000ull
+#define DCORE3_DEC0_CMD_MAX_OFFSET 0x1100
+#define DCORE3_DEC0_CMD_SECTION 0x1000
+#define DCORE3_DEC0_VSI_BASE 0x47E1000ull
+#define DCORE3_DEC0_VSI_MAX_OFFSET 0x6FC0
+#define DCORE3_DEC0_VSI_SECTION 0x1000
+#define DCORE3_DEC0_L2C_BASE 0x47E2000ull
+#define DCORE3_DEC0_L2C_MAX_OFFSET 0x39C0
+#define DCORE3_DEC0_L2C_SECTION 0x1000
+#define DCORE3_VDEC0_BRDG_CTRL_BASE 0x47E3000ull
+#define DCORE3_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_BRDG_CTRL_SECTION 0x8000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x47E3800ull
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x47E3900ull
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x47E3A00ull
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x47E3B00ull
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x47E3C00ull
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define DCORE3_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x47E3E80ull
+#define DCORE3_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE3_VDEC0_CTRL_BASE 0x47E4000ull
+#define DCORE3_VDEC0_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_CTRL_SECTION 0xE800
+#define DCORE3_VDEC0_CTRL_SPECIAL_BASE 0x47E4E80ull
+#define DCORE3_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_VDEC0_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x47E5000ull
+#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x47E5200ull
+#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x47E5400ull
+#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x47E5600ull
+#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x47E5800ull
+#define DCORE3_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_VDEC0_MSTR_IF_AXUSER_BASE 0x47E5A80ull
+#define DCORE3_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_VDEC0_MSTR_IF_DBG_HBW_BASE 0x47E5B00ull
+#define DCORE3_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_VDEC0_MSTR_IF_DBG_LBW_BASE 0x47E5B80ull
+#define DCORE3_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_VDEC0_MSTR_IF_CORE_HBW_BASE 0x47E5C00ull
+#define DCORE3_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_VDEC0_MSTR_IF_CORE_LBW_BASE 0x47E5D80ull
+#define DCORE3_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_VDEC0_MSTR_IF_SPECIAL_BASE 0x47E5E80ull
+#define DCORE3_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
+#define DCORE3_DEC1_CMD_BASE 0x47F0000ull
+#define DCORE3_DEC1_CMD_MAX_OFFSET 0x1100
+#define DCORE3_DEC1_CMD_SECTION 0x1000
+#define DCORE3_DEC1_VSI_BASE 0x47F1000ull
+#define DCORE3_DEC1_VSI_MAX_OFFSET 0x6FC0
+#define DCORE3_DEC1_VSI_SECTION 0x1000
+#define DCORE3_DEC1_L2C_BASE 0x47F2000ull
+#define DCORE3_DEC1_L2C_MAX_OFFSET 0x39C0
+#define DCORE3_DEC1_L2C_SECTION 0x1000
+#define DCORE3_VDEC1_BRDG_CTRL_BASE 0x47F3000ull
+#define DCORE3_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_BRDG_CTRL_SECTION 0x8000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x47F3800ull
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x47F3900ull
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x47F3A00ull
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x47F3B00ull
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x47F3C00ull
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define DCORE3_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x47F3E80ull
+#define DCORE3_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE3_VDEC1_CTRL_BASE 0x47F4000ull
+#define DCORE3_VDEC1_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_CTRL_SECTION 0xE800
+#define DCORE3_VDEC1_CTRL_SPECIAL_BASE 0x47F4E80ull
+#define DCORE3_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_VDEC1_CTRL_SPECIAL_SECTION 0x1800
+#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x47F5000ull
+#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x47F5200ull
+#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x47F5400ull
+#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x47F5600ull
+#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define DCORE3_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x47F5800ull
+#define DCORE3_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define DCORE3_VDEC1_MSTR_IF_AXUSER_BASE 0x47F5A80ull
+#define DCORE3_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define DCORE3_VDEC1_MSTR_IF_DBG_HBW_BASE 0x47F5B00ull
+#define DCORE3_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define DCORE3_VDEC1_MSTR_IF_DBG_LBW_BASE 0x47F5B80ull
+#define DCORE3_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define DCORE3_VDEC1_MSTR_IF_CORE_HBW_BASE 0x47F5C00ull
+#define DCORE3_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define DCORE3_VDEC1_MSTR_IF_CORE_LBW_BASE 0x47F5D80ull
+#define DCORE3_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define DCORE3_VDEC1_MSTR_IF_SPECIAL_BASE 0x47F5E80ull
+#define DCORE3_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180
+#define GIC_BASE 0x4800000ull
+#define GIC_MAX_OFFSET 0x10000
+#define GIC_SECTION 0x401000
+#define PCIE_WRAP_BASE 0x4C01000ull
+#define PCIE_WRAP_MAX_OFFSET 0x1000
+#define PCIE_WRAP_SECTION 0xE800
+#define PCIE_WRAP_SPECIAL_BASE 0x4C01E80ull
+#define PCIE_WRAP_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_WRAP_SPECIAL_SECTION 0x1800
+#define PCIE_DBI_BASE 0x4C02000ull
+#define PCIE_DBI_MAX_OFFSET 0xC040
+#define PCIE_DBI_SECTION 0x2000
+#define PCIE_CORE_BASE 0x4C04000ull
+#define PCIE_CORE_MAX_OFFSET 0x1000
+#define PCIE_CORE_SECTION 0xE800
+#define PCIE_CORE_SPECIAL_BASE 0x4C04E80ull
+#define PCIE_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_CORE_SPECIAL_SECTION 0x2180
+#define PCIE_AUX_BASE 0x4C07000ull
+#define PCIE_AUX_MAX_OFFSET 0x1000
+#define PCIE_AUX_SECTION 0xE800
+#define PCIE_AUX_SPECIAL_BASE 0x4C07E80ull
+#define PCIE_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_AUX_SPECIAL_SECTION 0x8180
+#define PCIE_PHY_BASE 0x4C10000ull
+#define PCIE_PHY_MAX_OFFSET 0x1000
+#define PCIE_PHY_SECTION 0xE800
+#define PCIE_PHY_SPECIAL_BASE 0x4C10E80ull
+#define PCIE_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_PHY_SPECIAL_SECTION 0x2180
+#define PCIE_MSI_BASE 0x4C13000ull
+#define PCIE_MSI_MAX_OFFSET 0x8000
+#define PCIE_MSI_SECTION 0x1000
+#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C14000ull
+#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C14200ull
+#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C14400ull
+#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C14600ull
+#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define PCIE_ELBI_RR_MSTR_IF_E2E_CRDT_BASE 0x4C14800ull
+#define PCIE_ELBI_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PCIE_ELBI_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define PCIE_ELBI_RR_MSTR_IF_AXUSER_BASE 0x4C14A80ull
+#define PCIE_ELBI_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PCIE_ELBI_RR_MSTR_IF_AXUSER_SECTION 0x8000
+#define PCIE_ELBI_RR_MSTR_IF_DBG_HBW_BASE 0x4C14B00ull
+#define PCIE_ELBI_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PCIE_ELBI_RR_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define PCIE_ELBI_RR_MSTR_IF_DBG_LBW_BASE 0x4C14B80ull
+#define PCIE_ELBI_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PCIE_ELBI_RR_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define PCIE_ELBI_RR_MSTR_IF_CORE_HBW_BASE 0x4C14C00ull
+#define PCIE_ELBI_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PCIE_ELBI_RR_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define PCIE_ELBI_RR_MSTR_IF_CORE_LBW_BASE 0x4C14D80ull
+#define PCIE_ELBI_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PCIE_ELBI_RR_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define PCIE_ELBI_RR_MSTR_IF_SPECIAL_BASE 0x4C14E80ull
+#define PCIE_ELBI_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_ELBI_RR_MSTR_IF_SPECIAL_SECTION 0x1800
+#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C15000ull
+#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C15200ull
+#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C15400ull
+#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C15600ull
+#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define PCIE_MSTR_RR_MSTR_IF_E2E_CRDT_BASE 0x4C15800ull
+#define PCIE_MSTR_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PCIE_MSTR_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define PCIE_MSTR_RR_MSTR_IF_AXUSER_BASE 0x4C15A80ull
+#define PCIE_MSTR_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PCIE_MSTR_RR_MSTR_IF_AXUSER_SECTION 0x8000
+#define PCIE_MSTR_RR_MSTR_IF_DBG_HBW_BASE 0x4C15B00ull
+#define PCIE_MSTR_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PCIE_MSTR_RR_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define PCIE_MSTR_RR_MSTR_IF_DBG_LBW_BASE 0x4C15B80ull
+#define PCIE_MSTR_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PCIE_MSTR_RR_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define PCIE_MSTR_RR_MSTR_IF_CORE_HBW_BASE 0x4C15C00ull
+#define PCIE_MSTR_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PCIE_MSTR_RR_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define PCIE_MSTR_RR_MSTR_IF_CORE_LBW_BASE 0x4C15D80ull
+#define PCIE_MSTR_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PCIE_MSTR_RR_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define PCIE_MSTR_RR_MSTR_IF_SPECIAL_BASE 0x4C15E80ull
+#define PCIE_MSTR_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_MSTR_RR_MSTR_IF_SPECIAL_SECTION 0x1800
+#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C16000ull
+#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C16200ull
+#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C16400ull
+#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C16600ull
+#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define PCIE_LBW_RR_MSTR_IF_E2E_CRDT_BASE 0x4C16800ull
+#define PCIE_LBW_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PCIE_LBW_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define PCIE_LBW_RR_MSTR_IF_AXUSER_BASE 0x4C16A80ull
+#define PCIE_LBW_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PCIE_LBW_RR_MSTR_IF_AXUSER_SECTION 0x8000
+#define PCIE_LBW_RR_MSTR_IF_DBG_HBW_BASE 0x4C16B00ull
+#define PCIE_LBW_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PCIE_LBW_RR_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define PCIE_LBW_RR_MSTR_IF_DBG_LBW_BASE 0x4C16B80ull
+#define PCIE_LBW_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PCIE_LBW_RR_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define PCIE_LBW_RR_MSTR_IF_CORE_HBW_BASE 0x4C16C00ull
+#define PCIE_LBW_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PCIE_LBW_RR_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define PCIE_LBW_RR_MSTR_IF_CORE_LBW_BASE 0x4C16D80ull
+#define PCIE_LBW_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PCIE_LBW_RR_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define PCIE_LBW_RR_MSTR_IF_SPECIAL_BASE 0x4C16E80ull
+#define PCIE_LBW_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_LBW_RR_MSTR_IF_SPECIAL_SECTION 0x1800
+#define PCIE_MSIX_BASE 0x4C17000ull
+#define PCIE_MSIX_MAX_OFFSET 0x4000
+#define PCIE_MSIX_SECTION 0x29000
+#define PSOC_I2C_M0_BASE 0x4C40000ull
+#define PSOC_I2C_M0_MAX_OFFSET 0x1000
+#define PSOC_I2C_M0_SECTION 0x1000
+#define PSOC_I2C_M1_BASE 0x4C41000ull
+#define PSOC_I2C_M1_MAX_OFFSET 0x1000
+#define PSOC_I2C_M1_SECTION 0x1000
+#define PSOC_I2C_S_BASE 0x4C42000ull
+#define PSOC_I2C_S_MAX_OFFSET 0x1000
+#define PSOC_I2C_S_SECTION 0x1000
+#define PSOC_SPI_BASE 0x4C43000ull
+#define PSOC_SPI_MAX_OFFSET 0x1000
+#define PSOC_SPI_SECTION 0x1000
+#define PSOC_QSPI_BASE 0x4C44000ull
+#define PSOC_QSPI_MAX_OFFSET 0x1000
+#define PSOC_QSPI_SECTION 0x1000
+#define PSOC_UART_0_BASE 0x4C45000ull
+#define PSOC_UART_0_MAX_OFFSET 0x1000
+#define PSOC_UART_0_SECTION 0x1000
+#define PSOC_UART_1_BASE 0x4C46000ull
+#define PSOC_UART_1_MAX_OFFSET 0x1000
+#define PSOC_UART_1_SECTION 0x1000
+#define PSOC_TIMER_BASE 0x4C47000ull
+#define PSOC_TIMER_MAX_OFFSET 0x1000
+#define PSOC_TIMER_SECTION 0x1000
+#define PSOC_WDOG_BASE 0x4C48000ull
+#define PSOC_WDOG_MAX_OFFSET 0x1000
+#define PSOC_WDOG_SECTION 0x1000
+#define PSOC_TIMESTAMP_BASE 0x4C49000ull
+#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000
+#define PSOC_TIMESTAMP_SECTION 0x1000
+#define PSOC_EFUSE_BASE 0x4C4A000ull
+#define PSOC_EFUSE_MAX_OFFSET 0x1000
+#define PSOC_EFUSE_SECTION 0xE800
+#define PSOC_EFUSE_SPECIAL_BASE 0x4C4AE80ull
+#define PSOC_EFUSE_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_EFUSE_SPECIAL_SECTION 0x1800
+#define PSOC_GLOBAL_CONF_BASE 0x4C4B000ull
+#define PSOC_GLOBAL_CONF_MAX_OFFSET 0x1000
+#define PSOC_GLOBAL_CONF_SECTION 0xE800
+#define PSOC_GLOBAL_CONF_SPECIAL_BASE 0x4C4BE80ull
+#define PSOC_GLOBAL_CONF_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_GLOBAL_CONF_SPECIAL_SECTION 0x1800
+#define PSOC_GPIO0_BASE 0x4C4C000ull
+#define PSOC_GPIO0_MAX_OFFSET 0x1000
+#define PSOC_GPIO0_SECTION 0x1000
+#define PSOC_GPIO1_BASE 0x4C4D000ull
+#define PSOC_GPIO1_MAX_OFFSET 0x1000
+#define PSOC_GPIO1_SECTION 0x1000
+#define PSOC_BTL_BASE 0x4C4E000ull
+#define PSOC_BTL_MAX_OFFSET 0x1000
+#define PSOC_BTL_SECTION 0xE800
+#define PSOC_BTL_SPECIAL_BASE 0x4C4EE80ull
+#define PSOC_BTL_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_BTL_SPECIAL_SECTION 0x1800
+#define PSOC_CS_TRACE_BASE 0x4C4F000ull
+#define PSOC_CS_TRACE_MAX_OFFSET 0x1000
+#define PSOC_CS_TRACE_SECTION 0xE800
+#define PSOC_CS_TRACE_SPECIAL_BASE 0x4C4FE80ull
+#define PSOC_CS_TRACE_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_CS_TRACE_SPECIAL_SECTION 0x1800
+#define PSOC_GPIO2_BASE 0x4C50000ull
+#define PSOC_GPIO2_MAX_OFFSET 0x1000
+#define PSOC_GPIO2_SECTION 0x1000
+#define PSOC_GPIO3_BASE 0x4C51000ull
+#define PSOC_GPIO3_MAX_OFFSET 0x1000
+#define PSOC_GPIO3_SECTION 0x2000
+#define PSOC_DFT_EFUSE_BASE 0x4C53000ull
+#define PSOC_DFT_EFUSE_MAX_OFFSET 0x1000
+#define PSOC_DFT_EFUSE_SECTION 0xE800
+#define PSOC_DFT_EFUSE_SPECIAL_BASE 0x4C53E80ull
+#define PSOC_DFT_EFUSE_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_DFT_EFUSE_SPECIAL_SECTION 0x1800
+#define PSOC_RPM_0_BASE 0x4C54000ull
+#define PSOC_RPM_0_MAX_OFFSET 0x1000
+#define PSOC_RPM_0_SECTION 0xE800
+#define PSOC_RPM_0_SPECIAL_BASE 0x4C54E80ull
+#define PSOC_RPM_0_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_RPM_0_SPECIAL_SECTION 0x1800
+#define PSOC_RPM_1_BASE 0x4C55000ull
+#define PSOC_RPM_1_MAX_OFFSET 0x1000
+#define PSOC_RPM_1_SECTION 0xE800
+#define PSOC_RPM_1_SPECIAL_BASE 0x4C55E80ull
+#define PSOC_RPM_1_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_RPM_1_SPECIAL_SECTION 0x1800
+#define PSOC_GPIO4_BASE 0x4C56000ull
+#define PSOC_GPIO4_MAX_OFFSET 0x1000
+#define PSOC_GPIO4_SECTION 0x1000
+#define PSOC_GPIO5_BASE 0x4C57000ull
+#define PSOC_GPIO5_MAX_OFFSET 0x1000
+#define PSOC_GPIO5_SECTION 0x1000
+#define PSOC_PID_BASE 0x4C58000ull
+#define PSOC_PID_MAX_OFFSET 0x1000
+#define PSOC_PID_SECTION 0xE800
+#define PSOC_PID_SPECIAL_BASE 0x4C58E80ull
+#define PSOC_PID_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_PID_SPECIAL_SECTION 0x1800
+#define PSOC_ARC0_CFG_BASE 0x4C59000ull
+#define PSOC_ARC0_CFG_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CFG_SECTION 0xE800
+#define PSOC_ARC0_CFG_SPECIAL_BASE 0x4C59E80ull
+#define PSOC_ARC0_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_ARC0_CFG_SPECIAL_SECTION 0x1800
+#define PSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE 0x4C5A000ull
+#define PSOC_ARC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PSOC_ARC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define PSOC_ARC0_MSTR_IF_RR_PRVT_HBW_BASE 0x4C5A200ull
+#define PSOC_ARC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PSOC_ARC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define PSOC_ARC0_MSTR_IF_RR_SHRD_LBW_BASE 0x4C5A400ull
+#define PSOC_ARC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PSOC_ARC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define PSOC_ARC0_MSTR_IF_RR_PRVT_LBW_BASE 0x4C5A600ull
+#define PSOC_ARC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PSOC_ARC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define PSOC_ARC0_MSTR_IF_E2E_CRDT_BASE 0x4C5A800ull
+#define PSOC_ARC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PSOC_ARC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define PSOC_ARC0_MSTR_IF_AXUSER_BASE 0x4C5AA80ull
+#define PSOC_ARC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PSOC_ARC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define PSOC_ARC0_MSTR_IF_DBG_HBW_BASE 0x4C5AB00ull
+#define PSOC_ARC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PSOC_ARC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define PSOC_ARC0_MSTR_IF_DBG_LBW_BASE 0x4C5AB80ull
+#define PSOC_ARC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PSOC_ARC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define PSOC_ARC0_MSTR_IF_CORE_HBW_BASE 0x4C5AC00ull
+#define PSOC_ARC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PSOC_ARC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define PSOC_ARC0_MSTR_IF_CORE_LBW_BASE 0x4C5AD80ull
+#define PSOC_ARC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PSOC_ARC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define PSOC_ARC0_MSTR_IF_SPECIAL_BASE 0x4C5AE80ull
+#define PSOC_ARC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_ARC0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define PSOC_ARC0_AUX_BASE 0x4C5B000ull
+#define PSOC_ARC0_AUX_MAX_OFFSET 0x1000
+#define PSOC_ARC0_AUX_SECTION 0xE800
+#define PSOC_ARC0_AUX_SPECIAL_BASE 0x4C5BE80ull
+#define PSOC_ARC0_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_ARC0_AUX_SPECIAL_SECTION 0x1800
+#define PSOC_ARC1_CFG_BASE 0x4C5C000ull
+#define PSOC_ARC1_CFG_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CFG_SECTION 0xE800
+#define PSOC_ARC1_CFG_SPECIAL_BASE 0x4C5CE80ull
+#define PSOC_ARC1_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_ARC1_CFG_SPECIAL_SECTION 0x1800
+#define PSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE 0x4C5D000ull
+#define PSOC_ARC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PSOC_ARC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define PSOC_ARC1_MSTR_IF_RR_PRVT_HBW_BASE 0x4C5D200ull
+#define PSOC_ARC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PSOC_ARC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define PSOC_ARC1_MSTR_IF_RR_SHRD_LBW_BASE 0x4C5D400ull
+#define PSOC_ARC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PSOC_ARC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define PSOC_ARC1_MSTR_IF_RR_PRVT_LBW_BASE 0x4C5D600ull
+#define PSOC_ARC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PSOC_ARC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define PSOC_ARC1_MSTR_IF_E2E_CRDT_BASE 0x4C5D800ull
+#define PSOC_ARC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PSOC_ARC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define PSOC_ARC1_MSTR_IF_AXUSER_BASE 0x4C5DA80ull
+#define PSOC_ARC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PSOC_ARC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define PSOC_ARC1_MSTR_IF_DBG_HBW_BASE 0x4C5DB00ull
+#define PSOC_ARC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PSOC_ARC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define PSOC_ARC1_MSTR_IF_DBG_LBW_BASE 0x4C5DB80ull
+#define PSOC_ARC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PSOC_ARC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define PSOC_ARC1_MSTR_IF_CORE_HBW_BASE 0x4C5DC00ull
+#define PSOC_ARC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PSOC_ARC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define PSOC_ARC1_MSTR_IF_CORE_LBW_BASE 0x4C5DD80ull
+#define PSOC_ARC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PSOC_ARC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define PSOC_ARC1_MSTR_IF_SPECIAL_BASE 0x4C5DE80ull
+#define PSOC_ARC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_ARC1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define PSOC_ARC1_AUX_BASE 0x4C5E000ull
+#define PSOC_ARC1_AUX_MAX_OFFSET 0x1000
+#define PSOC_ARC1_AUX_SECTION 0xE800
+#define PSOC_ARC1_AUX_SPECIAL_BASE 0x4C5EE80ull
+#define PSOC_ARC1_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_ARC1_AUX_SPECIAL_SECTION 0x1180
+#define PSOC_SECURITY_BASE 0x4C60000ull
+#define PSOC_SECURITY_MAX_OFFSET 0x1000
+#define PSOC_SECURITY_SECTION 0xE800
+#define PSOC_SECURITY_SPECIAL_BASE 0x4C60E80ull
+#define PSOC_SECURITY_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_SECURITY_SPECIAL_SECTION 0x1800
+#define JT_MSTR_IF_RR_SHRD_HBW_BASE 0x4C61000ull
+#define JT_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define JT_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define JT_MSTR_IF_RR_PRVT_HBW_BASE 0x4C61200ull
+#define JT_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define JT_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define JT_MSTR_IF_RR_SHRD_LBW_BASE 0x4C61400ull
+#define JT_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define JT_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define JT_MSTR_IF_RR_PRVT_LBW_BASE 0x4C61600ull
+#define JT_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define JT_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define JT_MSTR_IF_E2E_CRDT_BASE 0x4C61800ull
+#define JT_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define JT_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define JT_MSTR_IF_AXUSER_BASE 0x4C61A80ull
+#define JT_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define JT_MSTR_IF_AXUSER_SECTION 0x8000
+#define JT_MSTR_IF_DBG_HBW_BASE 0x4C61B00ull
+#define JT_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define JT_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define JT_MSTR_IF_DBG_LBW_BASE 0x4C61B80ull
+#define JT_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define JT_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define JT_MSTR_IF_CORE_HBW_BASE 0x4C61C00ull
+#define JT_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define JT_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define JT_MSTR_IF_CORE_LBW_BASE 0x4C61D80ull
+#define JT_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define JT_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define JT_MSTR_IF_SPECIAL_BASE 0x4C61E80ull
+#define JT_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define JT_MSTR_IF_SPECIAL_SECTION 0x1800
+#define SMI_MSTR_IF_RR_SHRD_HBW_BASE 0x4C62000ull
+#define SMI_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SMI_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define SMI_MSTR_IF_RR_PRVT_HBW_BASE 0x4C62200ull
+#define SMI_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SMI_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define SMI_MSTR_IF_RR_SHRD_LBW_BASE 0x4C62400ull
+#define SMI_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SMI_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define SMI_MSTR_IF_RR_PRVT_LBW_BASE 0x4C62600ull
+#define SMI_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SMI_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define SMI_MSTR_IF_E2E_CRDT_BASE 0x4C62800ull
+#define SMI_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SMI_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define SMI_MSTR_IF_AXUSER_BASE 0x4C62A80ull
+#define SMI_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SMI_MSTR_IF_AXUSER_SECTION 0x8000
+#define SMI_MSTR_IF_DBG_HBW_BASE 0x4C62B00ull
+#define SMI_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SMI_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define SMI_MSTR_IF_DBG_LBW_BASE 0x4C62B80ull
+#define SMI_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SMI_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define SMI_MSTR_IF_CORE_HBW_BASE 0x4C62C00ull
+#define SMI_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SMI_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define SMI_MSTR_IF_CORE_LBW_BASE 0x4C62D80ull
+#define SMI_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SMI_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define SMI_MSTR_IF_SPECIAL_BASE 0x4C62E80ull
+#define SMI_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SMI_MSTR_IF_SPECIAL_SECTION 0x1800
+#define I2C_S_MSTR_IF_RR_SHRD_HBW_BASE 0x4C63000ull
+#define I2C_S_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define I2C_S_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define I2C_S_MSTR_IF_RR_PRVT_HBW_BASE 0x4C63200ull
+#define I2C_S_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define I2C_S_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define I2C_S_MSTR_IF_RR_SHRD_LBW_BASE 0x4C63400ull
+#define I2C_S_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define I2C_S_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define I2C_S_MSTR_IF_RR_PRVT_LBW_BASE 0x4C63600ull
+#define I2C_S_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define I2C_S_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define I2C_S_MSTR_IF_E2E_CRDT_BASE 0x4C63800ull
+#define I2C_S_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define I2C_S_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define I2C_S_MSTR_IF_AXUSER_BASE 0x4C63A80ull
+#define I2C_S_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define I2C_S_MSTR_IF_AXUSER_SECTION 0x8000
+#define I2C_S_MSTR_IF_DBG_HBW_BASE 0x4C63B00ull
+#define I2C_S_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define I2C_S_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define I2C_S_MSTR_IF_DBG_LBW_BASE 0x4C63B80ull
+#define I2C_S_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define I2C_S_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define I2C_S_MSTR_IF_CORE_HBW_BASE 0x4C63C00ull
+#define I2C_S_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define I2C_S_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define I2C_S_MSTR_IF_CORE_LBW_BASE 0x4C63D80ull
+#define I2C_S_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define I2C_S_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define I2C_S_MSTR_IF_SPECIAL_BASE 0x4C63E80ull
+#define I2C_S_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define I2C_S_MSTR_IF_SPECIAL_SECTION 0x1800
+#define PSOC_SVID0_BASE 0x4C64000ull
+#define PSOC_SVID0_MAX_OFFSET 0x1000
+#define PSOC_SVID0_SECTION 0xE800
+#define PSOC_SVID0_SPECIAL_BASE 0x4C64E80ull
+#define PSOC_SVID0_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_SVID0_SPECIAL_SECTION 0x1800
+#define PSOC_SVID1_BASE 0x4C65000ull
+#define PSOC_SVID1_MAX_OFFSET 0x1000
+#define PSOC_SVID1_SECTION 0xE800
+#define PSOC_SVID1_SPECIAL_BASE 0x4C65E80ull
+#define PSOC_SVID1_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_SVID1_SPECIAL_SECTION 0x1800
+#define PSOC_SVID2_BASE 0x4C66000ull
+#define PSOC_SVID2_MAX_OFFSET 0x1000
+#define PSOC_SVID2_SECTION 0xE800
+#define PSOC_SVID2_SPECIAL_BASE 0x4C66E80ull
+#define PSOC_SVID2_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_SVID2_SPECIAL_SECTION 0x5180
+#define PSOC_MME_PLL_CTRL_BASE 0x4C6C000ull
+#define PSOC_MME_PLL_CTRL_MAX_OFFSET 0x3540
+#define PSOC_MME_PLL_CTRL_SECTION 0x3600
+#define PSOC_MME_PLL_ASIF_SLV_BASE 0x4C6C360ull
+#define PSOC_MME_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define PSOC_MME_PLL_ASIF_SLV_SECTION 0xA000
+#define PSOC_MME_PLL_DIV_0_RLX_BASE 0x4C6C400ull
+#define PSOC_MME_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define PSOC_MME_PLL_DIV_0_RLX_SECTION 0x4000
+#define PSOC_MME_PLL_DIV_1_RLX_BASE 0x4C6C800ull
+#define PSOC_MME_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define PSOC_MME_PLL_DIV_1_RLX_SECTION 0x2000
+#define PSOC_MME_PLL_DIV_2_RLX_BASE 0x4C6CA00ull
+#define PSOC_MME_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define PSOC_MME_PLL_DIV_2_RLX_SECTION 0x2000
+#define PSOC_MME_PLL_DIV_3_RLX_BASE 0x4C6CC00ull
+#define PSOC_MME_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define PSOC_MME_PLL_DIV_3_RLX_SECTION 0x2800
+#define PSOC_MME_PLL_SPECIAL_BASE 0x4C6CE80ull
+#define PSOC_MME_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_MME_PLL_SPECIAL_SECTION 0x1800
+#define PSOC_CPU_PLL_CTRL_BASE 0x4C6D000ull
+#define PSOC_CPU_PLL_CTRL_MAX_OFFSET 0x3540
+#define PSOC_CPU_PLL_CTRL_SECTION 0x3600
+#define PSOC_CPU_PLL_ASIF_SLV_BASE 0x4C6D360ull
+#define PSOC_CPU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define PSOC_CPU_PLL_ASIF_SLV_SECTION 0xA000
+#define PSOC_CPU_PLL_DIV_0_RLX_BASE 0x4C6D400ull
+#define PSOC_CPU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define PSOC_CPU_PLL_DIV_0_RLX_SECTION 0x4000
+#define PSOC_CPU_PLL_DIV_1_RLX_BASE 0x4C6D800ull
+#define PSOC_CPU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define PSOC_CPU_PLL_DIV_1_RLX_SECTION 0x2000
+#define PSOC_CPU_PLL_DIV_2_RLX_BASE 0x4C6DA00ull
+#define PSOC_CPU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define PSOC_CPU_PLL_DIV_2_RLX_SECTION 0x2000
+#define PSOC_CPU_PLL_DIV_3_RLX_BASE 0x4C6DC00ull
+#define PSOC_CPU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define PSOC_CPU_PLL_DIV_3_RLX_SECTION 0x2800
+#define PSOC_CPU_PLL_SPECIAL_BASE 0x4C6DE80ull
+#define PSOC_CPU_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_CPU_PLL_SPECIAL_SECTION 0x1800
+#define PSOC_VID_PLL_CTRL_BASE 0x4C6E000ull
+#define PSOC_VID_PLL_CTRL_MAX_OFFSET 0x3540
+#define PSOC_VID_PLL_CTRL_SECTION 0x3600
+#define PSOC_VID_PLL_ASIF_SLV_BASE 0x4C6E360ull
+#define PSOC_VID_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define PSOC_VID_PLL_ASIF_SLV_SECTION 0xA000
+#define PSOC_VID_PLL_DIV_0_RLX_BASE 0x4C6E400ull
+#define PSOC_VID_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define PSOC_VID_PLL_DIV_0_RLX_SECTION 0x4000
+#define PSOC_VID_PLL_DIV_1_RLX_BASE 0x4C6E800ull
+#define PSOC_VID_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define PSOC_VID_PLL_DIV_1_RLX_SECTION 0x2000
+#define PSOC_VID_PLL_DIV_2_RLX_BASE 0x4C6EA00ull
+#define PSOC_VID_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define PSOC_VID_PLL_DIV_2_RLX_SECTION 0x2000
+#define PSOC_VID_PLL_DIV_3_RLX_BASE 0x4C6EC00ull
+#define PSOC_VID_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define PSOC_VID_PLL_DIV_3_RLX_SECTION 0x2800
+#define PSOC_VID_PLL_SPECIAL_BASE 0x4C6EE80ull
+#define PSOC_VID_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_VID_PLL_SPECIAL_SECTION 0x5180
+#define PSOC_RESET_CONF_BASE 0x4C74000ull
+#define PSOC_RESET_CONF_MAX_OFFSET 0x1000
+#define PSOC_RESET_CONF_SECTION 0xE800
+#define PSOC_RESET_CONF_SPECIAL_BASE 0x4C74E80ull
+#define PSOC_RESET_CONF_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_RESET_CONF_SPECIAL_SECTION 0x1800
+#define PSOC_DFT_APB_BASE 0x4C75000ull
+#define PSOC_DFT_APB_MAX_OFFSET 0x8000
+#define PSOC_DFT_APB_SECTION 0x1000
+#define PSOC_AVS0_BASE 0x4C76000ull
+#define PSOC_AVS0_MAX_OFFSET 0x1000
+#define PSOC_AVS0_SECTION 0xE800
+#define PSOC_AVS0_SPECIAL_BASE 0x4C76E80ull
+#define PSOC_AVS0_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_AVS0_SPECIAL_SECTION 0x1800
+#define PSOC_AVS1_BASE 0x4C77000ull
+#define PSOC_AVS1_MAX_OFFSET 0x1000
+#define PSOC_AVS1_SECTION 0xE800
+#define PSOC_AVS1_SPECIAL_BASE 0x4C77E80ull
+#define PSOC_AVS1_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_AVS1_SPECIAL_SECTION 0x1800
+#define PSOC_AVS2_BASE 0x4C78000ull
+#define PSOC_AVS2_MAX_OFFSET 0x1000
+#define PSOC_AVS2_SECTION 0xE800
+#define PSOC_AVS2_SPECIAL_BASE 0x4C78E80ull
+#define PSOC_AVS2_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_AVS2_SPECIAL_SECTION 0x1800
+#define PSOC_PWM0_BASE 0x4C79000ull
+#define PSOC_PWM0_MAX_OFFSET 0x1000
+#define PSOC_PWM0_SECTION 0xE800
+#define PSOC_PWM0_SPECIAL_BASE 0x4C79E80ull
+#define PSOC_PWM0_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_PWM0_SPECIAL_SECTION 0x1800
+#define PSOC_PWM1_BASE 0x4C7A000ull
+#define PSOC_PWM1_MAX_OFFSET 0x1000
+#define PSOC_PWM1_SECTION 0xE800
+#define PSOC_PWM1_SPECIAL_BASE 0x4C7AE80ull
+#define PSOC_PWM1_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_PWM1_SPECIAL_SECTION 0x1800
+#define SVID0_AC_BASE 0x4C7B000ull
+#define SVID0_AC_MAX_OFFSET 0x1000
+#define SVID0_AC_SECTION 0xE800
+#define SVID0_AC_SPECIAL_BASE 0x4C7BE80ull
+#define SVID0_AC_SPECIAL_MAX_OFFSET 0x1800
+#define SVID0_AC_SPECIAL_SECTION 0x1800
+#define SVID1_AC_BASE 0x4C7C000ull
+#define SVID1_AC_MAX_OFFSET 0x1000
+#define SVID1_AC_SECTION 0xE800
+#define SVID1_AC_SPECIAL_BASE 0x4C7CE80ull
+#define SVID1_AC_SPECIAL_MAX_OFFSET 0x1800
+#define SVID1_AC_SPECIAL_SECTION 0x1800
+#define SVID2_AC_BASE 0x4C7D000ull
+#define SVID2_AC_MAX_OFFSET 0x1000
+#define SVID2_AC_SECTION 0xE800
+#define SVID2_AC_SPECIAL_BASE 0x4C7DE80ull
+#define SVID2_AC_SPECIAL_MAX_OFFSET 0x1800
+#define SVID2_AC_SPECIAL_SECTION 0x1180
+#define PSOC_MSTR_IF_RR_SHRD_HBW_BASE 0x4C7F000ull
+#define PSOC_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PSOC_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define PSOC_MSTR_IF_RR_PRVT_HBW_BASE 0x4C7F200ull
+#define PSOC_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PSOC_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define PSOC_MSTR_IF_RR_SHRD_LBW_BASE 0x4C7F400ull
+#define PSOC_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PSOC_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define PSOC_MSTR_IF_RR_PRVT_LBW_BASE 0x4C7F600ull
+#define PSOC_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PSOC_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define PSOC_MSTR_IF_E2E_CRDT_BASE 0x4C7F800ull
+#define PSOC_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PSOC_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define PSOC_MSTR_IF_AXUSER_BASE 0x4C7FA80ull
+#define PSOC_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PSOC_MSTR_IF_AXUSER_SECTION 0x8000
+#define PSOC_MSTR_IF_DBG_HBW_BASE 0x4C7FB00ull
+#define PSOC_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PSOC_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define PSOC_MSTR_IF_DBG_LBW_BASE 0x4C7FB80ull
+#define PSOC_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PSOC_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define PSOC_MSTR_IF_CORE_HBW_BASE 0x4C7FC00ull
+#define PSOC_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PSOC_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define PSOC_MSTR_IF_CORE_LBW_BASE 0x4C7FD80ull
+#define PSOC_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PSOC_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define PSOC_MSTR_IF_SPECIAL_BASE 0x4C7FE80ull
+#define PSOC_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_MSTR_IF_SPECIAL_SECTION 0x1800
+#define PDMA0_QM_ARC_DCCM_BASE 0x4C80000ull
+#define PDMA0_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define PDMA0_QM_ARC_DCCM_SECTION 0x8000
+#define PDMA0_QM_ARC_AUX_BASE 0x4C88000ull
+#define PDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define PDMA0_QM_ARC_AUX_SECTION 0xE800
+#define PDMA0_QM_ARC_AUX_SPECIAL_BASE 0x4C88E80ull
+#define PDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define PDMA0_QM_BASE 0x4C8A000ull
+#define PDMA0_QM_MAX_OFFSET 0x1000
+#define PDMA0_QM_SECTION 0x9000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C8A900ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C8A908ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C8A910ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C8A918ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C8A920ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C8A928ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C8A930ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C8A938ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C8A940ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C8A948ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C8A950ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C8A958ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C8A960ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C8A968ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C8A970ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C8A978ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define PDMA0_QM_AXUSER_SECURED_BASE 0x4C8AB00ull
+#define PDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define PDMA0_QM_AXUSER_SECURED_SECTION 0x8000
+#define PDMA0_QM_AXUSER_NONSECURED_BASE 0x4C8AB80ull
+#define PDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define PDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define PDMA0_QM_DBG_HBW_BASE 0x4C8AC00ull
+#define PDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define PDMA0_QM_DBG_HBW_SECTION 0x8000
+#define PDMA0_QM_DBG_LBW_BASE 0x4C8AC80ull
+#define PDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define PDMA0_QM_DBG_LBW_SECTION 0x1000
+#define PDMA0_QM_CGM_BASE 0x4C8AD80ull
+#define PDMA0_QM_CGM_MAX_OFFSET 0xC000
+#define PDMA0_QM_CGM_SECTION 0x1000
+#define PDMA0_QM_SPECIAL_BASE 0x4C8AE80ull
+#define PDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA0_QM_SPECIAL_SECTION 0x1800
+#define PDMA0_CORE_BASE 0x4C8B000ull
+#define PDMA0_CORE_MAX_OFFSET 0x1000
+#define PDMA0_CORE_SECTION 0x8000
+#define PDMA0_CORE_CTX_AXUSER_BASE 0x4C8B800ull
+#define PDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define PDMA0_CORE_CTX_AXUSER_SECTION 0x6000
+#define PDMA0_CORE_CTX_BASE 0x4C8B860ull
+#define PDMA0_CORE_CTX_MAX_OFFSET 0x9000
+#define PDMA0_CORE_CTX_SECTION 0x5A00
+#define PDMA0_CORE_KDMA_CGM_BASE 0x4C8BE00ull
+#define PDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define PDMA0_CORE_KDMA_CGM_SECTION 0x8000
+#define PDMA0_CORE_SPECIAL_BASE 0x4C8BE80ull
+#define PDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA0_CORE_SPECIAL_SECTION 0x1800
+#define PDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x4C8C000ull
+#define PDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define PDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x4C8C200ull
+#define PDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define PDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x4C8C400ull
+#define PDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define PDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x4C8C600ull
+#define PDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define PDMA0_MSTR_IF_E2E_CRDT_BASE 0x4C8C800ull
+#define PDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define PDMA0_MSTR_IF_AXUSER_BASE 0x4C8CA80ull
+#define PDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PDMA0_MSTR_IF_AXUSER_SECTION 0x8000
+#define PDMA0_MSTR_IF_DBG_HBW_BASE 0x4C8CB00ull
+#define PDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define PDMA0_MSTR_IF_DBG_LBW_BASE 0x4C8CB80ull
+#define PDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define PDMA0_MSTR_IF_CORE_HBW_BASE 0x4C8CC00ull
+#define PDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define PDMA0_MSTR_IF_CORE_LBW_BASE 0x4C8CD80ull
+#define PDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define PDMA0_MSTR_IF_SPECIAL_BASE 0x4C8CE80ull
+#define PDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define PDMA1_QM_ARC_DCCM_BASE 0x4C90000ull
+#define PDMA1_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define PDMA1_QM_ARC_DCCM_SECTION 0x8000
+#define PDMA1_QM_ARC_AUX_BASE 0x4C98000ull
+#define PDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define PDMA1_QM_ARC_AUX_SECTION 0xE800
+#define PDMA1_QM_ARC_AUX_SPECIAL_BASE 0x4C98E80ull
+#define PDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define PDMA1_QM_BASE 0x4C9A000ull
+#define PDMA1_QM_MAX_OFFSET 0x1000
+#define PDMA1_QM_SECTION 0x9000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C9A900ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C9A908ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C9A910ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C9A918ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C9A920ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C9A928ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C9A930ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C9A938ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C9A940ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C9A948ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C9A950ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C9A958ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C9A960ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C9A968ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C9A970ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C9A978ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define PDMA1_QM_AXUSER_SECURED_BASE 0x4C9AB00ull
+#define PDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define PDMA1_QM_AXUSER_SECURED_SECTION 0x8000
+#define PDMA1_QM_AXUSER_NONSECURED_BASE 0x4C9AB80ull
+#define PDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define PDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define PDMA1_QM_DBG_HBW_BASE 0x4C9AC00ull
+#define PDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define PDMA1_QM_DBG_HBW_SECTION 0x8000
+#define PDMA1_QM_DBG_LBW_BASE 0x4C9AC80ull
+#define PDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define PDMA1_QM_DBG_LBW_SECTION 0x1000
+#define PDMA1_QM_CGM_BASE 0x4C9AD80ull
+#define PDMA1_QM_CGM_MAX_OFFSET 0xC000
+#define PDMA1_QM_CGM_SECTION 0x1000
+#define PDMA1_QM_SPECIAL_BASE 0x4C9AE80ull
+#define PDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA1_QM_SPECIAL_SECTION 0x1800
+#define PDMA1_CORE_BASE 0x4C9B000ull
+#define PDMA1_CORE_MAX_OFFSET 0x1000
+#define PDMA1_CORE_SECTION 0x8000
+#define PDMA1_CORE_CTX_AXUSER_BASE 0x4C9B800ull
+#define PDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define PDMA1_CORE_CTX_AXUSER_SECTION 0x6000
+#define PDMA1_CORE_CTX_BASE 0x4C9B860ull
+#define PDMA1_CORE_CTX_MAX_OFFSET 0x9000
+#define PDMA1_CORE_CTX_SECTION 0x5A00
+#define PDMA1_CORE_KDMA_CGM_BASE 0x4C9BE00ull
+#define PDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define PDMA1_CORE_KDMA_CGM_SECTION 0x8000
+#define PDMA1_CORE_SPECIAL_BASE 0x4C9BE80ull
+#define PDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA1_CORE_SPECIAL_SECTION 0x1800
+#define PDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x4C9C000ull
+#define PDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define PDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x4C9C200ull
+#define PDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define PDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x4C9C400ull
+#define PDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define PDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x4C9C600ull
+#define PDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define PDMA1_MSTR_IF_E2E_CRDT_BASE 0x4C9C800ull
+#define PDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define PDMA1_MSTR_IF_AXUSER_BASE 0x4C9CA80ull
+#define PDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PDMA1_MSTR_IF_AXUSER_SECTION 0x8000
+#define PDMA1_MSTR_IF_DBG_HBW_BASE 0x4C9CB00ull
+#define PDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define PDMA1_MSTR_IF_DBG_LBW_BASE 0x4C9CB80ull
+#define PDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define PDMA1_MSTR_IF_CORE_HBW_BASE 0x4C9CC00ull
+#define PDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define PDMA1_MSTR_IF_CORE_LBW_BASE 0x4C9CD80ull
+#define PDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define PDMA1_MSTR_IF_SPECIAL_BASE 0x4C9CE80ull
+#define PDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA1_MSTR_IF_SPECIAL_SECTION 0x23180
+#define CPU_CA53_CFG_BASE 0x4CC0000ull
+#define CPU_CA53_CFG_MAX_OFFSET 0x1000
+#define CPU_CA53_CFG_SECTION 0xE800
+#define CPU_CA53_CFG_SPECIAL_BASE 0x4CC0E80ull
+#define CPU_CA53_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define CPU_CA53_CFG_SPECIAL_SECTION 0x1800
+#define CPU_IF_BASE 0x4CC1000ull
+#define CPU_IF_MAX_OFFSET 0x1000
+#define CPU_IF_SECTION 0xE800
+#define CPU_IF_SPECIAL_BASE 0x4CC1E80ull
+#define CPU_IF_SPECIAL_MAX_OFFSET 0x1800
+#define CPU_IF_SPECIAL_SECTION 0x1800
+#define CPU_TIMESTAMP_BASE 0x4CC2000ull
+#define CPU_TIMESTAMP_MAX_OFFSET 0x1000
+#define CPU_TIMESTAMP_SECTION 0x1000
+#define CPU_MSTR_IF_RR_SHRD_HBW_BASE 0x4CC3000ull
+#define CPU_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define CPU_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define CPU_MSTR_IF_RR_PRVT_HBW_BASE 0x4CC3200ull
+#define CPU_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define CPU_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define CPU_MSTR_IF_RR_SHRD_LBW_BASE 0x4CC3400ull
+#define CPU_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define CPU_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define CPU_MSTR_IF_RR_PRVT_LBW_BASE 0x4CC3600ull
+#define CPU_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define CPU_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define CPU_MSTR_IF_E2E_CRDT_BASE 0x4CC3800ull
+#define CPU_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define CPU_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define CPU_MSTR_IF_AXUSER_BASE 0x4CC3A80ull
+#define CPU_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define CPU_MSTR_IF_AXUSER_SECTION 0x8000
+#define CPU_MSTR_IF_DBG_HBW_BASE 0x4CC3B00ull
+#define CPU_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define CPU_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define CPU_MSTR_IF_DBG_LBW_BASE 0x4CC3B80ull
+#define CPU_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define CPU_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define CPU_MSTR_IF_CORE_HBW_BASE 0x4CC3C00ull
+#define CPU_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define CPU_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define CPU_MSTR_IF_CORE_LBW_BASE 0x4CC3D80ull
+#define CPU_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define CPU_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define CPU_MSTR_IF_SPECIAL_BASE 0x4CC3E80ull
+#define CPU_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define CPU_MSTR_IF_SPECIAL_SECTION 0x3C180
+#define PMMU_HBW_MMU_BASE 0x4D00000ull
+#define PMMU_HBW_MMU_MAX_OFFSET 0x1000
+#define PMMU_HBW_MMU_SECTION 0xE800
+#define PMMU_HBW_MMU_SPECIAL_BASE 0x4D00E80ull
+#define PMMU_HBW_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define PMMU_HBW_MMU_SPECIAL_SECTION 0x1800
+#define PMMU_HBW_STLB_BASE 0x4D01000ull
+#define PMMU_HBW_STLB_MAX_OFFSET 0x1000
+#define PMMU_HBW_STLB_SECTION 0xE800
+#define PMMU_HBW_STLB_SPECIAL_BASE 0x4D01E80ull
+#define PMMU_HBW_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define PMMU_HBW_STLB_SPECIAL_SECTION 0x1800
+#define PMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE 0x4D02000ull
+#define PMMU_HBW_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PMMU_HBW_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define PMMU_HBW_MSTR_IF_RR_PRVT_HBW_BASE 0x4D02200ull
+#define PMMU_HBW_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PMMU_HBW_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define PMMU_HBW_MSTR_IF_RR_SHRD_LBW_BASE 0x4D02400ull
+#define PMMU_HBW_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PMMU_HBW_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define PMMU_HBW_MSTR_IF_RR_PRVT_LBW_BASE 0x4D02600ull
+#define PMMU_HBW_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PMMU_HBW_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define PMMU_HBW_MSTR_IF_E2E_CRDT_BASE 0x4D02800ull
+#define PMMU_HBW_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PMMU_HBW_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define PMMU_HBW_MSTR_IF_AXUSER_BASE 0x4D02A80ull
+#define PMMU_HBW_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PMMU_HBW_MSTR_IF_AXUSER_SECTION 0x8000
+#define PMMU_HBW_MSTR_IF_DBG_HBW_BASE 0x4D02B00ull
+#define PMMU_HBW_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PMMU_HBW_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define PMMU_HBW_MSTR_IF_DBG_LBW_BASE 0x4D02B80ull
+#define PMMU_HBW_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PMMU_HBW_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define PMMU_HBW_MSTR_IF_CORE_HBW_BASE 0x4D02C00ull
+#define PMMU_HBW_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PMMU_HBW_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define PMMU_HBW_MSTR_IF_CORE_LBW_BASE 0x4D02D80ull
+#define PMMU_HBW_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PMMU_HBW_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define PMMU_HBW_MSTR_IF_SPECIAL_BASE 0x4D02E80ull
+#define PMMU_HBW_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PMMU_HBW_MSTR_IF_SPECIAL_SECTION 0x1800
+#define PMMU_PIF_BASE 0x4D03000ull
+#define PMMU_PIF_MAX_OFFSET 0x1000
+#define PMMU_PIF_SECTION 0xE800
+#define PMMU_PIF_SPECIAL_BASE 0x4D03E80ull
+#define PMMU_PIF_SPECIAL_MAX_OFFSET 0x1800
+#define PMMU_PIF_SPECIAL_SECTION 0x1800
+#define PMMU_MME_PLL_CTRL_BASE 0x4D04000ull
+#define PMMU_MME_PLL_CTRL_MAX_OFFSET 0x3540
+#define PMMU_MME_PLL_CTRL_SECTION 0x3600
+#define PMMU_MME_PLL_ASIF_SLV_BASE 0x4D04360ull
+#define PMMU_MME_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define PMMU_MME_PLL_ASIF_SLV_SECTION 0xA000
+#define PMMU_MME_PLL_DIV_0_RLX_BASE 0x4D04400ull
+#define PMMU_MME_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define PMMU_MME_PLL_DIV_0_RLX_SECTION 0x4000
+#define PMMU_MME_PLL_DIV_1_RLX_BASE 0x4D04800ull
+#define PMMU_MME_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define PMMU_MME_PLL_DIV_1_RLX_SECTION 0x2000
+#define PMMU_MME_PLL_DIV_2_RLX_BASE 0x4D04A00ull
+#define PMMU_MME_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define PMMU_MME_PLL_DIV_2_RLX_SECTION 0x2000
+#define PMMU_MME_PLL_DIV_3_RLX_BASE 0x4D04C00ull
+#define PMMU_MME_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define PMMU_MME_PLL_DIV_3_RLX_SECTION 0x2800
+#define PMMU_MME_PLL_SPECIAL_BASE 0x4D04E80ull
+#define PMMU_MME_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define PMMU_MME_PLL_SPECIAL_SECTION 0x1800
+#define PMMU_VID_PLL_CTRL_BASE 0x4D05000ull
+#define PMMU_VID_PLL_CTRL_MAX_OFFSET 0x3540
+#define PMMU_VID_PLL_CTRL_SECTION 0x3600
+#define PMMU_VID_PLL_ASIF_SLV_BASE 0x4D05360ull
+#define PMMU_VID_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define PMMU_VID_PLL_ASIF_SLV_SECTION 0xA000
+#define PMMU_VID_PLL_DIV_0_RLX_BASE 0x4D05400ull
+#define PMMU_VID_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define PMMU_VID_PLL_DIV_0_RLX_SECTION 0x4000
+#define PMMU_VID_PLL_DIV_1_RLX_BASE 0x4D05800ull
+#define PMMU_VID_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define PMMU_VID_PLL_DIV_1_RLX_SECTION 0x2000
+#define PMMU_VID_PLL_DIV_2_RLX_BASE 0x4D05A00ull
+#define PMMU_VID_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define PMMU_VID_PLL_DIV_2_RLX_SECTION 0x2000
+#define PMMU_VID_PLL_DIV_3_RLX_BASE 0x4D05C00ull
+#define PMMU_VID_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define PMMU_VID_PLL_DIV_3_RLX_SECTION 0x2800
+#define PMMU_VID_PLL_SPECIAL_BASE 0x4D05E80ull
+#define PMMU_VID_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define PMMU_VID_PLL_SPECIAL_SECTION 0x3A180
+#define XBAR_MID_0_BASE 0x4D40000ull
+#define XBAR_MID_0_MAX_OFFSET 0x1000
+#define XBAR_MID_0_SECTION 0xE800
+#define XBAR_MID_0_SPECIAL_BASE 0x4D40E80ull
+#define XBAR_MID_0_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_MID_0_SPECIAL_SECTION 0x1800
+#define DCORE0_XBAR_DMA_PLL_CTRL_BASE 0x4D41000ull
+#define DCORE0_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE0_XBAR_DMA_PLL_CTRL_SECTION 0x3600
+#define DCORE0_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D41360ull
+#define DCORE0_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE0_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D41400ull
+#define DCORE0_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE0_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D41800ull
+#define DCORE0_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE0_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D41A00ull
+#define DCORE0_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE0_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D41C00ull
+#define DCORE0_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE0_XBAR_DMA_PLL_SPECIAL_BASE 0x4D41E80ull
+#define DCORE0_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800
+#define DCORE0_XBAR_MMU_PLL_CTRL_BASE 0x4D42000ull
+#define DCORE0_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE0_XBAR_MMU_PLL_CTRL_SECTION 0x3600
+#define DCORE0_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D42360ull
+#define DCORE0_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE0_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D42400ull
+#define DCORE0_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE0_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D42800ull
+#define DCORE0_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE0_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D42A00ull
+#define DCORE0_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE0_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D42C00ull
+#define DCORE0_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE0_XBAR_MMU_PLL_SPECIAL_BASE 0x4D42E80ull
+#define DCORE0_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800
+#define DCORE0_XBAR_IF_PLL_CTRL_BASE 0x4D43000ull
+#define DCORE0_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE0_XBAR_IF_PLL_CTRL_SECTION 0x3600
+#define DCORE0_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D43360ull
+#define DCORE0_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE0_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D43400ull
+#define DCORE0_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE0_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D43800ull
+#define DCORE0_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE0_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D43A00ull
+#define DCORE0_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE0_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D43C00ull
+#define DCORE0_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE0_XBAR_IF_PLL_SPECIAL_BASE 0x4D43E80ull
+#define DCORE0_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_IF_PLL_SPECIAL_SECTION 0x1800
+#define DCORE0_XBAR_MESH_PLL_CTRL_BASE 0x4D44000ull
+#define DCORE0_XBAR_MESH_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE0_XBAR_MESH_PLL_CTRL_SECTION 0x3600
+#define DCORE0_XBAR_MESH_PLL_ASIF_SLV_BASE 0x4D44360ull
+#define DCORE0_XBAR_MESH_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_XBAR_MESH_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE0_XBAR_MESH_PLL_DIV_0_RLX_BASE 0x4D44400ull
+#define DCORE0_XBAR_MESH_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_MESH_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE0_XBAR_MESH_PLL_DIV_1_RLX_BASE 0x4D44800ull
+#define DCORE0_XBAR_MESH_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_MESH_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE0_XBAR_MESH_PLL_DIV_2_RLX_BASE 0x4D44A00ull
+#define DCORE0_XBAR_MESH_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_MESH_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE0_XBAR_MESH_PLL_DIV_3_RLX_BASE 0x4D44C00ull
+#define DCORE0_XBAR_MESH_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_MESH_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE0_XBAR_MESH_PLL_SPECIAL_BASE 0x4D44E80ull
+#define DCORE0_XBAR_MESH_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_MESH_PLL_SPECIAL_SECTION 0x3180
+#define XBAR_EDGE_0_BASE 0x4D48000ull
+#define XBAR_EDGE_0_MAX_OFFSET 0x1000
+#define XBAR_EDGE_0_SECTION 0xE800
+#define XBAR_EDGE_0_SPECIAL_BASE 0x4D48E80ull
+#define XBAR_EDGE_0_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_EDGE_0_SPECIAL_SECTION 0x7180
+#define XBAR_MID_1_BASE 0x4D50000ull
+#define XBAR_MID_1_MAX_OFFSET 0x1000
+#define XBAR_MID_1_SECTION 0xE800
+#define XBAR_MID_1_SPECIAL_BASE 0x4D50E80ull
+#define XBAR_MID_1_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_MID_1_SPECIAL_SECTION 0x1800
+#define DCORE1_XBAR_DMA_PLL_CTRL_BASE 0x4D51000ull
+#define DCORE1_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_XBAR_DMA_PLL_CTRL_SECTION 0x3600
+#define DCORE1_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D51360ull
+#define DCORE1_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE1_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D51400ull
+#define DCORE1_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE1_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D51800ull
+#define DCORE1_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE1_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D51A00ull
+#define DCORE1_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE1_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D51C00ull
+#define DCORE1_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE1_XBAR_DMA_PLL_SPECIAL_BASE 0x4D51E80ull
+#define DCORE1_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800
+#define DCORE1_XBAR_MMU_PLL_CTRL_BASE 0x4D52000ull
+#define DCORE1_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_XBAR_MMU_PLL_CTRL_SECTION 0x3600
+#define DCORE1_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D52360ull
+#define DCORE1_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE1_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D52400ull
+#define DCORE1_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE1_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D52800ull
+#define DCORE1_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE1_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D52A00ull
+#define DCORE1_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE1_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D52C00ull
+#define DCORE1_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE1_XBAR_MMU_PLL_SPECIAL_BASE 0x4D52E80ull
+#define DCORE1_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800
+#define DCORE1_XBAR_IF_PLL_CTRL_BASE 0x4D53000ull
+#define DCORE1_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_XBAR_IF_PLL_CTRL_SECTION 0x3600
+#define DCORE1_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D53360ull
+#define DCORE1_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE1_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D53400ull
+#define DCORE1_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE1_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D53800ull
+#define DCORE1_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE1_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D53A00ull
+#define DCORE1_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE1_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D53C00ull
+#define DCORE1_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE1_XBAR_IF_PLL_SPECIAL_BASE 0x4D53E80ull
+#define DCORE1_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_IF_PLL_SPECIAL_SECTION 0x1800
+#define DCORE1_XBAR_MESH_PLL_CTRL_BASE 0x4D54000ull
+#define DCORE1_XBAR_MESH_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_XBAR_MESH_PLL_CTRL_SECTION 0x3600
+#define DCORE1_XBAR_MESH_PLL_ASIF_SLV_BASE 0x4D54360ull
+#define DCORE1_XBAR_MESH_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_XBAR_MESH_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE1_XBAR_MESH_PLL_DIV_0_RLX_BASE 0x4D54400ull
+#define DCORE1_XBAR_MESH_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_MESH_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE1_XBAR_MESH_PLL_DIV_1_RLX_BASE 0x4D54800ull
+#define DCORE1_XBAR_MESH_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_MESH_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE1_XBAR_MESH_PLL_DIV_2_RLX_BASE 0x4D54A00ull
+#define DCORE1_XBAR_MESH_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_MESH_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE1_XBAR_MESH_PLL_DIV_3_RLX_BASE 0x4D54C00ull
+#define DCORE1_XBAR_MESH_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_MESH_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE1_XBAR_MESH_PLL_SPECIAL_BASE 0x4D54E80ull
+#define DCORE1_XBAR_MESH_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_MESH_PLL_SPECIAL_SECTION 0x1800
+#define DCORE1_XBAR_HBM_PLL_CTRL_BASE 0x4D55000ull
+#define DCORE1_XBAR_HBM_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_XBAR_HBM_PLL_CTRL_SECTION 0x3600
+#define DCORE1_XBAR_HBM_PLL_ASIF_SLV_BASE 0x4D55360ull
+#define DCORE1_XBAR_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_XBAR_HBM_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE1_XBAR_HBM_PLL_DIV_0_RLX_BASE 0x4D55400ull
+#define DCORE1_XBAR_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_HBM_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE1_XBAR_HBM_PLL_DIV_1_RLX_BASE 0x4D55800ull
+#define DCORE1_XBAR_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_HBM_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE1_XBAR_HBM_PLL_DIV_2_RLX_BASE 0x4D55A00ull
+#define DCORE1_XBAR_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_HBM_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE1_XBAR_HBM_PLL_DIV_3_RLX_BASE 0x4D55C00ull
+#define DCORE1_XBAR_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_HBM_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE1_XBAR_HBM_PLL_SPECIAL_BASE 0x4D55E80ull
+#define DCORE1_XBAR_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_HBM_PLL_SPECIAL_SECTION 0x2180
+#define XBAR_EDGE_1_BASE 0x4D58000ull
+#define XBAR_EDGE_1_MAX_OFFSET 0x1000
+#define XBAR_EDGE_1_SECTION 0xE800
+#define XBAR_EDGE_1_SPECIAL_BASE 0x4D58E80ull
+#define XBAR_EDGE_1_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_EDGE_1_SPECIAL_SECTION 0x7180
+#define XBAR_MID_2_BASE 0x4D60000ull
+#define XBAR_MID_2_MAX_OFFSET 0x1000
+#define XBAR_MID_2_SECTION 0xE800
+#define XBAR_MID_2_SPECIAL_BASE 0x4D60E80ull
+#define XBAR_MID_2_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_MID_2_SPECIAL_SECTION 0x1800
+#define DCORE2_XBAR_DMA_PLL_CTRL_BASE 0x4D61000ull
+#define DCORE2_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE2_XBAR_DMA_PLL_CTRL_SECTION 0x3600
+#define DCORE2_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D61360ull
+#define DCORE2_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE2_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D61400ull
+#define DCORE2_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE2_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D61800ull
+#define DCORE2_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE2_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D61A00ull
+#define DCORE2_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE2_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D61C00ull
+#define DCORE2_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE2_XBAR_DMA_PLL_SPECIAL_BASE 0x4D61E80ull
+#define DCORE2_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800
+#define DCORE2_XBAR_MMU_PLL_CTRL_BASE 0x4D62000ull
+#define DCORE2_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE2_XBAR_MMU_PLL_CTRL_SECTION 0x3600
+#define DCORE2_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D62360ull
+#define DCORE2_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE2_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D62400ull
+#define DCORE2_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE2_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D62800ull
+#define DCORE2_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE2_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D62A00ull
+#define DCORE2_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE2_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D62C00ull
+#define DCORE2_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE2_XBAR_MMU_PLL_SPECIAL_BASE 0x4D62E80ull
+#define DCORE2_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800
+#define DCORE2_XBAR_IF_PLL_CTRL_BASE 0x4D63000ull
+#define DCORE2_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE2_XBAR_IF_PLL_CTRL_SECTION 0x3600
+#define DCORE2_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D63360ull
+#define DCORE2_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE2_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D63400ull
+#define DCORE2_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE2_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D63800ull
+#define DCORE2_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE2_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D63A00ull
+#define DCORE2_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE2_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D63C00ull
+#define DCORE2_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE2_XBAR_IF_PLL_SPECIAL_BASE 0x4D63E80ull
+#define DCORE2_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_IF_PLL_SPECIAL_SECTION 0x1800
+#define DCORE2_XBAR_BANK_PLL_CTRL_BASE 0x4D64000ull
+#define DCORE2_XBAR_BANK_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE2_XBAR_BANK_PLL_CTRL_SECTION 0x3600
+#define DCORE2_XBAR_BANK_PLL_ASIF_SLV_BASE 0x4D64360ull
+#define DCORE2_XBAR_BANK_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_XBAR_BANK_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE2_XBAR_BANK_PLL_DIV_0_RLX_BASE 0x4D64400ull
+#define DCORE2_XBAR_BANK_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_BANK_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE2_XBAR_BANK_PLL_DIV_1_RLX_BASE 0x4D64800ull
+#define DCORE2_XBAR_BANK_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_BANK_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE2_XBAR_BANK_PLL_DIV_2_RLX_BASE 0x4D64A00ull
+#define DCORE2_XBAR_BANK_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_BANK_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE2_XBAR_BANK_PLL_DIV_3_RLX_BASE 0x4D64C00ull
+#define DCORE2_XBAR_BANK_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_BANK_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE2_XBAR_BANK_PLL_SPECIAL_BASE 0x4D64E80ull
+#define DCORE2_XBAR_BANK_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_BANK_PLL_SPECIAL_SECTION 0x1800
+#define DCORE2_XBAR_HBM_PLL_CTRL_BASE 0x4D65000ull
+#define DCORE2_XBAR_HBM_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE2_XBAR_HBM_PLL_CTRL_SECTION 0x3600
+#define DCORE2_XBAR_HBM_PLL_ASIF_SLV_BASE 0x4D65360ull
+#define DCORE2_XBAR_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_XBAR_HBM_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE2_XBAR_HBM_PLL_DIV_0_RLX_BASE 0x4D65400ull
+#define DCORE2_XBAR_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_HBM_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE2_XBAR_HBM_PLL_DIV_1_RLX_BASE 0x4D65800ull
+#define DCORE2_XBAR_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_HBM_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE2_XBAR_HBM_PLL_DIV_2_RLX_BASE 0x4D65A00ull
+#define DCORE2_XBAR_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_HBM_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE2_XBAR_HBM_PLL_DIV_3_RLX_BASE 0x4D65C00ull
+#define DCORE2_XBAR_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_HBM_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE2_XBAR_HBM_PLL_SPECIAL_BASE 0x4D65E80ull
+#define DCORE2_XBAR_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_HBM_PLL_SPECIAL_SECTION 0x2180
+#define XBAR_EDGE_2_BASE 0x4D68000ull
+#define XBAR_EDGE_2_MAX_OFFSET 0x1000
+#define XBAR_EDGE_2_SECTION 0xE800
+#define XBAR_EDGE_2_SPECIAL_BASE 0x4D68E80ull
+#define XBAR_EDGE_2_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_EDGE_2_SPECIAL_SECTION 0x7180
+#define XBAR_MID_3_BASE 0x4D70000ull
+#define XBAR_MID_3_MAX_OFFSET 0x1000
+#define XBAR_MID_3_SECTION 0xE800
+#define XBAR_MID_3_SPECIAL_BASE 0x4D70E80ull
+#define XBAR_MID_3_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_MID_3_SPECIAL_SECTION 0x1800
+#define DCORE3_XBAR_DMA_PLL_CTRL_BASE 0x4D71000ull
+#define DCORE3_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE3_XBAR_DMA_PLL_CTRL_SECTION 0x3600
+#define DCORE3_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D71360ull
+#define DCORE3_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE3_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D71400ull
+#define DCORE3_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE3_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D71800ull
+#define DCORE3_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE3_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D71A00ull
+#define DCORE3_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE3_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D71C00ull
+#define DCORE3_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE3_XBAR_DMA_PLL_SPECIAL_BASE 0x4D71E80ull
+#define DCORE3_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800
+#define DCORE3_XBAR_MMU_PLL_CTRL_BASE 0x4D72000ull
+#define DCORE3_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE3_XBAR_MMU_PLL_CTRL_SECTION 0x3600
+#define DCORE3_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D72360ull
+#define DCORE3_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE3_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D72400ull
+#define DCORE3_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE3_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D72800ull
+#define DCORE3_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE3_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D72A00ull
+#define DCORE3_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE3_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D72C00ull
+#define DCORE3_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE3_XBAR_MMU_PLL_SPECIAL_BASE 0x4D72E80ull
+#define DCORE3_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800
+#define DCORE3_XBAR_IF_PLL_CTRL_BASE 0x4D73000ull
+#define DCORE3_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE3_XBAR_IF_PLL_CTRL_SECTION 0x3600
+#define DCORE3_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D73360ull
+#define DCORE3_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE3_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D73400ull
+#define DCORE3_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE3_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D73800ull
+#define DCORE3_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE3_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D73A00ull
+#define DCORE3_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE3_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D73C00ull
+#define DCORE3_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE3_XBAR_IF_PLL_SPECIAL_BASE 0x4D73E80ull
+#define DCORE3_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_IF_PLL_SPECIAL_SECTION 0x1800
+#define DCORE3_XBAR_BANK_PLL_CTRL_BASE 0x4D74000ull
+#define DCORE3_XBAR_BANK_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE3_XBAR_BANK_PLL_CTRL_SECTION 0x3600
+#define DCORE3_XBAR_BANK_PLL_ASIF_SLV_BASE 0x4D74360ull
+#define DCORE3_XBAR_BANK_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_XBAR_BANK_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE3_XBAR_BANK_PLL_DIV_0_RLX_BASE 0x4D74400ull
+#define DCORE3_XBAR_BANK_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_BANK_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE3_XBAR_BANK_PLL_DIV_1_RLX_BASE 0x4D74800ull
+#define DCORE3_XBAR_BANK_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_BANK_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE3_XBAR_BANK_PLL_DIV_2_RLX_BASE 0x4D74A00ull
+#define DCORE3_XBAR_BANK_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_BANK_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE3_XBAR_BANK_PLL_DIV_3_RLX_BASE 0x4D74C00ull
+#define DCORE3_XBAR_BANK_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_BANK_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE3_XBAR_BANK_PLL_SPECIAL_BASE 0x4D74E80ull
+#define DCORE3_XBAR_BANK_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_BANK_PLL_SPECIAL_SECTION 0x3180
+#define XBAR_EDGE_3_BASE 0x4D78000ull
+#define XBAR_EDGE_3_MAX_OFFSET 0x1000
+#define XBAR_EDGE_3_SECTION 0xE800
+#define XBAR_EDGE_3_SPECIAL_BASE 0x4D78E80ull
+#define XBAR_EDGE_3_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_EDGE_3_SPECIAL_SECTION 0x7180
+#define PCIE_PMA_0_BASE 0x4D80000ull
+#define PCIE_PMA_0_MAX_OFFSET 0x40000
+#define PCIE_PMA_0_SECTION 0x40000
+#define PCIE_PMA_1_BASE 0x4DC0000ull
+#define PCIE_PMA_1_MAX_OFFSET 0x40000
+#define PCIE_PMA_1_SECTION 0x40000
+#define ROT0_QM_ARC_DCCM_BASE 0x4E00000ull
+#define ROT0_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define ROT0_QM_ARC_DCCM_SECTION 0x8000
+#define ROT0_QM_ARC_AUX_BASE 0x4E08000ull
+#define ROT0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define ROT0_QM_ARC_AUX_SECTION 0xE800
+#define ROT0_QM_ARC_AUX_SPECIAL_BASE 0x4E08E80ull
+#define ROT0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define ROT0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define ROT0_QM_BASE 0x4E0A000ull
+#define ROT0_QM_MAX_OFFSET 0x1000
+#define ROT0_QM_SECTION 0x9000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4E0A900ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4E0A908ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4E0A910ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4E0A918ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4E0A920ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4E0A928ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4E0A930ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4E0A938ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4E0A940ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4E0A948ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4E0A950ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4E0A958ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4E0A960ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4E0A968ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4E0A970ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4E0A978ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define ROT0_QM_AXUSER_SECURED_BASE 0x4E0AB00ull
+#define ROT0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define ROT0_QM_AXUSER_SECURED_SECTION 0x8000
+#define ROT0_QM_AXUSER_NONSECURED_BASE 0x4E0AB80ull
+#define ROT0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define ROT0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define ROT0_QM_DBG_HBW_BASE 0x4E0AC00ull
+#define ROT0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define ROT0_QM_DBG_HBW_SECTION 0x8000
+#define ROT0_QM_DBG_LBW_BASE 0x4E0AC80ull
+#define ROT0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define ROT0_QM_DBG_LBW_SECTION 0x1000
+#define ROT0_QM_CGM_BASE 0x4E0AD80ull
+#define ROT0_QM_CGM_MAX_OFFSET 0xC000
+#define ROT0_QM_CGM_SECTION 0x1000
+#define ROT0_QM_SPECIAL_BASE 0x4E0AE80ull
+#define ROT0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define ROT0_QM_SPECIAL_SECTION 0x1800
+#define ROT0_BASE 0x4E0B000ull
+#define ROT0_MAX_OFFSET 0x1000
+#define ROT0_SECTION 0x1000
+#define ROT0_DESC_BASE 0x4E0B100ull
+#define ROT0_DESC_MAX_OFFSET 0x1080
+#define ROT0_DESC_SECTION 0xD800
+#define ROT0_SPECIAL_BASE 0x4E0BE80ull
+#define ROT0_SPECIAL_MAX_OFFSET 0x1800
+#define ROT0_SPECIAL_SECTION 0x1800
+#define ROT0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E0C000ull
+#define ROT0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define ROT0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define ROT0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E0C200ull
+#define ROT0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define ROT0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define ROT0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E0C400ull
+#define ROT0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define ROT0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define ROT0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E0C600ull
+#define ROT0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define ROT0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define ROT0_MSTR_IF_E2E_CRDT_BASE 0x4E0C800ull
+#define ROT0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define ROT0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define ROT0_MSTR_IF_AXUSER_BASE 0x4E0CA80ull
+#define ROT0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define ROT0_MSTR_IF_AXUSER_SECTION 0x8000
+#define ROT0_MSTR_IF_DBG_HBW_BASE 0x4E0CB00ull
+#define ROT0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define ROT0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define ROT0_MSTR_IF_DBG_LBW_BASE 0x4E0CB80ull
+#define ROT0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define ROT0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define ROT0_MSTR_IF_CORE_HBW_BASE 0x4E0CC00ull
+#define ROT0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define ROT0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define ROT0_MSTR_IF_CORE_LBW_BASE 0x4E0CD80ull
+#define ROT0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define ROT0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define ROT0_MSTR_IF_SPECIAL_BASE 0x4E0CE80ull
+#define ROT0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define ROT0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define ROT1_QM_ARC_DCCM_BASE 0x4E10000ull
+#define ROT1_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define ROT1_QM_ARC_DCCM_SECTION 0x8000
+#define ROT1_QM_ARC_AUX_BASE 0x4E18000ull
+#define ROT1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define ROT1_QM_ARC_AUX_SECTION 0xE800
+#define ROT1_QM_ARC_AUX_SPECIAL_BASE 0x4E18E80ull
+#define ROT1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define ROT1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define ROT1_QM_BASE 0x4E1A000ull
+#define ROT1_QM_MAX_OFFSET 0x1000
+#define ROT1_QM_SECTION 0x9000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4E1A900ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4E1A908ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4E1A910ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4E1A918ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4E1A920ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4E1A928ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4E1A930ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4E1A938ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4E1A940ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4E1A948ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4E1A950ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4E1A958ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4E1A960ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4E1A968ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4E1A970ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4E1A978ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define ROT1_QM_AXUSER_SECURED_BASE 0x4E1AB00ull
+#define ROT1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define ROT1_QM_AXUSER_SECURED_SECTION 0x8000
+#define ROT1_QM_AXUSER_NONSECURED_BASE 0x4E1AB80ull
+#define ROT1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define ROT1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define ROT1_QM_DBG_HBW_BASE 0x4E1AC00ull
+#define ROT1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define ROT1_QM_DBG_HBW_SECTION 0x8000
+#define ROT1_QM_DBG_LBW_BASE 0x4E1AC80ull
+#define ROT1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define ROT1_QM_DBG_LBW_SECTION 0x1000
+#define ROT1_QM_CGM_BASE 0x4E1AD80ull
+#define ROT1_QM_CGM_MAX_OFFSET 0xC000
+#define ROT1_QM_CGM_SECTION 0x1000
+#define ROT1_QM_SPECIAL_BASE 0x4E1AE80ull
+#define ROT1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define ROT1_QM_SPECIAL_SECTION 0x1800
+#define ROT1_BASE 0x4E1B000ull
+#define ROT1_MAX_OFFSET 0x1000
+#define ROT1_SECTION 0x1000
+#define ROT1_DESC_BASE 0x4E1B100ull
+#define ROT1_DESC_MAX_OFFSET 0x1080
+#define ROT1_DESC_SECTION 0xD800
+#define ROT1_SPECIAL_BASE 0x4E1BE80ull
+#define ROT1_SPECIAL_MAX_OFFSET 0x1800
+#define ROT1_SPECIAL_SECTION 0x1800
+#define ROT1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E1C000ull
+#define ROT1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define ROT1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define ROT1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E1C200ull
+#define ROT1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define ROT1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define ROT1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E1C400ull
+#define ROT1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define ROT1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define ROT1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E1C600ull
+#define ROT1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define ROT1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define ROT1_MSTR_IF_E2E_CRDT_BASE 0x4E1C800ull
+#define ROT1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define ROT1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define ROT1_MSTR_IF_AXUSER_BASE 0x4E1CA80ull
+#define ROT1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define ROT1_MSTR_IF_AXUSER_SECTION 0x8000
+#define ROT1_MSTR_IF_DBG_HBW_BASE 0x4E1CB00ull
+#define ROT1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define ROT1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define ROT1_MSTR_IF_DBG_LBW_BASE 0x4E1CB80ull
+#define ROT1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define ROT1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define ROT1_MSTR_IF_CORE_HBW_BASE 0x4E1CC00ull
+#define ROT1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define ROT1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define ROT1_MSTR_IF_CORE_LBW_BASE 0x4E1CD80ull
+#define ROT1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define ROT1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define ROT1_MSTR_IF_SPECIAL_BASE 0x4E1CE80ull
+#define ROT1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define ROT1_MSTR_IF_SPECIAL_SECTION 0x23180
+#define SFT0_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E40000ull
+#define SFT0_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT0_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800
+#define SFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E40E80ull
+#define SFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define SFT0_HBW_RTR_IF0_RTR_H3_BASE 0x4E41000ull
+#define SFT0_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000
+#define SFT0_HBW_RTR_IF0_RTR_H3_SECTION 0xE800
+#define SFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E41E80ull
+#define SFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E42000ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E42200ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E42400ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E42600ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define SFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E42800ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define SFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E42A80ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000
+#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E42B00ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E42B80ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E42C00ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E42D80ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define SFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E42E80ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E43000ull
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E43400ull
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E43E80ull
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define SFT0_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E44000ull
+#define SFT0_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT0_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800
+#define SFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E44E80ull
+#define SFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define SFT0_HBW_RTR_IF1_RTR_H3_BASE 0x4E45000ull
+#define SFT0_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000
+#define SFT0_HBW_RTR_IF1_RTR_H3_SECTION 0xE800
+#define SFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E45E80ull
+#define SFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E46000ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E46200ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E46400ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E46600ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define SFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E46800ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define SFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E46A80ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000
+#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E46B00ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E46B80ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E46C00ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E46D80ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define SFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E46E80ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E47000ull
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E47400ull
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E47E80ull
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define SFT0_LBW_RTR_IF_RTR_CTRL_BASE 0x4E48000ull
+#define SFT0_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT0_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800
+#define SFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E48E80ull
+#define SFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define SFT0_LBW_RTR_IF_RTR_H3_BASE 0x4E49000ull
+#define SFT0_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000
+#define SFT0_LBW_RTR_IF_RTR_H3_SECTION 0xE800
+#define SFT0_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E49E80ull
+#define SFT0_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E4A000ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E4A200ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E4A400ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E4A600ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define SFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E4A800ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define SFT0_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E4AA80ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT0_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000
+#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E4AB00ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E4AB80ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E4AC00ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E4AD80ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define SFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E4AE80ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800
+#define SFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E4B000ull
+#define SFT0_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT0_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000
+#define SFT0_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E4B400ull
+#define SFT0_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT0_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800
+#define SFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E4BE80ull
+#define SFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define SFT0_BASE 0x4E4C000ull
+#define SFT0_MAX_OFFSET 0x1000
+#define SFT0_SECTION 0xE800
+#define SFT0_SPECIAL_BASE 0x4E4CE80ull
+#define SFT0_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_SPECIAL_SECTION 0x3180
+#define SFT1_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E50000ull
+#define SFT1_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT1_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800
+#define SFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E50E80ull
+#define SFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define SFT1_HBW_RTR_IF0_RTR_H3_BASE 0x4E51000ull
+#define SFT1_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000
+#define SFT1_HBW_RTR_IF0_RTR_H3_SECTION 0xE800
+#define SFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E51E80ull
+#define SFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E52000ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E52200ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E52400ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E52600ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define SFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E52800ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define SFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E52A80ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000
+#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E52B00ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E52B80ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E52C00ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E52D80ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define SFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E52E80ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E53000ull
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E53400ull
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E53E80ull
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define SFT1_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E54000ull
+#define SFT1_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT1_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800
+#define SFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E54E80ull
+#define SFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define SFT1_HBW_RTR_IF1_RTR_H3_BASE 0x4E55000ull
+#define SFT1_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000
+#define SFT1_HBW_RTR_IF1_RTR_H3_SECTION 0xE800
+#define SFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E55E80ull
+#define SFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E56000ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E56200ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E56400ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E56600ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define SFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E56800ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define SFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E56A80ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000
+#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E56B00ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E56B80ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E56C00ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E56D80ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define SFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E56E80ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E57000ull
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E57400ull
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E57E80ull
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define SFT1_LBW_RTR_IF_RTR_CTRL_BASE 0x4E58000ull
+#define SFT1_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT1_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800
+#define SFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E58E80ull
+#define SFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define SFT1_LBW_RTR_IF_RTR_H3_BASE 0x4E59000ull
+#define SFT1_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000
+#define SFT1_LBW_RTR_IF_RTR_H3_SECTION 0xE800
+#define SFT1_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E59E80ull
+#define SFT1_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E5A000ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E5A200ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E5A400ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E5A600ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define SFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E5A800ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define SFT1_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E5AA80ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT1_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000
+#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E5AB00ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E5AB80ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E5AC00ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E5AD80ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define SFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E5AE80ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800
+#define SFT1_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E5B000ull
+#define SFT1_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT1_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000
+#define SFT1_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E5B400ull
+#define SFT1_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT1_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800
+#define SFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E5BE80ull
+#define SFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define SFT1_BASE 0x4E5C000ull
+#define SFT1_MAX_OFFSET 0x1000
+#define SFT1_SECTION 0xE800
+#define SFT1_SPECIAL_BASE 0x4E5CE80ull
+#define SFT1_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_SPECIAL_SECTION 0x3180
+#define SFT2_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E60000ull
+#define SFT2_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT2_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800
+#define SFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E60E80ull
+#define SFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define SFT2_HBW_RTR_IF0_RTR_H3_BASE 0x4E61000ull
+#define SFT2_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000
+#define SFT2_HBW_RTR_IF0_RTR_H3_SECTION 0xE800
+#define SFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E61E80ull
+#define SFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E62000ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E62200ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E62400ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E62600ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define SFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E62800ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define SFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E62A80ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000
+#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E62B00ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E62B80ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E62C00ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E62D80ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define SFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E62E80ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E63000ull
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E63400ull
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E63E80ull
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define SFT2_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E64000ull
+#define SFT2_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT2_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800
+#define SFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E64E80ull
+#define SFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define SFT2_HBW_RTR_IF1_RTR_H3_BASE 0x4E65000ull
+#define SFT2_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000
+#define SFT2_HBW_RTR_IF1_RTR_H3_SECTION 0xE800
+#define SFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E65E80ull
+#define SFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E66000ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E66200ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E66400ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E66600ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define SFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E66800ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define SFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E66A80ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000
+#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E66B00ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E66B80ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E66C00ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E66D80ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define SFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E66E80ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E67000ull
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E67400ull
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E67E80ull
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define SFT2_LBW_RTR_IF_RTR_CTRL_BASE 0x4E68000ull
+#define SFT2_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT2_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800
+#define SFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E68E80ull
+#define SFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define SFT2_LBW_RTR_IF_RTR_H3_BASE 0x4E69000ull
+#define SFT2_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000
+#define SFT2_LBW_RTR_IF_RTR_H3_SECTION 0xE800
+#define SFT2_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E69E80ull
+#define SFT2_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E6A000ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E6A200ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E6A400ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E6A600ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define SFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E6A800ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define SFT2_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E6AA80ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT2_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000
+#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E6AB00ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E6AB80ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E6AC00ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E6AD80ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define SFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E6AE80ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800
+#define SFT2_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E6B000ull
+#define SFT2_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT2_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000
+#define SFT2_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E6B400ull
+#define SFT2_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT2_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800
+#define SFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E6BE80ull
+#define SFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define SFT2_BASE 0x4E6C000ull
+#define SFT2_MAX_OFFSET 0x1000
+#define SFT2_SECTION 0xE800
+#define SFT2_SPECIAL_BASE 0x4E6CE80ull
+#define SFT2_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_SPECIAL_SECTION 0x3180
+#define SFT3_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E70000ull
+#define SFT3_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT3_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800
+#define SFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E70E80ull
+#define SFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define SFT3_HBW_RTR_IF0_RTR_H3_BASE 0x4E71000ull
+#define SFT3_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000
+#define SFT3_HBW_RTR_IF0_RTR_H3_SECTION 0xE800
+#define SFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E71E80ull
+#define SFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E72000ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E72200ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E72400ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E72600ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define SFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E72800ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define SFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E72A80ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000
+#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E72B00ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E72B80ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E72C00ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E72D80ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define SFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E72E80ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E73000ull
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E73400ull
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E73E80ull
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define SFT3_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E74000ull
+#define SFT3_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT3_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800
+#define SFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E74E80ull
+#define SFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define SFT3_HBW_RTR_IF1_RTR_H3_BASE 0x4E75000ull
+#define SFT3_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000
+#define SFT3_HBW_RTR_IF1_RTR_H3_SECTION 0xE800
+#define SFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E75E80ull
+#define SFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E76000ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E76200ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E76400ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E76600ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define SFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E76800ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define SFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E76A80ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000
+#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E76B00ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E76B80ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E76C00ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E76D80ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define SFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E76E80ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E77000ull
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E77400ull
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E77E80ull
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define SFT3_LBW_RTR_IF_RTR_CTRL_BASE 0x4E78000ull
+#define SFT3_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT3_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800
+#define SFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E78E80ull
+#define SFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define SFT3_LBW_RTR_IF_RTR_H3_BASE 0x4E79000ull
+#define SFT3_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000
+#define SFT3_LBW_RTR_IF_RTR_H3_SECTION 0xE800
+#define SFT3_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E79E80ull
+#define SFT3_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E7A000ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E7A200ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E7A400ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E7A600ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define SFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E7A800ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define SFT3_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E7AA80ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT3_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000
+#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E7AB00ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E7AB80ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E7AC00ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E7AD80ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define SFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E7AE80ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800
+#define SFT3_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E7B000ull
+#define SFT3_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT3_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000
+#define SFT3_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E7B400ull
+#define SFT3_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT3_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800
+#define SFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E7BE80ull
+#define SFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define SFT3_BASE 0x4E7C000ull
+#define SFT3_MAX_OFFSET 0x1000
+#define SFT3_SECTION 0xE800
+#define SFT3_SPECIAL_BASE 0x4E7CE80ull
+#define SFT3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_SPECIAL_SECTION 0x4180
+#define ARC_FARM_FARM_BASE 0x4E81000ull
+#define ARC_FARM_FARM_MAX_OFFSET 0x1000
+#define ARC_FARM_FARM_SECTION 0xE800
+#define ARC_FARM_FARM_SPECIAL_BASE 0x4E81E80ull
+#define ARC_FARM_FARM_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_FARM_SPECIAL_SECTION 0x1800
+#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_BASE 0x4E82000ull
+#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_BASE 0x4E82200ull
+#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_BASE 0x4E82400ull
+#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_BASE 0x4E82600ull
+#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define ARC_FARM_FARM_MSTR_IF_E2E_CRDT_BASE 0x4E82800ull
+#define ARC_FARM_FARM_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define ARC_FARM_FARM_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define ARC_FARM_FARM_MSTR_IF_AXUSER_BASE 0x4E82A80ull
+#define ARC_FARM_FARM_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define ARC_FARM_FARM_MSTR_IF_AXUSER_SECTION 0x8000
+#define ARC_FARM_FARM_MSTR_IF_DBG_HBW_BASE 0x4E82B00ull
+#define ARC_FARM_FARM_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define ARC_FARM_FARM_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define ARC_FARM_FARM_MSTR_IF_DBG_LBW_BASE 0x4E82B80ull
+#define ARC_FARM_FARM_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define ARC_FARM_FARM_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define ARC_FARM_FARM_MSTR_IF_CORE_HBW_BASE 0x4E82C00ull
+#define ARC_FARM_FARM_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define ARC_FARM_FARM_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define ARC_FARM_FARM_MSTR_IF_CORE_LBW_BASE 0x4E82D80ull
+#define ARC_FARM_FARM_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define ARC_FARM_FARM_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define ARC_FARM_FARM_MSTR_IF_SPECIAL_BASE 0x4E82E80ull
+#define ARC_FARM_FARM_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_FARM_MSTR_IF_SPECIAL_SECTION 0x5180
+#define ARC_FARM_ARC0_AUX_BASE 0x4E88000ull
+#define ARC_FARM_ARC0_AUX_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC0_AUX_SECTION 0xE800
+#define ARC_FARM_ARC0_AUX_SPECIAL_BASE 0x4E88E80ull
+#define ARC_FARM_ARC0_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC0_AUX_SPECIAL_SECTION 0x1800
+#define ARC_FARM_ARC0_DUP_ENG_BASE 0x4E89000ull
+#define ARC_FARM_ARC0_DUP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC0_DUP_ENG_SECTION 0x9000
+#define ARC_FARM_ARC0_DUP_ENG_AXUSER_BASE 0x4E89900ull
+#define ARC_FARM_ARC0_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define ARC_FARM_ARC0_DUP_ENG_AXUSER_SECTION 0x5800
+#define ARC_FARM_ARC0_DUP_ENG_SPECIAL_BASE 0x4E89E80ull
+#define ARC_FARM_ARC0_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC0_DUP_ENG_SPECIAL_SECTION 0x1180
+#define ARC_FARM_KDMA_BASE 0x4E8B000ull
+#define ARC_FARM_KDMA_MAX_OFFSET 0x1000
+#define ARC_FARM_KDMA_SECTION 0x8000
+#define ARC_FARM_KDMA_CTX_AXUSER_BASE 0x4E8B800ull
+#define ARC_FARM_KDMA_CTX_AXUSER_MAX_OFFSET 0x5000
+#define ARC_FARM_KDMA_CTX_AXUSER_SECTION 0x6000
+#define ARC_FARM_KDMA_CTX_BASE 0x4E8B860ull
+#define ARC_FARM_KDMA_CTX_MAX_OFFSET 0x9000
+#define ARC_FARM_KDMA_CTX_SECTION 0x5A00
+#define ARC_FARM_KDMA_KDMA_CGM_BASE 0x4E8BE00ull
+#define ARC_FARM_KDMA_KDMA_CGM_MAX_OFFSET 0xC000
+#define ARC_FARM_KDMA_KDMA_CGM_SECTION 0x8000
+#define ARC_FARM_KDMA_SPECIAL_BASE 0x4E8BE80ull
+#define ARC_FARM_KDMA_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_KDMA_SPECIAL_SECTION 0x1800
+#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE 0x4E8C000ull
+#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_BASE 0x4E8C200ull
+#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_BASE 0x4E8C400ull
+#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_BASE 0x4E8C600ull
+#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define ARC_FARM_KDMA_MSTR_IF_E2E_CRDT_BASE 0x4E8C800ull
+#define ARC_FARM_KDMA_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define ARC_FARM_KDMA_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define ARC_FARM_KDMA_MSTR_IF_AXUSER_BASE 0x4E8CA80ull
+#define ARC_FARM_KDMA_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define ARC_FARM_KDMA_MSTR_IF_AXUSER_SECTION 0x8000
+#define ARC_FARM_KDMA_MSTR_IF_DBG_HBW_BASE 0x4E8CB00ull
+#define ARC_FARM_KDMA_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define ARC_FARM_KDMA_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define ARC_FARM_KDMA_MSTR_IF_DBG_LBW_BASE 0x4E8CB80ull
+#define ARC_FARM_KDMA_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define ARC_FARM_KDMA_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define ARC_FARM_KDMA_MSTR_IF_CORE_HBW_BASE 0x4E8CC00ull
+#define ARC_FARM_KDMA_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define ARC_FARM_KDMA_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define ARC_FARM_KDMA_MSTR_IF_CORE_LBW_BASE 0x4E8CD80ull
+#define ARC_FARM_KDMA_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define ARC_FARM_KDMA_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define ARC_FARM_KDMA_MSTR_IF_SPECIAL_BASE 0x4E8CE80ull
+#define ARC_FARM_KDMA_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_KDMA_MSTR_IF_SPECIAL_SECTION 0x2180
+#define ARC_FARM_ARC0_ACP_ENG_BASE 0x4E8F000ull
+#define ARC_FARM_ARC0_ACP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC0_ACP_ENG_SECTION 0xE800
+#define ARC_FARM_ARC0_ACP_ENG_SPECIAL_BASE 0x4E8FE80ull
+#define ARC_FARM_ARC0_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC0_ACP_ENG_SPECIAL_SECTION 0x1800
+#define ARC_FARM_ARC0_DCCM0_BASE 0x4E90000ull
+#define ARC_FARM_ARC0_DCCM0_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC0_DCCM0_SECTION 0x8000
+#define ARC_FARM_ARC0_DCCM1_BASE 0x4E98000ull
+#define ARC_FARM_ARC0_DCCM1_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC0_DCCM1_SECTION 0x10000
+#define ARC_FARM_ARC1_AUX_BASE 0x4EA8000ull
+#define ARC_FARM_ARC1_AUX_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC1_AUX_SECTION 0xE800
+#define ARC_FARM_ARC1_AUX_SPECIAL_BASE 0x4EA8E80ull
+#define ARC_FARM_ARC1_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC1_AUX_SPECIAL_SECTION 0x1800
+#define ARC_FARM_ARC1_DUP_ENG_BASE 0x4EA9000ull
+#define ARC_FARM_ARC1_DUP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC1_DUP_ENG_SECTION 0x9000
+#define ARC_FARM_ARC1_DUP_ENG_AXUSER_BASE 0x4EA9900ull
+#define ARC_FARM_ARC1_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define ARC_FARM_ARC1_DUP_ENG_AXUSER_SECTION 0x5800
+#define ARC_FARM_ARC1_DUP_ENG_SPECIAL_BASE 0x4EA9E80ull
+#define ARC_FARM_ARC1_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC1_DUP_ENG_SPECIAL_SECTION 0x5180
+#define ARC_FARM_ARC1_ACP_ENG_BASE 0x4EAF000ull
+#define ARC_FARM_ARC1_ACP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC1_ACP_ENG_SECTION 0xE800
+#define ARC_FARM_ARC1_ACP_ENG_SPECIAL_BASE 0x4EAFE80ull
+#define ARC_FARM_ARC1_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC1_ACP_ENG_SPECIAL_SECTION 0x1800
+#define ARC_FARM_ARC1_DCCM0_BASE 0x4EB0000ull
+#define ARC_FARM_ARC1_DCCM0_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC1_DCCM0_SECTION 0x8000
+#define ARC_FARM_ARC1_DCCM1_BASE 0x4EB8000ull
+#define ARC_FARM_ARC1_DCCM1_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC1_DCCM1_SECTION 0x10000
+#define ARC_FARM_ARC2_AUX_BASE 0x4EC8000ull
+#define ARC_FARM_ARC2_AUX_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC2_AUX_SECTION 0xE800
+#define ARC_FARM_ARC2_AUX_SPECIAL_BASE 0x4EC8E80ull
+#define ARC_FARM_ARC2_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC2_AUX_SPECIAL_SECTION 0x1800
+#define ARC_FARM_ARC2_DUP_ENG_BASE 0x4EC9000ull
+#define ARC_FARM_ARC2_DUP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC2_DUP_ENG_SECTION 0x9000
+#define ARC_FARM_ARC2_DUP_ENG_AXUSER_BASE 0x4EC9900ull
+#define ARC_FARM_ARC2_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define ARC_FARM_ARC2_DUP_ENG_AXUSER_SECTION 0x5800
+#define ARC_FARM_ARC2_DUP_ENG_SPECIAL_BASE 0x4EC9E80ull
+#define ARC_FARM_ARC2_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC2_DUP_ENG_SPECIAL_SECTION 0x5180
+#define ARC_FARM_ARC2_ACP_ENG_BASE 0x4ECF000ull
+#define ARC_FARM_ARC2_ACP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC2_ACP_ENG_SECTION 0xE800
+#define ARC_FARM_ARC2_ACP_ENG_SPECIAL_BASE 0x4ECFE80ull
+#define ARC_FARM_ARC2_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC2_ACP_ENG_SPECIAL_SECTION 0x1800
+#define ARC_FARM_ARC2_DCCM0_BASE 0x4ED0000ull
+#define ARC_FARM_ARC2_DCCM0_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC2_DCCM0_SECTION 0x8000
+#define ARC_FARM_ARC2_DCCM1_BASE 0x4ED8000ull
+#define ARC_FARM_ARC2_DCCM1_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC2_DCCM1_SECTION 0x10000
+#define ARC_FARM_ARC3_AUX_BASE 0x4EE8000ull
+#define ARC_FARM_ARC3_AUX_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC3_AUX_SECTION 0xE800
+#define ARC_FARM_ARC3_AUX_SPECIAL_BASE 0x4EE8E80ull
+#define ARC_FARM_ARC3_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC3_AUX_SPECIAL_SECTION 0x1800
+#define ARC_FARM_ARC3_DUP_ENG_BASE 0x4EE9000ull
+#define ARC_FARM_ARC3_DUP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC3_DUP_ENG_SECTION 0x9000
+#define ARC_FARM_ARC3_DUP_ENG_AXUSER_BASE 0x4EE9900ull
+#define ARC_FARM_ARC3_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define ARC_FARM_ARC3_DUP_ENG_AXUSER_SECTION 0x5800
+#define ARC_FARM_ARC3_DUP_ENG_SPECIAL_BASE 0x4EE9E80ull
+#define ARC_FARM_ARC3_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC3_DUP_ENG_SPECIAL_SECTION 0x5180
+#define ARC_FARM_ARC3_ACP_ENG_BASE 0x4EEF000ull
+#define ARC_FARM_ARC3_ACP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC3_ACP_ENG_SECTION 0xE800
+#define ARC_FARM_ARC3_ACP_ENG_SPECIAL_BASE 0x4EEFE80ull
+#define ARC_FARM_ARC3_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC3_ACP_ENG_SPECIAL_SECTION 0x1800
+#define ARC_FARM_ARC3_DCCM0_BASE 0x4EF0000ull
+#define ARC_FARM_ARC3_DCCM0_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC3_DCCM0_SECTION 0x8000
+#define ARC_FARM_ARC3_DCCM1_BASE 0x4EF8000ull
+#define ARC_FARM_ARC3_DCCM1_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC3_DCCM1_SECTION 0x8000
+#define PCIE_DEC0_CMD_BASE 0x4F00000ull
+#define PCIE_DEC0_CMD_MAX_OFFSET 0x1100
+#define PCIE_DEC0_CMD_SECTION 0x1000
+#define PCIE_DEC0_VSI_BASE 0x4F01000ull
+#define PCIE_DEC0_VSI_MAX_OFFSET 0x6FC0
+#define PCIE_DEC0_VSI_SECTION 0x1000
+#define PCIE_DEC0_L2C_BASE 0x4F02000ull
+#define PCIE_DEC0_L2C_MAX_OFFSET 0x39C0
+#define PCIE_DEC0_L2C_SECTION 0x1000
+#define PCIE_VDEC0_BRDG_CTRL_BASE 0x4F03000ull
+#define PCIE_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_BRDG_CTRL_SECTION 0x8000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x4F03800ull
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x4F03900ull
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x4F03A00ull
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x4F03B00ull
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x4F03C00ull
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define PCIE_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x4F03E80ull
+#define PCIE_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define PCIE_VDEC0_CTRL_BASE 0x4F04000ull
+#define PCIE_VDEC0_CTRL_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_CTRL_SECTION 0xE800
+#define PCIE_VDEC0_CTRL_SPECIAL_BASE 0x4F04E80ull
+#define PCIE_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_VDEC0_CTRL_SPECIAL_SECTION 0x1800
+#define PCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x4F05000ull
+#define PCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define PCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x4F05200ull
+#define PCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define PCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x4F05400ull
+#define PCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define PCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x4F05600ull
+#define PCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define PCIE_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x4F05800ull
+#define PCIE_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PCIE_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define PCIE_VDEC0_MSTR_IF_AXUSER_BASE 0x4F05A80ull
+#define PCIE_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PCIE_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define PCIE_VDEC0_MSTR_IF_DBG_HBW_BASE 0x4F05B00ull
+#define PCIE_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PCIE_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define PCIE_VDEC0_MSTR_IF_DBG_LBW_BASE 0x4F05B80ull
+#define PCIE_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PCIE_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define PCIE_VDEC0_MSTR_IF_CORE_HBW_BASE 0x4F05C00ull
+#define PCIE_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PCIE_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define PCIE_VDEC0_MSTR_IF_CORE_LBW_BASE 0x4F05D80ull
+#define PCIE_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PCIE_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define PCIE_VDEC0_MSTR_IF_SPECIAL_BASE 0x4F05E80ull
+#define PCIE_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
+#define PCIE_DEC1_CMD_BASE 0x4F10000ull
+#define PCIE_DEC1_CMD_MAX_OFFSET 0x1100
+#define PCIE_DEC1_CMD_SECTION 0x1000
+#define PCIE_DEC1_VSI_BASE 0x4F11000ull
+#define PCIE_DEC1_VSI_MAX_OFFSET 0x6FC0
+#define PCIE_DEC1_VSI_SECTION 0x1000
+#define PCIE_DEC1_L2C_BASE 0x4F12000ull
+#define PCIE_DEC1_L2C_MAX_OFFSET 0x39C0
+#define PCIE_DEC1_L2C_SECTION 0x1000
+#define PCIE_VDEC1_BRDG_CTRL_BASE 0x4F13000ull
+#define PCIE_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_BRDG_CTRL_SECTION 0x8000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x4F13800ull
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x4F13900ull
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x4F13A00ull
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x4F13B00ull
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x4F13C00ull
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define PCIE_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x4F13E80ull
+#define PCIE_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define PCIE_VDEC1_CTRL_BASE 0x4F14000ull
+#define PCIE_VDEC1_CTRL_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_CTRL_SECTION 0xE800
+#define PCIE_VDEC1_CTRL_SPECIAL_BASE 0x4F14E80ull
+#define PCIE_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_VDEC1_CTRL_SPECIAL_SECTION 0x1800
+#define PCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x4F15000ull
+#define PCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define PCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x4F15200ull
+#define PCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define PCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x4F15400ull
+#define PCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define PCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x4F15600ull
+#define PCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define PCIE_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x4F15800ull
+#define PCIE_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PCIE_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define PCIE_VDEC1_MSTR_IF_AXUSER_BASE 0x4F15A80ull
+#define PCIE_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PCIE_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define PCIE_VDEC1_MSTR_IF_DBG_HBW_BASE 0x4F15B00ull
+#define PCIE_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PCIE_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define PCIE_VDEC1_MSTR_IF_DBG_LBW_BASE 0x4F15B80ull
+#define PCIE_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PCIE_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define PCIE_VDEC1_MSTR_IF_CORE_HBW_BASE 0x4F15C00ull
+#define PCIE_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PCIE_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define PCIE_VDEC1_MSTR_IF_CORE_LBW_BASE 0x4F15D80ull
+#define PCIE_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PCIE_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define PCIE_VDEC1_MSTR_IF_SPECIAL_BASE 0x4F15E80ull
+#define PCIE_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_VDEC1_MSTR_IF_SPECIAL_SECTION 0x2A180
+#define DCORE0_XFT_BASE 0x4F40000ull
+#define DCORE0_XFT_MAX_OFFSET 0x1000
+#define DCORE0_XFT_SECTION 0xE800
+#define DCORE0_XFT_SPECIAL_BASE 0x4F40E80ull
+#define DCORE0_XFT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_XFT_SPECIAL_SECTION 0x1800
+#define DCORE0_HBM_PLL_CTRL_BASE 0x4F41000ull
+#define DCORE0_HBM_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE0_HBM_PLL_CTRL_SECTION 0x3600
+#define DCORE0_HBM_PLL_ASIF_SLV_BASE 0x4F41360ull
+#define DCORE0_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_HBM_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE0_HBM_PLL_DIV_0_RLX_BASE 0x4F41400ull
+#define DCORE0_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE0_HBM_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE0_HBM_PLL_DIV_1_RLX_BASE 0x4F41800ull
+#define DCORE0_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE0_HBM_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE0_HBM_PLL_DIV_2_RLX_BASE 0x4F41A00ull
+#define DCORE0_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE0_HBM_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE0_HBM_PLL_DIV_3_RLX_BASE 0x4F41C00ull
+#define DCORE0_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE0_HBM_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE0_HBM_PLL_SPECIAL_BASE 0x4F41E80ull
+#define DCORE0_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HBM_PLL_SPECIAL_SECTION 0x1800
+#define DCORE0_TPC_PLL_CTRL_BASE 0x4F42000ull
+#define DCORE0_TPC_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE0_TPC_PLL_CTRL_SECTION 0x3600
+#define DCORE0_TPC_PLL_ASIF_SLV_BASE 0x4F42360ull
+#define DCORE0_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_TPC_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE0_TPC_PLL_DIV_0_RLX_BASE 0x4F42400ull
+#define DCORE0_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE0_TPC_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE0_TPC_PLL_DIV_1_RLX_BASE 0x4F42800ull
+#define DCORE0_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE0_TPC_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE0_TPC_PLL_DIV_2_RLX_BASE 0x4F42A00ull
+#define DCORE0_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE0_TPC_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE0_TPC_PLL_DIV_3_RLX_BASE 0x4F42C00ull
+#define DCORE0_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE0_TPC_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE0_TPC_PLL_SPECIAL_BASE 0x4F42E80ull
+#define DCORE0_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC_PLL_SPECIAL_SECTION 0x1800
+#define DCORE0_PCI_PLL_CTRL_BASE 0x4F43000ull
+#define DCORE0_PCI_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE0_PCI_PLL_CTRL_SECTION 0x3600
+#define DCORE0_PCI_PLL_ASIF_SLV_BASE 0x4F43360ull
+#define DCORE0_PCI_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_PCI_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE0_PCI_PLL_DIV_0_RLX_BASE 0x4F43400ull
+#define DCORE0_PCI_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE0_PCI_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE0_PCI_PLL_DIV_1_RLX_BASE 0x4F43800ull
+#define DCORE0_PCI_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE0_PCI_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE0_PCI_PLL_DIV_2_RLX_BASE 0x4F43A00ull
+#define DCORE0_PCI_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE0_PCI_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE0_PCI_PLL_DIV_3_RLX_BASE 0x4F43C00ull
+#define DCORE0_PCI_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE0_PCI_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE0_PCI_PLL_SPECIAL_BASE 0x4F43E80ull
+#define DCORE0_PCI_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_PCI_PLL_SPECIAL_SECTION 0x1180
+#define DCORE0_TSTDVS_BASE 0x4F45000ull
+#define DCORE0_TSTDVS_MAX_OFFSET 0x7800
+#define DCORE0_TSTDVS_SECTION 0x1000
+#define DCORE0_TS_WRAP_BASE 0x4F46000ull
+#define DCORE0_TS_WRAP_MAX_OFFSET 0x2380
+#define DCORE0_TS_WRAP_SECTION 0x2000
+#define DCORE0_TS_WRAP_ASIF_SLV_BASE 0x4F46200ull
+#define DCORE0_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_TS_WRAP_ASIF_SLV_SECTION 0x9E00
+#define DCORE1_XFT_BASE 0x4F50000ull
+#define DCORE1_XFT_MAX_OFFSET 0x1000
+#define DCORE1_XFT_SECTION 0xE800
+#define DCORE1_XFT_SPECIAL_BASE 0x4F50E80ull
+#define DCORE1_XFT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_XFT_SPECIAL_SECTION 0x1800
+#define DCORE1_HBM_PLL_CTRL_BASE 0x4F51000ull
+#define DCORE1_HBM_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_HBM_PLL_CTRL_SECTION 0x3600
+#define DCORE1_HBM_PLL_ASIF_SLV_BASE 0x4F51360ull
+#define DCORE1_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_HBM_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE1_HBM_PLL_DIV_0_RLX_BASE 0x4F51400ull
+#define DCORE1_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_HBM_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE1_HBM_PLL_DIV_1_RLX_BASE 0x4F51800ull
+#define DCORE1_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_HBM_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE1_HBM_PLL_DIV_2_RLX_BASE 0x4F51A00ull
+#define DCORE1_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_HBM_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE1_HBM_PLL_DIV_3_RLX_BASE 0x4F51C00ull
+#define DCORE1_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_HBM_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE1_HBM_PLL_SPECIAL_BASE 0x4F51E80ull
+#define DCORE1_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HBM_PLL_SPECIAL_SECTION 0x1800
+#define DCORE1_TPC_PLL_CTRL_BASE 0x4F52000ull
+#define DCORE1_TPC_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_TPC_PLL_CTRL_SECTION 0x3600
+#define DCORE1_TPC_PLL_ASIF_SLV_BASE 0x4F52360ull
+#define DCORE1_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_TPC_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE1_TPC_PLL_DIV_0_RLX_BASE 0x4F52400ull
+#define DCORE1_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_TPC_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE1_TPC_PLL_DIV_1_RLX_BASE 0x4F52800ull
+#define DCORE1_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_TPC_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE1_TPC_PLL_DIV_2_RLX_BASE 0x4F52A00ull
+#define DCORE1_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_TPC_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE1_TPC_PLL_DIV_3_RLX_BASE 0x4F52C00ull
+#define DCORE1_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_TPC_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE1_TPC_PLL_SPECIAL_BASE 0x4F52E80ull
+#define DCORE1_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC_PLL_SPECIAL_SECTION 0x1800
+#define DCORE1_NIC_PLL_CTRL_BASE 0x4F53000ull
+#define DCORE1_NIC_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_NIC_PLL_CTRL_SECTION 0x3600
+#define DCORE1_NIC_PLL_ASIF_SLV_BASE 0x4F53360ull
+#define DCORE1_NIC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_NIC_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE1_NIC_PLL_DIV_0_RLX_BASE 0x4F53400ull
+#define DCORE1_NIC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_NIC_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE1_NIC_PLL_DIV_1_RLX_BASE 0x4F53800ull
+#define DCORE1_NIC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_NIC_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE1_NIC_PLL_DIV_2_RLX_BASE 0x4F53A00ull
+#define DCORE1_NIC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_NIC_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE1_NIC_PLL_DIV_3_RLX_BASE 0x4F53C00ull
+#define DCORE1_NIC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_NIC_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE1_NIC_PLL_SPECIAL_BASE 0x4F53E80ull
+#define DCORE1_NIC_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_NIC_PLL_SPECIAL_SECTION 0x1180
+#define DCORE1_TSTDVS_BASE 0x4F55000ull
+#define DCORE1_TSTDVS_MAX_OFFSET 0x7800
+#define DCORE1_TSTDVS_SECTION 0x1000
+#define DCORE1_TS_WRAP_BASE 0x4F56000ull
+#define DCORE1_TS_WRAP_MAX_OFFSET 0x2380
+#define DCORE1_TS_WRAP_SECTION 0x2000
+#define DCORE1_TS_WRAP_ASIF_SLV_BASE 0x4F56200ull
+#define DCORE1_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_TS_WRAP_ASIF_SLV_SECTION 0x9E00
+#define DCORE2_XFT_BASE 0x4F60000ull
+#define DCORE2_XFT_MAX_OFFSET 0x1000
+#define DCORE2_XFT_SECTION 0xE800
+#define DCORE2_XFT_SPECIAL_BASE 0x4F60E80ull
+#define DCORE2_XFT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_XFT_SPECIAL_SECTION 0x1800
+#define DCORE2_HBM_PLL_CTRL_BASE 0x4F61000ull
+#define DCORE2_HBM_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE2_HBM_PLL_CTRL_SECTION 0x3600
+#define DCORE2_HBM_PLL_ASIF_SLV_BASE 0x4F61360ull
+#define DCORE2_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_HBM_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE2_HBM_PLL_DIV_0_RLX_BASE 0x4F61400ull
+#define DCORE2_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE2_HBM_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE2_HBM_PLL_DIV_1_RLX_BASE 0x4F61800ull
+#define DCORE2_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE2_HBM_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE2_HBM_PLL_DIV_2_RLX_BASE 0x4F61A00ull
+#define DCORE2_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE2_HBM_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE2_HBM_PLL_DIV_3_RLX_BASE 0x4F61C00ull
+#define DCORE2_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE2_HBM_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE2_HBM_PLL_SPECIAL_BASE 0x4F61E80ull
+#define DCORE2_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HBM_PLL_SPECIAL_SECTION 0x1800
+#define DCORE2_TPC_PLL_CTRL_BASE 0x4F62000ull
+#define DCORE2_TPC_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE2_TPC_PLL_CTRL_SECTION 0x3600
+#define DCORE2_TPC_PLL_ASIF_SLV_BASE 0x4F62360ull
+#define DCORE2_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_TPC_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE2_TPC_PLL_DIV_0_RLX_BASE 0x4F62400ull
+#define DCORE2_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE2_TPC_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE2_TPC_PLL_DIV_1_RLX_BASE 0x4F62800ull
+#define DCORE2_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE2_TPC_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE2_TPC_PLL_DIV_2_RLX_BASE 0x4F62A00ull
+#define DCORE2_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE2_TPC_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE2_TPC_PLL_DIV_3_RLX_BASE 0x4F62C00ull
+#define DCORE2_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE2_TPC_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE2_TPC_PLL_SPECIAL_BASE 0x4F62E80ull
+#define DCORE2_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC_PLL_SPECIAL_SECTION 0x2180
+#define DCORE2_TSTDVS_BASE 0x4F65000ull
+#define DCORE2_TSTDVS_MAX_OFFSET 0x7800
+#define DCORE2_TSTDVS_SECTION 0x1000
+#define DCORE2_TS_WRAP_BASE 0x4F66000ull
+#define DCORE2_TS_WRAP_MAX_OFFSET 0x2380
+#define DCORE2_TS_WRAP_SECTION 0x2000
+#define DCORE2_TS_WRAP_ASIF_SLV_BASE 0x4F66200ull
+#define DCORE2_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_TS_WRAP_ASIF_SLV_SECTION 0x9E00
+#define DCORE3_XFT_BASE 0x4F70000ull
+#define DCORE3_XFT_MAX_OFFSET 0x1000
+#define DCORE3_XFT_SECTION 0xE800
+#define DCORE3_XFT_SPECIAL_BASE 0x4F70E80ull
+#define DCORE3_XFT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_XFT_SPECIAL_SECTION 0x1800
+#define DCORE3_HBM_PLL_CTRL_BASE 0x4F71000ull
+#define DCORE3_HBM_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE3_HBM_PLL_CTRL_SECTION 0x3600
+#define DCORE3_HBM_PLL_ASIF_SLV_BASE 0x4F71360ull
+#define DCORE3_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_HBM_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE3_HBM_PLL_DIV_0_RLX_BASE 0x4F71400ull
+#define DCORE3_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE3_HBM_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE3_HBM_PLL_DIV_1_RLX_BASE 0x4F71800ull
+#define DCORE3_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE3_HBM_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE3_HBM_PLL_DIV_2_RLX_BASE 0x4F71A00ull
+#define DCORE3_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE3_HBM_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE3_HBM_PLL_DIV_3_RLX_BASE 0x4F71C00ull
+#define DCORE3_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE3_HBM_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE3_HBM_PLL_SPECIAL_BASE 0x4F71E80ull
+#define DCORE3_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HBM_PLL_SPECIAL_SECTION 0x1800
+#define DCORE3_TPC_PLL_CTRL_BASE 0x4F72000ull
+#define DCORE3_TPC_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE3_TPC_PLL_CTRL_SECTION 0x3600
+#define DCORE3_TPC_PLL_ASIF_SLV_BASE 0x4F72360ull
+#define DCORE3_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_TPC_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE3_TPC_PLL_DIV_0_RLX_BASE 0x4F72400ull
+#define DCORE3_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE3_TPC_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE3_TPC_PLL_DIV_1_RLX_BASE 0x4F72800ull
+#define DCORE3_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE3_TPC_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE3_TPC_PLL_DIV_2_RLX_BASE 0x4F72A00ull
+#define DCORE3_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE3_TPC_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE3_TPC_PLL_DIV_3_RLX_BASE 0x4F72C00ull
+#define DCORE3_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE3_TPC_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE3_TPC_PLL_SPECIAL_BASE 0x4F72E80ull
+#define DCORE3_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC_PLL_SPECIAL_SECTION 0x1800
+#define DCORE3_NIC_PLL_CTRL_BASE 0x4F73000ull
+#define DCORE3_NIC_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE3_NIC_PLL_CTRL_SECTION 0x3600
+#define DCORE3_NIC_PLL_ASIF_SLV_BASE 0x4F73360ull
+#define DCORE3_NIC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_NIC_PLL_ASIF_SLV_SECTION 0xA000
+#define DCORE3_NIC_PLL_DIV_0_RLX_BASE 0x4F73400ull
+#define DCORE3_NIC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE3_NIC_PLL_DIV_0_RLX_SECTION 0x4000
+#define DCORE3_NIC_PLL_DIV_1_RLX_BASE 0x4F73800ull
+#define DCORE3_NIC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE3_NIC_PLL_DIV_1_RLX_SECTION 0x2000
+#define DCORE3_NIC_PLL_DIV_2_RLX_BASE 0x4F73A00ull
+#define DCORE3_NIC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE3_NIC_PLL_DIV_2_RLX_SECTION 0x2000
+#define DCORE3_NIC_PLL_DIV_3_RLX_BASE 0x4F73C00ull
+#define DCORE3_NIC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE3_NIC_PLL_DIV_3_RLX_SECTION 0x2800
+#define DCORE3_NIC_PLL_SPECIAL_BASE 0x4F73E80ull
+#define DCORE3_NIC_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_NIC_PLL_SPECIAL_SECTION 0x1180
+#define DCORE3_TSTDVS_BASE 0x4F75000ull
+#define DCORE3_TSTDVS_MAX_OFFSET 0x7800
+#define DCORE3_TSTDVS_SECTION 0x1000
+#define DCORE3_TS_WRAP_BASE 0x4F76000ull
+#define DCORE3_TS_WRAP_MAX_OFFSET 0x2380
+#define DCORE3_TS_WRAP_SECTION 0x2000
+#define DCORE3_TS_WRAP_ASIF_SLV_BASE 0x4F76200ull
+#define DCORE3_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_TS_WRAP_ASIF_SLV_SECTION 0x9E00
+#define PCIE_PMA_2_BASE 0x4F80000ull
+#define PCIE_PMA_2_MAX_OFFSET 0x40000
+#define PCIE_PMA_2_SECTION 0x40000
+#define PCIE_PMA_3_BASE 0x4FC0000ull
+#define PCIE_PMA_3_MAX_OFFSET 0x40000
+#define PCIE_PMA_3_SECTION 0x40000
+#define HBM0_MC0_BASE 0x5000000ull
+#define HBM0_MC0_MAX_OFFSET 0x1000
+#define HBM0_MC0_SECTION 0xE800
+#define HBM0_MC0_SPECIAL_BASE 0x5000E80ull
+#define HBM0_MC0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0_SPECIAL_SECTION 0x1800
+#define HBM0_MC0BIST0_BASE 0x5001000ull
+#define HBM0_MC0BIST0_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST0_SECTION 0xE800
+#define HBM0_MC0BIST0_SPECIAL_BASE 0x5001E80ull
+#define HBM0_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST0_SPECIAL_SECTION 0x1800
+#define HBM0_MC0BIST1_BASE 0x5002000ull
+#define HBM0_MC0BIST1_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST1_SECTION 0xE800
+#define HBM0_MC0BIST1_SPECIAL_BASE 0x5002E80ull
+#define HBM0_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST1_SPECIAL_SECTION 0x1800
+#define HBM0_MC0BIST2_BASE 0x5003000ull
+#define HBM0_MC0BIST2_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST2_SECTION 0xE800
+#define HBM0_MC0BIST2_SPECIAL_BASE 0x5003E80ull
+#define HBM0_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST2_SPECIAL_SECTION 0x1800
+#define HBM0_MC0BIST3_BASE 0x5004000ull
+#define HBM0_MC0BIST3_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST3_SECTION 0xE800
+#define HBM0_MC0BIST3_SPECIAL_BASE 0x5004E80ull
+#define HBM0_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST3_SPECIAL_SECTION 0x1800
+#define HBM0_MC0BIST4_BASE 0x5005000ull
+#define HBM0_MC0BIST4_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST4_SECTION 0xE800
+#define HBM0_MC0BIST4_SPECIAL_BASE 0x5005E80ull
+#define HBM0_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST4_SPECIAL_SECTION 0x1800
+#define HBM0_MC0BIST5_BASE 0x5006000ull
+#define HBM0_MC0BIST5_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST5_SECTION 0xE800
+#define HBM0_MC0BIST5_SPECIAL_BASE 0x5006E80ull
+#define HBM0_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST5_SPECIAL_SECTION 0x1800
+#define HBM0_MC0BIST6_BASE 0x5007000ull
+#define HBM0_MC0BIST6_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST6_SECTION 0xE800
+#define HBM0_MC0BIST6_SPECIAL_BASE 0x5007E80ull
+#define HBM0_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST6_SPECIAL_SECTION 0x1800
+#define HBM0_MC0BIST7_BASE 0x5008000ull
+#define HBM0_MC0BIST7_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST7_SECTION 0xE800
+#define HBM0_MC0BIST7_SPECIAL_BASE 0x5008E80ull
+#define HBM0_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST7_SPECIAL_SECTION 0x1800
+#define HBM0_MC0BIST8_MEM_BASE 0x5009000ull
+#define HBM0_MC0BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST8_MEM_SECTION 0xE800
+#define HBM0_MC0BIST8_MEM_SPECIAL_BASE 0x5009E80ull
+#define HBM0_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
+#define HBM0_MC1_BASE 0x5020000ull
+#define HBM0_MC1_MAX_OFFSET 0x1000
+#define HBM0_MC1_SECTION 0xE800
+#define HBM0_MC1_SPECIAL_BASE 0x5020E80ull
+#define HBM0_MC1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1_SPECIAL_SECTION 0x1800
+#define HBM0_MC1BIST0_BASE 0x5021000ull
+#define HBM0_MC1BIST0_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST0_SECTION 0xE800
+#define HBM0_MC1BIST0_SPECIAL_BASE 0x5021E80ull
+#define HBM0_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST0_SPECIAL_SECTION 0x1800
+#define HBM0_MC1BIST1_BASE 0x5022000ull
+#define HBM0_MC1BIST1_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST1_SECTION 0xE800
+#define HBM0_MC1BIST1_SPECIAL_BASE 0x5022E80ull
+#define HBM0_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST1_SPECIAL_SECTION 0x1800
+#define HBM0_MC1BIST2_BASE 0x5023000ull
+#define HBM0_MC1BIST2_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST2_SECTION 0xE800
+#define HBM0_MC1BIST2_SPECIAL_BASE 0x5023E80ull
+#define HBM0_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST2_SPECIAL_SECTION 0x1800
+#define HBM0_MC1BIST3_BASE 0x5024000ull
+#define HBM0_MC1BIST3_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST3_SECTION 0xE800
+#define HBM0_MC1BIST3_SPECIAL_BASE 0x5024E80ull
+#define HBM0_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST3_SPECIAL_SECTION 0x1800
+#define HBM0_MC1BIST4_BASE 0x5025000ull
+#define HBM0_MC1BIST4_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST4_SECTION 0xE800
+#define HBM0_MC1BIST4_SPECIAL_BASE 0x5025E80ull
+#define HBM0_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST4_SPECIAL_SECTION 0x1800
+#define HBM0_MC1BIST5_BASE 0x5026000ull
+#define HBM0_MC1BIST5_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST5_SECTION 0xE800
+#define HBM0_MC1BIST5_SPECIAL_BASE 0x5026E80ull
+#define HBM0_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST5_SPECIAL_SECTION 0x1800
+#define HBM0_MC1BIST6_BASE 0x5027000ull
+#define HBM0_MC1BIST6_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST6_SECTION 0xE800
+#define HBM0_MC1BIST6_SPECIAL_BASE 0x5027E80ull
+#define HBM0_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST6_SPECIAL_SECTION 0x1800
+#define HBM0_MC1BIST7_BASE 0x5028000ull
+#define HBM0_MC1BIST7_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST7_SECTION 0xE800
+#define HBM0_MC1BIST7_SPECIAL_BASE 0x5028E80ull
+#define HBM0_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST7_SPECIAL_SECTION 0x1800
+#define HBM0_MC1BIST8_MEM_BASE 0x5029000ull
+#define HBM0_MC1BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST8_MEM_SECTION 0xE800
+#define HBM0_MC1BIST8_MEM_SPECIAL_BASE 0x5029E80ull
+#define HBM0_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
+#define HBM0_PHY_BASE 0x5040000ull
+#define HBM0_PHY_MAX_OFFSET 0x4000
+#define HBM0_PHY_SECTION 0x40000
+#define HBM1_MC0_BASE 0x5080000ull
+#define HBM1_MC0_MAX_OFFSET 0x1000
+#define HBM1_MC0_SECTION 0xE800
+#define HBM1_MC0_SPECIAL_BASE 0x5080E80ull
+#define HBM1_MC0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0_SPECIAL_SECTION 0x1800
+#define HBM1_MC0BIST0_BASE 0x5081000ull
+#define HBM1_MC0BIST0_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST0_SECTION 0xE800
+#define HBM1_MC0BIST0_SPECIAL_BASE 0x5081E80ull
+#define HBM1_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST0_SPECIAL_SECTION 0x1800
+#define HBM1_MC0BIST1_BASE 0x5082000ull
+#define HBM1_MC0BIST1_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST1_SECTION 0xE800
+#define HBM1_MC0BIST1_SPECIAL_BASE 0x5082E80ull
+#define HBM1_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST1_SPECIAL_SECTION 0x1800
+#define HBM1_MC0BIST2_BASE 0x5083000ull
+#define HBM1_MC0BIST2_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST2_SECTION 0xE800
+#define HBM1_MC0BIST2_SPECIAL_BASE 0x5083E80ull
+#define HBM1_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST2_SPECIAL_SECTION 0x1800
+#define HBM1_MC0BIST3_BASE 0x5084000ull
+#define HBM1_MC0BIST3_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST3_SECTION 0xE800
+#define HBM1_MC0BIST3_SPECIAL_BASE 0x5084E80ull
+#define HBM1_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST3_SPECIAL_SECTION 0x1800
+#define HBM1_MC0BIST4_BASE 0x5085000ull
+#define HBM1_MC0BIST4_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST4_SECTION 0xE800
+#define HBM1_MC0BIST4_SPECIAL_BASE 0x5085E80ull
+#define HBM1_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST4_SPECIAL_SECTION 0x1800
+#define HBM1_MC0BIST5_BASE 0x5086000ull
+#define HBM1_MC0BIST5_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST5_SECTION 0xE800
+#define HBM1_MC0BIST5_SPECIAL_BASE 0x5086E80ull
+#define HBM1_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST5_SPECIAL_SECTION 0x1800
+#define HBM1_MC0BIST6_BASE 0x5087000ull
+#define HBM1_MC0BIST6_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST6_SECTION 0xE800
+#define HBM1_MC0BIST6_SPECIAL_BASE 0x5087E80ull
+#define HBM1_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST6_SPECIAL_SECTION 0x1800
+#define HBM1_MC0BIST7_BASE 0x5088000ull
+#define HBM1_MC0BIST7_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST7_SECTION 0xE800
+#define HBM1_MC0BIST7_SPECIAL_BASE 0x5088E80ull
+#define HBM1_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST7_SPECIAL_SECTION 0x1800
+#define HBM1_MC0BIST8_MEM_BASE 0x5089000ull
+#define HBM1_MC0BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST8_MEM_SECTION 0xE800
+#define HBM1_MC0BIST8_MEM_SPECIAL_BASE 0x5089E80ull
+#define HBM1_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
+#define HBM1_MC1_BASE 0x50A0000ull
+#define HBM1_MC1_MAX_OFFSET 0x1000
+#define HBM1_MC1_SECTION 0xE800
+#define HBM1_MC1_SPECIAL_BASE 0x50A0E80ull
+#define HBM1_MC1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1_SPECIAL_SECTION 0x1800
+#define HBM1_MC1BIST0_BASE 0x50A1000ull
+#define HBM1_MC1BIST0_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST0_SECTION 0xE800
+#define HBM1_MC1BIST0_SPECIAL_BASE 0x50A1E80ull
+#define HBM1_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST0_SPECIAL_SECTION 0x1800
+#define HBM1_MC1BIST1_BASE 0x50A2000ull
+#define HBM1_MC1BIST1_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST1_SECTION 0xE800
+#define HBM1_MC1BIST1_SPECIAL_BASE 0x50A2E80ull
+#define HBM1_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST1_SPECIAL_SECTION 0x1800
+#define HBM1_MC1BIST2_BASE 0x50A3000ull
+#define HBM1_MC1BIST2_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST2_SECTION 0xE800
+#define HBM1_MC1BIST2_SPECIAL_BASE 0x50A3E80ull
+#define HBM1_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST2_SPECIAL_SECTION 0x1800
+#define HBM1_MC1BIST3_BASE 0x50A4000ull
+#define HBM1_MC1BIST3_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST3_SECTION 0xE800
+#define HBM1_MC1BIST3_SPECIAL_BASE 0x50A4E80ull
+#define HBM1_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST3_SPECIAL_SECTION 0x1800
+#define HBM1_MC1BIST4_BASE 0x50A5000ull
+#define HBM1_MC1BIST4_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST4_SECTION 0xE800
+#define HBM1_MC1BIST4_SPECIAL_BASE 0x50A5E80ull
+#define HBM1_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST4_SPECIAL_SECTION 0x1800
+#define HBM1_MC1BIST5_BASE 0x50A6000ull
+#define HBM1_MC1BIST5_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST5_SECTION 0xE800
+#define HBM1_MC1BIST5_SPECIAL_BASE 0x50A6E80ull
+#define HBM1_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST5_SPECIAL_SECTION 0x1800
+#define HBM1_MC1BIST6_BASE 0x50A7000ull
+#define HBM1_MC1BIST6_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST6_SECTION 0xE800
+#define HBM1_MC1BIST6_SPECIAL_BASE 0x50A7E80ull
+#define HBM1_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST6_SPECIAL_SECTION 0x1800
+#define HBM1_MC1BIST7_BASE 0x50A8000ull
+#define HBM1_MC1BIST7_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST7_SECTION 0xE800
+#define HBM1_MC1BIST7_SPECIAL_BASE 0x50A8E80ull
+#define HBM1_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST7_SPECIAL_SECTION 0x1800
+#define HBM1_MC1BIST8_MEM_BASE 0x50A9000ull
+#define HBM1_MC1BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST8_MEM_SECTION 0xE800
+#define HBM1_MC1BIST8_MEM_SPECIAL_BASE 0x50A9E80ull
+#define HBM1_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
+#define HBM1_PHY_BASE 0x50C0000ull
+#define HBM1_PHY_MAX_OFFSET 0x4000
+#define HBM1_PHY_SECTION 0x40000
+#define HBM2_MC0_BASE 0x5100000ull
+#define HBM2_MC0_MAX_OFFSET 0x1000
+#define HBM2_MC0_SECTION 0xE800
+#define HBM2_MC0_SPECIAL_BASE 0x5100E80ull
+#define HBM2_MC0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0_SPECIAL_SECTION 0x1800
+#define HBM2_MC0BIST0_BASE 0x5101000ull
+#define HBM2_MC0BIST0_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST0_SECTION 0xE800
+#define HBM2_MC0BIST0_SPECIAL_BASE 0x5101E80ull
+#define HBM2_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST0_SPECIAL_SECTION 0x1800
+#define HBM2_MC0BIST1_BASE 0x5102000ull
+#define HBM2_MC0BIST1_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST1_SECTION 0xE800
+#define HBM2_MC0BIST1_SPECIAL_BASE 0x5102E80ull
+#define HBM2_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST1_SPECIAL_SECTION 0x1800
+#define HBM2_MC0BIST2_BASE 0x5103000ull
+#define HBM2_MC0BIST2_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST2_SECTION 0xE800
+#define HBM2_MC0BIST2_SPECIAL_BASE 0x5103E80ull
+#define HBM2_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST2_SPECIAL_SECTION 0x1800
+#define HBM2_MC0BIST3_BASE 0x5104000ull
+#define HBM2_MC0BIST3_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST3_SECTION 0xE800
+#define HBM2_MC0BIST3_SPECIAL_BASE 0x5104E80ull
+#define HBM2_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST3_SPECIAL_SECTION 0x1800
+#define HBM2_MC0BIST4_BASE 0x5105000ull
+#define HBM2_MC0BIST4_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST4_SECTION 0xE800
+#define HBM2_MC0BIST4_SPECIAL_BASE 0x5105E80ull
+#define HBM2_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST4_SPECIAL_SECTION 0x1800
+#define HBM2_MC0BIST5_BASE 0x5106000ull
+#define HBM2_MC0BIST5_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST5_SECTION 0xE800
+#define HBM2_MC0BIST5_SPECIAL_BASE 0x5106E80ull
+#define HBM2_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST5_SPECIAL_SECTION 0x1800
+#define HBM2_MC0BIST6_BASE 0x5107000ull
+#define HBM2_MC0BIST6_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST6_SECTION 0xE800
+#define HBM2_MC0BIST6_SPECIAL_BASE 0x5107E80ull
+#define HBM2_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST6_SPECIAL_SECTION 0x1800
+#define HBM2_MC0BIST7_BASE 0x5108000ull
+#define HBM2_MC0BIST7_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST7_SECTION 0xE800
+#define HBM2_MC0BIST7_SPECIAL_BASE 0x5108E80ull
+#define HBM2_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST7_SPECIAL_SECTION 0x1800
+#define HBM2_MC0BIST8_MEM_BASE 0x5109000ull
+#define HBM2_MC0BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST8_MEM_SECTION 0xE800
+#define HBM2_MC0BIST8_MEM_SPECIAL_BASE 0x5109E80ull
+#define HBM2_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
+#define HBM2_MC1_BASE 0x5120000ull
+#define HBM2_MC1_MAX_OFFSET 0x1000
+#define HBM2_MC1_SECTION 0xE800
+#define HBM2_MC1_SPECIAL_BASE 0x5120E80ull
+#define HBM2_MC1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1_SPECIAL_SECTION 0x1800
+#define HBM2_MC1BIST0_BASE 0x5121000ull
+#define HBM2_MC1BIST0_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST0_SECTION 0xE800
+#define HBM2_MC1BIST0_SPECIAL_BASE 0x5121E80ull
+#define HBM2_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST0_SPECIAL_SECTION 0x1800
+#define HBM2_MC1BIST1_BASE 0x5122000ull
+#define HBM2_MC1BIST1_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST1_SECTION 0xE800
+#define HBM2_MC1BIST1_SPECIAL_BASE 0x5122E80ull
+#define HBM2_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST1_SPECIAL_SECTION 0x1800
+#define HBM2_MC1BIST2_BASE 0x5123000ull
+#define HBM2_MC1BIST2_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST2_SECTION 0xE800
+#define HBM2_MC1BIST2_SPECIAL_BASE 0x5123E80ull
+#define HBM2_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST2_SPECIAL_SECTION 0x1800
+#define HBM2_MC1BIST3_BASE 0x5124000ull
+#define HBM2_MC1BIST3_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST3_SECTION 0xE800
+#define HBM2_MC1BIST3_SPECIAL_BASE 0x5124E80ull
+#define HBM2_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST3_SPECIAL_SECTION 0x1800
+#define HBM2_MC1BIST4_BASE 0x5125000ull
+#define HBM2_MC1BIST4_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST4_SECTION 0xE800
+#define HBM2_MC1BIST4_SPECIAL_BASE 0x5125E80ull
+#define HBM2_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST4_SPECIAL_SECTION 0x1800
+#define HBM2_MC1BIST5_BASE 0x5126000ull
+#define HBM2_MC1BIST5_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST5_SECTION 0xE800
+#define HBM2_MC1BIST5_SPECIAL_BASE 0x5126E80ull
+#define HBM2_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST5_SPECIAL_SECTION 0x1800
+#define HBM2_MC1BIST6_BASE 0x5127000ull
+#define HBM2_MC1BIST6_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST6_SECTION 0xE800
+#define HBM2_MC1BIST6_SPECIAL_BASE 0x5127E80ull
+#define HBM2_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST6_SPECIAL_SECTION 0x1800
+#define HBM2_MC1BIST7_BASE 0x5128000ull
+#define HBM2_MC1BIST7_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST7_SECTION 0xE800
+#define HBM2_MC1BIST7_SPECIAL_BASE 0x5128E80ull
+#define HBM2_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST7_SPECIAL_SECTION 0x1800
+#define HBM2_MC1BIST8_MEM_BASE 0x5129000ull
+#define HBM2_MC1BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST8_MEM_SECTION 0xE800
+#define HBM2_MC1BIST8_MEM_SPECIAL_BASE 0x5129E80ull
+#define HBM2_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
+#define HBM2_PHY_BASE 0x5140000ull
+#define HBM2_PHY_MAX_OFFSET 0x4000
+#define HBM2_PHY_SECTION 0x40000
+#define HBM3_MC0_BASE 0x5180000ull
+#define HBM3_MC0_MAX_OFFSET 0x1000
+#define HBM3_MC0_SECTION 0xE800
+#define HBM3_MC0_SPECIAL_BASE 0x5180E80ull
+#define HBM3_MC0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0_SPECIAL_SECTION 0x1800
+#define HBM3_MC0BIST0_BASE 0x5181000ull
+#define HBM3_MC0BIST0_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST0_SECTION 0xE800
+#define HBM3_MC0BIST0_SPECIAL_BASE 0x5181E80ull
+#define HBM3_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST0_SPECIAL_SECTION 0x1800
+#define HBM3_MC0BIST1_BASE 0x5182000ull
+#define HBM3_MC0BIST1_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST1_SECTION 0xE800
+#define HBM3_MC0BIST1_SPECIAL_BASE 0x5182E80ull
+#define HBM3_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST1_SPECIAL_SECTION 0x1800
+#define HBM3_MC0BIST2_BASE 0x5183000ull
+#define HBM3_MC0BIST2_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST2_SECTION 0xE800
+#define HBM3_MC0BIST2_SPECIAL_BASE 0x5183E80ull
+#define HBM3_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST2_SPECIAL_SECTION 0x1800
+#define HBM3_MC0BIST3_BASE 0x5184000ull
+#define HBM3_MC0BIST3_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST3_SECTION 0xE800
+#define HBM3_MC0BIST3_SPECIAL_BASE 0x5184E80ull
+#define HBM3_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST3_SPECIAL_SECTION 0x1800
+#define HBM3_MC0BIST4_BASE 0x5185000ull
+#define HBM3_MC0BIST4_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST4_SECTION 0xE800
+#define HBM3_MC0BIST4_SPECIAL_BASE 0x5185E80ull
+#define HBM3_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST4_SPECIAL_SECTION 0x1800
+#define HBM3_MC0BIST5_BASE 0x5186000ull
+#define HBM3_MC0BIST5_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST5_SECTION 0xE800
+#define HBM3_MC0BIST5_SPECIAL_BASE 0x5186E80ull
+#define HBM3_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST5_SPECIAL_SECTION 0x1800
+#define HBM3_MC0BIST6_BASE 0x5187000ull
+#define HBM3_MC0BIST6_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST6_SECTION 0xE800
+#define HBM3_MC0BIST6_SPECIAL_BASE 0x5187E80ull
+#define HBM3_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST6_SPECIAL_SECTION 0x1800
+#define HBM3_MC0BIST7_BASE 0x5188000ull
+#define HBM3_MC0BIST7_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST7_SECTION 0xE800
+#define HBM3_MC0BIST7_SPECIAL_BASE 0x5188E80ull
+#define HBM3_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST7_SPECIAL_SECTION 0x1800
+#define HBM3_MC0BIST8_MEM_BASE 0x5189000ull
+#define HBM3_MC0BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST8_MEM_SECTION 0xE800
+#define HBM3_MC0BIST8_MEM_SPECIAL_BASE 0x5189E80ull
+#define HBM3_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
+#define HBM3_MC1_BASE 0x51A0000ull
+#define HBM3_MC1_MAX_OFFSET 0x1000
+#define HBM3_MC1_SECTION 0xE800
+#define HBM3_MC1_SPECIAL_BASE 0x51A0E80ull
+#define HBM3_MC1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1_SPECIAL_SECTION 0x1800
+#define HBM3_MC1BIST0_BASE 0x51A1000ull
+#define HBM3_MC1BIST0_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST0_SECTION 0xE800
+#define HBM3_MC1BIST0_SPECIAL_BASE 0x51A1E80ull
+#define HBM3_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST0_SPECIAL_SECTION 0x1800
+#define HBM3_MC1BIST1_BASE 0x51A2000ull
+#define HBM3_MC1BIST1_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST1_SECTION 0xE800
+#define HBM3_MC1BIST1_SPECIAL_BASE 0x51A2E80ull
+#define HBM3_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST1_SPECIAL_SECTION 0x1800
+#define HBM3_MC1BIST2_BASE 0x51A3000ull
+#define HBM3_MC1BIST2_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST2_SECTION 0xE800
+#define HBM3_MC1BIST2_SPECIAL_BASE 0x51A3E80ull
+#define HBM3_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST2_SPECIAL_SECTION 0x1800
+#define HBM3_MC1BIST3_BASE 0x51A4000ull
+#define HBM3_MC1BIST3_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST3_SECTION 0xE800
+#define HBM3_MC1BIST3_SPECIAL_BASE 0x51A4E80ull
+#define HBM3_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST3_SPECIAL_SECTION 0x1800
+#define HBM3_MC1BIST4_BASE 0x51A5000ull
+#define HBM3_MC1BIST4_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST4_SECTION 0xE800
+#define HBM3_MC1BIST4_SPECIAL_BASE 0x51A5E80ull
+#define HBM3_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST4_SPECIAL_SECTION 0x1800
+#define HBM3_MC1BIST5_BASE 0x51A6000ull
+#define HBM3_MC1BIST5_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST5_SECTION 0xE800
+#define HBM3_MC1BIST5_SPECIAL_BASE 0x51A6E80ull
+#define HBM3_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST5_SPECIAL_SECTION 0x1800
+#define HBM3_MC1BIST6_BASE 0x51A7000ull
+#define HBM3_MC1BIST6_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST6_SECTION 0xE800
+#define HBM3_MC1BIST6_SPECIAL_BASE 0x51A7E80ull
+#define HBM3_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST6_SPECIAL_SECTION 0x1800
+#define HBM3_MC1BIST7_BASE 0x51A8000ull
+#define HBM3_MC1BIST7_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST7_SECTION 0xE800
+#define HBM3_MC1BIST7_SPECIAL_BASE 0x51A8E80ull
+#define HBM3_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST7_SPECIAL_SECTION 0x1800
+#define HBM3_MC1BIST8_MEM_BASE 0x51A9000ull
+#define HBM3_MC1BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST8_MEM_SECTION 0xE800
+#define HBM3_MC1BIST8_MEM_SPECIAL_BASE 0x51A9E80ull
+#define HBM3_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
+#define HBM3_PHY_BASE 0x51C0000ull
+#define HBM3_PHY_MAX_OFFSET 0x4000
+#define HBM3_PHY_SECTION 0x40000
+#define HBM4_MC0_BASE 0x5200000ull
+#define HBM4_MC0_MAX_OFFSET 0x1000
+#define HBM4_MC0_SECTION 0xE800
+#define HBM4_MC0_SPECIAL_BASE 0x5200E80ull
+#define HBM4_MC0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0_SPECIAL_SECTION 0x1800
+#define HBM4_MC0BIST0_BASE 0x5201000ull
+#define HBM4_MC0BIST0_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST0_SECTION 0xE800
+#define HBM4_MC0BIST0_SPECIAL_BASE 0x5201E80ull
+#define HBM4_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST0_SPECIAL_SECTION 0x1800
+#define HBM4_MC0BIST1_BASE 0x5202000ull
+#define HBM4_MC0BIST1_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST1_SECTION 0xE800
+#define HBM4_MC0BIST1_SPECIAL_BASE 0x5202E80ull
+#define HBM4_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST1_SPECIAL_SECTION 0x1800
+#define HBM4_MC0BIST2_BASE 0x5203000ull
+#define HBM4_MC0BIST2_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST2_SECTION 0xE800
+#define HBM4_MC0BIST2_SPECIAL_BASE 0x5203E80ull
+#define HBM4_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST2_SPECIAL_SECTION 0x1800
+#define HBM4_MC0BIST3_BASE 0x5204000ull
+#define HBM4_MC0BIST3_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST3_SECTION 0xE800
+#define HBM4_MC0BIST3_SPECIAL_BASE 0x5204E80ull
+#define HBM4_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST3_SPECIAL_SECTION 0x1800
+#define HBM4_MC0BIST4_BASE 0x5205000ull
+#define HBM4_MC0BIST4_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST4_SECTION 0xE800
+#define HBM4_MC0BIST4_SPECIAL_BASE 0x5205E80ull
+#define HBM4_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST4_SPECIAL_SECTION 0x1800
+#define HBM4_MC0BIST5_BASE 0x5206000ull
+#define HBM4_MC0BIST5_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST5_SECTION 0xE800
+#define HBM4_MC0BIST5_SPECIAL_BASE 0x5206E80ull
+#define HBM4_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST5_SPECIAL_SECTION 0x1800
+#define HBM4_MC0BIST6_BASE 0x5207000ull
+#define HBM4_MC0BIST6_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST6_SECTION 0xE800
+#define HBM4_MC0BIST6_SPECIAL_BASE 0x5207E80ull
+#define HBM4_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST6_SPECIAL_SECTION 0x1800
+#define HBM4_MC0BIST7_BASE 0x5208000ull
+#define HBM4_MC0BIST7_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST7_SECTION 0xE800
+#define HBM4_MC0BIST7_SPECIAL_BASE 0x5208E80ull
+#define HBM4_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST7_SPECIAL_SECTION 0x1800
+#define HBM4_MC0BIST8_MEM_BASE 0x5209000ull
+#define HBM4_MC0BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST8_MEM_SECTION 0xE800
+#define HBM4_MC0BIST8_MEM_SPECIAL_BASE 0x5209E80ull
+#define HBM4_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
+#define HBM4_MC1_BASE 0x5220000ull
+#define HBM4_MC1_MAX_OFFSET 0x1000
+#define HBM4_MC1_SECTION 0xE800
+#define HBM4_MC1_SPECIAL_BASE 0x5220E80ull
+#define HBM4_MC1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1_SPECIAL_SECTION 0x1800
+#define HBM4_MC1BIST0_BASE 0x5221000ull
+#define HBM4_MC1BIST0_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST0_SECTION 0xE800
+#define HBM4_MC1BIST0_SPECIAL_BASE 0x5221E80ull
+#define HBM4_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST0_SPECIAL_SECTION 0x1800
+#define HBM4_MC1BIST1_BASE 0x5222000ull
+#define HBM4_MC1BIST1_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST1_SECTION 0xE800
+#define HBM4_MC1BIST1_SPECIAL_BASE 0x5222E80ull
+#define HBM4_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST1_SPECIAL_SECTION 0x1800
+#define HBM4_MC1BIST2_BASE 0x5223000ull
+#define HBM4_MC1BIST2_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST2_SECTION 0xE800
+#define HBM4_MC1BIST2_SPECIAL_BASE 0x5223E80ull
+#define HBM4_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST2_SPECIAL_SECTION 0x1800
+#define HBM4_MC1BIST3_BASE 0x5224000ull
+#define HBM4_MC1BIST3_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST3_SECTION 0xE800
+#define HBM4_MC1BIST3_SPECIAL_BASE 0x5224E80ull
+#define HBM4_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST3_SPECIAL_SECTION 0x1800
+#define HBM4_MC1BIST4_BASE 0x5225000ull
+#define HBM4_MC1BIST4_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST4_SECTION 0xE800
+#define HBM4_MC1BIST4_SPECIAL_BASE 0x5225E80ull
+#define HBM4_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST4_SPECIAL_SECTION 0x1800
+#define HBM4_MC1BIST5_BASE 0x5226000ull
+#define HBM4_MC1BIST5_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST5_SECTION 0xE800
+#define HBM4_MC1BIST5_SPECIAL_BASE 0x5226E80ull
+#define HBM4_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST5_SPECIAL_SECTION 0x1800
+#define HBM4_MC1BIST6_BASE 0x5227000ull
+#define HBM4_MC1BIST6_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST6_SECTION 0xE800
+#define HBM4_MC1BIST6_SPECIAL_BASE 0x5227E80ull
+#define HBM4_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST6_SPECIAL_SECTION 0x1800
+#define HBM4_MC1BIST7_BASE 0x5228000ull
+#define HBM4_MC1BIST7_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST7_SECTION 0xE800
+#define HBM4_MC1BIST7_SPECIAL_BASE 0x5228E80ull
+#define HBM4_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST7_SPECIAL_SECTION 0x1800
+#define HBM4_MC1BIST8_MEM_BASE 0x5229000ull
+#define HBM4_MC1BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST8_MEM_SECTION 0xE800
+#define HBM4_MC1BIST8_MEM_SPECIAL_BASE 0x5229E80ull
+#define HBM4_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
+#define HBM4_PHY_BASE 0x5240000ull
+#define HBM4_PHY_MAX_OFFSET 0x4000
+#define HBM4_PHY_SECTION 0x40000
+#define HBM5_MC0_BASE 0x5280000ull
+#define HBM5_MC0_MAX_OFFSET 0x1000
+#define HBM5_MC0_SECTION 0xE800
+#define HBM5_MC0_SPECIAL_BASE 0x5280E80ull
+#define HBM5_MC0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0_SPECIAL_SECTION 0x1800
+#define HBM5_MC0BIST0_BASE 0x5281000ull
+#define HBM5_MC0BIST0_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST0_SECTION 0xE800
+#define HBM5_MC0BIST0_SPECIAL_BASE 0x5281E80ull
+#define HBM5_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST0_SPECIAL_SECTION 0x1800
+#define HBM5_MC0BIST1_BASE 0x5282000ull
+#define HBM5_MC0BIST1_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST1_SECTION 0xE800
+#define HBM5_MC0BIST1_SPECIAL_BASE 0x5282E80ull
+#define HBM5_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST1_SPECIAL_SECTION 0x1800
+#define HBM5_MC0BIST2_BASE 0x5283000ull
+#define HBM5_MC0BIST2_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST2_SECTION 0xE800
+#define HBM5_MC0BIST2_SPECIAL_BASE 0x5283E80ull
+#define HBM5_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST2_SPECIAL_SECTION 0x1800
+#define HBM5_MC0BIST3_BASE 0x5284000ull
+#define HBM5_MC0BIST3_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST3_SECTION 0xE800
+#define HBM5_MC0BIST3_SPECIAL_BASE 0x5284E80ull
+#define HBM5_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST3_SPECIAL_SECTION 0x1800
+#define HBM5_MC0BIST4_BASE 0x5285000ull
+#define HBM5_MC0BIST4_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST4_SECTION 0xE800
+#define HBM5_MC0BIST4_SPECIAL_BASE 0x5285E80ull
+#define HBM5_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST4_SPECIAL_SECTION 0x1800
+#define HBM5_MC0BIST5_BASE 0x5286000ull
+#define HBM5_MC0BIST5_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST5_SECTION 0xE800
+#define HBM5_MC0BIST5_SPECIAL_BASE 0x5286E80ull
+#define HBM5_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST5_SPECIAL_SECTION 0x1800
+#define HBM5_MC0BIST6_BASE 0x5287000ull
+#define HBM5_MC0BIST6_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST6_SECTION 0xE800
+#define HBM5_MC0BIST6_SPECIAL_BASE 0x5287E80ull
+#define HBM5_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST6_SPECIAL_SECTION 0x1800
+#define HBM5_MC0BIST7_BASE 0x5288000ull
+#define HBM5_MC0BIST7_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST7_SECTION 0xE800
+#define HBM5_MC0BIST7_SPECIAL_BASE 0x5288E80ull
+#define HBM5_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST7_SPECIAL_SECTION 0x1800
+#define HBM5_MC0BIST8_MEM_BASE 0x5289000ull
+#define HBM5_MC0BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST8_MEM_SECTION 0xE800
+#define HBM5_MC0BIST8_MEM_SPECIAL_BASE 0x5289E80ull
+#define HBM5_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
+#define HBM5_MC1_BASE 0x52A0000ull
+#define HBM5_MC1_MAX_OFFSET 0x1000
+#define HBM5_MC1_SECTION 0xE800
+#define HBM5_MC1_SPECIAL_BASE 0x52A0E80ull
+#define HBM5_MC1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1_SPECIAL_SECTION 0x1800
+#define HBM5_MC1BIST0_BASE 0x52A1000ull
+#define HBM5_MC1BIST0_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST0_SECTION 0xE800
+#define HBM5_MC1BIST0_SPECIAL_BASE 0x52A1E80ull
+#define HBM5_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST0_SPECIAL_SECTION 0x1800
+#define HBM5_MC1BIST1_BASE 0x52A2000ull
+#define HBM5_MC1BIST1_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST1_SECTION 0xE800
+#define HBM5_MC1BIST1_SPECIAL_BASE 0x52A2E80ull
+#define HBM5_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST1_SPECIAL_SECTION 0x1800
+#define HBM5_MC1BIST2_BASE 0x52A3000ull
+#define HBM5_MC1BIST2_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST2_SECTION 0xE800
+#define HBM5_MC1BIST2_SPECIAL_BASE 0x52A3E80ull
+#define HBM5_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST2_SPECIAL_SECTION 0x1800
+#define HBM5_MC1BIST3_BASE 0x52A4000ull
+#define HBM5_MC1BIST3_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST3_SECTION 0xE800
+#define HBM5_MC1BIST3_SPECIAL_BASE 0x52A4E80ull
+#define HBM5_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST3_SPECIAL_SECTION 0x1800
+#define HBM5_MC1BIST4_BASE 0x52A5000ull
+#define HBM5_MC1BIST4_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST4_SECTION 0xE800
+#define HBM5_MC1BIST4_SPECIAL_BASE 0x52A5E80ull
+#define HBM5_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST4_SPECIAL_SECTION 0x1800
+#define HBM5_MC1BIST5_BASE 0x52A6000ull
+#define HBM5_MC1BIST5_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST5_SECTION 0xE800
+#define HBM5_MC1BIST5_SPECIAL_BASE 0x52A6E80ull
+#define HBM5_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST5_SPECIAL_SECTION 0x1800
+#define HBM5_MC1BIST6_BASE 0x52A7000ull
+#define HBM5_MC1BIST6_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST6_SECTION 0xE800
+#define HBM5_MC1BIST6_SPECIAL_BASE 0x52A7E80ull
+#define HBM5_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST6_SPECIAL_SECTION 0x1800
+#define HBM5_MC1BIST7_BASE 0x52A8000ull
+#define HBM5_MC1BIST7_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST7_SECTION 0xE800
+#define HBM5_MC1BIST7_SPECIAL_BASE 0x52A8E80ull
+#define HBM5_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST7_SPECIAL_SECTION 0x1800
+#define HBM5_MC1BIST8_MEM_BASE 0x52A9000ull
+#define HBM5_MC1BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST8_MEM_SECTION 0xE800
+#define HBM5_MC1BIST8_MEM_SPECIAL_BASE 0x52A9E80ull
+#define HBM5_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
+#define HBM5_PHY_BASE 0x52C0000ull
+#define HBM5_PHY_MAX_OFFSET 0x4000
+#define HBM5_PHY_SECTION 0x140000
+#define NIC0_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5400000ull
+#define NIC0_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5400080ull
+#define NIC0_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5400100ull
+#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5400180ull
+#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_0_SPECIAL_BASE 0x5400E80ull
+#define NIC0_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_0_SPECIAL_SECTION 0x1800
+#define NIC0_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5401000ull
+#define NIC0_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5401080ull
+#define NIC0_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5401100ull
+#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5401180ull
+#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_1_SPECIAL_BASE 0x5401E80ull
+#define NIC0_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_1_SPECIAL_SECTION 0x1800
+#define NIC0_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5402000ull
+#define NIC0_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5402080ull
+#define NIC0_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5402100ull
+#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5402180ull
+#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_2_SPECIAL_BASE 0x5402E80ull
+#define NIC0_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_2_SPECIAL_SECTION 0x1800
+#define NIC0_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5403000ull
+#define NIC0_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5403080ull
+#define NIC0_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5403100ull
+#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5403180ull
+#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_3_SPECIAL_BASE 0x5403E80ull
+#define NIC0_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_3_SPECIAL_SECTION 0x1800
+#define NIC0_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5404000ull
+#define NIC0_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5404080ull
+#define NIC0_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5404100ull
+#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5404180ull
+#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_4_SPECIAL_BASE 0x5404E80ull
+#define NIC0_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_4_SPECIAL_SECTION 0x1800
+#define NIC0_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5405000ull
+#define NIC0_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5405080ull
+#define NIC0_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5405100ull
+#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5405180ull
+#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_5_SPECIAL_BASE 0x5405E80ull
+#define NIC0_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_5_SPECIAL_SECTION 0x1800
+#define NIC0_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5406000ull
+#define NIC0_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5406080ull
+#define NIC0_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5406100ull
+#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5406180ull
+#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_6_SPECIAL_BASE 0x5406E80ull
+#define NIC0_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_6_SPECIAL_SECTION 0x1800
+#define NIC0_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5407000ull
+#define NIC0_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5407080ull
+#define NIC0_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5407100ull
+#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5407180ull
+#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_7_SPECIAL_BASE 0x5407E80ull
+#define NIC0_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_7_SPECIAL_SECTION 0x1800
+#define NIC0_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5408000ull
+#define NIC0_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5408080ull
+#define NIC0_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5408100ull
+#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5408180ull
+#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_8_SPECIAL_BASE 0x5408E80ull
+#define NIC0_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_8_SPECIAL_SECTION 0x1800
+#define NIC0_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5409000ull
+#define NIC0_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5409080ull
+#define NIC0_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5409100ull
+#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5409180ull
+#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_9_SPECIAL_BASE 0x5409E80ull
+#define NIC0_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_9_SPECIAL_SECTION 0x1800
+#define NIC0_UMR0_10_UNSECURE_DOORBELL0_BASE 0x540A000ull
+#define NIC0_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_10_UNSECURE_DOORBELL1_BASE 0x540A080ull
+#define NIC0_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x540A100ull
+#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x540A180ull
+#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_10_SPECIAL_BASE 0x540AE80ull
+#define NIC0_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_10_SPECIAL_SECTION 0x1800
+#define NIC0_UMR0_11_UNSECURE_DOORBELL0_BASE 0x540B000ull
+#define NIC0_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_11_UNSECURE_DOORBELL1_BASE 0x540B080ull
+#define NIC0_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x540B100ull
+#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x540B180ull
+#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_11_SPECIAL_BASE 0x540BE80ull
+#define NIC0_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_11_SPECIAL_SECTION 0x1800
+#define NIC0_UMR0_12_UNSECURE_DOORBELL0_BASE 0x540C000ull
+#define NIC0_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_12_UNSECURE_DOORBELL1_BASE 0x540C080ull
+#define NIC0_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x540C100ull
+#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x540C180ull
+#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_12_SPECIAL_BASE 0x540CE80ull
+#define NIC0_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_12_SPECIAL_SECTION 0x1800
+#define NIC0_UMR0_13_UNSECURE_DOORBELL0_BASE 0x540D000ull
+#define NIC0_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_13_UNSECURE_DOORBELL1_BASE 0x540D080ull
+#define NIC0_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x540D100ull
+#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x540D180ull
+#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_13_SPECIAL_BASE 0x540DE80ull
+#define NIC0_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_13_SPECIAL_SECTION 0x1800
+#define NIC0_UMR0_14_UNSECURE_DOORBELL0_BASE 0x540E000ull
+#define NIC0_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR0_14_UNSECURE_DOORBELL1_BASE 0x540E080ull
+#define NIC0_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x540E100ull
+#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x540E180ull
+#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR0_14_SPECIAL_BASE 0x540EE80ull
+#define NIC0_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_14_SPECIAL_SECTION 0x1180
+#define NIC0_QM_DCCM0_BASE 0x5410000ull
+#define NIC0_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC0_QM_DCCM0_SECTION 0x8000
+#define NIC0_QM_ARC_AUX0_BASE 0x5418000ull
+#define NIC0_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC0_QM_ARC_AUX0_SECTION 0xE800
+#define NIC0_QM_ARC_AUX0_SPECIAL_BASE 0x5418E80ull
+#define NIC0_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define NIC0_QM0_BASE 0x541A000ull
+#define NIC0_QM0_MAX_OFFSET 0x1000
+#define NIC0_QM0_SECTION 0x9000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x541A900ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x541A908ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x541A910ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x541A918ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x541A920ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x541A928ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x541A930ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x541A938ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x541A940ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x541A948ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x541A950ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x541A958ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x541A960ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x541A968ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x541A970ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x541A978ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC0_QM0_AXUSER_SECURED_BASE 0x541AB00ull
+#define NIC0_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC0_QM0_AXUSER_SECURED_SECTION 0x8000
+#define NIC0_QM0_AXUSER_NONSECURED_BASE 0x541AB80ull
+#define NIC0_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC0_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC0_QM0_DBG_HBW_BASE 0x541AC00ull
+#define NIC0_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC0_QM0_DBG_HBW_SECTION 0x8000
+#define NIC0_QM0_DBG_LBW_BASE 0x541AC80ull
+#define NIC0_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC0_QM0_DBG_LBW_SECTION 0x1000
+#define NIC0_QM0_CGM_BASE 0x541AD80ull
+#define NIC0_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC0_QM0_CGM_SECTION 0x1000
+#define NIC0_QM0_SPECIAL_BASE 0x541AE80ull
+#define NIC0_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_QM0_SPECIAL_SECTION 0x4180
+#define NIC0_QPC0_BASE 0x541F000ull
+#define NIC0_QPC0_MAX_OFFSET 0x1000
+#define NIC0_QPC0_SECTION 0x7200
+#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x541F720ull
+#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x541F728ull
+#define NIC0_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x541F730ull
+#define NIC0_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x541F738ull
+#define NIC0_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x541F740ull
+#define NIC0_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x541F748ull
+#define NIC0_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x541F750ull
+#define NIC0_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x541F758ull
+#define NIC0_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x541F760ull
+#define NIC0_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x541F768ull
+#define NIC0_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x541F770ull
+#define NIC0_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x541F778ull
+#define NIC0_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x541F780ull
+#define NIC0_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x541F788ull
+#define NIC0_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x541F790ull
+#define NIC0_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x541F798ull
+#define NIC0_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x541F7A0ull
+#define NIC0_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x541F7A8ull
+#define NIC0_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x541F7B0ull
+#define NIC0_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x541F7B8ull
+#define NIC0_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x541F7C0ull
+#define NIC0_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x541F7C8ull
+#define NIC0_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x541F7D0ull
+#define NIC0_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x541F7D8ull
+#define NIC0_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x541F7E0ull
+#define NIC0_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x541F7E8ull
+#define NIC0_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x541F7F0ull
+#define NIC0_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x541F7F8ull
+#define NIC0_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x541F800ull
+#define NIC0_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x541F808ull
+#define NIC0_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x541F810ull
+#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x541F818ull
+#define NIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC0_QPC0_AXUSER_CONG_QUE_BASE 0x541FB80ull
+#define NIC0_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC0_QPC0_AXUSER_RXWQE_BASE 0x541FBE0ull
+#define NIC0_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x541FC40ull
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC0_QPC0_AXUSER_DB_FIFO_BASE 0x541FCA0ull
+#define NIC0_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x541FD00ull
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC0_QPC0_AXUSER_ERR_FIFO_BASE 0x541FD60ull
+#define NIC0_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC0_QPC0_AXUSER_QPC_RESP_BASE 0x541FDC0ull
+#define NIC0_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC0_QPC0_AXUSER_QPC_REQ_BASE 0x541FE20ull
+#define NIC0_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC0_QPC0_SPECIAL_BASE 0x541FE80ull
+#define NIC0_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_QPC0_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5420000ull
+#define NIC0_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5420080ull
+#define NIC0_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5420100ull
+#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5420180ull
+#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_0_SPECIAL_BASE 0x5420E80ull
+#define NIC0_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_0_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5421000ull
+#define NIC0_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5421080ull
+#define NIC0_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5421100ull
+#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5421180ull
+#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_1_SPECIAL_BASE 0x5421E80ull
+#define NIC0_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_1_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5422000ull
+#define NIC0_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5422080ull
+#define NIC0_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5422100ull
+#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5422180ull
+#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_2_SPECIAL_BASE 0x5422E80ull
+#define NIC0_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_2_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5423000ull
+#define NIC0_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5423080ull
+#define NIC0_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5423100ull
+#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5423180ull
+#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_3_SPECIAL_BASE 0x5423E80ull
+#define NIC0_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_3_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5424000ull
+#define NIC0_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5424080ull
+#define NIC0_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5424100ull
+#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5424180ull
+#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_4_SPECIAL_BASE 0x5424E80ull
+#define NIC0_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_4_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5425000ull
+#define NIC0_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5425080ull
+#define NIC0_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5425100ull
+#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5425180ull
+#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_5_SPECIAL_BASE 0x5425E80ull
+#define NIC0_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_5_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5426000ull
+#define NIC0_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5426080ull
+#define NIC0_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5426100ull
+#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5426180ull
+#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_6_SPECIAL_BASE 0x5426E80ull
+#define NIC0_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_6_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5427000ull
+#define NIC0_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5427080ull
+#define NIC0_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5427100ull
+#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5427180ull
+#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_7_SPECIAL_BASE 0x5427E80ull
+#define NIC0_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_7_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5428000ull
+#define NIC0_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5428080ull
+#define NIC0_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5428100ull
+#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5428180ull
+#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_8_SPECIAL_BASE 0x5428E80ull
+#define NIC0_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_8_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5429000ull
+#define NIC0_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5429080ull
+#define NIC0_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5429100ull
+#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5429180ull
+#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_9_SPECIAL_BASE 0x5429E80ull
+#define NIC0_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_9_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_10_UNSECURE_DOORBELL0_BASE 0x542A000ull
+#define NIC0_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_10_UNSECURE_DOORBELL1_BASE 0x542A080ull
+#define NIC0_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x542A100ull
+#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x542A180ull
+#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_10_SPECIAL_BASE 0x542AE80ull
+#define NIC0_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_10_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_11_UNSECURE_DOORBELL0_BASE 0x542B000ull
+#define NIC0_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_11_UNSECURE_DOORBELL1_BASE 0x542B080ull
+#define NIC0_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x542B100ull
+#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x542B180ull
+#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_11_SPECIAL_BASE 0x542BE80ull
+#define NIC0_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_11_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_12_UNSECURE_DOORBELL0_BASE 0x542C000ull
+#define NIC0_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_12_UNSECURE_DOORBELL1_BASE 0x542C080ull
+#define NIC0_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x542C100ull
+#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x542C180ull
+#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_12_SPECIAL_BASE 0x542CE80ull
+#define NIC0_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_12_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_13_UNSECURE_DOORBELL0_BASE 0x542D000ull
+#define NIC0_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_13_UNSECURE_DOORBELL1_BASE 0x542D080ull
+#define NIC0_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x542D100ull
+#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x542D180ull
+#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_13_SPECIAL_BASE 0x542DE80ull
+#define NIC0_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_13_SPECIAL_SECTION 0x1800
+#define NIC0_UMR1_14_UNSECURE_DOORBELL0_BASE 0x542E000ull
+#define NIC0_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC0_UMR1_14_UNSECURE_DOORBELL1_BASE 0x542E080ull
+#define NIC0_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x542E100ull
+#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x542E180ull
+#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC0_UMR1_14_SPECIAL_BASE 0x542EE80ull
+#define NIC0_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_14_SPECIAL_SECTION 0x1180
+#define NIC0_QM_DCCM1_BASE 0x5430000ull
+#define NIC0_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC0_QM_DCCM1_SECTION 0x8000
+#define NIC0_QM_ARC_AUX1_BASE 0x5438000ull
+#define NIC0_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC0_QM_ARC_AUX1_SECTION 0xE800
+#define NIC0_QM_ARC_AUX1_SPECIAL_BASE 0x5438E80ull
+#define NIC0_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define NIC0_QM1_BASE 0x543A000ull
+#define NIC0_QM1_MAX_OFFSET 0x1000
+#define NIC0_QM1_SECTION 0x9000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x543A900ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x543A908ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x543A910ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x543A918ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x543A920ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x543A928ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x543A930ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x543A938ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x543A940ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x543A948ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x543A950ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x543A958ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x543A960ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x543A968ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x543A970ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x543A978ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC0_QM1_AXUSER_SECURED_BASE 0x543AB00ull
+#define NIC0_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC0_QM1_AXUSER_SECURED_SECTION 0x8000
+#define NIC0_QM1_AXUSER_NONSECURED_BASE 0x543AB80ull
+#define NIC0_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC0_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC0_QM1_DBG_HBW_BASE 0x543AC00ull
+#define NIC0_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC0_QM1_DBG_HBW_SECTION 0x8000
+#define NIC0_QM1_DBG_LBW_BASE 0x543AC80ull
+#define NIC0_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC0_QM1_DBG_LBW_SECTION 0x1000
+#define NIC0_QM1_CGM_BASE 0x543AD80ull
+#define NIC0_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC0_QM1_CGM_SECTION 0x1000
+#define NIC0_QM1_SPECIAL_BASE 0x543AE80ull
+#define NIC0_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_QM1_SPECIAL_SECTION 0x4180
+#define NIC0_QPC1_BASE 0x543F000ull
+#define NIC0_QPC1_MAX_OFFSET 0x1000
+#define NIC0_QPC1_SECTION 0x7200
+#define NIC0_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x543F720ull
+#define NIC0_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x543F728ull
+#define NIC0_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x543F730ull
+#define NIC0_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x543F738ull
+#define NIC0_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x543F740ull
+#define NIC0_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x543F748ull
+#define NIC0_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x543F750ull
+#define NIC0_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x543F758ull
+#define NIC0_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x543F760ull
+#define NIC0_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x543F768ull
+#define NIC0_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x543F770ull
+#define NIC0_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x543F778ull
+#define NIC0_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x543F780ull
+#define NIC0_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x543F788ull
+#define NIC0_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x543F790ull
+#define NIC0_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x543F798ull
+#define NIC0_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x543F7A0ull
+#define NIC0_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x543F7A8ull
+#define NIC0_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x543F7B0ull
+#define NIC0_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x543F7B8ull
+#define NIC0_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x543F7C0ull
+#define NIC0_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x543F7C8ull
+#define NIC0_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x543F7D0ull
+#define NIC0_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x543F7D8ull
+#define NIC0_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x543F7E0ull
+#define NIC0_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x543F7E8ull
+#define NIC0_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x543F7F0ull
+#define NIC0_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x543F7F8ull
+#define NIC0_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x543F800ull
+#define NIC0_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x543F808ull
+#define NIC0_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x543F810ull
+#define NIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x543F818ull
+#define NIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC0_QPC1_AXUSER_CONG_QUE_BASE 0x543FB80ull
+#define NIC0_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC0_QPC1_AXUSER_RXWQE_BASE 0x543FBE0ull
+#define NIC0_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define NIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x543FC40ull
+#define NIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC0_QPC1_AXUSER_DB_FIFO_BASE 0x543FCA0ull
+#define NIC0_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x543FD00ull
+#define NIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC0_QPC1_AXUSER_ERR_FIFO_BASE 0x543FD60ull
+#define NIC0_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC0_QPC1_AXUSER_QPC_RESP_BASE 0x543FDC0ull
+#define NIC0_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC0_QPC1_AXUSER_QPC_REQ_BASE 0x543FE20ull
+#define NIC0_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC0_QPC1_SPECIAL_BASE 0x543FE80ull
+#define NIC0_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_QPC1_SPECIAL_SECTION 0x8180
+#define NIC0_TMR_BASE 0x5448000ull
+#define NIC0_TMR_MAX_OFFSET 0x1000
+#define NIC0_TMR_SECTION 0xD600
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5448D60ull
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define NIC0_TMR_AXUSER_TMR_FIFO_BASE 0x5448DC0ull
+#define NIC0_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC0_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define NIC0_TMR_AXUSER_TMR_FSM_BASE 0x5448E20ull
+#define NIC0_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC0_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define NIC0_TMR_SPECIAL_BASE 0x5448E80ull
+#define NIC0_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_TMR_SPECIAL_SECTION 0x1800
+#define NIC0_RXB_CORE_BASE 0x5449000ull
+#define NIC0_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC0_RXB_CORE_SECTION 0x6100
+#define NIC0_RXB_CORE_SCT_AWUSER_BASE 0x5449610ull
+#define NIC0_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC0_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define NIC0_RXB_CORE_SPECIAL_BASE 0x5449E80ull
+#define NIC0_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_RXB_CORE_SPECIAL_SECTION 0x1800
+#define NIC0_RXE0_BASE 0x544A000ull
+#define NIC0_RXE0_MAX_OFFSET 0x1000
+#define NIC0_RXE0_SECTION 0x9000
+#define NIC0_RXE0_WQE_ARUSER_BASE 0x544A900ull
+#define NIC0_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC0_RXE0_WQE_ARUSER_SECTION 0x5800
+#define NIC0_RXE0_SPECIAL_BASE 0x544AE80ull
+#define NIC0_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_RXE0_SPECIAL_SECTION 0x1800
+#define NIC0_RXE1_BASE 0x544B000ull
+#define NIC0_RXE1_MAX_OFFSET 0x1000
+#define NIC0_RXE1_SECTION 0x9000
+#define NIC0_RXE1_WQE_ARUSER_BASE 0x544B900ull
+#define NIC0_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC0_RXE1_WQE_ARUSER_SECTION 0x5800
+#define NIC0_RXE1_SPECIAL_BASE 0x544BE80ull
+#define NIC0_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_RXE1_SPECIAL_SECTION 0x1800
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_BASE 0x544C000ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_BASE 0x544C050ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ2_BASE 0x544C0A0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ3_BASE 0x544C0F0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ4_BASE 0x544C140ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ5_BASE 0x544C190ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ6_BASE 0x544C1E0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ7_BASE 0x544C230ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ8_BASE 0x544C280ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ9_BASE 0x544C2D0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ10_BASE 0x544C320ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ11_BASE 0x544C370ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ12_BASE 0x544C3C0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ13_BASE 0x544C410ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ14_BASE 0x544C460ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ15_BASE 0x544C4B0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ16_BASE 0x544C500ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ17_BASE 0x544C550ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ18_BASE 0x544C5A0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ19_BASE 0x544C5F0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ20_BASE 0x544C640ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ21_BASE 0x544C690ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ22_BASE 0x544C6E0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ23_BASE 0x544C730ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ24_BASE 0x544C780ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ25_BASE 0x544C7D0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ26_BASE 0x544C820ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ27_BASE 0x544C870ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ28_BASE 0x544C8C0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ29_BASE 0x544C910ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ30_BASE 0x544C960ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ31_BASE 0x544C9B0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC0_RXE0_AXUSER_SPECIAL_BASE 0x544CE80ull
+#define NIC0_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define NIC0_RXE1_AXUSER_AXUSER_CQ0_BASE 0x544D000ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ1_BASE 0x544D050ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ2_BASE 0x544D0A0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ3_BASE 0x544D0F0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ4_BASE 0x544D140ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ5_BASE 0x544D190ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ6_BASE 0x544D1E0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ7_BASE 0x544D230ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ8_BASE 0x544D280ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ9_BASE 0x544D2D0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ10_BASE 0x544D320ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ11_BASE 0x544D370ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ12_BASE 0x544D3C0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ13_BASE 0x544D410ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ14_BASE 0x544D460ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ15_BASE 0x544D4B0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ16_BASE 0x544D500ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ17_BASE 0x544D550ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ18_BASE 0x544D5A0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ19_BASE 0x544D5F0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ20_BASE 0x544D640ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ21_BASE 0x544D690ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ22_BASE 0x544D6E0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ23_BASE 0x544D730ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ24_BASE 0x544D780ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ25_BASE 0x544D7D0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ26_BASE 0x544D820ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ27_BASE 0x544D870ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ28_BASE 0x544D8C0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ29_BASE 0x544D910ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ30_BASE 0x544D960ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ31_BASE 0x544D9B0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC0_RXE1_AXUSER_SPECIAL_BASE 0x544DE80ull
+#define NIC0_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define NIC0_TXS0_BASE 0x5450000ull
+#define NIC0_TXS0_MAX_OFFSET 0x1000
+#define NIC0_TXS0_SECTION 0xE800
+#define NIC0_TXS0_SPECIAL_BASE 0x5450E80ull
+#define NIC0_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_TXS0_SPECIAL_SECTION 0x1800
+#define NIC0_TXS1_BASE 0x5451000ull
+#define NIC0_TXS1_MAX_OFFSET 0x1000
+#define NIC0_TXS1_SECTION 0xE800
+#define NIC0_TXS1_SPECIAL_BASE 0x5451E80ull
+#define NIC0_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_TXS1_SPECIAL_SECTION 0x1800
+#define NIC0_TXE0_BASE 0x5452000ull
+#define NIC0_TXE0_MAX_OFFSET 0x1000
+#define NIC0_TXE0_SECTION 0xE800
+#define NIC0_TXE0_SPECIAL_BASE 0x5452E80ull
+#define NIC0_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_TXE0_SPECIAL_SECTION 0x1800
+#define NIC0_TXE1_BASE 0x5453000ull
+#define NIC0_TXE1_MAX_OFFSET 0x1000
+#define NIC0_TXE1_SECTION 0xE800
+#define NIC0_TXE1_SPECIAL_BASE 0x5453E80ull
+#define NIC0_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_TXE1_SPECIAL_SECTION 0x1800
+#define NIC0_TXB_BASE 0x5454000ull
+#define NIC0_TXB_MAX_OFFSET 0x1000
+#define NIC0_TXB_SECTION 0xE800
+#define NIC0_TXB_SPECIAL_BASE 0x5454E80ull
+#define NIC0_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_TXB_SPECIAL_SECTION 0x1800
+#define NIC0_MSTR_IF_RR_SHRD_HBW_BASE 0x5455000ull
+#define NIC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define NIC0_MSTR_IF_RR_PRVT_HBW_BASE 0x5455200ull
+#define NIC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define NIC0_MSTR_IF_RR_SHRD_LBW_BASE 0x5455400ull
+#define NIC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define NIC0_MSTR_IF_RR_PRVT_LBW_BASE 0x5455600ull
+#define NIC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define NIC0_MSTR_IF_E2E_CRDT_BASE 0x5455800ull
+#define NIC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define NIC0_MSTR_IF_AXUSER_BASE 0x5455A80ull
+#define NIC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define NIC0_MSTR_IF_DBG_HBW_BASE 0x5455B00ull
+#define NIC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define NIC0_MSTR_IF_DBG_LBW_BASE 0x5455B80ull
+#define NIC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define NIC0_MSTR_IF_CORE_HBW_BASE 0x5455C00ull
+#define NIC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define NIC0_MSTR_IF_CORE_LBW_BASE 0x5455D80ull
+#define NIC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define NIC0_MSTR_IF_SPECIAL_BASE 0x5455E80ull
+#define NIC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define NIC0_TX_AXUSER_BASE 0x5456000ull
+#define NIC0_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC0_TX_AXUSER_SECTION 0x2000
+#define NIC0_SERDES0_BASE 0x5458000ull
+#define NIC0_SERDES0_MAX_OFFSET 0x3E40
+#define NIC0_SERDES0_SECTION 0x4000
+#define NIC0_SERDES1_BASE 0x545C000ull
+#define NIC0_SERDES1_MAX_OFFSET 0x3E40
+#define NIC0_SERDES1_SECTION 0x4000
+#define NIC0_PHY_BASE 0x5460000ull
+#define NIC0_PHY_MAX_OFFSET 0x1000
+#define NIC0_PHY_SECTION 0xE800
+#define NIC0_PHY_SPECIAL_BASE 0x5460E80ull
+#define NIC0_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_PHY_SPECIAL_SECTION 0x7180
+#define PRT0_MAC_AUX_BASE 0x5468000ull
+#define PRT0_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT0_MAC_AUX_SECTION 0xE800
+#define PRT0_MAC_AUX_SPECIAL_BASE 0x5468E80ull
+#define PRT0_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT0_MAC_AUX_SPECIAL_SECTION 0x1800
+#define PRT0_MAC_CORE_BASE 0x5469000ull
+#define PRT0_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT0_MAC_CORE_SECTION 0xE800
+#define PRT0_MAC_CORE_SPECIAL_BASE 0x5469E80ull
+#define PRT0_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT0_MAC_CORE_SPECIAL_SECTION 0x1800
+#define NIC0_MAC_RS_FEC_BASE 0x546A000ull
+#define NIC0_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC0_MAC_RS_FEC_SECTION 0x1000
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_BASE 0x546B000ull
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define NIC0_MAC_GLOB_STAT_RX0_BASE 0x546B100ull
+#define NIC0_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC0_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define NIC0_MAC_GLOB_STAT_RX1_BASE 0x546B18Cull
+#define NIC0_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC0_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define NIC0_MAC_GLOB_STAT_RX2_BASE 0x546B218ull
+#define NIC0_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC0_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define NIC0_MAC_GLOB_STAT_RX3_BASE 0x546B2A4ull
+#define NIC0_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC0_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define NIC0_MAC_GLOB_STAT_TX0_BASE 0x546B330ull
+#define NIC0_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC0_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define NIC0_MAC_GLOB_STAT_TX1_BASE 0x546B398ull
+#define NIC0_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC0_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define NIC0_MAC_GLOB_STAT_TX2_BASE 0x546B400ull
+#define NIC0_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC0_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define NIC0_MAC_GLOB_STAT_TX3_BASE 0x546B468ull
+#define NIC0_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC0_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define NIC0_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x546B800ull
+#define NIC0_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC0_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define NIC0_MAC_CH0_MAC_PCS_BASE 0x546C000ull
+#define NIC0_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC0_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define NIC0_MAC_CH0_MAC_128_BASE 0x546C400ull
+#define NIC0_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC0_MAC_CH0_MAC_128_SECTION 0x4000
+#define NIC0_MAC_CH0_MAC_AN_BASE 0x546C800ull
+#define NIC0_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC0_MAC_CH0_MAC_AN_SECTION 0x8000
+#define NIC0_MAC_CH1_MAC_PCS_BASE 0x546D000ull
+#define NIC0_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC0_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define NIC0_MAC_CH1_MAC_128_BASE 0x546D400ull
+#define NIC0_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC0_MAC_CH1_MAC_128_SECTION 0x4000
+#define NIC0_MAC_CH1_MAC_AN_BASE 0x546D800ull
+#define NIC0_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC0_MAC_CH1_MAC_AN_SECTION 0x8000
+#define NIC0_MAC_CH2_MAC_PCS_BASE 0x546E000ull
+#define NIC0_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC0_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define NIC0_MAC_CH2_MAC_128_BASE 0x546E400ull
+#define NIC0_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC0_MAC_CH2_MAC_128_SECTION 0x4000
+#define NIC0_MAC_CH2_MAC_AN_BASE 0x546E800ull
+#define NIC0_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC0_MAC_CH2_MAC_AN_SECTION 0x8000
+#define NIC0_MAC_CH3_MAC_PCS_BASE 0x546F000ull
+#define NIC0_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC0_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define NIC0_MAC_CH3_MAC_128_BASE 0x546F400ull
+#define NIC0_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC0_MAC_CH3_MAC_128_SECTION 0x4000
+#define NIC0_MAC_CH3_MAC_AN_BASE 0x546F800ull
+#define NIC0_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC0_MAC_CH3_MAC_AN_SECTION 0x10800
+#define NIC1_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5480000ull
+#define NIC1_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5480080ull
+#define NIC1_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5480100ull
+#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5480180ull
+#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_0_SPECIAL_BASE 0x5480E80ull
+#define NIC1_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_0_SPECIAL_SECTION 0x1800
+#define NIC1_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5481000ull
+#define NIC1_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5481080ull
+#define NIC1_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5481100ull
+#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5481180ull
+#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_1_SPECIAL_BASE 0x5481E80ull
+#define NIC1_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_1_SPECIAL_SECTION 0x1800
+#define NIC1_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5482000ull
+#define NIC1_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5482080ull
+#define NIC1_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5482100ull
+#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5482180ull
+#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_2_SPECIAL_BASE 0x5482E80ull
+#define NIC1_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_2_SPECIAL_SECTION 0x1800
+#define NIC1_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5483000ull
+#define NIC1_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5483080ull
+#define NIC1_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5483100ull
+#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5483180ull
+#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_3_SPECIAL_BASE 0x5483E80ull
+#define NIC1_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_3_SPECIAL_SECTION 0x1800
+#define NIC1_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5484000ull
+#define NIC1_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5484080ull
+#define NIC1_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5484100ull
+#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5484180ull
+#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_4_SPECIAL_BASE 0x5484E80ull
+#define NIC1_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_4_SPECIAL_SECTION 0x1800
+#define NIC1_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5485000ull
+#define NIC1_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5485080ull
+#define NIC1_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5485100ull
+#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5485180ull
+#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_5_SPECIAL_BASE 0x5485E80ull
+#define NIC1_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_5_SPECIAL_SECTION 0x1800
+#define NIC1_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5486000ull
+#define NIC1_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5486080ull
+#define NIC1_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5486100ull
+#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5486180ull
+#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_6_SPECIAL_BASE 0x5486E80ull
+#define NIC1_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_6_SPECIAL_SECTION 0x1800
+#define NIC1_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5487000ull
+#define NIC1_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5487080ull
+#define NIC1_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5487100ull
+#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5487180ull
+#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_7_SPECIAL_BASE 0x5487E80ull
+#define NIC1_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_7_SPECIAL_SECTION 0x1800
+#define NIC1_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5488000ull
+#define NIC1_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5488080ull
+#define NIC1_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5488100ull
+#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5488180ull
+#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_8_SPECIAL_BASE 0x5488E80ull
+#define NIC1_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_8_SPECIAL_SECTION 0x1800
+#define NIC1_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5489000ull
+#define NIC1_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5489080ull
+#define NIC1_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5489100ull
+#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5489180ull
+#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_9_SPECIAL_BASE 0x5489E80ull
+#define NIC1_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_9_SPECIAL_SECTION 0x1800
+#define NIC1_UMR0_10_UNSECURE_DOORBELL0_BASE 0x548A000ull
+#define NIC1_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_10_UNSECURE_DOORBELL1_BASE 0x548A080ull
+#define NIC1_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x548A100ull
+#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x548A180ull
+#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_10_SPECIAL_BASE 0x548AE80ull
+#define NIC1_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_10_SPECIAL_SECTION 0x1800
+#define NIC1_UMR0_11_UNSECURE_DOORBELL0_BASE 0x548B000ull
+#define NIC1_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_11_UNSECURE_DOORBELL1_BASE 0x548B080ull
+#define NIC1_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x548B100ull
+#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x548B180ull
+#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_11_SPECIAL_BASE 0x548BE80ull
+#define NIC1_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_11_SPECIAL_SECTION 0x1800
+#define NIC1_UMR0_12_UNSECURE_DOORBELL0_BASE 0x548C000ull
+#define NIC1_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_12_UNSECURE_DOORBELL1_BASE 0x548C080ull
+#define NIC1_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x548C100ull
+#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x548C180ull
+#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_12_SPECIAL_BASE 0x548CE80ull
+#define NIC1_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_12_SPECIAL_SECTION 0x1800
+#define NIC1_UMR0_13_UNSECURE_DOORBELL0_BASE 0x548D000ull
+#define NIC1_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_13_UNSECURE_DOORBELL1_BASE 0x548D080ull
+#define NIC1_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x548D100ull
+#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x548D180ull
+#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_13_SPECIAL_BASE 0x548DE80ull
+#define NIC1_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_13_SPECIAL_SECTION 0x1800
+#define NIC1_UMR0_14_UNSECURE_DOORBELL0_BASE 0x548E000ull
+#define NIC1_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR0_14_UNSECURE_DOORBELL1_BASE 0x548E080ull
+#define NIC1_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x548E100ull
+#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x548E180ull
+#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR0_14_SPECIAL_BASE 0x548EE80ull
+#define NIC1_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_14_SPECIAL_SECTION 0x1180
+#define NIC1_QM_DCCM0_BASE 0x5490000ull
+#define NIC1_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC1_QM_DCCM0_SECTION 0x8000
+#define NIC1_QM_ARC_AUX0_BASE 0x5498000ull
+#define NIC1_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC1_QM_ARC_AUX0_SECTION 0xE800
+#define NIC1_QM_ARC_AUX0_SPECIAL_BASE 0x5498E80ull
+#define NIC1_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define NIC1_QM0_BASE 0x549A000ull
+#define NIC1_QM0_MAX_OFFSET 0x1000
+#define NIC1_QM0_SECTION 0x9000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x549A900ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x549A908ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x549A910ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x549A918ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x549A920ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x549A928ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x549A930ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x549A938ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x549A940ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x549A948ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x549A950ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x549A958ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x549A960ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x549A968ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x549A970ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x549A978ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC1_QM0_AXUSER_SECURED_BASE 0x549AB00ull
+#define NIC1_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC1_QM0_AXUSER_SECURED_SECTION 0x8000
+#define NIC1_QM0_AXUSER_NONSECURED_BASE 0x549AB80ull
+#define NIC1_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC1_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC1_QM0_DBG_HBW_BASE 0x549AC00ull
+#define NIC1_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC1_QM0_DBG_HBW_SECTION 0x8000
+#define NIC1_QM0_DBG_LBW_BASE 0x549AC80ull
+#define NIC1_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC1_QM0_DBG_LBW_SECTION 0x1000
+#define NIC1_QM0_CGM_BASE 0x549AD80ull
+#define NIC1_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC1_QM0_CGM_SECTION 0x1000
+#define NIC1_QM0_SPECIAL_BASE 0x549AE80ull
+#define NIC1_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_QM0_SPECIAL_SECTION 0x4180
+#define NIC1_QPC0_BASE 0x549F000ull
+#define NIC1_QPC0_MAX_OFFSET 0x1000
+#define NIC1_QPC0_SECTION 0x7200
+#define NIC1_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x549F720ull
+#define NIC1_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x549F728ull
+#define NIC1_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x549F730ull
+#define NIC1_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x549F738ull
+#define NIC1_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x549F740ull
+#define NIC1_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x549F748ull
+#define NIC1_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x549F750ull
+#define NIC1_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x549F758ull
+#define NIC1_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x549F760ull
+#define NIC1_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x549F768ull
+#define NIC1_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x549F770ull
+#define NIC1_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x549F778ull
+#define NIC1_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x549F780ull
+#define NIC1_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x549F788ull
+#define NIC1_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x549F790ull
+#define NIC1_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x549F798ull
+#define NIC1_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x549F7A0ull
+#define NIC1_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x549F7A8ull
+#define NIC1_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x549F7B0ull
+#define NIC1_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x549F7B8ull
+#define NIC1_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x549F7C0ull
+#define NIC1_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x549F7C8ull
+#define NIC1_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x549F7D0ull
+#define NIC1_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x549F7D8ull
+#define NIC1_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x549F7E0ull
+#define NIC1_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x549F7E8ull
+#define NIC1_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x549F7F0ull
+#define NIC1_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x549F7F8ull
+#define NIC1_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x549F800ull
+#define NIC1_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x549F808ull
+#define NIC1_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x549F810ull
+#define NIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x549F818ull
+#define NIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC1_QPC0_AXUSER_CONG_QUE_BASE 0x549FB80ull
+#define NIC1_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC1_QPC0_AXUSER_RXWQE_BASE 0x549FBE0ull
+#define NIC1_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define NIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x549FC40ull
+#define NIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC1_QPC0_AXUSER_DB_FIFO_BASE 0x549FCA0ull
+#define NIC1_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x549FD00ull
+#define NIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC1_QPC0_AXUSER_ERR_FIFO_BASE 0x549FD60ull
+#define NIC1_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC1_QPC0_AXUSER_QPC_RESP_BASE 0x549FDC0ull
+#define NIC1_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC1_QPC0_AXUSER_QPC_REQ_BASE 0x549FE20ull
+#define NIC1_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC1_QPC0_SPECIAL_BASE 0x549FE80ull
+#define NIC1_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_QPC0_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_0_UNSECURE_DOORBELL0_BASE 0x54A0000ull
+#define NIC1_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_0_UNSECURE_DOORBELL1_BASE 0x54A0080ull
+#define NIC1_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x54A0100ull
+#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x54A0180ull
+#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_0_SPECIAL_BASE 0x54A0E80ull
+#define NIC1_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_0_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_1_UNSECURE_DOORBELL0_BASE 0x54A1000ull
+#define NIC1_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_1_UNSECURE_DOORBELL1_BASE 0x54A1080ull
+#define NIC1_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x54A1100ull
+#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x54A1180ull
+#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_1_SPECIAL_BASE 0x54A1E80ull
+#define NIC1_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_1_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_2_UNSECURE_DOORBELL0_BASE 0x54A2000ull
+#define NIC1_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_2_UNSECURE_DOORBELL1_BASE 0x54A2080ull
+#define NIC1_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x54A2100ull
+#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x54A2180ull
+#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_2_SPECIAL_BASE 0x54A2E80ull
+#define NIC1_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_2_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_3_UNSECURE_DOORBELL0_BASE 0x54A3000ull
+#define NIC1_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_3_UNSECURE_DOORBELL1_BASE 0x54A3080ull
+#define NIC1_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x54A3100ull
+#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x54A3180ull
+#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_3_SPECIAL_BASE 0x54A3E80ull
+#define NIC1_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_3_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_4_UNSECURE_DOORBELL0_BASE 0x54A4000ull
+#define NIC1_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_4_UNSECURE_DOORBELL1_BASE 0x54A4080ull
+#define NIC1_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x54A4100ull
+#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x54A4180ull
+#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_4_SPECIAL_BASE 0x54A4E80ull
+#define NIC1_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_4_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_5_UNSECURE_DOORBELL0_BASE 0x54A5000ull
+#define NIC1_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_5_UNSECURE_DOORBELL1_BASE 0x54A5080ull
+#define NIC1_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x54A5100ull
+#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x54A5180ull
+#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_5_SPECIAL_BASE 0x54A5E80ull
+#define NIC1_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_5_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_6_UNSECURE_DOORBELL0_BASE 0x54A6000ull
+#define NIC1_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_6_UNSECURE_DOORBELL1_BASE 0x54A6080ull
+#define NIC1_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x54A6100ull
+#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x54A6180ull
+#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_6_SPECIAL_BASE 0x54A6E80ull
+#define NIC1_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_6_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_7_UNSECURE_DOORBELL0_BASE 0x54A7000ull
+#define NIC1_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_7_UNSECURE_DOORBELL1_BASE 0x54A7080ull
+#define NIC1_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x54A7100ull
+#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x54A7180ull
+#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_7_SPECIAL_BASE 0x54A7E80ull
+#define NIC1_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_7_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_8_UNSECURE_DOORBELL0_BASE 0x54A8000ull
+#define NIC1_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_8_UNSECURE_DOORBELL1_BASE 0x54A8080ull
+#define NIC1_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x54A8100ull
+#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x54A8180ull
+#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_8_SPECIAL_BASE 0x54A8E80ull
+#define NIC1_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_8_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_9_UNSECURE_DOORBELL0_BASE 0x54A9000ull
+#define NIC1_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_9_UNSECURE_DOORBELL1_BASE 0x54A9080ull
+#define NIC1_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x54A9100ull
+#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x54A9180ull
+#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_9_SPECIAL_BASE 0x54A9E80ull
+#define NIC1_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_9_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_10_UNSECURE_DOORBELL0_BASE 0x54AA000ull
+#define NIC1_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_10_UNSECURE_DOORBELL1_BASE 0x54AA080ull
+#define NIC1_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x54AA100ull
+#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x54AA180ull
+#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_10_SPECIAL_BASE 0x54AAE80ull
+#define NIC1_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_10_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_11_UNSECURE_DOORBELL0_BASE 0x54AB000ull
+#define NIC1_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_11_UNSECURE_DOORBELL1_BASE 0x54AB080ull
+#define NIC1_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x54AB100ull
+#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x54AB180ull
+#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_11_SPECIAL_BASE 0x54ABE80ull
+#define NIC1_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_11_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_12_UNSECURE_DOORBELL0_BASE 0x54AC000ull
+#define NIC1_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_12_UNSECURE_DOORBELL1_BASE 0x54AC080ull
+#define NIC1_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x54AC100ull
+#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x54AC180ull
+#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_12_SPECIAL_BASE 0x54ACE80ull
+#define NIC1_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_12_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_13_UNSECURE_DOORBELL0_BASE 0x54AD000ull
+#define NIC1_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_13_UNSECURE_DOORBELL1_BASE 0x54AD080ull
+#define NIC1_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x54AD100ull
+#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x54AD180ull
+#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_13_SPECIAL_BASE 0x54ADE80ull
+#define NIC1_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_13_SPECIAL_SECTION 0x1800
+#define NIC1_UMR1_14_UNSECURE_DOORBELL0_BASE 0x54AE000ull
+#define NIC1_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC1_UMR1_14_UNSECURE_DOORBELL1_BASE 0x54AE080ull
+#define NIC1_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x54AE100ull
+#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x54AE180ull
+#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC1_UMR1_14_SPECIAL_BASE 0x54AEE80ull
+#define NIC1_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_14_SPECIAL_SECTION 0x1180
+#define NIC1_QM_DCCM1_BASE 0x54B0000ull
+#define NIC1_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC1_QM_DCCM1_SECTION 0x8000
+#define NIC1_QM_ARC_AUX1_BASE 0x54B8000ull
+#define NIC1_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC1_QM_ARC_AUX1_SECTION 0xE800
+#define NIC1_QM_ARC_AUX1_SPECIAL_BASE 0x54B8E80ull
+#define NIC1_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define NIC1_QM1_BASE 0x54BA000ull
+#define NIC1_QM1_MAX_OFFSET 0x1000
+#define NIC1_QM1_SECTION 0x9000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x54BA900ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x54BA908ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x54BA910ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x54BA918ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x54BA920ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x54BA928ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x54BA930ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x54BA938ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x54BA940ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x54BA948ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x54BA950ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x54BA958ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x54BA960ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x54BA968ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x54BA970ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x54BA978ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC1_QM1_AXUSER_SECURED_BASE 0x54BAB00ull
+#define NIC1_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC1_QM1_AXUSER_SECURED_SECTION 0x8000
+#define NIC1_QM1_AXUSER_NONSECURED_BASE 0x54BAB80ull
+#define NIC1_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC1_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC1_QM1_DBG_HBW_BASE 0x54BAC00ull
+#define NIC1_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC1_QM1_DBG_HBW_SECTION 0x8000
+#define NIC1_QM1_DBG_LBW_BASE 0x54BAC80ull
+#define NIC1_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC1_QM1_DBG_LBW_SECTION 0x1000
+#define NIC1_QM1_CGM_BASE 0x54BAD80ull
+#define NIC1_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC1_QM1_CGM_SECTION 0x1000
+#define NIC1_QM1_SPECIAL_BASE 0x54BAE80ull
+#define NIC1_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_QM1_SPECIAL_SECTION 0x4180
+#define NIC1_QPC1_BASE 0x54BF000ull
+#define NIC1_QPC1_MAX_OFFSET 0x1000
+#define NIC1_QPC1_SECTION 0x7200
+#define NIC1_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x54BF720ull
+#define NIC1_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x54BF728ull
+#define NIC1_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x54BF730ull
+#define NIC1_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x54BF738ull
+#define NIC1_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x54BF740ull
+#define NIC1_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x54BF748ull
+#define NIC1_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x54BF750ull
+#define NIC1_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x54BF758ull
+#define NIC1_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x54BF760ull
+#define NIC1_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x54BF768ull
+#define NIC1_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x54BF770ull
+#define NIC1_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x54BF778ull
+#define NIC1_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x54BF780ull
+#define NIC1_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x54BF788ull
+#define NIC1_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x54BF790ull
+#define NIC1_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x54BF798ull
+#define NIC1_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x54BF7A0ull
+#define NIC1_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x54BF7A8ull
+#define NIC1_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x54BF7B0ull
+#define NIC1_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x54BF7B8ull
+#define NIC1_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x54BF7C0ull
+#define NIC1_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x54BF7C8ull
+#define NIC1_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x54BF7D0ull
+#define NIC1_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x54BF7D8ull
+#define NIC1_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x54BF7E0ull
+#define NIC1_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x54BF7E8ull
+#define NIC1_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x54BF7F0ull
+#define NIC1_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x54BF7F8ull
+#define NIC1_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x54BF800ull
+#define NIC1_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x54BF808ull
+#define NIC1_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x54BF810ull
+#define NIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x54BF818ull
+#define NIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC1_QPC1_AXUSER_CONG_QUE_BASE 0x54BFB80ull
+#define NIC1_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC1_QPC1_AXUSER_RXWQE_BASE 0x54BFBE0ull
+#define NIC1_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define NIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x54BFC40ull
+#define NIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC1_QPC1_AXUSER_DB_FIFO_BASE 0x54BFCA0ull
+#define NIC1_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x54BFD00ull
+#define NIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC1_QPC1_AXUSER_ERR_FIFO_BASE 0x54BFD60ull
+#define NIC1_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC1_QPC1_AXUSER_QPC_RESP_BASE 0x54BFDC0ull
+#define NIC1_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC1_QPC1_AXUSER_QPC_REQ_BASE 0x54BFE20ull
+#define NIC1_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC1_QPC1_SPECIAL_BASE 0x54BFE80ull
+#define NIC1_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_QPC1_SPECIAL_SECTION 0x8180
+#define NIC1_TMR_BASE 0x54C8000ull
+#define NIC1_TMR_MAX_OFFSET 0x1000
+#define NIC1_TMR_SECTION 0xD600
+#define NIC1_TMR_AXUSER_TMR_FREE_LIST_BASE 0x54C8D60ull
+#define NIC1_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC1_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define NIC1_TMR_AXUSER_TMR_FIFO_BASE 0x54C8DC0ull
+#define NIC1_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC1_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define NIC1_TMR_AXUSER_TMR_FSM_BASE 0x54C8E20ull
+#define NIC1_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC1_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define NIC1_TMR_SPECIAL_BASE 0x54C8E80ull
+#define NIC1_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_TMR_SPECIAL_SECTION 0x1800
+#define NIC1_RXB_CORE_BASE 0x54C9000ull
+#define NIC1_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC1_RXB_CORE_SECTION 0x6100
+#define NIC1_RXB_CORE_SCT_AWUSER_BASE 0x54C9610ull
+#define NIC1_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC1_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define NIC1_RXB_CORE_SPECIAL_BASE 0x54C9E80ull
+#define NIC1_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_RXB_CORE_SPECIAL_SECTION 0x1800
+#define NIC1_RXE0_BASE 0x54CA000ull
+#define NIC1_RXE0_MAX_OFFSET 0x1000
+#define NIC1_RXE0_SECTION 0x9000
+#define NIC1_RXE0_WQE_ARUSER_BASE 0x54CA900ull
+#define NIC1_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC1_RXE0_WQE_ARUSER_SECTION 0x5800
+#define NIC1_RXE0_SPECIAL_BASE 0x54CAE80ull
+#define NIC1_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_RXE0_SPECIAL_SECTION 0x1800
+#define NIC1_RXE1_BASE 0x54CB000ull
+#define NIC1_RXE1_MAX_OFFSET 0x1000
+#define NIC1_RXE1_SECTION 0x9000
+#define NIC1_RXE1_WQE_ARUSER_BASE 0x54CB900ull
+#define NIC1_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC1_RXE1_WQE_ARUSER_SECTION 0x5800
+#define NIC1_RXE1_SPECIAL_BASE 0x54CBE80ull
+#define NIC1_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_RXE1_SPECIAL_SECTION 0x1800
+#define NIC1_RXE0_AXUSER_AXUSER_CQ0_BASE 0x54CC000ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ1_BASE 0x54CC050ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ2_BASE 0x54CC0A0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ3_BASE 0x54CC0F0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ4_BASE 0x54CC140ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ5_BASE 0x54CC190ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ6_BASE 0x54CC1E0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ7_BASE 0x54CC230ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ8_BASE 0x54CC280ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ9_BASE 0x54CC2D0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ10_BASE 0x54CC320ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ11_BASE 0x54CC370ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ12_BASE 0x54CC3C0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ13_BASE 0x54CC410ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ14_BASE 0x54CC460ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ15_BASE 0x54CC4B0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ16_BASE 0x54CC500ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ17_BASE 0x54CC550ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ18_BASE 0x54CC5A0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ19_BASE 0x54CC5F0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ20_BASE 0x54CC640ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ21_BASE 0x54CC690ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ22_BASE 0x54CC6E0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ23_BASE 0x54CC730ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ24_BASE 0x54CC780ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ25_BASE 0x54CC7D0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ26_BASE 0x54CC820ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ27_BASE 0x54CC870ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ28_BASE 0x54CC8C0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ29_BASE 0x54CC910ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ30_BASE 0x54CC960ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ31_BASE 0x54CC9B0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC1_RXE0_AXUSER_SPECIAL_BASE 0x54CCE80ull
+#define NIC1_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define NIC1_RXE1_AXUSER_AXUSER_CQ0_BASE 0x54CD000ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ1_BASE 0x54CD050ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ2_BASE 0x54CD0A0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ3_BASE 0x54CD0F0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ4_BASE 0x54CD140ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ5_BASE 0x54CD190ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ6_BASE 0x54CD1E0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ7_BASE 0x54CD230ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ8_BASE 0x54CD280ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ9_BASE 0x54CD2D0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ10_BASE 0x54CD320ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ11_BASE 0x54CD370ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ12_BASE 0x54CD3C0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ13_BASE 0x54CD410ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ14_BASE 0x54CD460ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ15_BASE 0x54CD4B0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ16_BASE 0x54CD500ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ17_BASE 0x54CD550ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ18_BASE 0x54CD5A0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ19_BASE 0x54CD5F0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ20_BASE 0x54CD640ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ21_BASE 0x54CD690ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ22_BASE 0x54CD6E0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ23_BASE 0x54CD730ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ24_BASE 0x54CD780ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ25_BASE 0x54CD7D0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ26_BASE 0x54CD820ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ27_BASE 0x54CD870ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ28_BASE 0x54CD8C0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ29_BASE 0x54CD910ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ30_BASE 0x54CD960ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ31_BASE 0x54CD9B0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC1_RXE1_AXUSER_SPECIAL_BASE 0x54CDE80ull
+#define NIC1_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define NIC1_TXS0_BASE 0x54D0000ull
+#define NIC1_TXS0_MAX_OFFSET 0x1000
+#define NIC1_TXS0_SECTION 0xE800
+#define NIC1_TXS0_SPECIAL_BASE 0x54D0E80ull
+#define NIC1_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_TXS0_SPECIAL_SECTION 0x1800
+#define NIC1_TXS1_BASE 0x54D1000ull
+#define NIC1_TXS1_MAX_OFFSET 0x1000
+#define NIC1_TXS1_SECTION 0xE800
+#define NIC1_TXS1_SPECIAL_BASE 0x54D1E80ull
+#define NIC1_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_TXS1_SPECIAL_SECTION 0x1800
+#define NIC1_TXE0_BASE 0x54D2000ull
+#define NIC1_TXE0_MAX_OFFSET 0x1000
+#define NIC1_TXE0_SECTION 0xE800
+#define NIC1_TXE0_SPECIAL_BASE 0x54D2E80ull
+#define NIC1_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_TXE0_SPECIAL_SECTION 0x1800
+#define NIC1_TXE1_BASE 0x54D3000ull
+#define NIC1_TXE1_MAX_OFFSET 0x1000
+#define NIC1_TXE1_SECTION 0xE800
+#define NIC1_TXE1_SPECIAL_BASE 0x54D3E80ull
+#define NIC1_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_TXE1_SPECIAL_SECTION 0x1800
+#define NIC1_TXB_BASE 0x54D4000ull
+#define NIC1_TXB_MAX_OFFSET 0x1000
+#define NIC1_TXB_SECTION 0xE800
+#define NIC1_TXB_SPECIAL_BASE 0x54D4E80ull
+#define NIC1_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_TXB_SPECIAL_SECTION 0x1800
+#define NIC1_MSTR_IF_RR_SHRD_HBW_BASE 0x54D5000ull
+#define NIC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define NIC1_MSTR_IF_RR_PRVT_HBW_BASE 0x54D5200ull
+#define NIC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define NIC1_MSTR_IF_RR_SHRD_LBW_BASE 0x54D5400ull
+#define NIC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define NIC1_MSTR_IF_RR_PRVT_LBW_BASE 0x54D5600ull
+#define NIC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define NIC1_MSTR_IF_E2E_CRDT_BASE 0x54D5800ull
+#define NIC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define NIC1_MSTR_IF_AXUSER_BASE 0x54D5A80ull
+#define NIC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define NIC1_MSTR_IF_DBG_HBW_BASE 0x54D5B00ull
+#define NIC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define NIC1_MSTR_IF_DBG_LBW_BASE 0x54D5B80ull
+#define NIC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define NIC1_MSTR_IF_CORE_HBW_BASE 0x54D5C00ull
+#define NIC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define NIC1_MSTR_IF_CORE_LBW_BASE 0x54D5D80ull
+#define NIC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define NIC1_MSTR_IF_SPECIAL_BASE 0x54D5E80ull
+#define NIC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define NIC1_TX_AXUSER_BASE 0x54D6000ull
+#define NIC1_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC1_TX_AXUSER_SECTION 0x2000
+#define NIC1_SERDES0_BASE 0x54D8000ull
+#define NIC1_SERDES0_MAX_OFFSET 0x3E40
+#define NIC1_SERDES0_SECTION 0x4000
+#define NIC1_SERDES1_BASE 0x54DC000ull
+#define NIC1_SERDES1_MAX_OFFSET 0x3E40
+#define NIC1_SERDES1_SECTION 0x4000
+#define NIC1_PHY_BASE 0x54E0000ull
+#define NIC1_PHY_MAX_OFFSET 0x1000
+#define NIC1_PHY_SECTION 0xE800
+#define NIC1_PHY_SPECIAL_BASE 0x54E0E80ull
+#define NIC1_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_PHY_SPECIAL_SECTION 0x7180
+#define PRT1_MAC_AUX_BASE 0x54E8000ull
+#define PRT1_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT1_MAC_AUX_SECTION 0xE800
+#define PRT1_MAC_AUX_SPECIAL_BASE 0x54E8E80ull
+#define PRT1_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT1_MAC_AUX_SPECIAL_SECTION 0x1800
+#define PRT1_MAC_CORE_BASE 0x54E9000ull
+#define PRT1_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT1_MAC_CORE_SECTION 0xE800
+#define PRT1_MAC_CORE_SPECIAL_BASE 0x54E9E80ull
+#define PRT1_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT1_MAC_CORE_SPECIAL_SECTION 0x1800
+#define NIC1_MAC_RS_FEC_BASE 0x54EA000ull
+#define NIC1_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC1_MAC_RS_FEC_SECTION 0x1000
+#define NIC1_MAC_GLOB_STAT_CONTROL_REG_BASE 0x54EB000ull
+#define NIC1_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC1_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define NIC1_MAC_GLOB_STAT_RX0_BASE 0x54EB100ull
+#define NIC1_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC1_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define NIC1_MAC_GLOB_STAT_RX1_BASE 0x54EB18Cull
+#define NIC1_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC1_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define NIC1_MAC_GLOB_STAT_RX2_BASE 0x54EB218ull
+#define NIC1_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC1_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define NIC1_MAC_GLOB_STAT_RX3_BASE 0x54EB2A4ull
+#define NIC1_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC1_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define NIC1_MAC_GLOB_STAT_TX0_BASE 0x54EB330ull
+#define NIC1_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC1_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define NIC1_MAC_GLOB_STAT_TX1_BASE 0x54EB398ull
+#define NIC1_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC1_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define NIC1_MAC_GLOB_STAT_TX2_BASE 0x54EB400ull
+#define NIC1_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC1_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define NIC1_MAC_GLOB_STAT_TX3_BASE 0x54EB468ull
+#define NIC1_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC1_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define NIC1_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x54EB800ull
+#define NIC1_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC1_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define NIC1_MAC_CH0_MAC_PCS_BASE 0x54EC000ull
+#define NIC1_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC1_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define NIC1_MAC_CH0_MAC_128_BASE 0x54EC400ull
+#define NIC1_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC1_MAC_CH0_MAC_128_SECTION 0x4000
+#define NIC1_MAC_CH0_MAC_AN_BASE 0x54EC800ull
+#define NIC1_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC1_MAC_CH0_MAC_AN_SECTION 0x8000
+#define NIC1_MAC_CH1_MAC_PCS_BASE 0x54ED000ull
+#define NIC1_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC1_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define NIC1_MAC_CH1_MAC_128_BASE 0x54ED400ull
+#define NIC1_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC1_MAC_CH1_MAC_128_SECTION 0x4000
+#define NIC1_MAC_CH1_MAC_AN_BASE 0x54ED800ull
+#define NIC1_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC1_MAC_CH1_MAC_AN_SECTION 0x8000
+#define NIC1_MAC_CH2_MAC_PCS_BASE 0x54EE000ull
+#define NIC1_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC1_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define NIC1_MAC_CH2_MAC_128_BASE 0x54EE400ull
+#define NIC1_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC1_MAC_CH2_MAC_128_SECTION 0x4000
+#define NIC1_MAC_CH2_MAC_AN_BASE 0x54EE800ull
+#define NIC1_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC1_MAC_CH2_MAC_AN_SECTION 0x8000
+#define NIC1_MAC_CH3_MAC_PCS_BASE 0x54EF000ull
+#define NIC1_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC1_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define NIC1_MAC_CH3_MAC_128_BASE 0x54EF400ull
+#define NIC1_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC1_MAC_CH3_MAC_128_SECTION 0x4000
+#define NIC1_MAC_CH3_MAC_AN_BASE 0x54EF800ull
+#define NIC1_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC1_MAC_CH3_MAC_AN_SECTION 0x10800
+#define NIC2_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5500000ull
+#define NIC2_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5500080ull
+#define NIC2_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5500100ull
+#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5500180ull
+#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_0_SPECIAL_BASE 0x5500E80ull
+#define NIC2_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_0_SPECIAL_SECTION 0x1800
+#define NIC2_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5501000ull
+#define NIC2_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5501080ull
+#define NIC2_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5501100ull
+#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5501180ull
+#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_1_SPECIAL_BASE 0x5501E80ull
+#define NIC2_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_1_SPECIAL_SECTION 0x1800
+#define NIC2_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5502000ull
+#define NIC2_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5502080ull
+#define NIC2_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5502100ull
+#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5502180ull
+#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_2_SPECIAL_BASE 0x5502E80ull
+#define NIC2_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_2_SPECIAL_SECTION 0x1800
+#define NIC2_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5503000ull
+#define NIC2_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5503080ull
+#define NIC2_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5503100ull
+#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5503180ull
+#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_3_SPECIAL_BASE 0x5503E80ull
+#define NIC2_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_3_SPECIAL_SECTION 0x1800
+#define NIC2_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5504000ull
+#define NIC2_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5504080ull
+#define NIC2_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5504100ull
+#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5504180ull
+#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_4_SPECIAL_BASE 0x5504E80ull
+#define NIC2_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_4_SPECIAL_SECTION 0x1800
+#define NIC2_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5505000ull
+#define NIC2_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5505080ull
+#define NIC2_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5505100ull
+#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5505180ull
+#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_5_SPECIAL_BASE 0x5505E80ull
+#define NIC2_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_5_SPECIAL_SECTION 0x1800
+#define NIC2_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5506000ull
+#define NIC2_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5506080ull
+#define NIC2_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5506100ull
+#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5506180ull
+#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_6_SPECIAL_BASE 0x5506E80ull
+#define NIC2_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_6_SPECIAL_SECTION 0x1800
+#define NIC2_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5507000ull
+#define NIC2_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5507080ull
+#define NIC2_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5507100ull
+#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5507180ull
+#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_7_SPECIAL_BASE 0x5507E80ull
+#define NIC2_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_7_SPECIAL_SECTION 0x1800
+#define NIC2_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5508000ull
+#define NIC2_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5508080ull
+#define NIC2_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5508100ull
+#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5508180ull
+#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_8_SPECIAL_BASE 0x5508E80ull
+#define NIC2_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_8_SPECIAL_SECTION 0x1800
+#define NIC2_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5509000ull
+#define NIC2_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5509080ull
+#define NIC2_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5509100ull
+#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5509180ull
+#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_9_SPECIAL_BASE 0x5509E80ull
+#define NIC2_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_9_SPECIAL_SECTION 0x1800
+#define NIC2_UMR0_10_UNSECURE_DOORBELL0_BASE 0x550A000ull
+#define NIC2_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_10_UNSECURE_DOORBELL1_BASE 0x550A080ull
+#define NIC2_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x550A100ull
+#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x550A180ull
+#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_10_SPECIAL_BASE 0x550AE80ull
+#define NIC2_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_10_SPECIAL_SECTION 0x1800
+#define NIC2_UMR0_11_UNSECURE_DOORBELL0_BASE 0x550B000ull
+#define NIC2_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_11_UNSECURE_DOORBELL1_BASE 0x550B080ull
+#define NIC2_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x550B100ull
+#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x550B180ull
+#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_11_SPECIAL_BASE 0x550BE80ull
+#define NIC2_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_11_SPECIAL_SECTION 0x1800
+#define NIC2_UMR0_12_UNSECURE_DOORBELL0_BASE 0x550C000ull
+#define NIC2_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_12_UNSECURE_DOORBELL1_BASE 0x550C080ull
+#define NIC2_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x550C100ull
+#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x550C180ull
+#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_12_SPECIAL_BASE 0x550CE80ull
+#define NIC2_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_12_SPECIAL_SECTION 0x1800
+#define NIC2_UMR0_13_UNSECURE_DOORBELL0_BASE 0x550D000ull
+#define NIC2_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_13_UNSECURE_DOORBELL1_BASE 0x550D080ull
+#define NIC2_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x550D100ull
+#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x550D180ull
+#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_13_SPECIAL_BASE 0x550DE80ull
+#define NIC2_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_13_SPECIAL_SECTION 0x1800
+#define NIC2_UMR0_14_UNSECURE_DOORBELL0_BASE 0x550E000ull
+#define NIC2_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR0_14_UNSECURE_DOORBELL1_BASE 0x550E080ull
+#define NIC2_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x550E100ull
+#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x550E180ull
+#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR0_14_SPECIAL_BASE 0x550EE80ull
+#define NIC2_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_14_SPECIAL_SECTION 0x1180
+#define NIC2_QM_DCCM0_BASE 0x5510000ull
+#define NIC2_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC2_QM_DCCM0_SECTION 0x8000
+#define NIC2_QM_ARC_AUX0_BASE 0x5518000ull
+#define NIC2_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC2_QM_ARC_AUX0_SECTION 0xE800
+#define NIC2_QM_ARC_AUX0_SPECIAL_BASE 0x5518E80ull
+#define NIC2_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define NIC2_QM0_BASE 0x551A000ull
+#define NIC2_QM0_MAX_OFFSET 0x1000
+#define NIC2_QM0_SECTION 0x9000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x551A900ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x551A908ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x551A910ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x551A918ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x551A920ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x551A928ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x551A930ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x551A938ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x551A940ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x551A948ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x551A950ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x551A958ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x551A960ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x551A968ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x551A970ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x551A978ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC2_QM0_AXUSER_SECURED_BASE 0x551AB00ull
+#define NIC2_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC2_QM0_AXUSER_SECURED_SECTION 0x8000
+#define NIC2_QM0_AXUSER_NONSECURED_BASE 0x551AB80ull
+#define NIC2_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC2_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC2_QM0_DBG_HBW_BASE 0x551AC00ull
+#define NIC2_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC2_QM0_DBG_HBW_SECTION 0x8000
+#define NIC2_QM0_DBG_LBW_BASE 0x551AC80ull
+#define NIC2_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC2_QM0_DBG_LBW_SECTION 0x1000
+#define NIC2_QM0_CGM_BASE 0x551AD80ull
+#define NIC2_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC2_QM0_CGM_SECTION 0x1000
+#define NIC2_QM0_SPECIAL_BASE 0x551AE80ull
+#define NIC2_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_QM0_SPECIAL_SECTION 0x4180
+#define NIC2_QPC0_BASE 0x551F000ull
+#define NIC2_QPC0_MAX_OFFSET 0x1000
+#define NIC2_QPC0_SECTION 0x7200
+#define NIC2_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x551F720ull
+#define NIC2_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x551F728ull
+#define NIC2_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x551F730ull
+#define NIC2_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x551F738ull
+#define NIC2_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x551F740ull
+#define NIC2_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x551F748ull
+#define NIC2_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x551F750ull
+#define NIC2_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x551F758ull
+#define NIC2_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x551F760ull
+#define NIC2_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x551F768ull
+#define NIC2_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x551F770ull
+#define NIC2_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x551F778ull
+#define NIC2_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x551F780ull
+#define NIC2_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x551F788ull
+#define NIC2_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x551F790ull
+#define NIC2_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x551F798ull
+#define NIC2_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x551F7A0ull
+#define NIC2_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x551F7A8ull
+#define NIC2_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x551F7B0ull
+#define NIC2_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x551F7B8ull
+#define NIC2_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x551F7C0ull
+#define NIC2_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x551F7C8ull
+#define NIC2_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x551F7D0ull
+#define NIC2_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x551F7D8ull
+#define NIC2_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x551F7E0ull
+#define NIC2_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x551F7E8ull
+#define NIC2_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x551F7F0ull
+#define NIC2_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x551F7F8ull
+#define NIC2_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x551F800ull
+#define NIC2_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x551F808ull
+#define NIC2_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x551F810ull
+#define NIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x551F818ull
+#define NIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC2_QPC0_AXUSER_CONG_QUE_BASE 0x551FB80ull
+#define NIC2_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC2_QPC0_AXUSER_RXWQE_BASE 0x551FBE0ull
+#define NIC2_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define NIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x551FC40ull
+#define NIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC2_QPC0_AXUSER_DB_FIFO_BASE 0x551FCA0ull
+#define NIC2_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x551FD00ull
+#define NIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC2_QPC0_AXUSER_ERR_FIFO_BASE 0x551FD60ull
+#define NIC2_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC2_QPC0_AXUSER_QPC_RESP_BASE 0x551FDC0ull
+#define NIC2_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC2_QPC0_AXUSER_QPC_REQ_BASE 0x551FE20ull
+#define NIC2_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC2_QPC0_SPECIAL_BASE 0x551FE80ull
+#define NIC2_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_QPC0_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5520000ull
+#define NIC2_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5520080ull
+#define NIC2_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5520100ull
+#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5520180ull
+#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_0_SPECIAL_BASE 0x5520E80ull
+#define NIC2_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_0_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5521000ull
+#define NIC2_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5521080ull
+#define NIC2_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5521100ull
+#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5521180ull
+#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_1_SPECIAL_BASE 0x5521E80ull
+#define NIC2_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_1_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5522000ull
+#define NIC2_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5522080ull
+#define NIC2_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5522100ull
+#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5522180ull
+#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_2_SPECIAL_BASE 0x5522E80ull
+#define NIC2_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_2_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5523000ull
+#define NIC2_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5523080ull
+#define NIC2_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5523100ull
+#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5523180ull
+#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_3_SPECIAL_BASE 0x5523E80ull
+#define NIC2_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_3_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5524000ull
+#define NIC2_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5524080ull
+#define NIC2_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5524100ull
+#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5524180ull
+#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_4_SPECIAL_BASE 0x5524E80ull
+#define NIC2_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_4_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5525000ull
+#define NIC2_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5525080ull
+#define NIC2_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5525100ull
+#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5525180ull
+#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_5_SPECIAL_BASE 0x5525E80ull
+#define NIC2_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_5_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5526000ull
+#define NIC2_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5526080ull
+#define NIC2_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5526100ull
+#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5526180ull
+#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_6_SPECIAL_BASE 0x5526E80ull
+#define NIC2_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_6_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5527000ull
+#define NIC2_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5527080ull
+#define NIC2_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5527100ull
+#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5527180ull
+#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_7_SPECIAL_BASE 0x5527E80ull
+#define NIC2_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_7_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5528000ull
+#define NIC2_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5528080ull
+#define NIC2_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5528100ull
+#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5528180ull
+#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_8_SPECIAL_BASE 0x5528E80ull
+#define NIC2_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_8_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5529000ull
+#define NIC2_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5529080ull
+#define NIC2_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5529100ull
+#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5529180ull
+#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_9_SPECIAL_BASE 0x5529E80ull
+#define NIC2_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_9_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_10_UNSECURE_DOORBELL0_BASE 0x552A000ull
+#define NIC2_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_10_UNSECURE_DOORBELL1_BASE 0x552A080ull
+#define NIC2_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x552A100ull
+#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x552A180ull
+#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_10_SPECIAL_BASE 0x552AE80ull
+#define NIC2_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_10_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_11_UNSECURE_DOORBELL0_BASE 0x552B000ull
+#define NIC2_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_11_UNSECURE_DOORBELL1_BASE 0x552B080ull
+#define NIC2_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x552B100ull
+#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x552B180ull
+#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_11_SPECIAL_BASE 0x552BE80ull
+#define NIC2_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_11_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_12_UNSECURE_DOORBELL0_BASE 0x552C000ull
+#define NIC2_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_12_UNSECURE_DOORBELL1_BASE 0x552C080ull
+#define NIC2_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x552C100ull
+#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x552C180ull
+#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_12_SPECIAL_BASE 0x552CE80ull
+#define NIC2_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_12_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_13_UNSECURE_DOORBELL0_BASE 0x552D000ull
+#define NIC2_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_13_UNSECURE_DOORBELL1_BASE 0x552D080ull
+#define NIC2_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x552D100ull
+#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x552D180ull
+#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_13_SPECIAL_BASE 0x552DE80ull
+#define NIC2_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_13_SPECIAL_SECTION 0x1800
+#define NIC2_UMR1_14_UNSECURE_DOORBELL0_BASE 0x552E000ull
+#define NIC2_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC2_UMR1_14_UNSECURE_DOORBELL1_BASE 0x552E080ull
+#define NIC2_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x552E100ull
+#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x552E180ull
+#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC2_UMR1_14_SPECIAL_BASE 0x552EE80ull
+#define NIC2_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_14_SPECIAL_SECTION 0x1180
+#define NIC2_QM_DCCM1_BASE 0x5530000ull
+#define NIC2_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC2_QM_DCCM1_SECTION 0x8000
+#define NIC2_QM_ARC_AUX1_BASE 0x5538000ull
+#define NIC2_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC2_QM_ARC_AUX1_SECTION 0xE800
+#define NIC2_QM_ARC_AUX1_SPECIAL_BASE 0x5538E80ull
+#define NIC2_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define NIC2_QM1_BASE 0x553A000ull
+#define NIC2_QM1_MAX_OFFSET 0x1000
+#define NIC2_QM1_SECTION 0x9000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x553A900ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x553A908ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x553A910ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x553A918ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x553A920ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x553A928ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x553A930ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x553A938ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x553A940ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x553A948ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x553A950ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x553A958ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x553A960ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x553A968ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x553A970ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x553A978ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC2_QM1_AXUSER_SECURED_BASE 0x553AB00ull
+#define NIC2_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC2_QM1_AXUSER_SECURED_SECTION 0x8000
+#define NIC2_QM1_AXUSER_NONSECURED_BASE 0x553AB80ull
+#define NIC2_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC2_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC2_QM1_DBG_HBW_BASE 0x553AC00ull
+#define NIC2_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC2_QM1_DBG_HBW_SECTION 0x8000
+#define NIC2_QM1_DBG_LBW_BASE 0x553AC80ull
+#define NIC2_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC2_QM1_DBG_LBW_SECTION 0x1000
+#define NIC2_QM1_CGM_BASE 0x553AD80ull
+#define NIC2_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC2_QM1_CGM_SECTION 0x1000
+#define NIC2_QM1_SPECIAL_BASE 0x553AE80ull
+#define NIC2_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_QM1_SPECIAL_SECTION 0x4180
+#define NIC2_QPC1_BASE 0x553F000ull
+#define NIC2_QPC1_MAX_OFFSET 0x1000
+#define NIC2_QPC1_SECTION 0x7200
+#define NIC2_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x553F720ull
+#define NIC2_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x553F728ull
+#define NIC2_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x553F730ull
+#define NIC2_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x553F738ull
+#define NIC2_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x553F740ull
+#define NIC2_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x553F748ull
+#define NIC2_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x553F750ull
+#define NIC2_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x553F758ull
+#define NIC2_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x553F760ull
+#define NIC2_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x553F768ull
+#define NIC2_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x553F770ull
+#define NIC2_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x553F778ull
+#define NIC2_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x553F780ull
+#define NIC2_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x553F788ull
+#define NIC2_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x553F790ull
+#define NIC2_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x553F798ull
+#define NIC2_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x553F7A0ull
+#define NIC2_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x553F7A8ull
+#define NIC2_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x553F7B0ull
+#define NIC2_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x553F7B8ull
+#define NIC2_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x553F7C0ull
+#define NIC2_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x553F7C8ull
+#define NIC2_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x553F7D0ull
+#define NIC2_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x553F7D8ull
+#define NIC2_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x553F7E0ull
+#define NIC2_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x553F7E8ull
+#define NIC2_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x553F7F0ull
+#define NIC2_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x553F7F8ull
+#define NIC2_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x553F800ull
+#define NIC2_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x553F808ull
+#define NIC2_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x553F810ull
+#define NIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x553F818ull
+#define NIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC2_QPC1_AXUSER_CONG_QUE_BASE 0x553FB80ull
+#define NIC2_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC2_QPC1_AXUSER_RXWQE_BASE 0x553FBE0ull
+#define NIC2_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define NIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x553FC40ull
+#define NIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC2_QPC1_AXUSER_DB_FIFO_BASE 0x553FCA0ull
+#define NIC2_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x553FD00ull
+#define NIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC2_QPC1_AXUSER_ERR_FIFO_BASE 0x553FD60ull
+#define NIC2_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC2_QPC1_AXUSER_QPC_RESP_BASE 0x553FDC0ull
+#define NIC2_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC2_QPC1_AXUSER_QPC_REQ_BASE 0x553FE20ull
+#define NIC2_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC2_QPC1_SPECIAL_BASE 0x553FE80ull
+#define NIC2_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_QPC1_SPECIAL_SECTION 0x8180
+#define NIC2_TMR_BASE 0x5548000ull
+#define NIC2_TMR_MAX_OFFSET 0x1000
+#define NIC2_TMR_SECTION 0xD600
+#define NIC2_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5548D60ull
+#define NIC2_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC2_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define NIC2_TMR_AXUSER_TMR_FIFO_BASE 0x5548DC0ull
+#define NIC2_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC2_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define NIC2_TMR_AXUSER_TMR_FSM_BASE 0x5548E20ull
+#define NIC2_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC2_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define NIC2_TMR_SPECIAL_BASE 0x5548E80ull
+#define NIC2_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_TMR_SPECIAL_SECTION 0x1800
+#define NIC2_RXB_CORE_BASE 0x5549000ull
+#define NIC2_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC2_RXB_CORE_SECTION 0x6100
+#define NIC2_RXB_CORE_SCT_AWUSER_BASE 0x5549610ull
+#define NIC2_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC2_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define NIC2_RXB_CORE_SPECIAL_BASE 0x5549E80ull
+#define NIC2_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_RXB_CORE_SPECIAL_SECTION 0x1800
+#define NIC2_RXE0_BASE 0x554A000ull
+#define NIC2_RXE0_MAX_OFFSET 0x1000
+#define NIC2_RXE0_SECTION 0x9000
+#define NIC2_RXE0_WQE_ARUSER_BASE 0x554A900ull
+#define NIC2_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC2_RXE0_WQE_ARUSER_SECTION 0x5800
+#define NIC2_RXE0_SPECIAL_BASE 0x554AE80ull
+#define NIC2_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_RXE0_SPECIAL_SECTION 0x1800
+#define NIC2_RXE1_BASE 0x554B000ull
+#define NIC2_RXE1_MAX_OFFSET 0x1000
+#define NIC2_RXE1_SECTION 0x9000
+#define NIC2_RXE1_WQE_ARUSER_BASE 0x554B900ull
+#define NIC2_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC2_RXE1_WQE_ARUSER_SECTION 0x5800
+#define NIC2_RXE1_SPECIAL_BASE 0x554BE80ull
+#define NIC2_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_RXE1_SPECIAL_SECTION 0x1800
+#define NIC2_RXE0_AXUSER_AXUSER_CQ0_BASE 0x554C000ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ1_BASE 0x554C050ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ2_BASE 0x554C0A0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ3_BASE 0x554C0F0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ4_BASE 0x554C140ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ5_BASE 0x554C190ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ6_BASE 0x554C1E0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ7_BASE 0x554C230ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ8_BASE 0x554C280ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ9_BASE 0x554C2D0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ10_BASE 0x554C320ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ11_BASE 0x554C370ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ12_BASE 0x554C3C0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ13_BASE 0x554C410ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ14_BASE 0x554C460ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ15_BASE 0x554C4B0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ16_BASE 0x554C500ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ17_BASE 0x554C550ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ18_BASE 0x554C5A0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ19_BASE 0x554C5F0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ20_BASE 0x554C640ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ21_BASE 0x554C690ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ22_BASE 0x554C6E0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ23_BASE 0x554C730ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ24_BASE 0x554C780ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ25_BASE 0x554C7D0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ26_BASE 0x554C820ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ27_BASE 0x554C870ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ28_BASE 0x554C8C0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ29_BASE 0x554C910ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ30_BASE 0x554C960ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ31_BASE 0x554C9B0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC2_RXE0_AXUSER_SPECIAL_BASE 0x554CE80ull
+#define NIC2_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define NIC2_RXE1_AXUSER_AXUSER_CQ0_BASE 0x554D000ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ1_BASE 0x554D050ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ2_BASE 0x554D0A0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ3_BASE 0x554D0F0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ4_BASE 0x554D140ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ5_BASE 0x554D190ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ6_BASE 0x554D1E0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ7_BASE 0x554D230ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ8_BASE 0x554D280ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ9_BASE 0x554D2D0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ10_BASE 0x554D320ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ11_BASE 0x554D370ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ12_BASE 0x554D3C0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ13_BASE 0x554D410ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ14_BASE 0x554D460ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ15_BASE 0x554D4B0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ16_BASE 0x554D500ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ17_BASE 0x554D550ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ18_BASE 0x554D5A0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ19_BASE 0x554D5F0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ20_BASE 0x554D640ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ21_BASE 0x554D690ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ22_BASE 0x554D6E0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ23_BASE 0x554D730ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ24_BASE 0x554D780ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ25_BASE 0x554D7D0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ26_BASE 0x554D820ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ27_BASE 0x554D870ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ28_BASE 0x554D8C0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ29_BASE 0x554D910ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ30_BASE 0x554D960ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ31_BASE 0x554D9B0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC2_RXE1_AXUSER_SPECIAL_BASE 0x554DE80ull
+#define NIC2_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define NIC2_TXS0_BASE 0x5550000ull
+#define NIC2_TXS0_MAX_OFFSET 0x1000
+#define NIC2_TXS0_SECTION 0xE800
+#define NIC2_TXS0_SPECIAL_BASE 0x5550E80ull
+#define NIC2_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_TXS0_SPECIAL_SECTION 0x1800
+#define NIC2_TXS1_BASE 0x5551000ull
+#define NIC2_TXS1_MAX_OFFSET 0x1000
+#define NIC2_TXS1_SECTION 0xE800
+#define NIC2_TXS1_SPECIAL_BASE 0x5551E80ull
+#define NIC2_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_TXS1_SPECIAL_SECTION 0x1800
+#define NIC2_TXE0_BASE 0x5552000ull
+#define NIC2_TXE0_MAX_OFFSET 0x1000
+#define NIC2_TXE0_SECTION 0xE800
+#define NIC2_TXE0_SPECIAL_BASE 0x5552E80ull
+#define NIC2_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_TXE0_SPECIAL_SECTION 0x1800
+#define NIC2_TXE1_BASE 0x5553000ull
+#define NIC2_TXE1_MAX_OFFSET 0x1000
+#define NIC2_TXE1_SECTION 0xE800
+#define NIC2_TXE1_SPECIAL_BASE 0x5553E80ull
+#define NIC2_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_TXE1_SPECIAL_SECTION 0x1800
+#define NIC2_TXB_BASE 0x5554000ull
+#define NIC2_TXB_MAX_OFFSET 0x1000
+#define NIC2_TXB_SECTION 0xE800
+#define NIC2_TXB_SPECIAL_BASE 0x5554E80ull
+#define NIC2_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_TXB_SPECIAL_SECTION 0x1800
+#define NIC2_MSTR_IF_RR_SHRD_HBW_BASE 0x5555000ull
+#define NIC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define NIC2_MSTR_IF_RR_PRVT_HBW_BASE 0x5555200ull
+#define NIC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define NIC2_MSTR_IF_RR_SHRD_LBW_BASE 0x5555400ull
+#define NIC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define NIC2_MSTR_IF_RR_PRVT_LBW_BASE 0x5555600ull
+#define NIC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define NIC2_MSTR_IF_E2E_CRDT_BASE 0x5555800ull
+#define NIC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define NIC2_MSTR_IF_AXUSER_BASE 0x5555A80ull
+#define NIC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC2_MSTR_IF_AXUSER_SECTION 0x8000
+#define NIC2_MSTR_IF_DBG_HBW_BASE 0x5555B00ull
+#define NIC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define NIC2_MSTR_IF_DBG_LBW_BASE 0x5555B80ull
+#define NIC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define NIC2_MSTR_IF_CORE_HBW_BASE 0x5555C00ull
+#define NIC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define NIC2_MSTR_IF_CORE_LBW_BASE 0x5555D80ull
+#define NIC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define NIC2_MSTR_IF_SPECIAL_BASE 0x5555E80ull
+#define NIC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_MSTR_IF_SPECIAL_SECTION 0x1800
+#define NIC2_TX_AXUSER_BASE 0x5556000ull
+#define NIC2_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC2_TX_AXUSER_SECTION 0x2000
+#define NIC2_SERDES0_BASE 0x5558000ull
+#define NIC2_SERDES0_MAX_OFFSET 0x3E40
+#define NIC2_SERDES0_SECTION 0x4000
+#define NIC2_SERDES1_BASE 0x555C000ull
+#define NIC2_SERDES1_MAX_OFFSET 0x3E40
+#define NIC2_SERDES1_SECTION 0x4000
+#define NIC2_PHY_BASE 0x5560000ull
+#define NIC2_PHY_MAX_OFFSET 0x1000
+#define NIC2_PHY_SECTION 0xE800
+#define NIC2_PHY_SPECIAL_BASE 0x5560E80ull
+#define NIC2_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_PHY_SPECIAL_SECTION 0x7180
+#define PRT2_MAC_AUX_BASE 0x5568000ull
+#define PRT2_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT2_MAC_AUX_SECTION 0xE800
+#define PRT2_MAC_AUX_SPECIAL_BASE 0x5568E80ull
+#define PRT2_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT2_MAC_AUX_SPECIAL_SECTION 0x1800
+#define PRT2_MAC_CORE_BASE 0x5569000ull
+#define PRT2_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT2_MAC_CORE_SECTION 0xE800
+#define PRT2_MAC_CORE_SPECIAL_BASE 0x5569E80ull
+#define PRT2_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT2_MAC_CORE_SPECIAL_SECTION 0x1800
+#define NIC2_MAC_RS_FEC_BASE 0x556A000ull
+#define NIC2_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC2_MAC_RS_FEC_SECTION 0x1000
+#define NIC2_MAC_GLOB_STAT_CONTROL_REG_BASE 0x556B000ull
+#define NIC2_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC2_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define NIC2_MAC_GLOB_STAT_RX0_BASE 0x556B100ull
+#define NIC2_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC2_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define NIC2_MAC_GLOB_STAT_RX1_BASE 0x556B18Cull
+#define NIC2_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC2_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define NIC2_MAC_GLOB_STAT_RX2_BASE 0x556B218ull
+#define NIC2_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC2_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define NIC2_MAC_GLOB_STAT_RX3_BASE 0x556B2A4ull
+#define NIC2_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC2_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define NIC2_MAC_GLOB_STAT_TX0_BASE 0x556B330ull
+#define NIC2_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC2_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define NIC2_MAC_GLOB_STAT_TX1_BASE 0x556B398ull
+#define NIC2_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC2_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define NIC2_MAC_GLOB_STAT_TX2_BASE 0x556B400ull
+#define NIC2_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC2_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define NIC2_MAC_GLOB_STAT_TX3_BASE 0x556B468ull
+#define NIC2_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC2_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define NIC2_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x556B800ull
+#define NIC2_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC2_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define NIC2_MAC_CH0_MAC_PCS_BASE 0x556C000ull
+#define NIC2_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC2_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define NIC2_MAC_CH0_MAC_128_BASE 0x556C400ull
+#define NIC2_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC2_MAC_CH0_MAC_128_SECTION 0x4000
+#define NIC2_MAC_CH0_MAC_AN_BASE 0x556C800ull
+#define NIC2_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC2_MAC_CH0_MAC_AN_SECTION 0x8000
+#define NIC2_MAC_CH1_MAC_PCS_BASE 0x556D000ull
+#define NIC2_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC2_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define NIC2_MAC_CH1_MAC_128_BASE 0x556D400ull
+#define NIC2_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC2_MAC_CH1_MAC_128_SECTION 0x4000
+#define NIC2_MAC_CH1_MAC_AN_BASE 0x556D800ull
+#define NIC2_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC2_MAC_CH1_MAC_AN_SECTION 0x8000
+#define NIC2_MAC_CH2_MAC_PCS_BASE 0x556E000ull
+#define NIC2_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC2_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define NIC2_MAC_CH2_MAC_128_BASE 0x556E400ull
+#define NIC2_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC2_MAC_CH2_MAC_128_SECTION 0x4000
+#define NIC2_MAC_CH2_MAC_AN_BASE 0x556E800ull
+#define NIC2_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC2_MAC_CH2_MAC_AN_SECTION 0x8000
+#define NIC2_MAC_CH3_MAC_PCS_BASE 0x556F000ull
+#define NIC2_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC2_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define NIC2_MAC_CH3_MAC_128_BASE 0x556F400ull
+#define NIC2_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC2_MAC_CH3_MAC_128_SECTION 0x4000
+#define NIC2_MAC_CH3_MAC_AN_BASE 0x556F800ull
+#define NIC2_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC2_MAC_CH3_MAC_AN_SECTION 0x10800
+#define NIC3_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5580000ull
+#define NIC3_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5580080ull
+#define NIC3_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5580100ull
+#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5580180ull
+#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_0_SPECIAL_BASE 0x5580E80ull
+#define NIC3_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_0_SPECIAL_SECTION 0x1800
+#define NIC3_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5581000ull
+#define NIC3_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5581080ull
+#define NIC3_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5581100ull
+#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5581180ull
+#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_1_SPECIAL_BASE 0x5581E80ull
+#define NIC3_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_1_SPECIAL_SECTION 0x1800
+#define NIC3_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5582000ull
+#define NIC3_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5582080ull
+#define NIC3_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5582100ull
+#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5582180ull
+#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_2_SPECIAL_BASE 0x5582E80ull
+#define NIC3_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_2_SPECIAL_SECTION 0x1800
+#define NIC3_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5583000ull
+#define NIC3_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5583080ull
+#define NIC3_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5583100ull
+#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5583180ull
+#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_3_SPECIAL_BASE 0x5583E80ull
+#define NIC3_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_3_SPECIAL_SECTION 0x1800
+#define NIC3_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5584000ull
+#define NIC3_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5584080ull
+#define NIC3_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5584100ull
+#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5584180ull
+#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_4_SPECIAL_BASE 0x5584E80ull
+#define NIC3_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_4_SPECIAL_SECTION 0x1800
+#define NIC3_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5585000ull
+#define NIC3_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5585080ull
+#define NIC3_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5585100ull
+#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5585180ull
+#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_5_SPECIAL_BASE 0x5585E80ull
+#define NIC3_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_5_SPECIAL_SECTION 0x1800
+#define NIC3_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5586000ull
+#define NIC3_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5586080ull
+#define NIC3_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5586100ull
+#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5586180ull
+#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_6_SPECIAL_BASE 0x5586E80ull
+#define NIC3_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_6_SPECIAL_SECTION 0x1800
+#define NIC3_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5587000ull
+#define NIC3_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5587080ull
+#define NIC3_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5587100ull
+#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5587180ull
+#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_7_SPECIAL_BASE 0x5587E80ull
+#define NIC3_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_7_SPECIAL_SECTION 0x1800
+#define NIC3_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5588000ull
+#define NIC3_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5588080ull
+#define NIC3_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5588100ull
+#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5588180ull
+#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_8_SPECIAL_BASE 0x5588E80ull
+#define NIC3_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_8_SPECIAL_SECTION 0x1800
+#define NIC3_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5589000ull
+#define NIC3_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5589080ull
+#define NIC3_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5589100ull
+#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5589180ull
+#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_9_SPECIAL_BASE 0x5589E80ull
+#define NIC3_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_9_SPECIAL_SECTION 0x1800
+#define NIC3_UMR0_10_UNSECURE_DOORBELL0_BASE 0x558A000ull
+#define NIC3_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_10_UNSECURE_DOORBELL1_BASE 0x558A080ull
+#define NIC3_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x558A100ull
+#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x558A180ull
+#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_10_SPECIAL_BASE 0x558AE80ull
+#define NIC3_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_10_SPECIAL_SECTION 0x1800
+#define NIC3_UMR0_11_UNSECURE_DOORBELL0_BASE 0x558B000ull
+#define NIC3_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_11_UNSECURE_DOORBELL1_BASE 0x558B080ull
+#define NIC3_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x558B100ull
+#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x558B180ull
+#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_11_SPECIAL_BASE 0x558BE80ull
+#define NIC3_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_11_SPECIAL_SECTION 0x1800
+#define NIC3_UMR0_12_UNSECURE_DOORBELL0_BASE 0x558C000ull
+#define NIC3_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_12_UNSECURE_DOORBELL1_BASE 0x558C080ull
+#define NIC3_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x558C100ull
+#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x558C180ull
+#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_12_SPECIAL_BASE 0x558CE80ull
+#define NIC3_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_12_SPECIAL_SECTION 0x1800
+#define NIC3_UMR0_13_UNSECURE_DOORBELL0_BASE 0x558D000ull
+#define NIC3_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_13_UNSECURE_DOORBELL1_BASE 0x558D080ull
+#define NIC3_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x558D100ull
+#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x558D180ull
+#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_13_SPECIAL_BASE 0x558DE80ull
+#define NIC3_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_13_SPECIAL_SECTION 0x1800
+#define NIC3_UMR0_14_UNSECURE_DOORBELL0_BASE 0x558E000ull
+#define NIC3_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR0_14_UNSECURE_DOORBELL1_BASE 0x558E080ull
+#define NIC3_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x558E100ull
+#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x558E180ull
+#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR0_14_SPECIAL_BASE 0x558EE80ull
+#define NIC3_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_14_SPECIAL_SECTION 0x1180
+#define NIC3_QM_DCCM0_BASE 0x5590000ull
+#define NIC3_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC3_QM_DCCM0_SECTION 0x8000
+#define NIC3_QM_ARC_AUX0_BASE 0x5598000ull
+#define NIC3_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC3_QM_ARC_AUX0_SECTION 0xE800
+#define NIC3_QM_ARC_AUX0_SPECIAL_BASE 0x5598E80ull
+#define NIC3_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define NIC3_QM0_BASE 0x559A000ull
+#define NIC3_QM0_MAX_OFFSET 0x1000
+#define NIC3_QM0_SECTION 0x9000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x559A900ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x559A908ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x559A910ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x559A918ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x559A920ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x559A928ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x559A930ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x559A938ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x559A940ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x559A948ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x559A950ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x559A958ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x559A960ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x559A968ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x559A970ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x559A978ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC3_QM0_AXUSER_SECURED_BASE 0x559AB00ull
+#define NIC3_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC3_QM0_AXUSER_SECURED_SECTION 0x8000
+#define NIC3_QM0_AXUSER_NONSECURED_BASE 0x559AB80ull
+#define NIC3_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC3_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC3_QM0_DBG_HBW_BASE 0x559AC00ull
+#define NIC3_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC3_QM0_DBG_HBW_SECTION 0x8000
+#define NIC3_QM0_DBG_LBW_BASE 0x559AC80ull
+#define NIC3_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC3_QM0_DBG_LBW_SECTION 0x1000
+#define NIC3_QM0_CGM_BASE 0x559AD80ull
+#define NIC3_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC3_QM0_CGM_SECTION 0x1000
+#define NIC3_QM0_SPECIAL_BASE 0x559AE80ull
+#define NIC3_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_QM0_SPECIAL_SECTION 0x4180
+#define NIC3_QPC0_BASE 0x559F000ull
+#define NIC3_QPC0_MAX_OFFSET 0x1000
+#define NIC3_QPC0_SECTION 0x7200
+#define NIC3_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x559F720ull
+#define NIC3_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x559F728ull
+#define NIC3_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x559F730ull
+#define NIC3_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x559F738ull
+#define NIC3_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x559F740ull
+#define NIC3_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x559F748ull
+#define NIC3_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x559F750ull
+#define NIC3_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x559F758ull
+#define NIC3_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x559F760ull
+#define NIC3_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x559F768ull
+#define NIC3_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x559F770ull
+#define NIC3_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x559F778ull
+#define NIC3_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x559F780ull
+#define NIC3_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x559F788ull
+#define NIC3_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x559F790ull
+#define NIC3_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x559F798ull
+#define NIC3_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x559F7A0ull
+#define NIC3_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x559F7A8ull
+#define NIC3_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x559F7B0ull
+#define NIC3_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x559F7B8ull
+#define NIC3_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x559F7C0ull
+#define NIC3_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x559F7C8ull
+#define NIC3_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x559F7D0ull
+#define NIC3_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x559F7D8ull
+#define NIC3_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x559F7E0ull
+#define NIC3_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x559F7E8ull
+#define NIC3_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x559F7F0ull
+#define NIC3_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x559F7F8ull
+#define NIC3_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x559F800ull
+#define NIC3_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x559F808ull
+#define NIC3_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x559F810ull
+#define NIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x559F818ull
+#define NIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC3_QPC0_AXUSER_CONG_QUE_BASE 0x559FB80ull
+#define NIC3_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC3_QPC0_AXUSER_RXWQE_BASE 0x559FBE0ull
+#define NIC3_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define NIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x559FC40ull
+#define NIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC3_QPC0_AXUSER_DB_FIFO_BASE 0x559FCA0ull
+#define NIC3_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x559FD00ull
+#define NIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC3_QPC0_AXUSER_ERR_FIFO_BASE 0x559FD60ull
+#define NIC3_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC3_QPC0_AXUSER_QPC_RESP_BASE 0x559FDC0ull
+#define NIC3_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC3_QPC0_AXUSER_QPC_REQ_BASE 0x559FE20ull
+#define NIC3_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC3_QPC0_SPECIAL_BASE 0x559FE80ull
+#define NIC3_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_QPC0_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_0_UNSECURE_DOORBELL0_BASE 0x55A0000ull
+#define NIC3_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_0_UNSECURE_DOORBELL1_BASE 0x55A0080ull
+#define NIC3_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x55A0100ull
+#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x55A0180ull
+#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_0_SPECIAL_BASE 0x55A0E80ull
+#define NIC3_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_0_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_1_UNSECURE_DOORBELL0_BASE 0x55A1000ull
+#define NIC3_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_1_UNSECURE_DOORBELL1_BASE 0x55A1080ull
+#define NIC3_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x55A1100ull
+#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x55A1180ull
+#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_1_SPECIAL_BASE 0x55A1E80ull
+#define NIC3_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_1_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_2_UNSECURE_DOORBELL0_BASE 0x55A2000ull
+#define NIC3_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_2_UNSECURE_DOORBELL1_BASE 0x55A2080ull
+#define NIC3_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x55A2100ull
+#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x55A2180ull
+#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_2_SPECIAL_BASE 0x55A2E80ull
+#define NIC3_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_2_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_3_UNSECURE_DOORBELL0_BASE 0x55A3000ull
+#define NIC3_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_3_UNSECURE_DOORBELL1_BASE 0x55A3080ull
+#define NIC3_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x55A3100ull
+#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x55A3180ull
+#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_3_SPECIAL_BASE 0x55A3E80ull
+#define NIC3_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_3_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_4_UNSECURE_DOORBELL0_BASE 0x55A4000ull
+#define NIC3_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_4_UNSECURE_DOORBELL1_BASE 0x55A4080ull
+#define NIC3_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x55A4100ull
+#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x55A4180ull
+#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_4_SPECIAL_BASE 0x55A4E80ull
+#define NIC3_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_4_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_5_UNSECURE_DOORBELL0_BASE 0x55A5000ull
+#define NIC3_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_5_UNSECURE_DOORBELL1_BASE 0x55A5080ull
+#define NIC3_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x55A5100ull
+#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x55A5180ull
+#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_5_SPECIAL_BASE 0x55A5E80ull
+#define NIC3_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_5_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_6_UNSECURE_DOORBELL0_BASE 0x55A6000ull
+#define NIC3_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_6_UNSECURE_DOORBELL1_BASE 0x55A6080ull
+#define NIC3_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x55A6100ull
+#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x55A6180ull
+#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_6_SPECIAL_BASE 0x55A6E80ull
+#define NIC3_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_6_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_7_UNSECURE_DOORBELL0_BASE 0x55A7000ull
+#define NIC3_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_7_UNSECURE_DOORBELL1_BASE 0x55A7080ull
+#define NIC3_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x55A7100ull
+#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x55A7180ull
+#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_7_SPECIAL_BASE 0x55A7E80ull
+#define NIC3_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_7_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_8_UNSECURE_DOORBELL0_BASE 0x55A8000ull
+#define NIC3_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_8_UNSECURE_DOORBELL1_BASE 0x55A8080ull
+#define NIC3_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x55A8100ull
+#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x55A8180ull
+#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_8_SPECIAL_BASE 0x55A8E80ull
+#define NIC3_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_8_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_9_UNSECURE_DOORBELL0_BASE 0x55A9000ull
+#define NIC3_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_9_UNSECURE_DOORBELL1_BASE 0x55A9080ull
+#define NIC3_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x55A9100ull
+#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x55A9180ull
+#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_9_SPECIAL_BASE 0x55A9E80ull
+#define NIC3_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_9_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_10_UNSECURE_DOORBELL0_BASE 0x55AA000ull
+#define NIC3_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_10_UNSECURE_DOORBELL1_BASE 0x55AA080ull
+#define NIC3_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x55AA100ull
+#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x55AA180ull
+#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_10_SPECIAL_BASE 0x55AAE80ull
+#define NIC3_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_10_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_11_UNSECURE_DOORBELL0_BASE 0x55AB000ull
+#define NIC3_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_11_UNSECURE_DOORBELL1_BASE 0x55AB080ull
+#define NIC3_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x55AB100ull
+#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x55AB180ull
+#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_11_SPECIAL_BASE 0x55ABE80ull
+#define NIC3_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_11_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_12_UNSECURE_DOORBELL0_BASE 0x55AC000ull
+#define NIC3_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_12_UNSECURE_DOORBELL1_BASE 0x55AC080ull
+#define NIC3_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x55AC100ull
+#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x55AC180ull
+#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_12_SPECIAL_BASE 0x55ACE80ull
+#define NIC3_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_12_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_13_UNSECURE_DOORBELL0_BASE 0x55AD000ull
+#define NIC3_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_13_UNSECURE_DOORBELL1_BASE 0x55AD080ull
+#define NIC3_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x55AD100ull
+#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x55AD180ull
+#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_13_SPECIAL_BASE 0x55ADE80ull
+#define NIC3_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_13_SPECIAL_SECTION 0x1800
+#define NIC3_UMR1_14_UNSECURE_DOORBELL0_BASE 0x55AE000ull
+#define NIC3_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC3_UMR1_14_UNSECURE_DOORBELL1_BASE 0x55AE080ull
+#define NIC3_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x55AE100ull
+#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x55AE180ull
+#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC3_UMR1_14_SPECIAL_BASE 0x55AEE80ull
+#define NIC3_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_14_SPECIAL_SECTION 0x1180
+#define NIC3_QM_DCCM1_BASE 0x55B0000ull
+#define NIC3_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC3_QM_DCCM1_SECTION 0x8000
+#define NIC3_QM_ARC_AUX1_BASE 0x55B8000ull
+#define NIC3_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC3_QM_ARC_AUX1_SECTION 0xE800
+#define NIC3_QM_ARC_AUX1_SPECIAL_BASE 0x55B8E80ull
+#define NIC3_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define NIC3_QM1_BASE 0x55BA000ull
+#define NIC3_QM1_MAX_OFFSET 0x1000
+#define NIC3_QM1_SECTION 0x9000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x55BA900ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x55BA908ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x55BA910ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x55BA918ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x55BA920ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x55BA928ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x55BA930ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x55BA938ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x55BA940ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x55BA948ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x55BA950ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x55BA958ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x55BA960ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x55BA968ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x55BA970ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x55BA978ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC3_QM1_AXUSER_SECURED_BASE 0x55BAB00ull
+#define NIC3_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC3_QM1_AXUSER_SECURED_SECTION 0x8000
+#define NIC3_QM1_AXUSER_NONSECURED_BASE 0x55BAB80ull
+#define NIC3_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC3_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC3_QM1_DBG_HBW_BASE 0x55BAC00ull
+#define NIC3_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC3_QM1_DBG_HBW_SECTION 0x8000
+#define NIC3_QM1_DBG_LBW_BASE 0x55BAC80ull
+#define NIC3_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC3_QM1_DBG_LBW_SECTION 0x1000
+#define NIC3_QM1_CGM_BASE 0x55BAD80ull
+#define NIC3_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC3_QM1_CGM_SECTION 0x1000
+#define NIC3_QM1_SPECIAL_BASE 0x55BAE80ull
+#define NIC3_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_QM1_SPECIAL_SECTION 0x4180
+#define NIC3_QPC1_BASE 0x55BF000ull
+#define NIC3_QPC1_MAX_OFFSET 0x1000
+#define NIC3_QPC1_SECTION 0x7200
+#define NIC3_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x55BF720ull
+#define NIC3_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x55BF728ull
+#define NIC3_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x55BF730ull
+#define NIC3_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x55BF738ull
+#define NIC3_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x55BF740ull
+#define NIC3_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x55BF748ull
+#define NIC3_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x55BF750ull
+#define NIC3_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x55BF758ull
+#define NIC3_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x55BF760ull
+#define NIC3_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x55BF768ull
+#define NIC3_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x55BF770ull
+#define NIC3_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x55BF778ull
+#define NIC3_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x55BF780ull
+#define NIC3_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x55BF788ull
+#define NIC3_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x55BF790ull
+#define NIC3_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x55BF798ull
+#define NIC3_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x55BF7A0ull
+#define NIC3_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x55BF7A8ull
+#define NIC3_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x55BF7B0ull
+#define NIC3_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x55BF7B8ull
+#define NIC3_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x55BF7C0ull
+#define NIC3_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x55BF7C8ull
+#define NIC3_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x55BF7D0ull
+#define NIC3_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x55BF7D8ull
+#define NIC3_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x55BF7E0ull
+#define NIC3_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x55BF7E8ull
+#define NIC3_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x55BF7F0ull
+#define NIC3_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x55BF7F8ull
+#define NIC3_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x55BF800ull
+#define NIC3_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x55BF808ull
+#define NIC3_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x55BF810ull
+#define NIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x55BF818ull
+#define NIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC3_QPC1_AXUSER_CONG_QUE_BASE 0x55BFB80ull
+#define NIC3_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC3_QPC1_AXUSER_RXWQE_BASE 0x55BFBE0ull
+#define NIC3_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define NIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x55BFC40ull
+#define NIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC3_QPC1_AXUSER_DB_FIFO_BASE 0x55BFCA0ull
+#define NIC3_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x55BFD00ull
+#define NIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC3_QPC1_AXUSER_ERR_FIFO_BASE 0x55BFD60ull
+#define NIC3_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC3_QPC1_AXUSER_QPC_RESP_BASE 0x55BFDC0ull
+#define NIC3_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC3_QPC1_AXUSER_QPC_REQ_BASE 0x55BFE20ull
+#define NIC3_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC3_QPC1_SPECIAL_BASE 0x55BFE80ull
+#define NIC3_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_QPC1_SPECIAL_SECTION 0x8180
+#define NIC3_TMR_BASE 0x55C8000ull
+#define NIC3_TMR_MAX_OFFSET 0x1000
+#define NIC3_TMR_SECTION 0xD600
+#define NIC3_TMR_AXUSER_TMR_FREE_LIST_BASE 0x55C8D60ull
+#define NIC3_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC3_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define NIC3_TMR_AXUSER_TMR_FIFO_BASE 0x55C8DC0ull
+#define NIC3_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC3_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define NIC3_TMR_AXUSER_TMR_FSM_BASE 0x55C8E20ull
+#define NIC3_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC3_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define NIC3_TMR_SPECIAL_BASE 0x55C8E80ull
+#define NIC3_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_TMR_SPECIAL_SECTION 0x1800
+#define NIC3_RXB_CORE_BASE 0x55C9000ull
+#define NIC3_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC3_RXB_CORE_SECTION 0x6100
+#define NIC3_RXB_CORE_SCT_AWUSER_BASE 0x55C9610ull
+#define NIC3_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC3_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define NIC3_RXB_CORE_SPECIAL_BASE 0x55C9E80ull
+#define NIC3_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_RXB_CORE_SPECIAL_SECTION 0x1800
+#define NIC3_RXE0_BASE 0x55CA000ull
+#define NIC3_RXE0_MAX_OFFSET 0x1000
+#define NIC3_RXE0_SECTION 0x9000
+#define NIC3_RXE0_WQE_ARUSER_BASE 0x55CA900ull
+#define NIC3_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC3_RXE0_WQE_ARUSER_SECTION 0x5800
+#define NIC3_RXE0_SPECIAL_BASE 0x55CAE80ull
+#define NIC3_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_RXE0_SPECIAL_SECTION 0x1800
+#define NIC3_RXE1_BASE 0x55CB000ull
+#define NIC3_RXE1_MAX_OFFSET 0x1000
+#define NIC3_RXE1_SECTION 0x9000
+#define NIC3_RXE1_WQE_ARUSER_BASE 0x55CB900ull
+#define NIC3_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC3_RXE1_WQE_ARUSER_SECTION 0x5800
+#define NIC3_RXE1_SPECIAL_BASE 0x55CBE80ull
+#define NIC3_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_RXE1_SPECIAL_SECTION 0x1800
+#define NIC3_RXE0_AXUSER_AXUSER_CQ0_BASE 0x55CC000ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ1_BASE 0x55CC050ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ2_BASE 0x55CC0A0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ3_BASE 0x55CC0F0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ4_BASE 0x55CC140ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ5_BASE 0x55CC190ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ6_BASE 0x55CC1E0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ7_BASE 0x55CC230ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ8_BASE 0x55CC280ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ9_BASE 0x55CC2D0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ10_BASE 0x55CC320ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ11_BASE 0x55CC370ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ12_BASE 0x55CC3C0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ13_BASE 0x55CC410ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ14_BASE 0x55CC460ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ15_BASE 0x55CC4B0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ16_BASE 0x55CC500ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ17_BASE 0x55CC550ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ18_BASE 0x55CC5A0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ19_BASE 0x55CC5F0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ20_BASE 0x55CC640ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ21_BASE 0x55CC690ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ22_BASE 0x55CC6E0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ23_BASE 0x55CC730ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ24_BASE 0x55CC780ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ25_BASE 0x55CC7D0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ26_BASE 0x55CC820ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ27_BASE 0x55CC870ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ28_BASE 0x55CC8C0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ29_BASE 0x55CC910ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ30_BASE 0x55CC960ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ31_BASE 0x55CC9B0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC3_RXE0_AXUSER_SPECIAL_BASE 0x55CCE80ull
+#define NIC3_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define NIC3_RXE1_AXUSER_AXUSER_CQ0_BASE 0x55CD000ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ1_BASE 0x55CD050ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ2_BASE 0x55CD0A0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ3_BASE 0x55CD0F0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ4_BASE 0x55CD140ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ5_BASE 0x55CD190ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ6_BASE 0x55CD1E0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ7_BASE 0x55CD230ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ8_BASE 0x55CD280ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ9_BASE 0x55CD2D0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ10_BASE 0x55CD320ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ11_BASE 0x55CD370ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ12_BASE 0x55CD3C0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ13_BASE 0x55CD410ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ14_BASE 0x55CD460ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ15_BASE 0x55CD4B0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ16_BASE 0x55CD500ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ17_BASE 0x55CD550ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ18_BASE 0x55CD5A0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ19_BASE 0x55CD5F0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ20_BASE 0x55CD640ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ21_BASE 0x55CD690ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ22_BASE 0x55CD6E0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ23_BASE 0x55CD730ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ24_BASE 0x55CD780ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ25_BASE 0x55CD7D0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ26_BASE 0x55CD820ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ27_BASE 0x55CD870ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ28_BASE 0x55CD8C0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ29_BASE 0x55CD910ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ30_BASE 0x55CD960ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ31_BASE 0x55CD9B0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC3_RXE1_AXUSER_SPECIAL_BASE 0x55CDE80ull
+#define NIC3_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define NIC3_TXS0_BASE 0x55D0000ull
+#define NIC3_TXS0_MAX_OFFSET 0x1000
+#define NIC3_TXS0_SECTION 0xE800
+#define NIC3_TXS0_SPECIAL_BASE 0x55D0E80ull
+#define NIC3_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_TXS0_SPECIAL_SECTION 0x1800
+#define NIC3_TXS1_BASE 0x55D1000ull
+#define NIC3_TXS1_MAX_OFFSET 0x1000
+#define NIC3_TXS1_SECTION 0xE800
+#define NIC3_TXS1_SPECIAL_BASE 0x55D1E80ull
+#define NIC3_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_TXS1_SPECIAL_SECTION 0x1800
+#define NIC3_TXE0_BASE 0x55D2000ull
+#define NIC3_TXE0_MAX_OFFSET 0x1000
+#define NIC3_TXE0_SECTION 0xE800
+#define NIC3_TXE0_SPECIAL_BASE 0x55D2E80ull
+#define NIC3_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_TXE0_SPECIAL_SECTION 0x1800
+#define NIC3_TXE1_BASE 0x55D3000ull
+#define NIC3_TXE1_MAX_OFFSET 0x1000
+#define NIC3_TXE1_SECTION 0xE800
+#define NIC3_TXE1_SPECIAL_BASE 0x55D3E80ull
+#define NIC3_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_TXE1_SPECIAL_SECTION 0x1800
+#define NIC3_TXB_BASE 0x55D4000ull
+#define NIC3_TXB_MAX_OFFSET 0x1000
+#define NIC3_TXB_SECTION 0xE800
+#define NIC3_TXB_SPECIAL_BASE 0x55D4E80ull
+#define NIC3_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_TXB_SPECIAL_SECTION 0x1800
+#define NIC3_MSTR_IF_RR_SHRD_HBW_BASE 0x55D5000ull
+#define NIC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define NIC3_MSTR_IF_RR_PRVT_HBW_BASE 0x55D5200ull
+#define NIC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define NIC3_MSTR_IF_RR_SHRD_LBW_BASE 0x55D5400ull
+#define NIC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define NIC3_MSTR_IF_RR_PRVT_LBW_BASE 0x55D5600ull
+#define NIC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define NIC3_MSTR_IF_E2E_CRDT_BASE 0x55D5800ull
+#define NIC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define NIC3_MSTR_IF_AXUSER_BASE 0x55D5A80ull
+#define NIC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC3_MSTR_IF_AXUSER_SECTION 0x8000
+#define NIC3_MSTR_IF_DBG_HBW_BASE 0x55D5B00ull
+#define NIC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define NIC3_MSTR_IF_DBG_LBW_BASE 0x55D5B80ull
+#define NIC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define NIC3_MSTR_IF_CORE_HBW_BASE 0x55D5C00ull
+#define NIC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define NIC3_MSTR_IF_CORE_LBW_BASE 0x55D5D80ull
+#define NIC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define NIC3_MSTR_IF_SPECIAL_BASE 0x55D5E80ull
+#define NIC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_MSTR_IF_SPECIAL_SECTION 0x1800
+#define NIC3_TX_AXUSER_BASE 0x55D6000ull
+#define NIC3_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC3_TX_AXUSER_SECTION 0x2000
+#define NIC3_SERDES0_BASE 0x55D8000ull
+#define NIC3_SERDES0_MAX_OFFSET 0x3E40
+#define NIC3_SERDES0_SECTION 0x4000
+#define NIC3_SERDES1_BASE 0x55DC000ull
+#define NIC3_SERDES1_MAX_OFFSET 0x3E40
+#define NIC3_SERDES1_SECTION 0x4000
+#define NIC3_PHY_BASE 0x55E0000ull
+#define NIC3_PHY_MAX_OFFSET 0x1000
+#define NIC3_PHY_SECTION 0xE800
+#define NIC3_PHY_SPECIAL_BASE 0x55E0E80ull
+#define NIC3_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_PHY_SPECIAL_SECTION 0x7180
+#define PRT3_MAC_AUX_BASE 0x55E8000ull
+#define PRT3_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT3_MAC_AUX_SECTION 0xE800
+#define PRT3_MAC_AUX_SPECIAL_BASE 0x55E8E80ull
+#define PRT3_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT3_MAC_AUX_SPECIAL_SECTION 0x1800
+#define PRT3_MAC_CORE_BASE 0x55E9000ull
+#define PRT3_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT3_MAC_CORE_SECTION 0xE800
+#define PRT3_MAC_CORE_SPECIAL_BASE 0x55E9E80ull
+#define PRT3_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT3_MAC_CORE_SPECIAL_SECTION 0x1800
+#define NIC3_MAC_RS_FEC_BASE 0x55EA000ull
+#define NIC3_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC3_MAC_RS_FEC_SECTION 0x1000
+#define NIC3_MAC_GLOB_STAT_CONTROL_REG_BASE 0x55EB000ull
+#define NIC3_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC3_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define NIC3_MAC_GLOB_STAT_RX0_BASE 0x55EB100ull
+#define NIC3_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC3_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define NIC3_MAC_GLOB_STAT_RX1_BASE 0x55EB18Cull
+#define NIC3_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC3_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define NIC3_MAC_GLOB_STAT_RX2_BASE 0x55EB218ull
+#define NIC3_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC3_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define NIC3_MAC_GLOB_STAT_RX3_BASE 0x55EB2A4ull
+#define NIC3_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC3_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define NIC3_MAC_GLOB_STAT_TX0_BASE 0x55EB330ull
+#define NIC3_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC3_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define NIC3_MAC_GLOB_STAT_TX1_BASE 0x55EB398ull
+#define NIC3_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC3_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define NIC3_MAC_GLOB_STAT_TX2_BASE 0x55EB400ull
+#define NIC3_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC3_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define NIC3_MAC_GLOB_STAT_TX3_BASE 0x55EB468ull
+#define NIC3_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC3_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define NIC3_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x55EB800ull
+#define NIC3_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC3_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define NIC3_MAC_CH0_MAC_PCS_BASE 0x55EC000ull
+#define NIC3_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC3_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define NIC3_MAC_CH0_MAC_128_BASE 0x55EC400ull
+#define NIC3_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC3_MAC_CH0_MAC_128_SECTION 0x4000
+#define NIC3_MAC_CH0_MAC_AN_BASE 0x55EC800ull
+#define NIC3_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC3_MAC_CH0_MAC_AN_SECTION 0x8000
+#define NIC3_MAC_CH1_MAC_PCS_BASE 0x55ED000ull
+#define NIC3_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC3_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define NIC3_MAC_CH1_MAC_128_BASE 0x55ED400ull
+#define NIC3_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC3_MAC_CH1_MAC_128_SECTION 0x4000
+#define NIC3_MAC_CH1_MAC_AN_BASE 0x55ED800ull
+#define NIC3_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC3_MAC_CH1_MAC_AN_SECTION 0x8000
+#define NIC3_MAC_CH2_MAC_PCS_BASE 0x55EE000ull
+#define NIC3_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC3_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define NIC3_MAC_CH2_MAC_128_BASE 0x55EE400ull
+#define NIC3_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC3_MAC_CH2_MAC_128_SECTION 0x4000
+#define NIC3_MAC_CH2_MAC_AN_BASE 0x55EE800ull
+#define NIC3_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC3_MAC_CH2_MAC_AN_SECTION 0x8000
+#define NIC3_MAC_CH3_MAC_PCS_BASE 0x55EF000ull
+#define NIC3_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC3_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define NIC3_MAC_CH3_MAC_128_BASE 0x55EF400ull
+#define NIC3_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC3_MAC_CH3_MAC_128_SECTION 0x4000
+#define NIC3_MAC_CH3_MAC_AN_BASE 0x55EF800ull
+#define NIC3_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC3_MAC_CH3_MAC_AN_SECTION 0x10800
+#define NIC4_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5600000ull
+#define NIC4_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5600080ull
+#define NIC4_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5600100ull
+#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5600180ull
+#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_0_SPECIAL_BASE 0x5600E80ull
+#define NIC4_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_0_SPECIAL_SECTION 0x1800
+#define NIC4_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5601000ull
+#define NIC4_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5601080ull
+#define NIC4_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5601100ull
+#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5601180ull
+#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_1_SPECIAL_BASE 0x5601E80ull
+#define NIC4_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_1_SPECIAL_SECTION 0x1800
+#define NIC4_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5602000ull
+#define NIC4_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5602080ull
+#define NIC4_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5602100ull
+#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5602180ull
+#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_2_SPECIAL_BASE 0x5602E80ull
+#define NIC4_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_2_SPECIAL_SECTION 0x1800
+#define NIC4_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5603000ull
+#define NIC4_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5603080ull
+#define NIC4_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5603100ull
+#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5603180ull
+#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_3_SPECIAL_BASE 0x5603E80ull
+#define NIC4_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_3_SPECIAL_SECTION 0x1800
+#define NIC4_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5604000ull
+#define NIC4_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5604080ull
+#define NIC4_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5604100ull
+#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5604180ull
+#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_4_SPECIAL_BASE 0x5604E80ull
+#define NIC4_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_4_SPECIAL_SECTION 0x1800
+#define NIC4_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5605000ull
+#define NIC4_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5605080ull
+#define NIC4_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5605100ull
+#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5605180ull
+#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_5_SPECIAL_BASE 0x5605E80ull
+#define NIC4_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_5_SPECIAL_SECTION 0x1800
+#define NIC4_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5606000ull
+#define NIC4_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5606080ull
+#define NIC4_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5606100ull
+#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5606180ull
+#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_6_SPECIAL_BASE 0x5606E80ull
+#define NIC4_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_6_SPECIAL_SECTION 0x1800
+#define NIC4_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5607000ull
+#define NIC4_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5607080ull
+#define NIC4_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5607100ull
+#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5607180ull
+#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_7_SPECIAL_BASE 0x5607E80ull
+#define NIC4_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_7_SPECIAL_SECTION 0x1800
+#define NIC4_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5608000ull
+#define NIC4_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5608080ull
+#define NIC4_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5608100ull
+#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5608180ull
+#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_8_SPECIAL_BASE 0x5608E80ull
+#define NIC4_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_8_SPECIAL_SECTION 0x1800
+#define NIC4_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5609000ull
+#define NIC4_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5609080ull
+#define NIC4_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5609100ull
+#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5609180ull
+#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_9_SPECIAL_BASE 0x5609E80ull
+#define NIC4_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_9_SPECIAL_SECTION 0x1800
+#define NIC4_UMR0_10_UNSECURE_DOORBELL0_BASE 0x560A000ull
+#define NIC4_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_10_UNSECURE_DOORBELL1_BASE 0x560A080ull
+#define NIC4_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x560A100ull
+#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x560A180ull
+#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_10_SPECIAL_BASE 0x560AE80ull
+#define NIC4_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_10_SPECIAL_SECTION 0x1800
+#define NIC4_UMR0_11_UNSECURE_DOORBELL0_BASE 0x560B000ull
+#define NIC4_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_11_UNSECURE_DOORBELL1_BASE 0x560B080ull
+#define NIC4_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x560B100ull
+#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x560B180ull
+#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_11_SPECIAL_BASE 0x560BE80ull
+#define NIC4_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_11_SPECIAL_SECTION 0x1800
+#define NIC4_UMR0_12_UNSECURE_DOORBELL0_BASE 0x560C000ull
+#define NIC4_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_12_UNSECURE_DOORBELL1_BASE 0x560C080ull
+#define NIC4_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x560C100ull
+#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x560C180ull
+#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_12_SPECIAL_BASE 0x560CE80ull
+#define NIC4_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_12_SPECIAL_SECTION 0x1800
+#define NIC4_UMR0_13_UNSECURE_DOORBELL0_BASE 0x560D000ull
+#define NIC4_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_13_UNSECURE_DOORBELL1_BASE 0x560D080ull
+#define NIC4_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x560D100ull
+#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x560D180ull
+#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_13_SPECIAL_BASE 0x560DE80ull
+#define NIC4_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_13_SPECIAL_SECTION 0x1800
+#define NIC4_UMR0_14_UNSECURE_DOORBELL0_BASE 0x560E000ull
+#define NIC4_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR0_14_UNSECURE_DOORBELL1_BASE 0x560E080ull
+#define NIC4_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x560E100ull
+#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x560E180ull
+#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR0_14_SPECIAL_BASE 0x560EE80ull
+#define NIC4_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_14_SPECIAL_SECTION 0x1180
+#define NIC4_QM_DCCM0_BASE 0x5610000ull
+#define NIC4_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC4_QM_DCCM0_SECTION 0x8000
+#define NIC4_QM_ARC_AUX0_BASE 0x5618000ull
+#define NIC4_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC4_QM_ARC_AUX0_SECTION 0xE800
+#define NIC4_QM_ARC_AUX0_SPECIAL_BASE 0x5618E80ull
+#define NIC4_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define NIC4_QM0_BASE 0x561A000ull
+#define NIC4_QM0_MAX_OFFSET 0x1000
+#define NIC4_QM0_SECTION 0x9000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x561A900ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x561A908ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x561A910ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x561A918ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x561A920ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x561A928ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x561A930ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x561A938ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x561A940ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x561A948ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x561A950ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x561A958ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x561A960ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x561A968ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x561A970ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x561A978ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC4_QM0_AXUSER_SECURED_BASE 0x561AB00ull
+#define NIC4_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC4_QM0_AXUSER_SECURED_SECTION 0x8000
+#define NIC4_QM0_AXUSER_NONSECURED_BASE 0x561AB80ull
+#define NIC4_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC4_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC4_QM0_DBG_HBW_BASE 0x561AC00ull
+#define NIC4_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC4_QM0_DBG_HBW_SECTION 0x8000
+#define NIC4_QM0_DBG_LBW_BASE 0x561AC80ull
+#define NIC4_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC4_QM0_DBG_LBW_SECTION 0x1000
+#define NIC4_QM0_CGM_BASE 0x561AD80ull
+#define NIC4_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC4_QM0_CGM_SECTION 0x1000
+#define NIC4_QM0_SPECIAL_BASE 0x561AE80ull
+#define NIC4_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_QM0_SPECIAL_SECTION 0x4180
+#define NIC4_QPC0_BASE 0x561F000ull
+#define NIC4_QPC0_MAX_OFFSET 0x1000
+#define NIC4_QPC0_SECTION 0x7200
+#define NIC4_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x561F720ull
+#define NIC4_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x561F728ull
+#define NIC4_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x561F730ull
+#define NIC4_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x561F738ull
+#define NIC4_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x561F740ull
+#define NIC4_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x561F748ull
+#define NIC4_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x561F750ull
+#define NIC4_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x561F758ull
+#define NIC4_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x561F760ull
+#define NIC4_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x561F768ull
+#define NIC4_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x561F770ull
+#define NIC4_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x561F778ull
+#define NIC4_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x561F780ull
+#define NIC4_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x561F788ull
+#define NIC4_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x561F790ull
+#define NIC4_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x561F798ull
+#define NIC4_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x561F7A0ull
+#define NIC4_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x561F7A8ull
+#define NIC4_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x561F7B0ull
+#define NIC4_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x561F7B8ull
+#define NIC4_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x561F7C0ull
+#define NIC4_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x561F7C8ull
+#define NIC4_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x561F7D0ull
+#define NIC4_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x561F7D8ull
+#define NIC4_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x561F7E0ull
+#define NIC4_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x561F7E8ull
+#define NIC4_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x561F7F0ull
+#define NIC4_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x561F7F8ull
+#define NIC4_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x561F800ull
+#define NIC4_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x561F808ull
+#define NIC4_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x561F810ull
+#define NIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x561F818ull
+#define NIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC4_QPC0_AXUSER_CONG_QUE_BASE 0x561FB80ull
+#define NIC4_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC4_QPC0_AXUSER_RXWQE_BASE 0x561FBE0ull
+#define NIC4_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define NIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x561FC40ull
+#define NIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC4_QPC0_AXUSER_DB_FIFO_BASE 0x561FCA0ull
+#define NIC4_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x561FD00ull
+#define NIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC4_QPC0_AXUSER_ERR_FIFO_BASE 0x561FD60ull
+#define NIC4_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC4_QPC0_AXUSER_QPC_RESP_BASE 0x561FDC0ull
+#define NIC4_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC4_QPC0_AXUSER_QPC_REQ_BASE 0x561FE20ull
+#define NIC4_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC4_QPC0_SPECIAL_BASE 0x561FE80ull
+#define NIC4_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_QPC0_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5620000ull
+#define NIC4_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5620080ull
+#define NIC4_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5620100ull
+#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5620180ull
+#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_0_SPECIAL_BASE 0x5620E80ull
+#define NIC4_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_0_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5621000ull
+#define NIC4_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5621080ull
+#define NIC4_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5621100ull
+#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5621180ull
+#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_1_SPECIAL_BASE 0x5621E80ull
+#define NIC4_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_1_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5622000ull
+#define NIC4_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5622080ull
+#define NIC4_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5622100ull
+#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5622180ull
+#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_2_SPECIAL_BASE 0x5622E80ull
+#define NIC4_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_2_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5623000ull
+#define NIC4_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5623080ull
+#define NIC4_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5623100ull
+#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5623180ull
+#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_3_SPECIAL_BASE 0x5623E80ull
+#define NIC4_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_3_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5624000ull
+#define NIC4_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5624080ull
+#define NIC4_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5624100ull
+#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5624180ull
+#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_4_SPECIAL_BASE 0x5624E80ull
+#define NIC4_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_4_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5625000ull
+#define NIC4_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5625080ull
+#define NIC4_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5625100ull
+#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5625180ull
+#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_5_SPECIAL_BASE 0x5625E80ull
+#define NIC4_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_5_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5626000ull
+#define NIC4_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5626080ull
+#define NIC4_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5626100ull
+#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5626180ull
+#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_6_SPECIAL_BASE 0x5626E80ull
+#define NIC4_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_6_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5627000ull
+#define NIC4_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5627080ull
+#define NIC4_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5627100ull
+#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5627180ull
+#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_7_SPECIAL_BASE 0x5627E80ull
+#define NIC4_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_7_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5628000ull
+#define NIC4_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5628080ull
+#define NIC4_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5628100ull
+#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5628180ull
+#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_8_SPECIAL_BASE 0x5628E80ull
+#define NIC4_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_8_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5629000ull
+#define NIC4_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5629080ull
+#define NIC4_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5629100ull
+#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5629180ull
+#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_9_SPECIAL_BASE 0x5629E80ull
+#define NIC4_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_9_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_10_UNSECURE_DOORBELL0_BASE 0x562A000ull
+#define NIC4_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_10_UNSECURE_DOORBELL1_BASE 0x562A080ull
+#define NIC4_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x562A100ull
+#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x562A180ull
+#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_10_SPECIAL_BASE 0x562AE80ull
+#define NIC4_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_10_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_11_UNSECURE_DOORBELL0_BASE 0x562B000ull
+#define NIC4_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_11_UNSECURE_DOORBELL1_BASE 0x562B080ull
+#define NIC4_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x562B100ull
+#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x562B180ull
+#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_11_SPECIAL_BASE 0x562BE80ull
+#define NIC4_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_11_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_12_UNSECURE_DOORBELL0_BASE 0x562C000ull
+#define NIC4_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_12_UNSECURE_DOORBELL1_BASE 0x562C080ull
+#define NIC4_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x562C100ull
+#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x562C180ull
+#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_12_SPECIAL_BASE 0x562CE80ull
+#define NIC4_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_12_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_13_UNSECURE_DOORBELL0_BASE 0x562D000ull
+#define NIC4_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_13_UNSECURE_DOORBELL1_BASE 0x562D080ull
+#define NIC4_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x562D100ull
+#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x562D180ull
+#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_13_SPECIAL_BASE 0x562DE80ull
+#define NIC4_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_13_SPECIAL_SECTION 0x1800
+#define NIC4_UMR1_14_UNSECURE_DOORBELL0_BASE 0x562E000ull
+#define NIC4_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC4_UMR1_14_UNSECURE_DOORBELL1_BASE 0x562E080ull
+#define NIC4_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x562E100ull
+#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x562E180ull
+#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC4_UMR1_14_SPECIAL_BASE 0x562EE80ull
+#define NIC4_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_14_SPECIAL_SECTION 0x1180
+#define NIC4_QM_DCCM1_BASE 0x5630000ull
+#define NIC4_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC4_QM_DCCM1_SECTION 0x8000
+#define NIC4_QM_ARC_AUX1_BASE 0x5638000ull
+#define NIC4_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC4_QM_ARC_AUX1_SECTION 0xE800
+#define NIC4_QM_ARC_AUX1_SPECIAL_BASE 0x5638E80ull
+#define NIC4_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define NIC4_QM1_BASE 0x563A000ull
+#define NIC4_QM1_MAX_OFFSET 0x1000
+#define NIC4_QM1_SECTION 0x9000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x563A900ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x563A908ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x563A910ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x563A918ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x563A920ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x563A928ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x563A930ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x563A938ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x563A940ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x563A948ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x563A950ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x563A958ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x563A960ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x563A968ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x563A970ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x563A978ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC4_QM1_AXUSER_SECURED_BASE 0x563AB00ull
+#define NIC4_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC4_QM1_AXUSER_SECURED_SECTION 0x8000
+#define NIC4_QM1_AXUSER_NONSECURED_BASE 0x563AB80ull
+#define NIC4_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC4_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC4_QM1_DBG_HBW_BASE 0x563AC00ull
+#define NIC4_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC4_QM1_DBG_HBW_SECTION 0x8000
+#define NIC4_QM1_DBG_LBW_BASE 0x563AC80ull
+#define NIC4_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC4_QM1_DBG_LBW_SECTION 0x1000
+#define NIC4_QM1_CGM_BASE 0x563AD80ull
+#define NIC4_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC4_QM1_CGM_SECTION 0x1000
+#define NIC4_QM1_SPECIAL_BASE 0x563AE80ull
+#define NIC4_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_QM1_SPECIAL_SECTION 0x4180
+#define NIC4_QPC1_BASE 0x563F000ull
+#define NIC4_QPC1_MAX_OFFSET 0x1000
+#define NIC4_QPC1_SECTION 0x7200
+#define NIC4_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x563F720ull
+#define NIC4_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x563F728ull
+#define NIC4_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x563F730ull
+#define NIC4_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x563F738ull
+#define NIC4_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x563F740ull
+#define NIC4_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x563F748ull
+#define NIC4_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x563F750ull
+#define NIC4_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x563F758ull
+#define NIC4_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x563F760ull
+#define NIC4_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x563F768ull
+#define NIC4_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x563F770ull
+#define NIC4_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x563F778ull
+#define NIC4_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x563F780ull
+#define NIC4_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x563F788ull
+#define NIC4_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x563F790ull
+#define NIC4_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x563F798ull
+#define NIC4_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x563F7A0ull
+#define NIC4_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x563F7A8ull
+#define NIC4_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x563F7B0ull
+#define NIC4_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x563F7B8ull
+#define NIC4_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x563F7C0ull
+#define NIC4_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x563F7C8ull
+#define NIC4_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x563F7D0ull
+#define NIC4_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x563F7D8ull
+#define NIC4_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x563F7E0ull
+#define NIC4_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x563F7E8ull
+#define NIC4_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x563F7F0ull
+#define NIC4_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x563F7F8ull
+#define NIC4_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x563F800ull
+#define NIC4_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x563F808ull
+#define NIC4_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x563F810ull
+#define NIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x563F818ull
+#define NIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC4_QPC1_AXUSER_CONG_QUE_BASE 0x563FB80ull
+#define NIC4_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC4_QPC1_AXUSER_RXWQE_BASE 0x563FBE0ull
+#define NIC4_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define NIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x563FC40ull
+#define NIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC4_QPC1_AXUSER_DB_FIFO_BASE 0x563FCA0ull
+#define NIC4_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x563FD00ull
+#define NIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC4_QPC1_AXUSER_ERR_FIFO_BASE 0x563FD60ull
+#define NIC4_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC4_QPC1_AXUSER_QPC_RESP_BASE 0x563FDC0ull
+#define NIC4_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC4_QPC1_AXUSER_QPC_REQ_BASE 0x563FE20ull
+#define NIC4_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC4_QPC1_SPECIAL_BASE 0x563FE80ull
+#define NIC4_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_QPC1_SPECIAL_SECTION 0x8180
+#define NIC4_TMR_BASE 0x5648000ull
+#define NIC4_TMR_MAX_OFFSET 0x1000
+#define NIC4_TMR_SECTION 0xD600
+#define NIC4_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5648D60ull
+#define NIC4_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC4_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define NIC4_TMR_AXUSER_TMR_FIFO_BASE 0x5648DC0ull
+#define NIC4_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC4_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define NIC4_TMR_AXUSER_TMR_FSM_BASE 0x5648E20ull
+#define NIC4_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC4_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define NIC4_TMR_SPECIAL_BASE 0x5648E80ull
+#define NIC4_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_TMR_SPECIAL_SECTION 0x1800
+#define NIC4_RXB_CORE_BASE 0x5649000ull
+#define NIC4_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC4_RXB_CORE_SECTION 0x6100
+#define NIC4_RXB_CORE_SCT_AWUSER_BASE 0x5649610ull
+#define NIC4_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC4_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define NIC4_RXB_CORE_SPECIAL_BASE 0x5649E80ull
+#define NIC4_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_RXB_CORE_SPECIAL_SECTION 0x1800
+#define NIC4_RXE0_BASE 0x564A000ull
+#define NIC4_RXE0_MAX_OFFSET 0x1000
+#define NIC4_RXE0_SECTION 0x9000
+#define NIC4_RXE0_WQE_ARUSER_BASE 0x564A900ull
+#define NIC4_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC4_RXE0_WQE_ARUSER_SECTION 0x5800
+#define NIC4_RXE0_SPECIAL_BASE 0x564AE80ull
+#define NIC4_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_RXE0_SPECIAL_SECTION 0x1800
+#define NIC4_RXE1_BASE 0x564B000ull
+#define NIC4_RXE1_MAX_OFFSET 0x1000
+#define NIC4_RXE1_SECTION 0x9000
+#define NIC4_RXE1_WQE_ARUSER_BASE 0x564B900ull
+#define NIC4_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC4_RXE1_WQE_ARUSER_SECTION 0x5800
+#define NIC4_RXE1_SPECIAL_BASE 0x564BE80ull
+#define NIC4_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_RXE1_SPECIAL_SECTION 0x1800
+#define NIC4_RXE0_AXUSER_AXUSER_CQ0_BASE 0x564C000ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ1_BASE 0x564C050ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ2_BASE 0x564C0A0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ3_BASE 0x564C0F0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ4_BASE 0x564C140ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ5_BASE 0x564C190ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ6_BASE 0x564C1E0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ7_BASE 0x564C230ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ8_BASE 0x564C280ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ9_BASE 0x564C2D0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ10_BASE 0x564C320ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ11_BASE 0x564C370ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ12_BASE 0x564C3C0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ13_BASE 0x564C410ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ14_BASE 0x564C460ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ15_BASE 0x564C4B0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ16_BASE 0x564C500ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ17_BASE 0x564C550ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ18_BASE 0x564C5A0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ19_BASE 0x564C5F0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ20_BASE 0x564C640ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ21_BASE 0x564C690ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ22_BASE 0x564C6E0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ23_BASE 0x564C730ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ24_BASE 0x564C780ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ25_BASE 0x564C7D0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ26_BASE 0x564C820ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ27_BASE 0x564C870ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ28_BASE 0x564C8C0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ29_BASE 0x564C910ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ30_BASE 0x564C960ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ31_BASE 0x564C9B0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC4_RXE0_AXUSER_SPECIAL_BASE 0x564CE80ull
+#define NIC4_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define NIC4_RXE1_AXUSER_AXUSER_CQ0_BASE 0x564D000ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ1_BASE 0x564D050ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ2_BASE 0x564D0A0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ3_BASE 0x564D0F0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ4_BASE 0x564D140ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ5_BASE 0x564D190ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ6_BASE 0x564D1E0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ7_BASE 0x564D230ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ8_BASE 0x564D280ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ9_BASE 0x564D2D0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ10_BASE 0x564D320ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ11_BASE 0x564D370ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ12_BASE 0x564D3C0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ13_BASE 0x564D410ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ14_BASE 0x564D460ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ15_BASE 0x564D4B0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ16_BASE 0x564D500ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ17_BASE 0x564D550ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ18_BASE 0x564D5A0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ19_BASE 0x564D5F0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ20_BASE 0x564D640ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ21_BASE 0x564D690ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ22_BASE 0x564D6E0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ23_BASE 0x564D730ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ24_BASE 0x564D780ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ25_BASE 0x564D7D0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ26_BASE 0x564D820ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ27_BASE 0x564D870ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ28_BASE 0x564D8C0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ29_BASE 0x564D910ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ30_BASE 0x564D960ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ31_BASE 0x564D9B0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC4_RXE1_AXUSER_SPECIAL_BASE 0x564DE80ull
+#define NIC4_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define NIC4_TXS0_BASE 0x5650000ull
+#define NIC4_TXS0_MAX_OFFSET 0x1000
+#define NIC4_TXS0_SECTION 0xE800
+#define NIC4_TXS0_SPECIAL_BASE 0x5650E80ull
+#define NIC4_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_TXS0_SPECIAL_SECTION 0x1800
+#define NIC4_TXS1_BASE 0x5651000ull
+#define NIC4_TXS1_MAX_OFFSET 0x1000
+#define NIC4_TXS1_SECTION 0xE800
+#define NIC4_TXS1_SPECIAL_BASE 0x5651E80ull
+#define NIC4_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_TXS1_SPECIAL_SECTION 0x1800
+#define NIC4_TXE0_BASE 0x5652000ull
+#define NIC4_TXE0_MAX_OFFSET 0x1000
+#define NIC4_TXE0_SECTION 0xE800
+#define NIC4_TXE0_SPECIAL_BASE 0x5652E80ull
+#define NIC4_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_TXE0_SPECIAL_SECTION 0x1800
+#define NIC4_TXE1_BASE 0x5653000ull
+#define NIC4_TXE1_MAX_OFFSET 0x1000
+#define NIC4_TXE1_SECTION 0xE800
+#define NIC4_TXE1_SPECIAL_BASE 0x5653E80ull
+#define NIC4_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_TXE1_SPECIAL_SECTION 0x1800
+#define NIC4_TXB_BASE 0x5654000ull
+#define NIC4_TXB_MAX_OFFSET 0x1000
+#define NIC4_TXB_SECTION 0xE800
+#define NIC4_TXB_SPECIAL_BASE 0x5654E80ull
+#define NIC4_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_TXB_SPECIAL_SECTION 0x1800
+#define NIC4_MSTR_IF_RR_SHRD_HBW_BASE 0x5655000ull
+#define NIC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define NIC4_MSTR_IF_RR_PRVT_HBW_BASE 0x5655200ull
+#define NIC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define NIC4_MSTR_IF_RR_SHRD_LBW_BASE 0x5655400ull
+#define NIC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define NIC4_MSTR_IF_RR_PRVT_LBW_BASE 0x5655600ull
+#define NIC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define NIC4_MSTR_IF_E2E_CRDT_BASE 0x5655800ull
+#define NIC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define NIC4_MSTR_IF_AXUSER_BASE 0x5655A80ull
+#define NIC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC4_MSTR_IF_AXUSER_SECTION 0x8000
+#define NIC4_MSTR_IF_DBG_HBW_BASE 0x5655B00ull
+#define NIC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define NIC4_MSTR_IF_DBG_LBW_BASE 0x5655B80ull
+#define NIC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define NIC4_MSTR_IF_CORE_HBW_BASE 0x5655C00ull
+#define NIC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define NIC4_MSTR_IF_CORE_LBW_BASE 0x5655D80ull
+#define NIC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define NIC4_MSTR_IF_SPECIAL_BASE 0x5655E80ull
+#define NIC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_MSTR_IF_SPECIAL_SECTION 0x1800
+#define NIC4_TX_AXUSER_BASE 0x5656000ull
+#define NIC4_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC4_TX_AXUSER_SECTION 0x2000
+#define NIC4_SERDES0_BASE 0x5658000ull
+#define NIC4_SERDES0_MAX_OFFSET 0x3E40
+#define NIC4_SERDES0_SECTION 0x4000
+#define NIC4_SERDES1_BASE 0x565C000ull
+#define NIC4_SERDES1_MAX_OFFSET 0x3E40
+#define NIC4_SERDES1_SECTION 0x4000
+#define NIC4_PHY_BASE 0x5660000ull
+#define NIC4_PHY_MAX_OFFSET 0x1000
+#define NIC4_PHY_SECTION 0xE800
+#define NIC4_PHY_SPECIAL_BASE 0x5660E80ull
+#define NIC4_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_PHY_SPECIAL_SECTION 0x7180
+#define PRT4_MAC_AUX_BASE 0x5668000ull
+#define PRT4_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT4_MAC_AUX_SECTION 0xE800
+#define PRT4_MAC_AUX_SPECIAL_BASE 0x5668E80ull
+#define PRT4_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT4_MAC_AUX_SPECIAL_SECTION 0x1800
+#define PRT4_MAC_CORE_BASE 0x5669000ull
+#define PRT4_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT4_MAC_CORE_SECTION 0xE800
+#define PRT4_MAC_CORE_SPECIAL_BASE 0x5669E80ull
+#define PRT4_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT4_MAC_CORE_SPECIAL_SECTION 0x1800
+#define NIC4_MAC_RS_FEC_BASE 0x566A000ull
+#define NIC4_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC4_MAC_RS_FEC_SECTION 0x1000
+#define NIC4_MAC_GLOB_STAT_CONTROL_REG_BASE 0x566B000ull
+#define NIC4_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC4_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define NIC4_MAC_GLOB_STAT_RX0_BASE 0x566B100ull
+#define NIC4_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC4_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define NIC4_MAC_GLOB_STAT_RX1_BASE 0x566B18Cull
+#define NIC4_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC4_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define NIC4_MAC_GLOB_STAT_RX2_BASE 0x566B218ull
+#define NIC4_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC4_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define NIC4_MAC_GLOB_STAT_RX3_BASE 0x566B2A4ull
+#define NIC4_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC4_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define NIC4_MAC_GLOB_STAT_TX0_BASE 0x566B330ull
+#define NIC4_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC4_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define NIC4_MAC_GLOB_STAT_TX1_BASE 0x566B398ull
+#define NIC4_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC4_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define NIC4_MAC_GLOB_STAT_TX2_BASE 0x566B400ull
+#define NIC4_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC4_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define NIC4_MAC_GLOB_STAT_TX3_BASE 0x566B468ull
+#define NIC4_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC4_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define NIC4_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x566B800ull
+#define NIC4_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC4_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define NIC4_MAC_CH0_MAC_PCS_BASE 0x566C000ull
+#define NIC4_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC4_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define NIC4_MAC_CH0_MAC_128_BASE 0x566C400ull
+#define NIC4_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC4_MAC_CH0_MAC_128_SECTION 0x4000
+#define NIC4_MAC_CH0_MAC_AN_BASE 0x566C800ull
+#define NIC4_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC4_MAC_CH0_MAC_AN_SECTION 0x8000
+#define NIC4_MAC_CH1_MAC_PCS_BASE 0x566D000ull
+#define NIC4_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC4_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define NIC4_MAC_CH1_MAC_128_BASE 0x566D400ull
+#define NIC4_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC4_MAC_CH1_MAC_128_SECTION 0x4000
+#define NIC4_MAC_CH1_MAC_AN_BASE 0x566D800ull
+#define NIC4_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC4_MAC_CH1_MAC_AN_SECTION 0x8000
+#define NIC4_MAC_CH2_MAC_PCS_BASE 0x566E000ull
+#define NIC4_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC4_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define NIC4_MAC_CH2_MAC_128_BASE 0x566E400ull
+#define NIC4_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC4_MAC_CH2_MAC_128_SECTION 0x4000
+#define NIC4_MAC_CH2_MAC_AN_BASE 0x566E800ull
+#define NIC4_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC4_MAC_CH2_MAC_AN_SECTION 0x8000
+#define NIC4_MAC_CH3_MAC_PCS_BASE 0x566F000ull
+#define NIC4_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC4_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define NIC4_MAC_CH3_MAC_128_BASE 0x566F400ull
+#define NIC4_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC4_MAC_CH3_MAC_128_SECTION 0x4000
+#define NIC4_MAC_CH3_MAC_AN_BASE 0x566F800ull
+#define NIC4_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC4_MAC_CH3_MAC_AN_SECTION 0x10800
+#define NIC5_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5680000ull
+#define NIC5_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5680080ull
+#define NIC5_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5680100ull
+#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5680180ull
+#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_0_SPECIAL_BASE 0x5680E80ull
+#define NIC5_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_0_SPECIAL_SECTION 0x1800
+#define NIC5_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5681000ull
+#define NIC5_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5681080ull
+#define NIC5_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5681100ull
+#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5681180ull
+#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_1_SPECIAL_BASE 0x5681E80ull
+#define NIC5_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_1_SPECIAL_SECTION 0x1800
+#define NIC5_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5682000ull
+#define NIC5_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5682080ull
+#define NIC5_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5682100ull
+#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5682180ull
+#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_2_SPECIAL_BASE 0x5682E80ull
+#define NIC5_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_2_SPECIAL_SECTION 0x1800
+#define NIC5_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5683000ull
+#define NIC5_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5683080ull
+#define NIC5_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5683100ull
+#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5683180ull
+#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_3_SPECIAL_BASE 0x5683E80ull
+#define NIC5_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_3_SPECIAL_SECTION 0x1800
+#define NIC5_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5684000ull
+#define NIC5_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5684080ull
+#define NIC5_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5684100ull
+#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5684180ull
+#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_4_SPECIAL_BASE 0x5684E80ull
+#define NIC5_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_4_SPECIAL_SECTION 0x1800
+#define NIC5_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5685000ull
+#define NIC5_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5685080ull
+#define NIC5_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5685100ull
+#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5685180ull
+#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_5_SPECIAL_BASE 0x5685E80ull
+#define NIC5_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_5_SPECIAL_SECTION 0x1800
+#define NIC5_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5686000ull
+#define NIC5_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5686080ull
+#define NIC5_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5686100ull
+#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5686180ull
+#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_6_SPECIAL_BASE 0x5686E80ull
+#define NIC5_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_6_SPECIAL_SECTION 0x1800
+#define NIC5_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5687000ull
+#define NIC5_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5687080ull
+#define NIC5_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5687100ull
+#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5687180ull
+#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_7_SPECIAL_BASE 0x5687E80ull
+#define NIC5_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_7_SPECIAL_SECTION 0x1800
+#define NIC5_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5688000ull
+#define NIC5_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5688080ull
+#define NIC5_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5688100ull
+#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5688180ull
+#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_8_SPECIAL_BASE 0x5688E80ull
+#define NIC5_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_8_SPECIAL_SECTION 0x1800
+#define NIC5_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5689000ull
+#define NIC5_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5689080ull
+#define NIC5_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5689100ull
+#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5689180ull
+#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_9_SPECIAL_BASE 0x5689E80ull
+#define NIC5_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_9_SPECIAL_SECTION 0x1800
+#define NIC5_UMR0_10_UNSECURE_DOORBELL0_BASE 0x568A000ull
+#define NIC5_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_10_UNSECURE_DOORBELL1_BASE 0x568A080ull
+#define NIC5_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x568A100ull
+#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x568A180ull
+#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_10_SPECIAL_BASE 0x568AE80ull
+#define NIC5_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_10_SPECIAL_SECTION 0x1800
+#define NIC5_UMR0_11_UNSECURE_DOORBELL0_BASE 0x568B000ull
+#define NIC5_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_11_UNSECURE_DOORBELL1_BASE 0x568B080ull
+#define NIC5_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x568B100ull
+#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x568B180ull
+#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_11_SPECIAL_BASE 0x568BE80ull
+#define NIC5_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_11_SPECIAL_SECTION 0x1800
+#define NIC5_UMR0_12_UNSECURE_DOORBELL0_BASE 0x568C000ull
+#define NIC5_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_12_UNSECURE_DOORBELL1_BASE 0x568C080ull
+#define NIC5_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x568C100ull
+#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x568C180ull
+#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_12_SPECIAL_BASE 0x568CE80ull
+#define NIC5_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_12_SPECIAL_SECTION 0x1800
+#define NIC5_UMR0_13_UNSECURE_DOORBELL0_BASE 0x568D000ull
+#define NIC5_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_13_UNSECURE_DOORBELL1_BASE 0x568D080ull
+#define NIC5_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x568D100ull
+#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x568D180ull
+#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_13_SPECIAL_BASE 0x568DE80ull
+#define NIC5_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_13_SPECIAL_SECTION 0x1800
+#define NIC5_UMR0_14_UNSECURE_DOORBELL0_BASE 0x568E000ull
+#define NIC5_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR0_14_UNSECURE_DOORBELL1_BASE 0x568E080ull
+#define NIC5_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x568E100ull
+#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x568E180ull
+#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR0_14_SPECIAL_BASE 0x568EE80ull
+#define NIC5_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_14_SPECIAL_SECTION 0x1180
+#define NIC5_QM_DCCM0_BASE 0x5690000ull
+#define NIC5_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC5_QM_DCCM0_SECTION 0x8000
+#define NIC5_QM_ARC_AUX0_BASE 0x5698000ull
+#define NIC5_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC5_QM_ARC_AUX0_SECTION 0xE800
+#define NIC5_QM_ARC_AUX0_SPECIAL_BASE 0x5698E80ull
+#define NIC5_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define NIC5_QM0_BASE 0x569A000ull
+#define NIC5_QM0_MAX_OFFSET 0x1000
+#define NIC5_QM0_SECTION 0x9000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x569A900ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x569A908ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x569A910ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x569A918ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x569A920ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x569A928ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x569A930ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x569A938ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x569A940ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x569A948ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x569A950ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x569A958ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x569A960ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x569A968ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x569A970ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x569A978ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC5_QM0_AXUSER_SECURED_BASE 0x569AB00ull
+#define NIC5_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC5_QM0_AXUSER_SECURED_SECTION 0x8000
+#define NIC5_QM0_AXUSER_NONSECURED_BASE 0x569AB80ull
+#define NIC5_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC5_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC5_QM0_DBG_HBW_BASE 0x569AC00ull
+#define NIC5_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC5_QM0_DBG_HBW_SECTION 0x8000
+#define NIC5_QM0_DBG_LBW_BASE 0x569AC80ull
+#define NIC5_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC5_QM0_DBG_LBW_SECTION 0x1000
+#define NIC5_QM0_CGM_BASE 0x569AD80ull
+#define NIC5_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC5_QM0_CGM_SECTION 0x1000
+#define NIC5_QM0_SPECIAL_BASE 0x569AE80ull
+#define NIC5_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_QM0_SPECIAL_SECTION 0x4180
+#define NIC5_QPC0_BASE 0x569F000ull
+#define NIC5_QPC0_MAX_OFFSET 0x1000
+#define NIC5_QPC0_SECTION 0x7200
+#define NIC5_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x569F720ull
+#define NIC5_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x569F728ull
+#define NIC5_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x569F730ull
+#define NIC5_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x569F738ull
+#define NIC5_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x569F740ull
+#define NIC5_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x569F748ull
+#define NIC5_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x569F750ull
+#define NIC5_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x569F758ull
+#define NIC5_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x569F760ull
+#define NIC5_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x569F768ull
+#define NIC5_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x569F770ull
+#define NIC5_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x569F778ull
+#define NIC5_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x569F780ull
+#define NIC5_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x569F788ull
+#define NIC5_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x569F790ull
+#define NIC5_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x569F798ull
+#define NIC5_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x569F7A0ull
+#define NIC5_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x569F7A8ull
+#define NIC5_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x569F7B0ull
+#define NIC5_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x569F7B8ull
+#define NIC5_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x569F7C0ull
+#define NIC5_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x569F7C8ull
+#define NIC5_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x569F7D0ull
+#define NIC5_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x569F7D8ull
+#define NIC5_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x569F7E0ull
+#define NIC5_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x569F7E8ull
+#define NIC5_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x569F7F0ull
+#define NIC5_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x569F7F8ull
+#define NIC5_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x569F800ull
+#define NIC5_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x569F808ull
+#define NIC5_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x569F810ull
+#define NIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x569F818ull
+#define NIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC5_QPC0_AXUSER_CONG_QUE_BASE 0x569FB80ull
+#define NIC5_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC5_QPC0_AXUSER_RXWQE_BASE 0x569FBE0ull
+#define NIC5_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define NIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x569FC40ull
+#define NIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC5_QPC0_AXUSER_DB_FIFO_BASE 0x569FCA0ull
+#define NIC5_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x569FD00ull
+#define NIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC5_QPC0_AXUSER_ERR_FIFO_BASE 0x569FD60ull
+#define NIC5_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC5_QPC0_AXUSER_QPC_RESP_BASE 0x569FDC0ull
+#define NIC5_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC5_QPC0_AXUSER_QPC_REQ_BASE 0x569FE20ull
+#define NIC5_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC5_QPC0_SPECIAL_BASE 0x569FE80ull
+#define NIC5_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_QPC0_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_0_UNSECURE_DOORBELL0_BASE 0x56A0000ull
+#define NIC5_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_0_UNSECURE_DOORBELL1_BASE 0x56A0080ull
+#define NIC5_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x56A0100ull
+#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x56A0180ull
+#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_0_SPECIAL_BASE 0x56A0E80ull
+#define NIC5_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_0_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_1_UNSECURE_DOORBELL0_BASE 0x56A1000ull
+#define NIC5_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_1_UNSECURE_DOORBELL1_BASE 0x56A1080ull
+#define NIC5_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x56A1100ull
+#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x56A1180ull
+#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_1_SPECIAL_BASE 0x56A1E80ull
+#define NIC5_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_1_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_2_UNSECURE_DOORBELL0_BASE 0x56A2000ull
+#define NIC5_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_2_UNSECURE_DOORBELL1_BASE 0x56A2080ull
+#define NIC5_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x56A2100ull
+#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x56A2180ull
+#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_2_SPECIAL_BASE 0x56A2E80ull
+#define NIC5_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_2_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_3_UNSECURE_DOORBELL0_BASE 0x56A3000ull
+#define NIC5_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_3_UNSECURE_DOORBELL1_BASE 0x56A3080ull
+#define NIC5_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x56A3100ull
+#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x56A3180ull
+#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_3_SPECIAL_BASE 0x56A3E80ull
+#define NIC5_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_3_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_4_UNSECURE_DOORBELL0_BASE 0x56A4000ull
+#define NIC5_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_4_UNSECURE_DOORBELL1_BASE 0x56A4080ull
+#define NIC5_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x56A4100ull
+#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x56A4180ull
+#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_4_SPECIAL_BASE 0x56A4E80ull
+#define NIC5_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_4_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_5_UNSECURE_DOORBELL0_BASE 0x56A5000ull
+#define NIC5_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_5_UNSECURE_DOORBELL1_BASE 0x56A5080ull
+#define NIC5_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x56A5100ull
+#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x56A5180ull
+#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_5_SPECIAL_BASE 0x56A5E80ull
+#define NIC5_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_5_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_6_UNSECURE_DOORBELL0_BASE 0x56A6000ull
+#define NIC5_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_6_UNSECURE_DOORBELL1_BASE 0x56A6080ull
+#define NIC5_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x56A6100ull
+#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x56A6180ull
+#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_6_SPECIAL_BASE 0x56A6E80ull
+#define NIC5_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_6_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_7_UNSECURE_DOORBELL0_BASE 0x56A7000ull
+#define NIC5_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_7_UNSECURE_DOORBELL1_BASE 0x56A7080ull
+#define NIC5_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x56A7100ull
+#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x56A7180ull
+#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_7_SPECIAL_BASE 0x56A7E80ull
+#define NIC5_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_7_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_8_UNSECURE_DOORBELL0_BASE 0x56A8000ull
+#define NIC5_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_8_UNSECURE_DOORBELL1_BASE 0x56A8080ull
+#define NIC5_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x56A8100ull
+#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x56A8180ull
+#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_8_SPECIAL_BASE 0x56A8E80ull
+#define NIC5_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_8_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_9_UNSECURE_DOORBELL0_BASE 0x56A9000ull
+#define NIC5_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_9_UNSECURE_DOORBELL1_BASE 0x56A9080ull
+#define NIC5_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x56A9100ull
+#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x56A9180ull
+#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_9_SPECIAL_BASE 0x56A9E80ull
+#define NIC5_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_9_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_10_UNSECURE_DOORBELL0_BASE 0x56AA000ull
+#define NIC5_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_10_UNSECURE_DOORBELL1_BASE 0x56AA080ull
+#define NIC5_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x56AA100ull
+#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x56AA180ull
+#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_10_SPECIAL_BASE 0x56AAE80ull
+#define NIC5_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_10_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_11_UNSECURE_DOORBELL0_BASE 0x56AB000ull
+#define NIC5_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_11_UNSECURE_DOORBELL1_BASE 0x56AB080ull
+#define NIC5_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x56AB100ull
+#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x56AB180ull
+#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_11_SPECIAL_BASE 0x56ABE80ull
+#define NIC5_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_11_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_12_UNSECURE_DOORBELL0_BASE 0x56AC000ull
+#define NIC5_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_12_UNSECURE_DOORBELL1_BASE 0x56AC080ull
+#define NIC5_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x56AC100ull
+#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x56AC180ull
+#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_12_SPECIAL_BASE 0x56ACE80ull
+#define NIC5_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_12_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_13_UNSECURE_DOORBELL0_BASE 0x56AD000ull
+#define NIC5_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_13_UNSECURE_DOORBELL1_BASE 0x56AD080ull
+#define NIC5_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x56AD100ull
+#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x56AD180ull
+#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_13_SPECIAL_BASE 0x56ADE80ull
+#define NIC5_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_13_SPECIAL_SECTION 0x1800
+#define NIC5_UMR1_14_UNSECURE_DOORBELL0_BASE 0x56AE000ull
+#define NIC5_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC5_UMR1_14_UNSECURE_DOORBELL1_BASE 0x56AE080ull
+#define NIC5_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x56AE100ull
+#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x56AE180ull
+#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC5_UMR1_14_SPECIAL_BASE 0x56AEE80ull
+#define NIC5_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_14_SPECIAL_SECTION 0x1180
+#define NIC5_QM_DCCM1_BASE 0x56B0000ull
+#define NIC5_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC5_QM_DCCM1_SECTION 0x8000
+#define NIC5_QM_ARC_AUX1_BASE 0x56B8000ull
+#define NIC5_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC5_QM_ARC_AUX1_SECTION 0xE800
+#define NIC5_QM_ARC_AUX1_SPECIAL_BASE 0x56B8E80ull
+#define NIC5_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define NIC5_QM1_BASE 0x56BA000ull
+#define NIC5_QM1_MAX_OFFSET 0x1000
+#define NIC5_QM1_SECTION 0x9000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x56BA900ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x56BA908ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x56BA910ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x56BA918ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x56BA920ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x56BA928ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x56BA930ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x56BA938ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x56BA940ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x56BA948ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x56BA950ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x56BA958ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x56BA960ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x56BA968ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x56BA970ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x56BA978ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC5_QM1_AXUSER_SECURED_BASE 0x56BAB00ull
+#define NIC5_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC5_QM1_AXUSER_SECURED_SECTION 0x8000
+#define NIC5_QM1_AXUSER_NONSECURED_BASE 0x56BAB80ull
+#define NIC5_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC5_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC5_QM1_DBG_HBW_BASE 0x56BAC00ull
+#define NIC5_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC5_QM1_DBG_HBW_SECTION 0x8000
+#define NIC5_QM1_DBG_LBW_BASE 0x56BAC80ull
+#define NIC5_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC5_QM1_DBG_LBW_SECTION 0x1000
+#define NIC5_QM1_CGM_BASE 0x56BAD80ull
+#define NIC5_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC5_QM1_CGM_SECTION 0x1000
+#define NIC5_QM1_SPECIAL_BASE 0x56BAE80ull
+#define NIC5_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_QM1_SPECIAL_SECTION 0x4180
+#define NIC5_QPC1_BASE 0x56BF000ull
+#define NIC5_QPC1_MAX_OFFSET 0x1000
+#define NIC5_QPC1_SECTION 0x7200
+#define NIC5_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x56BF720ull
+#define NIC5_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x56BF728ull
+#define NIC5_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x56BF730ull
+#define NIC5_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x56BF738ull
+#define NIC5_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x56BF740ull
+#define NIC5_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x56BF748ull
+#define NIC5_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x56BF750ull
+#define NIC5_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x56BF758ull
+#define NIC5_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x56BF760ull
+#define NIC5_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x56BF768ull
+#define NIC5_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x56BF770ull
+#define NIC5_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x56BF778ull
+#define NIC5_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x56BF780ull
+#define NIC5_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x56BF788ull
+#define NIC5_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x56BF790ull
+#define NIC5_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x56BF798ull
+#define NIC5_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x56BF7A0ull
+#define NIC5_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x56BF7A8ull
+#define NIC5_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x56BF7B0ull
+#define NIC5_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x56BF7B8ull
+#define NIC5_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x56BF7C0ull
+#define NIC5_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x56BF7C8ull
+#define NIC5_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x56BF7D0ull
+#define NIC5_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x56BF7D8ull
+#define NIC5_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x56BF7E0ull
+#define NIC5_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x56BF7E8ull
+#define NIC5_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x56BF7F0ull
+#define NIC5_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x56BF7F8ull
+#define NIC5_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x56BF800ull
+#define NIC5_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x56BF808ull
+#define NIC5_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x56BF810ull
+#define NIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x56BF818ull
+#define NIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC5_QPC1_AXUSER_CONG_QUE_BASE 0x56BFB80ull
+#define NIC5_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC5_QPC1_AXUSER_RXWQE_BASE 0x56BFBE0ull
+#define NIC5_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define NIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x56BFC40ull
+#define NIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC5_QPC1_AXUSER_DB_FIFO_BASE 0x56BFCA0ull
+#define NIC5_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x56BFD00ull
+#define NIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC5_QPC1_AXUSER_ERR_FIFO_BASE 0x56BFD60ull
+#define NIC5_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC5_QPC1_AXUSER_QPC_RESP_BASE 0x56BFDC0ull
+#define NIC5_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC5_QPC1_AXUSER_QPC_REQ_BASE 0x56BFE20ull
+#define NIC5_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC5_QPC1_SPECIAL_BASE 0x56BFE80ull
+#define NIC5_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_QPC1_SPECIAL_SECTION 0x8180
+#define NIC5_TMR_BASE 0x56C8000ull
+#define NIC5_TMR_MAX_OFFSET 0x1000
+#define NIC5_TMR_SECTION 0xD600
+#define NIC5_TMR_AXUSER_TMR_FREE_LIST_BASE 0x56C8D60ull
+#define NIC5_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC5_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define NIC5_TMR_AXUSER_TMR_FIFO_BASE 0x56C8DC0ull
+#define NIC5_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC5_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define NIC5_TMR_AXUSER_TMR_FSM_BASE 0x56C8E20ull
+#define NIC5_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC5_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define NIC5_TMR_SPECIAL_BASE 0x56C8E80ull
+#define NIC5_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_TMR_SPECIAL_SECTION 0x1800
+#define NIC5_RXB_CORE_BASE 0x56C9000ull
+#define NIC5_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC5_RXB_CORE_SECTION 0x6100
+#define NIC5_RXB_CORE_SCT_AWUSER_BASE 0x56C9610ull
+#define NIC5_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC5_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define NIC5_RXB_CORE_SPECIAL_BASE 0x56C9E80ull
+#define NIC5_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_RXB_CORE_SPECIAL_SECTION 0x1800
+#define NIC5_RXE0_BASE 0x56CA000ull
+#define NIC5_RXE0_MAX_OFFSET 0x1000
+#define NIC5_RXE0_SECTION 0x9000
+#define NIC5_RXE0_WQE_ARUSER_BASE 0x56CA900ull
+#define NIC5_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC5_RXE0_WQE_ARUSER_SECTION 0x5800
+#define NIC5_RXE0_SPECIAL_BASE 0x56CAE80ull
+#define NIC5_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_RXE0_SPECIAL_SECTION 0x1800
+#define NIC5_RXE1_BASE 0x56CB000ull
+#define NIC5_RXE1_MAX_OFFSET 0x1000
+#define NIC5_RXE1_SECTION 0x9000
+#define NIC5_RXE1_WQE_ARUSER_BASE 0x56CB900ull
+#define NIC5_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC5_RXE1_WQE_ARUSER_SECTION 0x5800
+#define NIC5_RXE1_SPECIAL_BASE 0x56CBE80ull
+#define NIC5_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_RXE1_SPECIAL_SECTION 0x1800
+#define NIC5_RXE0_AXUSER_AXUSER_CQ0_BASE 0x56CC000ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ1_BASE 0x56CC050ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ2_BASE 0x56CC0A0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ3_BASE 0x56CC0F0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ4_BASE 0x56CC140ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ5_BASE 0x56CC190ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ6_BASE 0x56CC1E0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ7_BASE 0x56CC230ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ8_BASE 0x56CC280ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ9_BASE 0x56CC2D0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ10_BASE 0x56CC320ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ11_BASE 0x56CC370ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ12_BASE 0x56CC3C0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ13_BASE 0x56CC410ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ14_BASE 0x56CC460ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ15_BASE 0x56CC4B0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ16_BASE 0x56CC500ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ17_BASE 0x56CC550ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ18_BASE 0x56CC5A0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ19_BASE 0x56CC5F0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ20_BASE 0x56CC640ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ21_BASE 0x56CC690ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ22_BASE 0x56CC6E0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ23_BASE 0x56CC730ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ24_BASE 0x56CC780ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ25_BASE 0x56CC7D0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ26_BASE 0x56CC820ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ27_BASE 0x56CC870ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ28_BASE 0x56CC8C0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ29_BASE 0x56CC910ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ30_BASE 0x56CC960ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ31_BASE 0x56CC9B0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC5_RXE0_AXUSER_SPECIAL_BASE 0x56CCE80ull
+#define NIC5_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define NIC5_RXE1_AXUSER_AXUSER_CQ0_BASE 0x56CD000ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ1_BASE 0x56CD050ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ2_BASE 0x56CD0A0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ3_BASE 0x56CD0F0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ4_BASE 0x56CD140ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ5_BASE 0x56CD190ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ6_BASE 0x56CD1E0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ7_BASE 0x56CD230ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ8_BASE 0x56CD280ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ9_BASE 0x56CD2D0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ10_BASE 0x56CD320ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ11_BASE 0x56CD370ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ12_BASE 0x56CD3C0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ13_BASE 0x56CD410ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ14_BASE 0x56CD460ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ15_BASE 0x56CD4B0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ16_BASE 0x56CD500ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ17_BASE 0x56CD550ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ18_BASE 0x56CD5A0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ19_BASE 0x56CD5F0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ20_BASE 0x56CD640ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ21_BASE 0x56CD690ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ22_BASE 0x56CD6E0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ23_BASE 0x56CD730ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ24_BASE 0x56CD780ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ25_BASE 0x56CD7D0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ26_BASE 0x56CD820ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ27_BASE 0x56CD870ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ28_BASE 0x56CD8C0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ29_BASE 0x56CD910ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ30_BASE 0x56CD960ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ31_BASE 0x56CD9B0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC5_RXE1_AXUSER_SPECIAL_BASE 0x56CDE80ull
+#define NIC5_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define NIC5_TXS0_BASE 0x56D0000ull
+#define NIC5_TXS0_MAX_OFFSET 0x1000
+#define NIC5_TXS0_SECTION 0xE800
+#define NIC5_TXS0_SPECIAL_BASE 0x56D0E80ull
+#define NIC5_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_TXS0_SPECIAL_SECTION 0x1800
+#define NIC5_TXS1_BASE 0x56D1000ull
+#define NIC5_TXS1_MAX_OFFSET 0x1000
+#define NIC5_TXS1_SECTION 0xE800
+#define NIC5_TXS1_SPECIAL_BASE 0x56D1E80ull
+#define NIC5_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_TXS1_SPECIAL_SECTION 0x1800
+#define NIC5_TXE0_BASE 0x56D2000ull
+#define NIC5_TXE0_MAX_OFFSET 0x1000
+#define NIC5_TXE0_SECTION 0xE800
+#define NIC5_TXE0_SPECIAL_BASE 0x56D2E80ull
+#define NIC5_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_TXE0_SPECIAL_SECTION 0x1800
+#define NIC5_TXE1_BASE 0x56D3000ull
+#define NIC5_TXE1_MAX_OFFSET 0x1000
+#define NIC5_TXE1_SECTION 0xE800
+#define NIC5_TXE1_SPECIAL_BASE 0x56D3E80ull
+#define NIC5_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_TXE1_SPECIAL_SECTION 0x1800
+#define NIC5_TXB_BASE 0x56D4000ull
+#define NIC5_TXB_MAX_OFFSET 0x1000
+#define NIC5_TXB_SECTION 0xE800
+#define NIC5_TXB_SPECIAL_BASE 0x56D4E80ull
+#define NIC5_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_TXB_SPECIAL_SECTION 0x1800
+#define NIC5_MSTR_IF_RR_SHRD_HBW_BASE 0x56D5000ull
+#define NIC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define NIC5_MSTR_IF_RR_PRVT_HBW_BASE 0x56D5200ull
+#define NIC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define NIC5_MSTR_IF_RR_SHRD_LBW_BASE 0x56D5400ull
+#define NIC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define NIC5_MSTR_IF_RR_PRVT_LBW_BASE 0x56D5600ull
+#define NIC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define NIC5_MSTR_IF_E2E_CRDT_BASE 0x56D5800ull
+#define NIC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define NIC5_MSTR_IF_AXUSER_BASE 0x56D5A80ull
+#define NIC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC5_MSTR_IF_AXUSER_SECTION 0x8000
+#define NIC5_MSTR_IF_DBG_HBW_BASE 0x56D5B00ull
+#define NIC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define NIC5_MSTR_IF_DBG_LBW_BASE 0x56D5B80ull
+#define NIC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define NIC5_MSTR_IF_CORE_HBW_BASE 0x56D5C00ull
+#define NIC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define NIC5_MSTR_IF_CORE_LBW_BASE 0x56D5D80ull
+#define NIC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define NIC5_MSTR_IF_SPECIAL_BASE 0x56D5E80ull
+#define NIC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_MSTR_IF_SPECIAL_SECTION 0x1800
+#define NIC5_TX_AXUSER_BASE 0x56D6000ull
+#define NIC5_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC5_TX_AXUSER_SECTION 0x2000
+#define NIC5_SERDES0_BASE 0x56D8000ull
+#define NIC5_SERDES0_MAX_OFFSET 0x3E40
+#define NIC5_SERDES0_SECTION 0x4000
+#define NIC5_SERDES1_BASE 0x56DC000ull
+#define NIC5_SERDES1_MAX_OFFSET 0x3E40
+#define NIC5_SERDES1_SECTION 0x4000
+#define NIC5_PHY_BASE 0x56E0000ull
+#define NIC5_PHY_MAX_OFFSET 0x1000
+#define NIC5_PHY_SECTION 0xE800
+#define NIC5_PHY_SPECIAL_BASE 0x56E0E80ull
+#define NIC5_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_PHY_SPECIAL_SECTION 0x7180
+#define PRT5_MAC_AUX_BASE 0x56E8000ull
+#define PRT5_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT5_MAC_AUX_SECTION 0xE800
+#define PRT5_MAC_AUX_SPECIAL_BASE 0x56E8E80ull
+#define PRT5_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT5_MAC_AUX_SPECIAL_SECTION 0x1800
+#define PRT5_MAC_CORE_BASE 0x56E9000ull
+#define PRT5_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT5_MAC_CORE_SECTION 0xE800
+#define PRT5_MAC_CORE_SPECIAL_BASE 0x56E9E80ull
+#define PRT5_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT5_MAC_CORE_SPECIAL_SECTION 0x1800
+#define NIC5_MAC_RS_FEC_BASE 0x56EA000ull
+#define NIC5_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC5_MAC_RS_FEC_SECTION 0x1000
+#define NIC5_MAC_GLOB_STAT_CONTROL_REG_BASE 0x56EB000ull
+#define NIC5_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC5_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define NIC5_MAC_GLOB_STAT_RX0_BASE 0x56EB100ull
+#define NIC5_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC5_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define NIC5_MAC_GLOB_STAT_RX1_BASE 0x56EB18Cull
+#define NIC5_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC5_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define NIC5_MAC_GLOB_STAT_RX2_BASE 0x56EB218ull
+#define NIC5_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC5_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define NIC5_MAC_GLOB_STAT_RX3_BASE 0x56EB2A4ull
+#define NIC5_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC5_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define NIC5_MAC_GLOB_STAT_TX0_BASE 0x56EB330ull
+#define NIC5_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC5_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define NIC5_MAC_GLOB_STAT_TX1_BASE 0x56EB398ull
+#define NIC5_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC5_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define NIC5_MAC_GLOB_STAT_TX2_BASE 0x56EB400ull
+#define NIC5_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC5_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define NIC5_MAC_GLOB_STAT_TX3_BASE 0x56EB468ull
+#define NIC5_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC5_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define NIC5_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x56EB800ull
+#define NIC5_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC5_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define NIC5_MAC_CH0_MAC_PCS_BASE 0x56EC000ull
+#define NIC5_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC5_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define NIC5_MAC_CH0_MAC_128_BASE 0x56EC400ull
+#define NIC5_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC5_MAC_CH0_MAC_128_SECTION 0x4000
+#define NIC5_MAC_CH0_MAC_AN_BASE 0x56EC800ull
+#define NIC5_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC5_MAC_CH0_MAC_AN_SECTION 0x8000
+#define NIC5_MAC_CH1_MAC_PCS_BASE 0x56ED000ull
+#define NIC5_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC5_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define NIC5_MAC_CH1_MAC_128_BASE 0x56ED400ull
+#define NIC5_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC5_MAC_CH1_MAC_128_SECTION 0x4000
+#define NIC5_MAC_CH1_MAC_AN_BASE 0x56ED800ull
+#define NIC5_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC5_MAC_CH1_MAC_AN_SECTION 0x8000
+#define NIC5_MAC_CH2_MAC_PCS_BASE 0x56EE000ull
+#define NIC5_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC5_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define NIC5_MAC_CH2_MAC_128_BASE 0x56EE400ull
+#define NIC5_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC5_MAC_CH2_MAC_128_SECTION 0x4000
+#define NIC5_MAC_CH2_MAC_AN_BASE 0x56EE800ull
+#define NIC5_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC5_MAC_CH2_MAC_AN_SECTION 0x8000
+#define NIC5_MAC_CH3_MAC_PCS_BASE 0x56EF000ull
+#define NIC5_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC5_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define NIC5_MAC_CH3_MAC_128_BASE 0x56EF400ull
+#define NIC5_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC5_MAC_CH3_MAC_128_SECTION 0x4000
+#define NIC5_MAC_CH3_MAC_AN_BASE 0x56EF800ull
+#define NIC5_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC5_MAC_CH3_MAC_AN_SECTION 0x10800
+#define NIC6_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5700000ull
+#define NIC6_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5700080ull
+#define NIC6_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5700100ull
+#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5700180ull
+#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_0_SPECIAL_BASE 0x5700E80ull
+#define NIC6_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_0_SPECIAL_SECTION 0x1800
+#define NIC6_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5701000ull
+#define NIC6_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5701080ull
+#define NIC6_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5701100ull
+#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5701180ull
+#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_1_SPECIAL_BASE 0x5701E80ull
+#define NIC6_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_1_SPECIAL_SECTION 0x1800
+#define NIC6_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5702000ull
+#define NIC6_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5702080ull
+#define NIC6_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5702100ull
+#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5702180ull
+#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_2_SPECIAL_BASE 0x5702E80ull
+#define NIC6_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_2_SPECIAL_SECTION 0x1800
+#define NIC6_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5703000ull
+#define NIC6_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5703080ull
+#define NIC6_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5703100ull
+#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5703180ull
+#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_3_SPECIAL_BASE 0x5703E80ull
+#define NIC6_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_3_SPECIAL_SECTION 0x1800
+#define NIC6_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5704000ull
+#define NIC6_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5704080ull
+#define NIC6_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5704100ull
+#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5704180ull
+#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_4_SPECIAL_BASE 0x5704E80ull
+#define NIC6_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_4_SPECIAL_SECTION 0x1800
+#define NIC6_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5705000ull
+#define NIC6_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5705080ull
+#define NIC6_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5705100ull
+#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5705180ull
+#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_5_SPECIAL_BASE 0x5705E80ull
+#define NIC6_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_5_SPECIAL_SECTION 0x1800
+#define NIC6_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5706000ull
+#define NIC6_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5706080ull
+#define NIC6_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5706100ull
+#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5706180ull
+#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_6_SPECIAL_BASE 0x5706E80ull
+#define NIC6_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_6_SPECIAL_SECTION 0x1800
+#define NIC6_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5707000ull
+#define NIC6_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5707080ull
+#define NIC6_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5707100ull
+#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5707180ull
+#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_7_SPECIAL_BASE 0x5707E80ull
+#define NIC6_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_7_SPECIAL_SECTION 0x1800
+#define NIC6_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5708000ull
+#define NIC6_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5708080ull
+#define NIC6_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5708100ull
+#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5708180ull
+#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_8_SPECIAL_BASE 0x5708E80ull
+#define NIC6_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_8_SPECIAL_SECTION 0x1800
+#define NIC6_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5709000ull
+#define NIC6_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5709080ull
+#define NIC6_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5709100ull
+#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5709180ull
+#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_9_SPECIAL_BASE 0x5709E80ull
+#define NIC6_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_9_SPECIAL_SECTION 0x1800
+#define NIC6_UMR0_10_UNSECURE_DOORBELL0_BASE 0x570A000ull
+#define NIC6_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_10_UNSECURE_DOORBELL1_BASE 0x570A080ull
+#define NIC6_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x570A100ull
+#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x570A180ull
+#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_10_SPECIAL_BASE 0x570AE80ull
+#define NIC6_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_10_SPECIAL_SECTION 0x1800
+#define NIC6_UMR0_11_UNSECURE_DOORBELL0_BASE 0x570B000ull
+#define NIC6_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_11_UNSECURE_DOORBELL1_BASE 0x570B080ull
+#define NIC6_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x570B100ull
+#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x570B180ull
+#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_11_SPECIAL_BASE 0x570BE80ull
+#define NIC6_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_11_SPECIAL_SECTION 0x1800
+#define NIC6_UMR0_12_UNSECURE_DOORBELL0_BASE 0x570C000ull
+#define NIC6_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_12_UNSECURE_DOORBELL1_BASE 0x570C080ull
+#define NIC6_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x570C100ull
+#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x570C180ull
+#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_12_SPECIAL_BASE 0x570CE80ull
+#define NIC6_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_12_SPECIAL_SECTION 0x1800
+#define NIC6_UMR0_13_UNSECURE_DOORBELL0_BASE 0x570D000ull
+#define NIC6_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_13_UNSECURE_DOORBELL1_BASE 0x570D080ull
+#define NIC6_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x570D100ull
+#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x570D180ull
+#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_13_SPECIAL_BASE 0x570DE80ull
+#define NIC6_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_13_SPECIAL_SECTION 0x1800
+#define NIC6_UMR0_14_UNSECURE_DOORBELL0_BASE 0x570E000ull
+#define NIC6_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR0_14_UNSECURE_DOORBELL1_BASE 0x570E080ull
+#define NIC6_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x570E100ull
+#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x570E180ull
+#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR0_14_SPECIAL_BASE 0x570EE80ull
+#define NIC6_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_14_SPECIAL_SECTION 0x1180
+#define NIC6_QM_DCCM0_BASE 0x5710000ull
+#define NIC6_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC6_QM_DCCM0_SECTION 0x8000
+#define NIC6_QM_ARC_AUX0_BASE 0x5718000ull
+#define NIC6_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC6_QM_ARC_AUX0_SECTION 0xE800
+#define NIC6_QM_ARC_AUX0_SPECIAL_BASE 0x5718E80ull
+#define NIC6_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define NIC6_QM0_BASE 0x571A000ull
+#define NIC6_QM0_MAX_OFFSET 0x1000
+#define NIC6_QM0_SECTION 0x9000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x571A900ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x571A908ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x571A910ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x571A918ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x571A920ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x571A928ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x571A930ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x571A938ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x571A940ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x571A948ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x571A950ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x571A958ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x571A960ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x571A968ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x571A970ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x571A978ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC6_QM0_AXUSER_SECURED_BASE 0x571AB00ull
+#define NIC6_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC6_QM0_AXUSER_SECURED_SECTION 0x8000
+#define NIC6_QM0_AXUSER_NONSECURED_BASE 0x571AB80ull
+#define NIC6_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC6_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC6_QM0_DBG_HBW_BASE 0x571AC00ull
+#define NIC6_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC6_QM0_DBG_HBW_SECTION 0x8000
+#define NIC6_QM0_DBG_LBW_BASE 0x571AC80ull
+#define NIC6_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC6_QM0_DBG_LBW_SECTION 0x1000
+#define NIC6_QM0_CGM_BASE 0x571AD80ull
+#define NIC6_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC6_QM0_CGM_SECTION 0x1000
+#define NIC6_QM0_SPECIAL_BASE 0x571AE80ull
+#define NIC6_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_QM0_SPECIAL_SECTION 0x4180
+#define NIC6_QPC0_BASE 0x571F000ull
+#define NIC6_QPC0_MAX_OFFSET 0x1000
+#define NIC6_QPC0_SECTION 0x7200
+#define NIC6_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x571F720ull
+#define NIC6_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x571F728ull
+#define NIC6_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x571F730ull
+#define NIC6_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x571F738ull
+#define NIC6_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x571F740ull
+#define NIC6_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x571F748ull
+#define NIC6_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x571F750ull
+#define NIC6_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x571F758ull
+#define NIC6_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x571F760ull
+#define NIC6_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x571F768ull
+#define NIC6_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x571F770ull
+#define NIC6_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x571F778ull
+#define NIC6_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x571F780ull
+#define NIC6_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x571F788ull
+#define NIC6_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x571F790ull
+#define NIC6_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x571F798ull
+#define NIC6_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x571F7A0ull
+#define NIC6_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x571F7A8ull
+#define NIC6_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x571F7B0ull
+#define NIC6_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x571F7B8ull
+#define NIC6_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x571F7C0ull
+#define NIC6_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x571F7C8ull
+#define NIC6_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x571F7D0ull
+#define NIC6_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x571F7D8ull
+#define NIC6_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x571F7E0ull
+#define NIC6_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x571F7E8ull
+#define NIC6_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x571F7F0ull
+#define NIC6_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x571F7F8ull
+#define NIC6_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x571F800ull
+#define NIC6_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x571F808ull
+#define NIC6_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x571F810ull
+#define NIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x571F818ull
+#define NIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC6_QPC0_AXUSER_CONG_QUE_BASE 0x571FB80ull
+#define NIC6_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC6_QPC0_AXUSER_RXWQE_BASE 0x571FBE0ull
+#define NIC6_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define NIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x571FC40ull
+#define NIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC6_QPC0_AXUSER_DB_FIFO_BASE 0x571FCA0ull
+#define NIC6_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x571FD00ull
+#define NIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC6_QPC0_AXUSER_ERR_FIFO_BASE 0x571FD60ull
+#define NIC6_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC6_QPC0_AXUSER_QPC_RESP_BASE 0x571FDC0ull
+#define NIC6_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC6_QPC0_AXUSER_QPC_REQ_BASE 0x571FE20ull
+#define NIC6_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC6_QPC0_SPECIAL_BASE 0x571FE80ull
+#define NIC6_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_QPC0_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5720000ull
+#define NIC6_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5720080ull
+#define NIC6_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5720100ull
+#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5720180ull
+#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_0_SPECIAL_BASE 0x5720E80ull
+#define NIC6_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_0_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5721000ull
+#define NIC6_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5721080ull
+#define NIC6_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5721100ull
+#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5721180ull
+#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_1_SPECIAL_BASE 0x5721E80ull
+#define NIC6_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_1_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5722000ull
+#define NIC6_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5722080ull
+#define NIC6_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5722100ull
+#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5722180ull
+#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_2_SPECIAL_BASE 0x5722E80ull
+#define NIC6_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_2_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5723000ull
+#define NIC6_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5723080ull
+#define NIC6_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5723100ull
+#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5723180ull
+#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_3_SPECIAL_BASE 0x5723E80ull
+#define NIC6_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_3_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5724000ull
+#define NIC6_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5724080ull
+#define NIC6_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5724100ull
+#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5724180ull
+#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_4_SPECIAL_BASE 0x5724E80ull
+#define NIC6_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_4_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5725000ull
+#define NIC6_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5725080ull
+#define NIC6_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5725100ull
+#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5725180ull
+#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_5_SPECIAL_BASE 0x5725E80ull
+#define NIC6_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_5_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5726000ull
+#define NIC6_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5726080ull
+#define NIC6_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5726100ull
+#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5726180ull
+#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_6_SPECIAL_BASE 0x5726E80ull
+#define NIC6_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_6_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5727000ull
+#define NIC6_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5727080ull
+#define NIC6_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5727100ull
+#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5727180ull
+#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_7_SPECIAL_BASE 0x5727E80ull
+#define NIC6_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_7_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5728000ull
+#define NIC6_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5728080ull
+#define NIC6_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5728100ull
+#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5728180ull
+#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_8_SPECIAL_BASE 0x5728E80ull
+#define NIC6_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_8_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5729000ull
+#define NIC6_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5729080ull
+#define NIC6_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5729100ull
+#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5729180ull
+#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_9_SPECIAL_BASE 0x5729E80ull
+#define NIC6_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_9_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_10_UNSECURE_DOORBELL0_BASE 0x572A000ull
+#define NIC6_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_10_UNSECURE_DOORBELL1_BASE 0x572A080ull
+#define NIC6_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x572A100ull
+#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x572A180ull
+#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_10_SPECIAL_BASE 0x572AE80ull
+#define NIC6_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_10_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_11_UNSECURE_DOORBELL0_BASE 0x572B000ull
+#define NIC6_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_11_UNSECURE_DOORBELL1_BASE 0x572B080ull
+#define NIC6_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x572B100ull
+#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x572B180ull
+#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_11_SPECIAL_BASE 0x572BE80ull
+#define NIC6_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_11_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_12_UNSECURE_DOORBELL0_BASE 0x572C000ull
+#define NIC6_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_12_UNSECURE_DOORBELL1_BASE 0x572C080ull
+#define NIC6_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x572C100ull
+#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x572C180ull
+#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_12_SPECIAL_BASE 0x572CE80ull
+#define NIC6_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_12_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_13_UNSECURE_DOORBELL0_BASE 0x572D000ull
+#define NIC6_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_13_UNSECURE_DOORBELL1_BASE 0x572D080ull
+#define NIC6_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x572D100ull
+#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x572D180ull
+#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_13_SPECIAL_BASE 0x572DE80ull
+#define NIC6_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_13_SPECIAL_SECTION 0x1800
+#define NIC6_UMR1_14_UNSECURE_DOORBELL0_BASE 0x572E000ull
+#define NIC6_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC6_UMR1_14_UNSECURE_DOORBELL1_BASE 0x572E080ull
+#define NIC6_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x572E100ull
+#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x572E180ull
+#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC6_UMR1_14_SPECIAL_BASE 0x572EE80ull
+#define NIC6_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_14_SPECIAL_SECTION 0x1180
+#define NIC6_QM_DCCM1_BASE 0x5730000ull
+#define NIC6_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC6_QM_DCCM1_SECTION 0x8000
+#define NIC6_QM_ARC_AUX1_BASE 0x5738000ull
+#define NIC6_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC6_QM_ARC_AUX1_SECTION 0xE800
+#define NIC6_QM_ARC_AUX1_SPECIAL_BASE 0x5738E80ull
+#define NIC6_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define NIC6_QM1_BASE 0x573A000ull
+#define NIC6_QM1_MAX_OFFSET 0x1000
+#define NIC6_QM1_SECTION 0x9000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x573A900ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x573A908ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x573A910ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x573A918ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x573A920ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x573A928ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x573A930ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x573A938ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x573A940ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x573A948ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x573A950ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x573A958ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x573A960ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x573A968ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x573A970ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x573A978ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC6_QM1_AXUSER_SECURED_BASE 0x573AB00ull
+#define NIC6_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC6_QM1_AXUSER_SECURED_SECTION 0x8000
+#define NIC6_QM1_AXUSER_NONSECURED_BASE 0x573AB80ull
+#define NIC6_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC6_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC6_QM1_DBG_HBW_BASE 0x573AC00ull
+#define NIC6_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC6_QM1_DBG_HBW_SECTION 0x8000
+#define NIC6_QM1_DBG_LBW_BASE 0x573AC80ull
+#define NIC6_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC6_QM1_DBG_LBW_SECTION 0x1000
+#define NIC6_QM1_CGM_BASE 0x573AD80ull
+#define NIC6_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC6_QM1_CGM_SECTION 0x1000
+#define NIC6_QM1_SPECIAL_BASE 0x573AE80ull
+#define NIC6_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_QM1_SPECIAL_SECTION 0x4180
+#define NIC6_QPC1_BASE 0x573F000ull
+#define NIC6_QPC1_MAX_OFFSET 0x1000
+#define NIC6_QPC1_SECTION 0x7200
+#define NIC6_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x573F720ull
+#define NIC6_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x573F728ull
+#define NIC6_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x573F730ull
+#define NIC6_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x573F738ull
+#define NIC6_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x573F740ull
+#define NIC6_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x573F748ull
+#define NIC6_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x573F750ull
+#define NIC6_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x573F758ull
+#define NIC6_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x573F760ull
+#define NIC6_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x573F768ull
+#define NIC6_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x573F770ull
+#define NIC6_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x573F778ull
+#define NIC6_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x573F780ull
+#define NIC6_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x573F788ull
+#define NIC6_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x573F790ull
+#define NIC6_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x573F798ull
+#define NIC6_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x573F7A0ull
+#define NIC6_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x573F7A8ull
+#define NIC6_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x573F7B0ull
+#define NIC6_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x573F7B8ull
+#define NIC6_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x573F7C0ull
+#define NIC6_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x573F7C8ull
+#define NIC6_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x573F7D0ull
+#define NIC6_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x573F7D8ull
+#define NIC6_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x573F7E0ull
+#define NIC6_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x573F7E8ull
+#define NIC6_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x573F7F0ull
+#define NIC6_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x573F7F8ull
+#define NIC6_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x573F800ull
+#define NIC6_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x573F808ull
+#define NIC6_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x573F810ull
+#define NIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x573F818ull
+#define NIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC6_QPC1_AXUSER_CONG_QUE_BASE 0x573FB80ull
+#define NIC6_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC6_QPC1_AXUSER_RXWQE_BASE 0x573FBE0ull
+#define NIC6_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define NIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x573FC40ull
+#define NIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC6_QPC1_AXUSER_DB_FIFO_BASE 0x573FCA0ull
+#define NIC6_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x573FD00ull
+#define NIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC6_QPC1_AXUSER_ERR_FIFO_BASE 0x573FD60ull
+#define NIC6_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC6_QPC1_AXUSER_QPC_RESP_BASE 0x573FDC0ull
+#define NIC6_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC6_QPC1_AXUSER_QPC_REQ_BASE 0x573FE20ull
+#define NIC6_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC6_QPC1_SPECIAL_BASE 0x573FE80ull
+#define NIC6_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_QPC1_SPECIAL_SECTION 0x8180
+#define NIC6_TMR_BASE 0x5748000ull
+#define NIC6_TMR_MAX_OFFSET 0x1000
+#define NIC6_TMR_SECTION 0xD600
+#define NIC6_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5748D60ull
+#define NIC6_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC6_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define NIC6_TMR_AXUSER_TMR_FIFO_BASE 0x5748DC0ull
+#define NIC6_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC6_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define NIC6_TMR_AXUSER_TMR_FSM_BASE 0x5748E20ull
+#define NIC6_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC6_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define NIC6_TMR_SPECIAL_BASE 0x5748E80ull
+#define NIC6_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_TMR_SPECIAL_SECTION 0x1800
+#define NIC6_RXB_CORE_BASE 0x5749000ull
+#define NIC6_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC6_RXB_CORE_SECTION 0x6100
+#define NIC6_RXB_CORE_SCT_AWUSER_BASE 0x5749610ull
+#define NIC6_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC6_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define NIC6_RXB_CORE_SPECIAL_BASE 0x5749E80ull
+#define NIC6_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_RXB_CORE_SPECIAL_SECTION 0x1800
+#define NIC6_RXE0_BASE 0x574A000ull
+#define NIC6_RXE0_MAX_OFFSET 0x1000
+#define NIC6_RXE0_SECTION 0x9000
+#define NIC6_RXE0_WQE_ARUSER_BASE 0x574A900ull
+#define NIC6_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC6_RXE0_WQE_ARUSER_SECTION 0x5800
+#define NIC6_RXE0_SPECIAL_BASE 0x574AE80ull
+#define NIC6_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_RXE0_SPECIAL_SECTION 0x1800
+#define NIC6_RXE1_BASE 0x574B000ull
+#define NIC6_RXE1_MAX_OFFSET 0x1000
+#define NIC6_RXE1_SECTION 0x9000
+#define NIC6_RXE1_WQE_ARUSER_BASE 0x574B900ull
+#define NIC6_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC6_RXE1_WQE_ARUSER_SECTION 0x5800
+#define NIC6_RXE1_SPECIAL_BASE 0x574BE80ull
+#define NIC6_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_RXE1_SPECIAL_SECTION 0x1800
+#define NIC6_RXE0_AXUSER_AXUSER_CQ0_BASE 0x574C000ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ1_BASE 0x574C050ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ2_BASE 0x574C0A0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ3_BASE 0x574C0F0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ4_BASE 0x574C140ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ5_BASE 0x574C190ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ6_BASE 0x574C1E0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ7_BASE 0x574C230ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ8_BASE 0x574C280ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ9_BASE 0x574C2D0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ10_BASE 0x574C320ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ11_BASE 0x574C370ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ12_BASE 0x574C3C0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ13_BASE 0x574C410ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ14_BASE 0x574C460ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ15_BASE 0x574C4B0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ16_BASE 0x574C500ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ17_BASE 0x574C550ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ18_BASE 0x574C5A0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ19_BASE 0x574C5F0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ20_BASE 0x574C640ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ21_BASE 0x574C690ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ22_BASE 0x574C6E0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ23_BASE 0x574C730ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ24_BASE 0x574C780ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ25_BASE 0x574C7D0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ26_BASE 0x574C820ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ27_BASE 0x574C870ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ28_BASE 0x574C8C0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ29_BASE 0x574C910ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ30_BASE 0x574C960ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ31_BASE 0x574C9B0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC6_RXE0_AXUSER_SPECIAL_BASE 0x574CE80ull
+#define NIC6_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define NIC6_RXE1_AXUSER_AXUSER_CQ0_BASE 0x574D000ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ1_BASE 0x574D050ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ2_BASE 0x574D0A0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ3_BASE 0x574D0F0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ4_BASE 0x574D140ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ5_BASE 0x574D190ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ6_BASE 0x574D1E0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ7_BASE 0x574D230ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ8_BASE 0x574D280ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ9_BASE 0x574D2D0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ10_BASE 0x574D320ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ11_BASE 0x574D370ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ12_BASE 0x574D3C0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ13_BASE 0x574D410ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ14_BASE 0x574D460ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ15_BASE 0x574D4B0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ16_BASE 0x574D500ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ17_BASE 0x574D550ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ18_BASE 0x574D5A0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ19_BASE 0x574D5F0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ20_BASE 0x574D640ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ21_BASE 0x574D690ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ22_BASE 0x574D6E0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ23_BASE 0x574D730ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ24_BASE 0x574D780ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ25_BASE 0x574D7D0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ26_BASE 0x574D820ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ27_BASE 0x574D870ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ28_BASE 0x574D8C0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ29_BASE 0x574D910ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ30_BASE 0x574D960ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ31_BASE 0x574D9B0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC6_RXE1_AXUSER_SPECIAL_BASE 0x574DE80ull
+#define NIC6_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define NIC6_TXS0_BASE 0x5750000ull
+#define NIC6_TXS0_MAX_OFFSET 0x1000
+#define NIC6_TXS0_SECTION 0xE800
+#define NIC6_TXS0_SPECIAL_BASE 0x5750E80ull
+#define NIC6_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_TXS0_SPECIAL_SECTION 0x1800
+#define NIC6_TXS1_BASE 0x5751000ull
+#define NIC6_TXS1_MAX_OFFSET 0x1000
+#define NIC6_TXS1_SECTION 0xE800
+#define NIC6_TXS1_SPECIAL_BASE 0x5751E80ull
+#define NIC6_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_TXS1_SPECIAL_SECTION 0x1800
+#define NIC6_TXE0_BASE 0x5752000ull
+#define NIC6_TXE0_MAX_OFFSET 0x1000
+#define NIC6_TXE0_SECTION 0xE800
+#define NIC6_TXE0_SPECIAL_BASE 0x5752E80ull
+#define NIC6_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_TXE0_SPECIAL_SECTION 0x1800
+#define NIC6_TXE1_BASE 0x5753000ull
+#define NIC6_TXE1_MAX_OFFSET 0x1000
+#define NIC6_TXE1_SECTION 0xE800
+#define NIC6_TXE1_SPECIAL_BASE 0x5753E80ull
+#define NIC6_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_TXE1_SPECIAL_SECTION 0x1800
+#define NIC6_TXB_BASE 0x5754000ull
+#define NIC6_TXB_MAX_OFFSET 0x1000
+#define NIC6_TXB_SECTION 0xE800
+#define NIC6_TXB_SPECIAL_BASE 0x5754E80ull
+#define NIC6_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_TXB_SPECIAL_SECTION 0x1800
+#define NIC6_MSTR_IF_RR_SHRD_HBW_BASE 0x5755000ull
+#define NIC6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define NIC6_MSTR_IF_RR_PRVT_HBW_BASE 0x5755200ull
+#define NIC6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define NIC6_MSTR_IF_RR_SHRD_LBW_BASE 0x5755400ull
+#define NIC6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define NIC6_MSTR_IF_RR_PRVT_LBW_BASE 0x5755600ull
+#define NIC6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define NIC6_MSTR_IF_E2E_CRDT_BASE 0x5755800ull
+#define NIC6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC6_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define NIC6_MSTR_IF_AXUSER_BASE 0x5755A80ull
+#define NIC6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC6_MSTR_IF_AXUSER_SECTION 0x8000
+#define NIC6_MSTR_IF_DBG_HBW_BASE 0x5755B00ull
+#define NIC6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC6_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define NIC6_MSTR_IF_DBG_LBW_BASE 0x5755B80ull
+#define NIC6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC6_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define NIC6_MSTR_IF_CORE_HBW_BASE 0x5755C00ull
+#define NIC6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC6_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define NIC6_MSTR_IF_CORE_LBW_BASE 0x5755D80ull
+#define NIC6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC6_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define NIC6_MSTR_IF_SPECIAL_BASE 0x5755E80ull
+#define NIC6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_MSTR_IF_SPECIAL_SECTION 0x1800
+#define NIC6_TX_AXUSER_BASE 0x5756000ull
+#define NIC6_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC6_TX_AXUSER_SECTION 0x2000
+#define NIC6_SERDES0_BASE 0x5758000ull
+#define NIC6_SERDES0_MAX_OFFSET 0x3E40
+#define NIC6_SERDES0_SECTION 0x4000
+#define NIC6_SERDES1_BASE 0x575C000ull
+#define NIC6_SERDES1_MAX_OFFSET 0x3E40
+#define NIC6_SERDES1_SECTION 0x4000
+#define NIC6_PHY_BASE 0x5760000ull
+#define NIC6_PHY_MAX_OFFSET 0x1000
+#define NIC6_PHY_SECTION 0xE800
+#define NIC6_PHY_SPECIAL_BASE 0x5760E80ull
+#define NIC6_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_PHY_SPECIAL_SECTION 0x7180
+#define PRT6_MAC_AUX_BASE 0x5768000ull
+#define PRT6_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT6_MAC_AUX_SECTION 0xE800
+#define PRT6_MAC_AUX_SPECIAL_BASE 0x5768E80ull
+#define PRT6_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT6_MAC_AUX_SPECIAL_SECTION 0x1800
+#define PRT6_MAC_CORE_BASE 0x5769000ull
+#define PRT6_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT6_MAC_CORE_SECTION 0xE800
+#define PRT6_MAC_CORE_SPECIAL_BASE 0x5769E80ull
+#define PRT6_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT6_MAC_CORE_SPECIAL_SECTION 0x1800
+#define NIC6_MAC_RS_FEC_BASE 0x576A000ull
+#define NIC6_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC6_MAC_RS_FEC_SECTION 0x1000
+#define NIC6_MAC_GLOB_STAT_CONTROL_REG_BASE 0x576B000ull
+#define NIC6_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC6_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define NIC6_MAC_GLOB_STAT_RX0_BASE 0x576B100ull
+#define NIC6_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC6_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define NIC6_MAC_GLOB_STAT_RX1_BASE 0x576B18Cull
+#define NIC6_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC6_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define NIC6_MAC_GLOB_STAT_RX2_BASE 0x576B218ull
+#define NIC6_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC6_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define NIC6_MAC_GLOB_STAT_RX3_BASE 0x576B2A4ull
+#define NIC6_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC6_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define NIC6_MAC_GLOB_STAT_TX0_BASE 0x576B330ull
+#define NIC6_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC6_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define NIC6_MAC_GLOB_STAT_TX1_BASE 0x576B398ull
+#define NIC6_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC6_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define NIC6_MAC_GLOB_STAT_TX2_BASE 0x576B400ull
+#define NIC6_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC6_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define NIC6_MAC_GLOB_STAT_TX3_BASE 0x576B468ull
+#define NIC6_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC6_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define NIC6_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x576B800ull
+#define NIC6_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC6_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define NIC6_MAC_CH0_MAC_PCS_BASE 0x576C000ull
+#define NIC6_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC6_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define NIC6_MAC_CH0_MAC_128_BASE 0x576C400ull
+#define NIC6_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC6_MAC_CH0_MAC_128_SECTION 0x4000
+#define NIC6_MAC_CH0_MAC_AN_BASE 0x576C800ull
+#define NIC6_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC6_MAC_CH0_MAC_AN_SECTION 0x8000
+#define NIC6_MAC_CH1_MAC_PCS_BASE 0x576D000ull
+#define NIC6_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC6_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define NIC6_MAC_CH1_MAC_128_BASE 0x576D400ull
+#define NIC6_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC6_MAC_CH1_MAC_128_SECTION 0x4000
+#define NIC6_MAC_CH1_MAC_AN_BASE 0x576D800ull
+#define NIC6_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC6_MAC_CH1_MAC_AN_SECTION 0x8000
+#define NIC6_MAC_CH2_MAC_PCS_BASE 0x576E000ull
+#define NIC6_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC6_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define NIC6_MAC_CH2_MAC_128_BASE 0x576E400ull
+#define NIC6_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC6_MAC_CH2_MAC_128_SECTION 0x4000
+#define NIC6_MAC_CH2_MAC_AN_BASE 0x576E800ull
+#define NIC6_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC6_MAC_CH2_MAC_AN_SECTION 0x8000
+#define NIC6_MAC_CH3_MAC_PCS_BASE 0x576F000ull
+#define NIC6_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC6_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define NIC6_MAC_CH3_MAC_128_BASE 0x576F400ull
+#define NIC6_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC6_MAC_CH3_MAC_128_SECTION 0x4000
+#define NIC6_MAC_CH3_MAC_AN_BASE 0x576F800ull
+#define NIC6_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC6_MAC_CH3_MAC_AN_SECTION 0x10800
+#define NIC7_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5780000ull
+#define NIC7_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5780080ull
+#define NIC7_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5780100ull
+#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5780180ull
+#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_0_SPECIAL_BASE 0x5780E80ull
+#define NIC7_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_0_SPECIAL_SECTION 0x1800
+#define NIC7_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5781000ull
+#define NIC7_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5781080ull
+#define NIC7_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5781100ull
+#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5781180ull
+#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_1_SPECIAL_BASE 0x5781E80ull
+#define NIC7_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_1_SPECIAL_SECTION 0x1800
+#define NIC7_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5782000ull
+#define NIC7_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5782080ull
+#define NIC7_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5782100ull
+#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5782180ull
+#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_2_SPECIAL_BASE 0x5782E80ull
+#define NIC7_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_2_SPECIAL_SECTION 0x1800
+#define NIC7_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5783000ull
+#define NIC7_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5783080ull
+#define NIC7_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5783100ull
+#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5783180ull
+#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_3_SPECIAL_BASE 0x5783E80ull
+#define NIC7_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_3_SPECIAL_SECTION 0x1800
+#define NIC7_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5784000ull
+#define NIC7_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5784080ull
+#define NIC7_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5784100ull
+#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5784180ull
+#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_4_SPECIAL_BASE 0x5784E80ull
+#define NIC7_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_4_SPECIAL_SECTION 0x1800
+#define NIC7_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5785000ull
+#define NIC7_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5785080ull
+#define NIC7_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5785100ull
+#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5785180ull
+#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_5_SPECIAL_BASE 0x5785E80ull
+#define NIC7_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_5_SPECIAL_SECTION 0x1800
+#define NIC7_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5786000ull
+#define NIC7_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5786080ull
+#define NIC7_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5786100ull
+#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5786180ull
+#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_6_SPECIAL_BASE 0x5786E80ull
+#define NIC7_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_6_SPECIAL_SECTION 0x1800
+#define NIC7_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5787000ull
+#define NIC7_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5787080ull
+#define NIC7_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5787100ull
+#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5787180ull
+#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_7_SPECIAL_BASE 0x5787E80ull
+#define NIC7_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_7_SPECIAL_SECTION 0x1800
+#define NIC7_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5788000ull
+#define NIC7_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5788080ull
+#define NIC7_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5788100ull
+#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5788180ull
+#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_8_SPECIAL_BASE 0x5788E80ull
+#define NIC7_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_8_SPECIAL_SECTION 0x1800
+#define NIC7_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5789000ull
+#define NIC7_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5789080ull
+#define NIC7_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5789100ull
+#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5789180ull
+#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_9_SPECIAL_BASE 0x5789E80ull
+#define NIC7_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_9_SPECIAL_SECTION 0x1800
+#define NIC7_UMR0_10_UNSECURE_DOORBELL0_BASE 0x578A000ull
+#define NIC7_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_10_UNSECURE_DOORBELL1_BASE 0x578A080ull
+#define NIC7_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x578A100ull
+#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x578A180ull
+#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_10_SPECIAL_BASE 0x578AE80ull
+#define NIC7_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_10_SPECIAL_SECTION 0x1800
+#define NIC7_UMR0_11_UNSECURE_DOORBELL0_BASE 0x578B000ull
+#define NIC7_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_11_UNSECURE_DOORBELL1_BASE 0x578B080ull
+#define NIC7_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x578B100ull
+#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x578B180ull
+#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_11_SPECIAL_BASE 0x578BE80ull
+#define NIC7_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_11_SPECIAL_SECTION 0x1800
+#define NIC7_UMR0_12_UNSECURE_DOORBELL0_BASE 0x578C000ull
+#define NIC7_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_12_UNSECURE_DOORBELL1_BASE 0x578C080ull
+#define NIC7_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x578C100ull
+#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x578C180ull
+#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_12_SPECIAL_BASE 0x578CE80ull
+#define NIC7_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_12_SPECIAL_SECTION 0x1800
+#define NIC7_UMR0_13_UNSECURE_DOORBELL0_BASE 0x578D000ull
+#define NIC7_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_13_UNSECURE_DOORBELL1_BASE 0x578D080ull
+#define NIC7_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x578D100ull
+#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x578D180ull
+#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_13_SPECIAL_BASE 0x578DE80ull
+#define NIC7_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_13_SPECIAL_SECTION 0x1800
+#define NIC7_UMR0_14_UNSECURE_DOORBELL0_BASE 0x578E000ull
+#define NIC7_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR0_14_UNSECURE_DOORBELL1_BASE 0x578E080ull
+#define NIC7_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x578E100ull
+#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x578E180ull
+#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR0_14_SPECIAL_BASE 0x578EE80ull
+#define NIC7_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_14_SPECIAL_SECTION 0x1180
+#define NIC7_QM_DCCM0_BASE 0x5790000ull
+#define NIC7_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC7_QM_DCCM0_SECTION 0x8000
+#define NIC7_QM_ARC_AUX0_BASE 0x5798000ull
+#define NIC7_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC7_QM_ARC_AUX0_SECTION 0xE800
+#define NIC7_QM_ARC_AUX0_SPECIAL_BASE 0x5798E80ull
+#define NIC7_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define NIC7_QM0_BASE 0x579A000ull
+#define NIC7_QM0_MAX_OFFSET 0x1000
+#define NIC7_QM0_SECTION 0x9000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x579A900ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x579A908ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x579A910ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x579A918ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x579A920ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x579A928ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x579A930ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x579A938ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x579A940ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x579A948ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x579A950ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x579A958ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x579A960ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x579A968ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x579A970ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x579A978ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC7_QM0_AXUSER_SECURED_BASE 0x579AB00ull
+#define NIC7_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC7_QM0_AXUSER_SECURED_SECTION 0x8000
+#define NIC7_QM0_AXUSER_NONSECURED_BASE 0x579AB80ull
+#define NIC7_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC7_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC7_QM0_DBG_HBW_BASE 0x579AC00ull
+#define NIC7_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC7_QM0_DBG_HBW_SECTION 0x8000
+#define NIC7_QM0_DBG_LBW_BASE 0x579AC80ull
+#define NIC7_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC7_QM0_DBG_LBW_SECTION 0x1000
+#define NIC7_QM0_CGM_BASE 0x579AD80ull
+#define NIC7_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC7_QM0_CGM_SECTION 0x1000
+#define NIC7_QM0_SPECIAL_BASE 0x579AE80ull
+#define NIC7_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_QM0_SPECIAL_SECTION 0x4180
+#define NIC7_QPC0_BASE 0x579F000ull
+#define NIC7_QPC0_MAX_OFFSET 0x1000
+#define NIC7_QPC0_SECTION 0x7200
+#define NIC7_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x579F720ull
+#define NIC7_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x579F728ull
+#define NIC7_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x579F730ull
+#define NIC7_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x579F738ull
+#define NIC7_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x579F740ull
+#define NIC7_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x579F748ull
+#define NIC7_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x579F750ull
+#define NIC7_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x579F758ull
+#define NIC7_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x579F760ull
+#define NIC7_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x579F768ull
+#define NIC7_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x579F770ull
+#define NIC7_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x579F778ull
+#define NIC7_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x579F780ull
+#define NIC7_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x579F788ull
+#define NIC7_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x579F790ull
+#define NIC7_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x579F798ull
+#define NIC7_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x579F7A0ull
+#define NIC7_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x579F7A8ull
+#define NIC7_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x579F7B0ull
+#define NIC7_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x579F7B8ull
+#define NIC7_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x579F7C0ull
+#define NIC7_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x579F7C8ull
+#define NIC7_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x579F7D0ull
+#define NIC7_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x579F7D8ull
+#define NIC7_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x579F7E0ull
+#define NIC7_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x579F7E8ull
+#define NIC7_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x579F7F0ull
+#define NIC7_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x579F7F8ull
+#define NIC7_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x579F800ull
+#define NIC7_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x579F808ull
+#define NIC7_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x579F810ull
+#define NIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x579F818ull
+#define NIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC7_QPC0_AXUSER_CONG_QUE_BASE 0x579FB80ull
+#define NIC7_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC7_QPC0_AXUSER_RXWQE_BASE 0x579FBE0ull
+#define NIC7_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define NIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x579FC40ull
+#define NIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC7_QPC0_AXUSER_DB_FIFO_BASE 0x579FCA0ull
+#define NIC7_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x579FD00ull
+#define NIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC7_QPC0_AXUSER_ERR_FIFO_BASE 0x579FD60ull
+#define NIC7_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC7_QPC0_AXUSER_QPC_RESP_BASE 0x579FDC0ull
+#define NIC7_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC7_QPC0_AXUSER_QPC_REQ_BASE 0x579FE20ull
+#define NIC7_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC7_QPC0_SPECIAL_BASE 0x579FE80ull
+#define NIC7_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_QPC0_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_0_UNSECURE_DOORBELL0_BASE 0x57A0000ull
+#define NIC7_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_0_UNSECURE_DOORBELL1_BASE 0x57A0080ull
+#define NIC7_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x57A0100ull
+#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x57A0180ull
+#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_0_SPECIAL_BASE 0x57A0E80ull
+#define NIC7_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_0_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_1_UNSECURE_DOORBELL0_BASE 0x57A1000ull
+#define NIC7_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_1_UNSECURE_DOORBELL1_BASE 0x57A1080ull
+#define NIC7_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x57A1100ull
+#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x57A1180ull
+#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_1_SPECIAL_BASE 0x57A1E80ull
+#define NIC7_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_1_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_2_UNSECURE_DOORBELL0_BASE 0x57A2000ull
+#define NIC7_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_2_UNSECURE_DOORBELL1_BASE 0x57A2080ull
+#define NIC7_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x57A2100ull
+#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x57A2180ull
+#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_2_SPECIAL_BASE 0x57A2E80ull
+#define NIC7_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_2_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_3_UNSECURE_DOORBELL0_BASE 0x57A3000ull
+#define NIC7_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_3_UNSECURE_DOORBELL1_BASE 0x57A3080ull
+#define NIC7_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x57A3100ull
+#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x57A3180ull
+#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_3_SPECIAL_BASE 0x57A3E80ull
+#define NIC7_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_3_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_4_UNSECURE_DOORBELL0_BASE 0x57A4000ull
+#define NIC7_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_4_UNSECURE_DOORBELL1_BASE 0x57A4080ull
+#define NIC7_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x57A4100ull
+#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x57A4180ull
+#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_4_SPECIAL_BASE 0x57A4E80ull
+#define NIC7_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_4_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_5_UNSECURE_DOORBELL0_BASE 0x57A5000ull
+#define NIC7_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_5_UNSECURE_DOORBELL1_BASE 0x57A5080ull
+#define NIC7_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x57A5100ull
+#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x57A5180ull
+#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_5_SPECIAL_BASE 0x57A5E80ull
+#define NIC7_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_5_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_6_UNSECURE_DOORBELL0_BASE 0x57A6000ull
+#define NIC7_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_6_UNSECURE_DOORBELL1_BASE 0x57A6080ull
+#define NIC7_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x57A6100ull
+#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x57A6180ull
+#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_6_SPECIAL_BASE 0x57A6E80ull
+#define NIC7_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_6_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_7_UNSECURE_DOORBELL0_BASE 0x57A7000ull
+#define NIC7_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_7_UNSECURE_DOORBELL1_BASE 0x57A7080ull
+#define NIC7_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x57A7100ull
+#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x57A7180ull
+#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_7_SPECIAL_BASE 0x57A7E80ull
+#define NIC7_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_7_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_8_UNSECURE_DOORBELL0_BASE 0x57A8000ull
+#define NIC7_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_8_UNSECURE_DOORBELL1_BASE 0x57A8080ull
+#define NIC7_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x57A8100ull
+#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x57A8180ull
+#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_8_SPECIAL_BASE 0x57A8E80ull
+#define NIC7_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_8_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_9_UNSECURE_DOORBELL0_BASE 0x57A9000ull
+#define NIC7_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_9_UNSECURE_DOORBELL1_BASE 0x57A9080ull
+#define NIC7_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x57A9100ull
+#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x57A9180ull
+#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_9_SPECIAL_BASE 0x57A9E80ull
+#define NIC7_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_9_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_10_UNSECURE_DOORBELL0_BASE 0x57AA000ull
+#define NIC7_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_10_UNSECURE_DOORBELL1_BASE 0x57AA080ull
+#define NIC7_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x57AA100ull
+#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x57AA180ull
+#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_10_SPECIAL_BASE 0x57AAE80ull
+#define NIC7_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_10_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_11_UNSECURE_DOORBELL0_BASE 0x57AB000ull
+#define NIC7_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_11_UNSECURE_DOORBELL1_BASE 0x57AB080ull
+#define NIC7_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x57AB100ull
+#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x57AB180ull
+#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_11_SPECIAL_BASE 0x57ABE80ull
+#define NIC7_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_11_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_12_UNSECURE_DOORBELL0_BASE 0x57AC000ull
+#define NIC7_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_12_UNSECURE_DOORBELL1_BASE 0x57AC080ull
+#define NIC7_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x57AC100ull
+#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x57AC180ull
+#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_12_SPECIAL_BASE 0x57ACE80ull
+#define NIC7_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_12_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_13_UNSECURE_DOORBELL0_BASE 0x57AD000ull
+#define NIC7_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_13_UNSECURE_DOORBELL1_BASE 0x57AD080ull
+#define NIC7_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x57AD100ull
+#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x57AD180ull
+#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_13_SPECIAL_BASE 0x57ADE80ull
+#define NIC7_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_13_SPECIAL_SECTION 0x1800
+#define NIC7_UMR1_14_UNSECURE_DOORBELL0_BASE 0x57AE000ull
+#define NIC7_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC7_UMR1_14_UNSECURE_DOORBELL1_BASE 0x57AE080ull
+#define NIC7_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x57AE100ull
+#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x57AE180ull
+#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC7_UMR1_14_SPECIAL_BASE 0x57AEE80ull
+#define NIC7_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_14_SPECIAL_SECTION 0x1180
+#define NIC7_QM_DCCM1_BASE 0x57B0000ull
+#define NIC7_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC7_QM_DCCM1_SECTION 0x8000
+#define NIC7_QM_ARC_AUX1_BASE 0x57B8000ull
+#define NIC7_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC7_QM_ARC_AUX1_SECTION 0xE800
+#define NIC7_QM_ARC_AUX1_SPECIAL_BASE 0x57B8E80ull
+#define NIC7_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define NIC7_QM1_BASE 0x57BA000ull
+#define NIC7_QM1_MAX_OFFSET 0x1000
+#define NIC7_QM1_SECTION 0x9000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x57BA900ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x57BA908ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x57BA910ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x57BA918ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x57BA920ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x57BA928ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x57BA930ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x57BA938ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x57BA940ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x57BA948ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x57BA950ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x57BA958ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x57BA960ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x57BA968ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x57BA970ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x57BA978ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC7_QM1_AXUSER_SECURED_BASE 0x57BAB00ull
+#define NIC7_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC7_QM1_AXUSER_SECURED_SECTION 0x8000
+#define NIC7_QM1_AXUSER_NONSECURED_BASE 0x57BAB80ull
+#define NIC7_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC7_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC7_QM1_DBG_HBW_BASE 0x57BAC00ull
+#define NIC7_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC7_QM1_DBG_HBW_SECTION 0x8000
+#define NIC7_QM1_DBG_LBW_BASE 0x57BAC80ull
+#define NIC7_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC7_QM1_DBG_LBW_SECTION 0x1000
+#define NIC7_QM1_CGM_BASE 0x57BAD80ull
+#define NIC7_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC7_QM1_CGM_SECTION 0x1000
+#define NIC7_QM1_SPECIAL_BASE 0x57BAE80ull
+#define NIC7_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_QM1_SPECIAL_SECTION 0x4180
+#define NIC7_QPC1_BASE 0x57BF000ull
+#define NIC7_QPC1_MAX_OFFSET 0x1000
+#define NIC7_QPC1_SECTION 0x7200
+#define NIC7_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x57BF720ull
+#define NIC7_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x57BF728ull
+#define NIC7_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x57BF730ull
+#define NIC7_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x57BF738ull
+#define NIC7_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x57BF740ull
+#define NIC7_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x57BF748ull
+#define NIC7_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x57BF750ull
+#define NIC7_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x57BF758ull
+#define NIC7_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x57BF760ull
+#define NIC7_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x57BF768ull
+#define NIC7_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x57BF770ull
+#define NIC7_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x57BF778ull
+#define NIC7_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x57BF780ull
+#define NIC7_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x57BF788ull
+#define NIC7_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x57BF790ull
+#define NIC7_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x57BF798ull
+#define NIC7_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x57BF7A0ull
+#define NIC7_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x57BF7A8ull
+#define NIC7_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x57BF7B0ull
+#define NIC7_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x57BF7B8ull
+#define NIC7_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x57BF7C0ull
+#define NIC7_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x57BF7C8ull
+#define NIC7_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x57BF7D0ull
+#define NIC7_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x57BF7D8ull
+#define NIC7_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x57BF7E0ull
+#define NIC7_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x57BF7E8ull
+#define NIC7_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x57BF7F0ull
+#define NIC7_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x57BF7F8ull
+#define NIC7_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x57BF800ull
+#define NIC7_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x57BF808ull
+#define NIC7_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x57BF810ull
+#define NIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x57BF818ull
+#define NIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC7_QPC1_AXUSER_CONG_QUE_BASE 0x57BFB80ull
+#define NIC7_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC7_QPC1_AXUSER_RXWQE_BASE 0x57BFBE0ull
+#define NIC7_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define NIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x57BFC40ull
+#define NIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC7_QPC1_AXUSER_DB_FIFO_BASE 0x57BFCA0ull
+#define NIC7_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x57BFD00ull
+#define NIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC7_QPC1_AXUSER_ERR_FIFO_BASE 0x57BFD60ull
+#define NIC7_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC7_QPC1_AXUSER_QPC_RESP_BASE 0x57BFDC0ull
+#define NIC7_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC7_QPC1_AXUSER_QPC_REQ_BASE 0x57BFE20ull
+#define NIC7_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC7_QPC1_SPECIAL_BASE 0x57BFE80ull
+#define NIC7_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_QPC1_SPECIAL_SECTION 0x8180
+#define NIC7_TMR_BASE 0x57C8000ull
+#define NIC7_TMR_MAX_OFFSET 0x1000
+#define NIC7_TMR_SECTION 0xD600
+#define NIC7_TMR_AXUSER_TMR_FREE_LIST_BASE 0x57C8D60ull
+#define NIC7_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC7_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define NIC7_TMR_AXUSER_TMR_FIFO_BASE 0x57C8DC0ull
+#define NIC7_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC7_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define NIC7_TMR_AXUSER_TMR_FSM_BASE 0x57C8E20ull
+#define NIC7_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC7_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define NIC7_TMR_SPECIAL_BASE 0x57C8E80ull
+#define NIC7_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_TMR_SPECIAL_SECTION 0x1800
+#define NIC7_RXB_CORE_BASE 0x57C9000ull
+#define NIC7_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC7_RXB_CORE_SECTION 0x6100
+#define NIC7_RXB_CORE_SCT_AWUSER_BASE 0x57C9610ull
+#define NIC7_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC7_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define NIC7_RXB_CORE_SPECIAL_BASE 0x57C9E80ull
+#define NIC7_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_RXB_CORE_SPECIAL_SECTION 0x1800
+#define NIC7_RXE0_BASE 0x57CA000ull
+#define NIC7_RXE0_MAX_OFFSET 0x1000
+#define NIC7_RXE0_SECTION 0x9000
+#define NIC7_RXE0_WQE_ARUSER_BASE 0x57CA900ull
+#define NIC7_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC7_RXE0_WQE_ARUSER_SECTION 0x5800
+#define NIC7_RXE0_SPECIAL_BASE 0x57CAE80ull
+#define NIC7_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_RXE0_SPECIAL_SECTION 0x1800
+#define NIC7_RXE1_BASE 0x57CB000ull
+#define NIC7_RXE1_MAX_OFFSET 0x1000
+#define NIC7_RXE1_SECTION 0x9000
+#define NIC7_RXE1_WQE_ARUSER_BASE 0x57CB900ull
+#define NIC7_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC7_RXE1_WQE_ARUSER_SECTION 0x5800
+#define NIC7_RXE1_SPECIAL_BASE 0x57CBE80ull
+#define NIC7_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_RXE1_SPECIAL_SECTION 0x1800
+#define NIC7_RXE0_AXUSER_AXUSER_CQ0_BASE 0x57CC000ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ1_BASE 0x57CC050ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ2_BASE 0x57CC0A0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ3_BASE 0x57CC0F0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ4_BASE 0x57CC140ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ5_BASE 0x57CC190ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ6_BASE 0x57CC1E0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ7_BASE 0x57CC230ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ8_BASE 0x57CC280ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ9_BASE 0x57CC2D0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ10_BASE 0x57CC320ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ11_BASE 0x57CC370ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ12_BASE 0x57CC3C0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ13_BASE 0x57CC410ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ14_BASE 0x57CC460ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ15_BASE 0x57CC4B0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ16_BASE 0x57CC500ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ17_BASE 0x57CC550ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ18_BASE 0x57CC5A0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ19_BASE 0x57CC5F0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ20_BASE 0x57CC640ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ21_BASE 0x57CC690ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ22_BASE 0x57CC6E0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ23_BASE 0x57CC730ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ24_BASE 0x57CC780ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ25_BASE 0x57CC7D0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ26_BASE 0x57CC820ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ27_BASE 0x57CC870ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ28_BASE 0x57CC8C0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ29_BASE 0x57CC910ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ30_BASE 0x57CC960ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ31_BASE 0x57CC9B0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC7_RXE0_AXUSER_SPECIAL_BASE 0x57CCE80ull
+#define NIC7_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define NIC7_RXE1_AXUSER_AXUSER_CQ0_BASE 0x57CD000ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ1_BASE 0x57CD050ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ2_BASE 0x57CD0A0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ3_BASE 0x57CD0F0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ4_BASE 0x57CD140ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ5_BASE 0x57CD190ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ6_BASE 0x57CD1E0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ7_BASE 0x57CD230ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ8_BASE 0x57CD280ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ9_BASE 0x57CD2D0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ10_BASE 0x57CD320ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ11_BASE 0x57CD370ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ12_BASE 0x57CD3C0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ13_BASE 0x57CD410ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ14_BASE 0x57CD460ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ15_BASE 0x57CD4B0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ16_BASE 0x57CD500ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ17_BASE 0x57CD550ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ18_BASE 0x57CD5A0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ19_BASE 0x57CD5F0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ20_BASE 0x57CD640ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ21_BASE 0x57CD690ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ22_BASE 0x57CD6E0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ23_BASE 0x57CD730ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ24_BASE 0x57CD780ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ25_BASE 0x57CD7D0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ26_BASE 0x57CD820ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ27_BASE 0x57CD870ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ28_BASE 0x57CD8C0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ29_BASE 0x57CD910ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ30_BASE 0x57CD960ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ31_BASE 0x57CD9B0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC7_RXE1_AXUSER_SPECIAL_BASE 0x57CDE80ull
+#define NIC7_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define NIC7_TXS0_BASE 0x57D0000ull
+#define NIC7_TXS0_MAX_OFFSET 0x1000
+#define NIC7_TXS0_SECTION 0xE800
+#define NIC7_TXS0_SPECIAL_BASE 0x57D0E80ull
+#define NIC7_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_TXS0_SPECIAL_SECTION 0x1800
+#define NIC7_TXS1_BASE 0x57D1000ull
+#define NIC7_TXS1_MAX_OFFSET 0x1000
+#define NIC7_TXS1_SECTION 0xE800
+#define NIC7_TXS1_SPECIAL_BASE 0x57D1E80ull
+#define NIC7_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_TXS1_SPECIAL_SECTION 0x1800
+#define NIC7_TXE0_BASE 0x57D2000ull
+#define NIC7_TXE0_MAX_OFFSET 0x1000
+#define NIC7_TXE0_SECTION 0xE800
+#define NIC7_TXE0_SPECIAL_BASE 0x57D2E80ull
+#define NIC7_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_TXE0_SPECIAL_SECTION 0x1800
+#define NIC7_TXE1_BASE 0x57D3000ull
+#define NIC7_TXE1_MAX_OFFSET 0x1000
+#define NIC7_TXE1_SECTION 0xE800
+#define NIC7_TXE1_SPECIAL_BASE 0x57D3E80ull
+#define NIC7_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_TXE1_SPECIAL_SECTION 0x1800
+#define NIC7_TXB_BASE 0x57D4000ull
+#define NIC7_TXB_MAX_OFFSET 0x1000
+#define NIC7_TXB_SECTION 0xE800
+#define NIC7_TXB_SPECIAL_BASE 0x57D4E80ull
+#define NIC7_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_TXB_SPECIAL_SECTION 0x1800
+#define NIC7_MSTR_IF_RR_SHRD_HBW_BASE 0x57D5000ull
+#define NIC7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define NIC7_MSTR_IF_RR_PRVT_HBW_BASE 0x57D5200ull
+#define NIC7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define NIC7_MSTR_IF_RR_SHRD_LBW_BASE 0x57D5400ull
+#define NIC7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define NIC7_MSTR_IF_RR_PRVT_LBW_BASE 0x57D5600ull
+#define NIC7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define NIC7_MSTR_IF_E2E_CRDT_BASE 0x57D5800ull
+#define NIC7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC7_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define NIC7_MSTR_IF_AXUSER_BASE 0x57D5A80ull
+#define NIC7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC7_MSTR_IF_AXUSER_SECTION 0x8000
+#define NIC7_MSTR_IF_DBG_HBW_BASE 0x57D5B00ull
+#define NIC7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC7_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define NIC7_MSTR_IF_DBG_LBW_BASE 0x57D5B80ull
+#define NIC7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC7_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define NIC7_MSTR_IF_CORE_HBW_BASE 0x57D5C00ull
+#define NIC7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC7_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define NIC7_MSTR_IF_CORE_LBW_BASE 0x57D5D80ull
+#define NIC7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC7_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define NIC7_MSTR_IF_SPECIAL_BASE 0x57D5E80ull
+#define NIC7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_MSTR_IF_SPECIAL_SECTION 0x1800
+#define NIC7_TX_AXUSER_BASE 0x57D6000ull
+#define NIC7_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC7_TX_AXUSER_SECTION 0x2000
+#define NIC7_SERDES0_BASE 0x57D8000ull
+#define NIC7_SERDES0_MAX_OFFSET 0x3E40
+#define NIC7_SERDES0_SECTION 0x4000
+#define NIC7_SERDES1_BASE 0x57DC000ull
+#define NIC7_SERDES1_MAX_OFFSET 0x3E40
+#define NIC7_SERDES1_SECTION 0x4000
+#define NIC7_PHY_BASE 0x57E0000ull
+#define NIC7_PHY_MAX_OFFSET 0x1000
+#define NIC7_PHY_SECTION 0xE800
+#define NIC7_PHY_SPECIAL_BASE 0x57E0E80ull
+#define NIC7_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_PHY_SPECIAL_SECTION 0x7180
+#define PRT7_MAC_AUX_BASE 0x57E8000ull
+#define PRT7_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT7_MAC_AUX_SECTION 0xE800
+#define PRT7_MAC_AUX_SPECIAL_BASE 0x57E8E80ull
+#define PRT7_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT7_MAC_AUX_SPECIAL_SECTION 0x1800
+#define PRT7_MAC_CORE_BASE 0x57E9000ull
+#define PRT7_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT7_MAC_CORE_SECTION 0xE800
+#define PRT7_MAC_CORE_SPECIAL_BASE 0x57E9E80ull
+#define PRT7_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT7_MAC_CORE_SPECIAL_SECTION 0x1800
+#define NIC7_MAC_RS_FEC_BASE 0x57EA000ull
+#define NIC7_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC7_MAC_RS_FEC_SECTION 0x1000
+#define NIC7_MAC_GLOB_STAT_CONTROL_REG_BASE 0x57EB000ull
+#define NIC7_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC7_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define NIC7_MAC_GLOB_STAT_RX0_BASE 0x57EB100ull
+#define NIC7_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC7_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define NIC7_MAC_GLOB_STAT_RX1_BASE 0x57EB18Cull
+#define NIC7_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC7_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define NIC7_MAC_GLOB_STAT_RX2_BASE 0x57EB218ull
+#define NIC7_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC7_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define NIC7_MAC_GLOB_STAT_RX3_BASE 0x57EB2A4ull
+#define NIC7_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC7_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define NIC7_MAC_GLOB_STAT_TX0_BASE 0x57EB330ull
+#define NIC7_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC7_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define NIC7_MAC_GLOB_STAT_TX1_BASE 0x57EB398ull
+#define NIC7_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC7_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define NIC7_MAC_GLOB_STAT_TX2_BASE 0x57EB400ull
+#define NIC7_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC7_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define NIC7_MAC_GLOB_STAT_TX3_BASE 0x57EB468ull
+#define NIC7_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC7_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define NIC7_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x57EB800ull
+#define NIC7_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC7_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define NIC7_MAC_CH0_MAC_PCS_BASE 0x57EC000ull
+#define NIC7_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC7_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define NIC7_MAC_CH0_MAC_128_BASE 0x57EC400ull
+#define NIC7_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC7_MAC_CH0_MAC_128_SECTION 0x4000
+#define NIC7_MAC_CH0_MAC_AN_BASE 0x57EC800ull
+#define NIC7_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC7_MAC_CH0_MAC_AN_SECTION 0x8000
+#define NIC7_MAC_CH1_MAC_PCS_BASE 0x57ED000ull
+#define NIC7_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC7_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define NIC7_MAC_CH1_MAC_128_BASE 0x57ED400ull
+#define NIC7_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC7_MAC_CH1_MAC_128_SECTION 0x4000
+#define NIC7_MAC_CH1_MAC_AN_BASE 0x57ED800ull
+#define NIC7_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC7_MAC_CH1_MAC_AN_SECTION 0x8000
+#define NIC7_MAC_CH2_MAC_PCS_BASE 0x57EE000ull
+#define NIC7_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC7_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define NIC7_MAC_CH2_MAC_128_BASE 0x57EE400ull
+#define NIC7_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC7_MAC_CH2_MAC_128_SECTION 0x4000
+#define NIC7_MAC_CH2_MAC_AN_BASE 0x57EE800ull
+#define NIC7_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC7_MAC_CH2_MAC_AN_SECTION 0x8000
+#define NIC7_MAC_CH3_MAC_PCS_BASE 0x57EF000ull
+#define NIC7_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC7_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define NIC7_MAC_CH3_MAC_128_BASE 0x57EF400ull
+#define NIC7_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC7_MAC_CH3_MAC_128_SECTION 0x4000
+#define NIC7_MAC_CH3_MAC_AN_BASE 0x57EF800ull
+#define NIC7_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC7_MAC_CH3_MAC_AN_SECTION 0x10800
+#define NIC8_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5800000ull
+#define NIC8_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5800080ull
+#define NIC8_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5800100ull
+#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5800180ull
+#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_0_SPECIAL_BASE 0x5800E80ull
+#define NIC8_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_0_SPECIAL_SECTION 0x1800
+#define NIC8_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5801000ull
+#define NIC8_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5801080ull
+#define NIC8_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5801100ull
+#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5801180ull
+#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_1_SPECIAL_BASE 0x5801E80ull
+#define NIC8_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_1_SPECIAL_SECTION 0x1800
+#define NIC8_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5802000ull
+#define NIC8_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5802080ull
+#define NIC8_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5802100ull
+#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5802180ull
+#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_2_SPECIAL_BASE 0x5802E80ull
+#define NIC8_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_2_SPECIAL_SECTION 0x1800
+#define NIC8_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5803000ull
+#define NIC8_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5803080ull
+#define NIC8_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5803100ull
+#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5803180ull
+#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_3_SPECIAL_BASE 0x5803E80ull
+#define NIC8_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_3_SPECIAL_SECTION 0x1800
+#define NIC8_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5804000ull
+#define NIC8_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5804080ull
+#define NIC8_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5804100ull
+#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5804180ull
+#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_4_SPECIAL_BASE 0x5804E80ull
+#define NIC8_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_4_SPECIAL_SECTION 0x1800
+#define NIC8_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5805000ull
+#define NIC8_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5805080ull
+#define NIC8_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5805100ull
+#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5805180ull
+#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_5_SPECIAL_BASE 0x5805E80ull
+#define NIC8_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_5_SPECIAL_SECTION 0x1800
+#define NIC8_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5806000ull
+#define NIC8_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5806080ull
+#define NIC8_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5806100ull
+#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5806180ull
+#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_6_SPECIAL_BASE 0x5806E80ull
+#define NIC8_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_6_SPECIAL_SECTION 0x1800
+#define NIC8_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5807000ull
+#define NIC8_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5807080ull
+#define NIC8_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5807100ull
+#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5807180ull
+#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_7_SPECIAL_BASE 0x5807E80ull
+#define NIC8_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_7_SPECIAL_SECTION 0x1800
+#define NIC8_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5808000ull
+#define NIC8_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5808080ull
+#define NIC8_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5808100ull
+#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5808180ull
+#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_8_SPECIAL_BASE 0x5808E80ull
+#define NIC8_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_8_SPECIAL_SECTION 0x1800
+#define NIC8_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5809000ull
+#define NIC8_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5809080ull
+#define NIC8_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5809100ull
+#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5809180ull
+#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_9_SPECIAL_BASE 0x5809E80ull
+#define NIC8_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_9_SPECIAL_SECTION 0x1800
+#define NIC8_UMR0_10_UNSECURE_DOORBELL0_BASE 0x580A000ull
+#define NIC8_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_10_UNSECURE_DOORBELL1_BASE 0x580A080ull
+#define NIC8_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x580A100ull
+#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x580A180ull
+#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_10_SPECIAL_BASE 0x580AE80ull
+#define NIC8_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_10_SPECIAL_SECTION 0x1800
+#define NIC8_UMR0_11_UNSECURE_DOORBELL0_BASE 0x580B000ull
+#define NIC8_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_11_UNSECURE_DOORBELL1_BASE 0x580B080ull
+#define NIC8_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x580B100ull
+#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x580B180ull
+#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_11_SPECIAL_BASE 0x580BE80ull
+#define NIC8_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_11_SPECIAL_SECTION 0x1800
+#define NIC8_UMR0_12_UNSECURE_DOORBELL0_BASE 0x580C000ull
+#define NIC8_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_12_UNSECURE_DOORBELL1_BASE 0x580C080ull
+#define NIC8_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x580C100ull
+#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x580C180ull
+#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_12_SPECIAL_BASE 0x580CE80ull
+#define NIC8_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_12_SPECIAL_SECTION 0x1800
+#define NIC8_UMR0_13_UNSECURE_DOORBELL0_BASE 0x580D000ull
+#define NIC8_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_13_UNSECURE_DOORBELL1_BASE 0x580D080ull
+#define NIC8_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x580D100ull
+#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x580D180ull
+#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_13_SPECIAL_BASE 0x580DE80ull
+#define NIC8_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_13_SPECIAL_SECTION 0x1800
+#define NIC8_UMR0_14_UNSECURE_DOORBELL0_BASE 0x580E000ull
+#define NIC8_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR0_14_UNSECURE_DOORBELL1_BASE 0x580E080ull
+#define NIC8_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x580E100ull
+#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x580E180ull
+#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR0_14_SPECIAL_BASE 0x580EE80ull
+#define NIC8_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_14_SPECIAL_SECTION 0x1180
+#define NIC8_QM_DCCM0_BASE 0x5810000ull
+#define NIC8_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC8_QM_DCCM0_SECTION 0x8000
+#define NIC8_QM_ARC_AUX0_BASE 0x5818000ull
+#define NIC8_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC8_QM_ARC_AUX0_SECTION 0xE800
+#define NIC8_QM_ARC_AUX0_SPECIAL_BASE 0x5818E80ull
+#define NIC8_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define NIC8_QM0_BASE 0x581A000ull
+#define NIC8_QM0_MAX_OFFSET 0x1000
+#define NIC8_QM0_SECTION 0x9000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x581A900ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x581A908ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x581A910ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x581A918ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x581A920ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x581A928ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x581A930ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x581A938ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x581A940ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x581A948ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x581A950ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x581A958ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x581A960ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x581A968ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x581A970ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x581A978ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC8_QM0_AXUSER_SECURED_BASE 0x581AB00ull
+#define NIC8_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC8_QM0_AXUSER_SECURED_SECTION 0x8000
+#define NIC8_QM0_AXUSER_NONSECURED_BASE 0x581AB80ull
+#define NIC8_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC8_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC8_QM0_DBG_HBW_BASE 0x581AC00ull
+#define NIC8_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC8_QM0_DBG_HBW_SECTION 0x8000
+#define NIC8_QM0_DBG_LBW_BASE 0x581AC80ull
+#define NIC8_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC8_QM0_DBG_LBW_SECTION 0x1000
+#define NIC8_QM0_CGM_BASE 0x581AD80ull
+#define NIC8_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC8_QM0_CGM_SECTION 0x1000
+#define NIC8_QM0_SPECIAL_BASE 0x581AE80ull
+#define NIC8_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_QM0_SPECIAL_SECTION 0x4180
+#define NIC8_QPC0_BASE 0x581F000ull
+#define NIC8_QPC0_MAX_OFFSET 0x1000
+#define NIC8_QPC0_SECTION 0x7200
+#define NIC8_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x581F720ull
+#define NIC8_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x581F728ull
+#define NIC8_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x581F730ull
+#define NIC8_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x581F738ull
+#define NIC8_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x581F740ull
+#define NIC8_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x581F748ull
+#define NIC8_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x581F750ull
+#define NIC8_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x581F758ull
+#define NIC8_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x581F760ull
+#define NIC8_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x581F768ull
+#define NIC8_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x581F770ull
+#define NIC8_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x581F778ull
+#define NIC8_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x581F780ull
+#define NIC8_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x581F788ull
+#define NIC8_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x581F790ull
+#define NIC8_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x581F798ull
+#define NIC8_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x581F7A0ull
+#define NIC8_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x581F7A8ull
+#define NIC8_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x581F7B0ull
+#define NIC8_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x581F7B8ull
+#define NIC8_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x581F7C0ull
+#define NIC8_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x581F7C8ull
+#define NIC8_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x581F7D0ull
+#define NIC8_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x581F7D8ull
+#define NIC8_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x581F7E0ull
+#define NIC8_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x581F7E8ull
+#define NIC8_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x581F7F0ull
+#define NIC8_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x581F7F8ull
+#define NIC8_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x581F800ull
+#define NIC8_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x581F808ull
+#define NIC8_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x581F810ull
+#define NIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x581F818ull
+#define NIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC8_QPC0_AXUSER_CONG_QUE_BASE 0x581FB80ull
+#define NIC8_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC8_QPC0_AXUSER_RXWQE_BASE 0x581FBE0ull
+#define NIC8_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define NIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x581FC40ull
+#define NIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC8_QPC0_AXUSER_DB_FIFO_BASE 0x581FCA0ull
+#define NIC8_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x581FD00ull
+#define NIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC8_QPC0_AXUSER_ERR_FIFO_BASE 0x581FD60ull
+#define NIC8_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC8_QPC0_AXUSER_QPC_RESP_BASE 0x581FDC0ull
+#define NIC8_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC8_QPC0_AXUSER_QPC_REQ_BASE 0x581FE20ull
+#define NIC8_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC8_QPC0_SPECIAL_BASE 0x581FE80ull
+#define NIC8_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_QPC0_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5820000ull
+#define NIC8_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5820080ull
+#define NIC8_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5820100ull
+#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5820180ull
+#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_0_SPECIAL_BASE 0x5820E80ull
+#define NIC8_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_0_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5821000ull
+#define NIC8_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5821080ull
+#define NIC8_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5821100ull
+#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5821180ull
+#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_1_SPECIAL_BASE 0x5821E80ull
+#define NIC8_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_1_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5822000ull
+#define NIC8_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5822080ull
+#define NIC8_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5822100ull
+#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5822180ull
+#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_2_SPECIAL_BASE 0x5822E80ull
+#define NIC8_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_2_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5823000ull
+#define NIC8_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5823080ull
+#define NIC8_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5823100ull
+#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5823180ull
+#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_3_SPECIAL_BASE 0x5823E80ull
+#define NIC8_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_3_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5824000ull
+#define NIC8_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5824080ull
+#define NIC8_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5824100ull
+#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5824180ull
+#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_4_SPECIAL_BASE 0x5824E80ull
+#define NIC8_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_4_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5825000ull
+#define NIC8_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5825080ull
+#define NIC8_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5825100ull
+#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5825180ull
+#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_5_SPECIAL_BASE 0x5825E80ull
+#define NIC8_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_5_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5826000ull
+#define NIC8_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5826080ull
+#define NIC8_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5826100ull
+#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5826180ull
+#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_6_SPECIAL_BASE 0x5826E80ull
+#define NIC8_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_6_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5827000ull
+#define NIC8_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5827080ull
+#define NIC8_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5827100ull
+#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5827180ull
+#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_7_SPECIAL_BASE 0x5827E80ull
+#define NIC8_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_7_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5828000ull
+#define NIC8_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5828080ull
+#define NIC8_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5828100ull
+#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5828180ull
+#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_8_SPECIAL_BASE 0x5828E80ull
+#define NIC8_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_8_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5829000ull
+#define NIC8_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5829080ull
+#define NIC8_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5829100ull
+#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5829180ull
+#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_9_SPECIAL_BASE 0x5829E80ull
+#define NIC8_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_9_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_10_UNSECURE_DOORBELL0_BASE 0x582A000ull
+#define NIC8_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_10_UNSECURE_DOORBELL1_BASE 0x582A080ull
+#define NIC8_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x582A100ull
+#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x582A180ull
+#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_10_SPECIAL_BASE 0x582AE80ull
+#define NIC8_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_10_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_11_UNSECURE_DOORBELL0_BASE 0x582B000ull
+#define NIC8_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_11_UNSECURE_DOORBELL1_BASE 0x582B080ull
+#define NIC8_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x582B100ull
+#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x582B180ull
+#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_11_SPECIAL_BASE 0x582BE80ull
+#define NIC8_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_11_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_12_UNSECURE_DOORBELL0_BASE 0x582C000ull
+#define NIC8_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_12_UNSECURE_DOORBELL1_BASE 0x582C080ull
+#define NIC8_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x582C100ull
+#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x582C180ull
+#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_12_SPECIAL_BASE 0x582CE80ull
+#define NIC8_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_12_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_13_UNSECURE_DOORBELL0_BASE 0x582D000ull
+#define NIC8_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_13_UNSECURE_DOORBELL1_BASE 0x582D080ull
+#define NIC8_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x582D100ull
+#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x582D180ull
+#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_13_SPECIAL_BASE 0x582DE80ull
+#define NIC8_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_13_SPECIAL_SECTION 0x1800
+#define NIC8_UMR1_14_UNSECURE_DOORBELL0_BASE 0x582E000ull
+#define NIC8_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC8_UMR1_14_UNSECURE_DOORBELL1_BASE 0x582E080ull
+#define NIC8_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x582E100ull
+#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x582E180ull
+#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC8_UMR1_14_SPECIAL_BASE 0x582EE80ull
+#define NIC8_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_14_SPECIAL_SECTION 0x1180
+#define NIC8_QM_DCCM1_BASE 0x5830000ull
+#define NIC8_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC8_QM_DCCM1_SECTION 0x8000
+#define NIC8_QM_ARC_AUX1_BASE 0x5838000ull
+#define NIC8_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC8_QM_ARC_AUX1_SECTION 0xE800
+#define NIC8_QM_ARC_AUX1_SPECIAL_BASE 0x5838E80ull
+#define NIC8_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define NIC8_QM1_BASE 0x583A000ull
+#define NIC8_QM1_MAX_OFFSET 0x1000
+#define NIC8_QM1_SECTION 0x9000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x583A900ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x583A908ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x583A910ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x583A918ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x583A920ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x583A928ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x583A930ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x583A938ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x583A940ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x583A948ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x583A950ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x583A958ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x583A960ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x583A968ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x583A970ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x583A978ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC8_QM1_AXUSER_SECURED_BASE 0x583AB00ull
+#define NIC8_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC8_QM1_AXUSER_SECURED_SECTION 0x8000
+#define NIC8_QM1_AXUSER_NONSECURED_BASE 0x583AB80ull
+#define NIC8_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC8_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC8_QM1_DBG_HBW_BASE 0x583AC00ull
+#define NIC8_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC8_QM1_DBG_HBW_SECTION 0x8000
+#define NIC8_QM1_DBG_LBW_BASE 0x583AC80ull
+#define NIC8_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC8_QM1_DBG_LBW_SECTION 0x1000
+#define NIC8_QM1_CGM_BASE 0x583AD80ull
+#define NIC8_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC8_QM1_CGM_SECTION 0x1000
+#define NIC8_QM1_SPECIAL_BASE 0x583AE80ull
+#define NIC8_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_QM1_SPECIAL_SECTION 0x4180
+#define NIC8_QPC1_BASE 0x583F000ull
+#define NIC8_QPC1_MAX_OFFSET 0x1000
+#define NIC8_QPC1_SECTION 0x7200
+#define NIC8_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x583F720ull
+#define NIC8_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x583F728ull
+#define NIC8_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x583F730ull
+#define NIC8_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x583F738ull
+#define NIC8_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x583F740ull
+#define NIC8_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x583F748ull
+#define NIC8_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x583F750ull
+#define NIC8_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x583F758ull
+#define NIC8_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x583F760ull
+#define NIC8_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x583F768ull
+#define NIC8_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x583F770ull
+#define NIC8_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x583F778ull
+#define NIC8_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x583F780ull
+#define NIC8_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x583F788ull
+#define NIC8_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x583F790ull
+#define NIC8_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x583F798ull
+#define NIC8_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x583F7A0ull
+#define NIC8_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x583F7A8ull
+#define NIC8_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x583F7B0ull
+#define NIC8_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x583F7B8ull
+#define NIC8_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x583F7C0ull
+#define NIC8_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x583F7C8ull
+#define NIC8_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x583F7D0ull
+#define NIC8_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x583F7D8ull
+#define NIC8_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x583F7E0ull
+#define NIC8_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x583F7E8ull
+#define NIC8_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x583F7F0ull
+#define NIC8_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x583F7F8ull
+#define NIC8_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x583F800ull
+#define NIC8_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x583F808ull
+#define NIC8_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x583F810ull
+#define NIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x583F818ull
+#define NIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC8_QPC1_AXUSER_CONG_QUE_BASE 0x583FB80ull
+#define NIC8_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC8_QPC1_AXUSER_RXWQE_BASE 0x583FBE0ull
+#define NIC8_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define NIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x583FC40ull
+#define NIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC8_QPC1_AXUSER_DB_FIFO_BASE 0x583FCA0ull
+#define NIC8_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x583FD00ull
+#define NIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC8_QPC1_AXUSER_ERR_FIFO_BASE 0x583FD60ull
+#define NIC8_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC8_QPC1_AXUSER_QPC_RESP_BASE 0x583FDC0ull
+#define NIC8_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC8_QPC1_AXUSER_QPC_REQ_BASE 0x583FE20ull
+#define NIC8_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC8_QPC1_SPECIAL_BASE 0x583FE80ull
+#define NIC8_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_QPC1_SPECIAL_SECTION 0x8180
+#define NIC8_TMR_BASE 0x5848000ull
+#define NIC8_TMR_MAX_OFFSET 0x1000
+#define NIC8_TMR_SECTION 0xD600
+#define NIC8_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5848D60ull
+#define NIC8_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC8_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define NIC8_TMR_AXUSER_TMR_FIFO_BASE 0x5848DC0ull
+#define NIC8_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC8_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define NIC8_TMR_AXUSER_TMR_FSM_BASE 0x5848E20ull
+#define NIC8_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC8_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define NIC8_TMR_SPECIAL_BASE 0x5848E80ull
+#define NIC8_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_TMR_SPECIAL_SECTION 0x1800
+#define NIC8_RXB_CORE_BASE 0x5849000ull
+#define NIC8_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC8_RXB_CORE_SECTION 0x6100
+#define NIC8_RXB_CORE_SCT_AWUSER_BASE 0x5849610ull
+#define NIC8_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC8_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define NIC8_RXB_CORE_SPECIAL_BASE 0x5849E80ull
+#define NIC8_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_RXB_CORE_SPECIAL_SECTION 0x1800
+#define NIC8_RXE0_BASE 0x584A000ull
+#define NIC8_RXE0_MAX_OFFSET 0x1000
+#define NIC8_RXE0_SECTION 0x9000
+#define NIC8_RXE0_WQE_ARUSER_BASE 0x584A900ull
+#define NIC8_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC8_RXE0_WQE_ARUSER_SECTION 0x5800
+#define NIC8_RXE0_SPECIAL_BASE 0x584AE80ull
+#define NIC8_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_RXE0_SPECIAL_SECTION 0x1800
+#define NIC8_RXE1_BASE 0x584B000ull
+#define NIC8_RXE1_MAX_OFFSET 0x1000
+#define NIC8_RXE1_SECTION 0x9000
+#define NIC8_RXE1_WQE_ARUSER_BASE 0x584B900ull
+#define NIC8_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC8_RXE1_WQE_ARUSER_SECTION 0x5800
+#define NIC8_RXE1_SPECIAL_BASE 0x584BE80ull
+#define NIC8_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_RXE1_SPECIAL_SECTION 0x1800
+#define NIC8_RXE0_AXUSER_AXUSER_CQ0_BASE 0x584C000ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ1_BASE 0x584C050ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ2_BASE 0x584C0A0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ3_BASE 0x584C0F0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ4_BASE 0x584C140ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ5_BASE 0x584C190ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ6_BASE 0x584C1E0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ7_BASE 0x584C230ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ8_BASE 0x584C280ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ9_BASE 0x584C2D0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ10_BASE 0x584C320ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ11_BASE 0x584C370ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ12_BASE 0x584C3C0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ13_BASE 0x584C410ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ14_BASE 0x584C460ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ15_BASE 0x584C4B0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ16_BASE 0x584C500ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ17_BASE 0x584C550ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ18_BASE 0x584C5A0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ19_BASE 0x584C5F0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ20_BASE 0x584C640ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ21_BASE 0x584C690ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ22_BASE 0x584C6E0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ23_BASE 0x584C730ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ24_BASE 0x584C780ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ25_BASE 0x584C7D0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ26_BASE 0x584C820ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ27_BASE 0x584C870ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ28_BASE 0x584C8C0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ29_BASE 0x584C910ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ30_BASE 0x584C960ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ31_BASE 0x584C9B0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC8_RXE0_AXUSER_SPECIAL_BASE 0x584CE80ull
+#define NIC8_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define NIC8_RXE1_AXUSER_AXUSER_CQ0_BASE 0x584D000ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ1_BASE 0x584D050ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ2_BASE 0x584D0A0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ3_BASE 0x584D0F0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ4_BASE 0x584D140ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ5_BASE 0x584D190ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ6_BASE 0x584D1E0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ7_BASE 0x584D230ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ8_BASE 0x584D280ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ9_BASE 0x584D2D0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ10_BASE 0x584D320ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ11_BASE 0x584D370ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ12_BASE 0x584D3C0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ13_BASE 0x584D410ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ14_BASE 0x584D460ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ15_BASE 0x584D4B0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ16_BASE 0x584D500ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ17_BASE 0x584D550ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ18_BASE 0x584D5A0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ19_BASE 0x584D5F0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ20_BASE 0x584D640ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ21_BASE 0x584D690ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ22_BASE 0x584D6E0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ23_BASE 0x584D730ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ24_BASE 0x584D780ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ25_BASE 0x584D7D0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ26_BASE 0x584D820ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ27_BASE 0x584D870ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ28_BASE 0x584D8C0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ29_BASE 0x584D910ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ30_BASE 0x584D960ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ31_BASE 0x584D9B0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC8_RXE1_AXUSER_SPECIAL_BASE 0x584DE80ull
+#define NIC8_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define NIC8_TXS0_BASE 0x5850000ull
+#define NIC8_TXS0_MAX_OFFSET 0x1000
+#define NIC8_TXS0_SECTION 0xE800
+#define NIC8_TXS0_SPECIAL_BASE 0x5850E80ull
+#define NIC8_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_TXS0_SPECIAL_SECTION 0x1800
+#define NIC8_TXS1_BASE 0x5851000ull
+#define NIC8_TXS1_MAX_OFFSET 0x1000
+#define NIC8_TXS1_SECTION 0xE800
+#define NIC8_TXS1_SPECIAL_BASE 0x5851E80ull
+#define NIC8_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_TXS1_SPECIAL_SECTION 0x1800
+#define NIC8_TXE0_BASE 0x5852000ull
+#define NIC8_TXE0_MAX_OFFSET 0x1000
+#define NIC8_TXE0_SECTION 0xE800
+#define NIC8_TXE0_SPECIAL_BASE 0x5852E80ull
+#define NIC8_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_TXE0_SPECIAL_SECTION 0x1800
+#define NIC8_TXE1_BASE 0x5853000ull
+#define NIC8_TXE1_MAX_OFFSET 0x1000
+#define NIC8_TXE1_SECTION 0xE800
+#define NIC8_TXE1_SPECIAL_BASE 0x5853E80ull
+#define NIC8_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_TXE1_SPECIAL_SECTION 0x1800
+#define NIC8_TXB_BASE 0x5854000ull
+#define NIC8_TXB_MAX_OFFSET 0x1000
+#define NIC8_TXB_SECTION 0xE800
+#define NIC8_TXB_SPECIAL_BASE 0x5854E80ull
+#define NIC8_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_TXB_SPECIAL_SECTION 0x1800
+#define NIC8_MSTR_IF_RR_SHRD_HBW_BASE 0x5855000ull
+#define NIC8_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC8_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define NIC8_MSTR_IF_RR_PRVT_HBW_BASE 0x5855200ull
+#define NIC8_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC8_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define NIC8_MSTR_IF_RR_SHRD_LBW_BASE 0x5855400ull
+#define NIC8_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC8_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define NIC8_MSTR_IF_RR_PRVT_LBW_BASE 0x5855600ull
+#define NIC8_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC8_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define NIC8_MSTR_IF_E2E_CRDT_BASE 0x5855800ull
+#define NIC8_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC8_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define NIC8_MSTR_IF_AXUSER_BASE 0x5855A80ull
+#define NIC8_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC8_MSTR_IF_AXUSER_SECTION 0x8000
+#define NIC8_MSTR_IF_DBG_HBW_BASE 0x5855B00ull
+#define NIC8_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC8_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define NIC8_MSTR_IF_DBG_LBW_BASE 0x5855B80ull
+#define NIC8_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC8_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define NIC8_MSTR_IF_CORE_HBW_BASE 0x5855C00ull
+#define NIC8_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC8_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define NIC8_MSTR_IF_CORE_LBW_BASE 0x5855D80ull
+#define NIC8_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC8_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define NIC8_MSTR_IF_SPECIAL_BASE 0x5855E80ull
+#define NIC8_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_MSTR_IF_SPECIAL_SECTION 0x1800
+#define NIC8_TX_AXUSER_BASE 0x5856000ull
+#define NIC8_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC8_TX_AXUSER_SECTION 0x2000
+#define NIC8_SERDES0_BASE 0x5858000ull
+#define NIC8_SERDES0_MAX_OFFSET 0x3E40
+#define NIC8_SERDES0_SECTION 0x4000
+#define NIC8_SERDES1_BASE 0x585C000ull
+#define NIC8_SERDES1_MAX_OFFSET 0x3E40
+#define NIC8_SERDES1_SECTION 0x4000
+#define NIC8_PHY_BASE 0x5860000ull
+#define NIC8_PHY_MAX_OFFSET 0x1000
+#define NIC8_PHY_SECTION 0xE800
+#define NIC8_PHY_SPECIAL_BASE 0x5860E80ull
+#define NIC8_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_PHY_SPECIAL_SECTION 0x7180
+#define PRT8_MAC_AUX_BASE 0x5868000ull
+#define PRT8_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT8_MAC_AUX_SECTION 0xE800
+#define PRT8_MAC_AUX_SPECIAL_BASE 0x5868E80ull
+#define PRT8_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT8_MAC_AUX_SPECIAL_SECTION 0x1800
+#define PRT8_MAC_CORE_BASE 0x5869000ull
+#define PRT8_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT8_MAC_CORE_SECTION 0xE800
+#define PRT8_MAC_CORE_SPECIAL_BASE 0x5869E80ull
+#define PRT8_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT8_MAC_CORE_SPECIAL_SECTION 0x1800
+#define NIC8_MAC_RS_FEC_BASE 0x586A000ull
+#define NIC8_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC8_MAC_RS_FEC_SECTION 0x1000
+#define NIC8_MAC_GLOB_STAT_CONTROL_REG_BASE 0x586B000ull
+#define NIC8_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC8_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define NIC8_MAC_GLOB_STAT_RX0_BASE 0x586B100ull
+#define NIC8_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC8_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define NIC8_MAC_GLOB_STAT_RX1_BASE 0x586B18Cull
+#define NIC8_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC8_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define NIC8_MAC_GLOB_STAT_RX2_BASE 0x586B218ull
+#define NIC8_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC8_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define NIC8_MAC_GLOB_STAT_RX3_BASE 0x586B2A4ull
+#define NIC8_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC8_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define NIC8_MAC_GLOB_STAT_TX0_BASE 0x586B330ull
+#define NIC8_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC8_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define NIC8_MAC_GLOB_STAT_TX1_BASE 0x586B398ull
+#define NIC8_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC8_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define NIC8_MAC_GLOB_STAT_TX2_BASE 0x586B400ull
+#define NIC8_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC8_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define NIC8_MAC_GLOB_STAT_TX3_BASE 0x586B468ull
+#define NIC8_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC8_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define NIC8_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x586B800ull
+#define NIC8_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC8_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define NIC8_MAC_CH0_MAC_PCS_BASE 0x586C000ull
+#define NIC8_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC8_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define NIC8_MAC_CH0_MAC_128_BASE 0x586C400ull
+#define NIC8_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC8_MAC_CH0_MAC_128_SECTION 0x4000
+#define NIC8_MAC_CH0_MAC_AN_BASE 0x586C800ull
+#define NIC8_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC8_MAC_CH0_MAC_AN_SECTION 0x8000
+#define NIC8_MAC_CH1_MAC_PCS_BASE 0x586D000ull
+#define NIC8_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC8_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define NIC8_MAC_CH1_MAC_128_BASE 0x586D400ull
+#define NIC8_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC8_MAC_CH1_MAC_128_SECTION 0x4000
+#define NIC8_MAC_CH1_MAC_AN_BASE 0x586D800ull
+#define NIC8_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC8_MAC_CH1_MAC_AN_SECTION 0x8000
+#define NIC8_MAC_CH2_MAC_PCS_BASE 0x586E000ull
+#define NIC8_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC8_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define NIC8_MAC_CH2_MAC_128_BASE 0x586E400ull
+#define NIC8_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC8_MAC_CH2_MAC_128_SECTION 0x4000
+#define NIC8_MAC_CH2_MAC_AN_BASE 0x586E800ull
+#define NIC8_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC8_MAC_CH2_MAC_AN_SECTION 0x8000
+#define NIC8_MAC_CH3_MAC_PCS_BASE 0x586F000ull
+#define NIC8_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC8_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define NIC8_MAC_CH3_MAC_128_BASE 0x586F400ull
+#define NIC8_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC8_MAC_CH3_MAC_128_SECTION 0x4000
+#define NIC8_MAC_CH3_MAC_AN_BASE 0x586F800ull
+#define NIC8_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC8_MAC_CH3_MAC_AN_SECTION 0x10800
+#define NIC9_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5880000ull
+#define NIC9_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5880080ull
+#define NIC9_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5880100ull
+#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5880180ull
+#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_0_SPECIAL_BASE 0x5880E80ull
+#define NIC9_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_0_SPECIAL_SECTION 0x1800
+#define NIC9_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5881000ull
+#define NIC9_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5881080ull
+#define NIC9_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5881100ull
+#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5881180ull
+#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_1_SPECIAL_BASE 0x5881E80ull
+#define NIC9_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_1_SPECIAL_SECTION 0x1800
+#define NIC9_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5882000ull
+#define NIC9_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5882080ull
+#define NIC9_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5882100ull
+#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5882180ull
+#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_2_SPECIAL_BASE 0x5882E80ull
+#define NIC9_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_2_SPECIAL_SECTION 0x1800
+#define NIC9_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5883000ull
+#define NIC9_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5883080ull
+#define NIC9_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5883100ull
+#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5883180ull
+#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_3_SPECIAL_BASE 0x5883E80ull
+#define NIC9_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_3_SPECIAL_SECTION 0x1800
+#define NIC9_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5884000ull
+#define NIC9_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5884080ull
+#define NIC9_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5884100ull
+#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5884180ull
+#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_4_SPECIAL_BASE 0x5884E80ull
+#define NIC9_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_4_SPECIAL_SECTION 0x1800
+#define NIC9_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5885000ull
+#define NIC9_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5885080ull
+#define NIC9_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5885100ull
+#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5885180ull
+#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_5_SPECIAL_BASE 0x5885E80ull
+#define NIC9_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_5_SPECIAL_SECTION 0x1800
+#define NIC9_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5886000ull
+#define NIC9_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5886080ull
+#define NIC9_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5886100ull
+#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5886180ull
+#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_6_SPECIAL_BASE 0x5886E80ull
+#define NIC9_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_6_SPECIAL_SECTION 0x1800
+#define NIC9_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5887000ull
+#define NIC9_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5887080ull
+#define NIC9_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5887100ull
+#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5887180ull
+#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_7_SPECIAL_BASE 0x5887E80ull
+#define NIC9_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_7_SPECIAL_SECTION 0x1800
+#define NIC9_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5888000ull
+#define NIC9_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5888080ull
+#define NIC9_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5888100ull
+#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5888180ull
+#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_8_SPECIAL_BASE 0x5888E80ull
+#define NIC9_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_8_SPECIAL_SECTION 0x1800
+#define NIC9_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5889000ull
+#define NIC9_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5889080ull
+#define NIC9_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5889100ull
+#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5889180ull
+#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_9_SPECIAL_BASE 0x5889E80ull
+#define NIC9_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_9_SPECIAL_SECTION 0x1800
+#define NIC9_UMR0_10_UNSECURE_DOORBELL0_BASE 0x588A000ull
+#define NIC9_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_10_UNSECURE_DOORBELL1_BASE 0x588A080ull
+#define NIC9_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x588A100ull
+#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x588A180ull
+#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_10_SPECIAL_BASE 0x588AE80ull
+#define NIC9_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_10_SPECIAL_SECTION 0x1800
+#define NIC9_UMR0_11_UNSECURE_DOORBELL0_BASE 0x588B000ull
+#define NIC9_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_11_UNSECURE_DOORBELL1_BASE 0x588B080ull
+#define NIC9_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x588B100ull
+#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x588B180ull
+#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_11_SPECIAL_BASE 0x588BE80ull
+#define NIC9_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_11_SPECIAL_SECTION 0x1800
+#define NIC9_UMR0_12_UNSECURE_DOORBELL0_BASE 0x588C000ull
+#define NIC9_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_12_UNSECURE_DOORBELL1_BASE 0x588C080ull
+#define NIC9_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x588C100ull
+#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x588C180ull
+#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_12_SPECIAL_BASE 0x588CE80ull
+#define NIC9_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_12_SPECIAL_SECTION 0x1800
+#define NIC9_UMR0_13_UNSECURE_DOORBELL0_BASE 0x588D000ull
+#define NIC9_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_13_UNSECURE_DOORBELL1_BASE 0x588D080ull
+#define NIC9_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x588D100ull
+#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x588D180ull
+#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_13_SPECIAL_BASE 0x588DE80ull
+#define NIC9_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_13_SPECIAL_SECTION 0x1800
+#define NIC9_UMR0_14_UNSECURE_DOORBELL0_BASE 0x588E000ull
+#define NIC9_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR0_14_UNSECURE_DOORBELL1_BASE 0x588E080ull
+#define NIC9_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x588E100ull
+#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x588E180ull
+#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR0_14_SPECIAL_BASE 0x588EE80ull
+#define NIC9_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_14_SPECIAL_SECTION 0x1180
+#define NIC9_QM_DCCM0_BASE 0x5890000ull
+#define NIC9_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC9_QM_DCCM0_SECTION 0x8000
+#define NIC9_QM_ARC_AUX0_BASE 0x5898000ull
+#define NIC9_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC9_QM_ARC_AUX0_SECTION 0xE800
+#define NIC9_QM_ARC_AUX0_SPECIAL_BASE 0x5898E80ull
+#define NIC9_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define NIC9_QM0_BASE 0x589A000ull
+#define NIC9_QM0_MAX_OFFSET 0x1000
+#define NIC9_QM0_SECTION 0x9000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x589A900ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x589A908ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x589A910ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x589A918ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x589A920ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x589A928ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x589A930ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x589A938ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x589A940ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x589A948ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x589A950ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x589A958ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x589A960ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x589A968ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x589A970ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x589A978ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC9_QM0_AXUSER_SECURED_BASE 0x589AB00ull
+#define NIC9_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC9_QM0_AXUSER_SECURED_SECTION 0x8000
+#define NIC9_QM0_AXUSER_NONSECURED_BASE 0x589AB80ull
+#define NIC9_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC9_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC9_QM0_DBG_HBW_BASE 0x589AC00ull
+#define NIC9_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC9_QM0_DBG_HBW_SECTION 0x8000
+#define NIC9_QM0_DBG_LBW_BASE 0x589AC80ull
+#define NIC9_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC9_QM0_DBG_LBW_SECTION 0x1000
+#define NIC9_QM0_CGM_BASE 0x589AD80ull
+#define NIC9_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC9_QM0_CGM_SECTION 0x1000
+#define NIC9_QM0_SPECIAL_BASE 0x589AE80ull
+#define NIC9_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_QM0_SPECIAL_SECTION 0x4180
+#define NIC9_QPC0_BASE 0x589F000ull
+#define NIC9_QPC0_MAX_OFFSET 0x1000
+#define NIC9_QPC0_SECTION 0x7200
+#define NIC9_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x589F720ull
+#define NIC9_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x589F728ull
+#define NIC9_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x589F730ull
+#define NIC9_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x589F738ull
+#define NIC9_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x589F740ull
+#define NIC9_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x589F748ull
+#define NIC9_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x589F750ull
+#define NIC9_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x589F758ull
+#define NIC9_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x589F760ull
+#define NIC9_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x589F768ull
+#define NIC9_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x589F770ull
+#define NIC9_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x589F778ull
+#define NIC9_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x589F780ull
+#define NIC9_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x589F788ull
+#define NIC9_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x589F790ull
+#define NIC9_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x589F798ull
+#define NIC9_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x589F7A0ull
+#define NIC9_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x589F7A8ull
+#define NIC9_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x589F7B0ull
+#define NIC9_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x589F7B8ull
+#define NIC9_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x589F7C0ull
+#define NIC9_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x589F7C8ull
+#define NIC9_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x589F7D0ull
+#define NIC9_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x589F7D8ull
+#define NIC9_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x589F7E0ull
+#define NIC9_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x589F7E8ull
+#define NIC9_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x589F7F0ull
+#define NIC9_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x589F7F8ull
+#define NIC9_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x589F800ull
+#define NIC9_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x589F808ull
+#define NIC9_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x589F810ull
+#define NIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x589F818ull
+#define NIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC9_QPC0_AXUSER_CONG_QUE_BASE 0x589FB80ull
+#define NIC9_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC9_QPC0_AXUSER_RXWQE_BASE 0x589FBE0ull
+#define NIC9_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define NIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x589FC40ull
+#define NIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC9_QPC0_AXUSER_DB_FIFO_BASE 0x589FCA0ull
+#define NIC9_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x589FD00ull
+#define NIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC9_QPC0_AXUSER_ERR_FIFO_BASE 0x589FD60ull
+#define NIC9_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC9_QPC0_AXUSER_QPC_RESP_BASE 0x589FDC0ull
+#define NIC9_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC9_QPC0_AXUSER_QPC_REQ_BASE 0x589FE20ull
+#define NIC9_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC9_QPC0_SPECIAL_BASE 0x589FE80ull
+#define NIC9_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_QPC0_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_0_UNSECURE_DOORBELL0_BASE 0x58A0000ull
+#define NIC9_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_0_UNSECURE_DOORBELL1_BASE 0x58A0080ull
+#define NIC9_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x58A0100ull
+#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x58A0180ull
+#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_0_SPECIAL_BASE 0x58A0E80ull
+#define NIC9_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_0_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_1_UNSECURE_DOORBELL0_BASE 0x58A1000ull
+#define NIC9_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_1_UNSECURE_DOORBELL1_BASE 0x58A1080ull
+#define NIC9_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x58A1100ull
+#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x58A1180ull
+#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_1_SPECIAL_BASE 0x58A1E80ull
+#define NIC9_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_1_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_2_UNSECURE_DOORBELL0_BASE 0x58A2000ull
+#define NIC9_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_2_UNSECURE_DOORBELL1_BASE 0x58A2080ull
+#define NIC9_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x58A2100ull
+#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x58A2180ull
+#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_2_SPECIAL_BASE 0x58A2E80ull
+#define NIC9_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_2_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_3_UNSECURE_DOORBELL0_BASE 0x58A3000ull
+#define NIC9_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_3_UNSECURE_DOORBELL1_BASE 0x58A3080ull
+#define NIC9_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x58A3100ull
+#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x58A3180ull
+#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_3_SPECIAL_BASE 0x58A3E80ull
+#define NIC9_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_3_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_4_UNSECURE_DOORBELL0_BASE 0x58A4000ull
+#define NIC9_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_4_UNSECURE_DOORBELL1_BASE 0x58A4080ull
+#define NIC9_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x58A4100ull
+#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x58A4180ull
+#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_4_SPECIAL_BASE 0x58A4E80ull
+#define NIC9_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_4_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_5_UNSECURE_DOORBELL0_BASE 0x58A5000ull
+#define NIC9_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_5_UNSECURE_DOORBELL1_BASE 0x58A5080ull
+#define NIC9_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x58A5100ull
+#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x58A5180ull
+#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_5_SPECIAL_BASE 0x58A5E80ull
+#define NIC9_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_5_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_6_UNSECURE_DOORBELL0_BASE 0x58A6000ull
+#define NIC9_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_6_UNSECURE_DOORBELL1_BASE 0x58A6080ull
+#define NIC9_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x58A6100ull
+#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x58A6180ull
+#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_6_SPECIAL_BASE 0x58A6E80ull
+#define NIC9_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_6_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_7_UNSECURE_DOORBELL0_BASE 0x58A7000ull
+#define NIC9_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_7_UNSECURE_DOORBELL1_BASE 0x58A7080ull
+#define NIC9_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x58A7100ull
+#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x58A7180ull
+#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_7_SPECIAL_BASE 0x58A7E80ull
+#define NIC9_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_7_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_8_UNSECURE_DOORBELL0_BASE 0x58A8000ull
+#define NIC9_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_8_UNSECURE_DOORBELL1_BASE 0x58A8080ull
+#define NIC9_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x58A8100ull
+#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x58A8180ull
+#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_8_SPECIAL_BASE 0x58A8E80ull
+#define NIC9_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_8_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_9_UNSECURE_DOORBELL0_BASE 0x58A9000ull
+#define NIC9_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_9_UNSECURE_DOORBELL1_BASE 0x58A9080ull
+#define NIC9_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x58A9100ull
+#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x58A9180ull
+#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_9_SPECIAL_BASE 0x58A9E80ull
+#define NIC9_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_9_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_10_UNSECURE_DOORBELL0_BASE 0x58AA000ull
+#define NIC9_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_10_UNSECURE_DOORBELL1_BASE 0x58AA080ull
+#define NIC9_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x58AA100ull
+#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x58AA180ull
+#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_10_SPECIAL_BASE 0x58AAE80ull
+#define NIC9_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_10_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_11_UNSECURE_DOORBELL0_BASE 0x58AB000ull
+#define NIC9_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_11_UNSECURE_DOORBELL1_BASE 0x58AB080ull
+#define NIC9_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x58AB100ull
+#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x58AB180ull
+#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_11_SPECIAL_BASE 0x58ABE80ull
+#define NIC9_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_11_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_12_UNSECURE_DOORBELL0_BASE 0x58AC000ull
+#define NIC9_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_12_UNSECURE_DOORBELL1_BASE 0x58AC080ull
+#define NIC9_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x58AC100ull
+#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x58AC180ull
+#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_12_SPECIAL_BASE 0x58ACE80ull
+#define NIC9_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_12_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_13_UNSECURE_DOORBELL0_BASE 0x58AD000ull
+#define NIC9_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_13_UNSECURE_DOORBELL1_BASE 0x58AD080ull
+#define NIC9_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x58AD100ull
+#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x58AD180ull
+#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_13_SPECIAL_BASE 0x58ADE80ull
+#define NIC9_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_13_SPECIAL_SECTION 0x1800
+#define NIC9_UMR1_14_UNSECURE_DOORBELL0_BASE 0x58AE000ull
+#define NIC9_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC9_UMR1_14_UNSECURE_DOORBELL1_BASE 0x58AE080ull
+#define NIC9_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x58AE100ull
+#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x58AE180ull
+#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC9_UMR1_14_SPECIAL_BASE 0x58AEE80ull
+#define NIC9_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_14_SPECIAL_SECTION 0x1180
+#define NIC9_QM_DCCM1_BASE 0x58B0000ull
+#define NIC9_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC9_QM_DCCM1_SECTION 0x8000
+#define NIC9_QM_ARC_AUX1_BASE 0x58B8000ull
+#define NIC9_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC9_QM_ARC_AUX1_SECTION 0xE800
+#define NIC9_QM_ARC_AUX1_SPECIAL_BASE 0x58B8E80ull
+#define NIC9_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define NIC9_QM1_BASE 0x58BA000ull
+#define NIC9_QM1_MAX_OFFSET 0x1000
+#define NIC9_QM1_SECTION 0x9000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x58BA900ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x58BA908ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x58BA910ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x58BA918ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x58BA920ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x58BA928ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x58BA930ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x58BA938ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x58BA940ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x58BA948ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x58BA950ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x58BA958ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x58BA960ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x58BA968ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x58BA970ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x58BA978ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC9_QM1_AXUSER_SECURED_BASE 0x58BAB00ull
+#define NIC9_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC9_QM1_AXUSER_SECURED_SECTION 0x8000
+#define NIC9_QM1_AXUSER_NONSECURED_BASE 0x58BAB80ull
+#define NIC9_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC9_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC9_QM1_DBG_HBW_BASE 0x58BAC00ull
+#define NIC9_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC9_QM1_DBG_HBW_SECTION 0x8000
+#define NIC9_QM1_DBG_LBW_BASE 0x58BAC80ull
+#define NIC9_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC9_QM1_DBG_LBW_SECTION 0x1000
+#define NIC9_QM1_CGM_BASE 0x58BAD80ull
+#define NIC9_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC9_QM1_CGM_SECTION 0x1000
+#define NIC9_QM1_SPECIAL_BASE 0x58BAE80ull
+#define NIC9_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_QM1_SPECIAL_SECTION 0x4180
+#define NIC9_QPC1_BASE 0x58BF000ull
+#define NIC9_QPC1_MAX_OFFSET 0x1000
+#define NIC9_QPC1_SECTION 0x7200
+#define NIC9_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x58BF720ull
+#define NIC9_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x58BF728ull
+#define NIC9_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x58BF730ull
+#define NIC9_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x58BF738ull
+#define NIC9_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x58BF740ull
+#define NIC9_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x58BF748ull
+#define NIC9_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x58BF750ull
+#define NIC9_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x58BF758ull
+#define NIC9_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x58BF760ull
+#define NIC9_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x58BF768ull
+#define NIC9_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x58BF770ull
+#define NIC9_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x58BF778ull
+#define NIC9_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x58BF780ull
+#define NIC9_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x58BF788ull
+#define NIC9_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x58BF790ull
+#define NIC9_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x58BF798ull
+#define NIC9_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x58BF7A0ull
+#define NIC9_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x58BF7A8ull
+#define NIC9_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x58BF7B0ull
+#define NIC9_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x58BF7B8ull
+#define NIC9_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x58BF7C0ull
+#define NIC9_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x58BF7C8ull
+#define NIC9_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x58BF7D0ull
+#define NIC9_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x58BF7D8ull
+#define NIC9_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x58BF7E0ull
+#define NIC9_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x58BF7E8ull
+#define NIC9_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x58BF7F0ull
+#define NIC9_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x58BF7F8ull
+#define NIC9_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x58BF800ull
+#define NIC9_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x58BF808ull
+#define NIC9_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x58BF810ull
+#define NIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x58BF818ull
+#define NIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC9_QPC1_AXUSER_CONG_QUE_BASE 0x58BFB80ull
+#define NIC9_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC9_QPC1_AXUSER_RXWQE_BASE 0x58BFBE0ull
+#define NIC9_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define NIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x58BFC40ull
+#define NIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC9_QPC1_AXUSER_DB_FIFO_BASE 0x58BFCA0ull
+#define NIC9_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x58BFD00ull
+#define NIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC9_QPC1_AXUSER_ERR_FIFO_BASE 0x58BFD60ull
+#define NIC9_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC9_QPC1_AXUSER_QPC_RESP_BASE 0x58BFDC0ull
+#define NIC9_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC9_QPC1_AXUSER_QPC_REQ_BASE 0x58BFE20ull
+#define NIC9_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC9_QPC1_SPECIAL_BASE 0x58BFE80ull
+#define NIC9_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_QPC1_SPECIAL_SECTION 0x8180
+#define NIC9_TMR_BASE 0x58C8000ull
+#define NIC9_TMR_MAX_OFFSET 0x1000
+#define NIC9_TMR_SECTION 0xD600
+#define NIC9_TMR_AXUSER_TMR_FREE_LIST_BASE 0x58C8D60ull
+#define NIC9_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC9_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define NIC9_TMR_AXUSER_TMR_FIFO_BASE 0x58C8DC0ull
+#define NIC9_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC9_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define NIC9_TMR_AXUSER_TMR_FSM_BASE 0x58C8E20ull
+#define NIC9_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC9_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define NIC9_TMR_SPECIAL_BASE 0x58C8E80ull
+#define NIC9_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_TMR_SPECIAL_SECTION 0x1800
+#define NIC9_RXB_CORE_BASE 0x58C9000ull
+#define NIC9_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC9_RXB_CORE_SECTION 0x6100
+#define NIC9_RXB_CORE_SCT_AWUSER_BASE 0x58C9610ull
+#define NIC9_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC9_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define NIC9_RXB_CORE_SPECIAL_BASE 0x58C9E80ull
+#define NIC9_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_RXB_CORE_SPECIAL_SECTION 0x1800
+#define NIC9_RXE0_BASE 0x58CA000ull
+#define NIC9_RXE0_MAX_OFFSET 0x1000
+#define NIC9_RXE0_SECTION 0x9000
+#define NIC9_RXE0_WQE_ARUSER_BASE 0x58CA900ull
+#define NIC9_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC9_RXE0_WQE_ARUSER_SECTION 0x5800
+#define NIC9_RXE0_SPECIAL_BASE 0x58CAE80ull
+#define NIC9_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_RXE0_SPECIAL_SECTION 0x1800
+#define NIC9_RXE1_BASE 0x58CB000ull
+#define NIC9_RXE1_MAX_OFFSET 0x1000
+#define NIC9_RXE1_SECTION 0x9000
+#define NIC9_RXE1_WQE_ARUSER_BASE 0x58CB900ull
+#define NIC9_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC9_RXE1_WQE_ARUSER_SECTION 0x5800
+#define NIC9_RXE1_SPECIAL_BASE 0x58CBE80ull
+#define NIC9_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_RXE1_SPECIAL_SECTION 0x1800
+#define NIC9_RXE0_AXUSER_AXUSER_CQ0_BASE 0x58CC000ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ1_BASE 0x58CC050ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ2_BASE 0x58CC0A0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ3_BASE 0x58CC0F0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ4_BASE 0x58CC140ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ5_BASE 0x58CC190ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ6_BASE 0x58CC1E0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ7_BASE 0x58CC230ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ8_BASE 0x58CC280ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ9_BASE 0x58CC2D0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ10_BASE 0x58CC320ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ11_BASE 0x58CC370ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ12_BASE 0x58CC3C0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ13_BASE 0x58CC410ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ14_BASE 0x58CC460ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ15_BASE 0x58CC4B0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ16_BASE 0x58CC500ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ17_BASE 0x58CC550ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ18_BASE 0x58CC5A0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ19_BASE 0x58CC5F0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ20_BASE 0x58CC640ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ21_BASE 0x58CC690ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ22_BASE 0x58CC6E0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ23_BASE 0x58CC730ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ24_BASE 0x58CC780ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ25_BASE 0x58CC7D0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ26_BASE 0x58CC820ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ27_BASE 0x58CC870ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ28_BASE 0x58CC8C0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ29_BASE 0x58CC910ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ30_BASE 0x58CC960ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ31_BASE 0x58CC9B0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC9_RXE0_AXUSER_SPECIAL_BASE 0x58CCE80ull
+#define NIC9_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define NIC9_RXE1_AXUSER_AXUSER_CQ0_BASE 0x58CD000ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ1_BASE 0x58CD050ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ2_BASE 0x58CD0A0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ3_BASE 0x58CD0F0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ4_BASE 0x58CD140ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ5_BASE 0x58CD190ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ6_BASE 0x58CD1E0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ7_BASE 0x58CD230ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ8_BASE 0x58CD280ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ9_BASE 0x58CD2D0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ10_BASE 0x58CD320ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ11_BASE 0x58CD370ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ12_BASE 0x58CD3C0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ13_BASE 0x58CD410ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ14_BASE 0x58CD460ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ15_BASE 0x58CD4B0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ16_BASE 0x58CD500ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ17_BASE 0x58CD550ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ18_BASE 0x58CD5A0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ19_BASE 0x58CD5F0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ20_BASE 0x58CD640ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ21_BASE 0x58CD690ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ22_BASE 0x58CD6E0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ23_BASE 0x58CD730ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ24_BASE 0x58CD780ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ25_BASE 0x58CD7D0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ26_BASE 0x58CD820ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ27_BASE 0x58CD870ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ28_BASE 0x58CD8C0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ29_BASE 0x58CD910ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ30_BASE 0x58CD960ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ31_BASE 0x58CD9B0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC9_RXE1_AXUSER_SPECIAL_BASE 0x58CDE80ull
+#define NIC9_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define NIC9_TXS0_BASE 0x58D0000ull
+#define NIC9_TXS0_MAX_OFFSET 0x1000
+#define NIC9_TXS0_SECTION 0xE800
+#define NIC9_TXS0_SPECIAL_BASE 0x58D0E80ull
+#define NIC9_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_TXS0_SPECIAL_SECTION 0x1800
+#define NIC9_TXS1_BASE 0x58D1000ull
+#define NIC9_TXS1_MAX_OFFSET 0x1000
+#define NIC9_TXS1_SECTION 0xE800
+#define NIC9_TXS1_SPECIAL_BASE 0x58D1E80ull
+#define NIC9_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_TXS1_SPECIAL_SECTION 0x1800
+#define NIC9_TXE0_BASE 0x58D2000ull
+#define NIC9_TXE0_MAX_OFFSET 0x1000
+#define NIC9_TXE0_SECTION 0xE800
+#define NIC9_TXE0_SPECIAL_BASE 0x58D2E80ull
+#define NIC9_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_TXE0_SPECIAL_SECTION 0x1800
+#define NIC9_TXE1_BASE 0x58D3000ull
+#define NIC9_TXE1_MAX_OFFSET 0x1000
+#define NIC9_TXE1_SECTION 0xE800
+#define NIC9_TXE1_SPECIAL_BASE 0x58D3E80ull
+#define NIC9_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_TXE1_SPECIAL_SECTION 0x1800
+#define NIC9_TXB_BASE 0x58D4000ull
+#define NIC9_TXB_MAX_OFFSET 0x1000
+#define NIC9_TXB_SECTION 0xE800
+#define NIC9_TXB_SPECIAL_BASE 0x58D4E80ull
+#define NIC9_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_TXB_SPECIAL_SECTION 0x1800
+#define NIC9_MSTR_IF_RR_SHRD_HBW_BASE 0x58D5000ull
+#define NIC9_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC9_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define NIC9_MSTR_IF_RR_PRVT_HBW_BASE 0x58D5200ull
+#define NIC9_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC9_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define NIC9_MSTR_IF_RR_SHRD_LBW_BASE 0x58D5400ull
+#define NIC9_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC9_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define NIC9_MSTR_IF_RR_PRVT_LBW_BASE 0x58D5600ull
+#define NIC9_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC9_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define NIC9_MSTR_IF_E2E_CRDT_BASE 0x58D5800ull
+#define NIC9_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC9_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define NIC9_MSTR_IF_AXUSER_BASE 0x58D5A80ull
+#define NIC9_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC9_MSTR_IF_AXUSER_SECTION 0x8000
+#define NIC9_MSTR_IF_DBG_HBW_BASE 0x58D5B00ull
+#define NIC9_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC9_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define NIC9_MSTR_IF_DBG_LBW_BASE 0x58D5B80ull
+#define NIC9_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC9_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define NIC9_MSTR_IF_CORE_HBW_BASE 0x58D5C00ull
+#define NIC9_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC9_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define NIC9_MSTR_IF_CORE_LBW_BASE 0x58D5D80ull
+#define NIC9_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC9_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define NIC9_MSTR_IF_SPECIAL_BASE 0x58D5E80ull
+#define NIC9_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_MSTR_IF_SPECIAL_SECTION 0x1800
+#define NIC9_TX_AXUSER_BASE 0x58D6000ull
+#define NIC9_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC9_TX_AXUSER_SECTION 0x2000
+#define NIC9_SERDES0_BASE 0x58D8000ull
+#define NIC9_SERDES0_MAX_OFFSET 0x3E40
+#define NIC9_SERDES0_SECTION 0x4000
+#define NIC9_SERDES1_BASE 0x58DC000ull
+#define NIC9_SERDES1_MAX_OFFSET 0x3E40
+#define NIC9_SERDES1_SECTION 0x4000
+#define NIC9_PHY_BASE 0x58E0000ull
+#define NIC9_PHY_MAX_OFFSET 0x1000
+#define NIC9_PHY_SECTION 0xE800
+#define NIC9_PHY_SPECIAL_BASE 0x58E0E80ull
+#define NIC9_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_PHY_SPECIAL_SECTION 0x7180
+#define PRT9_MAC_AUX_BASE 0x58E8000ull
+#define PRT9_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT9_MAC_AUX_SECTION 0xE800
+#define PRT9_MAC_AUX_SPECIAL_BASE 0x58E8E80ull
+#define PRT9_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT9_MAC_AUX_SPECIAL_SECTION 0x1800
+#define PRT9_MAC_CORE_BASE 0x58E9000ull
+#define PRT9_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT9_MAC_CORE_SECTION 0xE800
+#define PRT9_MAC_CORE_SPECIAL_BASE 0x58E9E80ull
+#define PRT9_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT9_MAC_CORE_SPECIAL_SECTION 0x1800
+#define NIC9_MAC_RS_FEC_BASE 0x58EA000ull
+#define NIC9_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC9_MAC_RS_FEC_SECTION 0x1000
+#define NIC9_MAC_GLOB_STAT_CONTROL_REG_BASE 0x58EB000ull
+#define NIC9_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC9_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define NIC9_MAC_GLOB_STAT_RX0_BASE 0x58EB100ull
+#define NIC9_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC9_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define NIC9_MAC_GLOB_STAT_RX1_BASE 0x58EB18Cull
+#define NIC9_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC9_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define NIC9_MAC_GLOB_STAT_RX2_BASE 0x58EB218ull
+#define NIC9_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC9_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define NIC9_MAC_GLOB_STAT_RX3_BASE 0x58EB2A4ull
+#define NIC9_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC9_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define NIC9_MAC_GLOB_STAT_TX0_BASE 0x58EB330ull
+#define NIC9_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC9_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define NIC9_MAC_GLOB_STAT_TX1_BASE 0x58EB398ull
+#define NIC9_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC9_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define NIC9_MAC_GLOB_STAT_TX2_BASE 0x58EB400ull
+#define NIC9_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC9_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define NIC9_MAC_GLOB_STAT_TX3_BASE 0x58EB468ull
+#define NIC9_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC9_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define NIC9_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x58EB800ull
+#define NIC9_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC9_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define NIC9_MAC_CH0_MAC_PCS_BASE 0x58EC000ull
+#define NIC9_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC9_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define NIC9_MAC_CH0_MAC_128_BASE 0x58EC400ull
+#define NIC9_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC9_MAC_CH0_MAC_128_SECTION 0x4000
+#define NIC9_MAC_CH0_MAC_AN_BASE 0x58EC800ull
+#define NIC9_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC9_MAC_CH0_MAC_AN_SECTION 0x8000
+#define NIC9_MAC_CH1_MAC_PCS_BASE 0x58ED000ull
+#define NIC9_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC9_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define NIC9_MAC_CH1_MAC_128_BASE 0x58ED400ull
+#define NIC9_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC9_MAC_CH1_MAC_128_SECTION 0x4000
+#define NIC9_MAC_CH1_MAC_AN_BASE 0x58ED800ull
+#define NIC9_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC9_MAC_CH1_MAC_AN_SECTION 0x8000
+#define NIC9_MAC_CH2_MAC_PCS_BASE 0x58EE000ull
+#define NIC9_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC9_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define NIC9_MAC_CH2_MAC_128_BASE 0x58EE400ull
+#define NIC9_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC9_MAC_CH2_MAC_128_SECTION 0x4000
+#define NIC9_MAC_CH2_MAC_AN_BASE 0x58EE800ull
+#define NIC9_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC9_MAC_CH2_MAC_AN_SECTION 0x8000
+#define NIC9_MAC_CH3_MAC_PCS_BASE 0x58EF000ull
+#define NIC9_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC9_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define NIC9_MAC_CH3_MAC_128_BASE 0x58EF400ull
+#define NIC9_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC9_MAC_CH3_MAC_128_SECTION 0x4000
+#define NIC9_MAC_CH3_MAC_AN_BASE 0x58EF800ull
+#define NIC9_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC9_MAC_CH3_MAC_AN_SECTION 0x10800
+#define NIC10_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5900000ull
+#define NIC10_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5900080ull
+#define NIC10_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5900100ull
+#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5900180ull
+#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_0_SPECIAL_BASE 0x5900E80ull
+#define NIC10_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_0_SPECIAL_SECTION 0x1800
+#define NIC10_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5901000ull
+#define NIC10_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5901080ull
+#define NIC10_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5901100ull
+#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5901180ull
+#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_1_SPECIAL_BASE 0x5901E80ull
+#define NIC10_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_1_SPECIAL_SECTION 0x1800
+#define NIC10_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5902000ull
+#define NIC10_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5902080ull
+#define NIC10_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5902100ull
+#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5902180ull
+#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_2_SPECIAL_BASE 0x5902E80ull
+#define NIC10_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_2_SPECIAL_SECTION 0x1800
+#define NIC10_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5903000ull
+#define NIC10_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5903080ull
+#define NIC10_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5903100ull
+#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5903180ull
+#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_3_SPECIAL_BASE 0x5903E80ull
+#define NIC10_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_3_SPECIAL_SECTION 0x1800
+#define NIC10_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5904000ull
+#define NIC10_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5904080ull
+#define NIC10_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5904100ull
+#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5904180ull
+#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_4_SPECIAL_BASE 0x5904E80ull
+#define NIC10_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_4_SPECIAL_SECTION 0x1800
+#define NIC10_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5905000ull
+#define NIC10_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5905080ull
+#define NIC10_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5905100ull
+#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5905180ull
+#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_5_SPECIAL_BASE 0x5905E80ull
+#define NIC10_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_5_SPECIAL_SECTION 0x1800
+#define NIC10_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5906000ull
+#define NIC10_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5906080ull
+#define NIC10_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5906100ull
+#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5906180ull
+#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_6_SPECIAL_BASE 0x5906E80ull
+#define NIC10_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_6_SPECIAL_SECTION 0x1800
+#define NIC10_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5907000ull
+#define NIC10_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5907080ull
+#define NIC10_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5907100ull
+#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5907180ull
+#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_7_SPECIAL_BASE 0x5907E80ull
+#define NIC10_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_7_SPECIAL_SECTION 0x1800
+#define NIC10_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5908000ull
+#define NIC10_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5908080ull
+#define NIC10_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5908100ull
+#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5908180ull
+#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_8_SPECIAL_BASE 0x5908E80ull
+#define NIC10_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_8_SPECIAL_SECTION 0x1800
+#define NIC10_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5909000ull
+#define NIC10_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5909080ull
+#define NIC10_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5909100ull
+#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5909180ull
+#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_9_SPECIAL_BASE 0x5909E80ull
+#define NIC10_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_9_SPECIAL_SECTION 0x1800
+#define NIC10_UMR0_10_UNSECURE_DOORBELL0_BASE 0x590A000ull
+#define NIC10_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_10_UNSECURE_DOORBELL1_BASE 0x590A080ull
+#define NIC10_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x590A100ull
+#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x590A180ull
+#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_10_SPECIAL_BASE 0x590AE80ull
+#define NIC10_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_10_SPECIAL_SECTION 0x1800
+#define NIC10_UMR0_11_UNSECURE_DOORBELL0_BASE 0x590B000ull
+#define NIC10_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_11_UNSECURE_DOORBELL1_BASE 0x590B080ull
+#define NIC10_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x590B100ull
+#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x590B180ull
+#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_11_SPECIAL_BASE 0x590BE80ull
+#define NIC10_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_11_SPECIAL_SECTION 0x1800
+#define NIC10_UMR0_12_UNSECURE_DOORBELL0_BASE 0x590C000ull
+#define NIC10_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_12_UNSECURE_DOORBELL1_BASE 0x590C080ull
+#define NIC10_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x590C100ull
+#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x590C180ull
+#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_12_SPECIAL_BASE 0x590CE80ull
+#define NIC10_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_12_SPECIAL_SECTION 0x1800
+#define NIC10_UMR0_13_UNSECURE_DOORBELL0_BASE 0x590D000ull
+#define NIC10_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_13_UNSECURE_DOORBELL1_BASE 0x590D080ull
+#define NIC10_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x590D100ull
+#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x590D180ull
+#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_13_SPECIAL_BASE 0x590DE80ull
+#define NIC10_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_13_SPECIAL_SECTION 0x1800
+#define NIC10_UMR0_14_UNSECURE_DOORBELL0_BASE 0x590E000ull
+#define NIC10_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR0_14_UNSECURE_DOORBELL1_BASE 0x590E080ull
+#define NIC10_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x590E100ull
+#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x590E180ull
+#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR0_14_SPECIAL_BASE 0x590EE80ull
+#define NIC10_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_14_SPECIAL_SECTION 0x1180
+#define NIC10_QM_DCCM0_BASE 0x5910000ull
+#define NIC10_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC10_QM_DCCM0_SECTION 0x8000
+#define NIC10_QM_ARC_AUX0_BASE 0x5918000ull
+#define NIC10_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC10_QM_ARC_AUX0_SECTION 0xE800
+#define NIC10_QM_ARC_AUX0_SPECIAL_BASE 0x5918E80ull
+#define NIC10_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define NIC10_QM0_BASE 0x591A000ull
+#define NIC10_QM0_MAX_OFFSET 0x1000
+#define NIC10_QM0_SECTION 0x9000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x591A900ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x591A908ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x591A910ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x591A918ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x591A920ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x591A928ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x591A930ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x591A938ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x591A940ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x591A948ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x591A950ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x591A958ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x591A960ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x591A968ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x591A970ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x591A978ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC10_QM0_AXUSER_SECURED_BASE 0x591AB00ull
+#define NIC10_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC10_QM0_AXUSER_SECURED_SECTION 0x8000
+#define NIC10_QM0_AXUSER_NONSECURED_BASE 0x591AB80ull
+#define NIC10_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC10_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC10_QM0_DBG_HBW_BASE 0x591AC00ull
+#define NIC10_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC10_QM0_DBG_HBW_SECTION 0x8000
+#define NIC10_QM0_DBG_LBW_BASE 0x591AC80ull
+#define NIC10_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC10_QM0_DBG_LBW_SECTION 0x1000
+#define NIC10_QM0_CGM_BASE 0x591AD80ull
+#define NIC10_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC10_QM0_CGM_SECTION 0x1000
+#define NIC10_QM0_SPECIAL_BASE 0x591AE80ull
+#define NIC10_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_QM0_SPECIAL_SECTION 0x4180
+#define NIC10_QPC0_BASE 0x591F000ull
+#define NIC10_QPC0_MAX_OFFSET 0x1000
+#define NIC10_QPC0_SECTION 0x7200
+#define NIC10_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x591F720ull
+#define NIC10_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x591F728ull
+#define NIC10_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x591F730ull
+#define NIC10_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x591F738ull
+#define NIC10_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x591F740ull
+#define NIC10_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x591F748ull
+#define NIC10_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x591F750ull
+#define NIC10_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x591F758ull
+#define NIC10_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x591F760ull
+#define NIC10_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x591F768ull
+#define NIC10_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x591F770ull
+#define NIC10_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x591F778ull
+#define NIC10_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x591F780ull
+#define NIC10_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x591F788ull
+#define NIC10_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x591F790ull
+#define NIC10_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x591F798ull
+#define NIC10_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x591F7A0ull
+#define NIC10_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x591F7A8ull
+#define NIC10_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x591F7B0ull
+#define NIC10_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x591F7B8ull
+#define NIC10_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x591F7C0ull
+#define NIC10_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x591F7C8ull
+#define NIC10_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x591F7D0ull
+#define NIC10_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x591F7D8ull
+#define NIC10_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x591F7E0ull
+#define NIC10_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x591F7E8ull
+#define NIC10_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x591F7F0ull
+#define NIC10_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x591F7F8ull
+#define NIC10_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x591F800ull
+#define NIC10_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x591F808ull
+#define NIC10_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x591F810ull
+#define NIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x591F818ull
+#define NIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC10_QPC0_AXUSER_CONG_QUE_BASE 0x591FB80ull
+#define NIC10_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC10_QPC0_AXUSER_RXWQE_BASE 0x591FBE0ull
+#define NIC10_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define NIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x591FC40ull
+#define NIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC10_QPC0_AXUSER_DB_FIFO_BASE 0x591FCA0ull
+#define NIC10_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x591FD00ull
+#define NIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC10_QPC0_AXUSER_ERR_FIFO_BASE 0x591FD60ull
+#define NIC10_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC10_QPC0_AXUSER_QPC_RESP_BASE 0x591FDC0ull
+#define NIC10_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC10_QPC0_AXUSER_QPC_REQ_BASE 0x591FE20ull
+#define NIC10_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC10_QPC0_SPECIAL_BASE 0x591FE80ull
+#define NIC10_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_QPC0_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5920000ull
+#define NIC10_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5920080ull
+#define NIC10_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5920100ull
+#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5920180ull
+#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_0_SPECIAL_BASE 0x5920E80ull
+#define NIC10_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_0_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5921000ull
+#define NIC10_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5921080ull
+#define NIC10_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5921100ull
+#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5921180ull
+#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_1_SPECIAL_BASE 0x5921E80ull
+#define NIC10_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_1_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5922000ull
+#define NIC10_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5922080ull
+#define NIC10_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5922100ull
+#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5922180ull
+#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_2_SPECIAL_BASE 0x5922E80ull
+#define NIC10_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_2_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5923000ull
+#define NIC10_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5923080ull
+#define NIC10_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5923100ull
+#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5923180ull
+#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_3_SPECIAL_BASE 0x5923E80ull
+#define NIC10_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_3_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5924000ull
+#define NIC10_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5924080ull
+#define NIC10_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5924100ull
+#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5924180ull
+#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_4_SPECIAL_BASE 0x5924E80ull
+#define NIC10_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_4_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5925000ull
+#define NIC10_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5925080ull
+#define NIC10_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5925100ull
+#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5925180ull
+#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_5_SPECIAL_BASE 0x5925E80ull
+#define NIC10_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_5_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5926000ull
+#define NIC10_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5926080ull
+#define NIC10_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5926100ull
+#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5926180ull
+#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_6_SPECIAL_BASE 0x5926E80ull
+#define NIC10_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_6_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5927000ull
+#define NIC10_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5927080ull
+#define NIC10_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5927100ull
+#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5927180ull
+#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_7_SPECIAL_BASE 0x5927E80ull
+#define NIC10_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_7_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5928000ull
+#define NIC10_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5928080ull
+#define NIC10_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5928100ull
+#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5928180ull
+#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_8_SPECIAL_BASE 0x5928E80ull
+#define NIC10_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_8_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5929000ull
+#define NIC10_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5929080ull
+#define NIC10_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5929100ull
+#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5929180ull
+#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_9_SPECIAL_BASE 0x5929E80ull
+#define NIC10_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_9_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_10_UNSECURE_DOORBELL0_BASE 0x592A000ull
+#define NIC10_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_10_UNSECURE_DOORBELL1_BASE 0x592A080ull
+#define NIC10_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x592A100ull
+#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x592A180ull
+#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_10_SPECIAL_BASE 0x592AE80ull
+#define NIC10_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_10_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_11_UNSECURE_DOORBELL0_BASE 0x592B000ull
+#define NIC10_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_11_UNSECURE_DOORBELL1_BASE 0x592B080ull
+#define NIC10_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x592B100ull
+#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x592B180ull
+#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_11_SPECIAL_BASE 0x592BE80ull
+#define NIC10_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_11_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_12_UNSECURE_DOORBELL0_BASE 0x592C000ull
+#define NIC10_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_12_UNSECURE_DOORBELL1_BASE 0x592C080ull
+#define NIC10_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x592C100ull
+#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x592C180ull
+#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_12_SPECIAL_BASE 0x592CE80ull
+#define NIC10_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_12_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_13_UNSECURE_DOORBELL0_BASE 0x592D000ull
+#define NIC10_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_13_UNSECURE_DOORBELL1_BASE 0x592D080ull
+#define NIC10_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x592D100ull
+#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x592D180ull
+#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_13_SPECIAL_BASE 0x592DE80ull
+#define NIC10_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_13_SPECIAL_SECTION 0x1800
+#define NIC10_UMR1_14_UNSECURE_DOORBELL0_BASE 0x592E000ull
+#define NIC10_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC10_UMR1_14_UNSECURE_DOORBELL1_BASE 0x592E080ull
+#define NIC10_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x592E100ull
+#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x592E180ull
+#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC10_UMR1_14_SPECIAL_BASE 0x592EE80ull
+#define NIC10_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_14_SPECIAL_SECTION 0x1180
+#define NIC10_QM_DCCM1_BASE 0x5930000ull
+#define NIC10_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC10_QM_DCCM1_SECTION 0x8000
+#define NIC10_QM_ARC_AUX1_BASE 0x5938000ull
+#define NIC10_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC10_QM_ARC_AUX1_SECTION 0xE800
+#define NIC10_QM_ARC_AUX1_SPECIAL_BASE 0x5938E80ull
+#define NIC10_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define NIC10_QM1_BASE 0x593A000ull
+#define NIC10_QM1_MAX_OFFSET 0x1000
+#define NIC10_QM1_SECTION 0x9000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x593A900ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x593A908ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x593A910ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x593A918ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x593A920ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x593A928ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x593A930ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x593A938ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x593A940ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x593A948ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x593A950ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x593A958ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x593A960ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x593A968ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x593A970ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x593A978ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC10_QM1_AXUSER_SECURED_BASE 0x593AB00ull
+#define NIC10_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC10_QM1_AXUSER_SECURED_SECTION 0x8000
+#define NIC10_QM1_AXUSER_NONSECURED_BASE 0x593AB80ull
+#define NIC10_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC10_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC10_QM1_DBG_HBW_BASE 0x593AC00ull
+#define NIC10_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC10_QM1_DBG_HBW_SECTION 0x8000
+#define NIC10_QM1_DBG_LBW_BASE 0x593AC80ull
+#define NIC10_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC10_QM1_DBG_LBW_SECTION 0x1000
+#define NIC10_QM1_CGM_BASE 0x593AD80ull
+#define NIC10_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC10_QM1_CGM_SECTION 0x1000
+#define NIC10_QM1_SPECIAL_BASE 0x593AE80ull
+#define NIC10_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_QM1_SPECIAL_SECTION 0x4180
+#define NIC10_QPC1_BASE 0x593F000ull
+#define NIC10_QPC1_MAX_OFFSET 0x1000
+#define NIC10_QPC1_SECTION 0x7200
+#define NIC10_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x593F720ull
+#define NIC10_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x593F728ull
+#define NIC10_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x593F730ull
+#define NIC10_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x593F738ull
+#define NIC10_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x593F740ull
+#define NIC10_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x593F748ull
+#define NIC10_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x593F750ull
+#define NIC10_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x593F758ull
+#define NIC10_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x593F760ull
+#define NIC10_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x593F768ull
+#define NIC10_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x593F770ull
+#define NIC10_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x593F778ull
+#define NIC10_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x593F780ull
+#define NIC10_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x593F788ull
+#define NIC10_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x593F790ull
+#define NIC10_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x593F798ull
+#define NIC10_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x593F7A0ull
+#define NIC10_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x593F7A8ull
+#define NIC10_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x593F7B0ull
+#define NIC10_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x593F7B8ull
+#define NIC10_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x593F7C0ull
+#define NIC10_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x593F7C8ull
+#define NIC10_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x593F7D0ull
+#define NIC10_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x593F7D8ull
+#define NIC10_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x593F7E0ull
+#define NIC10_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x593F7E8ull
+#define NIC10_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x593F7F0ull
+#define NIC10_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x593F7F8ull
+#define NIC10_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x593F800ull
+#define NIC10_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x593F808ull
+#define NIC10_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x593F810ull
+#define NIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x593F818ull
+#define NIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC10_QPC1_AXUSER_CONG_QUE_BASE 0x593FB80ull
+#define NIC10_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC10_QPC1_AXUSER_RXWQE_BASE 0x593FBE0ull
+#define NIC10_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define NIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x593FC40ull
+#define NIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC10_QPC1_AXUSER_DB_FIFO_BASE 0x593FCA0ull
+#define NIC10_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x593FD00ull
+#define NIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC10_QPC1_AXUSER_ERR_FIFO_BASE 0x593FD60ull
+#define NIC10_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC10_QPC1_AXUSER_QPC_RESP_BASE 0x593FDC0ull
+#define NIC10_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC10_QPC1_AXUSER_QPC_REQ_BASE 0x593FE20ull
+#define NIC10_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC10_QPC1_SPECIAL_BASE 0x593FE80ull
+#define NIC10_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_QPC1_SPECIAL_SECTION 0x8180
+#define NIC10_TMR_BASE 0x5948000ull
+#define NIC10_TMR_MAX_OFFSET 0x1000
+#define NIC10_TMR_SECTION 0xD600
+#define NIC10_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5948D60ull
+#define NIC10_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC10_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define NIC10_TMR_AXUSER_TMR_FIFO_BASE 0x5948DC0ull
+#define NIC10_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC10_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define NIC10_TMR_AXUSER_TMR_FSM_BASE 0x5948E20ull
+#define NIC10_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC10_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define NIC10_TMR_SPECIAL_BASE 0x5948E80ull
+#define NIC10_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_TMR_SPECIAL_SECTION 0x1800
+#define NIC10_RXB_CORE_BASE 0x5949000ull
+#define NIC10_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC10_RXB_CORE_SECTION 0x6100
+#define NIC10_RXB_CORE_SCT_AWUSER_BASE 0x5949610ull
+#define NIC10_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC10_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define NIC10_RXB_CORE_SPECIAL_BASE 0x5949E80ull
+#define NIC10_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_RXB_CORE_SPECIAL_SECTION 0x1800
+#define NIC10_RXE0_BASE 0x594A000ull
+#define NIC10_RXE0_MAX_OFFSET 0x1000
+#define NIC10_RXE0_SECTION 0x9000
+#define NIC10_RXE0_WQE_ARUSER_BASE 0x594A900ull
+#define NIC10_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC10_RXE0_WQE_ARUSER_SECTION 0x5800
+#define NIC10_RXE0_SPECIAL_BASE 0x594AE80ull
+#define NIC10_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_RXE0_SPECIAL_SECTION 0x1800
+#define NIC10_RXE1_BASE 0x594B000ull
+#define NIC10_RXE1_MAX_OFFSET 0x1000
+#define NIC10_RXE1_SECTION 0x9000
+#define NIC10_RXE1_WQE_ARUSER_BASE 0x594B900ull
+#define NIC10_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC10_RXE1_WQE_ARUSER_SECTION 0x5800
+#define NIC10_RXE1_SPECIAL_BASE 0x594BE80ull
+#define NIC10_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_RXE1_SPECIAL_SECTION 0x1800
+#define NIC10_RXE0_AXUSER_AXUSER_CQ0_BASE 0x594C000ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ1_BASE 0x594C050ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ2_BASE 0x594C0A0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ3_BASE 0x594C0F0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ4_BASE 0x594C140ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ5_BASE 0x594C190ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ6_BASE 0x594C1E0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ7_BASE 0x594C230ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ8_BASE 0x594C280ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ9_BASE 0x594C2D0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ10_BASE 0x594C320ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ11_BASE 0x594C370ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ12_BASE 0x594C3C0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ13_BASE 0x594C410ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ14_BASE 0x594C460ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ15_BASE 0x594C4B0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ16_BASE 0x594C500ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ17_BASE 0x594C550ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ18_BASE 0x594C5A0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ19_BASE 0x594C5F0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ20_BASE 0x594C640ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ21_BASE 0x594C690ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ22_BASE 0x594C6E0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ23_BASE 0x594C730ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ24_BASE 0x594C780ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ25_BASE 0x594C7D0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ26_BASE 0x594C820ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ27_BASE 0x594C870ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ28_BASE 0x594C8C0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ29_BASE 0x594C910ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ30_BASE 0x594C960ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ31_BASE 0x594C9B0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC10_RXE0_AXUSER_SPECIAL_BASE 0x594CE80ull
+#define NIC10_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define NIC10_RXE1_AXUSER_AXUSER_CQ0_BASE 0x594D000ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ1_BASE 0x594D050ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ2_BASE 0x594D0A0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ3_BASE 0x594D0F0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ4_BASE 0x594D140ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ5_BASE 0x594D190ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ6_BASE 0x594D1E0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ7_BASE 0x594D230ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ8_BASE 0x594D280ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ9_BASE 0x594D2D0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ10_BASE 0x594D320ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ11_BASE 0x594D370ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ12_BASE 0x594D3C0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ13_BASE 0x594D410ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ14_BASE 0x594D460ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ15_BASE 0x594D4B0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ16_BASE 0x594D500ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ17_BASE 0x594D550ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ18_BASE 0x594D5A0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ19_BASE 0x594D5F0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ20_BASE 0x594D640ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ21_BASE 0x594D690ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ22_BASE 0x594D6E0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ23_BASE 0x594D730ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ24_BASE 0x594D780ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ25_BASE 0x594D7D0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ26_BASE 0x594D820ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ27_BASE 0x594D870ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ28_BASE 0x594D8C0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ29_BASE 0x594D910ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ30_BASE 0x594D960ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ31_BASE 0x594D9B0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC10_RXE1_AXUSER_SPECIAL_BASE 0x594DE80ull
+#define NIC10_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define NIC10_TXS0_BASE 0x5950000ull
+#define NIC10_TXS0_MAX_OFFSET 0x1000
+#define NIC10_TXS0_SECTION 0xE800
+#define NIC10_TXS0_SPECIAL_BASE 0x5950E80ull
+#define NIC10_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_TXS0_SPECIAL_SECTION 0x1800
+#define NIC10_TXS1_BASE 0x5951000ull
+#define NIC10_TXS1_MAX_OFFSET 0x1000
+#define NIC10_TXS1_SECTION 0xE800
+#define NIC10_TXS1_SPECIAL_BASE 0x5951E80ull
+#define NIC10_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_TXS1_SPECIAL_SECTION 0x1800
+#define NIC10_TXE0_BASE 0x5952000ull
+#define NIC10_TXE0_MAX_OFFSET 0x1000
+#define NIC10_TXE0_SECTION 0xE800
+#define NIC10_TXE0_SPECIAL_BASE 0x5952E80ull
+#define NIC10_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_TXE0_SPECIAL_SECTION 0x1800
+#define NIC10_TXE1_BASE 0x5953000ull
+#define NIC10_TXE1_MAX_OFFSET 0x1000
+#define NIC10_TXE1_SECTION 0xE800
+#define NIC10_TXE1_SPECIAL_BASE 0x5953E80ull
+#define NIC10_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_TXE1_SPECIAL_SECTION 0x1800
+#define NIC10_TXB_BASE 0x5954000ull
+#define NIC10_TXB_MAX_OFFSET 0x1000
+#define NIC10_TXB_SECTION 0xE800
+#define NIC10_TXB_SPECIAL_BASE 0x5954E80ull
+#define NIC10_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_TXB_SPECIAL_SECTION 0x1800
+#define NIC10_MSTR_IF_RR_SHRD_HBW_BASE 0x5955000ull
+#define NIC10_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC10_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define NIC10_MSTR_IF_RR_PRVT_HBW_BASE 0x5955200ull
+#define NIC10_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC10_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define NIC10_MSTR_IF_RR_SHRD_LBW_BASE 0x5955400ull
+#define NIC10_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC10_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define NIC10_MSTR_IF_RR_PRVT_LBW_BASE 0x5955600ull
+#define NIC10_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC10_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define NIC10_MSTR_IF_E2E_CRDT_BASE 0x5955800ull
+#define NIC10_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC10_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define NIC10_MSTR_IF_AXUSER_BASE 0x5955A80ull
+#define NIC10_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC10_MSTR_IF_AXUSER_SECTION 0x8000
+#define NIC10_MSTR_IF_DBG_HBW_BASE 0x5955B00ull
+#define NIC10_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC10_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define NIC10_MSTR_IF_DBG_LBW_BASE 0x5955B80ull
+#define NIC10_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC10_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define NIC10_MSTR_IF_CORE_HBW_BASE 0x5955C00ull
+#define NIC10_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC10_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define NIC10_MSTR_IF_CORE_LBW_BASE 0x5955D80ull
+#define NIC10_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC10_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define NIC10_MSTR_IF_SPECIAL_BASE 0x5955E80ull
+#define NIC10_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_MSTR_IF_SPECIAL_SECTION 0x1800
+#define NIC10_TX_AXUSER_BASE 0x5956000ull
+#define NIC10_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC10_TX_AXUSER_SECTION 0x2000
+#define NIC10_SERDES0_BASE 0x5958000ull
+#define NIC10_SERDES0_MAX_OFFSET 0x3E40
+#define NIC10_SERDES0_SECTION 0x4000
+#define NIC10_SERDES1_BASE 0x595C000ull
+#define NIC10_SERDES1_MAX_OFFSET 0x3E40
+#define NIC10_SERDES1_SECTION 0x4000
+#define NIC10_PHY_BASE 0x5960000ull
+#define NIC10_PHY_MAX_OFFSET 0x1000
+#define NIC10_PHY_SECTION 0xE800
+#define NIC10_PHY_SPECIAL_BASE 0x5960E80ull
+#define NIC10_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_PHY_SPECIAL_SECTION 0x7180
+#define PRT10_MAC_AUX_BASE 0x5968000ull
+#define PRT10_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT10_MAC_AUX_SECTION 0xE800
+#define PRT10_MAC_AUX_SPECIAL_BASE 0x5968E80ull
+#define PRT10_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT10_MAC_AUX_SPECIAL_SECTION 0x1800
+#define PRT10_MAC_CORE_BASE 0x5969000ull
+#define PRT10_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT10_MAC_CORE_SECTION 0xE800
+#define PRT10_MAC_CORE_SPECIAL_BASE 0x5969E80ull
+#define PRT10_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT10_MAC_CORE_SPECIAL_SECTION 0x1800
+#define NIC10_MAC_RS_FEC_BASE 0x596A000ull
+#define NIC10_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC10_MAC_RS_FEC_SECTION 0x1000
+#define NIC10_MAC_GLOB_STAT_CONTROL_REG_BASE 0x596B000ull
+#define NIC10_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC10_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define NIC10_MAC_GLOB_STAT_RX0_BASE 0x596B100ull
+#define NIC10_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC10_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define NIC10_MAC_GLOB_STAT_RX1_BASE 0x596B18Cull
+#define NIC10_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC10_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define NIC10_MAC_GLOB_STAT_RX2_BASE 0x596B218ull
+#define NIC10_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC10_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define NIC10_MAC_GLOB_STAT_RX3_BASE 0x596B2A4ull
+#define NIC10_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC10_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define NIC10_MAC_GLOB_STAT_TX0_BASE 0x596B330ull
+#define NIC10_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC10_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define NIC10_MAC_GLOB_STAT_TX1_BASE 0x596B398ull
+#define NIC10_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC10_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define NIC10_MAC_GLOB_STAT_TX2_BASE 0x596B400ull
+#define NIC10_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC10_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define NIC10_MAC_GLOB_STAT_TX3_BASE 0x596B468ull
+#define NIC10_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC10_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define NIC10_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x596B800ull
+#define NIC10_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC10_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define NIC10_MAC_CH0_MAC_PCS_BASE 0x596C000ull
+#define NIC10_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC10_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define NIC10_MAC_CH0_MAC_128_BASE 0x596C400ull
+#define NIC10_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC10_MAC_CH0_MAC_128_SECTION 0x4000
+#define NIC10_MAC_CH0_MAC_AN_BASE 0x596C800ull
+#define NIC10_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC10_MAC_CH0_MAC_AN_SECTION 0x8000
+#define NIC10_MAC_CH1_MAC_PCS_BASE 0x596D000ull
+#define NIC10_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC10_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define NIC10_MAC_CH1_MAC_128_BASE 0x596D400ull
+#define NIC10_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC10_MAC_CH1_MAC_128_SECTION 0x4000
+#define NIC10_MAC_CH1_MAC_AN_BASE 0x596D800ull
+#define NIC10_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC10_MAC_CH1_MAC_AN_SECTION 0x8000
+#define NIC10_MAC_CH2_MAC_PCS_BASE 0x596E000ull
+#define NIC10_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC10_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define NIC10_MAC_CH2_MAC_128_BASE 0x596E400ull
+#define NIC10_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC10_MAC_CH2_MAC_128_SECTION 0x4000
+#define NIC10_MAC_CH2_MAC_AN_BASE 0x596E800ull
+#define NIC10_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC10_MAC_CH2_MAC_AN_SECTION 0x8000
+#define NIC10_MAC_CH3_MAC_PCS_BASE 0x596F000ull
+#define NIC10_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC10_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define NIC10_MAC_CH3_MAC_128_BASE 0x596F400ull
+#define NIC10_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC10_MAC_CH3_MAC_128_SECTION 0x4000
+#define NIC10_MAC_CH3_MAC_AN_BASE 0x596F800ull
+#define NIC10_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC10_MAC_CH3_MAC_AN_SECTION 0x10800
+#define NIC11_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5980000ull
+#define NIC11_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5980080ull
+#define NIC11_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5980100ull
+#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5980180ull
+#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_0_SPECIAL_BASE 0x5980E80ull
+#define NIC11_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_0_SPECIAL_SECTION 0x1800
+#define NIC11_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5981000ull
+#define NIC11_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5981080ull
+#define NIC11_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5981100ull
+#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5981180ull
+#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_1_SPECIAL_BASE 0x5981E80ull
+#define NIC11_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_1_SPECIAL_SECTION 0x1800
+#define NIC11_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5982000ull
+#define NIC11_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5982080ull
+#define NIC11_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5982100ull
+#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5982180ull
+#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_2_SPECIAL_BASE 0x5982E80ull
+#define NIC11_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_2_SPECIAL_SECTION 0x1800
+#define NIC11_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5983000ull
+#define NIC11_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5983080ull
+#define NIC11_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5983100ull
+#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5983180ull
+#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_3_SPECIAL_BASE 0x5983E80ull
+#define NIC11_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_3_SPECIAL_SECTION 0x1800
+#define NIC11_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5984000ull
+#define NIC11_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5984080ull
+#define NIC11_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5984100ull
+#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5984180ull
+#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_4_SPECIAL_BASE 0x5984E80ull
+#define NIC11_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_4_SPECIAL_SECTION 0x1800
+#define NIC11_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5985000ull
+#define NIC11_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5985080ull
+#define NIC11_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5985100ull
+#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5985180ull
+#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_5_SPECIAL_BASE 0x5985E80ull
+#define NIC11_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_5_SPECIAL_SECTION 0x1800
+#define NIC11_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5986000ull
+#define NIC11_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5986080ull
+#define NIC11_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5986100ull
+#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5986180ull
+#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_6_SPECIAL_BASE 0x5986E80ull
+#define NIC11_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_6_SPECIAL_SECTION 0x1800
+#define NIC11_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5987000ull
+#define NIC11_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5987080ull
+#define NIC11_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5987100ull
+#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5987180ull
+#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_7_SPECIAL_BASE 0x5987E80ull
+#define NIC11_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_7_SPECIAL_SECTION 0x1800
+#define NIC11_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5988000ull
+#define NIC11_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5988080ull
+#define NIC11_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5988100ull
+#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5988180ull
+#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_8_SPECIAL_BASE 0x5988E80ull
+#define NIC11_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_8_SPECIAL_SECTION 0x1800
+#define NIC11_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5989000ull
+#define NIC11_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5989080ull
+#define NIC11_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5989100ull
+#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5989180ull
+#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_9_SPECIAL_BASE 0x5989E80ull
+#define NIC11_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_9_SPECIAL_SECTION 0x1800
+#define NIC11_UMR0_10_UNSECURE_DOORBELL0_BASE 0x598A000ull
+#define NIC11_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_10_UNSECURE_DOORBELL1_BASE 0x598A080ull
+#define NIC11_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x598A100ull
+#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x598A180ull
+#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_10_SPECIAL_BASE 0x598AE80ull
+#define NIC11_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_10_SPECIAL_SECTION 0x1800
+#define NIC11_UMR0_11_UNSECURE_DOORBELL0_BASE 0x598B000ull
+#define NIC11_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_11_UNSECURE_DOORBELL1_BASE 0x598B080ull
+#define NIC11_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x598B100ull
+#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x598B180ull
+#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_11_SPECIAL_BASE 0x598BE80ull
+#define NIC11_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_11_SPECIAL_SECTION 0x1800
+#define NIC11_UMR0_12_UNSECURE_DOORBELL0_BASE 0x598C000ull
+#define NIC11_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_12_UNSECURE_DOORBELL1_BASE 0x598C080ull
+#define NIC11_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x598C100ull
+#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x598C180ull
+#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_12_SPECIAL_BASE 0x598CE80ull
+#define NIC11_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_12_SPECIAL_SECTION 0x1800
+#define NIC11_UMR0_13_UNSECURE_DOORBELL0_BASE 0x598D000ull
+#define NIC11_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_13_UNSECURE_DOORBELL1_BASE 0x598D080ull
+#define NIC11_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x598D100ull
+#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x598D180ull
+#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_13_SPECIAL_BASE 0x598DE80ull
+#define NIC11_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_13_SPECIAL_SECTION 0x1800
+#define NIC11_UMR0_14_UNSECURE_DOORBELL0_BASE 0x598E000ull
+#define NIC11_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR0_14_UNSECURE_DOORBELL1_BASE 0x598E080ull
+#define NIC11_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x598E100ull
+#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x598E180ull
+#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR0_14_SPECIAL_BASE 0x598EE80ull
+#define NIC11_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_14_SPECIAL_SECTION 0x1180
+#define NIC11_QM_DCCM0_BASE 0x5990000ull
+#define NIC11_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC11_QM_DCCM0_SECTION 0x8000
+#define NIC11_QM_ARC_AUX0_BASE 0x5998000ull
+#define NIC11_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC11_QM_ARC_AUX0_SECTION 0xE800
+#define NIC11_QM_ARC_AUX0_SPECIAL_BASE 0x5998E80ull
+#define NIC11_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define NIC11_QM0_BASE 0x599A000ull
+#define NIC11_QM0_MAX_OFFSET 0x1000
+#define NIC11_QM0_SECTION 0x9000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x599A900ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x599A908ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x599A910ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x599A918ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x599A920ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x599A928ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x599A930ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x599A938ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x599A940ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x599A948ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x599A950ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x599A958ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x599A960ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x599A968ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x599A970ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x599A978ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC11_QM0_AXUSER_SECURED_BASE 0x599AB00ull
+#define NIC11_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC11_QM0_AXUSER_SECURED_SECTION 0x8000
+#define NIC11_QM0_AXUSER_NONSECURED_BASE 0x599AB80ull
+#define NIC11_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC11_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC11_QM0_DBG_HBW_BASE 0x599AC00ull
+#define NIC11_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC11_QM0_DBG_HBW_SECTION 0x8000
+#define NIC11_QM0_DBG_LBW_BASE 0x599AC80ull
+#define NIC11_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC11_QM0_DBG_LBW_SECTION 0x1000
+#define NIC11_QM0_CGM_BASE 0x599AD80ull
+#define NIC11_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC11_QM0_CGM_SECTION 0x1000
+#define NIC11_QM0_SPECIAL_BASE 0x599AE80ull
+#define NIC11_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_QM0_SPECIAL_SECTION 0x4180
+#define NIC11_QPC0_BASE 0x599F000ull
+#define NIC11_QPC0_MAX_OFFSET 0x1000
+#define NIC11_QPC0_SECTION 0x7200
+#define NIC11_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x599F720ull
+#define NIC11_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x599F728ull
+#define NIC11_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x599F730ull
+#define NIC11_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x599F738ull
+#define NIC11_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x599F740ull
+#define NIC11_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x599F748ull
+#define NIC11_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x599F750ull
+#define NIC11_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x599F758ull
+#define NIC11_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x599F760ull
+#define NIC11_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x599F768ull
+#define NIC11_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x599F770ull
+#define NIC11_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x599F778ull
+#define NIC11_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x599F780ull
+#define NIC11_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x599F788ull
+#define NIC11_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x599F790ull
+#define NIC11_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x599F798ull
+#define NIC11_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x599F7A0ull
+#define NIC11_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x599F7A8ull
+#define NIC11_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x599F7B0ull
+#define NIC11_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x599F7B8ull
+#define NIC11_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x599F7C0ull
+#define NIC11_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x599F7C8ull
+#define NIC11_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x599F7D0ull
+#define NIC11_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x599F7D8ull
+#define NIC11_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x599F7E0ull
+#define NIC11_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x599F7E8ull
+#define NIC11_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x599F7F0ull
+#define NIC11_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x599F7F8ull
+#define NIC11_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x599F800ull
+#define NIC11_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x599F808ull
+#define NIC11_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x599F810ull
+#define NIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x599F818ull
+#define NIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC11_QPC0_AXUSER_CONG_QUE_BASE 0x599FB80ull
+#define NIC11_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC11_QPC0_AXUSER_RXWQE_BASE 0x599FBE0ull
+#define NIC11_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define NIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x599FC40ull
+#define NIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC11_QPC0_AXUSER_DB_FIFO_BASE 0x599FCA0ull
+#define NIC11_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x599FD00ull
+#define NIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC11_QPC0_AXUSER_ERR_FIFO_BASE 0x599FD60ull
+#define NIC11_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC11_QPC0_AXUSER_QPC_RESP_BASE 0x599FDC0ull
+#define NIC11_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC11_QPC0_AXUSER_QPC_REQ_BASE 0x599FE20ull
+#define NIC11_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC11_QPC0_SPECIAL_BASE 0x599FE80ull
+#define NIC11_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_QPC0_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_0_UNSECURE_DOORBELL0_BASE 0x59A0000ull
+#define NIC11_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_0_UNSECURE_DOORBELL1_BASE 0x59A0080ull
+#define NIC11_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x59A0100ull
+#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x59A0180ull
+#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_0_SPECIAL_BASE 0x59A0E80ull
+#define NIC11_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_0_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_1_UNSECURE_DOORBELL0_BASE 0x59A1000ull
+#define NIC11_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_1_UNSECURE_DOORBELL1_BASE 0x59A1080ull
+#define NIC11_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x59A1100ull
+#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x59A1180ull
+#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_1_SPECIAL_BASE 0x59A1E80ull
+#define NIC11_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_1_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_2_UNSECURE_DOORBELL0_BASE 0x59A2000ull
+#define NIC11_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_2_UNSECURE_DOORBELL1_BASE 0x59A2080ull
+#define NIC11_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x59A2100ull
+#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x59A2180ull
+#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_2_SPECIAL_BASE 0x59A2E80ull
+#define NIC11_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_2_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_3_UNSECURE_DOORBELL0_BASE 0x59A3000ull
+#define NIC11_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_3_UNSECURE_DOORBELL1_BASE 0x59A3080ull
+#define NIC11_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x59A3100ull
+#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x59A3180ull
+#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_3_SPECIAL_BASE 0x59A3E80ull
+#define NIC11_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_3_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_4_UNSECURE_DOORBELL0_BASE 0x59A4000ull
+#define NIC11_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_4_UNSECURE_DOORBELL1_BASE 0x59A4080ull
+#define NIC11_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x59A4100ull
+#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x59A4180ull
+#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_4_SPECIAL_BASE 0x59A4E80ull
+#define NIC11_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_4_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_5_UNSECURE_DOORBELL0_BASE 0x59A5000ull
+#define NIC11_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_5_UNSECURE_DOORBELL1_BASE 0x59A5080ull
+#define NIC11_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x59A5100ull
+#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x59A5180ull
+#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_5_SPECIAL_BASE 0x59A5E80ull
+#define NIC11_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_5_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_6_UNSECURE_DOORBELL0_BASE 0x59A6000ull
+#define NIC11_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_6_UNSECURE_DOORBELL1_BASE 0x59A6080ull
+#define NIC11_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x59A6100ull
+#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x59A6180ull
+#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_6_SPECIAL_BASE 0x59A6E80ull
+#define NIC11_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_6_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_7_UNSECURE_DOORBELL0_BASE 0x59A7000ull
+#define NIC11_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_7_UNSECURE_DOORBELL1_BASE 0x59A7080ull
+#define NIC11_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x59A7100ull
+#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x59A7180ull
+#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_7_SPECIAL_BASE 0x59A7E80ull
+#define NIC11_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_7_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_8_UNSECURE_DOORBELL0_BASE 0x59A8000ull
+#define NIC11_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_8_UNSECURE_DOORBELL1_BASE 0x59A8080ull
+#define NIC11_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x59A8100ull
+#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x59A8180ull
+#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_8_SPECIAL_BASE 0x59A8E80ull
+#define NIC11_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_8_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_9_UNSECURE_DOORBELL0_BASE 0x59A9000ull
+#define NIC11_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_9_UNSECURE_DOORBELL1_BASE 0x59A9080ull
+#define NIC11_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x59A9100ull
+#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x59A9180ull
+#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_9_SPECIAL_BASE 0x59A9E80ull
+#define NIC11_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_9_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_10_UNSECURE_DOORBELL0_BASE 0x59AA000ull
+#define NIC11_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_10_UNSECURE_DOORBELL1_BASE 0x59AA080ull
+#define NIC11_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x59AA100ull
+#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x59AA180ull
+#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_10_SPECIAL_BASE 0x59AAE80ull
+#define NIC11_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_10_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_11_UNSECURE_DOORBELL0_BASE 0x59AB000ull
+#define NIC11_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_11_UNSECURE_DOORBELL1_BASE 0x59AB080ull
+#define NIC11_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x59AB100ull
+#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x59AB180ull
+#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_11_SPECIAL_BASE 0x59ABE80ull
+#define NIC11_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_11_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_12_UNSECURE_DOORBELL0_BASE 0x59AC000ull
+#define NIC11_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_12_UNSECURE_DOORBELL1_BASE 0x59AC080ull
+#define NIC11_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x59AC100ull
+#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x59AC180ull
+#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_12_SPECIAL_BASE 0x59ACE80ull
+#define NIC11_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_12_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_13_UNSECURE_DOORBELL0_BASE 0x59AD000ull
+#define NIC11_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_13_UNSECURE_DOORBELL1_BASE 0x59AD080ull
+#define NIC11_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x59AD100ull
+#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x59AD180ull
+#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_13_SPECIAL_BASE 0x59ADE80ull
+#define NIC11_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_13_SPECIAL_SECTION 0x1800
+#define NIC11_UMR1_14_UNSECURE_DOORBELL0_BASE 0x59AE000ull
+#define NIC11_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define NIC11_UMR1_14_UNSECURE_DOORBELL1_BASE 0x59AE080ull
+#define NIC11_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x59AE100ull
+#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x59AE180ull
+#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define NIC11_UMR1_14_SPECIAL_BASE 0x59AEE80ull
+#define NIC11_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_14_SPECIAL_SECTION 0x1180
+#define NIC11_QM_DCCM1_BASE 0x59B0000ull
+#define NIC11_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC11_QM_DCCM1_SECTION 0x8000
+#define NIC11_QM_ARC_AUX1_BASE 0x59B8000ull
+#define NIC11_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC11_QM_ARC_AUX1_SECTION 0xE800
+#define NIC11_QM_ARC_AUX1_SPECIAL_BASE 0x59B8E80ull
+#define NIC11_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define NIC11_QM1_BASE 0x59BA000ull
+#define NIC11_QM1_MAX_OFFSET 0x1000
+#define NIC11_QM1_SECTION 0x9000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x59BA900ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x59BA908ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x59BA910ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x59BA918ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x59BA920ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x59BA928ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x59BA930ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x59BA938ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x59BA940ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x59BA948ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x59BA950ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x59BA958ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x59BA960ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x59BA968ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x59BA970ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x59BA978ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define NIC11_QM1_AXUSER_SECURED_BASE 0x59BAB00ull
+#define NIC11_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC11_QM1_AXUSER_SECURED_SECTION 0x8000
+#define NIC11_QM1_AXUSER_NONSECURED_BASE 0x59BAB80ull
+#define NIC11_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC11_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define NIC11_QM1_DBG_HBW_BASE 0x59BAC00ull
+#define NIC11_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC11_QM1_DBG_HBW_SECTION 0x8000
+#define NIC11_QM1_DBG_LBW_BASE 0x59BAC80ull
+#define NIC11_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC11_QM1_DBG_LBW_SECTION 0x1000
+#define NIC11_QM1_CGM_BASE 0x59BAD80ull
+#define NIC11_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC11_QM1_CGM_SECTION 0x1000
+#define NIC11_QM1_SPECIAL_BASE 0x59BAE80ull
+#define NIC11_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_QM1_SPECIAL_SECTION 0x4180
+#define NIC11_QPC1_BASE 0x59BF000ull
+#define NIC11_QPC1_MAX_OFFSET 0x1000
+#define NIC11_QPC1_SECTION 0x7200
+#define NIC11_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x59BF720ull
+#define NIC11_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x59BF728ull
+#define NIC11_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x59BF730ull
+#define NIC11_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x59BF738ull
+#define NIC11_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x59BF740ull
+#define NIC11_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x59BF748ull
+#define NIC11_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x59BF750ull
+#define NIC11_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x59BF758ull
+#define NIC11_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x59BF760ull
+#define NIC11_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x59BF768ull
+#define NIC11_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x59BF770ull
+#define NIC11_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x59BF778ull
+#define NIC11_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x59BF780ull
+#define NIC11_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x59BF788ull
+#define NIC11_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x59BF790ull
+#define NIC11_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x59BF798ull
+#define NIC11_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x59BF7A0ull
+#define NIC11_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x59BF7A8ull
+#define NIC11_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x59BF7B0ull
+#define NIC11_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x59BF7B8ull
+#define NIC11_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x59BF7C0ull
+#define NIC11_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x59BF7C8ull
+#define NIC11_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x59BF7D0ull
+#define NIC11_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x59BF7D8ull
+#define NIC11_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x59BF7E0ull
+#define NIC11_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x59BF7E8ull
+#define NIC11_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x59BF7F0ull
+#define NIC11_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x59BF7F8ull
+#define NIC11_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x59BF800ull
+#define NIC11_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x59BF808ull
+#define NIC11_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x59BF810ull
+#define NIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define NIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x59BF818ull
+#define NIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define NIC11_QPC1_AXUSER_CONG_QUE_BASE 0x59BFB80ull
+#define NIC11_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define NIC11_QPC1_AXUSER_RXWQE_BASE 0x59BFBE0ull
+#define NIC11_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define NIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x59BFC40ull
+#define NIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define NIC11_QPC1_AXUSER_DB_FIFO_BASE 0x59BFCA0ull
+#define NIC11_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define NIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x59BFD00ull
+#define NIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define NIC11_QPC1_AXUSER_ERR_FIFO_BASE 0x59BFD60ull
+#define NIC11_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define NIC11_QPC1_AXUSER_QPC_RESP_BASE 0x59BFDC0ull
+#define NIC11_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define NIC11_QPC1_AXUSER_QPC_REQ_BASE 0x59BFE20ull
+#define NIC11_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define NIC11_QPC1_SPECIAL_BASE 0x59BFE80ull
+#define NIC11_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_QPC1_SPECIAL_SECTION 0x8180
+#define NIC11_TMR_BASE 0x59C8000ull
+#define NIC11_TMR_MAX_OFFSET 0x1000
+#define NIC11_TMR_SECTION 0xD600
+#define NIC11_TMR_AXUSER_TMR_FREE_LIST_BASE 0x59C8D60ull
+#define NIC11_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC11_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define NIC11_TMR_AXUSER_TMR_FIFO_BASE 0x59C8DC0ull
+#define NIC11_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC11_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define NIC11_TMR_AXUSER_TMR_FSM_BASE 0x59C8E20ull
+#define NIC11_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC11_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define NIC11_TMR_SPECIAL_BASE 0x59C8E80ull
+#define NIC11_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_TMR_SPECIAL_SECTION 0x1800
+#define NIC11_RXB_CORE_BASE 0x59C9000ull
+#define NIC11_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC11_RXB_CORE_SECTION 0x6100
+#define NIC11_RXB_CORE_SCT_AWUSER_BASE 0x59C9610ull
+#define NIC11_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC11_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define NIC11_RXB_CORE_SPECIAL_BASE 0x59C9E80ull
+#define NIC11_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_RXB_CORE_SPECIAL_SECTION 0x1800
+#define NIC11_RXE0_BASE 0x59CA000ull
+#define NIC11_RXE0_MAX_OFFSET 0x1000
+#define NIC11_RXE0_SECTION 0x9000
+#define NIC11_RXE0_WQE_ARUSER_BASE 0x59CA900ull
+#define NIC11_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC11_RXE0_WQE_ARUSER_SECTION 0x5800
+#define NIC11_RXE0_SPECIAL_BASE 0x59CAE80ull
+#define NIC11_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_RXE0_SPECIAL_SECTION 0x1800
+#define NIC11_RXE1_BASE 0x59CB000ull
+#define NIC11_RXE1_MAX_OFFSET 0x1000
+#define NIC11_RXE1_SECTION 0x9000
+#define NIC11_RXE1_WQE_ARUSER_BASE 0x59CB900ull
+#define NIC11_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC11_RXE1_WQE_ARUSER_SECTION 0x5800
+#define NIC11_RXE1_SPECIAL_BASE 0x59CBE80ull
+#define NIC11_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_RXE1_SPECIAL_SECTION 0x1800
+#define NIC11_RXE0_AXUSER_AXUSER_CQ0_BASE 0x59CC000ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ1_BASE 0x59CC050ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ2_BASE 0x59CC0A0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ3_BASE 0x59CC0F0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ4_BASE 0x59CC140ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ5_BASE 0x59CC190ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ6_BASE 0x59CC1E0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ7_BASE 0x59CC230ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ8_BASE 0x59CC280ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ9_BASE 0x59CC2D0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ10_BASE 0x59CC320ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ11_BASE 0x59CC370ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ12_BASE 0x59CC3C0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ13_BASE 0x59CC410ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ14_BASE 0x59CC460ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ15_BASE 0x59CC4B0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ16_BASE 0x59CC500ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ17_BASE 0x59CC550ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ18_BASE 0x59CC5A0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ19_BASE 0x59CC5F0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ20_BASE 0x59CC640ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ21_BASE 0x59CC690ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ22_BASE 0x59CC6E0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ23_BASE 0x59CC730ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ24_BASE 0x59CC780ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ25_BASE 0x59CC7D0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ26_BASE 0x59CC820ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ27_BASE 0x59CC870ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ28_BASE 0x59CC8C0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ29_BASE 0x59CC910ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ30_BASE 0x59CC960ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ31_BASE 0x59CC9B0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC11_RXE0_AXUSER_SPECIAL_BASE 0x59CCE80ull
+#define NIC11_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define NIC11_RXE1_AXUSER_AXUSER_CQ0_BASE 0x59CD000ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ1_BASE 0x59CD050ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ2_BASE 0x59CD0A0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ3_BASE 0x59CD0F0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ4_BASE 0x59CD140ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ5_BASE 0x59CD190ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ6_BASE 0x59CD1E0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ7_BASE 0x59CD230ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ8_BASE 0x59CD280ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ9_BASE 0x59CD2D0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ10_BASE 0x59CD320ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ11_BASE 0x59CD370ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ12_BASE 0x59CD3C0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ13_BASE 0x59CD410ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ14_BASE 0x59CD460ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ15_BASE 0x59CD4B0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ16_BASE 0x59CD500ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ17_BASE 0x59CD550ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ18_BASE 0x59CD5A0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ19_BASE 0x59CD5F0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ20_BASE 0x59CD640ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ21_BASE 0x59CD690ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ22_BASE 0x59CD6E0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ23_BASE 0x59CD730ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ24_BASE 0x59CD780ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ25_BASE 0x59CD7D0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ26_BASE 0x59CD820ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ27_BASE 0x59CD870ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ28_BASE 0x59CD8C0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ29_BASE 0x59CD910ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ30_BASE 0x59CD960ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ31_BASE 0x59CD9B0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define NIC11_RXE1_AXUSER_SPECIAL_BASE 0x59CDE80ull
+#define NIC11_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define NIC11_TXS0_BASE 0x59D0000ull
+#define NIC11_TXS0_MAX_OFFSET 0x1000
+#define NIC11_TXS0_SECTION 0xE800
+#define NIC11_TXS0_SPECIAL_BASE 0x59D0E80ull
+#define NIC11_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_TXS0_SPECIAL_SECTION 0x1800
+#define NIC11_TXS1_BASE 0x59D1000ull
+#define NIC11_TXS1_MAX_OFFSET 0x1000
+#define NIC11_TXS1_SECTION 0xE800
+#define NIC11_TXS1_SPECIAL_BASE 0x59D1E80ull
+#define NIC11_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_TXS1_SPECIAL_SECTION 0x1800
+#define NIC11_TXE0_BASE 0x59D2000ull
+#define NIC11_TXE0_MAX_OFFSET 0x1000
+#define NIC11_TXE0_SECTION 0xE800
+#define NIC11_TXE0_SPECIAL_BASE 0x59D2E80ull
+#define NIC11_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_TXE0_SPECIAL_SECTION 0x1800
+#define NIC11_TXE1_BASE 0x59D3000ull
+#define NIC11_TXE1_MAX_OFFSET 0x1000
+#define NIC11_TXE1_SECTION 0xE800
+#define NIC11_TXE1_SPECIAL_BASE 0x59D3E80ull
+#define NIC11_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_TXE1_SPECIAL_SECTION 0x1800
+#define NIC11_TXB_BASE 0x59D4000ull
+#define NIC11_TXB_MAX_OFFSET 0x1000
+#define NIC11_TXB_SECTION 0xE800
+#define NIC11_TXB_SPECIAL_BASE 0x59D4E80ull
+#define NIC11_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_TXB_SPECIAL_SECTION 0x1800
+#define NIC11_MSTR_IF_RR_SHRD_HBW_BASE 0x59D5000ull
+#define NIC11_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC11_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define NIC11_MSTR_IF_RR_PRVT_HBW_BASE 0x59D5200ull
+#define NIC11_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC11_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define NIC11_MSTR_IF_RR_SHRD_LBW_BASE 0x59D5400ull
+#define NIC11_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC11_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define NIC11_MSTR_IF_RR_PRVT_LBW_BASE 0x59D5600ull
+#define NIC11_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC11_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define NIC11_MSTR_IF_E2E_CRDT_BASE 0x59D5800ull
+#define NIC11_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC11_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define NIC11_MSTR_IF_AXUSER_BASE 0x59D5A80ull
+#define NIC11_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC11_MSTR_IF_AXUSER_SECTION 0x8000
+#define NIC11_MSTR_IF_DBG_HBW_BASE 0x59D5B00ull
+#define NIC11_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC11_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define NIC11_MSTR_IF_DBG_LBW_BASE 0x59D5B80ull
+#define NIC11_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC11_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define NIC11_MSTR_IF_CORE_HBW_BASE 0x59D5C00ull
+#define NIC11_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC11_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define NIC11_MSTR_IF_CORE_LBW_BASE 0x59D5D80ull
+#define NIC11_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC11_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define NIC11_MSTR_IF_SPECIAL_BASE 0x59D5E80ull
+#define NIC11_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_MSTR_IF_SPECIAL_SECTION 0x1800
+#define NIC11_TX_AXUSER_BASE 0x59D6000ull
+#define NIC11_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC11_TX_AXUSER_SECTION 0x2000
+#define NIC11_SERDES0_BASE 0x59D8000ull
+#define NIC11_SERDES0_MAX_OFFSET 0x3E40
+#define NIC11_SERDES0_SECTION 0x4000
+#define NIC11_SERDES1_BASE 0x59DC000ull
+#define NIC11_SERDES1_MAX_OFFSET 0x3E40
+#define NIC11_SERDES1_SECTION 0x4000
+#define NIC11_PHY_BASE 0x59E0000ull
+#define NIC11_PHY_MAX_OFFSET 0x1000
+#define NIC11_PHY_SECTION 0xE800
+#define NIC11_PHY_SPECIAL_BASE 0x59E0E80ull
+#define NIC11_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_PHY_SPECIAL_SECTION 0x7180
+#define PRT11_MAC_AUX_BASE 0x59E8000ull
+#define PRT11_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT11_MAC_AUX_SECTION 0xE800
+#define PRT11_MAC_AUX_SPECIAL_BASE 0x59E8E80ull
+#define PRT11_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT11_MAC_AUX_SPECIAL_SECTION 0x1800
+#define PRT11_MAC_CORE_BASE 0x59E9000ull
+#define PRT11_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT11_MAC_CORE_SECTION 0xE800
+#define PRT11_MAC_CORE_SPECIAL_BASE 0x59E9E80ull
+#define PRT11_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT11_MAC_CORE_SPECIAL_SECTION 0x1800
+#define NIC11_MAC_RS_FEC_BASE 0x59EA000ull
+#define NIC11_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC11_MAC_RS_FEC_SECTION 0x1000
+#define NIC11_MAC_GLOB_STAT_CONTROL_REG_BASE 0x59EB000ull
+#define NIC11_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC11_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define NIC11_MAC_GLOB_STAT_RX0_BASE 0x59EB100ull
+#define NIC11_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC11_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define NIC11_MAC_GLOB_STAT_RX1_BASE 0x59EB18Cull
+#define NIC11_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC11_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define NIC11_MAC_GLOB_STAT_RX2_BASE 0x59EB218ull
+#define NIC11_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC11_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define NIC11_MAC_GLOB_STAT_RX3_BASE 0x59EB2A4ull
+#define NIC11_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC11_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define NIC11_MAC_GLOB_STAT_TX0_BASE 0x59EB330ull
+#define NIC11_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC11_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define NIC11_MAC_GLOB_STAT_TX1_BASE 0x59EB398ull
+#define NIC11_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC11_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define NIC11_MAC_GLOB_STAT_TX2_BASE 0x59EB400ull
+#define NIC11_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC11_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define NIC11_MAC_GLOB_STAT_TX3_BASE 0x59EB468ull
+#define NIC11_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC11_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define NIC11_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x59EB800ull
+#define NIC11_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC11_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define NIC11_MAC_CH0_MAC_PCS_BASE 0x59EC000ull
+#define NIC11_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC11_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define NIC11_MAC_CH0_MAC_128_BASE 0x59EC400ull
+#define NIC11_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC11_MAC_CH0_MAC_128_SECTION 0x4000
+#define NIC11_MAC_CH0_MAC_AN_BASE 0x59EC800ull
+#define NIC11_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC11_MAC_CH0_MAC_AN_SECTION 0x8000
+#define NIC11_MAC_CH1_MAC_PCS_BASE 0x59ED000ull
+#define NIC11_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC11_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define NIC11_MAC_CH1_MAC_128_BASE 0x59ED400ull
+#define NIC11_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC11_MAC_CH1_MAC_128_SECTION 0x4000
+#define NIC11_MAC_CH1_MAC_AN_BASE 0x59ED800ull
+#define NIC11_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC11_MAC_CH1_MAC_AN_SECTION 0x8000
+#define NIC11_MAC_CH2_MAC_PCS_BASE 0x59EE000ull
+#define NIC11_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC11_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define NIC11_MAC_CH2_MAC_128_BASE 0x59EE400ull
+#define NIC11_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC11_MAC_CH2_MAC_128_SECTION 0x4000
+#define NIC11_MAC_CH2_MAC_AN_BASE 0x59EE800ull
+#define NIC11_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC11_MAC_CH2_MAC_AN_SECTION 0x8000
+#define NIC11_MAC_CH3_MAC_PCS_BASE 0x59EF000ull
+#define NIC11_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC11_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define NIC11_MAC_CH3_MAC_128_BASE 0x59EF400ull
+#define NIC11_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC11_MAC_CH3_MAC_128_SECTION 0x4000
+#define NIC11_MAC_CH3_MAC_AN_BASE 0x59EF800ull
+#define NIC11_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC11_MAC_CH3_MAC_AN_SECTION 0x610800
+#define DCORE0_ROM_TABLE_L_BASE 0x6000000ull
+#define DCORE0_ROM_TABLE_L_MAX_OFFSET 0x1000
+#define DCORE0_ROM_TABLE_L_SECTION 0x80000
+#define DCORE0_HMMU0_CS_ROM_TBL_BASE 0x6080000ull
+#define DCORE0_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_CS_ROM_TBL_SECTION 0x1000
+#define DCORE0_HMMU0_CS_STM_BASE 0x6081000ull
+#define DCORE0_HMMU0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_CS_STM_SECTION 0x1000
+#define DCORE0_HMMU0_CS_CTI_BASE 0x6082000ull
+#define DCORE0_HMMU0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_CS_CTI_SECTION 0x1000
+#define DCORE0_HMMU0_CS_ETF_BASE 0x6083000ull
+#define DCORE0_HMMU0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_CS_ETF_SECTION 0x1000
+#define DCORE0_HMMU0_CS_SPMU_BASE 0x6084000ull
+#define DCORE0_HMMU0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_CS_SPMU_SECTION 0x1000
+#define DCORE0_HMMU0_BMON_CTI_BASE 0x6085000ull
+#define DCORE0_HMMU0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_BMON_CTI_SECTION 0x1000
+#define DCORE0_HMMU0_USER_CTI_BASE 0x6086000ull
+#define DCORE0_HMMU0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_USER_CTI_SECTION 0x1000
+#define DCORE0_HMMU0_BMON_0_BASE 0x6087000ull
+#define DCORE0_HMMU0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_BMON_0_SECTION 0x1000
+#define DCORE0_HMMU0_BMON_1_BASE 0x6088000ull
+#define DCORE0_HMMU0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_BMON_1_SECTION 0x1000
+#define DCORE0_HMMU0_BMON_3_BASE 0x6089000ull
+#define DCORE0_HMMU0_BMON_3_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_BMON_3_SECTION 0x1000
+#define DCORE0_HMMU0_BMON_2_BASE 0x608A000ull
+#define DCORE0_HMMU0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_BMON_2_SECTION 0x1000
+#define DCORE0_HMMU0_BMON_4_BASE 0x608B000ull
+#define DCORE0_HMMU0_BMON_4_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_BMON_4_SECTION 0x5000
+#define DCORE0_HMMU1_CS_ROM_TBL_BASE 0x6090000ull
+#define DCORE0_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_CS_ROM_TBL_SECTION 0x1000
+#define DCORE0_HMMU1_CS_STM_BASE 0x6091000ull
+#define DCORE0_HMMU1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_CS_STM_SECTION 0x1000
+#define DCORE0_HMMU1_CS_CTI_BASE 0x6092000ull
+#define DCORE0_HMMU1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_CS_CTI_SECTION 0x1000
+#define DCORE0_HMMU1_CS_ETF_BASE 0x6093000ull
+#define DCORE0_HMMU1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_CS_ETF_SECTION 0x1000
+#define DCORE0_HMMU1_CS_SPMU_BASE 0x6094000ull
+#define DCORE0_HMMU1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_CS_SPMU_SECTION 0x1000
+#define DCORE0_HMMU1_BMON_CTI_BASE 0x6095000ull
+#define DCORE0_HMMU1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_BMON_CTI_SECTION 0x1000
+#define DCORE0_HMMU1_USER_CTI_BASE 0x6096000ull
+#define DCORE0_HMMU1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_USER_CTI_SECTION 0x1000
+#define DCORE0_HMMU1_BMON_0_BASE 0x6097000ull
+#define DCORE0_HMMU1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_BMON_0_SECTION 0x1000
+#define DCORE0_HMMU1_BMON_1_BASE 0x6098000ull
+#define DCORE0_HMMU1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_BMON_1_SECTION 0x1000
+#define DCORE0_HMMU1_BMON_3_BASE 0x6099000ull
+#define DCORE0_HMMU1_BMON_3_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_BMON_3_SECTION 0x1000
+#define DCORE0_HMMU1_BMON_2_BASE 0x609A000ull
+#define DCORE0_HMMU1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_BMON_2_SECTION 0x1000
+#define DCORE0_HMMU1_BMON_4_BASE 0x609B000ull
+#define DCORE0_HMMU1_BMON_4_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_BMON_4_SECTION 0x5000
+#define DCORE0_HMMU2_CS_ROM_TBL_BASE 0x60A0000ull
+#define DCORE0_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_CS_ROM_TBL_SECTION 0x1000
+#define DCORE0_HMMU2_CS_STM_BASE 0x60A1000ull
+#define DCORE0_HMMU2_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_CS_STM_SECTION 0x1000
+#define DCORE0_HMMU2_CS_CTI_BASE 0x60A2000ull
+#define DCORE0_HMMU2_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_CS_CTI_SECTION 0x1000
+#define DCORE0_HMMU2_CS_ETF_BASE 0x60A3000ull
+#define DCORE0_HMMU2_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_CS_ETF_SECTION 0x1000
+#define DCORE0_HMMU2_CS_SPMU_BASE 0x60A4000ull
+#define DCORE0_HMMU2_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_CS_SPMU_SECTION 0x1000
+#define DCORE0_HMMU2_BMON_CTI_BASE 0x60A5000ull
+#define DCORE0_HMMU2_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_BMON_CTI_SECTION 0x1000
+#define DCORE0_HMMU2_USER_CTI_BASE 0x60A6000ull
+#define DCORE0_HMMU2_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_USER_CTI_SECTION 0x1000
+#define DCORE0_HMMU2_BMON_0_BASE 0x60A7000ull
+#define DCORE0_HMMU2_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_BMON_0_SECTION 0x1000
+#define DCORE0_HMMU2_BMON_1_BASE 0x60A8000ull
+#define DCORE0_HMMU2_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_BMON_1_SECTION 0x1000
+#define DCORE0_HMMU2_BMON_3_BASE 0x60A9000ull
+#define DCORE0_HMMU2_BMON_3_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_BMON_3_SECTION 0x1000
+#define DCORE0_HMMU2_BMON_2_BASE 0x60AA000ull
+#define DCORE0_HMMU2_BMON_2_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_BMON_2_SECTION 0x1000
+#define DCORE0_HMMU2_BMON_4_BASE 0x60AB000ull
+#define DCORE0_HMMU2_BMON_4_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_BMON_4_SECTION 0x5000
+#define DCORE0_HMMU3_CS_ROM_TBL_BASE 0x60B0000ull
+#define DCORE0_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_CS_ROM_TBL_SECTION 0x1000
+#define DCORE0_HMMU3_CS_STM_BASE 0x60B1000ull
+#define DCORE0_HMMU3_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_CS_STM_SECTION 0x1000
+#define DCORE0_HMMU3_CS_CTI_BASE 0x60B2000ull
+#define DCORE0_HMMU3_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_CS_CTI_SECTION 0x1000
+#define DCORE0_HMMU3_CS_ETF_BASE 0x60B3000ull
+#define DCORE0_HMMU3_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_CS_ETF_SECTION 0x1000
+#define DCORE0_HMMU3_CS_SPMU_BASE 0x60B4000ull
+#define DCORE0_HMMU3_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_CS_SPMU_SECTION 0x1000
+#define DCORE0_HMMU3_BMON_CTI_BASE 0x60B5000ull
+#define DCORE0_HMMU3_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_BMON_CTI_SECTION 0x1000
+#define DCORE0_HMMU3_USER_CTI_BASE 0x60B6000ull
+#define DCORE0_HMMU3_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_USER_CTI_SECTION 0x1000
+#define DCORE0_HMMU3_BMON_0_BASE 0x60B7000ull
+#define DCORE0_HMMU3_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_BMON_0_SECTION 0x1000
+#define DCORE0_HMMU3_BMON_1_BASE 0x60B8000ull
+#define DCORE0_HMMU3_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_BMON_1_SECTION 0x1000
+#define DCORE0_HMMU3_BMON_3_BASE 0x60B9000ull
+#define DCORE0_HMMU3_BMON_3_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_BMON_3_SECTION 0x1000
+#define DCORE0_HMMU3_BMON_2_BASE 0x60BA000ull
+#define DCORE0_HMMU3_BMON_2_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_BMON_2_SECTION 0x1000
+#define DCORE0_HMMU3_BMON_4_BASE 0x60BB000ull
+#define DCORE0_HMMU3_BMON_4_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_BMON_4_SECTION 0x5000
+#define DCORE0_MME_CTRL_ROM_TABLE_BASE 0x60C0000ull
+#define DCORE0_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_ROM_TABLE_SECTION 0x1000
+#define DCORE0_MME_CTRL_STM_BASE 0x60C1000ull
+#define DCORE0_MME_CTRL_STM_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_STM_SECTION 0x1000
+#define DCORE0_MME_CTRL_CTI_BASE 0x60C2000ull
+#define DCORE0_MME_CTRL_CTI_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_CTI_SECTION 0x1000
+#define DCORE0_MME_CTRL_ETF_BASE 0x60C3000ull
+#define DCORE0_MME_CTRL_ETF_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_ETF_SECTION 0x1000
+#define DCORE0_MME_CTRL_SPMU_BASE 0x60C4000ull
+#define DCORE0_MME_CTRL_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_SPMU_SECTION 0x1000
+#define DCORE0_MME_CTRL_CTI0_BASE 0x60C5000ull
+#define DCORE0_MME_CTRL_CTI0_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_CTI0_SECTION 0x1000
+#define DCORE0_MME_CTRL_CTI1_BASE 0x60C6000ull
+#define DCORE0_MME_CTRL_CTI1_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_CTI1_SECTION 0x1000
+#define DCORE0_MME_CTRL_BMON0_BASE 0x60C7000ull
+#define DCORE0_MME_CTRL_BMON0_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_BMON0_SECTION 0x1000
+#define DCORE0_MME_CTRL_BMON1_BASE 0x60C8000ull
+#define DCORE0_MME_CTRL_BMON1_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_BMON1_SECTION 0x1000
+#define DCORE0_MME_CTRL_BMON2_BASE 0x60C9000ull
+#define DCORE0_MME_CTRL_BMON2_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_BMON2_SECTION 0x1000
+#define DCORE0_MME_CTRL_BMON3_BASE 0x60CA000ull
+#define DCORE0_MME_CTRL_BMON3_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_BMON3_SECTION 0x1000
+#define DCORE0_MME_CTRL_ARC_RTT_BASE 0x60CB000ull
+#define DCORE0_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_ARC_RTT_SECTION 0x5000
+#define DCORE0_MME_SBTE0_ROM_TBL_BASE 0x60D0000ull
+#define DCORE0_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_ROM_TBL_SECTION 0x1000
+#define DCORE0_MME_SBTE0_STM_BASE 0x60D1000ull
+#define DCORE0_MME_SBTE0_STM_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_STM_SECTION 0x1000
+#define DCORE0_MME_SBTE0_CTI_BASE 0x60D2000ull
+#define DCORE0_MME_SBTE0_CTI_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_CTI_SECTION 0x1000
+#define DCORE0_MME_SBTE0_ETF_BASE 0x60D3000ull
+#define DCORE0_MME_SBTE0_ETF_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_ETF_SECTION 0x1000
+#define DCORE0_MME_SBTE0_SPMU_BASE 0x60D4000ull
+#define DCORE0_MME_SBTE0_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_SPMU_SECTION 0x1000
+#define DCORE0_MME_SBTE0_CTI0_BASE 0x60D5000ull
+#define DCORE0_MME_SBTE0_CTI0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_CTI0_SECTION 0x1000
+#define DCORE0_MME_SBTE0_CTI1_BASE 0x60D6000ull
+#define DCORE0_MME_SBTE0_CTI1_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_CTI1_SECTION 0x1000
+#define DCORE0_MME_SBTE0_BMON0_BASE 0x60D7000ull
+#define DCORE0_MME_SBTE0_BMON0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_BMON0_SECTION 0x1000
+#define DCORE0_MME_SBTE1_ROM_TBL_BASE 0x60D8000ull
+#define DCORE0_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_ROM_TBL_SECTION 0x1000
+#define DCORE0_MME_SBTE1_STM_BASE 0x60D9000ull
+#define DCORE0_MME_SBTE1_STM_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_STM_SECTION 0x1000
+#define DCORE0_MME_SBTE1_CTI_BASE 0x60DA000ull
+#define DCORE0_MME_SBTE1_CTI_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_CTI_SECTION 0x1000
+#define DCORE0_MME_SBTE1_ETF_BASE 0x60DB000ull
+#define DCORE0_MME_SBTE1_ETF_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_ETF_SECTION 0x1000
+#define DCORE0_MME_SBTE1_SPMU_BASE 0x60DC000ull
+#define DCORE0_MME_SBTE1_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_SPMU_SECTION 0x1000
+#define DCORE0_MME_SBTE1_CTI0_BASE 0x60DD000ull
+#define DCORE0_MME_SBTE1_CTI0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_CTI0_SECTION 0x1000
+#define DCORE0_MME_SBTE1_CTI1_BASE 0x60DE000ull
+#define DCORE0_MME_SBTE1_CTI1_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_CTI1_SECTION 0x1000
+#define DCORE0_MME_SBTE1_BMON0_BASE 0x60DF000ull
+#define DCORE0_MME_SBTE1_BMON0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_BMON0_SECTION 0x1000
+#define DCORE0_MME_SBTE2_ROM_TBL_BASE 0x60E0000ull
+#define DCORE0_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_ROM_TBL_SECTION 0x1000
+#define DCORE0_MME_SBTE2_STM_BASE 0x60E1000ull
+#define DCORE0_MME_SBTE2_STM_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_STM_SECTION 0x1000
+#define DCORE0_MME_SBTE2_CTI_BASE 0x60E2000ull
+#define DCORE0_MME_SBTE2_CTI_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_CTI_SECTION 0x1000
+#define DCORE0_MME_SBTE2_ETF_BASE 0x60E3000ull
+#define DCORE0_MME_SBTE2_ETF_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_ETF_SECTION 0x1000
+#define DCORE0_MME_SBTE2_SPMU_BASE 0x60E4000ull
+#define DCORE0_MME_SBTE2_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_SPMU_SECTION 0x1000
+#define DCORE0_MME_SBTE2_CTI0_BASE 0x60E5000ull
+#define DCORE0_MME_SBTE2_CTI0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_CTI0_SECTION 0x1000
+#define DCORE0_MME_SBTE2_CTI1_BASE 0x60E6000ull
+#define DCORE0_MME_SBTE2_CTI1_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_CTI1_SECTION 0x1000
+#define DCORE0_MME_SBTE2_BMON0_BASE 0x60E7000ull
+#define DCORE0_MME_SBTE2_BMON0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_BMON0_SECTION 0x1000
+#define DCORE0_MME_SBTE3_ROM_TBL_BASE 0x60E8000ull
+#define DCORE0_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_ROM_TBL_SECTION 0x1000
+#define DCORE0_MME_SBTE3_STM_BASE 0x60E9000ull
+#define DCORE0_MME_SBTE3_STM_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_STM_SECTION 0x1000
+#define DCORE0_MME_SBTE3_CTI_BASE 0x60EA000ull
+#define DCORE0_MME_SBTE3_CTI_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_CTI_SECTION 0x1000
+#define DCORE0_MME_SBTE3_ETF_BASE 0x60EB000ull
+#define DCORE0_MME_SBTE3_ETF_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_ETF_SECTION 0x1000
+#define DCORE0_MME_SBTE3_SPMU_BASE 0x60EC000ull
+#define DCORE0_MME_SBTE3_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_SPMU_SECTION 0x1000
+#define DCORE0_MME_SBTE3_CTI0_BASE 0x60ED000ull
+#define DCORE0_MME_SBTE3_CTI0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_CTI0_SECTION 0x1000
+#define DCORE0_MME_SBTE3_CTI1_BASE 0x60EE000ull
+#define DCORE0_MME_SBTE3_CTI1_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_CTI1_SECTION 0x1000
+#define DCORE0_MME_SBTE3_BMON0_BASE 0x60EF000ull
+#define DCORE0_MME_SBTE3_BMON0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_BMON0_SECTION 0x1000
+#define DCORE0_MME_SBTE4_ROM_TBL_BASE 0x60F0000ull
+#define DCORE0_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_ROM_TBL_SECTION 0x1000
+#define DCORE0_MME_SBTE4_STM_BASE 0x60F1000ull
+#define DCORE0_MME_SBTE4_STM_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_STM_SECTION 0x1000
+#define DCORE0_MME_SBTE4_CTI_BASE 0x60F2000ull
+#define DCORE0_MME_SBTE4_CTI_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_CTI_SECTION 0x1000
+#define DCORE0_MME_SBTE4_ETF_BASE 0x60F3000ull
+#define DCORE0_MME_SBTE4_ETF_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_ETF_SECTION 0x1000
+#define DCORE0_MME_SBTE4_SPMU_BASE 0x60F4000ull
+#define DCORE0_MME_SBTE4_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_SPMU_SECTION 0x1000
+#define DCORE0_MME_SBTE4_CTI0_BASE 0x60F5000ull
+#define DCORE0_MME_SBTE4_CTI0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_CTI0_SECTION 0x1000
+#define DCORE0_MME_SBTE4_CTI1_BASE 0x60F6000ull
+#define DCORE0_MME_SBTE4_CTI1_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_CTI1_SECTION 0x1000
+#define DCORE0_MME_SBTE4_BMON0_BASE 0x60F7000ull
+#define DCORE0_MME_SBTE4_BMON0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_BMON0_SECTION 0x9000
+#define DCORE0_MME_ACC_CS_ROM_TBL_BASE 0x6100000ull
+#define DCORE0_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_CS_ROM_TBL_SECTION 0x1000
+#define DCORE0_MME_ACC_STM_BASE 0x6101000ull
+#define DCORE0_MME_ACC_STM_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_STM_SECTION 0x1000
+#define DCORE0_MME_ACC_CTI_BASE 0x6102000ull
+#define DCORE0_MME_ACC_CTI_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_CTI_SECTION 0x1000
+#define DCORE0_MME_ACC_ETF_BASE 0x6103000ull
+#define DCORE0_MME_ACC_ETF_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_ETF_SECTION 0x1000
+#define DCORE0_MME_ACC_SPMU_BASE 0x6104000ull
+#define DCORE0_MME_ACC_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_SPMU_SECTION 0x1000
+#define DCORE0_MME_ACC_CTI0_BASE 0x6105000ull
+#define DCORE0_MME_ACC_CTI0_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_CTI0_SECTION 0x1000
+#define DCORE0_MME_ACC_CTI1_BASE 0x6106000ull
+#define DCORE0_MME_ACC_CTI1_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_CTI1_SECTION 0x1000
+#define DCORE0_MME_ACC_BMON0_BASE 0x6107000ull
+#define DCORE0_MME_ACC_BMON0_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_BMON0_SECTION 0x1000
+#define DCORE0_MME_ACC_BMON1_BASE 0x6108000ull
+#define DCORE0_MME_ACC_BMON1_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_BMON1_SECTION 0x8000
+#define DCORE0_SM_CS_DBG_ROM_TBL_BASE 0x6110000ull
+#define DCORE0_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_SM_CS_DBG_ROM_TBL_SECTION 0x1000
+#define DCORE0_SM_STM_BASE 0x6111000ull
+#define DCORE0_SM_STM_MAX_OFFSET 0x1000
+#define DCORE0_SM_STM_SECTION 0x1000
+#define DCORE0_SM_CTI_BASE 0x6112000ull
+#define DCORE0_SM_CTI_MAX_OFFSET 0x1000
+#define DCORE0_SM_CTI_SECTION 0x1000
+#define DCORE0_SM_ETF_BASE 0x6113000ull
+#define DCORE0_SM_ETF_MAX_OFFSET 0x1000
+#define DCORE0_SM_ETF_SECTION 0x1000
+#define DCORE0_SM_SPMU_BASE 0x6114000ull
+#define DCORE0_SM_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_SM_SPMU_SECTION 0x1000
+#define DCORE0_SM_BMON_CTI_BASE 0x6115000ull
+#define DCORE0_SM_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_SM_BMON_CTI_SECTION 0x1000
+#define DCORE0_SM_USER_CTI_BASE 0x6116000ull
+#define DCORE0_SM_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_SM_USER_CTI_SECTION 0x1000
+#define DCORE0_SM_BMON_BASE 0x6117000ull
+#define DCORE0_SM_BMON_MAX_OFFSET 0x1000
+#define DCORE0_SM_BMON_SECTION 0x1000
+#define DCORE0_SM_BMON1_BASE 0x6118000ull
+#define DCORE0_SM_BMON1_MAX_OFFSET 0x1000
+#define DCORE0_SM_BMON1_SECTION 0x18000
+#define DCORE0_XFT_FUNNEL_BASE 0x6130000ull
+#define DCORE0_XFT_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_XFT_FUNNEL_SECTION 0x8000
+#define DCORE0_TFT0_FUNNEL_BASE 0x6138000ull
+#define DCORE0_TFT0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TFT0_FUNNEL_SECTION 0x1000
+#define DCORE0_TFT1_FUNNEL_BASE 0x6139000ull
+#define DCORE0_TFT1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TFT1_FUNNEL_SECTION 0x1000
+#define DCORE0_TFT2_FUNNEL_BASE 0x613A000ull
+#define DCORE0_TFT2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TFT2_FUNNEL_SECTION 0x7000
+#define DCORE0_RTR0_FUNNEL_BASE 0x6141000ull
+#define DCORE0_RTR0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR0_FUNNEL_SECTION 0x8000
+#define DCORE0_RTR1_FUNNEL_BASE 0x6149000ull
+#define DCORE0_RTR1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR1_FUNNEL_SECTION 0x8000
+#define DCORE0_RTR2_FUNNEL_BASE 0x6151000ull
+#define DCORE0_RTR2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR2_FUNNEL_SECTION 0x8000
+#define DCORE0_RTR3_FUNNEL_BASE 0x6159000ull
+#define DCORE0_RTR3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR3_FUNNEL_SECTION 0x8000
+#define DCORE0_RTR4_FUNNEL_BASE 0x6161000ull
+#define DCORE0_RTR4_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR4_FUNNEL_SECTION 0x4000
+#define DCORE0_MIF0_FUNNEL_BASE 0x6165000ull
+#define DCORE0_MIF0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_MIF0_FUNNEL_SECTION 0x4000
+#define DCORE0_RTR5_FUNNEL_BASE 0x6169000ull
+#define DCORE0_RTR5_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR5_FUNNEL_SECTION 0x4000
+#define DCORE0_MIF1_FUNNEL_BASE 0x616D000ull
+#define DCORE0_MIF1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_MIF1_FUNNEL_SECTION 0x4000
+#define DCORE0_RTR6_FUNNEL_BASE 0x6171000ull
+#define DCORE0_RTR6_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR6_FUNNEL_SECTION 0x4000
+#define DCORE0_MIF2_FUNNEL_BASE 0x6175000ull
+#define DCORE0_MIF2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_MIF2_FUNNEL_SECTION 0x4000
+#define DCORE0_RTR7_FUNNEL_BASE 0x6179000ull
+#define DCORE0_RTR7_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR7_FUNNEL_SECTION 0x4000
+#define DCORE0_MIF3_FUNNEL_BASE 0x617D000ull
+#define DCORE0_MIF3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_MIF3_FUNNEL_SECTION 0x43000
+#define DCORE0_EDMA0_CS_ROM_TBL_BASE 0x61C0000ull
+#define DCORE0_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_CS_ROM_TBL_SECTION 0x1000
+#define DCORE0_EDMA0_CS_STM_BASE 0x61C1000ull
+#define DCORE0_EDMA0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_CS_STM_SECTION 0x1000
+#define DCORE0_EDMA0_CS_CTI_BASE 0x61C2000ull
+#define DCORE0_EDMA0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_CS_CTI_SECTION 0x1000
+#define DCORE0_EDMA0_CS_ETF_BASE 0x61C3000ull
+#define DCORE0_EDMA0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_CS_ETF_SECTION 0x1000
+#define DCORE0_EDMA0_CS_SPMU_BASE 0x61C4000ull
+#define DCORE0_EDMA0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_CS_SPMU_SECTION 0x1000
+#define DCORE0_EDMA0_BMON_CTI_BASE 0x61C5000ull
+#define DCORE0_EDMA0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_BMON_CTI_SECTION 0x1000
+#define DCORE0_EDMA0_USER_CTI_BASE 0x61C6000ull
+#define DCORE0_EDMA0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_USER_CTI_SECTION 0x1000
+#define DCORE0_EDMA0_BMON_0_BASE 0x61C7000ull
+#define DCORE0_EDMA0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_BMON_0_SECTION 0x1000
+#define DCORE0_EDMA0_BMON_1_BASE 0x61C8000ull
+#define DCORE0_EDMA0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_BMON_1_SECTION 0x1000
+#define DCORE0_EDMA0_QM_ARC_RTT_BASE 0x61C9000ull
+#define DCORE0_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_EDMA0_QM_ARC_RTT_SECTION 0x7000
+#define DCORE0_EDMA1_CS_ROM_TBL_BASE 0x61D0000ull
+#define DCORE0_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_CS_ROM_TBL_SECTION 0x1000
+#define DCORE0_EDMA1_CS_STM_BASE 0x61D1000ull
+#define DCORE0_EDMA1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_CS_STM_SECTION 0x1000
+#define DCORE0_EDMA1_CS_CTI_BASE 0x61D2000ull
+#define DCORE0_EDMA1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_CS_CTI_SECTION 0x1000
+#define DCORE0_EDMA1_CS_ETF_BASE 0x61D3000ull
+#define DCORE0_EDMA1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_CS_ETF_SECTION 0x1000
+#define DCORE0_EDMA1_CS_SPMU_BASE 0x61D4000ull
+#define DCORE0_EDMA1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_CS_SPMU_SECTION 0x1000
+#define DCORE0_EDMA1_BMON_CTI_BASE 0x61D5000ull
+#define DCORE0_EDMA1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_BMON_CTI_SECTION 0x1000
+#define DCORE0_EDMA1_USER_CTI_BASE 0x61D6000ull
+#define DCORE0_EDMA1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_USER_CTI_SECTION 0x1000
+#define DCORE0_EDMA1_BMON_0_BASE 0x61D7000ull
+#define DCORE0_EDMA1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_BMON_0_SECTION 0x1000
+#define DCORE0_EDMA1_BMON_1_BASE 0x61D8000ull
+#define DCORE0_EDMA1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_BMON_1_SECTION 0x1000
+#define DCORE0_EDMA1_QM_ARC_RTT_BASE 0x61D9000ull
+#define DCORE0_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_EDMA1_QM_ARC_RTT_SECTION 0x7000
+#define DCORE0_VDEC0_CS_ROM_TBL_BASE 0x61E0000ull
+#define DCORE0_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_CS_ROM_TBL_SECTION 0x1000
+#define DCORE0_VDEC0_CS_STM_BASE 0x61E1000ull
+#define DCORE0_VDEC0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_CS_STM_SECTION 0x1000
+#define DCORE0_VDEC0_CS_CTI_BASE 0x61E2000ull
+#define DCORE0_VDEC0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_CS_CTI_SECTION 0x1000
+#define DCORE0_VDEC0_CS_ETF_BASE 0x61E3000ull
+#define DCORE0_VDEC0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_CS_ETF_SECTION 0x1000
+#define DCORE0_VDEC0_CS_SPMU_BASE 0x61E4000ull
+#define DCORE0_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_CS_SPMU_SECTION 0x1000
+#define DCORE0_VDEC0_BMON_CTI_BASE 0x61E5000ull
+#define DCORE0_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_BMON_CTI_SECTION 0x1000
+#define DCORE0_VDEC0_USER_CTI_BASE 0x61E6000ull
+#define DCORE0_VDEC0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_USER_CTI_SECTION 0x1000
+#define DCORE0_VDEC0_BMON_0_BASE 0x61E7000ull
+#define DCORE0_VDEC0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_BMON_0_SECTION 0x1000
+#define DCORE0_VDEC0_BMON_1_BASE 0x61E8000ull
+#define DCORE0_VDEC0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_BMON_1_SECTION 0x1000
+#define DCORE0_VDEC0_BMON_2_BASE 0x61E9000ull
+#define DCORE0_VDEC0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_BMON_2_SECTION 0x7000
+#define DCORE0_VDEC1_CS_ROM_TBL_BASE 0x61F0000ull
+#define DCORE0_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_CS_ROM_TBL_SECTION 0x1000
+#define DCORE0_VDEC1_CS_STM_BASE 0x61F1000ull
+#define DCORE0_VDEC1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_CS_STM_SECTION 0x1000
+#define DCORE0_VDEC1_CS_CTI_BASE 0x61F2000ull
+#define DCORE0_VDEC1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_CS_CTI_SECTION 0x1000
+#define DCORE0_VDEC1_CS_ETF_BASE 0x61F3000ull
+#define DCORE0_VDEC1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_CS_ETF_SECTION 0x1000
+#define DCORE0_VDEC1_CS_SPMU_BASE 0x61F4000ull
+#define DCORE0_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_CS_SPMU_SECTION 0x1000
+#define DCORE0_VDEC1_BMON_CTI_BASE 0x61F5000ull
+#define DCORE0_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_BMON_CTI_SECTION 0x1000
+#define DCORE0_VDEC1_USER_CTI_BASE 0x61F6000ull
+#define DCORE0_VDEC1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_USER_CTI_SECTION 0x1000
+#define DCORE0_VDEC1_BMON_0_BASE 0x61F7000ull
+#define DCORE0_VDEC1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_BMON_0_SECTION 0x1000
+#define DCORE0_VDEC1_BMON_1_BASE 0x61F8000ull
+#define DCORE0_VDEC1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_BMON_1_SECTION 0x1000
+#define DCORE0_VDEC1_BMON_2_BASE 0x61F9000ull
+#define DCORE0_VDEC1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_BMON_2_SECTION 0x7000
+#define DCORE1_ROM_TABLE_L_BASE 0x6200000ull
+#define DCORE1_ROM_TABLE_L_MAX_OFFSET 0x1000
+#define DCORE1_ROM_TABLE_L_SECTION 0x80000
+#define DCORE1_HMMU0_CS_ROM_TBL_BASE 0x6280000ull
+#define DCORE1_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_CS_ROM_TBL_SECTION 0x1000
+#define DCORE1_HMMU0_CS_STM_BASE 0x6281000ull
+#define DCORE1_HMMU0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_CS_STM_SECTION 0x1000
+#define DCORE1_HMMU0_CS_CTI_BASE 0x6282000ull
+#define DCORE1_HMMU0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_CS_CTI_SECTION 0x1000
+#define DCORE1_HMMU0_CS_ETF_BASE 0x6283000ull
+#define DCORE1_HMMU0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_CS_ETF_SECTION 0x1000
+#define DCORE1_HMMU0_CS_SPMU_BASE 0x6284000ull
+#define DCORE1_HMMU0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_CS_SPMU_SECTION 0x1000
+#define DCORE1_HMMU0_BMON_CTI_BASE 0x6285000ull
+#define DCORE1_HMMU0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_BMON_CTI_SECTION 0x1000
+#define DCORE1_HMMU0_USER_CTI_BASE 0x6286000ull
+#define DCORE1_HMMU0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_USER_CTI_SECTION 0x1000
+#define DCORE1_HMMU0_BMON_0_BASE 0x6287000ull
+#define DCORE1_HMMU0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_BMON_0_SECTION 0x1000
+#define DCORE1_HMMU0_BMON_1_BASE 0x6288000ull
+#define DCORE1_HMMU0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_BMON_1_SECTION 0x1000
+#define DCORE1_HMMU0_BMON_3_BASE 0x6289000ull
+#define DCORE1_HMMU0_BMON_3_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_BMON_3_SECTION 0x1000
+#define DCORE1_HMMU0_BMON_2_BASE 0x628A000ull
+#define DCORE1_HMMU0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_BMON_2_SECTION 0x1000
+#define DCORE1_HMMU0_BMON_4_BASE 0x628B000ull
+#define DCORE1_HMMU0_BMON_4_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_BMON_4_SECTION 0x5000
+#define DCORE1_HMMU1_CS_ROM_TBL_BASE 0x6290000ull
+#define DCORE1_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_CS_ROM_TBL_SECTION 0x1000
+#define DCORE1_HMMU1_CS_STM_BASE 0x6291000ull
+#define DCORE1_HMMU1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_CS_STM_SECTION 0x1000
+#define DCORE1_HMMU1_CS_CTI_BASE 0x6292000ull
+#define DCORE1_HMMU1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_CS_CTI_SECTION 0x1000
+#define DCORE1_HMMU1_CS_ETF_BASE 0x6293000ull
+#define DCORE1_HMMU1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_CS_ETF_SECTION 0x1000
+#define DCORE1_HMMU1_CS_SPMU_BASE 0x6294000ull
+#define DCORE1_HMMU1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_CS_SPMU_SECTION 0x1000
+#define DCORE1_HMMU1_BMON_CTI_BASE 0x6295000ull
+#define DCORE1_HMMU1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_BMON_CTI_SECTION 0x1000
+#define DCORE1_HMMU1_USER_CTI_BASE 0x6296000ull
+#define DCORE1_HMMU1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_USER_CTI_SECTION 0x1000
+#define DCORE1_HMMU1_BMON_0_BASE 0x6297000ull
+#define DCORE1_HMMU1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_BMON_0_SECTION 0x1000
+#define DCORE1_HMMU1_BMON_1_BASE 0x6298000ull
+#define DCORE1_HMMU1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_BMON_1_SECTION 0x1000
+#define DCORE1_HMMU1_BMON_3_BASE 0x6299000ull
+#define DCORE1_HMMU1_BMON_3_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_BMON_3_SECTION 0x1000
+#define DCORE1_HMMU1_BMON_2_BASE 0x629A000ull
+#define DCORE1_HMMU1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_BMON_2_SECTION 0x1000
+#define DCORE1_HMMU1_BMON_4_BASE 0x629B000ull
+#define DCORE1_HMMU1_BMON_4_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_BMON_4_SECTION 0x5000
+#define DCORE1_HMMU2_CS_ROM_TBL_BASE 0x62A0000ull
+#define DCORE1_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_CS_ROM_TBL_SECTION 0x1000
+#define DCORE1_HMMU2_CS_STM_BASE 0x62A1000ull
+#define DCORE1_HMMU2_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_CS_STM_SECTION 0x1000
+#define DCORE1_HMMU2_CS_CTI_BASE 0x62A2000ull
+#define DCORE1_HMMU2_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_CS_CTI_SECTION 0x1000
+#define DCORE1_HMMU2_CS_ETF_BASE 0x62A3000ull
+#define DCORE1_HMMU2_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_CS_ETF_SECTION 0x1000
+#define DCORE1_HMMU2_CS_SPMU_BASE 0x62A4000ull
+#define DCORE1_HMMU2_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_CS_SPMU_SECTION 0x1000
+#define DCORE1_HMMU2_BMON_CTI_BASE 0x62A5000ull
+#define DCORE1_HMMU2_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_BMON_CTI_SECTION 0x1000
+#define DCORE1_HMMU2_USER_CTI_BASE 0x62A6000ull
+#define DCORE1_HMMU2_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_USER_CTI_SECTION 0x1000
+#define DCORE1_HMMU2_BMON_0_BASE 0x62A7000ull
+#define DCORE1_HMMU2_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_BMON_0_SECTION 0x1000
+#define DCORE1_HMMU2_BMON_1_BASE 0x62A8000ull
+#define DCORE1_HMMU2_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_BMON_1_SECTION 0x1000
+#define DCORE1_HMMU2_BMON_3_BASE 0x62A9000ull
+#define DCORE1_HMMU2_BMON_3_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_BMON_3_SECTION 0x1000
+#define DCORE1_HMMU2_BMON_2_BASE 0x62AA000ull
+#define DCORE1_HMMU2_BMON_2_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_BMON_2_SECTION 0x1000
+#define DCORE1_HMMU2_BMON_4_BASE 0x62AB000ull
+#define DCORE1_HMMU2_BMON_4_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_BMON_4_SECTION 0x5000
+#define DCORE1_HMMU3_CS_ROM_TBL_BASE 0x62B0000ull
+#define DCORE1_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_CS_ROM_TBL_SECTION 0x1000
+#define DCORE1_HMMU3_CS_STM_BASE 0x62B1000ull
+#define DCORE1_HMMU3_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_CS_STM_SECTION 0x1000
+#define DCORE1_HMMU3_CS_CTI_BASE 0x62B2000ull
+#define DCORE1_HMMU3_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_CS_CTI_SECTION 0x1000
+#define DCORE1_HMMU3_CS_ETF_BASE 0x62B3000ull
+#define DCORE1_HMMU3_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_CS_ETF_SECTION 0x1000
+#define DCORE1_HMMU3_CS_SPMU_BASE 0x62B4000ull
+#define DCORE1_HMMU3_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_CS_SPMU_SECTION 0x1000
+#define DCORE1_HMMU3_BMON_CTI_BASE 0x62B5000ull
+#define DCORE1_HMMU3_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_BMON_CTI_SECTION 0x1000
+#define DCORE1_HMMU3_USER_CTI_BASE 0x62B6000ull
+#define DCORE1_HMMU3_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_USER_CTI_SECTION 0x1000
+#define DCORE1_HMMU3_BMON_0_BASE 0x62B7000ull
+#define DCORE1_HMMU3_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_BMON_0_SECTION 0x1000
+#define DCORE1_HMMU3_BMON_1_BASE 0x62B8000ull
+#define DCORE1_HMMU3_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_BMON_1_SECTION 0x1000
+#define DCORE1_HMMU3_BMON_3_BASE 0x62B9000ull
+#define DCORE1_HMMU3_BMON_3_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_BMON_3_SECTION 0x1000
+#define DCORE1_HMMU3_BMON_2_BASE 0x62BA000ull
+#define DCORE1_HMMU3_BMON_2_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_BMON_2_SECTION 0x1000
+#define DCORE1_HMMU3_BMON_4_BASE 0x62BB000ull
+#define DCORE1_HMMU3_BMON_4_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_BMON_4_SECTION 0x5000
+#define DCORE1_MME_CTRL_ROM_TABLE_BASE 0x62C0000ull
+#define DCORE1_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_ROM_TABLE_SECTION 0x1000
+#define DCORE1_MME_CTRL_STM_BASE 0x62C1000ull
+#define DCORE1_MME_CTRL_STM_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_STM_SECTION 0x1000
+#define DCORE1_MME_CTRL_CTI_BASE 0x62C2000ull
+#define DCORE1_MME_CTRL_CTI_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_CTI_SECTION 0x1000
+#define DCORE1_MME_CTRL_ETF_BASE 0x62C3000ull
+#define DCORE1_MME_CTRL_ETF_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_ETF_SECTION 0x1000
+#define DCORE1_MME_CTRL_SPMU_BASE 0x62C4000ull
+#define DCORE1_MME_CTRL_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_SPMU_SECTION 0x1000
+#define DCORE1_MME_CTRL_CTI0_BASE 0x62C5000ull
+#define DCORE1_MME_CTRL_CTI0_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_CTI0_SECTION 0x1000
+#define DCORE1_MME_CTRL_CTI1_BASE 0x62C6000ull
+#define DCORE1_MME_CTRL_CTI1_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_CTI1_SECTION 0x1000
+#define DCORE1_MME_CTRL_BMON0_BASE 0x62C7000ull
+#define DCORE1_MME_CTRL_BMON0_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_BMON0_SECTION 0x1000
+#define DCORE1_MME_CTRL_BMON1_BASE 0x62C8000ull
+#define DCORE1_MME_CTRL_BMON1_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_BMON1_SECTION 0x1000
+#define DCORE1_MME_CTRL_BMON2_BASE 0x62C9000ull
+#define DCORE1_MME_CTRL_BMON2_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_BMON2_SECTION 0x1000
+#define DCORE1_MME_CTRL_BMON3_BASE 0x62CA000ull
+#define DCORE1_MME_CTRL_BMON3_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_BMON3_SECTION 0x1000
+#define DCORE1_MME_CTRL_ARC_RTT_BASE 0x62CB000ull
+#define DCORE1_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_ARC_RTT_SECTION 0x5000
+#define DCORE1_MME_SBTE0_ROM_TBL_BASE 0x62D0000ull
+#define DCORE1_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_ROM_TBL_SECTION 0x1000
+#define DCORE1_MME_SBTE0_STM_BASE 0x62D1000ull
+#define DCORE1_MME_SBTE0_STM_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_STM_SECTION 0x1000
+#define DCORE1_MME_SBTE0_CTI_BASE 0x62D2000ull
+#define DCORE1_MME_SBTE0_CTI_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_CTI_SECTION 0x1000
+#define DCORE1_MME_SBTE0_ETF_BASE 0x62D3000ull
+#define DCORE1_MME_SBTE0_ETF_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_ETF_SECTION 0x1000
+#define DCORE1_MME_SBTE0_SPMU_BASE 0x62D4000ull
+#define DCORE1_MME_SBTE0_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_SPMU_SECTION 0x1000
+#define DCORE1_MME_SBTE0_CTI0_BASE 0x62D5000ull
+#define DCORE1_MME_SBTE0_CTI0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_CTI0_SECTION 0x1000
+#define DCORE1_MME_SBTE0_CTI1_BASE 0x62D6000ull
+#define DCORE1_MME_SBTE0_CTI1_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_CTI1_SECTION 0x1000
+#define DCORE1_MME_SBTE0_BMON0_BASE 0x62D7000ull
+#define DCORE1_MME_SBTE0_BMON0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_BMON0_SECTION 0x1000
+#define DCORE1_MME_SBTE1_ROM_TBL_BASE 0x62D8000ull
+#define DCORE1_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_ROM_TBL_SECTION 0x1000
+#define DCORE1_MME_SBTE1_STM_BASE 0x62D9000ull
+#define DCORE1_MME_SBTE1_STM_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_STM_SECTION 0x1000
+#define DCORE1_MME_SBTE1_CTI_BASE 0x62DA000ull
+#define DCORE1_MME_SBTE1_CTI_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_CTI_SECTION 0x1000
+#define DCORE1_MME_SBTE1_ETF_BASE 0x62DB000ull
+#define DCORE1_MME_SBTE1_ETF_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_ETF_SECTION 0x1000
+#define DCORE1_MME_SBTE1_SPMU_BASE 0x62DC000ull
+#define DCORE1_MME_SBTE1_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_SPMU_SECTION 0x1000
+#define DCORE1_MME_SBTE1_CTI0_BASE 0x62DD000ull
+#define DCORE1_MME_SBTE1_CTI0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_CTI0_SECTION 0x1000
+#define DCORE1_MME_SBTE1_CTI1_BASE 0x62DE000ull
+#define DCORE1_MME_SBTE1_CTI1_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_CTI1_SECTION 0x1000
+#define DCORE1_MME_SBTE1_BMON0_BASE 0x62DF000ull
+#define DCORE1_MME_SBTE1_BMON0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_BMON0_SECTION 0x1000
+#define DCORE1_MME_SBTE2_ROM_TBL_BASE 0x62E0000ull
+#define DCORE1_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_ROM_TBL_SECTION 0x1000
+#define DCORE1_MME_SBTE2_STM_BASE 0x62E1000ull
+#define DCORE1_MME_SBTE2_STM_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_STM_SECTION 0x1000
+#define DCORE1_MME_SBTE2_CTI_BASE 0x62E2000ull
+#define DCORE1_MME_SBTE2_CTI_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_CTI_SECTION 0x1000
+#define DCORE1_MME_SBTE2_ETF_BASE 0x62E3000ull
+#define DCORE1_MME_SBTE2_ETF_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_ETF_SECTION 0x1000
+#define DCORE1_MME_SBTE2_SPMU_BASE 0x62E4000ull
+#define DCORE1_MME_SBTE2_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_SPMU_SECTION 0x1000
+#define DCORE1_MME_SBTE2_CTI0_BASE 0x62E5000ull
+#define DCORE1_MME_SBTE2_CTI0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_CTI0_SECTION 0x1000
+#define DCORE1_MME_SBTE2_CTI1_BASE 0x62E6000ull
+#define DCORE1_MME_SBTE2_CTI1_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_CTI1_SECTION 0x1000
+#define DCORE1_MME_SBTE2_BMON0_BASE 0x62E7000ull
+#define DCORE1_MME_SBTE2_BMON0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_BMON0_SECTION 0x1000
+#define DCORE1_MME_SBTE3_ROM_TBL_BASE 0x62E8000ull
+#define DCORE1_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_ROM_TBL_SECTION 0x1000
+#define DCORE1_MME_SBTE3_STM_BASE 0x62E9000ull
+#define DCORE1_MME_SBTE3_STM_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_STM_SECTION 0x1000
+#define DCORE1_MME_SBTE3_CTI_BASE 0x62EA000ull
+#define DCORE1_MME_SBTE3_CTI_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_CTI_SECTION 0x1000
+#define DCORE1_MME_SBTE3_ETF_BASE 0x62EB000ull
+#define DCORE1_MME_SBTE3_ETF_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_ETF_SECTION 0x1000
+#define DCORE1_MME_SBTE3_SPMU_BASE 0x62EC000ull
+#define DCORE1_MME_SBTE3_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_SPMU_SECTION 0x1000
+#define DCORE1_MME_SBTE3_CTI0_BASE 0x62ED000ull
+#define DCORE1_MME_SBTE3_CTI0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_CTI0_SECTION 0x1000
+#define DCORE1_MME_SBTE3_CTI1_BASE 0x62EE000ull
+#define DCORE1_MME_SBTE3_CTI1_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_CTI1_SECTION 0x1000
+#define DCORE1_MME_SBTE3_BMON0_BASE 0x62EF000ull
+#define DCORE1_MME_SBTE3_BMON0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_BMON0_SECTION 0x1000
+#define DCORE1_MME_SBTE4_ROM_TBL_BASE 0x62F0000ull
+#define DCORE1_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_ROM_TBL_SECTION 0x1000
+#define DCORE1_MME_SBTE4_STM_BASE 0x62F1000ull
+#define DCORE1_MME_SBTE4_STM_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_STM_SECTION 0x1000
+#define DCORE1_MME_SBTE4_CTI_BASE 0x62F2000ull
+#define DCORE1_MME_SBTE4_CTI_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_CTI_SECTION 0x1000
+#define DCORE1_MME_SBTE4_ETF_BASE 0x62F3000ull
+#define DCORE1_MME_SBTE4_ETF_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_ETF_SECTION 0x1000
+#define DCORE1_MME_SBTE4_SPMU_BASE 0x62F4000ull
+#define DCORE1_MME_SBTE4_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_SPMU_SECTION 0x1000
+#define DCORE1_MME_SBTE4_CTI0_BASE 0x62F5000ull
+#define DCORE1_MME_SBTE4_CTI0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_CTI0_SECTION 0x1000
+#define DCORE1_MME_SBTE4_CTI1_BASE 0x62F6000ull
+#define DCORE1_MME_SBTE4_CTI1_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_CTI1_SECTION 0x1000
+#define DCORE1_MME_SBTE4_BMON0_BASE 0x62F7000ull
+#define DCORE1_MME_SBTE4_BMON0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_BMON0_SECTION 0x9000
+#define DCORE1_MME_ACC_CS_ROM_TBL_BASE 0x6300000ull
+#define DCORE1_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_CS_ROM_TBL_SECTION 0x1000
+#define DCORE1_MME_ACC_STM_BASE 0x6301000ull
+#define DCORE1_MME_ACC_STM_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_STM_SECTION 0x1000
+#define DCORE1_MME_ACC_CTI_BASE 0x6302000ull
+#define DCORE1_MME_ACC_CTI_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_CTI_SECTION 0x1000
+#define DCORE1_MME_ACC_ETF_BASE 0x6303000ull
+#define DCORE1_MME_ACC_ETF_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_ETF_SECTION 0x1000
+#define DCORE1_MME_ACC_SPMU_BASE 0x6304000ull
+#define DCORE1_MME_ACC_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_SPMU_SECTION 0x1000
+#define DCORE1_MME_ACC_CTI0_BASE 0x6305000ull
+#define DCORE1_MME_ACC_CTI0_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_CTI0_SECTION 0x1000
+#define DCORE1_MME_ACC_CTI1_BASE 0x6306000ull
+#define DCORE1_MME_ACC_CTI1_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_CTI1_SECTION 0x1000
+#define DCORE1_MME_ACC_BMON0_BASE 0x6307000ull
+#define DCORE1_MME_ACC_BMON0_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_BMON0_SECTION 0x1000
+#define DCORE1_MME_ACC_BMON1_BASE 0x6308000ull
+#define DCORE1_MME_ACC_BMON1_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_BMON1_SECTION 0x8000
+#define DCORE1_SM_CS_DBG_ROM_TBL_BASE 0x6310000ull
+#define DCORE1_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_SM_CS_DBG_ROM_TBL_SECTION 0x1000
+#define DCORE1_SM_STM_BASE 0x6311000ull
+#define DCORE1_SM_STM_MAX_OFFSET 0x1000
+#define DCORE1_SM_STM_SECTION 0x1000
+#define DCORE1_SM_CTI_BASE 0x6312000ull
+#define DCORE1_SM_CTI_MAX_OFFSET 0x1000
+#define DCORE1_SM_CTI_SECTION 0x1000
+#define DCORE1_SM_ETF_BASE 0x6313000ull
+#define DCORE1_SM_ETF_MAX_OFFSET 0x1000
+#define DCORE1_SM_ETF_SECTION 0x1000
+#define DCORE1_SM_SPMU_BASE 0x6314000ull
+#define DCORE1_SM_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_SM_SPMU_SECTION 0x1000
+#define DCORE1_SM_BMON_CTI_BASE 0x6315000ull
+#define DCORE1_SM_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_SM_BMON_CTI_SECTION 0x1000
+#define DCORE1_SM_USER_CTI_BASE 0x6316000ull
+#define DCORE1_SM_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_SM_USER_CTI_SECTION 0x1000
+#define DCORE1_SM_BMON_BASE 0x6317000ull
+#define DCORE1_SM_BMON_MAX_OFFSET 0x1000
+#define DCORE1_SM_BMON_SECTION 0x1000
+#define DCORE1_SM_BMON1_BASE 0x6318000ull
+#define DCORE1_SM_BMON1_MAX_OFFSET 0x1000
+#define DCORE1_SM_BMON1_SECTION 0x18000
+#define DCORE1_XFT_FUNNEL_BASE 0x6330000ull
+#define DCORE1_XFT_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_XFT_FUNNEL_SECTION 0x8000
+#define DCORE1_TFT0_FUNNEL_BASE 0x6338000ull
+#define DCORE1_TFT0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TFT0_FUNNEL_SECTION 0x1000
+#define DCORE1_TFT1_FUNNEL_BASE 0x6339000ull
+#define DCORE1_TFT1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TFT1_FUNNEL_SECTION 0x1000
+#define DCORE1_TFT2_FUNNEL_BASE 0x633A000ull
+#define DCORE1_TFT2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TFT2_FUNNEL_SECTION 0x7000
+#define DCORE1_RTR0_FUNNEL_BASE 0x6341000ull
+#define DCORE1_RTR0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR0_FUNNEL_SECTION 0x4000
+#define DCORE1_MIF0_FUNNEL_BASE 0x6345000ull
+#define DCORE1_MIF0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_MIF0_FUNNEL_SECTION 0x4000
+#define DCORE1_RTR1_FUNNEL_BASE 0x6349000ull
+#define DCORE1_RTR1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR1_FUNNEL_SECTION 0x4000
+#define DCORE1_MIF1_FUNNEL_BASE 0x634D000ull
+#define DCORE1_MIF1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_MIF1_FUNNEL_SECTION 0x4000
+#define DCORE1_RTR2_FUNNEL_BASE 0x6351000ull
+#define DCORE1_RTR2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR2_FUNNEL_SECTION 0x4000
+#define DCORE1_MIF2_FUNNEL_BASE 0x6355000ull
+#define DCORE1_MIF2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_MIF2_FUNNEL_SECTION 0x4000
+#define DCORE1_RTR3_FUNNEL_BASE 0x6359000ull
+#define DCORE1_RTR3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR3_FUNNEL_SECTION 0x4000
+#define DCORE1_MIF3_FUNNEL_BASE 0x635D000ull
+#define DCORE1_MIF3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_MIF3_FUNNEL_SECTION 0x4000
+#define DCORE1_RTR4_FUNNEL_BASE 0x6361000ull
+#define DCORE1_RTR4_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR4_FUNNEL_SECTION 0x8000
+#define DCORE1_RTR5_FUNNEL_BASE 0x6369000ull
+#define DCORE1_RTR5_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR5_FUNNEL_SECTION 0x8000
+#define DCORE1_RTR6_FUNNEL_BASE 0x6371000ull
+#define DCORE1_RTR6_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR6_FUNNEL_SECTION 0x8000
+#define DCORE1_RTR7_FUNNEL_BASE 0x6379000ull
+#define DCORE1_RTR7_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR7_FUNNEL_SECTION 0x47000
+#define DCORE1_EDMA0_CS_ROM_TBL_BASE 0x63C0000ull
+#define DCORE1_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_CS_ROM_TBL_SECTION 0x1000
+#define DCORE1_EDMA0_CS_STM_BASE 0x63C1000ull
+#define DCORE1_EDMA0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_CS_STM_SECTION 0x1000
+#define DCORE1_EDMA0_CS_CTI_BASE 0x63C2000ull
+#define DCORE1_EDMA0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_CS_CTI_SECTION 0x1000
+#define DCORE1_EDMA0_CS_ETF_BASE 0x63C3000ull
+#define DCORE1_EDMA0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_CS_ETF_SECTION 0x1000
+#define DCORE1_EDMA0_CS_SPMU_BASE 0x63C4000ull
+#define DCORE1_EDMA0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_CS_SPMU_SECTION 0x1000
+#define DCORE1_EDMA0_BMON_CTI_BASE 0x63C5000ull
+#define DCORE1_EDMA0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_BMON_CTI_SECTION 0x1000
+#define DCORE1_EDMA0_USER_CTI_BASE 0x63C6000ull
+#define DCORE1_EDMA0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_USER_CTI_SECTION 0x1000
+#define DCORE1_EDMA0_BMON_0_BASE 0x63C7000ull
+#define DCORE1_EDMA0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_BMON_0_SECTION 0x1000
+#define DCORE1_EDMA0_BMON_1_BASE 0x63C8000ull
+#define DCORE1_EDMA0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_BMON_1_SECTION 0x1000
+#define DCORE1_EDMA0_QM_ARC_RTT_BASE 0x63C9000ull
+#define DCORE1_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_EDMA0_QM_ARC_RTT_SECTION 0x7000
+#define DCORE1_EDMA1_CS_ROM_TBL_BASE 0x63D0000ull
+#define DCORE1_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_CS_ROM_TBL_SECTION 0x1000
+#define DCORE1_EDMA1_CS_STM_BASE 0x63D1000ull
+#define DCORE1_EDMA1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_CS_STM_SECTION 0x1000
+#define DCORE1_EDMA1_CS_CTI_BASE 0x63D2000ull
+#define DCORE1_EDMA1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_CS_CTI_SECTION 0x1000
+#define DCORE1_EDMA1_CS_ETF_BASE 0x63D3000ull
+#define DCORE1_EDMA1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_CS_ETF_SECTION 0x1000
+#define DCORE1_EDMA1_CS_SPMU_BASE 0x63D4000ull
+#define DCORE1_EDMA1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_CS_SPMU_SECTION 0x1000
+#define DCORE1_EDMA1_BMON_CTI_BASE 0x63D5000ull
+#define DCORE1_EDMA1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_BMON_CTI_SECTION 0x1000
+#define DCORE1_EDMA1_USER_CTI_BASE 0x63D6000ull
+#define DCORE1_EDMA1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_USER_CTI_SECTION 0x1000
+#define DCORE1_EDMA1_BMON_0_BASE 0x63D7000ull
+#define DCORE1_EDMA1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_BMON_0_SECTION 0x1000
+#define DCORE1_EDMA1_BMON_1_BASE 0x63D8000ull
+#define DCORE1_EDMA1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_BMON_1_SECTION 0x1000
+#define DCORE1_EDMA1_QM_ARC_RTT_BASE 0x63D9000ull
+#define DCORE1_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_EDMA1_QM_ARC_RTT_SECTION 0x7000
+#define DCORE1_VDEC0_CS_ROM_TBL_BASE 0x63E0000ull
+#define DCORE1_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_CS_ROM_TBL_SECTION 0x1000
+#define DCORE1_VDEC0_CS_STM_BASE 0x63E1000ull
+#define DCORE1_VDEC0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_CS_STM_SECTION 0x1000
+#define DCORE1_VDEC0_CS_CTI_BASE 0x63E2000ull
+#define DCORE1_VDEC0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_CS_CTI_SECTION 0x1000
+#define DCORE1_VDEC0_CS_ETF_BASE 0x63E3000ull
+#define DCORE1_VDEC0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_CS_ETF_SECTION 0x1000
+#define DCORE1_VDEC0_CS_SPMU_BASE 0x63E4000ull
+#define DCORE1_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_CS_SPMU_SECTION 0x1000
+#define DCORE1_VDEC0_BMON_CTI_BASE 0x63E5000ull
+#define DCORE1_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_BMON_CTI_SECTION 0x1000
+#define DCORE1_VDEC0_USER_CTI_BASE 0x63E6000ull
+#define DCORE1_VDEC0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_USER_CTI_SECTION 0x1000
+#define DCORE1_VDEC0_BMON_0_BASE 0x63E7000ull
+#define DCORE1_VDEC0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_BMON_0_SECTION 0x1000
+#define DCORE1_VDEC0_BMON_1_BASE 0x63E8000ull
+#define DCORE1_VDEC0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_BMON_1_SECTION 0x1000
+#define DCORE1_VDEC0_BMON_2_BASE 0x63E9000ull
+#define DCORE1_VDEC0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_BMON_2_SECTION 0x7000
+#define DCORE1_VDEC1_CS_ROM_TBL_BASE 0x63F0000ull
+#define DCORE1_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_CS_ROM_TBL_SECTION 0x1000
+#define DCORE1_VDEC1_CS_STM_BASE 0x63F1000ull
+#define DCORE1_VDEC1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_CS_STM_SECTION 0x1000
+#define DCORE1_VDEC1_CS_CTI_BASE 0x63F2000ull
+#define DCORE1_VDEC1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_CS_CTI_SECTION 0x1000
+#define DCORE1_VDEC1_CS_ETF_BASE 0x63F3000ull
+#define DCORE1_VDEC1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_CS_ETF_SECTION 0x1000
+#define DCORE1_VDEC1_CS_SPMU_BASE 0x63F4000ull
+#define DCORE1_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_CS_SPMU_SECTION 0x1000
+#define DCORE1_VDEC1_BMON_CTI_BASE 0x63F5000ull
+#define DCORE1_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_BMON_CTI_SECTION 0x1000
+#define DCORE1_VDEC1_USER_CTI_BASE 0x63F6000ull
+#define DCORE1_VDEC1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_USER_CTI_SECTION 0x1000
+#define DCORE1_VDEC1_BMON_0_BASE 0x63F7000ull
+#define DCORE1_VDEC1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_BMON_0_SECTION 0x1000
+#define DCORE1_VDEC1_BMON_1_BASE 0x63F8000ull
+#define DCORE1_VDEC1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_BMON_1_SECTION 0x1000
+#define DCORE1_VDEC1_BMON_2_BASE 0x63F9000ull
+#define DCORE1_VDEC1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_BMON_2_SECTION 0x7000
+#define DCORE2_ROM_TABLE_L_BASE 0x6400000ull
+#define DCORE2_ROM_TABLE_L_MAX_OFFSET 0x1000
+#define DCORE2_ROM_TABLE_L_SECTION 0x80000
+#define DCORE2_HMMU0_CS_ROM_TBL_BASE 0x6480000ull
+#define DCORE2_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_CS_ROM_TBL_SECTION 0x1000
+#define DCORE2_HMMU0_CS_STM_BASE 0x6481000ull
+#define DCORE2_HMMU0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_CS_STM_SECTION 0x1000
+#define DCORE2_HMMU0_CS_CTI_BASE 0x6482000ull
+#define DCORE2_HMMU0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_CS_CTI_SECTION 0x1000
+#define DCORE2_HMMU0_CS_ETF_BASE 0x6483000ull
+#define DCORE2_HMMU0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_CS_ETF_SECTION 0x1000
+#define DCORE2_HMMU0_CS_SPMU_BASE 0x6484000ull
+#define DCORE2_HMMU0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_CS_SPMU_SECTION 0x1000
+#define DCORE2_HMMU0_BMON_CTI_BASE 0x6485000ull
+#define DCORE2_HMMU0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_BMON_CTI_SECTION 0x1000
+#define DCORE2_HMMU0_USER_CTI_BASE 0x6486000ull
+#define DCORE2_HMMU0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_USER_CTI_SECTION 0x1000
+#define DCORE2_HMMU0_BMON_0_BASE 0x6487000ull
+#define DCORE2_HMMU0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_BMON_0_SECTION 0x1000
+#define DCORE2_HMMU0_BMON_1_BASE 0x6488000ull
+#define DCORE2_HMMU0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_BMON_1_SECTION 0x1000
+#define DCORE2_HMMU0_BMON_3_BASE 0x6489000ull
+#define DCORE2_HMMU0_BMON_3_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_BMON_3_SECTION 0x1000
+#define DCORE2_HMMU0_BMON_2_BASE 0x648A000ull
+#define DCORE2_HMMU0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_BMON_2_SECTION 0x1000
+#define DCORE2_HMMU0_BMON_4_BASE 0x648B000ull
+#define DCORE2_HMMU0_BMON_4_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_BMON_4_SECTION 0x5000
+#define DCORE2_HMMU1_CS_ROM_TBL_BASE 0x6490000ull
+#define DCORE2_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_CS_ROM_TBL_SECTION 0x1000
+#define DCORE2_HMMU1_CS_STM_BASE 0x6491000ull
+#define DCORE2_HMMU1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_CS_STM_SECTION 0x1000
+#define DCORE2_HMMU1_CS_CTI_BASE 0x6492000ull
+#define DCORE2_HMMU1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_CS_CTI_SECTION 0x1000
+#define DCORE2_HMMU1_CS_ETF_BASE 0x6493000ull
+#define DCORE2_HMMU1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_CS_ETF_SECTION 0x1000
+#define DCORE2_HMMU1_CS_SPMU_BASE 0x6494000ull
+#define DCORE2_HMMU1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_CS_SPMU_SECTION 0x1000
+#define DCORE2_HMMU1_BMON_CTI_BASE 0x6495000ull
+#define DCORE2_HMMU1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_BMON_CTI_SECTION 0x1000
+#define DCORE2_HMMU1_USER_CTI_BASE 0x6496000ull
+#define DCORE2_HMMU1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_USER_CTI_SECTION 0x1000
+#define DCORE2_HMMU1_BMON_0_BASE 0x6497000ull
+#define DCORE2_HMMU1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_BMON_0_SECTION 0x1000
+#define DCORE2_HMMU1_BMON_1_BASE 0x6498000ull
+#define DCORE2_HMMU1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_BMON_1_SECTION 0x1000
+#define DCORE2_HMMU1_BMON_3_BASE 0x6499000ull
+#define DCORE2_HMMU1_BMON_3_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_BMON_3_SECTION 0x1000
+#define DCORE2_HMMU1_BMON_2_BASE 0x649A000ull
+#define DCORE2_HMMU1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_BMON_2_SECTION 0x1000
+#define DCORE2_HMMU1_BMON_4_BASE 0x649B000ull
+#define DCORE2_HMMU1_BMON_4_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_BMON_4_SECTION 0x5000
+#define DCORE2_HMMU2_CS_ROM_TBL_BASE 0x64A0000ull
+#define DCORE2_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_CS_ROM_TBL_SECTION 0x1000
+#define DCORE2_HMMU2_CS_STM_BASE 0x64A1000ull
+#define DCORE2_HMMU2_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_CS_STM_SECTION 0x1000
+#define DCORE2_HMMU2_CS_CTI_BASE 0x64A2000ull
+#define DCORE2_HMMU2_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_CS_CTI_SECTION 0x1000
+#define DCORE2_HMMU2_CS_ETF_BASE 0x64A3000ull
+#define DCORE2_HMMU2_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_CS_ETF_SECTION 0x1000
+#define DCORE2_HMMU2_CS_SPMU_BASE 0x64A4000ull
+#define DCORE2_HMMU2_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_CS_SPMU_SECTION 0x1000
+#define DCORE2_HMMU2_BMON_CTI_BASE 0x64A5000ull
+#define DCORE2_HMMU2_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_BMON_CTI_SECTION 0x1000
+#define DCORE2_HMMU2_USER_CTI_BASE 0x64A6000ull
+#define DCORE2_HMMU2_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_USER_CTI_SECTION 0x1000
+#define DCORE2_HMMU2_BMON_0_BASE 0x64A7000ull
+#define DCORE2_HMMU2_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_BMON_0_SECTION 0x1000
+#define DCORE2_HMMU2_BMON_1_BASE 0x64A8000ull
+#define DCORE2_HMMU2_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_BMON_1_SECTION 0x1000
+#define DCORE2_HMMU2_BMON_3_BASE 0x64A9000ull
+#define DCORE2_HMMU2_BMON_3_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_BMON_3_SECTION 0x1000
+#define DCORE2_HMMU2_BMON_2_BASE 0x64AA000ull
+#define DCORE2_HMMU2_BMON_2_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_BMON_2_SECTION 0x1000
+#define DCORE2_HMMU2_BMON_4_BASE 0x64AB000ull
+#define DCORE2_HMMU2_BMON_4_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_BMON_4_SECTION 0x5000
+#define DCORE2_HMMU3_CS_ROM_TBL_BASE 0x64B0000ull
+#define DCORE2_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_CS_ROM_TBL_SECTION 0x1000
+#define DCORE2_HMMU3_CS_STM_BASE 0x64B1000ull
+#define DCORE2_HMMU3_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_CS_STM_SECTION 0x1000
+#define DCORE2_HMMU3_CS_CTI_BASE 0x64B2000ull
+#define DCORE2_HMMU3_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_CS_CTI_SECTION 0x1000
+#define DCORE2_HMMU3_CS_ETF_BASE 0x64B3000ull
+#define DCORE2_HMMU3_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_CS_ETF_SECTION 0x1000
+#define DCORE2_HMMU3_CS_SPMU_BASE 0x64B4000ull
+#define DCORE2_HMMU3_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_CS_SPMU_SECTION 0x1000
+#define DCORE2_HMMU3_BMON_CTI_BASE 0x64B5000ull
+#define DCORE2_HMMU3_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_BMON_CTI_SECTION 0x1000
+#define DCORE2_HMMU3_USER_CTI_BASE 0x64B6000ull
+#define DCORE2_HMMU3_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_USER_CTI_SECTION 0x1000
+#define DCORE2_HMMU3_BMON_0_BASE 0x64B7000ull
+#define DCORE2_HMMU3_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_BMON_0_SECTION 0x1000
+#define DCORE2_HMMU3_BMON_1_BASE 0x64B8000ull
+#define DCORE2_HMMU3_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_BMON_1_SECTION 0x1000
+#define DCORE2_HMMU3_BMON_3_BASE 0x64B9000ull
+#define DCORE2_HMMU3_BMON_3_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_BMON_3_SECTION 0x1000
+#define DCORE2_HMMU3_BMON_2_BASE 0x64BA000ull
+#define DCORE2_HMMU3_BMON_2_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_BMON_2_SECTION 0x1000
+#define DCORE2_HMMU3_BMON_4_BASE 0x64BB000ull
+#define DCORE2_HMMU3_BMON_4_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_BMON_4_SECTION 0x5000
+#define DCORE2_MME_CTRL_ROM_TABLE_BASE 0x64C0000ull
+#define DCORE2_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_ROM_TABLE_SECTION 0x1000
+#define DCORE2_MME_CTRL_STM_BASE 0x64C1000ull
+#define DCORE2_MME_CTRL_STM_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_STM_SECTION 0x1000
+#define DCORE2_MME_CTRL_CTI_BASE 0x64C2000ull
+#define DCORE2_MME_CTRL_CTI_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_CTI_SECTION 0x1000
+#define DCORE2_MME_CTRL_ETF_BASE 0x64C3000ull
+#define DCORE2_MME_CTRL_ETF_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_ETF_SECTION 0x1000
+#define DCORE2_MME_CTRL_SPMU_BASE 0x64C4000ull
+#define DCORE2_MME_CTRL_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_SPMU_SECTION 0x1000
+#define DCORE2_MME_CTRL_CTI0_BASE 0x64C5000ull
+#define DCORE2_MME_CTRL_CTI0_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_CTI0_SECTION 0x1000
+#define DCORE2_MME_CTRL_CTI1_BASE 0x64C6000ull
+#define DCORE2_MME_CTRL_CTI1_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_CTI1_SECTION 0x1000
+#define DCORE2_MME_CTRL_BMON0_BASE 0x64C7000ull
+#define DCORE2_MME_CTRL_BMON0_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_BMON0_SECTION 0x1000
+#define DCORE2_MME_CTRL_BMON1_BASE 0x64C8000ull
+#define DCORE2_MME_CTRL_BMON1_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_BMON1_SECTION 0x1000
+#define DCORE2_MME_CTRL_BMON2_BASE 0x64C9000ull
+#define DCORE2_MME_CTRL_BMON2_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_BMON2_SECTION 0x1000
+#define DCORE2_MME_CTRL_BMON3_BASE 0x64CA000ull
+#define DCORE2_MME_CTRL_BMON3_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_BMON3_SECTION 0x1000
+#define DCORE2_MME_CTRL_ARC_RTT_BASE 0x64CB000ull
+#define DCORE2_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_ARC_RTT_SECTION 0x5000
+#define DCORE2_MME_SBTE0_ROM_TBL_BASE 0x64D0000ull
+#define DCORE2_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_ROM_TBL_SECTION 0x1000
+#define DCORE2_MME_SBTE0_STM_BASE 0x64D1000ull
+#define DCORE2_MME_SBTE0_STM_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_STM_SECTION 0x1000
+#define DCORE2_MME_SBTE0_CTI_BASE 0x64D2000ull
+#define DCORE2_MME_SBTE0_CTI_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_CTI_SECTION 0x1000
+#define DCORE2_MME_SBTE0_ETF_BASE 0x64D3000ull
+#define DCORE2_MME_SBTE0_ETF_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_ETF_SECTION 0x1000
+#define DCORE2_MME_SBTE0_SPMU_BASE 0x64D4000ull
+#define DCORE2_MME_SBTE0_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_SPMU_SECTION 0x1000
+#define DCORE2_MME_SBTE0_CTI0_BASE 0x64D5000ull
+#define DCORE2_MME_SBTE0_CTI0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_CTI0_SECTION 0x1000
+#define DCORE2_MME_SBTE0_CTI1_BASE 0x64D6000ull
+#define DCORE2_MME_SBTE0_CTI1_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_CTI1_SECTION 0x1000
+#define DCORE2_MME_SBTE0_BMON0_BASE 0x64D7000ull
+#define DCORE2_MME_SBTE0_BMON0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_BMON0_SECTION 0x1000
+#define DCORE2_MME_SBTE1_ROM_TBL_BASE 0x64D8000ull
+#define DCORE2_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_ROM_TBL_SECTION 0x1000
+#define DCORE2_MME_SBTE1_STM_BASE 0x64D9000ull
+#define DCORE2_MME_SBTE1_STM_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_STM_SECTION 0x1000
+#define DCORE2_MME_SBTE1_CTI_BASE 0x64DA000ull
+#define DCORE2_MME_SBTE1_CTI_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_CTI_SECTION 0x1000
+#define DCORE2_MME_SBTE1_ETF_BASE 0x64DB000ull
+#define DCORE2_MME_SBTE1_ETF_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_ETF_SECTION 0x1000
+#define DCORE2_MME_SBTE1_SPMU_BASE 0x64DC000ull
+#define DCORE2_MME_SBTE1_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_SPMU_SECTION 0x1000
+#define DCORE2_MME_SBTE1_CTI0_BASE 0x64DD000ull
+#define DCORE2_MME_SBTE1_CTI0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_CTI0_SECTION 0x1000
+#define DCORE2_MME_SBTE1_CTI1_BASE 0x64DE000ull
+#define DCORE2_MME_SBTE1_CTI1_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_CTI1_SECTION 0x1000
+#define DCORE2_MME_SBTE1_BMON0_BASE 0x64DF000ull
+#define DCORE2_MME_SBTE1_BMON0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_BMON0_SECTION 0x1000
+#define DCORE2_MME_SBTE2_ROM_TBL_BASE 0x64E0000ull
+#define DCORE2_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_ROM_TBL_SECTION 0x1000
+#define DCORE2_MME_SBTE2_STM_BASE 0x64E1000ull
+#define DCORE2_MME_SBTE2_STM_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_STM_SECTION 0x1000
+#define DCORE2_MME_SBTE2_CTI_BASE 0x64E2000ull
+#define DCORE2_MME_SBTE2_CTI_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_CTI_SECTION 0x1000
+#define DCORE2_MME_SBTE2_ETF_BASE 0x64E3000ull
+#define DCORE2_MME_SBTE2_ETF_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_ETF_SECTION 0x1000
+#define DCORE2_MME_SBTE2_SPMU_BASE 0x64E4000ull
+#define DCORE2_MME_SBTE2_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_SPMU_SECTION 0x1000
+#define DCORE2_MME_SBTE2_CTI0_BASE 0x64E5000ull
+#define DCORE2_MME_SBTE2_CTI0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_CTI0_SECTION 0x1000
+#define DCORE2_MME_SBTE2_CTI1_BASE 0x64E6000ull
+#define DCORE2_MME_SBTE2_CTI1_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_CTI1_SECTION 0x1000
+#define DCORE2_MME_SBTE2_BMON0_BASE 0x64E7000ull
+#define DCORE2_MME_SBTE2_BMON0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_BMON0_SECTION 0x1000
+#define DCORE2_MME_SBTE3_ROM_TBL_BASE 0x64E8000ull
+#define DCORE2_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_ROM_TBL_SECTION 0x1000
+#define DCORE2_MME_SBTE3_STM_BASE 0x64E9000ull
+#define DCORE2_MME_SBTE3_STM_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_STM_SECTION 0x1000
+#define DCORE2_MME_SBTE3_CTI_BASE 0x64EA000ull
+#define DCORE2_MME_SBTE3_CTI_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_CTI_SECTION 0x1000
+#define DCORE2_MME_SBTE3_ETF_BASE 0x64EB000ull
+#define DCORE2_MME_SBTE3_ETF_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_ETF_SECTION 0x1000
+#define DCORE2_MME_SBTE3_SPMU_BASE 0x64EC000ull
+#define DCORE2_MME_SBTE3_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_SPMU_SECTION 0x1000
+#define DCORE2_MME_SBTE3_CTI0_BASE 0x64ED000ull
+#define DCORE2_MME_SBTE3_CTI0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_CTI0_SECTION 0x1000
+#define DCORE2_MME_SBTE3_CTI1_BASE 0x64EE000ull
+#define DCORE2_MME_SBTE3_CTI1_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_CTI1_SECTION 0x1000
+#define DCORE2_MME_SBTE3_BMON0_BASE 0x64EF000ull
+#define DCORE2_MME_SBTE3_BMON0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_BMON0_SECTION 0x1000
+#define DCORE2_MME_SBTE4_ROM_TBL_BASE 0x64F0000ull
+#define DCORE2_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_ROM_TBL_SECTION 0x1000
+#define DCORE2_MME_SBTE4_STM_BASE 0x64F1000ull
+#define DCORE2_MME_SBTE4_STM_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_STM_SECTION 0x1000
+#define DCORE2_MME_SBTE4_CTI_BASE 0x64F2000ull
+#define DCORE2_MME_SBTE4_CTI_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_CTI_SECTION 0x1000
+#define DCORE2_MME_SBTE4_ETF_BASE 0x64F3000ull
+#define DCORE2_MME_SBTE4_ETF_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_ETF_SECTION 0x1000
+#define DCORE2_MME_SBTE4_SPMU_BASE 0x64F4000ull
+#define DCORE2_MME_SBTE4_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_SPMU_SECTION 0x1000
+#define DCORE2_MME_SBTE4_CTI0_BASE 0x64F5000ull
+#define DCORE2_MME_SBTE4_CTI0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_CTI0_SECTION 0x1000
+#define DCORE2_MME_SBTE4_CTI1_BASE 0x64F6000ull
+#define DCORE2_MME_SBTE4_CTI1_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_CTI1_SECTION 0x1000
+#define DCORE2_MME_SBTE4_BMON0_BASE 0x64F7000ull
+#define DCORE2_MME_SBTE4_BMON0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_BMON0_SECTION 0x9000
+#define DCORE2_MME_ACC_CS_ROM_TBL_BASE 0x6500000ull
+#define DCORE2_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_CS_ROM_TBL_SECTION 0x1000
+#define DCORE2_MME_ACC_STM_BASE 0x6501000ull
+#define DCORE2_MME_ACC_STM_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_STM_SECTION 0x1000
+#define DCORE2_MME_ACC_CTI_BASE 0x6502000ull
+#define DCORE2_MME_ACC_CTI_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_CTI_SECTION 0x1000
+#define DCORE2_MME_ACC_ETF_BASE 0x6503000ull
+#define DCORE2_MME_ACC_ETF_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_ETF_SECTION 0x1000
+#define DCORE2_MME_ACC_SPMU_BASE 0x6504000ull
+#define DCORE2_MME_ACC_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_SPMU_SECTION 0x1000
+#define DCORE2_MME_ACC_CTI0_BASE 0x6505000ull
+#define DCORE2_MME_ACC_CTI0_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_CTI0_SECTION 0x1000
+#define DCORE2_MME_ACC_CTI1_BASE 0x6506000ull
+#define DCORE2_MME_ACC_CTI1_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_CTI1_SECTION 0x1000
+#define DCORE2_MME_ACC_BMON0_BASE 0x6507000ull
+#define DCORE2_MME_ACC_BMON0_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_BMON0_SECTION 0x1000
+#define DCORE2_MME_ACC_BMON1_BASE 0x6508000ull
+#define DCORE2_MME_ACC_BMON1_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_BMON1_SECTION 0x8000
+#define DCORE2_SM_CS_DBG_ROM_TBL_BASE 0x6510000ull
+#define DCORE2_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_SM_CS_DBG_ROM_TBL_SECTION 0x1000
+#define DCORE2_SM_STM_BASE 0x6511000ull
+#define DCORE2_SM_STM_MAX_OFFSET 0x1000
+#define DCORE2_SM_STM_SECTION 0x1000
+#define DCORE2_SM_CTI_BASE 0x6512000ull
+#define DCORE2_SM_CTI_MAX_OFFSET 0x1000
+#define DCORE2_SM_CTI_SECTION 0x1000
+#define DCORE2_SM_ETF_BASE 0x6513000ull
+#define DCORE2_SM_ETF_MAX_OFFSET 0x1000
+#define DCORE2_SM_ETF_SECTION 0x1000
+#define DCORE2_SM_SPMU_BASE 0x6514000ull
+#define DCORE2_SM_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_SM_SPMU_SECTION 0x1000
+#define DCORE2_SM_BMON_CTI_BASE 0x6515000ull
+#define DCORE2_SM_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_SM_BMON_CTI_SECTION 0x1000
+#define DCORE2_SM_USER_CTI_BASE 0x6516000ull
+#define DCORE2_SM_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_SM_USER_CTI_SECTION 0x1000
+#define DCORE2_SM_BMON_BASE 0x6517000ull
+#define DCORE2_SM_BMON_MAX_OFFSET 0x1000
+#define DCORE2_SM_BMON_SECTION 0x1000
+#define DCORE2_SM_BMON1_BASE 0x6518000ull
+#define DCORE2_SM_BMON1_MAX_OFFSET 0x1000
+#define DCORE2_SM_BMON1_SECTION 0x18000
+#define DCORE2_XFT_FUNNEL_BASE 0x6530000ull
+#define DCORE2_XFT_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_XFT_FUNNEL_SECTION 0x8000
+#define DCORE2_TFT0_FUNNEL_BASE 0x6538000ull
+#define DCORE2_TFT0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TFT0_FUNNEL_SECTION 0x1000
+#define DCORE2_TFT1_FUNNEL_BASE 0x6539000ull
+#define DCORE2_TFT1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TFT1_FUNNEL_SECTION 0x1000
+#define DCORE2_TFT2_FUNNEL_BASE 0x653A000ull
+#define DCORE2_TFT2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TFT2_FUNNEL_SECTION 0x7000
+#define DCORE2_RTR0_FUNNEL_BASE 0x6541000ull
+#define DCORE2_RTR0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR0_FUNNEL_SECTION 0x8000
+#define DCORE2_RTR1_FUNNEL_BASE 0x6549000ull
+#define DCORE2_RTR1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR1_FUNNEL_SECTION 0x8000
+#define DCORE2_RTR2_FUNNEL_BASE 0x6551000ull
+#define DCORE2_RTR2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR2_FUNNEL_SECTION 0x8000
+#define DCORE2_RTR3_FUNNEL_BASE 0x6559000ull
+#define DCORE2_RTR3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR3_FUNNEL_SECTION 0x8000
+#define DCORE2_RTR4_FUNNEL_BASE 0x6561000ull
+#define DCORE2_RTR4_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR4_FUNNEL_SECTION 0x4000
+#define DCORE2_MIF0_FUNNEL_BASE 0x6565000ull
+#define DCORE2_MIF0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_MIF0_FUNNEL_SECTION 0x4000
+#define DCORE2_RTR5_FUNNEL_BASE 0x6569000ull
+#define DCORE2_RTR5_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR5_FUNNEL_SECTION 0x4000
+#define DCORE2_MIF1_FUNNEL_BASE 0x656D000ull
+#define DCORE2_MIF1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_MIF1_FUNNEL_SECTION 0x4000
+#define DCORE2_RTR6_FUNNEL_BASE 0x6571000ull
+#define DCORE2_RTR6_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR6_FUNNEL_SECTION 0x4000
+#define DCORE2_MIF2_FUNNEL_BASE 0x6575000ull
+#define DCORE2_MIF2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_MIF2_FUNNEL_SECTION 0x4000
+#define DCORE2_RTR7_FUNNEL_BASE 0x6579000ull
+#define DCORE2_RTR7_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR7_FUNNEL_SECTION 0x4000
+#define DCORE2_MIF3_FUNNEL_BASE 0x657D000ull
+#define DCORE2_MIF3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_MIF3_FUNNEL_SECTION 0x43000
+#define DCORE2_EDMA0_CS_ROM_TBL_BASE 0x65C0000ull
+#define DCORE2_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_CS_ROM_TBL_SECTION 0x1000
+#define DCORE2_EDMA0_CS_STM_BASE 0x65C1000ull
+#define DCORE2_EDMA0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_CS_STM_SECTION 0x1000
+#define DCORE2_EDMA0_CS_CTI_BASE 0x65C2000ull
+#define DCORE2_EDMA0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_CS_CTI_SECTION 0x1000
+#define DCORE2_EDMA0_CS_ETF_BASE 0x65C3000ull
+#define DCORE2_EDMA0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_CS_ETF_SECTION 0x1000
+#define DCORE2_EDMA0_CS_SPMU_BASE 0x65C4000ull
+#define DCORE2_EDMA0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_CS_SPMU_SECTION 0x1000
+#define DCORE2_EDMA0_BMON_CTI_BASE 0x65C5000ull
+#define DCORE2_EDMA0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_BMON_CTI_SECTION 0x1000
+#define DCORE2_EDMA0_USER_CTI_BASE 0x65C6000ull
+#define DCORE2_EDMA0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_USER_CTI_SECTION 0x1000
+#define DCORE2_EDMA0_BMON_0_BASE 0x65C7000ull
+#define DCORE2_EDMA0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_BMON_0_SECTION 0x1000
+#define DCORE2_EDMA0_BMON_1_BASE 0x65C8000ull
+#define DCORE2_EDMA0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_BMON_1_SECTION 0x1000
+#define DCORE2_EDMA0_QM_ARC_RTT_BASE 0x65C9000ull
+#define DCORE2_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_EDMA0_QM_ARC_RTT_SECTION 0x7000
+#define DCORE2_EDMA1_CS_ROM_TBL_BASE 0x65D0000ull
+#define DCORE2_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_CS_ROM_TBL_SECTION 0x1000
+#define DCORE2_EDMA1_CS_STM_BASE 0x65D1000ull
+#define DCORE2_EDMA1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_CS_STM_SECTION 0x1000
+#define DCORE2_EDMA1_CS_CTI_BASE 0x65D2000ull
+#define DCORE2_EDMA1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_CS_CTI_SECTION 0x1000
+#define DCORE2_EDMA1_CS_ETF_BASE 0x65D3000ull
+#define DCORE2_EDMA1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_CS_ETF_SECTION 0x1000
+#define DCORE2_EDMA1_CS_SPMU_BASE 0x65D4000ull
+#define DCORE2_EDMA1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_CS_SPMU_SECTION 0x1000
+#define DCORE2_EDMA1_BMON_CTI_BASE 0x65D5000ull
+#define DCORE2_EDMA1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_BMON_CTI_SECTION 0x1000
+#define DCORE2_EDMA1_USER_CTI_BASE 0x65D6000ull
+#define DCORE2_EDMA1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_USER_CTI_SECTION 0x1000
+#define DCORE2_EDMA1_BMON_0_BASE 0x65D7000ull
+#define DCORE2_EDMA1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_BMON_0_SECTION 0x1000
+#define DCORE2_EDMA1_BMON_1_BASE 0x65D8000ull
+#define DCORE2_EDMA1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_BMON_1_SECTION 0x1000
+#define DCORE2_EDMA1_QM_ARC_RTT_BASE 0x65D9000ull
+#define DCORE2_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_EDMA1_QM_ARC_RTT_SECTION 0x7000
+#define DCORE2_VDEC0_CS_ROM_TBL_BASE 0x65E0000ull
+#define DCORE2_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_CS_ROM_TBL_SECTION 0x1000
+#define DCORE2_VDEC0_CS_STM_BASE 0x65E1000ull
+#define DCORE2_VDEC0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_CS_STM_SECTION 0x1000
+#define DCORE2_VDEC0_CS_CTI_BASE 0x65E2000ull
+#define DCORE2_VDEC0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_CS_CTI_SECTION 0x1000
+#define DCORE2_VDEC0_CS_ETF_BASE 0x65E3000ull
+#define DCORE2_VDEC0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_CS_ETF_SECTION 0x1000
+#define DCORE2_VDEC0_CS_SPMU_BASE 0x65E4000ull
+#define DCORE2_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_CS_SPMU_SECTION 0x1000
+#define DCORE2_VDEC0_BMON_CTI_BASE 0x65E5000ull
+#define DCORE2_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_BMON_CTI_SECTION 0x1000
+#define DCORE2_VDEC0_USER_CTI_BASE 0x65E6000ull
+#define DCORE2_VDEC0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_USER_CTI_SECTION 0x1000
+#define DCORE2_VDEC0_BMON_0_BASE 0x65E7000ull
+#define DCORE2_VDEC0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_BMON_0_SECTION 0x1000
+#define DCORE2_VDEC0_BMON_1_BASE 0x65E8000ull
+#define DCORE2_VDEC0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_BMON_1_SECTION 0x1000
+#define DCORE2_VDEC0_BMON_2_BASE 0x65E9000ull
+#define DCORE2_VDEC0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_BMON_2_SECTION 0x7000
+#define DCORE2_VDEC1_CS_ROM_TBL_BASE 0x65F0000ull
+#define DCORE2_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_CS_ROM_TBL_SECTION 0x1000
+#define DCORE2_VDEC1_CS_STM_BASE 0x65F1000ull
+#define DCORE2_VDEC1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_CS_STM_SECTION 0x1000
+#define DCORE2_VDEC1_CS_CTI_BASE 0x65F2000ull
+#define DCORE2_VDEC1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_CS_CTI_SECTION 0x1000
+#define DCORE2_VDEC1_CS_ETF_BASE 0x65F3000ull
+#define DCORE2_VDEC1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_CS_ETF_SECTION 0x1000
+#define DCORE2_VDEC1_CS_SPMU_BASE 0x65F4000ull
+#define DCORE2_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_CS_SPMU_SECTION 0x1000
+#define DCORE2_VDEC1_BMON_CTI_BASE 0x65F5000ull
+#define DCORE2_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_BMON_CTI_SECTION 0x1000
+#define DCORE2_VDEC1_USER_CTI_BASE 0x65F6000ull
+#define DCORE2_VDEC1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_USER_CTI_SECTION 0x1000
+#define DCORE2_VDEC1_BMON_0_BASE 0x65F7000ull
+#define DCORE2_VDEC1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_BMON_0_SECTION 0x1000
+#define DCORE2_VDEC1_BMON_1_BASE 0x65F8000ull
+#define DCORE2_VDEC1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_BMON_1_SECTION 0x1000
+#define DCORE2_VDEC1_BMON_2_BASE 0x65F9000ull
+#define DCORE2_VDEC1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_BMON_2_SECTION 0x7000
+#define DCORE3_ROM_TABLE_L_BASE 0x6600000ull
+#define DCORE3_ROM_TABLE_L_MAX_OFFSET 0x1000
+#define DCORE3_ROM_TABLE_L_SECTION 0x80000
+#define DCORE3_HMMU0_CS_ROM_TBL_BASE 0x6680000ull
+#define DCORE3_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_CS_ROM_TBL_SECTION 0x1000
+#define DCORE3_HMMU0_CS_STM_BASE 0x6681000ull
+#define DCORE3_HMMU0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_CS_STM_SECTION 0x1000
+#define DCORE3_HMMU0_CS_CTI_BASE 0x6682000ull
+#define DCORE3_HMMU0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_CS_CTI_SECTION 0x1000
+#define DCORE3_HMMU0_CS_ETF_BASE 0x6683000ull
+#define DCORE3_HMMU0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_CS_ETF_SECTION 0x1000
+#define DCORE3_HMMU0_CS_SPMU_BASE 0x6684000ull
+#define DCORE3_HMMU0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_CS_SPMU_SECTION 0x1000
+#define DCORE3_HMMU0_BMON_CTI_BASE 0x6685000ull
+#define DCORE3_HMMU0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_BMON_CTI_SECTION 0x1000
+#define DCORE3_HMMU0_USER_CTI_BASE 0x6686000ull
+#define DCORE3_HMMU0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_USER_CTI_SECTION 0x1000
+#define DCORE3_HMMU0_BMON_0_BASE 0x6687000ull
+#define DCORE3_HMMU0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_BMON_0_SECTION 0x1000
+#define DCORE3_HMMU0_BMON_1_BASE 0x6688000ull
+#define DCORE3_HMMU0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_BMON_1_SECTION 0x1000
+#define DCORE3_HMMU0_BMON_3_BASE 0x6689000ull
+#define DCORE3_HMMU0_BMON_3_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_BMON_3_SECTION 0x1000
+#define DCORE3_HMMU0_BMON_2_BASE 0x668A000ull
+#define DCORE3_HMMU0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_BMON_2_SECTION 0x1000
+#define DCORE3_HMMU0_BMON_4_BASE 0x668B000ull
+#define DCORE3_HMMU0_BMON_4_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_BMON_4_SECTION 0x5000
+#define DCORE3_HMMU1_CS_ROM_TBL_BASE 0x6690000ull
+#define DCORE3_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_CS_ROM_TBL_SECTION 0x1000
+#define DCORE3_HMMU1_CS_STM_BASE 0x6691000ull
+#define DCORE3_HMMU1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_CS_STM_SECTION 0x1000
+#define DCORE3_HMMU1_CS_CTI_BASE 0x6692000ull
+#define DCORE3_HMMU1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_CS_CTI_SECTION 0x1000
+#define DCORE3_HMMU1_CS_ETF_BASE 0x6693000ull
+#define DCORE3_HMMU1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_CS_ETF_SECTION 0x1000
+#define DCORE3_HMMU1_CS_SPMU_BASE 0x6694000ull
+#define DCORE3_HMMU1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_CS_SPMU_SECTION 0x1000
+#define DCORE3_HMMU1_BMON_CTI_BASE 0x6695000ull
+#define DCORE3_HMMU1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_BMON_CTI_SECTION 0x1000
+#define DCORE3_HMMU1_USER_CTI_BASE 0x6696000ull
+#define DCORE3_HMMU1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_USER_CTI_SECTION 0x1000
+#define DCORE3_HMMU1_BMON_0_BASE 0x6697000ull
+#define DCORE3_HMMU1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_BMON_0_SECTION 0x1000
+#define DCORE3_HMMU1_BMON_1_BASE 0x6698000ull
+#define DCORE3_HMMU1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_BMON_1_SECTION 0x1000
+#define DCORE3_HMMU1_BMON_3_BASE 0x6699000ull
+#define DCORE3_HMMU1_BMON_3_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_BMON_3_SECTION 0x1000
+#define DCORE3_HMMU1_BMON_2_BASE 0x669A000ull
+#define DCORE3_HMMU1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_BMON_2_SECTION 0x1000
+#define DCORE3_HMMU1_BMON_4_BASE 0x669B000ull
+#define DCORE3_HMMU1_BMON_4_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_BMON_4_SECTION 0x5000
+#define DCORE3_HMMU2_CS_ROM_TBL_BASE 0x66A0000ull
+#define DCORE3_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_CS_ROM_TBL_SECTION 0x1000
+#define DCORE3_HMMU2_CS_STM_BASE 0x66A1000ull
+#define DCORE3_HMMU2_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_CS_STM_SECTION 0x1000
+#define DCORE3_HMMU2_CS_CTI_BASE 0x66A2000ull
+#define DCORE3_HMMU2_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_CS_CTI_SECTION 0x1000
+#define DCORE3_HMMU2_CS_ETF_BASE 0x66A3000ull
+#define DCORE3_HMMU2_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_CS_ETF_SECTION 0x1000
+#define DCORE3_HMMU2_CS_SPMU_BASE 0x66A4000ull
+#define DCORE3_HMMU2_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_CS_SPMU_SECTION 0x1000
+#define DCORE3_HMMU2_BMON_CTI_BASE 0x66A5000ull
+#define DCORE3_HMMU2_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_BMON_CTI_SECTION 0x1000
+#define DCORE3_HMMU2_USER_CTI_BASE 0x66A6000ull
+#define DCORE3_HMMU2_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_USER_CTI_SECTION 0x1000
+#define DCORE3_HMMU2_BMON_0_BASE 0x66A7000ull
+#define DCORE3_HMMU2_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_BMON_0_SECTION 0x1000
+#define DCORE3_HMMU2_BMON_1_BASE 0x66A8000ull
+#define DCORE3_HMMU2_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_BMON_1_SECTION 0x1000
+#define DCORE3_HMMU2_BMON_3_BASE 0x66A9000ull
+#define DCORE3_HMMU2_BMON_3_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_BMON_3_SECTION 0x1000
+#define DCORE3_HMMU2_BMON_2_BASE 0x66AA000ull
+#define DCORE3_HMMU2_BMON_2_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_BMON_2_SECTION 0x1000
+#define DCORE3_HMMU2_BMON_4_BASE 0x66AB000ull
+#define DCORE3_HMMU2_BMON_4_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_BMON_4_SECTION 0x5000
+#define DCORE3_HMMU3_CS_ROM_TBL_BASE 0x66B0000ull
+#define DCORE3_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_CS_ROM_TBL_SECTION 0x1000
+#define DCORE3_HMMU3_CS_STM_BASE 0x66B1000ull
+#define DCORE3_HMMU3_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_CS_STM_SECTION 0x1000
+#define DCORE3_HMMU3_CS_CTI_BASE 0x66B2000ull
+#define DCORE3_HMMU3_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_CS_CTI_SECTION 0x1000
+#define DCORE3_HMMU3_CS_ETF_BASE 0x66B3000ull
+#define DCORE3_HMMU3_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_CS_ETF_SECTION 0x1000
+#define DCORE3_HMMU3_CS_SPMU_BASE 0x66B4000ull
+#define DCORE3_HMMU3_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_CS_SPMU_SECTION 0x1000
+#define DCORE3_HMMU3_BMON_CTI_BASE 0x66B5000ull
+#define DCORE3_HMMU3_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_BMON_CTI_SECTION 0x1000
+#define DCORE3_HMMU3_USER_CTI_BASE 0x66B6000ull
+#define DCORE3_HMMU3_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_USER_CTI_SECTION 0x1000
+#define DCORE3_HMMU3_BMON_0_BASE 0x66B7000ull
+#define DCORE3_HMMU3_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_BMON_0_SECTION 0x1000
+#define DCORE3_HMMU3_BMON_1_BASE 0x66B8000ull
+#define DCORE3_HMMU3_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_BMON_1_SECTION 0x1000
+#define DCORE3_HMMU3_BMON_3_BASE 0x66B9000ull
+#define DCORE3_HMMU3_BMON_3_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_BMON_3_SECTION 0x1000
+#define DCORE3_HMMU3_BMON_2_BASE 0x66BA000ull
+#define DCORE3_HMMU3_BMON_2_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_BMON_2_SECTION 0x1000
+#define DCORE3_HMMU3_BMON_4_BASE 0x66BB000ull
+#define DCORE3_HMMU3_BMON_4_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_BMON_4_SECTION 0x5000
+#define DCORE3_MME_CTRL_ROM_TABLE_BASE 0x66C0000ull
+#define DCORE3_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_ROM_TABLE_SECTION 0x1000
+#define DCORE3_MME_CTRL_STM_BASE 0x66C1000ull
+#define DCORE3_MME_CTRL_STM_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_STM_SECTION 0x1000
+#define DCORE3_MME_CTRL_CTI_BASE 0x66C2000ull
+#define DCORE3_MME_CTRL_CTI_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_CTI_SECTION 0x1000
+#define DCORE3_MME_CTRL_ETF_BASE 0x66C3000ull
+#define DCORE3_MME_CTRL_ETF_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_ETF_SECTION 0x1000
+#define DCORE3_MME_CTRL_SPMU_BASE 0x66C4000ull
+#define DCORE3_MME_CTRL_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_SPMU_SECTION 0x1000
+#define DCORE3_MME_CTRL_CTI0_BASE 0x66C5000ull
+#define DCORE3_MME_CTRL_CTI0_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_CTI0_SECTION 0x1000
+#define DCORE3_MME_CTRL_CTI1_BASE 0x66C6000ull
+#define DCORE3_MME_CTRL_CTI1_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_CTI1_SECTION 0x1000
+#define DCORE3_MME_CTRL_BMON0_BASE 0x66C7000ull
+#define DCORE3_MME_CTRL_BMON0_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_BMON0_SECTION 0x1000
+#define DCORE3_MME_CTRL_BMON1_BASE 0x66C8000ull
+#define DCORE3_MME_CTRL_BMON1_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_BMON1_SECTION 0x1000
+#define DCORE3_MME_CTRL_BMON2_BASE 0x66C9000ull
+#define DCORE3_MME_CTRL_BMON2_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_BMON2_SECTION 0x1000
+#define DCORE3_MME_CTRL_BMON3_BASE 0x66CA000ull
+#define DCORE3_MME_CTRL_BMON3_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_BMON3_SECTION 0x1000
+#define DCORE3_MME_CTRL_ARC_RTT_BASE 0x66CB000ull
+#define DCORE3_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_ARC_RTT_SECTION 0x5000
+#define DCORE3_MME_SBTE0_ROM_TBL_BASE 0x66D0000ull
+#define DCORE3_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_ROM_TBL_SECTION 0x1000
+#define DCORE3_MME_SBTE0_STM_BASE 0x66D1000ull
+#define DCORE3_MME_SBTE0_STM_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_STM_SECTION 0x1000
+#define DCORE3_MME_SBTE0_CTI_BASE 0x66D2000ull
+#define DCORE3_MME_SBTE0_CTI_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_CTI_SECTION 0x1000
+#define DCORE3_MME_SBTE0_ETF_BASE 0x66D3000ull
+#define DCORE3_MME_SBTE0_ETF_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_ETF_SECTION 0x1000
+#define DCORE3_MME_SBTE0_SPMU_BASE 0x66D4000ull
+#define DCORE3_MME_SBTE0_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_SPMU_SECTION 0x1000
+#define DCORE3_MME_SBTE0_CTI0_BASE 0x66D5000ull
+#define DCORE3_MME_SBTE0_CTI0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_CTI0_SECTION 0x1000
+#define DCORE3_MME_SBTE0_CTI1_BASE 0x66D6000ull
+#define DCORE3_MME_SBTE0_CTI1_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_CTI1_SECTION 0x1000
+#define DCORE3_MME_SBTE0_BMON0_BASE 0x66D7000ull
+#define DCORE3_MME_SBTE0_BMON0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_BMON0_SECTION 0x1000
+#define DCORE3_MME_SBTE1_ROM_TBL_BASE 0x66D8000ull
+#define DCORE3_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_ROM_TBL_SECTION 0x1000
+#define DCORE3_MME_SBTE1_STM_BASE 0x66D9000ull
+#define DCORE3_MME_SBTE1_STM_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_STM_SECTION 0x1000
+#define DCORE3_MME_SBTE1_CTI_BASE 0x66DA000ull
+#define DCORE3_MME_SBTE1_CTI_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_CTI_SECTION 0x1000
+#define DCORE3_MME_SBTE1_ETF_BASE 0x66DB000ull
+#define DCORE3_MME_SBTE1_ETF_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_ETF_SECTION 0x1000
+#define DCORE3_MME_SBTE1_SPMU_BASE 0x66DC000ull
+#define DCORE3_MME_SBTE1_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_SPMU_SECTION 0x1000
+#define DCORE3_MME_SBTE1_CTI0_BASE 0x66DD000ull
+#define DCORE3_MME_SBTE1_CTI0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_CTI0_SECTION 0x1000
+#define DCORE3_MME_SBTE1_CTI1_BASE 0x66DE000ull
+#define DCORE3_MME_SBTE1_CTI1_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_CTI1_SECTION 0x1000
+#define DCORE3_MME_SBTE1_BMON0_BASE 0x66DF000ull
+#define DCORE3_MME_SBTE1_BMON0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_BMON0_SECTION 0x1000
+#define DCORE3_MME_SBTE2_ROM_TBL_BASE 0x66E0000ull
+#define DCORE3_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_ROM_TBL_SECTION 0x1000
+#define DCORE3_MME_SBTE2_STM_BASE 0x66E1000ull
+#define DCORE3_MME_SBTE2_STM_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_STM_SECTION 0x1000
+#define DCORE3_MME_SBTE2_CTI_BASE 0x66E2000ull
+#define DCORE3_MME_SBTE2_CTI_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_CTI_SECTION 0x1000
+#define DCORE3_MME_SBTE2_ETF_BASE 0x66E3000ull
+#define DCORE3_MME_SBTE2_ETF_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_ETF_SECTION 0x1000
+#define DCORE3_MME_SBTE2_SPMU_BASE 0x66E4000ull
+#define DCORE3_MME_SBTE2_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_SPMU_SECTION 0x1000
+#define DCORE3_MME_SBTE2_CTI0_BASE 0x66E5000ull
+#define DCORE3_MME_SBTE2_CTI0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_CTI0_SECTION 0x1000
+#define DCORE3_MME_SBTE2_CTI1_BASE 0x66E6000ull
+#define DCORE3_MME_SBTE2_CTI1_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_CTI1_SECTION 0x1000
+#define DCORE3_MME_SBTE2_BMON0_BASE 0x66E7000ull
+#define DCORE3_MME_SBTE2_BMON0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_BMON0_SECTION 0x1000
+#define DCORE3_MME_SBTE3_ROM_TBL_BASE 0x66E8000ull
+#define DCORE3_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_ROM_TBL_SECTION 0x1000
+#define DCORE3_MME_SBTE3_STM_BASE 0x66E9000ull
+#define DCORE3_MME_SBTE3_STM_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_STM_SECTION 0x1000
+#define DCORE3_MME_SBTE3_CTI_BASE 0x66EA000ull
+#define DCORE3_MME_SBTE3_CTI_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_CTI_SECTION 0x1000
+#define DCORE3_MME_SBTE3_ETF_BASE 0x66EB000ull
+#define DCORE3_MME_SBTE3_ETF_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_ETF_SECTION 0x1000
+#define DCORE3_MME_SBTE3_SPMU_BASE 0x66EC000ull
+#define DCORE3_MME_SBTE3_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_SPMU_SECTION 0x1000
+#define DCORE3_MME_SBTE3_CTI0_BASE 0x66ED000ull
+#define DCORE3_MME_SBTE3_CTI0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_CTI0_SECTION 0x1000
+#define DCORE3_MME_SBTE3_CTI1_BASE 0x66EE000ull
+#define DCORE3_MME_SBTE3_CTI1_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_CTI1_SECTION 0x1000
+#define DCORE3_MME_SBTE3_BMON0_BASE 0x66EF000ull
+#define DCORE3_MME_SBTE3_BMON0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_BMON0_SECTION 0x1000
+#define DCORE3_MME_SBTE4_ROM_TBL_BASE 0x66F0000ull
+#define DCORE3_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_ROM_TBL_SECTION 0x1000
+#define DCORE3_MME_SBTE4_STM_BASE 0x66F1000ull
+#define DCORE3_MME_SBTE4_STM_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_STM_SECTION 0x1000
+#define DCORE3_MME_SBTE4_CTI_BASE 0x66F2000ull
+#define DCORE3_MME_SBTE4_CTI_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_CTI_SECTION 0x1000
+#define DCORE3_MME_SBTE4_ETF_BASE 0x66F3000ull
+#define DCORE3_MME_SBTE4_ETF_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_ETF_SECTION 0x1000
+#define DCORE3_MME_SBTE4_SPMU_BASE 0x66F4000ull
+#define DCORE3_MME_SBTE4_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_SPMU_SECTION 0x1000
+#define DCORE3_MME_SBTE4_CTI0_BASE 0x66F5000ull
+#define DCORE3_MME_SBTE4_CTI0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_CTI0_SECTION 0x1000
+#define DCORE3_MME_SBTE4_CTI1_BASE 0x66F6000ull
+#define DCORE3_MME_SBTE4_CTI1_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_CTI1_SECTION 0x1000
+#define DCORE3_MME_SBTE4_BMON0_BASE 0x66F7000ull
+#define DCORE3_MME_SBTE4_BMON0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_BMON0_SECTION 0x9000
+#define DCORE3_MME_ACC_CS_ROM_TBL_BASE 0x6700000ull
+#define DCORE3_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_CS_ROM_TBL_SECTION 0x1000
+#define DCORE3_MME_ACC_STM_BASE 0x6701000ull
+#define DCORE3_MME_ACC_STM_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_STM_SECTION 0x1000
+#define DCORE3_MME_ACC_CTI_BASE 0x6702000ull
+#define DCORE3_MME_ACC_CTI_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_CTI_SECTION 0x1000
+#define DCORE3_MME_ACC_ETF_BASE 0x6703000ull
+#define DCORE3_MME_ACC_ETF_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_ETF_SECTION 0x1000
+#define DCORE3_MME_ACC_SPMU_BASE 0x6704000ull
+#define DCORE3_MME_ACC_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_SPMU_SECTION 0x1000
+#define DCORE3_MME_ACC_CTI0_BASE 0x6705000ull
+#define DCORE3_MME_ACC_CTI0_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_CTI0_SECTION 0x1000
+#define DCORE3_MME_ACC_CTI1_BASE 0x6706000ull
+#define DCORE3_MME_ACC_CTI1_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_CTI1_SECTION 0x1000
+#define DCORE3_MME_ACC_BMON0_BASE 0x6707000ull
+#define DCORE3_MME_ACC_BMON0_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_BMON0_SECTION 0x1000
+#define DCORE3_MME_ACC_BMON1_BASE 0x6708000ull
+#define DCORE3_MME_ACC_BMON1_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_BMON1_SECTION 0x8000
+#define DCORE3_SM_CS_DBG_ROM_TBL_BASE 0x6710000ull
+#define DCORE3_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_SM_CS_DBG_ROM_TBL_SECTION 0x1000
+#define DCORE3_SM_STM_BASE 0x6711000ull
+#define DCORE3_SM_STM_MAX_OFFSET 0x1000
+#define DCORE3_SM_STM_SECTION 0x1000
+#define DCORE3_SM_CTI_BASE 0x6712000ull
+#define DCORE3_SM_CTI_MAX_OFFSET 0x1000
+#define DCORE3_SM_CTI_SECTION 0x1000
+#define DCORE3_SM_ETF_BASE 0x6713000ull
+#define DCORE3_SM_ETF_MAX_OFFSET 0x1000
+#define DCORE3_SM_ETF_SECTION 0x1000
+#define DCORE3_SM_SPMU_BASE 0x6714000ull
+#define DCORE3_SM_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_SM_SPMU_SECTION 0x1000
+#define DCORE3_SM_BMON_CTI_BASE 0x6715000ull
+#define DCORE3_SM_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_SM_BMON_CTI_SECTION 0x1000
+#define DCORE3_SM_USER_CTI_BASE 0x6716000ull
+#define DCORE3_SM_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_SM_USER_CTI_SECTION 0x1000
+#define DCORE3_SM_BMON_BASE 0x6717000ull
+#define DCORE3_SM_BMON_MAX_OFFSET 0x1000
+#define DCORE3_SM_BMON_SECTION 0x1000
+#define DCORE3_SM_BMON1_BASE 0x6718000ull
+#define DCORE3_SM_BMON1_MAX_OFFSET 0x1000
+#define DCORE3_SM_BMON1_SECTION 0x18000
+#define DCORE3_XFT_FUNNEL_BASE 0x6730000ull
+#define DCORE3_XFT_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_XFT_FUNNEL_SECTION 0x8000
+#define DCORE3_TFT0_FUNNEL_BASE 0x6738000ull
+#define DCORE3_TFT0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TFT0_FUNNEL_SECTION 0x1000
+#define DCORE3_TFT1_FUNNEL_BASE 0x6739000ull
+#define DCORE3_TFT1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TFT1_FUNNEL_SECTION 0x1000
+#define DCORE3_TFT2_FUNNEL_BASE 0x673A000ull
+#define DCORE3_TFT2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TFT2_FUNNEL_SECTION 0x7000
+#define DCORE3_RTR0_FUNNEL_BASE 0x6741000ull
+#define DCORE3_RTR0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR0_FUNNEL_SECTION 0x4000
+#define DCORE3_MIF0_FUNNEL_BASE 0x6745000ull
+#define DCORE3_MIF0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_MIF0_FUNNEL_SECTION 0x4000
+#define DCORE3_RTR1_FUNNEL_BASE 0x6749000ull
+#define DCORE3_RTR1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR1_FUNNEL_SECTION 0x4000
+#define DCORE3_MIF1_FUNNEL_BASE 0x674D000ull
+#define DCORE3_MIF1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_MIF1_FUNNEL_SECTION 0x4000
+#define DCORE3_RTR2_FUNNEL_BASE 0x6751000ull
+#define DCORE3_RTR2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR2_FUNNEL_SECTION 0x4000
+#define DCORE3_MIF2_FUNNEL_BASE 0x6755000ull
+#define DCORE3_MIF2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_MIF2_FUNNEL_SECTION 0x4000
+#define DCORE3_RTR3_FUNNEL_BASE 0x6759000ull
+#define DCORE3_RTR3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR3_FUNNEL_SECTION 0x4000
+#define DCORE3_MIF3_FUNNEL_BASE 0x675D000ull
+#define DCORE3_MIF3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_MIF3_FUNNEL_SECTION 0x4000
+#define DCORE3_RTR4_FUNNEL_BASE 0x6761000ull
+#define DCORE3_RTR4_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR4_FUNNEL_SECTION 0x8000
+#define DCORE3_RTR5_FUNNEL_BASE 0x6769000ull
+#define DCORE3_RTR5_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR5_FUNNEL_SECTION 0x8000
+#define DCORE3_RTR6_FUNNEL_BASE 0x6771000ull
+#define DCORE3_RTR6_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR6_FUNNEL_SECTION 0x8000
+#define DCORE3_RTR7_FUNNEL_BASE 0x6779000ull
+#define DCORE3_RTR7_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR7_FUNNEL_SECTION 0x47000
+#define DCORE3_EDMA0_CS_ROM_TBL_BASE 0x67C0000ull
+#define DCORE3_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_CS_ROM_TBL_SECTION 0x1000
+#define DCORE3_EDMA0_CS_STM_BASE 0x67C1000ull
+#define DCORE3_EDMA0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_CS_STM_SECTION 0x1000
+#define DCORE3_EDMA0_CS_CTI_BASE 0x67C2000ull
+#define DCORE3_EDMA0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_CS_CTI_SECTION 0x1000
+#define DCORE3_EDMA0_CS_ETF_BASE 0x67C3000ull
+#define DCORE3_EDMA0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_CS_ETF_SECTION 0x1000
+#define DCORE3_EDMA0_CS_SPMU_BASE 0x67C4000ull
+#define DCORE3_EDMA0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_CS_SPMU_SECTION 0x1000
+#define DCORE3_EDMA0_BMON_CTI_BASE 0x67C5000ull
+#define DCORE3_EDMA0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_BMON_CTI_SECTION 0x1000
+#define DCORE3_EDMA0_USER_CTI_BASE 0x67C6000ull
+#define DCORE3_EDMA0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_USER_CTI_SECTION 0x1000
+#define DCORE3_EDMA0_BMON_0_BASE 0x67C7000ull
+#define DCORE3_EDMA0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_BMON_0_SECTION 0x1000
+#define DCORE3_EDMA0_BMON_1_BASE 0x67C8000ull
+#define DCORE3_EDMA0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_BMON_1_SECTION 0x1000
+#define DCORE3_EDMA0_QM_ARC_RTT_BASE 0x67C9000ull
+#define DCORE3_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_EDMA0_QM_ARC_RTT_SECTION 0x7000
+#define DCORE3_EDMA1_CS_ROM_TBL_BASE 0x67D0000ull
+#define DCORE3_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_CS_ROM_TBL_SECTION 0x1000
+#define DCORE3_EDMA1_CS_STM_BASE 0x67D1000ull
+#define DCORE3_EDMA1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_CS_STM_SECTION 0x1000
+#define DCORE3_EDMA1_CS_CTI_BASE 0x67D2000ull
+#define DCORE3_EDMA1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_CS_CTI_SECTION 0x1000
+#define DCORE3_EDMA1_CS_ETF_BASE 0x67D3000ull
+#define DCORE3_EDMA1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_CS_ETF_SECTION 0x1000
+#define DCORE3_EDMA1_CS_SPMU_BASE 0x67D4000ull
+#define DCORE3_EDMA1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_CS_SPMU_SECTION 0x1000
+#define DCORE3_EDMA1_BMON_CTI_BASE 0x67D5000ull
+#define DCORE3_EDMA1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_BMON_CTI_SECTION 0x1000
+#define DCORE3_EDMA1_USER_CTI_BASE 0x67D6000ull
+#define DCORE3_EDMA1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_USER_CTI_SECTION 0x1000
+#define DCORE3_EDMA1_BMON_0_BASE 0x67D7000ull
+#define DCORE3_EDMA1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_BMON_0_SECTION 0x1000
+#define DCORE3_EDMA1_BMON_1_BASE 0x67D8000ull
+#define DCORE3_EDMA1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_BMON_1_SECTION 0x1000
+#define DCORE3_EDMA1_QM_ARC_RTT_BASE 0x67D9000ull
+#define DCORE3_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_EDMA1_QM_ARC_RTT_SECTION 0x7000
+#define DCORE3_VDEC0_CS_ROM_TBL_BASE 0x67E0000ull
+#define DCORE3_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_CS_ROM_TBL_SECTION 0x1000
+#define DCORE3_VDEC0_CS_STM_BASE 0x67E1000ull
+#define DCORE3_VDEC0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_CS_STM_SECTION 0x1000
+#define DCORE3_VDEC0_CS_CTI_BASE 0x67E2000ull
+#define DCORE3_VDEC0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_CS_CTI_SECTION 0x1000
+#define DCORE3_VDEC0_CS_ETF_BASE 0x67E3000ull
+#define DCORE3_VDEC0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_CS_ETF_SECTION 0x1000
+#define DCORE3_VDEC0_CS_SPMU_BASE 0x67E4000ull
+#define DCORE3_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_CS_SPMU_SECTION 0x1000
+#define DCORE3_VDEC0_BMON_CTI_BASE 0x67E5000ull
+#define DCORE3_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_BMON_CTI_SECTION 0x1000
+#define DCORE3_VDEC0_USER_CTI_BASE 0x67E6000ull
+#define DCORE3_VDEC0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_USER_CTI_SECTION 0x1000
+#define DCORE3_VDEC0_BMON_0_BASE 0x67E7000ull
+#define DCORE3_VDEC0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_BMON_0_SECTION 0x1000
+#define DCORE3_VDEC0_BMON_1_BASE 0x67E8000ull
+#define DCORE3_VDEC0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_BMON_1_SECTION 0x1000
+#define DCORE3_VDEC0_BMON_2_BASE 0x67E9000ull
+#define DCORE3_VDEC0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_BMON_2_SECTION 0x7000
+#define DCORE3_VDEC1_CS_ROM_TBL_BASE 0x67F0000ull
+#define DCORE3_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_CS_ROM_TBL_SECTION 0x1000
+#define DCORE3_VDEC1_CS_STM_BASE 0x67F1000ull
+#define DCORE3_VDEC1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_CS_STM_SECTION 0x1000
+#define DCORE3_VDEC1_CS_CTI_BASE 0x67F2000ull
+#define DCORE3_VDEC1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_CS_CTI_SECTION 0x1000
+#define DCORE3_VDEC1_CS_ETF_BASE 0x67F3000ull
+#define DCORE3_VDEC1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_CS_ETF_SECTION 0x1000
+#define DCORE3_VDEC1_CS_SPMU_BASE 0x67F4000ull
+#define DCORE3_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_CS_SPMU_SECTION 0x1000
+#define DCORE3_VDEC1_BMON_CTI_BASE 0x67F5000ull
+#define DCORE3_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_BMON_CTI_SECTION 0x1000
+#define DCORE3_VDEC1_USER_CTI_BASE 0x67F6000ull
+#define DCORE3_VDEC1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_USER_CTI_SECTION 0x1000
+#define DCORE3_VDEC1_BMON_0_BASE 0x67F7000ull
+#define DCORE3_VDEC1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_BMON_0_SECTION 0x1000
+#define DCORE3_VDEC1_BMON_1_BASE 0x67F8000ull
+#define DCORE3_VDEC1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_BMON_1_SECTION 0x1000
+#define DCORE3_VDEC1_BMON_2_BASE 0x67F9000ull
+#define DCORE3_VDEC1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_BMON_2_SECTION 0x7000
+#define CA53_BASE 0x6800000ull
+#define CA53_MAX_OFFSET 0x141000
+#define CA53_SECTION 0x400000
+#define PCI_ROM_TABLE_BASE 0x6C00000ull
+#define PCI_ROM_TABLE_MAX_OFFSET 0x1000
+#define PCI_ROM_TABLE_SECTION 0x1000
+#define PCIE_STM_BASE 0x6C01000ull
+#define PCIE_STM_MAX_OFFSET 0x1000
+#define PCIE_STM_SECTION 0x1000
+#define PCIE_ETF_BASE 0x6C02000ull
+#define PCIE_ETF_MAX_OFFSET 0x1000
+#define PCIE_ETF_SECTION 0x1000
+#define PCIE_CTI_0_BASE 0x6C03000ull
+#define PCIE_CTI_0_MAX_OFFSET 0x1000
+#define PCIE_CTI_0_SECTION 0x1000
+#define PCIE_SPMU_BASE 0x6C04000ull
+#define PCIE_SPMU_MAX_OFFSET 0x1000
+#define PCIE_SPMU_SECTION 0x1000
+#define PCIE_CTI_1_BASE 0x6C05000ull
+#define PCIE_CTI_1_MAX_OFFSET 0x1000
+#define PCIE_CTI_1_SECTION 0x2000
+#define PCIE_BMON_MSTR_WR_BASE 0x6C07000ull
+#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000
+#define PCIE_BMON_MSTR_WR_SECTION 0x1000
+#define PCIE_BMON_MSTR_RD_BASE 0x6C08000ull
+#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000
+#define PCIE_BMON_MSTR_RD_SECTION 0x1000
+#define PCIE_BMON_SLV_WR_BASE 0x6C09000ull
+#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000
+#define PCIE_BMON_SLV_WR_SECTION 0x1000
+#define PCIE_BMON_SLV_RD_BASE 0x6C0A000ull
+#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000
+#define PCIE_BMON_SLV_RD_SECTION 0x36000
+#define TOP_ROM_TABLE_BASE 0x6C40000ull
+#define TOP_ROM_TABLE_MAX_OFFSET 0x1000
+#define TOP_ROM_TABLE_SECTION 0x1000
+#define PSOC_CTI_BASE 0x6C41000ull
+#define PSOC_CTI_MAX_OFFSET 0x1000
+#define PSOC_CTI_SECTION 0x1000
+#define PSOC_STM_BASE 0x6C42000ull
+#define PSOC_STM_MAX_OFFSET 0x1000
+#define PSOC_STM_SECTION 0x1000
+#define PSOC_FUNNEL_BASE 0x6C43000ull
+#define PSOC_FUNNEL_MAX_OFFSET 0x1000
+#define PSOC_FUNNEL_SECTION 0x1000
+#define PSOC_ETR_BASE 0x6C44000ull
+#define PSOC_ETR_MAX_OFFSET 0x1000
+#define PSOC_ETR_SECTION 0x1000
+#define PSOC_ETF_BASE 0x6C45000ull
+#define PSOC_ETF_MAX_OFFSET 0x1000
+#define PSOC_ETF_SECTION 0x1000
+#define PSOC_TS_CTI_BASE 0x6C46000ull
+#define PSOC_TS_CTI_MAX_OFFSET 0x1000
+#define PSOC_TS_CTI_SECTION 0xA000
+#define PSOC_ARC0_CS_DBG_ROM_TBL_BASE 0x6C50000ull
+#define PSOC_ARC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define PSOC_ARC0_CS_STM_BASE 0x6C51000ull
+#define PSOC_ARC0_CS_STM_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CS_STM_SECTION 0x1000
+#define PSOC_ARC0_CS_CTI_BASE 0x6C52000ull
+#define PSOC_ARC0_CS_CTI_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CS_CTI_SECTION 0x1000
+#define PSOC_ARC0_CS_ETF_BASE 0x6C53000ull
+#define PSOC_ARC0_CS_ETF_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CS_ETF_SECTION 0x1000
+#define PSOC_ARC0_CS_SPMU_BASE 0x6C54000ull
+#define PSOC_ARC0_CS_SPMU_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CS_SPMU_SECTION 0x1000
+#define PSOC_ARC0_BMON_CTI_BASE 0x6C55000ull
+#define PSOC_ARC0_BMON_CTI_MAX_OFFSET 0x1000
+#define PSOC_ARC0_BMON_CTI_SECTION 0x1000
+#define PSOC_ARC0_USER_CTI_BASE 0x6C56000ull
+#define PSOC_ARC0_USER_CTI_MAX_OFFSET 0x1000
+#define PSOC_ARC0_USER_CTI_SECTION 0x1000
+#define PSOC_ARC0_BMON_0_BASE 0x6C57000ull
+#define PSOC_ARC0_BMON_0_MAX_OFFSET 0x1000
+#define PSOC_ARC0_BMON_0_SECTION 0x1000
+#define PSOC_ARC0_BMON_1_BASE 0x6C58000ull
+#define PSOC_ARC0_BMON_1_MAX_OFFSET 0x1000
+#define PSOC_ARC0_BMON_1_SECTION 0x6000
+#define PSOC_ARC0_RTT_BASE 0x6C5E000ull
+#define PSOC_ARC0_RTT_MAX_OFFSET 0x1400
+#define PSOC_ARC0_RTT_SECTION 0x1000
+#define PSOC_ARC0_FUNNEL_BASE 0x6C5F000ull
+#define PSOC_ARC0_FUNNEL_MAX_OFFSET 0x1000
+#define PSOC_ARC0_FUNNEL_SECTION 0x1000
+#define PSOC_ARC1_CS_DBG_ROM_TBL_BASE 0x6C60000ull
+#define PSOC_ARC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define PSOC_ARC1_CS_STM_BASE 0x6C61000ull
+#define PSOC_ARC1_CS_STM_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CS_STM_SECTION 0x1000
+#define PSOC_ARC1_CS_CTI_BASE 0x6C62000ull
+#define PSOC_ARC1_CS_CTI_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CS_CTI_SECTION 0x1000
+#define PSOC_ARC1_CS_ETF_BASE 0x6C63000ull
+#define PSOC_ARC1_CS_ETF_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CS_ETF_SECTION 0x1000
+#define PSOC_ARC1_CS_SPMU_BASE 0x6C64000ull
+#define PSOC_ARC1_CS_SPMU_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CS_SPMU_SECTION 0x1000
+#define PSOC_ARC1_BMON_CTI_BASE 0x6C65000ull
+#define PSOC_ARC1_BMON_CTI_MAX_OFFSET 0x1000
+#define PSOC_ARC1_BMON_CTI_SECTION 0x1000
+#define PSOC_ARC1_USER_CTI_BASE 0x6C66000ull
+#define PSOC_ARC1_USER_CTI_MAX_OFFSET 0x1000
+#define PSOC_ARC1_USER_CTI_SECTION 0x1000
+#define PSOC_ARC1_BMON_0_BASE 0x6C67000ull
+#define PSOC_ARC1_BMON_0_MAX_OFFSET 0x1000
+#define PSOC_ARC1_BMON_0_SECTION 0x1000
+#define PSOC_ARC1_BMON_1_BASE 0x6C68000ull
+#define PSOC_ARC1_BMON_1_MAX_OFFSET 0x1000
+#define PSOC_ARC1_BMON_1_SECTION 0x6000
+#define PSOC_ARC1_RTT_BASE 0x6C6E000ull
+#define PSOC_ARC1_RTT_MAX_OFFSET 0x1400
+#define PSOC_ARC1_RTT_SECTION 0x1000
+#define PSOC_ARC1_FUNNEL_BASE 0x6C6F000ull
+#define PSOC_ARC1_FUNNEL_MAX_OFFSET 0x1000
+#define PSOC_ARC1_FUNNEL_SECTION 0x1000
+#define PSOC_ARC0_CTI0_BASE 0x6C70000ull
+#define PSOC_ARC0_CTI0_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CTI0_SECTION 0x1000
+#define PSOC_ARC0_CTI1_BASE 0x6C71000ull
+#define PSOC_ARC0_CTI1_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CTI1_SECTION 0x1000
+#define PSOC_ARC0_CTI2_BASE 0x6C72000ull
+#define PSOC_ARC0_CTI2_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CTI2_SECTION 0x1000
+#define PSOC_ARC0_CTI3_BASE 0x6C73000ull
+#define PSOC_ARC0_CTI3_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CTI3_SECTION 0x1000
+#define PSOC_ARC1_CTI0_BASE 0x6C74000ull
+#define PSOC_ARC1_CTI0_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CTI0_SECTION 0x1000
+#define PSOC_ARC1_CTI1_BASE 0x6C75000ull
+#define PSOC_ARC1_CTI1_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CTI1_SECTION 0x1000
+#define PSOC_ARC1_CTI2_BASE 0x6C76000ull
+#define PSOC_ARC1_CTI2_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CTI2_SECTION 0x1000
+#define PSOC_ARC1_CTI3_BASE 0x6C77000ull
+#define PSOC_ARC1_CTI3_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CTI3_SECTION 0x9000
+#define PDMA0_CS_ROM_TBL_BASE 0x6C80000ull
+#define PDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define PDMA0_CS_ROM_TBL_SECTION 0x1000
+#define PDMA0_CS_STM_BASE 0x6C81000ull
+#define PDMA0_CS_STM_MAX_OFFSET 0x1000
+#define PDMA0_CS_STM_SECTION 0x1000
+#define PDMA0_CS_CTI_BASE 0x6C82000ull
+#define PDMA0_CS_CTI_MAX_OFFSET 0x1000
+#define PDMA0_CS_CTI_SECTION 0x1000
+#define PDMA0_CS_ETF_BASE 0x6C83000ull
+#define PDMA0_CS_ETF_MAX_OFFSET 0x1000
+#define PDMA0_CS_ETF_SECTION 0x1000
+#define PDMA0_CS_SPMU_BASE 0x6C84000ull
+#define PDMA0_CS_SPMU_MAX_OFFSET 0x1000
+#define PDMA0_CS_SPMU_SECTION 0x1000
+#define PDMA0_BMON_CTI_BASE 0x6C85000ull
+#define PDMA0_BMON_CTI_MAX_OFFSET 0x1000
+#define PDMA0_BMON_CTI_SECTION 0x1000
+#define PDMA0_USER_CTI_BASE 0x6C86000ull
+#define PDMA0_USER_CTI_MAX_OFFSET 0x1000
+#define PDMA0_USER_CTI_SECTION 0x1000
+#define PDMA0_BMON_0_BASE 0x6C87000ull
+#define PDMA0_BMON_0_MAX_OFFSET 0x1000
+#define PDMA0_BMON_0_SECTION 0x1000
+#define PDMA0_BMON_1_BASE 0x6C88000ull
+#define PDMA0_BMON_1_MAX_OFFSET 0x1000
+#define PDMA0_BMON_1_SECTION 0x1000
+#define PDMA0_QM_ARC_RTT_BASE 0x6C89000ull
+#define PDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define PDMA0_QM_ARC_RTT_SECTION 0x7000
+#define PDMA1_CS_ROM_TBL_BASE 0x6C90000ull
+#define PDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define PDMA1_CS_ROM_TBL_SECTION 0x1000
+#define PDMA1_CS_STM_BASE 0x6C91000ull
+#define PDMA1_CS_STM_MAX_OFFSET 0x1000
+#define PDMA1_CS_STM_SECTION 0x1000
+#define PDMA1_CS_CTI_BASE 0x6C92000ull
+#define PDMA1_CS_CTI_MAX_OFFSET 0x1000
+#define PDMA1_CS_CTI_SECTION 0x1000
+#define PDMA1_CS_ETF_BASE 0x6C93000ull
+#define PDMA1_CS_ETF_MAX_OFFSET 0x1000
+#define PDMA1_CS_ETF_SECTION 0x1000
+#define PDMA1_CS_SPMU_BASE 0x6C94000ull
+#define PDMA1_CS_SPMU_MAX_OFFSET 0x1000
+#define PDMA1_CS_SPMU_SECTION 0x1000
+#define PDMA1_BMON_CTI_BASE 0x6C95000ull
+#define PDMA1_BMON_CTI_MAX_OFFSET 0x1000
+#define PDMA1_BMON_CTI_SECTION 0x1000
+#define PDMA1_USER_CTI_BASE 0x6C96000ull
+#define PDMA1_USER_CTI_MAX_OFFSET 0x1000
+#define PDMA1_USER_CTI_SECTION 0x1000
+#define PDMA1_BMON_0_BASE 0x6C97000ull
+#define PDMA1_BMON_0_MAX_OFFSET 0x1000
+#define PDMA1_BMON_0_SECTION 0x1000
+#define PDMA1_BMON_1_BASE 0x6C98000ull
+#define PDMA1_BMON_1_MAX_OFFSET 0x1000
+#define PDMA1_BMON_1_SECTION 0x1000
+#define PDMA1_QM_ARC_RTT_BASE 0x6C99000ull
+#define PDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define PDMA1_QM_ARC_RTT_SECTION 0x7000
+#define XDMA_FUNNEL_BASE 0x6CA0000ull
+#define XDMA_FUNNEL_MAX_OFFSET 0x1000
+#define XDMA_FUNNEL_SECTION 0x21000
+#define CPU_ETF_0_BASE 0x6CC1000ull
+#define CPU_ETF_0_MAX_OFFSET 0x1000
+#define CPU_ETF_0_SECTION 0x1000
+#define CPU_ETF_1_BASE 0x6CC2000ull
+#define CPU_ETF_1_MAX_OFFSET 0x1000
+#define CPU_ETF_1_SECTION 0x2000
+#define CPU_CTI_BASE 0x6CC4000ull
+#define CPU_CTI_MAX_OFFSET 0x1000
+#define CPU_CTI_SECTION 0x1000
+#define CPU_FUNNEL_BASE 0x6CC5000ull
+#define CPU_FUNNEL_MAX_OFFSET 0x1000
+#define CPU_FUNNEL_SECTION 0x1000
+#define CPU_STM_BASE 0x6CC6000ull
+#define CPU_STM_MAX_OFFSET 0x1000
+#define CPU_STM_SECTION 0x1000
+#define CPU_CTI_TRACE_BASE 0x6CC7000ull
+#define CPU_CTI_TRACE_MAX_OFFSET 0x1000
+#define CPU_CTI_TRACE_SECTION 0x1000
+#define CPU_ETF_TRACE_BASE 0x6CC8000ull
+#define CPU_ETF_TRACE_MAX_OFFSET 0x1000
+#define CPU_ETF_TRACE_SECTION 0x1000
+#define CPU_WR_BMON_BASE 0x6CC9000ull
+#define CPU_WR_BMON_MAX_OFFSET 0x1000
+#define CPU_WR_BMON_SECTION 0x1000
+#define CPU_RD_BMON_BASE 0x6CCA000ull
+#define CPU_RD_BMON_MAX_OFFSET 0x1000
+#define CPU_RD_BMON_SECTION 0x36000
+#define PMMU_CS_DBG_ROM_TBL_BASE 0x6D00000ull
+#define PMMU_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define PMMU_CS_DBG_ROM_TBL_SECTION 0x1000
+#define PMMU_CS_STM_BASE 0x6D01000ull
+#define PMMU_CS_STM_MAX_OFFSET 0x1000
+#define PMMU_CS_STM_SECTION 0x1000
+#define PMMU_CS_CTI_BASE 0x6D02000ull
+#define PMMU_CS_CTI_MAX_OFFSET 0x1000
+#define PMMU_CS_CTI_SECTION 0x1000
+#define PMMU_CS_ETF_BASE 0x6D03000ull
+#define PMMU_CS_ETF_MAX_OFFSET 0x1000
+#define PMMU_CS_ETF_SECTION 0x1000
+#define PMMU_CS_SPMU_BASE 0x6D04000ull
+#define PMMU_CS_SPMU_MAX_OFFSET 0x1000
+#define PMMU_CS_SPMU_SECTION 0x1000
+#define PMMU_BMON_CTI_BASE 0x6D05000ull
+#define PMMU_BMON_CTI_MAX_OFFSET 0x1000
+#define PMMU_BMON_CTI_SECTION 0x1000
+#define PMMU_USER_CTI_BASE 0x6D06000ull
+#define PMMU_USER_CTI_MAX_OFFSET 0x1000
+#define PMMU_USER_CTI_SECTION 0x1000
+#define PMMU_BMON_0_BASE 0x6D07000ull
+#define PMMU_BMON_0_MAX_OFFSET 0x1000
+#define PMMU_BMON_0_SECTION 0x1000
+#define PMMU_BMON_1_BASE 0x6D08000ull
+#define PMMU_BMON_1_MAX_OFFSET 0x1000
+#define PMMU_BMON_1_SECTION 0x1000
+#define PMMU_BMON_2_BASE 0x6D09000ull
+#define PMMU_BMON_2_MAX_OFFSET 0x1000
+#define PMMU_BMON_2_SECTION 0x1000
+#define PMMU_BMON_3_BASE 0x6D0A000ull
+#define PMMU_BMON_3_MAX_OFFSET 0x1000
+#define PMMU_BMON_3_SECTION 0x1000
+#define PMMU_BMON_4_BASE 0x6D0B000ull
+#define PMMU_BMON_4_MAX_OFFSET 0x1000
+#define PMMU_BMON_4_SECTION 0x1000
+#define PMMU_FUNNEL_BASE 0x6D0C000ull
+#define PMMU_FUNNEL_MAX_OFFSET 0x1000
+#define PMMU_FUNNEL_SECTION 0x1000
+#define PMMU_FUNNEL_DEC_BASE 0x6D0D000ull
+#define PMMU_FUNNEL_DEC_MAX_OFFSET 0x1000
+#define PMMU_FUNNEL_DEC_SECTION 0x33000
+#define DCORE0_XBAR_MID_FUNNEL_BASE 0x6D40000ull
+#define DCORE0_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_XBAR_MID_FUNNEL_SECTION 0x8000
+#define DCORE0_XBAR_EDGE_FUNNEL_BASE 0x6D48000ull
+#define DCORE0_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_XBAR_EDGE_FUNNEL_SECTION 0x8000
+#define DCORE1_XBAR_MID_FUNNEL_BASE 0x6D50000ull
+#define DCORE1_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_XBAR_MID_FUNNEL_SECTION 0x8000
+#define DCORE1_XBAR_EDGE_FUNNEL_BASE 0x6D58000ull
+#define DCORE1_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_XBAR_EDGE_FUNNEL_SECTION 0x8000
+#define DCORE2_XBAR_MID_FUNNEL_BASE 0x6D60000ull
+#define DCORE2_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_XBAR_MID_FUNNEL_SECTION 0x8000
+#define DCORE2_XBAR_EDGE_FUNNEL_BASE 0x6D68000ull
+#define DCORE2_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_XBAR_EDGE_FUNNEL_SECTION 0x8000
+#define DCORE3_XBAR_MID_FUNNEL_BASE 0x6D70000ull
+#define DCORE3_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_XBAR_MID_FUNNEL_SECTION 0x8000
+#define DCORE3_XBAR_EDGE_FUNNEL_BASE 0x6D78000ull
+#define DCORE3_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_XBAR_EDGE_FUNNEL_SECTION 0x88000
+#define ROT0_CS_ROM_TBL_BASE 0x6E00000ull
+#define ROT0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define ROT0_CS_ROM_TBL_SECTION 0x1000
+#define ROT0_CS_STM_BASE 0x6E01000ull
+#define ROT0_CS_STM_MAX_OFFSET 0x1000
+#define ROT0_CS_STM_SECTION 0x1000
+#define ROT0_CS_CTI_BASE 0x6E02000ull
+#define ROT0_CS_CTI_MAX_OFFSET 0x1000
+#define ROT0_CS_CTI_SECTION 0x1000
+#define ROT0_CS_ETF_BASE 0x6E03000ull
+#define ROT0_CS_ETF_MAX_OFFSET 0x1000
+#define ROT0_CS_ETF_SECTION 0x1000
+#define ROT0_CS_SPMU_BASE 0x6E04000ull
+#define ROT0_CS_SPMU_MAX_OFFSET 0x1000
+#define ROT0_CS_SPMU_SECTION 0x1000
+#define ROT0_BMON_CTI_BASE 0x6E05000ull
+#define ROT0_BMON_CTI_MAX_OFFSET 0x1000
+#define ROT0_BMON_CTI_SECTION 0x1000
+#define ROT0_USER_CTI_BASE 0x6E06000ull
+#define ROT0_USER_CTI_MAX_OFFSET 0x1000
+#define ROT0_USER_CTI_SECTION 0x1000
+#define ROT0_BMON_0_BASE 0x6E07000ull
+#define ROT0_BMON_0_MAX_OFFSET 0x1000
+#define ROT0_BMON_0_SECTION 0x1000
+#define ROT0_BMON_1_BASE 0x6E08000ull
+#define ROT0_BMON_1_MAX_OFFSET 0x1000
+#define ROT0_BMON_1_SECTION 0x1000
+#define ROT0_BMON_2_BASE 0x6E09000ull
+#define ROT0_BMON_2_MAX_OFFSET 0x1000
+#define ROT0_BMON_2_SECTION 0x1000
+#define ROT0_BMON_3_BASE 0x6E0A000ull
+#define ROT0_BMON_3_MAX_OFFSET 0x1000
+#define ROT0_BMON_3_SECTION 0x1000
+#define ROT0_ARC_RTT_BASE 0x6E0B000ull
+#define ROT0_ARC_RTT_MAX_OFFSET 0x1400
+#define ROT0_ARC_RTT_SECTION 0x5000
+#define ROT1_CS_ROM_TBL_BASE 0x6E10000ull
+#define ROT1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define ROT1_CS_ROM_TBL_SECTION 0x1000
+#define ROT1_CS_STM_BASE 0x6E11000ull
+#define ROT1_CS_STM_MAX_OFFSET 0x1000
+#define ROT1_CS_STM_SECTION 0x1000
+#define ROT1_CS_CTI_BASE 0x6E12000ull
+#define ROT1_CS_CTI_MAX_OFFSET 0x1000
+#define ROT1_CS_CTI_SECTION 0x1000
+#define ROT1_CS_ETF_BASE 0x6E13000ull
+#define ROT1_CS_ETF_MAX_OFFSET 0x1000
+#define ROT1_CS_ETF_SECTION 0x1000
+#define ROT1_CS_SPMU_BASE 0x6E14000ull
+#define ROT1_CS_SPMU_MAX_OFFSET 0x1000
+#define ROT1_CS_SPMU_SECTION 0x1000
+#define ROT1_BMON_CTI_BASE 0x6E15000ull
+#define ROT1_BMON_CTI_MAX_OFFSET 0x1000
+#define ROT1_BMON_CTI_SECTION 0x1000
+#define ROT1_USER_CTI_BASE 0x6E16000ull
+#define ROT1_USER_CTI_MAX_OFFSET 0x1000
+#define ROT1_USER_CTI_SECTION 0x1000
+#define ROT1_BMON_0_BASE 0x6E17000ull
+#define ROT1_BMON_0_MAX_OFFSET 0x1000
+#define ROT1_BMON_0_SECTION 0x1000
+#define ROT1_BMON_1_BASE 0x6E18000ull
+#define ROT1_BMON_1_MAX_OFFSET 0x1000
+#define ROT1_BMON_1_SECTION 0x1000
+#define ROT1_BMON_2_BASE 0x6E19000ull
+#define ROT1_BMON_2_MAX_OFFSET 0x1000
+#define ROT1_BMON_2_SECTION 0x1000
+#define ROT1_BMON_3_BASE 0x6E1A000ull
+#define ROT1_BMON_3_MAX_OFFSET 0x1000
+#define ROT1_BMON_3_SECTION 0x1000
+#define ROT1_ARC_RTT_BASE 0x6E1B000ull
+#define ROT1_ARC_RTT_MAX_OFFSET 0x1400
+#define ROT1_ARC_RTT_SECTION 0x65000
+#define ARC_FARM_ARC0_RTT_BASE 0x6E80000ull
+#define ARC_FARM_ARC0_RTT_MAX_OFFSET 0x1400
+#define ARC_FARM_ARC0_RTT_SECTION 0x1000
+#define ARC_FARM_ARC1_RTT_BASE 0x6E81000ull
+#define ARC_FARM_ARC1_RTT_MAX_OFFSET 0x1400
+#define ARC_FARM_ARC1_RTT_SECTION 0x1000
+#define ARC_FARM_ARC2_RTT_BASE 0x6E82000ull
+#define ARC_FARM_ARC2_RTT_MAX_OFFSET 0x1400
+#define ARC_FARM_ARC2_RTT_SECTION 0x1000
+#define ARC_FARM_ARC3_RTT_BASE 0x6E83000ull
+#define ARC_FARM_ARC3_RTT_MAX_OFFSET 0x1400
+#define ARC_FARM_ARC3_RTT_SECTION 0xD000
+#define ARC_FARM_CS_ROM_TBL_BASE 0x6E90000ull
+#define ARC_FARM_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define ARC_FARM_CS_ROM_TBL_SECTION 0x1000
+#define ARC_FARM_CS_STM_BASE 0x6E91000ull
+#define ARC_FARM_CS_STM_MAX_OFFSET 0x1000
+#define ARC_FARM_CS_STM_SECTION 0x1000
+#define ARC_FARM_CS_CTI_BASE 0x6E92000ull
+#define ARC_FARM_CS_CTI_MAX_OFFSET 0x1000
+#define ARC_FARM_CS_CTI_SECTION 0x1000
+#define ARC_FARM_CS_ETF_BASE 0x6E93000ull
+#define ARC_FARM_CS_ETF_MAX_OFFSET 0x1000
+#define ARC_FARM_CS_ETF_SECTION 0x1000
+#define ARC_FARM_CS_SPMU_BASE 0x6E94000ull
+#define ARC_FARM_CS_SPMU_MAX_OFFSET 0x1000
+#define ARC_FARM_CS_SPMU_SECTION 0x1000
+#define ARC_FARM_BMON_CTI_BASE 0x6E95000ull
+#define ARC_FARM_BMON_CTI_MAX_OFFSET 0x1000
+#define ARC_FARM_BMON_CTI_SECTION 0x1000
+#define ARC_FARM_USER_CTI_BASE 0x6E96000ull
+#define ARC_FARM_USER_CTI_MAX_OFFSET 0x1000
+#define ARC_FARM_USER_CTI_SECTION 0x1000
+#define ARC_FARM_BMON_0_BASE 0x6E97000ull
+#define ARC_FARM_BMON_0_MAX_OFFSET 0x1000
+#define ARC_FARM_BMON_0_SECTION 0x1000
+#define ARC_FARM_BMON_1_BASE 0x6E98000ull
+#define ARC_FARM_BMON_1_MAX_OFFSET 0x1000
+#define ARC_FARM_BMON_1_SECTION 0x1000
+#define ARC_FARM_BMON_2_BASE 0x6E99000ull
+#define ARC_FARM_BMON_2_MAX_OFFSET 0x1000
+#define ARC_FARM_BMON_2_SECTION 0x1000
+#define ARC_FARM_BMON_3_BASE 0x6E9A000ull
+#define ARC_FARM_BMON_3_MAX_OFFSET 0x1000
+#define ARC_FARM_BMON_3_SECTION 0x1000
+#define ARC_FARM_CTI_BASE 0x6E9B000ull
+#define ARC_FARM_CTI_MAX_OFFSET 0x1000
+#define ARC_FARM_CTI_SECTION 0x1000
+#define ARC_FARM_FUNNEL_BASE 0x6E9C000ull
+#define ARC_FARM_FUNNEL_MAX_OFFSET 0x1000
+#define ARC_FARM_FUNNEL_SECTION 0x4000
+#define KDMA_CS_ROM_TBL_BASE 0x6EA0000ull
+#define KDMA_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define KDMA_CS_ROM_TBL_SECTION 0x1000
+#define KDMA_CS_STM_BASE 0x6EA1000ull
+#define KDMA_CS_STM_MAX_OFFSET 0x1000
+#define KDMA_CS_STM_SECTION 0x1000
+#define KDMA_CS_CTI_BASE 0x6EA2000ull
+#define KDMA_CS_CTI_MAX_OFFSET 0x1000
+#define KDMA_CS_CTI_SECTION 0x1000
+#define KDMA_CS_ETF_BASE 0x6EA3000ull
+#define KDMA_CS_ETF_MAX_OFFSET 0x1000
+#define KDMA_CS_ETF_SECTION 0x1000
+#define KDMA_CS_SPMU_BASE 0x6EA4000ull
+#define KDMA_CS_SPMU_MAX_OFFSET 0x1000
+#define KDMA_CS_SPMU_SECTION 0x1000
+#define KDMA_BMON_CTI_BASE 0x6EA5000ull
+#define KDMA_BMON_CTI_MAX_OFFSET 0x1000
+#define KDMA_BMON_CTI_SECTION 0x1000
+#define KDMA_USER_CTI_BASE 0x6EA6000ull
+#define KDMA_USER_CTI_MAX_OFFSET 0x1000
+#define KDMA_USER_CTI_SECTION 0x1000
+#define KDMA_BMON_0_BASE 0x6EA7000ull
+#define KDMA_BMON_0_MAX_OFFSET 0x1000
+#define KDMA_BMON_0_SECTION 0x1000
+#define KDMA_BMON_1_BASE 0x6EA8000ull
+#define KDMA_BMON_1_MAX_OFFSET 0x1000
+#define KDMA_BMON_1_SECTION 0x1000
+#define KDMA_BMON_2_BASE 0x6EA9000ull
+#define KDMA_BMON_2_MAX_OFFSET 0x1000
+#define KDMA_BMON_2_SECTION 0x1000
+#define KDMA_BMON_3_BASE 0x6EAA000ull
+#define KDMA_BMON_3_MAX_OFFSET 0x1000
+#define KDMA_BMON_3_SECTION 0x56000
+#define PCIE_VDEC0_CS_DBG_ROM_TBL_BASE 0x6F00000ull
+#define PCIE_VDEC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define PCIE_VDEC0_CS_STM_BASE 0x6F01000ull
+#define PCIE_VDEC0_CS_STM_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_CS_STM_SECTION 0x1000
+#define PCIE_VDEC0_CS_CTI_BASE 0x6F02000ull
+#define PCIE_VDEC0_CS_CTI_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_CS_CTI_SECTION 0x1000
+#define PCIE_VDEC0_CS_ETF_BASE 0x6F03000ull
+#define PCIE_VDEC0_CS_ETF_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_CS_ETF_SECTION 0x1000
+#define PCIE_VDEC0_CS_SPMU_BASE 0x6F04000ull
+#define PCIE_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_CS_SPMU_SECTION 0x1000
+#define PCIE_VDEC0_BMON_CTI_BASE 0x6F05000ull
+#define PCIE_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_BMON_CTI_SECTION 0x1000
+#define PCIE_VDEC0_USER_CTI_BASE 0x6F06000ull
+#define PCIE_VDEC0_USER_CTI_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_USER_CTI_SECTION 0x1000
+#define PCIE_VDEC0_BMON_0_BASE 0x6F07000ull
+#define PCIE_VDEC0_BMON_0_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_BMON_0_SECTION 0x1000
+#define PCIE_VDEC0_BMON_1_BASE 0x6F08000ull
+#define PCIE_VDEC0_BMON_1_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_BMON_1_SECTION 0x1000
+#define PCIE_VDEC0_BMON_2_BASE 0x6F09000ull
+#define PCIE_VDEC0_BMON_2_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_BMON_2_SECTION 0x7000
+#define PCIE_VDEC1_CS_DBG_ROM_TBL_BASE 0x6F10000ull
+#define PCIE_VDEC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define PCIE_VDEC1_CS_STM_BASE 0x6F11000ull
+#define PCIE_VDEC1_CS_STM_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_CS_STM_SECTION 0x1000
+#define PCIE_VDEC1_CS_CTI_BASE 0x6F12000ull
+#define PCIE_VDEC1_CS_CTI_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_CS_CTI_SECTION 0x1000
+#define PCIE_VDEC1_CS_ETF_BASE 0x6F13000ull
+#define PCIE_VDEC1_CS_ETF_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_CS_ETF_SECTION 0x1000
+#define PCIE_VDEC1_CS_SPMU_BASE 0x6F14000ull
+#define PCIE_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_CS_SPMU_SECTION 0x1000
+#define PCIE_VDEC1_BMON_CTI_BASE 0x6F15000ull
+#define PCIE_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_BMON_CTI_SECTION 0x1000
+#define PCIE_VDEC1_USER_CTI_BASE 0x6F16000ull
+#define PCIE_VDEC1_USER_CTI_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_USER_CTI_SECTION 0x1000
+#define PCIE_VDEC1_BMON_0_BASE 0x6F17000ull
+#define PCIE_VDEC1_BMON_0_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_BMON_0_SECTION 0x1000
+#define PCIE_VDEC1_BMON_1_BASE 0x6F18000ull
+#define PCIE_VDEC1_BMON_1_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_BMON_1_SECTION 0x1000
+#define PCIE_VDEC1_BMON_2_BASE 0x6F19000ull
+#define PCIE_VDEC1_BMON_2_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_BMON_2_SECTION 0xF7000
+#define HBM0_MC0_CS_DBG_ROM_TBL_BASE 0x7010000ull
+#define HBM0_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM0_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define HBM0_MC0_CS_STM_BASE 0x7011000ull
+#define HBM0_MC0_CS_STM_MAX_OFFSET 0x1000
+#define HBM0_MC0_CS_STM_SECTION 0x1000
+#define HBM0_MC0_CS_CTI_BASE 0x7012000ull
+#define HBM0_MC0_CS_CTI_MAX_OFFSET 0x1000
+#define HBM0_MC0_CS_CTI_SECTION 0x1000
+#define HBM0_MC0_CS_ETF_BASE 0x7013000ull
+#define HBM0_MC0_CS_ETF_MAX_OFFSET 0x1000
+#define HBM0_MC0_CS_ETF_SECTION 0x1000
+#define HBM0_MC0_CS_SPMU_BASE 0x7014000ull
+#define HBM0_MC0_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM0_MC0_CS_SPMU_SECTION 0x1000
+#define HBM0_MC0_BMON_CTI_BASE 0x7015000ull
+#define HBM0_MC0_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM0_MC0_BMON_CTI_SECTION 0x1000
+#define HBM0_MC0_USER_CTI_BASE 0x7016000ull
+#define HBM0_MC0_USER_CTI_MAX_OFFSET 0x1000
+#define HBM0_MC0_USER_CTI_SECTION 0xA000
+#define HBM0_MC0_FUNNEL_BASE 0x7020000ull
+#define HBM0_MC0_FUNNEL_MAX_OFFSET 0x1000
+#define HBM0_MC0_FUNNEL_SECTION 0x30000
+#define HBM0_MC1_CS_DBG_ROM_TBL_BASE 0x7050000ull
+#define HBM0_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM0_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define HBM0_MC1_CS_STM_BASE 0x7051000ull
+#define HBM0_MC1_CS_STM_MAX_OFFSET 0x1000
+#define HBM0_MC1_CS_STM_SECTION 0x1000
+#define HBM0_MC1_CS_CTI_BASE 0x7052000ull
+#define HBM0_MC1_CS_CTI_MAX_OFFSET 0x1000
+#define HBM0_MC1_CS_CTI_SECTION 0x1000
+#define HBM0_MC1_CS_ETF_BASE 0x7053000ull
+#define HBM0_MC1_CS_ETF_MAX_OFFSET 0x1000
+#define HBM0_MC1_CS_ETF_SECTION 0x1000
+#define HBM0_MC1_CS_SPMU_BASE 0x7054000ull
+#define HBM0_MC1_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM0_MC1_CS_SPMU_SECTION 0x1000
+#define HBM0_MC1_BMON_CTI_BASE 0x7055000ull
+#define HBM0_MC1_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM0_MC1_BMON_CTI_SECTION 0x1000
+#define HBM0_MC1_USER_CTI_BASE 0x7056000ull
+#define HBM0_MC1_USER_CTI_MAX_OFFSET 0x1000
+#define HBM0_MC1_USER_CTI_SECTION 0xA000
+#define HBM0_MC1_FUNNEL_BASE 0x7060000ull
+#define HBM0_MC1_FUNNEL_MAX_OFFSET 0x1000
+#define HBM0_MC1_FUNNEL_SECTION 0x30000
+#define HBM1_MC0_CS_DBG_ROM_TBL_BASE 0x7090000ull
+#define HBM1_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM1_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define HBM1_MC0_CS_STM_BASE 0x7091000ull
+#define HBM1_MC0_CS_STM_MAX_OFFSET 0x1000
+#define HBM1_MC0_CS_STM_SECTION 0x1000
+#define HBM1_MC0_CS_CTI_BASE 0x7092000ull
+#define HBM1_MC0_CS_CTI_MAX_OFFSET 0x1000
+#define HBM1_MC0_CS_CTI_SECTION 0x1000
+#define HBM1_MC0_CS_ETF_BASE 0x7093000ull
+#define HBM1_MC0_CS_ETF_MAX_OFFSET 0x1000
+#define HBM1_MC0_CS_ETF_SECTION 0x1000
+#define HBM1_MC0_CS_SPMU_BASE 0x7094000ull
+#define HBM1_MC0_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM1_MC0_CS_SPMU_SECTION 0x1000
+#define HBM1_MC0_BMON_CTI_BASE 0x7095000ull
+#define HBM1_MC0_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM1_MC0_BMON_CTI_SECTION 0x1000
+#define HBM1_MC0_USER_CTI_BASE 0x7096000ull
+#define HBM1_MC0_USER_CTI_MAX_OFFSET 0x1000
+#define HBM1_MC0_USER_CTI_SECTION 0xA000
+#define HBM1_MC0_FUNNEL_BASE 0x70A0000ull
+#define HBM1_MC0_FUNNEL_MAX_OFFSET 0x1000
+#define HBM1_MC0_FUNNEL_SECTION 0x30000
+#define HBM1_MC1_CS_DBG_ROM_TBL_BASE 0x70D0000ull
+#define HBM1_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM1_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define HBM1_MC1_CS_STM_BASE 0x70D1000ull
+#define HBM1_MC1_CS_STM_MAX_OFFSET 0x1000
+#define HBM1_MC1_CS_STM_SECTION 0x1000
+#define HBM1_MC1_CS_CTI_BASE 0x70D2000ull
+#define HBM1_MC1_CS_CTI_MAX_OFFSET 0x1000
+#define HBM1_MC1_CS_CTI_SECTION 0x1000
+#define HBM1_MC1_CS_ETF_BASE 0x70D3000ull
+#define HBM1_MC1_CS_ETF_MAX_OFFSET 0x1000
+#define HBM1_MC1_CS_ETF_SECTION 0x1000
+#define HBM1_MC1_CS_SPMU_BASE 0x70D4000ull
+#define HBM1_MC1_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM1_MC1_CS_SPMU_SECTION 0x1000
+#define HBM1_MC1_BMON_CTI_BASE 0x70D5000ull
+#define HBM1_MC1_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM1_MC1_BMON_CTI_SECTION 0x1000
+#define HBM1_MC1_USER_CTI_BASE 0x70D6000ull
+#define HBM1_MC1_USER_CTI_MAX_OFFSET 0x1000
+#define HBM1_MC1_USER_CTI_SECTION 0xA000
+#define HBM1_MC1_FUNNEL_BASE 0x70E0000ull
+#define HBM1_MC1_FUNNEL_MAX_OFFSET 0x1000
+#define HBM1_MC1_FUNNEL_SECTION 0x30000
+#define HBM2_MC0_CS_DBG_ROM_TBL_BASE 0x7110000ull
+#define HBM2_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM2_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define HBM2_MC0_CS_STM_BASE 0x7111000ull
+#define HBM2_MC0_CS_STM_MAX_OFFSET 0x1000
+#define HBM2_MC0_CS_STM_SECTION 0x1000
+#define HBM2_MC0_CS_CTI_BASE 0x7112000ull
+#define HBM2_MC0_CS_CTI_MAX_OFFSET 0x1000
+#define HBM2_MC0_CS_CTI_SECTION 0x1000
+#define HBM2_MC0_CS_ETF_BASE 0x7113000ull
+#define HBM2_MC0_CS_ETF_MAX_OFFSET 0x1000
+#define HBM2_MC0_CS_ETF_SECTION 0x1000
+#define HBM2_MC0_CS_SPMU_BASE 0x7114000ull
+#define HBM2_MC0_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM2_MC0_CS_SPMU_SECTION 0x1000
+#define HBM2_MC0_BMON_CTI_BASE 0x7115000ull
+#define HBM2_MC0_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM2_MC0_BMON_CTI_SECTION 0x1000
+#define HBM2_MC0_USER_CTI_BASE 0x7116000ull
+#define HBM2_MC0_USER_CTI_MAX_OFFSET 0x1000
+#define HBM2_MC0_USER_CTI_SECTION 0xA000
+#define HBM2_MC0_FUNNEL_BASE 0x7120000ull
+#define HBM2_MC0_FUNNEL_MAX_OFFSET 0x1000
+#define HBM2_MC0_FUNNEL_SECTION 0x30000
+#define HBM2_MC1_CS_DBG_ROM_TBL_BASE 0x7150000ull
+#define HBM2_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM2_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define HBM2_MC1_CS_STM_BASE 0x7151000ull
+#define HBM2_MC1_CS_STM_MAX_OFFSET 0x1000
+#define HBM2_MC1_CS_STM_SECTION 0x1000
+#define HBM2_MC1_CS_CTI_BASE 0x7152000ull
+#define HBM2_MC1_CS_CTI_MAX_OFFSET 0x1000
+#define HBM2_MC1_CS_CTI_SECTION 0x1000
+#define HBM2_MC1_CS_ETF_BASE 0x7153000ull
+#define HBM2_MC1_CS_ETF_MAX_OFFSET 0x1000
+#define HBM2_MC1_CS_ETF_SECTION 0x1000
+#define HBM2_MC1_CS_SPMU_BASE 0x7154000ull
+#define HBM2_MC1_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM2_MC1_CS_SPMU_SECTION 0x1000
+#define HBM2_MC1_BMON_CTI_BASE 0x7155000ull
+#define HBM2_MC1_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM2_MC1_BMON_CTI_SECTION 0x1000
+#define HBM2_MC1_USER_CTI_BASE 0x7156000ull
+#define HBM2_MC1_USER_CTI_MAX_OFFSET 0x1000
+#define HBM2_MC1_USER_CTI_SECTION 0xA000
+#define HBM2_MC1_FUNNEL_BASE 0x7160000ull
+#define HBM2_MC1_FUNNEL_MAX_OFFSET 0x1000
+#define HBM2_MC1_FUNNEL_SECTION 0x30000
+#define HBM3_MC0_CS_DBG_ROM_TBL_BASE 0x7190000ull
+#define HBM3_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM3_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define HBM3_MC0_CS_STM_BASE 0x7191000ull
+#define HBM3_MC0_CS_STM_MAX_OFFSET 0x1000
+#define HBM3_MC0_CS_STM_SECTION 0x1000
+#define HBM3_MC0_CS_CTI_BASE 0x7192000ull
+#define HBM3_MC0_CS_CTI_MAX_OFFSET 0x1000
+#define HBM3_MC0_CS_CTI_SECTION 0x1000
+#define HBM3_MC0_CS_ETF_BASE 0x7193000ull
+#define HBM3_MC0_CS_ETF_MAX_OFFSET 0x1000
+#define HBM3_MC0_CS_ETF_SECTION 0x1000
+#define HBM3_MC0_CS_SPMU_BASE 0x7194000ull
+#define HBM3_MC0_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM3_MC0_CS_SPMU_SECTION 0x1000
+#define HBM3_MC0_BMON_CTI_BASE 0x7195000ull
+#define HBM3_MC0_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM3_MC0_BMON_CTI_SECTION 0x1000
+#define HBM3_MC0_USER_CTI_BASE 0x7196000ull
+#define HBM3_MC0_USER_CTI_MAX_OFFSET 0x1000
+#define HBM3_MC0_USER_CTI_SECTION 0xA000
+#define HBM3_MC0_FUNNEL_BASE 0x71A0000ull
+#define HBM3_MC0_FUNNEL_MAX_OFFSET 0x1000
+#define HBM3_MC0_FUNNEL_SECTION 0x30000
+#define HBM3_MC1_CS_DBG_ROM_TBL_BASE 0x71D0000ull
+#define HBM3_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM3_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define HBM3_MC1_CS_STM_BASE 0x71D1000ull
+#define HBM3_MC1_CS_STM_MAX_OFFSET 0x1000
+#define HBM3_MC1_CS_STM_SECTION 0x1000
+#define HBM3_MC1_CS_CTI_BASE 0x71D2000ull
+#define HBM3_MC1_CS_CTI_MAX_OFFSET 0x1000
+#define HBM3_MC1_CS_CTI_SECTION 0x1000
+#define HBM3_MC1_CS_ETF_BASE 0x71D3000ull
+#define HBM3_MC1_CS_ETF_MAX_OFFSET 0x1000
+#define HBM3_MC1_CS_ETF_SECTION 0x1000
+#define HBM3_MC1_CS_SPMU_BASE 0x71D4000ull
+#define HBM3_MC1_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM3_MC1_CS_SPMU_SECTION 0x1000
+#define HBM3_MC1_BMON_CTI_BASE 0x71D5000ull
+#define HBM3_MC1_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM3_MC1_BMON_CTI_SECTION 0x1000
+#define HBM3_MC1_USER_CTI_BASE 0x71D6000ull
+#define HBM3_MC1_USER_CTI_MAX_OFFSET 0x1000
+#define HBM3_MC1_USER_CTI_SECTION 0xA000
+#define HBM3_MC1_FUNNEL_BASE 0x71E0000ull
+#define HBM3_MC1_FUNNEL_MAX_OFFSET 0x1000
+#define HBM3_MC1_FUNNEL_SECTION 0x30000
+#define HBM4_MC0_CS_DBG_ROM_TBL_BASE 0x7210000ull
+#define HBM4_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM4_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define HBM4_MC0_CS_STM_BASE 0x7211000ull
+#define HBM4_MC0_CS_STM_MAX_OFFSET 0x1000
+#define HBM4_MC0_CS_STM_SECTION 0x1000
+#define HBM4_MC0_CS_CTI_BASE 0x7212000ull
+#define HBM4_MC0_CS_CTI_MAX_OFFSET 0x1000
+#define HBM4_MC0_CS_CTI_SECTION 0x1000
+#define HBM4_MC0_CS_ETF_BASE 0x7213000ull
+#define HBM4_MC0_CS_ETF_MAX_OFFSET 0x1000
+#define HBM4_MC0_CS_ETF_SECTION 0x1000
+#define HBM4_MC0_CS_SPMU_BASE 0x7214000ull
+#define HBM4_MC0_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM4_MC0_CS_SPMU_SECTION 0x1000
+#define HBM4_MC0_BMON_CTI_BASE 0x7215000ull
+#define HBM4_MC0_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM4_MC0_BMON_CTI_SECTION 0x1000
+#define HBM4_MC0_USER_CTI_BASE 0x7216000ull
+#define HBM4_MC0_USER_CTI_MAX_OFFSET 0x1000
+#define HBM4_MC0_USER_CTI_SECTION 0xA000
+#define HBM4_MC0_FUNNEL_BASE 0x7220000ull
+#define HBM4_MC0_FUNNEL_MAX_OFFSET 0x1000
+#define HBM4_MC0_FUNNEL_SECTION 0x30000
+#define HBM4_MC1_CS_DBG_ROM_TBL_BASE 0x7250000ull
+#define HBM4_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM4_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define HBM4_MC1_CS_STM_BASE 0x7251000ull
+#define HBM4_MC1_CS_STM_MAX_OFFSET 0x1000
+#define HBM4_MC1_CS_STM_SECTION 0x1000
+#define HBM4_MC1_CS_CTI_BASE 0x7252000ull
+#define HBM4_MC1_CS_CTI_MAX_OFFSET 0x1000
+#define HBM4_MC1_CS_CTI_SECTION 0x1000
+#define HBM4_MC1_CS_ETF_BASE 0x7253000ull
+#define HBM4_MC1_CS_ETF_MAX_OFFSET 0x1000
+#define HBM4_MC1_CS_ETF_SECTION 0x1000
+#define HBM4_MC1_CS_SPMU_BASE 0x7254000ull
+#define HBM4_MC1_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM4_MC1_CS_SPMU_SECTION 0x1000
+#define HBM4_MC1_BMON_CTI_BASE 0x7255000ull
+#define HBM4_MC1_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM4_MC1_BMON_CTI_SECTION 0x1000
+#define HBM4_MC1_USER_CTI_BASE 0x7256000ull
+#define HBM4_MC1_USER_CTI_MAX_OFFSET 0x1000
+#define HBM4_MC1_USER_CTI_SECTION 0xA000
+#define HBM4_MC1_FUNNEL_BASE 0x7260000ull
+#define HBM4_MC1_FUNNEL_MAX_OFFSET 0x1000
+#define HBM4_MC1_FUNNEL_SECTION 0x30000
+#define HBM5_MC0_CS_DBG_ROM_TBL_BASE 0x7290000ull
+#define HBM5_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM5_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define HBM5_MC0_CS_STM_BASE 0x7291000ull
+#define HBM5_MC0_CS_STM_MAX_OFFSET 0x1000
+#define HBM5_MC0_CS_STM_SECTION 0x1000
+#define HBM5_MC0_CS_CTI_BASE 0x7292000ull
+#define HBM5_MC0_CS_CTI_MAX_OFFSET 0x1000
+#define HBM5_MC0_CS_CTI_SECTION 0x1000
+#define HBM5_MC0_CS_ETF_BASE 0x7293000ull
+#define HBM5_MC0_CS_ETF_MAX_OFFSET 0x1000
+#define HBM5_MC0_CS_ETF_SECTION 0x1000
+#define HBM5_MC0_CS_SPMU_BASE 0x7294000ull
+#define HBM5_MC0_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM5_MC0_CS_SPMU_SECTION 0x1000
+#define HBM5_MC0_BMON_CTI_BASE 0x7295000ull
+#define HBM5_MC0_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM5_MC0_BMON_CTI_SECTION 0x1000
+#define HBM5_MC0_USER_CTI_BASE 0x7296000ull
+#define HBM5_MC0_USER_CTI_MAX_OFFSET 0x1000
+#define HBM5_MC0_USER_CTI_SECTION 0xA000
+#define HBM5_MC0_FUNNEL_BASE 0x72A0000ull
+#define HBM5_MC0_FUNNEL_MAX_OFFSET 0x1000
+#define HBM5_MC0_FUNNEL_SECTION 0x30000
+#define HBM5_MC1_CS_DBG_ROM_TBL_BASE 0x72D0000ull
+#define HBM5_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM5_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define HBM5_MC1_CS_STM_BASE 0x72D1000ull
+#define HBM5_MC1_CS_STM_MAX_OFFSET 0x1000
+#define HBM5_MC1_CS_STM_SECTION 0x1000
+#define HBM5_MC1_CS_CTI_BASE 0x72D2000ull
+#define HBM5_MC1_CS_CTI_MAX_OFFSET 0x1000
+#define HBM5_MC1_CS_CTI_SECTION 0x1000
+#define HBM5_MC1_CS_ETF_BASE 0x72D3000ull
+#define HBM5_MC1_CS_ETF_MAX_OFFSET 0x1000
+#define HBM5_MC1_CS_ETF_SECTION 0x1000
+#define HBM5_MC1_CS_SPMU_BASE 0x72D4000ull
+#define HBM5_MC1_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM5_MC1_CS_SPMU_SECTION 0x1000
+#define HBM5_MC1_BMON_CTI_BASE 0x72D5000ull
+#define HBM5_MC1_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM5_MC1_BMON_CTI_SECTION 0x1000
+#define HBM5_MC1_USER_CTI_BASE 0x72D6000ull
+#define HBM5_MC1_USER_CTI_MAX_OFFSET 0x1000
+#define HBM5_MC1_USER_CTI_SECTION 0xA000
+#define HBM5_MC1_FUNNEL_BASE 0x72E0000ull
+#define HBM5_MC1_FUNNEL_MAX_OFFSET 0x1000
+#define HBM5_MC1_FUNNEL_SECTION 0x20000
+#define NIC0_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7300000ull
+#define NIC0_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define NIC0_DBG_STM_0_BASE 0x7301000ull
+#define NIC0_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_STM_0_SECTION 0x1000
+#define NIC0_DBG_CTI_0_BASE 0x7302000ull
+#define NIC0_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_CTI_0_SECTION 0x1000
+#define NIC0_DBG_ETF_0_BASE 0x7303000ull
+#define NIC0_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_ETF_0_SECTION 0x1000
+#define NIC0_DBG_SPMU_0_BASE 0x7304000ull
+#define NIC0_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_SPMU_0_SECTION 0x1000
+#define NIC0_DBG_USER_CTI_0_BASE 0x7305000ull
+#define NIC0_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_USER_CTI_0_SECTION 0x1000
+#define NIC0_DBG_BMON_CTI_0_BASE 0x7306000ull
+#define NIC0_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON_CTI_0_SECTION 0x1000
+#define NIC0_DBG_BMON0_0_BASE 0x7307000ull
+#define NIC0_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON0_0_SECTION 0x1000
+#define NIC0_DBG_BMON1_0_BASE 0x7308000ull
+#define NIC0_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON1_0_SECTION 0x1000
+#define NIC0_DBG_BMON2_0_BASE 0x7309000ull
+#define NIC0_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON2_0_SECTION 0x7000
+#define NIC0_DBG_ARC_RTT0_BASE 0x7310000ull
+#define NIC0_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC0_DBG_ARC_RTT0_SECTION 0x10000
+#define NIC0_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7320000ull
+#define NIC0_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define NIC0_DBG_STM_1_BASE 0x7321000ull
+#define NIC0_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_STM_1_SECTION 0x1000
+#define NIC0_DBG_CTI_1_BASE 0x7322000ull
+#define NIC0_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_CTI_1_SECTION 0x1000
+#define NIC0_DBG_ETF_1_BASE 0x7323000ull
+#define NIC0_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_ETF_1_SECTION 0x1000
+#define NIC0_DBG_SPMU_1_BASE 0x7324000ull
+#define NIC0_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_SPMU_1_SECTION 0x1000
+#define NIC0_DBG_USER_CTI_1_BASE 0x7325000ull
+#define NIC0_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_USER_CTI_1_SECTION 0x1000
+#define NIC0_DBG_BMON_CTI_1_BASE 0x7326000ull
+#define NIC0_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON_CTI_1_SECTION 0x1000
+#define NIC0_DBG_BMON0_1_BASE 0x7327000ull
+#define NIC0_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON0_1_SECTION 0x1000
+#define NIC0_DBG_BMON1_1_BASE 0x7328000ull
+#define NIC0_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON1_1_SECTION 0x1000
+#define NIC0_DBG_BMON2_1_BASE 0x7329000ull
+#define NIC0_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON2_1_SECTION 0x7000
+#define NIC0_DBG_ARC_RTT1_BASE 0x7330000ull
+#define NIC0_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC0_DBG_ARC_RTT1_SECTION 0x8000
+#define NIC0_DBG_FUNNEL_TX_BASE 0x7338000ull
+#define NIC0_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC0_DBG_FUNNEL_TX_SECTION 0x1000
+#define NIC0_DBG_FUNNEL_NCH_BASE 0x7339000ull
+#define NIC0_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC0_DBG_FUNNEL_NCH_SECTION 0x7000
+#define NIC1_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7340000ull
+#define NIC1_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define NIC1_DBG_STM_0_BASE 0x7341000ull
+#define NIC1_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_STM_0_SECTION 0x1000
+#define NIC1_DBG_CTI_0_BASE 0x7342000ull
+#define NIC1_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_CTI_0_SECTION 0x1000
+#define NIC1_DBG_ETF_0_BASE 0x7343000ull
+#define NIC1_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_ETF_0_SECTION 0x1000
+#define NIC1_DBG_SPMU_0_BASE 0x7344000ull
+#define NIC1_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_SPMU_0_SECTION 0x1000
+#define NIC1_DBG_USER_CTI_0_BASE 0x7345000ull
+#define NIC1_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_USER_CTI_0_SECTION 0x1000
+#define NIC1_DBG_BMON_CTI_0_BASE 0x7346000ull
+#define NIC1_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON_CTI_0_SECTION 0x1000
+#define NIC1_DBG_BMON0_0_BASE 0x7347000ull
+#define NIC1_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON0_0_SECTION 0x1000
+#define NIC1_DBG_BMON1_0_BASE 0x7348000ull
+#define NIC1_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON1_0_SECTION 0x1000
+#define NIC1_DBG_BMON2_0_BASE 0x7349000ull
+#define NIC1_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON2_0_SECTION 0x7000
+#define NIC1_DBG_ARC_RTT0_BASE 0x7350000ull
+#define NIC1_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC1_DBG_ARC_RTT0_SECTION 0x10000
+#define NIC1_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7360000ull
+#define NIC1_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define NIC1_DBG_STM_1_BASE 0x7361000ull
+#define NIC1_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_STM_1_SECTION 0x1000
+#define NIC1_DBG_CTI_1_BASE 0x7362000ull
+#define NIC1_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_CTI_1_SECTION 0x1000
+#define NIC1_DBG_ETF_1_BASE 0x7363000ull
+#define NIC1_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_ETF_1_SECTION 0x1000
+#define NIC1_DBG_SPMU_1_BASE 0x7364000ull
+#define NIC1_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_SPMU_1_SECTION 0x1000
+#define NIC1_DBG_USER_CTI_1_BASE 0x7365000ull
+#define NIC1_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_USER_CTI_1_SECTION 0x1000
+#define NIC1_DBG_BMON_CTI_1_BASE 0x7366000ull
+#define NIC1_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON_CTI_1_SECTION 0x1000
+#define NIC1_DBG_BMON0_1_BASE 0x7367000ull
+#define NIC1_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON0_1_SECTION 0x1000
+#define NIC1_DBG_BMON1_1_BASE 0x7368000ull
+#define NIC1_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON1_1_SECTION 0x1000
+#define NIC1_DBG_BMON2_1_BASE 0x7369000ull
+#define NIC1_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON2_1_SECTION 0x7000
+#define NIC1_DBG_ARC_RTT1_BASE 0x7370000ull
+#define NIC1_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC1_DBG_ARC_RTT1_SECTION 0x8000
+#define NIC1_DBG_FUNNEL_TX_BASE 0x7378000ull
+#define NIC1_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC1_DBG_FUNNEL_TX_SECTION 0x1000
+#define NIC1_DBG_FUNNEL_NCH_BASE 0x7379000ull
+#define NIC1_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC1_DBG_FUNNEL_NCH_SECTION 0x7000
+#define NIC2_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7380000ull
+#define NIC2_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define NIC2_DBG_STM_0_BASE 0x7381000ull
+#define NIC2_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_STM_0_SECTION 0x1000
+#define NIC2_DBG_CTI_0_BASE 0x7382000ull
+#define NIC2_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_CTI_0_SECTION 0x1000
+#define NIC2_DBG_ETF_0_BASE 0x7383000ull
+#define NIC2_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_ETF_0_SECTION 0x1000
+#define NIC2_DBG_SPMU_0_BASE 0x7384000ull
+#define NIC2_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_SPMU_0_SECTION 0x1000
+#define NIC2_DBG_USER_CTI_0_BASE 0x7385000ull
+#define NIC2_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_USER_CTI_0_SECTION 0x1000
+#define NIC2_DBG_BMON_CTI_0_BASE 0x7386000ull
+#define NIC2_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON_CTI_0_SECTION 0x1000
+#define NIC2_DBG_BMON0_0_BASE 0x7387000ull
+#define NIC2_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON0_0_SECTION 0x1000
+#define NIC2_DBG_BMON1_0_BASE 0x7388000ull
+#define NIC2_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON1_0_SECTION 0x1000
+#define NIC2_DBG_BMON2_0_BASE 0x7389000ull
+#define NIC2_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON2_0_SECTION 0x7000
+#define NIC2_DBG_ARC_RTT0_BASE 0x7390000ull
+#define NIC2_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC2_DBG_ARC_RTT0_SECTION 0x10000
+#define NIC2_DBG_CS_DBG_ROM_TABLE_1_BASE 0x73A0000ull
+#define NIC2_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define NIC2_DBG_STM_1_BASE 0x73A1000ull
+#define NIC2_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_STM_1_SECTION 0x1000
+#define NIC2_DBG_CTI_1_BASE 0x73A2000ull
+#define NIC2_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_CTI_1_SECTION 0x1000
+#define NIC2_DBG_ETF_1_BASE 0x73A3000ull
+#define NIC2_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_ETF_1_SECTION 0x1000
+#define NIC2_DBG_SPMU_1_BASE 0x73A4000ull
+#define NIC2_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_SPMU_1_SECTION 0x1000
+#define NIC2_DBG_USER_CTI_1_BASE 0x73A5000ull
+#define NIC2_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_USER_CTI_1_SECTION 0x1000
+#define NIC2_DBG_BMON_CTI_1_BASE 0x73A6000ull
+#define NIC2_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON_CTI_1_SECTION 0x1000
+#define NIC2_DBG_BMON0_1_BASE 0x73A7000ull
+#define NIC2_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON0_1_SECTION 0x1000
+#define NIC2_DBG_BMON1_1_BASE 0x73A8000ull
+#define NIC2_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON1_1_SECTION 0x1000
+#define NIC2_DBG_BMON2_1_BASE 0x73A9000ull
+#define NIC2_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON2_1_SECTION 0x7000
+#define NIC2_DBG_ARC_RTT1_BASE 0x73B0000ull
+#define NIC2_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC2_DBG_ARC_RTT1_SECTION 0x8000
+#define NIC2_DBG_FUNNEL_TX_BASE 0x73B8000ull
+#define NIC2_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC2_DBG_FUNNEL_TX_SECTION 0x1000
+#define NIC2_DBG_FUNNEL_NCH_BASE 0x73B9000ull
+#define NIC2_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC2_DBG_FUNNEL_NCH_SECTION 0x7000
+#define NIC3_DBG_CS_DBG_ROM_TABLE_0_BASE 0x73C0000ull
+#define NIC3_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define NIC3_DBG_STM_0_BASE 0x73C1000ull
+#define NIC3_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_STM_0_SECTION 0x1000
+#define NIC3_DBG_CTI_0_BASE 0x73C2000ull
+#define NIC3_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_CTI_0_SECTION 0x1000
+#define NIC3_DBG_ETF_0_BASE 0x73C3000ull
+#define NIC3_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_ETF_0_SECTION 0x1000
+#define NIC3_DBG_SPMU_0_BASE 0x73C4000ull
+#define NIC3_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_SPMU_0_SECTION 0x1000
+#define NIC3_DBG_USER_CTI_0_BASE 0x73C5000ull
+#define NIC3_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_USER_CTI_0_SECTION 0x1000
+#define NIC3_DBG_BMON_CTI_0_BASE 0x73C6000ull
+#define NIC3_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON_CTI_0_SECTION 0x1000
+#define NIC3_DBG_BMON0_0_BASE 0x73C7000ull
+#define NIC3_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON0_0_SECTION 0x1000
+#define NIC3_DBG_BMON1_0_BASE 0x73C8000ull
+#define NIC3_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON1_0_SECTION 0x1000
+#define NIC3_DBG_BMON2_0_BASE 0x73C9000ull
+#define NIC3_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON2_0_SECTION 0x7000
+#define NIC3_DBG_ARC_RTT0_BASE 0x73D0000ull
+#define NIC3_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC3_DBG_ARC_RTT0_SECTION 0x10000
+#define NIC3_DBG_CS_DBG_ROM_TABLE_1_BASE 0x73E0000ull
+#define NIC3_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define NIC3_DBG_STM_1_BASE 0x73E1000ull
+#define NIC3_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_STM_1_SECTION 0x1000
+#define NIC3_DBG_CTI_1_BASE 0x73E2000ull
+#define NIC3_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_CTI_1_SECTION 0x1000
+#define NIC3_DBG_ETF_1_BASE 0x73E3000ull
+#define NIC3_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_ETF_1_SECTION 0x1000
+#define NIC3_DBG_SPMU_1_BASE 0x73E4000ull
+#define NIC3_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_SPMU_1_SECTION 0x1000
+#define NIC3_DBG_USER_CTI_1_BASE 0x73E5000ull
+#define NIC3_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_USER_CTI_1_SECTION 0x1000
+#define NIC3_DBG_BMON_CTI_1_BASE 0x73E6000ull
+#define NIC3_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON_CTI_1_SECTION 0x1000
+#define NIC3_DBG_BMON0_1_BASE 0x73E7000ull
+#define NIC3_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON0_1_SECTION 0x1000
+#define NIC3_DBG_BMON1_1_BASE 0x73E8000ull
+#define NIC3_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON1_1_SECTION 0x1000
+#define NIC3_DBG_BMON2_1_BASE 0x73E9000ull
+#define NIC3_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON2_1_SECTION 0x7000
+#define NIC3_DBG_ARC_RTT1_BASE 0x73F0000ull
+#define NIC3_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC3_DBG_ARC_RTT1_SECTION 0x8000
+#define NIC3_DBG_FUNNEL_TX_BASE 0x73F8000ull
+#define NIC3_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC3_DBG_FUNNEL_TX_SECTION 0x1000
+#define NIC3_DBG_FUNNEL_NCH_BASE 0x73F9000ull
+#define NIC3_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC3_DBG_FUNNEL_NCH_SECTION 0x7000
+#define NIC4_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7400000ull
+#define NIC4_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define NIC4_DBG_STM_0_BASE 0x7401000ull
+#define NIC4_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_STM_0_SECTION 0x1000
+#define NIC4_DBG_CTI_0_BASE 0x7402000ull
+#define NIC4_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_CTI_0_SECTION 0x1000
+#define NIC4_DBG_ETF_0_BASE 0x7403000ull
+#define NIC4_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_ETF_0_SECTION 0x1000
+#define NIC4_DBG_SPMU_0_BASE 0x7404000ull
+#define NIC4_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_SPMU_0_SECTION 0x1000
+#define NIC4_DBG_USER_CTI_0_BASE 0x7405000ull
+#define NIC4_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_USER_CTI_0_SECTION 0x1000
+#define NIC4_DBG_BMON_CTI_0_BASE 0x7406000ull
+#define NIC4_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON_CTI_0_SECTION 0x1000
+#define NIC4_DBG_BMON0_0_BASE 0x7407000ull
+#define NIC4_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON0_0_SECTION 0x1000
+#define NIC4_DBG_BMON1_0_BASE 0x7408000ull
+#define NIC4_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON1_0_SECTION 0x1000
+#define NIC4_DBG_BMON2_0_BASE 0x7409000ull
+#define NIC4_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON2_0_SECTION 0x7000
+#define NIC4_DBG_ARC_RTT0_BASE 0x7410000ull
+#define NIC4_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC4_DBG_ARC_RTT0_SECTION 0x10000
+#define NIC4_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7420000ull
+#define NIC4_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define NIC4_DBG_STM_1_BASE 0x7421000ull
+#define NIC4_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_STM_1_SECTION 0x1000
+#define NIC4_DBG_CTI_1_BASE 0x7422000ull
+#define NIC4_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_CTI_1_SECTION 0x1000
+#define NIC4_DBG_ETF_1_BASE 0x7423000ull
+#define NIC4_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_ETF_1_SECTION 0x1000
+#define NIC4_DBG_SPMU_1_BASE 0x7424000ull
+#define NIC4_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_SPMU_1_SECTION 0x1000
+#define NIC4_DBG_USER_CTI_1_BASE 0x7425000ull
+#define NIC4_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_USER_CTI_1_SECTION 0x1000
+#define NIC4_DBG_BMON_CTI_1_BASE 0x7426000ull
+#define NIC4_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON_CTI_1_SECTION 0x1000
+#define NIC4_DBG_BMON0_1_BASE 0x7427000ull
+#define NIC4_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON0_1_SECTION 0x1000
+#define NIC4_DBG_BMON1_1_BASE 0x7428000ull
+#define NIC4_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON1_1_SECTION 0x1000
+#define NIC4_DBG_BMON2_1_BASE 0x7429000ull
+#define NIC4_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON2_1_SECTION 0x7000
+#define NIC4_DBG_ARC_RTT1_BASE 0x7430000ull
+#define NIC4_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC4_DBG_ARC_RTT1_SECTION 0x8000
+#define NIC4_DBG_FUNNEL_TX_BASE 0x7438000ull
+#define NIC4_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC4_DBG_FUNNEL_TX_SECTION 0x1000
+#define NIC4_DBG_FUNNEL_NCH_BASE 0x7439000ull
+#define NIC4_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC4_DBG_FUNNEL_NCH_SECTION 0x7000
+#define NIC5_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7440000ull
+#define NIC5_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define NIC5_DBG_STM_0_BASE 0x7441000ull
+#define NIC5_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_STM_0_SECTION 0x1000
+#define NIC5_DBG_CTI_0_BASE 0x7442000ull
+#define NIC5_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_CTI_0_SECTION 0x1000
+#define NIC5_DBG_ETF_0_BASE 0x7443000ull
+#define NIC5_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_ETF_0_SECTION 0x1000
+#define NIC5_DBG_SPMU_0_BASE 0x7444000ull
+#define NIC5_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_SPMU_0_SECTION 0x1000
+#define NIC5_DBG_USER_CTI_0_BASE 0x7445000ull
+#define NIC5_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_USER_CTI_0_SECTION 0x1000
+#define NIC5_DBG_BMON_CTI_0_BASE 0x7446000ull
+#define NIC5_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON_CTI_0_SECTION 0x1000
+#define NIC5_DBG_BMON0_0_BASE 0x7447000ull
+#define NIC5_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON0_0_SECTION 0x1000
+#define NIC5_DBG_BMON1_0_BASE 0x7448000ull
+#define NIC5_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON1_0_SECTION 0x1000
+#define NIC5_DBG_BMON2_0_BASE 0x7449000ull
+#define NIC5_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON2_0_SECTION 0x7000
+#define NIC5_DBG_ARC_RTT0_BASE 0x7450000ull
+#define NIC5_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC5_DBG_ARC_RTT0_SECTION 0x10000
+#define NIC5_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7460000ull
+#define NIC5_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define NIC5_DBG_STM_1_BASE 0x7461000ull
+#define NIC5_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_STM_1_SECTION 0x1000
+#define NIC5_DBG_CTI_1_BASE 0x7462000ull
+#define NIC5_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_CTI_1_SECTION 0x1000
+#define NIC5_DBG_ETF_1_BASE 0x7463000ull
+#define NIC5_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_ETF_1_SECTION 0x1000
+#define NIC5_DBG_SPMU_1_BASE 0x7464000ull
+#define NIC5_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_SPMU_1_SECTION 0x1000
+#define NIC5_DBG_USER_CTI_1_BASE 0x7465000ull
+#define NIC5_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_USER_CTI_1_SECTION 0x1000
+#define NIC5_DBG_BMON_CTI_1_BASE 0x7466000ull
+#define NIC5_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON_CTI_1_SECTION 0x1000
+#define NIC5_DBG_BMON0_1_BASE 0x7467000ull
+#define NIC5_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON0_1_SECTION 0x1000
+#define NIC5_DBG_BMON1_1_BASE 0x7468000ull
+#define NIC5_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON1_1_SECTION 0x1000
+#define NIC5_DBG_BMON2_1_BASE 0x7469000ull
+#define NIC5_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON2_1_SECTION 0x7000
+#define NIC5_DBG_ARC_RTT1_BASE 0x7470000ull
+#define NIC5_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC5_DBG_ARC_RTT1_SECTION 0x8000
+#define NIC5_DBG_FUNNEL_TX_BASE 0x7478000ull
+#define NIC5_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC5_DBG_FUNNEL_TX_SECTION 0x1000
+#define NIC5_DBG_FUNNEL_NCH_BASE 0x7479000ull
+#define NIC5_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC5_DBG_FUNNEL_NCH_SECTION 0x7000
+#define NIC6_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7480000ull
+#define NIC6_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define NIC6_DBG_STM_0_BASE 0x7481000ull
+#define NIC6_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_STM_0_SECTION 0x1000
+#define NIC6_DBG_CTI_0_BASE 0x7482000ull
+#define NIC6_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_CTI_0_SECTION 0x1000
+#define NIC6_DBG_ETF_0_BASE 0x7483000ull
+#define NIC6_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_ETF_0_SECTION 0x1000
+#define NIC6_DBG_SPMU_0_BASE 0x7484000ull
+#define NIC6_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_SPMU_0_SECTION 0x1000
+#define NIC6_DBG_USER_CTI_0_BASE 0x7485000ull
+#define NIC6_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_USER_CTI_0_SECTION 0x1000
+#define NIC6_DBG_BMON_CTI_0_BASE 0x7486000ull
+#define NIC6_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON_CTI_0_SECTION 0x1000
+#define NIC6_DBG_BMON0_0_BASE 0x7487000ull
+#define NIC6_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON0_0_SECTION 0x1000
+#define NIC6_DBG_BMON1_0_BASE 0x7488000ull
+#define NIC6_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON1_0_SECTION 0x1000
+#define NIC6_DBG_BMON2_0_BASE 0x7489000ull
+#define NIC6_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON2_0_SECTION 0x7000
+#define NIC6_DBG_ARC_RTT0_BASE 0x7490000ull
+#define NIC6_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC6_DBG_ARC_RTT0_SECTION 0x10000
+#define NIC6_DBG_CS_DBG_ROM_TABLE_1_BASE 0x74A0000ull
+#define NIC6_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define NIC6_DBG_STM_1_BASE 0x74A1000ull
+#define NIC6_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_STM_1_SECTION 0x1000
+#define NIC6_DBG_CTI_1_BASE 0x74A2000ull
+#define NIC6_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_CTI_1_SECTION 0x1000
+#define NIC6_DBG_ETF_1_BASE 0x74A3000ull
+#define NIC6_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_ETF_1_SECTION 0x1000
+#define NIC6_DBG_SPMU_1_BASE 0x74A4000ull
+#define NIC6_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_SPMU_1_SECTION 0x1000
+#define NIC6_DBG_USER_CTI_1_BASE 0x74A5000ull
+#define NIC6_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_USER_CTI_1_SECTION 0x1000
+#define NIC6_DBG_BMON_CTI_1_BASE 0x74A6000ull
+#define NIC6_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON_CTI_1_SECTION 0x1000
+#define NIC6_DBG_BMON0_1_BASE 0x74A7000ull
+#define NIC6_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON0_1_SECTION 0x1000
+#define NIC6_DBG_BMON1_1_BASE 0x74A8000ull
+#define NIC6_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON1_1_SECTION 0x1000
+#define NIC6_DBG_BMON2_1_BASE 0x74A9000ull
+#define NIC6_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON2_1_SECTION 0x7000
+#define NIC6_DBG_ARC_RTT1_BASE 0x74B0000ull
+#define NIC6_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC6_DBG_ARC_RTT1_SECTION 0x8000
+#define NIC6_DBG_FUNNEL_TX_BASE 0x74B8000ull
+#define NIC6_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC6_DBG_FUNNEL_TX_SECTION 0x1000
+#define NIC6_DBG_FUNNEL_NCH_BASE 0x74B9000ull
+#define NIC6_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC6_DBG_FUNNEL_NCH_SECTION 0x7000
+#define NIC7_DBG_CS_DBG_ROM_TABLE_0_BASE 0x74C0000ull
+#define NIC7_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define NIC7_DBG_STM_0_BASE 0x74C1000ull
+#define NIC7_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_STM_0_SECTION 0x1000
+#define NIC7_DBG_CTI_0_BASE 0x74C2000ull
+#define NIC7_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_CTI_0_SECTION 0x1000
+#define NIC7_DBG_ETF_0_BASE 0x74C3000ull
+#define NIC7_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_ETF_0_SECTION 0x1000
+#define NIC7_DBG_SPMU_0_BASE 0x74C4000ull
+#define NIC7_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_SPMU_0_SECTION 0x1000
+#define NIC7_DBG_USER_CTI_0_BASE 0x74C5000ull
+#define NIC7_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_USER_CTI_0_SECTION 0x1000
+#define NIC7_DBG_BMON_CTI_0_BASE 0x74C6000ull
+#define NIC7_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON_CTI_0_SECTION 0x1000
+#define NIC7_DBG_BMON0_0_BASE 0x74C7000ull
+#define NIC7_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON0_0_SECTION 0x1000
+#define NIC7_DBG_BMON1_0_BASE 0x74C8000ull
+#define NIC7_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON1_0_SECTION 0x1000
+#define NIC7_DBG_BMON2_0_BASE 0x74C9000ull
+#define NIC7_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON2_0_SECTION 0x7000
+#define NIC7_DBG_ARC_RTT0_BASE 0x74D0000ull
+#define NIC7_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC7_DBG_ARC_RTT0_SECTION 0x10000
+#define NIC7_DBG_CS_DBG_ROM_TABLE_1_BASE 0x74E0000ull
+#define NIC7_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define NIC7_DBG_STM_1_BASE 0x74E1000ull
+#define NIC7_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_STM_1_SECTION 0x1000
+#define NIC7_DBG_CTI_1_BASE 0x74E2000ull
+#define NIC7_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_CTI_1_SECTION 0x1000
+#define NIC7_DBG_ETF_1_BASE 0x74E3000ull
+#define NIC7_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_ETF_1_SECTION 0x1000
+#define NIC7_DBG_SPMU_1_BASE 0x74E4000ull
+#define NIC7_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_SPMU_1_SECTION 0x1000
+#define NIC7_DBG_USER_CTI_1_BASE 0x74E5000ull
+#define NIC7_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_USER_CTI_1_SECTION 0x1000
+#define NIC7_DBG_BMON_CTI_1_BASE 0x74E6000ull
+#define NIC7_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON_CTI_1_SECTION 0x1000
+#define NIC7_DBG_BMON0_1_BASE 0x74E7000ull
+#define NIC7_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON0_1_SECTION 0x1000
+#define NIC7_DBG_BMON1_1_BASE 0x74E8000ull
+#define NIC7_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON1_1_SECTION 0x1000
+#define NIC7_DBG_BMON2_1_BASE 0x74E9000ull
+#define NIC7_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON2_1_SECTION 0x7000
+#define NIC7_DBG_ARC_RTT1_BASE 0x74F0000ull
+#define NIC7_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC7_DBG_ARC_RTT1_SECTION 0x8000
+#define NIC7_DBG_FUNNEL_TX_BASE 0x74F8000ull
+#define NIC7_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC7_DBG_FUNNEL_TX_SECTION 0x1000
+#define NIC7_DBG_FUNNEL_NCH_BASE 0x74F9000ull
+#define NIC7_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC7_DBG_FUNNEL_NCH_SECTION 0x7000
+#define NIC8_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7500000ull
+#define NIC8_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define NIC8_DBG_STM_0_BASE 0x7501000ull
+#define NIC8_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_STM_0_SECTION 0x1000
+#define NIC8_DBG_CTI_0_BASE 0x7502000ull
+#define NIC8_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_CTI_0_SECTION 0x1000
+#define NIC8_DBG_ETF_0_BASE 0x7503000ull
+#define NIC8_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_ETF_0_SECTION 0x1000
+#define NIC8_DBG_SPMU_0_BASE 0x7504000ull
+#define NIC8_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_SPMU_0_SECTION 0x1000
+#define NIC8_DBG_USER_CTI_0_BASE 0x7505000ull
+#define NIC8_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_USER_CTI_0_SECTION 0x1000
+#define NIC8_DBG_BMON_CTI_0_BASE 0x7506000ull
+#define NIC8_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON_CTI_0_SECTION 0x1000
+#define NIC8_DBG_BMON0_0_BASE 0x7507000ull
+#define NIC8_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON0_0_SECTION 0x1000
+#define NIC8_DBG_BMON1_0_BASE 0x7508000ull
+#define NIC8_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON1_0_SECTION 0x1000
+#define NIC8_DBG_BMON2_0_BASE 0x7509000ull
+#define NIC8_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON2_0_SECTION 0x7000
+#define NIC8_DBG_ARC_RTT0_BASE 0x7510000ull
+#define NIC8_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC8_DBG_ARC_RTT0_SECTION 0x10000
+#define NIC8_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7520000ull
+#define NIC8_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define NIC8_DBG_STM_1_BASE 0x7521000ull
+#define NIC8_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_STM_1_SECTION 0x1000
+#define NIC8_DBG_CTI_1_BASE 0x7522000ull
+#define NIC8_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_CTI_1_SECTION 0x1000
+#define NIC8_DBG_ETF_1_BASE 0x7523000ull
+#define NIC8_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_ETF_1_SECTION 0x1000
+#define NIC8_DBG_SPMU_1_BASE 0x7524000ull
+#define NIC8_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_SPMU_1_SECTION 0x1000
+#define NIC8_DBG_USER_CTI_1_BASE 0x7525000ull
+#define NIC8_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_USER_CTI_1_SECTION 0x1000
+#define NIC8_DBG_BMON_CTI_1_BASE 0x7526000ull
+#define NIC8_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON_CTI_1_SECTION 0x1000
+#define NIC8_DBG_BMON0_1_BASE 0x7527000ull
+#define NIC8_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON0_1_SECTION 0x1000
+#define NIC8_DBG_BMON1_1_BASE 0x7528000ull
+#define NIC8_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON1_1_SECTION 0x1000
+#define NIC8_DBG_BMON2_1_BASE 0x7529000ull
+#define NIC8_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON2_1_SECTION 0x7000
+#define NIC8_DBG_ARC_RTT1_BASE 0x7530000ull
+#define NIC8_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC8_DBG_ARC_RTT1_SECTION 0x8000
+#define NIC8_DBG_FUNNEL_TX_BASE 0x7538000ull
+#define NIC8_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC8_DBG_FUNNEL_TX_SECTION 0x1000
+#define NIC8_DBG_FUNNEL_NCH_BASE 0x7539000ull
+#define NIC8_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC8_DBG_FUNNEL_NCH_SECTION 0x7000
+#define NIC9_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7540000ull
+#define NIC9_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define NIC9_DBG_STM_0_BASE 0x7541000ull
+#define NIC9_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_STM_0_SECTION 0x1000
+#define NIC9_DBG_CTI_0_BASE 0x7542000ull
+#define NIC9_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_CTI_0_SECTION 0x1000
+#define NIC9_DBG_ETF_0_BASE 0x7543000ull
+#define NIC9_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_ETF_0_SECTION 0x1000
+#define NIC9_DBG_SPMU_0_BASE 0x7544000ull
+#define NIC9_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_SPMU_0_SECTION 0x1000
+#define NIC9_DBG_USER_CTI_0_BASE 0x7545000ull
+#define NIC9_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_USER_CTI_0_SECTION 0x1000
+#define NIC9_DBG_BMON_CTI_0_BASE 0x7546000ull
+#define NIC9_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON_CTI_0_SECTION 0x1000
+#define NIC9_DBG_BMON0_0_BASE 0x7547000ull
+#define NIC9_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON0_0_SECTION 0x1000
+#define NIC9_DBG_BMON1_0_BASE 0x7548000ull
+#define NIC9_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON1_0_SECTION 0x1000
+#define NIC9_DBG_BMON2_0_BASE 0x7549000ull
+#define NIC9_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON2_0_SECTION 0x7000
+#define NIC9_DBG_ARC_RTT0_BASE 0x7550000ull
+#define NIC9_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC9_DBG_ARC_RTT0_SECTION 0x10000
+#define NIC9_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7560000ull
+#define NIC9_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define NIC9_DBG_STM_1_BASE 0x7561000ull
+#define NIC9_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_STM_1_SECTION 0x1000
+#define NIC9_DBG_CTI_1_BASE 0x7562000ull
+#define NIC9_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_CTI_1_SECTION 0x1000
+#define NIC9_DBG_ETF_1_BASE 0x7563000ull
+#define NIC9_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_ETF_1_SECTION 0x1000
+#define NIC9_DBG_SPMU_1_BASE 0x7564000ull
+#define NIC9_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_SPMU_1_SECTION 0x1000
+#define NIC9_DBG_USER_CTI_1_BASE 0x7565000ull
+#define NIC9_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_USER_CTI_1_SECTION 0x1000
+#define NIC9_DBG_BMON_CTI_1_BASE 0x7566000ull
+#define NIC9_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON_CTI_1_SECTION 0x1000
+#define NIC9_DBG_BMON0_1_BASE 0x7567000ull
+#define NIC9_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON0_1_SECTION 0x1000
+#define NIC9_DBG_BMON1_1_BASE 0x7568000ull
+#define NIC9_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON1_1_SECTION 0x1000
+#define NIC9_DBG_BMON2_1_BASE 0x7569000ull
+#define NIC9_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON2_1_SECTION 0x7000
+#define NIC9_DBG_ARC_RTT1_BASE 0x7570000ull
+#define NIC9_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC9_DBG_ARC_RTT1_SECTION 0x8000
+#define NIC9_DBG_FUNNEL_TX_BASE 0x7578000ull
+#define NIC9_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC9_DBG_FUNNEL_TX_SECTION 0x1000
+#define NIC9_DBG_FUNNEL_NCH_BASE 0x7579000ull
+#define NIC9_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC9_DBG_FUNNEL_NCH_SECTION 0x7000
+#define NIC10_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7580000ull
+#define NIC10_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define NIC10_DBG_STM_0_BASE 0x7581000ull
+#define NIC10_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_STM_0_SECTION 0x1000
+#define NIC10_DBG_CTI_0_BASE 0x7582000ull
+#define NIC10_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_CTI_0_SECTION 0x1000
+#define NIC10_DBG_ETF_0_BASE 0x7583000ull
+#define NIC10_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_ETF_0_SECTION 0x1000
+#define NIC10_DBG_SPMU_0_BASE 0x7584000ull
+#define NIC10_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_SPMU_0_SECTION 0x1000
+#define NIC10_DBG_USER_CTI_0_BASE 0x7585000ull
+#define NIC10_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_USER_CTI_0_SECTION 0x1000
+#define NIC10_DBG_BMON_CTI_0_BASE 0x7586000ull
+#define NIC10_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON_CTI_0_SECTION 0x1000
+#define NIC10_DBG_BMON0_0_BASE 0x7587000ull
+#define NIC10_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON0_0_SECTION 0x1000
+#define NIC10_DBG_BMON1_0_BASE 0x7588000ull
+#define NIC10_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON1_0_SECTION 0x1000
+#define NIC10_DBG_BMON2_0_BASE 0x7589000ull
+#define NIC10_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON2_0_SECTION 0x7000
+#define NIC10_DBG_ARC_RTT0_BASE 0x7590000ull
+#define NIC10_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC10_DBG_ARC_RTT0_SECTION 0x10000
+#define NIC10_DBG_CS_DBG_ROM_TABLE_1_BASE 0x75A0000ull
+#define NIC10_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define NIC10_DBG_STM_1_BASE 0x75A1000ull
+#define NIC10_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_STM_1_SECTION 0x1000
+#define NIC10_DBG_CTI_1_BASE 0x75A2000ull
+#define NIC10_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_CTI_1_SECTION 0x1000
+#define NIC10_DBG_ETF_1_BASE 0x75A3000ull
+#define NIC10_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_ETF_1_SECTION 0x1000
+#define NIC10_DBG_SPMU_1_BASE 0x75A4000ull
+#define NIC10_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_SPMU_1_SECTION 0x1000
+#define NIC10_DBG_USER_CTI_1_BASE 0x75A5000ull
+#define NIC10_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_USER_CTI_1_SECTION 0x1000
+#define NIC10_DBG_BMON_CTI_1_BASE 0x75A6000ull
+#define NIC10_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON_CTI_1_SECTION 0x1000
+#define NIC10_DBG_BMON0_1_BASE 0x75A7000ull
+#define NIC10_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON0_1_SECTION 0x1000
+#define NIC10_DBG_BMON1_1_BASE 0x75A8000ull
+#define NIC10_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON1_1_SECTION 0x1000
+#define NIC10_DBG_BMON2_1_BASE 0x75A9000ull
+#define NIC10_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON2_1_SECTION 0x7000
+#define NIC10_DBG_ARC_RTT1_BASE 0x75B0000ull
+#define NIC10_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC10_DBG_ARC_RTT1_SECTION 0x8000
+#define NIC10_DBG_FUNNEL_TX_BASE 0x75B8000ull
+#define NIC10_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC10_DBG_FUNNEL_TX_SECTION 0x1000
+#define NIC10_DBG_FUNNEL_NCH_BASE 0x75B9000ull
+#define NIC10_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC10_DBG_FUNNEL_NCH_SECTION 0x7000
+#define NIC11_DBG_CS_DBG_ROM_TABLE_0_BASE 0x75C0000ull
+#define NIC11_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define NIC11_DBG_STM_0_BASE 0x75C1000ull
+#define NIC11_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_STM_0_SECTION 0x1000
+#define NIC11_DBG_CTI_0_BASE 0x75C2000ull
+#define NIC11_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_CTI_0_SECTION 0x1000
+#define NIC11_DBG_ETF_0_BASE 0x75C3000ull
+#define NIC11_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_ETF_0_SECTION 0x1000
+#define NIC11_DBG_SPMU_0_BASE 0x75C4000ull
+#define NIC11_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_SPMU_0_SECTION 0x1000
+#define NIC11_DBG_USER_CTI_0_BASE 0x75C5000ull
+#define NIC11_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_USER_CTI_0_SECTION 0x1000
+#define NIC11_DBG_BMON_CTI_0_BASE 0x75C6000ull
+#define NIC11_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON_CTI_0_SECTION 0x1000
+#define NIC11_DBG_BMON0_0_BASE 0x75C7000ull
+#define NIC11_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON0_0_SECTION 0x1000
+#define NIC11_DBG_BMON1_0_BASE 0x75C8000ull
+#define NIC11_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON1_0_SECTION 0x1000
+#define NIC11_DBG_BMON2_0_BASE 0x75C9000ull
+#define NIC11_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON2_0_SECTION 0x7000
+#define NIC11_DBG_ARC_RTT0_BASE 0x75D0000ull
+#define NIC11_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC11_DBG_ARC_RTT0_SECTION 0x10000
+#define NIC11_DBG_CS_DBG_ROM_TABLE_1_BASE 0x75E0000ull
+#define NIC11_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define NIC11_DBG_STM_1_BASE 0x75E1000ull
+#define NIC11_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_STM_1_SECTION 0x1000
+#define NIC11_DBG_CTI_1_BASE 0x75E2000ull
+#define NIC11_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_CTI_1_SECTION 0x1000
+#define NIC11_DBG_ETF_1_BASE 0x75E3000ull
+#define NIC11_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_ETF_1_SECTION 0x1000
+#define NIC11_DBG_SPMU_1_BASE 0x75E4000ull
+#define NIC11_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_SPMU_1_SECTION 0x1000
+#define NIC11_DBG_USER_CTI_1_BASE 0x75E5000ull
+#define NIC11_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_USER_CTI_1_SECTION 0x1000
+#define NIC11_DBG_BMON_CTI_1_BASE 0x75E6000ull
+#define NIC11_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON_CTI_1_SECTION 0x1000
+#define NIC11_DBG_BMON0_1_BASE 0x75E7000ull
+#define NIC11_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON0_1_SECTION 0x1000
+#define NIC11_DBG_BMON1_1_BASE 0x75E8000ull
+#define NIC11_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON1_1_SECTION 0x1000
+#define NIC11_DBG_BMON2_1_BASE 0x75E9000ull
+#define NIC11_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON2_1_SECTION 0x7000
+#define NIC11_DBG_ARC_RTT1_BASE 0x75F0000ull
+#define NIC11_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC11_DBG_ARC_RTT1_SECTION 0x8000
+#define NIC11_DBG_FUNNEL_TX_BASE 0x75F8000ull
+#define NIC11_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC11_DBG_FUNNEL_TX_SECTION 0x1000
+#define NIC11_DBG_FUNNEL_NCH_BASE 0x75F9000ull
+#define NIC11_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+
+#endif /* GAUDI2_BLOCKS_LINUX_DRIVER_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/gaudi2_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/gaudi2_regs.h
new file mode 100644
index 000000000000..00d50b3c84d3
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/gaudi2_regs.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef ASIC_REG_GAUDI2_REGS_H_
+#define ASIC_REG_GAUDI2_REGS_H_
+
+#include "arc_farm_kdma_ctx_axuser_masks.h"
+#include "dcore0_sync_mngr_objs_regs.h"
+#include "gaudi2_blocks_linux_driver.h"
+#include "nic0_mac_ch0_mac_128_masks.h"
+#include "nic0_mac_ch0_mac_128_regs.h"
+#include "nic0_mac_ch0_mac_pcs_masks.h"
+#include "nic0_mac_ch0_mac_pcs_regs.h"
+#include "nic0_mac_ch1_mac_pcs_regs.h"
+#include "nic0_mac_ch2_mac_pcs_regs.h"
+#include "nic0_mac_ch3_mac_pcs_regs.h"
+#include "nic0_mac_glob_stat_control_reg_masks.h"
+#include "nic0_mac_glob_stat_control_reg_regs.h"
+#include "nic0_mac_glob_stat_rx0_regs.h"
+#include "nic0_mac_glob_stat_rx2_regs.h"
+#include "nic0_mac_glob_stat_tx0_regs.h"
+#include "nic0_mac_glob_stat_tx2_regs.h"
+#include "nic0_mac_rs_fec_regs.h"
+#include "nic0_phy_masks.h"
+#include "nic0_phy_regs.h"
+#include "nic0_qm0_axuser_nonsecured_regs.h"
+#include "nic0_qpc0_axuser_cong_que_regs.h"
+#include "nic0_qpc0_axuser_db_fifo_regs.h"
+#include "nic0_qpc0_axuser_err_fifo_regs.h"
+#include "nic0_qpc0_axuser_ev_que_lbw_intr_regs.h"
+#include "nic0_qpc0_axuser_qpc_req_regs.h"
+#include "nic0_qpc0_axuser_qpc_resp_regs.h"
+#include "nic0_qpc0_axuser_rxwqe_regs.h"
+#include "nic0_qpc0_axuser_txwqe_lbw_qman_bp_regs.h"
+#include "nic0_qpc0_dbfifo0_ci_upd_addr_regs.h"
+#include "nic0_qpc0_dbfifosecur_ci_upd_addr_regs.h"
+#include "nic0_qpc0_masks.h"
+#include "nic0_qpc0_regs.h"
+#include "nic0_qpc1_regs.h"
+#include "nic0_rxb_core_masks.h"
+#include "nic0_rxb_core_regs.h"
+#include "nic0_rxe0_axuser_axuser_cq0_regs.h"
+#include "nic0_rxe0_axuser_axuser_cq1_regs.h"
+#include "nic0_rxe0_masks.h"
+#include "nic0_rxe0_regs.h"
+#include "nic0_rxe0_wqe_aruser_regs.h"
+#include "nic0_rxe1_regs.h"
+#include "nic0_serdes0_masks.h"
+#include "nic0_serdes0_regs.h"
+#include "nic0_serdes1_regs.h"
+#include "nic0_tmr_axuser_tmr_fifo_regs.h"
+#include "nic0_tmr_axuser_tmr_free_list_regs.h"
+#include "nic0_tmr_axuser_tmr_fsm_regs.h"
+#include "nic0_tmr_masks.h"
+#include "nic0_tmr_regs.h"
+#include "nic0_txb_regs.h"
+#include "nic0_txe0_masks.h"
+#include "nic0_txe0_regs.h"
+#include "nic0_txs0_masks.h"
+#include "nic0_txs0_regs.h"
+#include "nic0_umr0_0_completion_queue_ci_1_regs.h"
+#include "nic0_umr0_0_unsecure_doorbell0_regs.h"
+#include "nic0_umr0_0_unsecure_doorbell1_regs.h"
+#include "prt0_mac_core_masks.h"
+#include "prt0_mac_core_regs.h"
+
+#define NIC_OFFSET (NIC1_MSTR_IF_RR_SHRD_HBW_BASE - NIC0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define NIC_UMR_OFFSET \
+ (NIC0_UMR0_1_UNSECURE_DOORBELL0_BASE - NIC0_UMR0_0_UNSECURE_DOORBELL0_BASE)
+
+#endif /* ASIC_REG_GAUDI2_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_128_masks.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_128_masks.h
new file mode 100644
index 000000000000..da2510ec0612
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_128_masks.h
@@ -0,0 +1,339 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_MAC_CH0_MAC_128_MASKS_H_
+#define ASIC_REG_NIC0_MAC_CH0_MAC_128_MASKS_H_
+
+/*****************************************
+ * NIC0_MAC_CH0_MAC_128
+ * (Prototype: NIC_MAC_128)
+ *****************************************
+ */
+
+/* NIC0_MAC_CH0_MAC_128_REVISION */
+#define NIC0_MAC_CH0_MAC_128_REVISION_CORE_REVISION_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_REVISION_CORE_REVISION_MASK 0xFF
+#define NIC0_MAC_CH0_MAC_128_REVISION_CORE_VERSION_SHIFT 8
+#define NIC0_MAC_CH0_MAC_128_REVISION_CORE_VERSION_MASK 0xFF00
+#define NIC0_MAC_CH0_MAC_128_REVISION_CUSTOMER_REVISION_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_REVISION_CUSTOMER_REVISION_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_SCRATCH */
+#define NIC0_MAC_CH0_MAC_128_SCRATCH_SCRATCH_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_SCRATCH_SCRATCH_MASK 0xFFFFFFFF
+
+/* NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG */
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_TX_ENA_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_TX_ENA_MASK 0x1
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_RX_ENA_SHIFT 1
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_RX_ENA_MASK 0x2
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_MACCC_RSV2_SHIFT 2
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_MACCC_RSV2_MASK 0x4
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_MACCC_RSV3_SHIFT 3
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_MACCC_RSV3_MASK 0x8
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PROMIS_EN_SHIFT 4
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PROMIS_EN_MASK 0x10
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PAD_EN_SHIFT 5
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PAD_EN_MASK 0x20
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_CRC_FWD_SHIFT 6
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_CRC_FWD_MASK 0x40
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PAUSE_FWD_SHIFT 7
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PAUSE_FWD_MASK 0x80
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PAUSE_IGNORE_SHIFT 8
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PAUSE_IGNORE_MASK 0x100
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_TX_ADDR_INS_SHIFT 9
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_TX_ADDR_INS_MASK 0x200
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_LOOPBACK_EN_SHIFT 10
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_LOOPBACK_EN_MASK 0x400
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_TX_PAD_EN_SHIFT 11
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_TX_PAD_EN_MASK 0x800
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_SW_RESET_SHIFT 12
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_SW_RESET_MASK 0x1000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_CNTL_FRAME_ENA_SHIFT 13
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_CNTL_FRAME_ENA_MASK 0x2000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_RX_ERR_DISC_SHIFT 14
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_RX_ERR_DISC_MASK 0x4000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PHY_TXENA_SHIFT 15
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PHY_TXENA_MASK 0x8000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_SEND_IDLE_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_SEND_IDLE_MASK 0x10000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_NO_LGTH_CHECK_SHIFT 17
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_NO_LGTH_CHECK_MASK 0x20000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_RS_COL_CNT_EXT_SHIFT 18
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_RS_COL_CNT_EXT_MASK 0x40000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PFC_MODE_SHIFT 19
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PFC_MODE_MASK 0x80000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PAUSE_PFC_COMP_SHIFT 20
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PAUSE_PFC_COMP_MASK 0x100000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_RX_SFD_ANY_SHIFT 21
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_RX_SFD_ANY_MASK 0x200000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_TX_FLUSH_SHIFT 22
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_TX_FLUSH_MASK 0x400000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT 23
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_TX_LOWP_ENA_MASK 0x800000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_LOWP_RXEMPTY_SHIFT 24
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_LOWP_RXEMPTY_MASK 0x1000000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_MACCC_RSV25_SHIFT 25
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_MACCC_RSV25_MASK 0x2000000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_TX_FIFO_RESET_SHIFT 26
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_TX_FIFO_RESET_MASK 0x4000000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_FLT_HDL_DIS_SHIFT 27
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_FLT_HDL_DIS_MASK 0x8000000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_MACCC_RSV28_SHIFT 28
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_MACCC_RSV28_MASK 0x10000000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_MACCC_RSV29_SHIFT 29
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_MACCC_RSV29_MASK 0x20000000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_SHORT_PREAMBLE_SHIFT 30
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_SHORT_PREAMBLE_MASK 0x40000000
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_NO_PREAMBLE_SHIFT 31
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_NO_PREAMBLE_MASK 0x80000000
+
+/* NIC0_MAC_CH0_MAC_128_MAC_ADDR_0 */
+#define NIC0_MAC_CH0_MAC_128_MAC_ADDR_0_MAC_ADDRESS_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_MAC_ADDR_0_MAC_ADDRESS_0_MASK 0xFFFFFFFF
+
+/* NIC0_MAC_CH0_MAC_128_MAC_ADDR_1 */
+#define NIC0_MAC_CH0_MAC_128_MAC_ADDR_1_MAC_ADDRESS_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_MAC_ADDR_1_MAC_ADDRESS_1_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_128_FRM_LENGTH */
+#define NIC0_MAC_CH0_MAC_128_FRM_LENGTH_FRM_LENGTH_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_FRM_LENGTH_FRM_LENGTH_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_FRM_LENGTH_TX_MTU_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_FRM_LENGTH_TX_MTU_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_RX_FIFO_SECTIONS */
+#define NIC0_MAC_CH0_MAC_128_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_RX_FIFO_SECTIONS_RX_SECTION_FULL_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_RX_FIFO_SECTIONS_RX_SECTION_EMPTY_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_RX_FIFO_SECTIONS_RX_SECTION_EMPTY_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_TX_FIFO_SECTIONS */
+#define NIC0_MAC_CH0_MAC_128_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_TX_FIFO_SECTIONS_TX_SECTION_FULL_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_RX_FIFO_ALMOST_F_E */
+#define NIC0_MAC_CH0_MAC_128_RX_FIFO_ALMOST_F_E_RX_FIFO_ALMOST_EMPTY_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_RX_FIFO_ALMOST_F_E_RX_FIFO_ALMOST_EMPTY_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_RX_FIFO_ALMOST_F_E_RX_FIFO_ALMOST_FULL_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_RX_FIFO_ALMOST_F_E_RX_FIFO_ALMOST_FULL_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_TX_FIFO_ALMOST_F_E */
+#define NIC0_MAC_CH0_MAC_128_TX_FIFO_ALMOST_F_E_TX_FIFO_ALMOST_EMPTY_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_TX_FIFO_ALMOST_F_E_TX_FIFO_ALMOST_EMPTY_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_TX_FIFO_ALMOST_F_E_TX_FIFO_ALMOST_FULL_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_TX_FIFO_ALMOST_F_E_TX_FIFO_ALMOST_FULL_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_HASHTABLE_LOAD */
+#define NIC0_MAC_CH0_MAC_128_HASHTABLE_LOAD_FLD_0_DUMMY_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_HASHTABLE_LOAD_FLD_0_DUMMY_MASK 0x1F
+#define NIC0_MAC_CH0_MAC_128_HASHTABLE_LOAD_ENABLE_MULTICAST_FRAME_SHIFT 8
+#define NIC0_MAC_CH0_MAC_128_HASHTABLE_LOAD_ENABLE_MULTICAST_FRAME_MASK 0x100
+
+/* NIC0_MAC_CH0_MAC_128_MDIO_CFG_STATUS */
+#define NIC0_MAC_CH0_MAC_128_MDIO_CFG_STATUS_MDIO_BUSY_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_MDIO_CFG_STATUS_MDIO_BUSY_MASK 0x1
+#define NIC0_MAC_CH0_MAC_128_MDIO_CFG_STATUS_MDIO_READ_ERROR_SHIFT 1
+#define NIC0_MAC_CH0_MAC_128_MDIO_CFG_STATUS_MDIO_READ_ERROR_MASK 0x2
+#define NIC0_MAC_CH0_MAC_128_MDIO_CFG_STATUS_MDIO_HOLD_TIME_SETTING_SHIFT 2
+#define NIC0_MAC_CH0_MAC_128_MDIO_CFG_STATUS_MDIO_HOLD_TIME_SETTING_MASK 0x1C
+#define NIC0_MAC_CH0_MAC_128_MDIO_CFG_STATUS_MDIO_DISABLE_PREAMBLE_SHIFT 5
+#define NIC0_MAC_CH0_MAC_128_MDIO_CFG_STATUS_MDIO_DISABLE_PREAMBLE_MASK 0x20
+#define NIC0_MAC_CH0_MAC_128_MDIO_CFG_STATUS_MDIO_CLAUSE45_SHIFT 6
+#define NIC0_MAC_CH0_MAC_128_MDIO_CFG_STATUS_MDIO_CLAUSE45_MASK 0x40
+#define NIC0_MAC_CH0_MAC_128_MDIO_CFG_STATUS_MDIO_CLOCK_DIVISOR_SHIFT 7
+#define NIC0_MAC_CH0_MAC_128_MDIO_CFG_STATUS_MDIO_CLOCK_DIVISOR_MASK 0xFF80
+
+/* NIC0_MAC_CH0_MAC_128_MDIO_COMMAND */
+#define NIC0_MAC_CH0_MAC_128_MDIO_COMMAND_DEVICE_ADDRESS_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_MDIO_COMMAND_DEVICE_ADDRESS_MASK 0x1F
+#define NIC0_MAC_CH0_MAC_128_MDIO_COMMAND_PORT_ADDRESS_SHIFT 5
+#define NIC0_MAC_CH0_MAC_128_MDIO_COMMAND_PORT_ADDRESS_MASK 0x3E0
+#define NIC0_MAC_CH0_MAC_128_MDIO_COMMAND_READ_ADDRESS_POST_INCREMENT_SHIFT 14
+#define NIC0_MAC_CH0_MAC_128_MDIO_COMMAND_READ_ADDRESS_POST_INCREMENT_MASK 0x4000
+#define NIC0_MAC_CH0_MAC_128_MDIO_COMMAND_NORMAL_READ_TRANSACTION_SHIFT 15
+#define NIC0_MAC_CH0_MAC_128_MDIO_COMMAND_NORMAL_READ_TRANSACTION_MASK 0x8000
+
+/* NIC0_MAC_CH0_MAC_128_MDIO_DATA */
+#define NIC0_MAC_CH0_MAC_128_MDIO_DATA_MDIO_DATA_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_MDIO_DATA_MDIO_DATA_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_128_MDIO_REGADDR */
+#define NIC0_MAC_CH0_MAC_128_MDIO_REGADDR_MDIO_REGADDR_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_MDIO_REGADDR_MDIO_REGADDR_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_128_STATUS */
+#define NIC0_MAC_CH0_MAC_128_STATUS_RX_LOC_FAULT_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_STATUS_RX_LOC_FAULT_MASK 0x1
+#define NIC0_MAC_CH0_MAC_128_STATUS_RX_REM_FAULT_SHIFT 1
+#define NIC0_MAC_CH0_MAC_128_STATUS_RX_REM_FAULT_MASK 0x2
+#define NIC0_MAC_CH0_MAC_128_STATUS_PHY_LOS_SHIFT 2
+#define NIC0_MAC_CH0_MAC_128_STATUS_PHY_LOS_MASK 0x4
+#define NIC0_MAC_CH0_MAC_128_STATUS_TS_AVAIL_SHIFT 3
+#define NIC0_MAC_CH0_MAC_128_STATUS_TS_AVAIL_MASK 0x8
+#define NIC0_MAC_CH0_MAC_128_STATUS_RX_LOWP_SHIFT 4
+#define NIC0_MAC_CH0_MAC_128_STATUS_RX_LOWP_MASK 0x10
+#define NIC0_MAC_CH0_MAC_128_STATUS_TX_EMPTY_SHIFT 5
+#define NIC0_MAC_CH0_MAC_128_STATUS_TX_EMPTY_MASK 0x20
+#define NIC0_MAC_CH0_MAC_128_STATUS_RX_EMPTY_SHIFT 6
+#define NIC0_MAC_CH0_MAC_128_STATUS_RX_EMPTY_MASK 0x40
+#define NIC0_MAC_CH0_MAC_128_STATUS_RX_LINT_FAULT_SHIFT 7
+#define NIC0_MAC_CH0_MAC_128_STATUS_RX_LINT_FAULT_MASK 0x80
+#define NIC0_MAC_CH0_MAC_128_STATUS_TX_IS_IDLE_SHIFT 8
+#define NIC0_MAC_CH0_MAC_128_STATUS_TX_IS_IDLE_MASK 0x100
+
+/* NIC0_MAC_CH0_MAC_128_TX_IPG_LENGTH */
+#define NIC0_MAC_CH0_MAC_128_TX_IPG_LENGTH_TXIPG_DIC_DISABLE_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_TX_IPG_LENGTH_TXIPG_DIC_DISABLE_MASK 0x1
+#define NIC0_MAC_CH0_MAC_128_TX_IPG_LENGTH_TXIPG_RESERVED1_SHIFT 1
+#define NIC0_MAC_CH0_MAC_128_TX_IPG_LENGTH_TXIPG_RESERVED1_MASK 0x2
+#define NIC0_MAC_CH0_MAC_128_TX_IPG_LENGTH_TXIPG_RESERVED2_SHIFT 2
+#define NIC0_MAC_CH0_MAC_128_TX_IPG_LENGTH_TXIPG_RESERVED2_MASK 0x4
+#define NIC0_MAC_CH0_MAC_128_TX_IPG_LENGTH_TXIPG_SHIFT 3
+#define NIC0_MAC_CH0_MAC_128_TX_IPG_LENGTH_TXIPG_MASK 0x38
+#define NIC0_MAC_CH0_MAC_128_TX_IPG_LENGTH_COMPENSATION_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_TX_IPG_LENGTH_COMPENSATION_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CRC_MODE */
+#define NIC0_MAC_CH0_MAC_128_CRC_MODE_DISABLE_RX_CRC_CHECK_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CRC_MODE_DISABLE_RX_CRC_CHECK_MASK 0x10000
+#define NIC0_MAC_CH0_MAC_128_CRC_MODE_CRCSIZE_0_SHIFT 18
+#define NIC0_MAC_CH0_MAC_128_CRC_MODE_CRCSIZE_0_MASK 0x40000
+#define NIC0_MAC_CH0_MAC_128_CRC_MODE_CRCSIZE_1_SHIFT 19
+#define NIC0_MAC_CH0_MAC_128_CRC_MODE_CRCSIZE_1_MASK 0x80000
+#define NIC0_MAC_CH0_MAC_128_CRC_MODE_CRCSIZE_2_SHIFT 20
+#define NIC0_MAC_CH0_MAC_128_CRC_MODE_CRCSIZE_2_MASK 0x100000
+
+/* NIC0_MAC_CH0_MAC_128_INIT_CREDIT */
+#define NIC0_MAC_CH0_MAC_128_INIT_CREDIT_INITIALCREDIT_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_INIT_CREDIT_INITIALCREDIT_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_128_CREDIT_REG */
+#define NIC0_MAC_CH0_MAC_128_CREDIT_REG_CREDITS_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CREDIT_REG_CREDITS_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_128_CL01_PAUSE_QUANTA */
+#define NIC0_MAC_CH0_MAC_128_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CL23_PAUSE_QUANTA */
+#define NIC0_MAC_CH0_MAC_128_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CL45_PAUSE_QUANTA */
+#define NIC0_MAC_CH0_MAC_128_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CL67_PAUSE_QUANTA */
+#define NIC0_MAC_CH0_MAC_128_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CL01_QUANTA_THRESH */
+#define NIC0_MAC_CH0_MAC_128_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CL23_QUANTA_THRESH */
+#define NIC0_MAC_CH0_MAC_128_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CL45_QUANTA_THRESH */
+#define NIC0_MAC_CH0_MAC_128_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CL67_QUANTA_THRESH */
+#define NIC0_MAC_CH0_MAC_128_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_RX_PAUSE_STATUS */
+#define NIC0_MAC_CH0_MAC_128_RX_PAUSE_STATUS_PAUSESTATUS_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_RX_PAUSE_STATUS_PAUSESTATUS_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_128_TS_TIMESTAMP */
+#define NIC0_MAC_CH0_MAC_128_TS_TIMESTAMP_TS_TIMESTAMP_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_TS_TIMESTAMP_TS_TIMESTAMP_MASK 0xFFFFFFFF
+
+/* NIC0_MAC_CH0_MAC_128_XIF_MODE */
+#define NIC0_MAC_CH0_MAC_128_XIF_MODE_XGMII_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_XIF_MODE_XGMII_MASK 0x1
+#define NIC0_MAC_CH0_MAC_128_XIF_MODE_PAUSETIMERX8_SHIFT 4
+#define NIC0_MAC_CH0_MAC_128_XIF_MODE_PAUSETIMERX8_MASK 0x10
+#define NIC0_MAC_CH0_MAC_128_XIF_MODE_ONESTEPENA_SHIFT 5
+#define NIC0_MAC_CH0_MAC_128_XIF_MODE_ONESTEPENA_MASK 0x20
+
+/* NIC0_MAC_CH0_MAC_128_CL89_PAUSE_QUANTA */
+#define NIC0_MAC_CH0_MAC_128_CL89_PAUSE_QUANTA_CL8_PAUSE_QUANTA_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL89_PAUSE_QUANTA_CL8_PAUSE_QUANTA_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL89_PAUSE_QUANTA_CL9_PAUSE_QUANTA_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL89_PAUSE_QUANTA_CL9_PAUSE_QUANTA_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CL1011_PAUSE_QUANTA */
+#define NIC0_MAC_CH0_MAC_128_CL1011_PAUSE_QUANTA_CL10_PAUSE_QUANTA_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL1011_PAUSE_QUANTA_CL10_PAUSE_QUANTA_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL1011_PAUSE_QUANTA_CL11_PAUSE_QUANTA_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL1011_PAUSE_QUANTA_CL11_PAUSE_QUANTA_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CL1213_PAUSE_QUANTA */
+#define NIC0_MAC_CH0_MAC_128_CL1213_PAUSE_QUANTA_CL12_PAUSE_QUANTA_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL1213_PAUSE_QUANTA_CL12_PAUSE_QUANTA_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL1213_PAUSE_QUANTA_CL13_PAUSE_QUANTA_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL1213_PAUSE_QUANTA_CL13_PAUSE_QUANTA_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CL1415_PAUSE_QUANTA */
+#define NIC0_MAC_CH0_MAC_128_CL1415_PAUSE_QUANTA_CL14_PAUSE_QUANTA_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL1415_PAUSE_QUANTA_CL14_PAUSE_QUANTA_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL1415_PAUSE_QUANTA_CL15_PAUSE_QUANTA_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL1415_PAUSE_QUANTA_CL15_PAUSE_QUANTA_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CL89_QUANTA_THRESH */
+#define NIC0_MAC_CH0_MAC_128_CL89_QUANTA_THRESH_CL8_QUANTA_THRESH_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL89_QUANTA_THRESH_CL8_QUANTA_THRESH_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL89_QUANTA_THRESH_CL9_QUANTA_THRESH_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL89_QUANTA_THRESH_CL9_QUANTA_THRESH_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CL1011_QUANTA_THRESH */
+#define NIC0_MAC_CH0_MAC_128_CL1011_QUANTA_THRESH_CL10_QUANTA_THRESH_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL1011_QUANTA_THRESH_CL10_QUANTA_THRESH_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL1011_QUANTA_THRESH_CL11_QUANTA_THRESH_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL1011_QUANTA_THRESH_CL11_QUANTA_THRESH_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CL1213_QUANTA_THRESH */
+#define NIC0_MAC_CH0_MAC_128_CL1213_QUANTA_THRESH_CL12_QUANTA_THRESH_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL1213_QUANTA_THRESH_CL12_QUANTA_THRESH_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL1213_QUANTA_THRESH_CL13_QUANTA_THRESH_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL1213_QUANTA_THRESH_CL13_QUANTA_THRESH_MASK 0xFFFF0000
+
+/* NIC0_MAC_CH0_MAC_128_CL1415_QUANTA_THRESH */
+#define NIC0_MAC_CH0_MAC_128_CL1415_QUANTA_THRESH_CL14_QUANTA_THRESH_SHIFT 0
+#define NIC0_MAC_CH0_MAC_128_CL1415_QUANTA_THRESH_CL14_QUANTA_THRESH_MASK 0xFFFF
+#define NIC0_MAC_CH0_MAC_128_CL1415_QUANTA_THRESH_CL15_QUANTA_THRESH_SHIFT 16
+#define NIC0_MAC_CH0_MAC_128_CL1415_QUANTA_THRESH_CL15_QUANTA_THRESH_MASK 0xFFFF0000
+
+#endif /* ASIC_REG_NIC0_MAC_CH0_MAC_128_MASKS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_128_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_128_regs.h
new file mode 100644
index 000000000000..fd1729f9df5e
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_128_regs.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_MAC_CH0_MAC_128_REGS_H_
+#define ASIC_REG_NIC0_MAC_CH0_MAC_128_REGS_H_
+
+/*****************************************
+ * NIC0_MAC_CH0_MAC_128
+ * (Prototype: NIC_MAC_128)
+ *****************************************
+ */
+
+#define NIC0_MAC_CH0_MAC_128_REVISION 0x546C400
+
+#define NIC0_MAC_CH0_MAC_128_SCRATCH 0x546C404
+
+#define NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG 0x546C408
+
+#define NIC0_MAC_CH0_MAC_128_MAC_ADDR_0 0x546C40C
+
+#define NIC0_MAC_CH0_MAC_128_MAC_ADDR_1 0x546C410
+
+#define NIC0_MAC_CH0_MAC_128_FRM_LENGTH 0x546C414
+
+#define NIC0_MAC_CH0_MAC_128_RX_FIFO_SECTIONS 0x546C41C
+
+#define NIC0_MAC_CH0_MAC_128_TX_FIFO_SECTIONS 0x546C420
+
+#define NIC0_MAC_CH0_MAC_128_RX_FIFO_ALMOST_F_E 0x546C424
+
+#define NIC0_MAC_CH0_MAC_128_TX_FIFO_ALMOST_F_E 0x546C428
+
+#define NIC0_MAC_CH0_MAC_128_HASHTABLE_LOAD 0x546C42C
+
+#define NIC0_MAC_CH0_MAC_128_MDIO_CFG_STATUS 0x546C430
+
+#define NIC0_MAC_CH0_MAC_128_MDIO_COMMAND 0x546C434
+
+#define NIC0_MAC_CH0_MAC_128_MDIO_DATA 0x546C438
+
+#define NIC0_MAC_CH0_MAC_128_MDIO_REGADDR 0x546C43C
+
+#define NIC0_MAC_CH0_MAC_128_STATUS 0x546C440
+
+#define NIC0_MAC_CH0_MAC_128_TX_IPG_LENGTH 0x546C444
+
+#define NIC0_MAC_CH0_MAC_128_CRC_MODE 0x546C448
+
+#define NIC0_MAC_CH0_MAC_128_INIT_CREDIT 0x546C44C
+
+#define NIC0_MAC_CH0_MAC_128_CREDIT_REG 0x546C450
+
+#define NIC0_MAC_CH0_MAC_128_CL01_PAUSE_QUANTA 0x546C454
+
+#define NIC0_MAC_CH0_MAC_128_CL23_PAUSE_QUANTA 0x546C458
+
+#define NIC0_MAC_CH0_MAC_128_CL45_PAUSE_QUANTA 0x546C45C
+
+#define NIC0_MAC_CH0_MAC_128_CL67_PAUSE_QUANTA 0x546C460
+
+#define NIC0_MAC_CH0_MAC_128_CL01_QUANTA_THRESH 0x546C464
+
+#define NIC0_MAC_CH0_MAC_128_CL23_QUANTA_THRESH 0x546C468
+
+#define NIC0_MAC_CH0_MAC_128_CL45_QUANTA_THRESH 0x546C46C
+
+#define NIC0_MAC_CH0_MAC_128_CL67_QUANTA_THRESH 0x546C470
+
+#define NIC0_MAC_CH0_MAC_128_RX_PAUSE_STATUS 0x546C474
+
+#define NIC0_MAC_CH0_MAC_128_TS_TIMESTAMP 0x546C47C
+
+#define NIC0_MAC_CH0_MAC_128_XIF_MODE 0x546C480
+
+#define NIC0_MAC_CH0_MAC_128_CL89_PAUSE_QUANTA 0x546C484
+
+#define NIC0_MAC_CH0_MAC_128_CL1011_PAUSE_QUANTA 0x546C488
+
+#define NIC0_MAC_CH0_MAC_128_CL1213_PAUSE_QUANTA 0x546C48C
+
+#define NIC0_MAC_CH0_MAC_128_CL1415_PAUSE_QUANTA 0x546C490
+
+#define NIC0_MAC_CH0_MAC_128_CL89_QUANTA_THRESH 0x546C494
+
+#define NIC0_MAC_CH0_MAC_128_CL1011_QUANTA_THRESH 0x546C498
+
+#define NIC0_MAC_CH0_MAC_128_CL1213_QUANTA_THRESH 0x546C49C
+
+#define NIC0_MAC_CH0_MAC_128_CL1415_QUANTA_THRESH 0x546C4A0
+
+#endif /* ASIC_REG_NIC0_MAC_CH0_MAC_128_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_pcs_masks.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_pcs_masks.h
new file mode 100644
index 000000000000..d925829ab0cf
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_pcs_masks.h
@@ -0,0 +1,713 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_MAC_CH0_MAC_PCS_MASKS_H_
+#define ASIC_REG_NIC0_MAC_CH0_MAC_PCS_MASKS_H_
+
+/*****************************************
+ * NIC0_MAC_CH0_MAC_PCS
+ * (Prototype: NIC_XPCS91)
+ *****************************************
+ */
+
+/* NIC0_MAC_CH0_MAC_PCS_CONTROL1 */
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL1_SPEED_SELECTION_SHIFT 2
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL1_SPEED_SELECTION_MASK 0x3C
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL1_SPEED_ALWAYS1_SHIFT 6
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL1_SPEED_ALWAYS1_MASK 0x40
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL1_LOW_POWER_SHIFT 11
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL1_LOW_POWER_MASK 0x800
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL1_SPEED_SELECT_ALWAYS1_SHIFT 13
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL1_SPEED_SELECT_ALWAYS1_MASK 0x2000
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL1_LOOPBACK_SHIFT 14
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL1_LOOPBACK_MASK 0x4000
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL1_FLD_RESET_SHIFT 15
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL1_FLD_RESET_MASK 0x8000
+
+/* NIC0_MAC_CH0_MAC_PCS_STATUS1 */
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1_LOW_POWER_ABILITY_SHIFT 1
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1_LOW_POWER_ABILITY_MASK 0x2
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1_PCS_RECEIVE_LINK_SHIFT 2
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1_PCS_RECEIVE_LINK_MASK 0x4
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1_FAULT_SHIFT 7
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1_FAULT_MASK 0x80
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1_RX_LPI_ACTIVE_SHIFT 8
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1_RX_LPI_ACTIVE_MASK 0x100
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1_TX_LPI_ACTIVE_SHIFT 9
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1_TX_LPI_ACTIVE_MASK 0x200
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1_RX_LPI_SHIFT 10
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1_RX_LPI_MASK 0x400
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1_TX_LPI_SHIFT 11
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1_TX_LPI_MASK 0x800
+
+/* NIC0_MAC_CH0_MAC_PCS_DEVICE_ID0 */
+#define NIC0_MAC_CH0_MAC_PCS_DEVICE_ID0_IDENTIFIER0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_DEVICE_ID0_IDENTIFIER0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_DEVICE_ID1 */
+#define NIC0_MAC_CH0_MAC_PCS_DEVICE_ID1_IDENTIFIER1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_DEVICE_ID1_IDENTIFIER1_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_SPEED_ABILITY */
+#define NIC0_MAC_CH0_MAC_PCS_SPEED_ABILITY_C10GETH_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_SPEED_ABILITY_C10GETH_MASK 0x1
+#define NIC0_MAC_CH0_MAC_PCS_SPEED_ABILITY_C10PASS_TS_SHIFT 1
+#define NIC0_MAC_CH0_MAC_PCS_SPEED_ABILITY_C10PASS_TS_MASK 0x2
+#define NIC0_MAC_CH0_MAC_PCS_SPEED_ABILITY_C40G_SHIFT 2
+#define NIC0_MAC_CH0_MAC_PCS_SPEED_ABILITY_C40G_MASK 0x4
+#define NIC0_MAC_CH0_MAC_PCS_SPEED_ABILITY_C100G_SHIFT 3
+#define NIC0_MAC_CH0_MAC_PCS_SPEED_ABILITY_C100G_MASK 0x8
+#define NIC0_MAC_CH0_MAC_PCS_SPEED_ABILITY_C25G_SHIFT 4
+#define NIC0_MAC_CH0_MAC_PCS_SPEED_ABILITY_C25G_MASK 0x10
+#define NIC0_MAC_CH0_MAC_PCS_SPEED_ABILITY_C50G_SHIFT 5
+#define NIC0_MAC_CH0_MAC_PCS_SPEED_ABILITY_C50G_MASK 0x20
+
+/* NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1 */
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1_CLAUSE22_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1_CLAUSE22_MASK 0x1
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1_PMD_PMA_SHIFT 1
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1_PMD_PMA_MASK 0x2
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1_WIS_PRES_SHIFT 2
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1_WIS_PRES_MASK 0x4
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1_PCS_PRES_SHIFT 3
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1_PCS_PRES_MASK 0x8
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1_PHY_XS_SHIFT 4
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1_PHY_XS_MASK 0x10
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1_DTE_XS_SHIFT 5
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1_DTE_XS_MASK 0x20
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1_TC_PRES_SHIFT 6
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1_TC_PRES_MASK 0x40
+
+/* NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG2 */
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG2_CLAUSE22_SHIFT 13
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG2_CLAUSE22_MASK 0x2000
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG2_DEVICE1_SHIFT 14
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG2_DEVICE1_MASK 0x4000
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG2_DEVICE2_SHIFT 15
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG2_DEVICE2_MASK 0x8000
+
+/* NIC0_MAC_CH0_MAC_PCS_CONTROL2 */
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL2_PCS_TYPE_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL2_PCS_TYPE_MASK 0xF
+
+/* NIC0_MAC_CH0_MAC_PCS_STATUS2 */
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C10GBASE_R_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C10GBASE_R_MASK 0x1
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C10GBASE_X_SHIFT 1
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C10GBASE_X_MASK 0x2
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C10GBASE_W_SHIFT 2
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C10GBASE_W_MASK 0x4
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C10GBASE_T_SHIFT 3
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C10GBASE_T_MASK 0x8
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C40GBASE_R_SHIFT 4
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C40GBASE_R_MASK 0x10
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C100GBASE_R_SHIFT 5
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C100GBASE_R_MASK 0x20
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C25GBASE_R_SHIFT 7
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C25GBASE_R_MASK 0x80
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C50GBASE_R_SHIFT 8
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_C50GBASE_R_MASK 0x100
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_RECEIVE_FAULT_SHIFT 10
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_RECEIVE_FAULT_MASK 0x400
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_TRANSMIT_FAULT_SHIFT 11
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_TRANSMIT_FAULT_MASK 0x800
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_DEVICE_PRESENT_SHIFT 14
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2_DEVICE_PRESENT_MASK 0xC000
+
+/* NIC0_MAC_CH0_MAC_PCS_PKG_ID0 */
+#define NIC0_MAC_CH0_MAC_PCS_PKG_ID0_IDENTIFIER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_PKG_ID0_IDENTIFIER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_PKG_ID1 */
+#define NIC0_MAC_CH0_MAC_PCS_PKG_ID1_IDENTIFIER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_PKG_ID1_IDENTIFIER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY */
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_LPI_FW_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_LPI_FW_MASK 0x1
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_EEE_10GBASE_KR_SHIFT 6
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_EEE_10GBASE_KR_MASK 0x40
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_EEE_40GBASE_RAWAKE_SHIFT 8
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_EEE_40GBASE_RAWAKE_MASK 0x100
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_EEE_40GBASE_RSLEEP_SHIFT 9
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_EEE_40GBASE_RSLEEP_MASK 0x200
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_EEE_25GBASE_RAWAKE_SHIFT 10
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_EEE_25GBASE_RAWAKE_MASK 0x400
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_EEE_25GBASE_RSLEEP_SHIFT 11
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_EEE_25GBASE_RSLEEP_MASK 0x800
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_EEE_100GBASE_RAWAKE_SHIFT 12
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_EEE_100GBASE_RAWAKE_MASK 0x1000
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_EEE_50GBASE_RAWAKE_SHIFT 14
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY_EEE_50GBASE_RAWAKE_MASK 0x4000
+
+/* NIC0_MAC_CH0_MAC_PCS_WAKE_ERR_COUNTER */
+#define NIC0_MAC_CH0_MAC_PCS_WAKE_ERR_COUNTER_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_WAKE_ERR_COUNTER_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BASER_STATUS1 */
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS1_BLOCK_LOCK_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS1_BLOCK_LOCK_MASK 0x1
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS1_HIGH_BER_SHIFT 1
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS1_HIGH_BER_MASK 0x2
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS1_RECEIVE_LINK_SHIFT 12
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS1_RECEIVE_LINK_MASK 0x1000
+
+/* NIC0_MAC_CH0_MAC_PCS_BASER_STATUS2 */
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS2_ERRORED_CNT_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS2_ERRORED_CNT_MASK 0xFF
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS2_BER_COUNTER_SHIFT 8
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS2_BER_COUNTER_MASK 0x3F00
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS2_HIGH_BER_SHIFT 14
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS2_HIGH_BER_MASK 0x4000
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS2_BLOCK_LOCK_SHIFT 15
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS2_BLOCK_LOCK_MASK 0x8000
+
+/* NIC0_MAC_CH0_MAC_PCS_SEED_A0 */
+#define NIC0_MAC_CH0_MAC_PCS_SEED_A0_SEED_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_SEED_A0_SEED_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_SEED_A1 */
+#define NIC0_MAC_CH0_MAC_PCS_SEED_A1_SEED_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_SEED_A1_SEED_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_SEED_A2 */
+#define NIC0_MAC_CH0_MAC_PCS_SEED_A2_SEED_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_SEED_A2_SEED_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_SEED_A3 */
+#define NIC0_MAC_CH0_MAC_PCS_SEED_A3_SEED_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_SEED_A3_SEED_MASK 0x3FF
+
+/* NIC0_MAC_CH0_MAC_PCS_SEED_B0 */
+#define NIC0_MAC_CH0_MAC_PCS_SEED_B0_SEED_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_SEED_B0_SEED_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_SEED_B1 */
+#define NIC0_MAC_CH0_MAC_PCS_SEED_B1_SEED_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_SEED_B1_SEED_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_SEED_B2 */
+#define NIC0_MAC_CH0_MAC_PCS_SEED_B2_SEED_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_SEED_B2_SEED_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_SEED_B3 */
+#define NIC0_MAC_CH0_MAC_PCS_SEED_B3_SEED_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_SEED_B3_SEED_MASK 0x3FF
+
+/* NIC0_MAC_CH0_MAC_PCS_BASER_TEST_CONTROL */
+#define NIC0_MAC_CH0_MAC_PCS_BASER_TEST_CONTROL_DATA_PATTERN_SEL_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BASER_TEST_CONTROL_DATA_PATTERN_SEL_MASK 0x1
+#define NIC0_MAC_CH0_MAC_PCS_BASER_TEST_CONTROL_SELECT_SQUARE_SHIFT 1
+#define NIC0_MAC_CH0_MAC_PCS_BASER_TEST_CONTROL_SELECT_SQUARE_MASK 0x2
+#define NIC0_MAC_CH0_MAC_PCS_BASER_TEST_CONTROL_RX_TESTPATTERN_SHIFT 2
+#define NIC0_MAC_CH0_MAC_PCS_BASER_TEST_CONTROL_RX_TESTPATTERN_MASK 0x4
+#define NIC0_MAC_CH0_MAC_PCS_BASER_TEST_CONTROL_TX_TESTPATTERN_SHIFT 3
+#define NIC0_MAC_CH0_MAC_PCS_BASER_TEST_CONTROL_TX_TESTPATTERN_MASK 0x8
+#define NIC0_MAC_CH0_MAC_PCS_BASER_TEST_CONTROL_SELECT_RANDOM_SHIFT 7
+#define NIC0_MAC_CH0_MAC_PCS_BASER_TEST_CONTROL_SELECT_RANDOM_MASK 0x80
+
+/* NIC0_MAC_CH0_MAC_PCS_BASER_TEST_ERR_CNT */
+#define NIC0_MAC_CH0_MAC_PCS_BASER_TEST_ERR_CNT_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BASER_TEST_ERR_CNT_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BER_HIGH_ORDER_CNT */
+#define NIC0_MAC_CH0_MAC_PCS_BER_HIGH_ORDER_CNT_BER_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BER_HIGH_ORDER_CNT_BER_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_ERR_BLK_HIGH_ORDER_CNT */
+#define NIC0_MAC_CH0_MAC_PCS_ERR_BLK_HIGH_ORDER_CNT_ERRORED_BLOCKS_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_ERR_BLK_HIGH_ORDER_CNT_ERRORED_BLOCKS_COUNTER_MASK 0x3FFF
+#define NIC0_MAC_CH0_MAC_PCS_ERR_BLK_HIGH_ORDER_CNT_HIGH_ORDER_PRESENT_SHIFT 15
+#define NIC0_MAC_CH0_MAC_PCS_ERR_BLK_HIGH_ORDER_CNT_HIGH_ORDER_PRESENT_MASK 0x8000
+
+/* NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1 */
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE0_BLOCK_LOCK_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE0_BLOCK_LOCK_MASK 0x1
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE1_BLOCK_LOCK_SHIFT 1
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE1_BLOCK_LOCK_MASK 0x2
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE2_BLOCK_LOCK_SHIFT 2
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE2_BLOCK_LOCK_MASK 0x4
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE3_BLOCK_LOCK_SHIFT 3
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE3_BLOCK_LOCK_MASK 0x8
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE4_BLOCK_LOCK_SHIFT 4
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE4_BLOCK_LOCK_MASK 0x10
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE5_BLOCK_LOCK_SHIFT 5
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE5_BLOCK_LOCK_MASK 0x20
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE6_BLOCK_LOCK_SHIFT 6
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE6_BLOCK_LOCK_MASK 0x40
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE7_BLOCK_LOCK_SHIFT 7
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE7_BLOCK_LOCK_MASK 0x80
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE_ALIGN_STATUS_SHIFT 12
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1_LANE_ALIGN_STATUS_MASK 0x1000
+
+/* NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2 */
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE8_BLOCK_LOCK_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE8_BLOCK_LOCK_MASK 0x1
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE9_BLOCK_LOCK_SHIFT 1
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE9_BLOCK_LOCK_MASK 0x2
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE10_BLOCK_LOCK_SHIFT 2
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE10_BLOCK_LOCK_MASK 0x4
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE11_BLOCK_LOCK_SHIFT 3
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE11_BLOCK_LOCK_MASK 0x8
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE12_BLOCK_LOCK_SHIFT 4
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE12_BLOCK_LOCK_MASK 0x10
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE13_BLOCK_LOCK_SHIFT 5
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE13_BLOCK_LOCK_MASK 0x20
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE14_BLOCK_LOCK_SHIFT 6
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE14_BLOCK_LOCK_MASK 0x40
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE15_BLOCK_LOCK_SHIFT 7
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE15_BLOCK_LOCK_MASK 0x80
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE16_BLOCK_LOCK_SHIFT 8
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE16_BLOCK_LOCK_MASK 0x100
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE17_BLOCK_LOCK_SHIFT 9
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE17_BLOCK_LOCK_MASK 0x200
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE18_BLOCK_LOCK_SHIFT 10
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE18_BLOCK_LOCK_MASK 0x400
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE19_BLOCK_LOCK_SHIFT 11
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2_LANE19_BLOCK_LOCK_MASK 0x800
+
+/* NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3 */
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE0_ALIGN_MLOCK_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE0_ALIGN_MLOCK_MASK 0x1
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE1_ALIGN_MLOCK_SHIFT 1
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE1_ALIGN_MLOCK_MASK 0x2
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE2_ALIGN_MLOCK_SHIFT 2
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE2_ALIGN_MLOCK_MASK 0x4
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE3_ALIGN_MLOCK_SHIFT 3
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE3_ALIGN_MLOCK_MASK 0x8
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE4_ALIGN_MLOCK_SHIFT 4
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE4_ALIGN_MLOCK_MASK 0x10
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE5_ALIGN_MLOCK_SHIFT 5
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE5_ALIGN_MLOCK_MASK 0x20
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE6_ALIGN_MLOCK_SHIFT 6
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE6_ALIGN_MLOCK_MASK 0x40
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE7_ALIGN_MLOCK_SHIFT 7
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3_LANE7_ALIGN_MLOCK_MASK 0x80
+
+/* NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4 */
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE8_ALIGN_MLOCK_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE8_ALIGN_MLOCK_MASK 0x1
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE9_ALIGN_MLOCK_SHIFT 1
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE9_ALIGN_MLOCK_MASK 0x2
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE10_ALIGN_MLOCK_SHIFT 2
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE10_ALIGN_MLOCK_MASK 0x4
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE11_ALIGN_MLOCK_SHIFT 3
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE11_ALIGN_MLOCK_MASK 0x8
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE12_ALIGN_MLOCK_SHIFT 4
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE12_ALIGN_MLOCK_MASK 0x10
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE13_ALIGN_MLOCK_SHIFT 5
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE13_ALIGN_MLOCK_MASK 0x20
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE14_ALIGN_MLOCK_SHIFT 6
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE14_ALIGN_MLOCK_MASK 0x40
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE15_ALIGN_MLOCK_SHIFT 7
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE15_ALIGN_MLOCK_MASK 0x80
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE16_ALIGN_MLOCK_SHIFT 8
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE16_ALIGN_MLOCK_MASK 0x100
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE17_ALIGN_MLOCK_SHIFT 9
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE17_ALIGN_MLOCK_MASK 0x200
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE18_ALIGN_MLOCK_SHIFT 10
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE18_ALIGN_MLOCK_MASK 0x400
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE19_ALIGN_MLOCK_SHIFT 11
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4_LANE19_ALIGN_MLOCK_MASK 0x800
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE0 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE0_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE0_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE1 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE1_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE1_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE2 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE2_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE2_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE3 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE3_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE3_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE4 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE4_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE4_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE5 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE5_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE5_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE6 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE6_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE6_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE7 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE7_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE7_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE8 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE8_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE8_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE9 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE9_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE9_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE10 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE10_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE10_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE11 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE11_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE11_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE12 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE12_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE12_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE13 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE13_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE13_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE14 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE14_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE14_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE15 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE15_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE15_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE16 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE16_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE16_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE17 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE17_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE17_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE18 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE18_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE18_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE19 */
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE19_ERROR_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE19_ERROR_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE0_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE0_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE0_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE1_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE1_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE1_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE2_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE2_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE2_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE3_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE3_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE3_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE4_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE4_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE4_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE5_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE5_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE5_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE6_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE6_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE6_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE7_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE7_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE7_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE8_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE8_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE8_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE9_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE9_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE9_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE10_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE10_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE10_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE11_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE11_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE11_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE12_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE12_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE12_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE13_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE13_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE13_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE14_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE14_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE14_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE15_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE15_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE15_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE16_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE16_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE16_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE17_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE17_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE17_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE18_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE18_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE18_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_LANE19_MAPPING */
+#define NIC0_MAC_CH0_MAC_PCS_LANE19_MAPPING_MAPPING_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_LANE19_MAPPING_MAPPING_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VENDOR_SCRATCH */
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_SCRATCH_SCRATCH_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_SCRATCH_SCRATCH_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VENDOR_CORE_REV */
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_CORE_REV_REVISION_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_CORE_REV_REVISION_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VENDOR_VL_INTVL */
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL_INTVL_MARKER_COUNTER_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL_INTVL_MARKER_COUNTER_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VENDOR_TXLANE_THRESH */
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_TXLANE_THRESH_THRESHOLD4_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_TXLANE_THRESH_THRESHOLD4_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0_M0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0_M0_MASK 0xFF
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0_M1_SHIFT 8
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0_M1_MASK 0xFF00
+
+/* NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_1_M2_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_1_M2_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0_M0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0_M0_MASK 0xFF
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0_M1_SHIFT 8
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0_M1_MASK 0xFF00
+
+/* NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_1_M2_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_1_M2_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0_M0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0_M0_MASK 0xFF
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0_M1_SHIFT 8
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0_M1_MASK 0xFF00
+
+/* NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_1_M2_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_1_M2_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0_M0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0_M0_MASK 0xFF
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0_M1_SHIFT 8
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0_M1_MASK 0xFF00
+
+/* NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_1_M2_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_1_M2_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE */
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE_ENA_CLAUSE49_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE_ENA_CLAUSE49_MASK 0x1
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE_DISABLE_MLD_SHIFT 1
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE_DISABLE_MLD_MASK 0x2
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE_HI_BER25_SHIFT 2
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE_HI_BER25_MASK 0x4
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE_HI_BER5_SHIFT 3
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE_HI_BER5_MASK 0x8
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE_ST_ENA_CLAUSE49_SHIFT 8
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE_ST_ENA_CLAUSE49_MASK 0x100
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE_ST_DISABLE_MLD_SHIFT 9
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE_ST_DISABLE_MLD_MASK 0x200
+
+/* NIC0_MAC_CH0_MAC_PCS_VL0_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL0_0_VL0_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL0_0_VL0_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL0_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL0_1_VL0_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL0_1_VL0_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL1_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL1_0_VL1_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL1_0_VL1_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL1_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL1_1_VL1_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL1_1_VL1_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL2_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL2_0_VL2_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL2_0_VL2_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL2_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL2_1_VL2_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL2_1_VL2_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL3_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL3_0_VL3_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL3_0_VL3_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL3_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL3_1_VL3_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL3_1_VL3_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL4_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL4_0_VL4_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL4_0_VL4_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL4_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL4_1_VL4_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL4_1_VL4_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL5_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL5_0_VL5_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL5_0_VL5_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL5_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL5_1_VL5_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL5_1_VL5_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL6_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL6_0_VL6_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL6_0_VL6_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL6_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL6_1_VL6_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL6_1_VL6_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL7_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL7_0_VL7_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL7_0_VL7_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL7_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL7_1_VL7_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL7_1_VL7_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL8_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL8_0_VL8_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL8_0_VL8_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL8_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL8_1_VL8_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL8_1_VL8_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL9_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL9_0_VL9_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL9_0_VL9_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL9_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL9_1_VL9_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL9_1_VL9_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL10_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL10_0_VL10_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL10_0_VL10_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL10_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL10_1_VL10_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL10_1_VL10_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL11_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL11_0_VL11_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL11_0_VL11_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL11_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL11_1_VL11_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL11_1_VL11_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL12_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL12_0_VL12_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL12_0_VL12_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL12_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL12_1_VL12_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL12_1_VL12_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL13_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL13_0_VL13_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL13_0_VL13_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL13_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL13_1_VL13_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL13_1_VL13_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL14_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL14_0_VL14_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL14_0_VL14_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL14_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL14_1_VL14_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL14_1_VL14_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL15_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL15_0_VL15_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL15_0_VL15_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL15_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL15_1_VL15_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL15_1_VL15_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL16_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL16_0_VL16_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL16_0_VL16_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL16_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL16_1_VL16_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL16_1_VL16_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL17_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL17_0_VL17_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL17_0_VL17_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL17_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL17_1_VL17_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL17_1_VL17_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL18_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL18_0_VL18_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL18_0_VL18_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL18_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL18_1_VL18_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL18_1_VL18_1_MASK 0xFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL19_0 */
+#define NIC0_MAC_CH0_MAC_PCS_VL19_0_VL19_0_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL19_0_VL19_0_MASK 0xFFFF
+
+/* NIC0_MAC_CH0_MAC_PCS_VL19_1 */
+#define NIC0_MAC_CH0_MAC_PCS_VL19_1_VL19_1_SHIFT 0
+#define NIC0_MAC_CH0_MAC_PCS_VL19_1_VL19_1_MASK 0xFF
+
+#endif /* ASIC_REG_NIC0_MAC_CH0_MAC_PCS_MASKS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_pcs_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_pcs_regs.h
new file mode 100644
index 000000000000..8a4916d547bb
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_pcs_regs.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_MAC_CH0_MAC_PCS_REGS_H_
+#define ASIC_REG_NIC0_MAC_CH0_MAC_PCS_REGS_H_
+
+/*****************************************
+ * NIC0_MAC_CH0_MAC_PCS
+ * (Prototype: NIC_XPCS91)
+ *****************************************
+ */
+
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL1 0x546C000
+
+#define NIC0_MAC_CH0_MAC_PCS_STATUS1 0x546C004
+
+#define NIC0_MAC_CH0_MAC_PCS_DEVICE_ID0 0x546C008
+
+#define NIC0_MAC_CH0_MAC_PCS_DEVICE_ID1 0x546C00C
+
+#define NIC0_MAC_CH0_MAC_PCS_SPEED_ABILITY 0x546C010
+
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG1 0x546C014
+
+#define NIC0_MAC_CH0_MAC_PCS_DEVICES_IN_PKG2 0x546C018
+
+#define NIC0_MAC_CH0_MAC_PCS_CONTROL2 0x546C01C
+
+#define NIC0_MAC_CH0_MAC_PCS_STATUS2 0x546C020
+
+#define NIC0_MAC_CH0_MAC_PCS_PKG_ID0 0x546C038
+
+#define NIC0_MAC_CH0_MAC_PCS_PKG_ID1 0x546C03C
+
+#define NIC0_MAC_CH0_MAC_PCS_EEE_CTRL_CAPABILITY 0x546C050
+
+#define NIC0_MAC_CH0_MAC_PCS_WAKE_ERR_COUNTER 0x546C058
+
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS1 0x546C080
+
+#define NIC0_MAC_CH0_MAC_PCS_BASER_STATUS2 0x546C084
+
+#define NIC0_MAC_CH0_MAC_PCS_SEED_A0 0x546C088
+
+#define NIC0_MAC_CH0_MAC_PCS_SEED_A1 0x546C08C
+
+#define NIC0_MAC_CH0_MAC_PCS_SEED_A2 0x546C090
+
+#define NIC0_MAC_CH0_MAC_PCS_SEED_A3 0x546C094
+
+#define NIC0_MAC_CH0_MAC_PCS_SEED_B0 0x546C098
+
+#define NIC0_MAC_CH0_MAC_PCS_SEED_B1 0x546C09C
+
+#define NIC0_MAC_CH0_MAC_PCS_SEED_B2 0x546C0A0
+
+#define NIC0_MAC_CH0_MAC_PCS_SEED_B3 0x546C0A4
+
+#define NIC0_MAC_CH0_MAC_PCS_BASER_TEST_CONTROL 0x546C0A8
+
+#define NIC0_MAC_CH0_MAC_PCS_BASER_TEST_ERR_CNT 0x546C0AC
+
+#define NIC0_MAC_CH0_MAC_PCS_BER_HIGH_ORDER_CNT 0x546C0B0
+
+#define NIC0_MAC_CH0_MAC_PCS_ERR_BLK_HIGH_ORDER_CNT 0x546C0B4
+
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT1 0x546C0C8
+
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT2 0x546C0CC
+
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT3 0x546C0D0
+
+#define NIC0_MAC_CH0_MAC_PCS_MULTILANE_ALIGN_STAT4 0x546C0D4
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE0 0x546C0D8
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE1 0x546C0DC
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE2 0x546C0E0
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE3 0x546C0E4
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE4 0x546C0E8
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE5 0x546C0EC
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE6 0x546C0F0
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE7 0x546C0F4
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE8 0x546C0F8
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE9 0x546C0FC
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE10 0x546C100
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE11 0x546C104
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE12 0x546C108
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE13 0x546C10C
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE14 0x546C110
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE15 0x546C114
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE16 0x546C118
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE17 0x546C11C
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE18 0x546C120
+
+#define NIC0_MAC_CH0_MAC_PCS_BIP_ERR_CNT_LANE19 0x546C124
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE0_MAPPING 0x546C128
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE1_MAPPING 0x546C12C
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE2_MAPPING 0x546C130
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE3_MAPPING 0x546C134
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE4_MAPPING 0x546C138
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE5_MAPPING 0x546C13C
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE6_MAPPING 0x546C140
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE7_MAPPING 0x546C144
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE8_MAPPING 0x546C148
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE9_MAPPING 0x546C14C
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE10_MAPPING 0x546C150
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE11_MAPPING 0x546C154
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE12_MAPPING 0x546C158
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE13_MAPPING 0x546C15C
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE14_MAPPING 0x546C160
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE15_MAPPING 0x546C164
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE16_MAPPING 0x546C168
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE17_MAPPING 0x546C16C
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE18_MAPPING 0x546C170
+
+#define NIC0_MAC_CH0_MAC_PCS_LANE19_MAPPING 0x546C174
+
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_SCRATCH 0x546C17C
+
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_CORE_REV 0x546C180
+
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL_INTVL 0x546C184
+
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_TXLANE_THRESH 0x546C188
+
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0 0x546C19C
+
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_1 0x546C1A0
+
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0 0x546C1A4
+
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_1 0x546C1A8
+
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0 0x546C1AC
+
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_1 0x546C1B0
+
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0 0x546C1B4
+
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_1 0x546C1B8
+
+#define NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE 0x546C1BC
+
+#define NIC0_MAC_CH0_MAC_PCS_VL0_0 0x546C27C
+
+#define NIC0_MAC_CH0_MAC_PCS_VL0_1 0x546C280
+
+#define NIC0_MAC_CH0_MAC_PCS_VL1_0 0x546C284
+
+#define NIC0_MAC_CH0_MAC_PCS_VL1_1 0x546C288
+
+#define NIC0_MAC_CH0_MAC_PCS_VL2_0 0x546C28C
+
+#define NIC0_MAC_CH0_MAC_PCS_VL2_1 0x546C290
+
+#define NIC0_MAC_CH0_MAC_PCS_VL3_0 0x546C294
+
+#define NIC0_MAC_CH0_MAC_PCS_VL3_1 0x546C298
+
+#define NIC0_MAC_CH0_MAC_PCS_VL4_0 0x546C29C
+
+#define NIC0_MAC_CH0_MAC_PCS_VL4_1 0x546C2A0
+
+#define NIC0_MAC_CH0_MAC_PCS_VL5_0 0x546C2A4
+
+#define NIC0_MAC_CH0_MAC_PCS_VL5_1 0x546C2A8
+
+#define NIC0_MAC_CH0_MAC_PCS_VL6_0 0x546C2AC
+
+#define NIC0_MAC_CH0_MAC_PCS_VL6_1 0x546C2B0
+
+#define NIC0_MAC_CH0_MAC_PCS_VL7_0 0x546C2B4
+
+#define NIC0_MAC_CH0_MAC_PCS_VL7_1 0x546C2B8
+
+#define NIC0_MAC_CH0_MAC_PCS_VL8_0 0x546C2BC
+
+#define NIC0_MAC_CH0_MAC_PCS_VL8_1 0x546C2C0
+
+#define NIC0_MAC_CH0_MAC_PCS_VL9_0 0x546C2C4
+
+#define NIC0_MAC_CH0_MAC_PCS_VL9_1 0x546C2C8
+
+#define NIC0_MAC_CH0_MAC_PCS_VL10_0 0x546C2CC
+
+#define NIC0_MAC_CH0_MAC_PCS_VL10_1 0x546C2D0
+
+#define NIC0_MAC_CH0_MAC_PCS_VL11_0 0x546C2D4
+
+#define NIC0_MAC_CH0_MAC_PCS_VL11_1 0x546C2D8
+
+#define NIC0_MAC_CH0_MAC_PCS_VL12_0 0x546C2DC
+
+#define NIC0_MAC_CH0_MAC_PCS_VL12_1 0x546C2E0
+
+#define NIC0_MAC_CH0_MAC_PCS_VL13_0 0x546C2E4
+
+#define NIC0_MAC_CH0_MAC_PCS_VL13_1 0x546C2E8
+
+#define NIC0_MAC_CH0_MAC_PCS_VL14_0 0x546C2EC
+
+#define NIC0_MAC_CH0_MAC_PCS_VL14_1 0x546C2F0
+
+#define NIC0_MAC_CH0_MAC_PCS_VL15_0 0x546C2F4
+
+#define NIC0_MAC_CH0_MAC_PCS_VL15_1 0x546C2F8
+
+#define NIC0_MAC_CH0_MAC_PCS_VL16_0 0x546C2FC
+
+#define NIC0_MAC_CH0_MAC_PCS_VL16_1 0x546C300
+
+#define NIC0_MAC_CH0_MAC_PCS_VL17_0 0x546C304
+
+#define NIC0_MAC_CH0_MAC_PCS_VL17_1 0x546C308
+
+#define NIC0_MAC_CH0_MAC_PCS_VL18_0 0x546C30C
+
+#define NIC0_MAC_CH0_MAC_PCS_VL18_1 0x546C310
+
+#define NIC0_MAC_CH0_MAC_PCS_VL19_0 0x546C314
+
+#define NIC0_MAC_CH0_MAC_PCS_VL19_1 0x546C318
+
+#endif /* ASIC_REG_NIC0_MAC_CH0_MAC_PCS_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch1_mac_pcs_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch1_mac_pcs_regs.h
new file mode 100644
index 000000000000..7a6cb9156611
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch1_mac_pcs_regs.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_MAC_CH1_MAC_PCS_REGS_H_
+#define ASIC_REG_NIC0_MAC_CH1_MAC_PCS_REGS_H_
+
+/*****************************************
+ * NIC0_MAC_CH1_MAC_PCS
+ * (Prototype: NIC_XPCS91)
+ *****************************************
+ */
+
+#define NIC0_MAC_CH1_MAC_PCS_CONTROL1 0x546D000
+
+#define NIC0_MAC_CH1_MAC_PCS_STATUS1 0x546D004
+
+#define NIC0_MAC_CH1_MAC_PCS_DEVICE_ID0 0x546D008
+
+#define NIC0_MAC_CH1_MAC_PCS_DEVICE_ID1 0x546D00C
+
+#define NIC0_MAC_CH1_MAC_PCS_SPEED_ABILITY 0x546D010
+
+#define NIC0_MAC_CH1_MAC_PCS_DEVICES_IN_PKG1 0x546D014
+
+#define NIC0_MAC_CH1_MAC_PCS_DEVICES_IN_PKG2 0x546D018
+
+#define NIC0_MAC_CH1_MAC_PCS_CONTROL2 0x546D01C
+
+#define NIC0_MAC_CH1_MAC_PCS_STATUS2 0x546D020
+
+#define NIC0_MAC_CH1_MAC_PCS_PKG_ID0 0x546D038
+
+#define NIC0_MAC_CH1_MAC_PCS_PKG_ID1 0x546D03C
+
+#define NIC0_MAC_CH1_MAC_PCS_EEE_CTRL_CAPABILITY 0x546D050
+
+#define NIC0_MAC_CH1_MAC_PCS_WAKE_ERR_COUNTER 0x546D058
+
+#define NIC0_MAC_CH1_MAC_PCS_BASER_STATUS1 0x546D080
+
+#define NIC0_MAC_CH1_MAC_PCS_BASER_STATUS2 0x546D084
+
+#define NIC0_MAC_CH1_MAC_PCS_SEED_A0 0x546D088
+
+#define NIC0_MAC_CH1_MAC_PCS_SEED_A1 0x546D08C
+
+#define NIC0_MAC_CH1_MAC_PCS_SEED_A2 0x546D090
+
+#define NIC0_MAC_CH1_MAC_PCS_SEED_A3 0x546D094
+
+#define NIC0_MAC_CH1_MAC_PCS_SEED_B0 0x546D098
+
+#define NIC0_MAC_CH1_MAC_PCS_SEED_B1 0x546D09C
+
+#define NIC0_MAC_CH1_MAC_PCS_SEED_B2 0x546D0A0
+
+#define NIC0_MAC_CH1_MAC_PCS_SEED_B3 0x546D0A4
+
+#define NIC0_MAC_CH1_MAC_PCS_BASER_TEST_CONTROL 0x546D0A8
+
+#define NIC0_MAC_CH1_MAC_PCS_BASER_TEST_ERR_CNT 0x546D0AC
+
+#define NIC0_MAC_CH1_MAC_PCS_BER_HIGH_ORDER_CNT 0x546D0B0
+
+#define NIC0_MAC_CH1_MAC_PCS_ERR_BLK_HIGH_ORDER_CNT 0x546D0B4
+
+#define NIC0_MAC_CH1_MAC_PCS_MULTILANE_ALIGN_STAT1 0x546D0C8
+
+#define NIC0_MAC_CH1_MAC_PCS_MULTILANE_ALIGN_STAT2 0x546D0CC
+
+#define NIC0_MAC_CH1_MAC_PCS_MULTILANE_ALIGN_STAT3 0x546D0D0
+
+#define NIC0_MAC_CH1_MAC_PCS_MULTILANE_ALIGN_STAT4 0x546D0D4
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE0 0x546D0D8
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE1 0x546D0DC
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE2 0x546D0E0
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE3 0x546D0E4
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE4 0x546D0E8
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE5 0x546D0EC
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE6 0x546D0F0
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE7 0x546D0F4
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE8 0x546D0F8
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE9 0x546D0FC
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE10 0x546D100
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE11 0x546D104
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE12 0x546D108
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE13 0x546D10C
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE14 0x546D110
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE15 0x546D114
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE16 0x546D118
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE17 0x546D11C
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE18 0x546D120
+
+#define NIC0_MAC_CH1_MAC_PCS_BIP_ERR_CNT_LANE19 0x546D124
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE0_MAPPING 0x546D128
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE1_MAPPING 0x546D12C
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE2_MAPPING 0x546D130
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE3_MAPPING 0x546D134
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE4_MAPPING 0x546D138
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE5_MAPPING 0x546D13C
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE6_MAPPING 0x546D140
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE7_MAPPING 0x546D144
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE8_MAPPING 0x546D148
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE9_MAPPING 0x546D14C
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE10_MAPPING 0x546D150
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE11_MAPPING 0x546D154
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE12_MAPPING 0x546D158
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE13_MAPPING 0x546D15C
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE14_MAPPING 0x546D160
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE15_MAPPING 0x546D164
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE16_MAPPING 0x546D168
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE17_MAPPING 0x546D16C
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE18_MAPPING 0x546D170
+
+#define NIC0_MAC_CH1_MAC_PCS_LANE19_MAPPING 0x546D174
+
+#define NIC0_MAC_CH1_MAC_PCS_VENDOR_SCRATCH 0x546D17C
+
+#define NIC0_MAC_CH1_MAC_PCS_VENDOR_CORE_REV 0x546D180
+
+#define NIC0_MAC_CH1_MAC_PCS_VENDOR_VL_INTVL 0x546D184
+
+#define NIC0_MAC_CH1_MAC_PCS_VENDOR_TXLANE_THRESH 0x546D188
+
+#define NIC0_MAC_CH1_MAC_PCS_VENDOR_VL0_0 0x546D19C
+
+#define NIC0_MAC_CH1_MAC_PCS_VENDOR_VL0_1 0x546D1A0
+
+#define NIC0_MAC_CH1_MAC_PCS_VENDOR_VL1_0 0x546D1A4
+
+#define NIC0_MAC_CH1_MAC_PCS_VENDOR_VL1_1 0x546D1A8
+
+#define NIC0_MAC_CH1_MAC_PCS_VENDOR_VL2_0 0x546D1AC
+
+#define NIC0_MAC_CH1_MAC_PCS_VENDOR_VL2_1 0x546D1B0
+
+#define NIC0_MAC_CH1_MAC_PCS_VENDOR_VL3_0 0x546D1B4
+
+#define NIC0_MAC_CH1_MAC_PCS_VENDOR_VL3_1 0x546D1B8
+
+#define NIC0_MAC_CH1_MAC_PCS_VENDOR_PCS_MODE 0x546D1BC
+
+#define NIC0_MAC_CH1_MAC_PCS_VL0_0 0x546D27C
+
+#define NIC0_MAC_CH1_MAC_PCS_VL0_1 0x546D280
+
+#define NIC0_MAC_CH1_MAC_PCS_VL1_0 0x546D284
+
+#define NIC0_MAC_CH1_MAC_PCS_VL1_1 0x546D288
+
+#define NIC0_MAC_CH1_MAC_PCS_VL2_0 0x546D28C
+
+#define NIC0_MAC_CH1_MAC_PCS_VL2_1 0x546D290
+
+#define NIC0_MAC_CH1_MAC_PCS_VL3_0 0x546D294
+
+#define NIC0_MAC_CH1_MAC_PCS_VL3_1 0x546D298
+
+#define NIC0_MAC_CH1_MAC_PCS_VL4_0 0x546D29C
+
+#define NIC0_MAC_CH1_MAC_PCS_VL4_1 0x546D2A0
+
+#define NIC0_MAC_CH1_MAC_PCS_VL5_0 0x546D2A4
+
+#define NIC0_MAC_CH1_MAC_PCS_VL5_1 0x546D2A8
+
+#define NIC0_MAC_CH1_MAC_PCS_VL6_0 0x546D2AC
+
+#define NIC0_MAC_CH1_MAC_PCS_VL6_1 0x546D2B0
+
+#define NIC0_MAC_CH1_MAC_PCS_VL7_0 0x546D2B4
+
+#define NIC0_MAC_CH1_MAC_PCS_VL7_1 0x546D2B8
+
+#define NIC0_MAC_CH1_MAC_PCS_VL8_0 0x546D2BC
+
+#define NIC0_MAC_CH1_MAC_PCS_VL8_1 0x546D2C0
+
+#define NIC0_MAC_CH1_MAC_PCS_VL9_0 0x546D2C4
+
+#define NIC0_MAC_CH1_MAC_PCS_VL9_1 0x546D2C8
+
+#define NIC0_MAC_CH1_MAC_PCS_VL10_0 0x546D2CC
+
+#define NIC0_MAC_CH1_MAC_PCS_VL10_1 0x546D2D0
+
+#define NIC0_MAC_CH1_MAC_PCS_VL11_0 0x546D2D4
+
+#define NIC0_MAC_CH1_MAC_PCS_VL11_1 0x546D2D8
+
+#define NIC0_MAC_CH1_MAC_PCS_VL12_0 0x546D2DC
+
+#define NIC0_MAC_CH1_MAC_PCS_VL12_1 0x546D2E0
+
+#define NIC0_MAC_CH1_MAC_PCS_VL13_0 0x546D2E4
+
+#define NIC0_MAC_CH1_MAC_PCS_VL13_1 0x546D2E8
+
+#define NIC0_MAC_CH1_MAC_PCS_VL14_0 0x546D2EC
+
+#define NIC0_MAC_CH1_MAC_PCS_VL14_1 0x546D2F0
+
+#define NIC0_MAC_CH1_MAC_PCS_VL15_0 0x546D2F4
+
+#define NIC0_MAC_CH1_MAC_PCS_VL15_1 0x546D2F8
+
+#define NIC0_MAC_CH1_MAC_PCS_VL16_0 0x546D2FC
+
+#define NIC0_MAC_CH1_MAC_PCS_VL16_1 0x546D300
+
+#define NIC0_MAC_CH1_MAC_PCS_VL17_0 0x546D304
+
+#define NIC0_MAC_CH1_MAC_PCS_VL17_1 0x546D308
+
+#define NIC0_MAC_CH1_MAC_PCS_VL18_0 0x546D30C
+
+#define NIC0_MAC_CH1_MAC_PCS_VL18_1 0x546D310
+
+#define NIC0_MAC_CH1_MAC_PCS_VL19_0 0x546D314
+
+#define NIC0_MAC_CH1_MAC_PCS_VL19_1 0x546D318
+
+#endif /* ASIC_REG_NIC0_MAC_CH1_MAC_PCS_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch2_mac_pcs_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch2_mac_pcs_regs.h
new file mode 100644
index 000000000000..744d99068997
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch2_mac_pcs_regs.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_MAC_CH2_MAC_PCS_REGS_H_
+#define ASIC_REG_NIC0_MAC_CH2_MAC_PCS_REGS_H_
+
+/*****************************************
+ * NIC0_MAC_CH2_MAC_PCS
+ * (Prototype: NIC_XPCS91)
+ *****************************************
+ */
+
+#define NIC0_MAC_CH2_MAC_PCS_CONTROL1 0x546E000
+
+#define NIC0_MAC_CH2_MAC_PCS_STATUS1 0x546E004
+
+#define NIC0_MAC_CH2_MAC_PCS_DEVICE_ID0 0x546E008
+
+#define NIC0_MAC_CH2_MAC_PCS_DEVICE_ID1 0x546E00C
+
+#define NIC0_MAC_CH2_MAC_PCS_SPEED_ABILITY 0x546E010
+
+#define NIC0_MAC_CH2_MAC_PCS_DEVICES_IN_PKG1 0x546E014
+
+#define NIC0_MAC_CH2_MAC_PCS_DEVICES_IN_PKG2 0x546E018
+
+#define NIC0_MAC_CH2_MAC_PCS_CONTROL2 0x546E01C
+
+#define NIC0_MAC_CH2_MAC_PCS_STATUS2 0x546E020
+
+#define NIC0_MAC_CH2_MAC_PCS_PKG_ID0 0x546E038
+
+#define NIC0_MAC_CH2_MAC_PCS_PKG_ID1 0x546E03C
+
+#define NIC0_MAC_CH2_MAC_PCS_EEE_CTRL_CAPABILITY 0x546E050
+
+#define NIC0_MAC_CH2_MAC_PCS_WAKE_ERR_COUNTER 0x546E058
+
+#define NIC0_MAC_CH2_MAC_PCS_BASER_STATUS1 0x546E080
+
+#define NIC0_MAC_CH2_MAC_PCS_BASER_STATUS2 0x546E084
+
+#define NIC0_MAC_CH2_MAC_PCS_SEED_A0 0x546E088
+
+#define NIC0_MAC_CH2_MAC_PCS_SEED_A1 0x546E08C
+
+#define NIC0_MAC_CH2_MAC_PCS_SEED_A2 0x546E090
+
+#define NIC0_MAC_CH2_MAC_PCS_SEED_A3 0x546E094
+
+#define NIC0_MAC_CH2_MAC_PCS_SEED_B0 0x546E098
+
+#define NIC0_MAC_CH2_MAC_PCS_SEED_B1 0x546E09C
+
+#define NIC0_MAC_CH2_MAC_PCS_SEED_B2 0x546E0A0
+
+#define NIC0_MAC_CH2_MAC_PCS_SEED_B3 0x546E0A4
+
+#define NIC0_MAC_CH2_MAC_PCS_BASER_TEST_CONTROL 0x546E0A8
+
+#define NIC0_MAC_CH2_MAC_PCS_BASER_TEST_ERR_CNT 0x546E0AC
+
+#define NIC0_MAC_CH2_MAC_PCS_BER_HIGH_ORDER_CNT 0x546E0B0
+
+#define NIC0_MAC_CH2_MAC_PCS_ERR_BLK_HIGH_ORDER_CNT 0x546E0B4
+
+#define NIC0_MAC_CH2_MAC_PCS_MULTILANE_ALIGN_STAT1 0x546E0C8
+
+#define NIC0_MAC_CH2_MAC_PCS_MULTILANE_ALIGN_STAT2 0x546E0CC
+
+#define NIC0_MAC_CH2_MAC_PCS_MULTILANE_ALIGN_STAT3 0x546E0D0
+
+#define NIC0_MAC_CH2_MAC_PCS_MULTILANE_ALIGN_STAT4 0x546E0D4
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE0 0x546E0D8
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE1 0x546E0DC
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE2 0x546E0E0
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE3 0x546E0E4
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE4 0x546E0E8
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE5 0x546E0EC
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE6 0x546E0F0
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE7 0x546E0F4
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE8 0x546E0F8
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE9 0x546E0FC
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE10 0x546E100
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE11 0x546E104
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE12 0x546E108
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE13 0x546E10C
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE14 0x546E110
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE15 0x546E114
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE16 0x546E118
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE17 0x546E11C
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE18 0x546E120
+
+#define NIC0_MAC_CH2_MAC_PCS_BIP_ERR_CNT_LANE19 0x546E124
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE0_MAPPING 0x546E128
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE1_MAPPING 0x546E12C
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE2_MAPPING 0x546E130
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE3_MAPPING 0x546E134
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE4_MAPPING 0x546E138
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE5_MAPPING 0x546E13C
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE6_MAPPING 0x546E140
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE7_MAPPING 0x546E144
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE8_MAPPING 0x546E148
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE9_MAPPING 0x546E14C
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE10_MAPPING 0x546E150
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE11_MAPPING 0x546E154
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE12_MAPPING 0x546E158
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE13_MAPPING 0x546E15C
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE14_MAPPING 0x546E160
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE15_MAPPING 0x546E164
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE16_MAPPING 0x546E168
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE17_MAPPING 0x546E16C
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE18_MAPPING 0x546E170
+
+#define NIC0_MAC_CH2_MAC_PCS_LANE19_MAPPING 0x546E174
+
+#define NIC0_MAC_CH2_MAC_PCS_VENDOR_SCRATCH 0x546E17C
+
+#define NIC0_MAC_CH2_MAC_PCS_VENDOR_CORE_REV 0x546E180
+
+#define NIC0_MAC_CH2_MAC_PCS_VENDOR_VL_INTVL 0x546E184
+
+#define NIC0_MAC_CH2_MAC_PCS_VENDOR_TXLANE_THRESH 0x546E188
+
+#define NIC0_MAC_CH2_MAC_PCS_VENDOR_VL0_0 0x546E19C
+
+#define NIC0_MAC_CH2_MAC_PCS_VENDOR_VL0_1 0x546E1A0
+
+#define NIC0_MAC_CH2_MAC_PCS_VENDOR_VL1_0 0x546E1A4
+
+#define NIC0_MAC_CH2_MAC_PCS_VENDOR_VL1_1 0x546E1A8
+
+#define NIC0_MAC_CH2_MAC_PCS_VENDOR_VL2_0 0x546E1AC
+
+#define NIC0_MAC_CH2_MAC_PCS_VENDOR_VL2_1 0x546E1B0
+
+#define NIC0_MAC_CH2_MAC_PCS_VENDOR_VL3_0 0x546E1B4
+
+#define NIC0_MAC_CH2_MAC_PCS_VENDOR_VL3_1 0x546E1B8
+
+#define NIC0_MAC_CH2_MAC_PCS_VENDOR_PCS_MODE 0x546E1BC
+
+#define NIC0_MAC_CH2_MAC_PCS_VL0_0 0x546E27C
+
+#define NIC0_MAC_CH2_MAC_PCS_VL0_1 0x546E280
+
+#define NIC0_MAC_CH2_MAC_PCS_VL1_0 0x546E284
+
+#define NIC0_MAC_CH2_MAC_PCS_VL1_1 0x546E288
+
+#define NIC0_MAC_CH2_MAC_PCS_VL2_0 0x546E28C
+
+#define NIC0_MAC_CH2_MAC_PCS_VL2_1 0x546E290
+
+#define NIC0_MAC_CH2_MAC_PCS_VL3_0 0x546E294
+
+#define NIC0_MAC_CH2_MAC_PCS_VL3_1 0x546E298
+
+#define NIC0_MAC_CH2_MAC_PCS_VL4_0 0x546E29C
+
+#define NIC0_MAC_CH2_MAC_PCS_VL4_1 0x546E2A0
+
+#define NIC0_MAC_CH2_MAC_PCS_VL5_0 0x546E2A4
+
+#define NIC0_MAC_CH2_MAC_PCS_VL5_1 0x546E2A8
+
+#define NIC0_MAC_CH2_MAC_PCS_VL6_0 0x546E2AC
+
+#define NIC0_MAC_CH2_MAC_PCS_VL6_1 0x546E2B0
+
+#define NIC0_MAC_CH2_MAC_PCS_VL7_0 0x546E2B4
+
+#define NIC0_MAC_CH2_MAC_PCS_VL7_1 0x546E2B8
+
+#define NIC0_MAC_CH2_MAC_PCS_VL8_0 0x546E2BC
+
+#define NIC0_MAC_CH2_MAC_PCS_VL8_1 0x546E2C0
+
+#define NIC0_MAC_CH2_MAC_PCS_VL9_0 0x546E2C4
+
+#define NIC0_MAC_CH2_MAC_PCS_VL9_1 0x546E2C8
+
+#define NIC0_MAC_CH2_MAC_PCS_VL10_0 0x546E2CC
+
+#define NIC0_MAC_CH2_MAC_PCS_VL10_1 0x546E2D0
+
+#define NIC0_MAC_CH2_MAC_PCS_VL11_0 0x546E2D4
+
+#define NIC0_MAC_CH2_MAC_PCS_VL11_1 0x546E2D8
+
+#define NIC0_MAC_CH2_MAC_PCS_VL12_0 0x546E2DC
+
+#define NIC0_MAC_CH2_MAC_PCS_VL12_1 0x546E2E0
+
+#define NIC0_MAC_CH2_MAC_PCS_VL13_0 0x546E2E4
+
+#define NIC0_MAC_CH2_MAC_PCS_VL13_1 0x546E2E8
+
+#define NIC0_MAC_CH2_MAC_PCS_VL14_0 0x546E2EC
+
+#define NIC0_MAC_CH2_MAC_PCS_VL14_1 0x546E2F0
+
+#define NIC0_MAC_CH2_MAC_PCS_VL15_0 0x546E2F4
+
+#define NIC0_MAC_CH2_MAC_PCS_VL15_1 0x546E2F8
+
+#define NIC0_MAC_CH2_MAC_PCS_VL16_0 0x546E2FC
+
+#define NIC0_MAC_CH2_MAC_PCS_VL16_1 0x546E300
+
+#define NIC0_MAC_CH2_MAC_PCS_VL17_0 0x546E304
+
+#define NIC0_MAC_CH2_MAC_PCS_VL17_1 0x546E308
+
+#define NIC0_MAC_CH2_MAC_PCS_VL18_0 0x546E30C
+
+#define NIC0_MAC_CH2_MAC_PCS_VL18_1 0x546E310
+
+#define NIC0_MAC_CH2_MAC_PCS_VL19_0 0x546E314
+
+#define NIC0_MAC_CH2_MAC_PCS_VL19_1 0x546E318
+
+#endif /* ASIC_REG_NIC0_MAC_CH2_MAC_PCS_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch3_mac_pcs_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch3_mac_pcs_regs.h
new file mode 100644
index 000000000000..42d062998852
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch3_mac_pcs_regs.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_MAC_CH3_MAC_PCS_REGS_H_
+#define ASIC_REG_NIC0_MAC_CH3_MAC_PCS_REGS_H_
+
+/*****************************************
+ * NIC0_MAC_CH3_MAC_PCS
+ * (Prototype: NIC_XPCS91)
+ *****************************************
+ */
+
+#define NIC0_MAC_CH3_MAC_PCS_CONTROL1 0x546F000
+
+#define NIC0_MAC_CH3_MAC_PCS_STATUS1 0x546F004
+
+#define NIC0_MAC_CH3_MAC_PCS_DEVICE_ID0 0x546F008
+
+#define NIC0_MAC_CH3_MAC_PCS_DEVICE_ID1 0x546F00C
+
+#define NIC0_MAC_CH3_MAC_PCS_SPEED_ABILITY 0x546F010
+
+#define NIC0_MAC_CH3_MAC_PCS_DEVICES_IN_PKG1 0x546F014
+
+#define NIC0_MAC_CH3_MAC_PCS_DEVICES_IN_PKG2 0x546F018
+
+#define NIC0_MAC_CH3_MAC_PCS_CONTROL2 0x546F01C
+
+#define NIC0_MAC_CH3_MAC_PCS_STATUS2 0x546F020
+
+#define NIC0_MAC_CH3_MAC_PCS_PKG_ID0 0x546F038
+
+#define NIC0_MAC_CH3_MAC_PCS_PKG_ID1 0x546F03C
+
+#define NIC0_MAC_CH3_MAC_PCS_EEE_CTRL_CAPABILITY 0x546F050
+
+#define NIC0_MAC_CH3_MAC_PCS_WAKE_ERR_COUNTER 0x546F058
+
+#define NIC0_MAC_CH3_MAC_PCS_BASER_STATUS1 0x546F080
+
+#define NIC0_MAC_CH3_MAC_PCS_BASER_STATUS2 0x546F084
+
+#define NIC0_MAC_CH3_MAC_PCS_SEED_A0 0x546F088
+
+#define NIC0_MAC_CH3_MAC_PCS_SEED_A1 0x546F08C
+
+#define NIC0_MAC_CH3_MAC_PCS_SEED_A2 0x546F090
+
+#define NIC0_MAC_CH3_MAC_PCS_SEED_A3 0x546F094
+
+#define NIC0_MAC_CH3_MAC_PCS_SEED_B0 0x546F098
+
+#define NIC0_MAC_CH3_MAC_PCS_SEED_B1 0x546F09C
+
+#define NIC0_MAC_CH3_MAC_PCS_SEED_B2 0x546F0A0
+
+#define NIC0_MAC_CH3_MAC_PCS_SEED_B3 0x546F0A4
+
+#define NIC0_MAC_CH3_MAC_PCS_BASER_TEST_CONTROL 0x546F0A8
+
+#define NIC0_MAC_CH3_MAC_PCS_BASER_TEST_ERR_CNT 0x546F0AC
+
+#define NIC0_MAC_CH3_MAC_PCS_BER_HIGH_ORDER_CNT 0x546F0B0
+
+#define NIC0_MAC_CH3_MAC_PCS_ERR_BLK_HIGH_ORDER_CNT 0x546F0B4
+
+#define NIC0_MAC_CH3_MAC_PCS_MULTILANE_ALIGN_STAT1 0x546F0C8
+
+#define NIC0_MAC_CH3_MAC_PCS_MULTILANE_ALIGN_STAT2 0x546F0CC
+
+#define NIC0_MAC_CH3_MAC_PCS_MULTILANE_ALIGN_STAT3 0x546F0D0
+
+#define NIC0_MAC_CH3_MAC_PCS_MULTILANE_ALIGN_STAT4 0x546F0D4
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE0 0x546F0D8
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE1 0x546F0DC
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE2 0x546F0E0
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE3 0x546F0E4
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE4 0x546F0E8
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE5 0x546F0EC
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE6 0x546F0F0
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE7 0x546F0F4
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE8 0x546F0F8
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE9 0x546F0FC
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE10 0x546F100
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE11 0x546F104
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE12 0x546F108
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE13 0x546F10C
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE14 0x546F110
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE15 0x546F114
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE16 0x546F118
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE17 0x546F11C
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE18 0x546F120
+
+#define NIC0_MAC_CH3_MAC_PCS_BIP_ERR_CNT_LANE19 0x546F124
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE0_MAPPING 0x546F128
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE1_MAPPING 0x546F12C
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE2_MAPPING 0x546F130
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE3_MAPPING 0x546F134
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE4_MAPPING 0x546F138
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE5_MAPPING 0x546F13C
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE6_MAPPING 0x546F140
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE7_MAPPING 0x546F144
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE8_MAPPING 0x546F148
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE9_MAPPING 0x546F14C
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE10_MAPPING 0x546F150
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE11_MAPPING 0x546F154
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE12_MAPPING 0x546F158
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE13_MAPPING 0x546F15C
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE14_MAPPING 0x546F160
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE15_MAPPING 0x546F164
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE16_MAPPING 0x546F168
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE17_MAPPING 0x546F16C
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE18_MAPPING 0x546F170
+
+#define NIC0_MAC_CH3_MAC_PCS_LANE19_MAPPING 0x546F174
+
+#define NIC0_MAC_CH3_MAC_PCS_VENDOR_SCRATCH 0x546F17C
+
+#define NIC0_MAC_CH3_MAC_PCS_VENDOR_CORE_REV 0x546F180
+
+#define NIC0_MAC_CH3_MAC_PCS_VENDOR_VL_INTVL 0x546F184
+
+#define NIC0_MAC_CH3_MAC_PCS_VENDOR_TXLANE_THRESH 0x546F188
+
+#define NIC0_MAC_CH3_MAC_PCS_VENDOR_VL0_0 0x546F19C
+
+#define NIC0_MAC_CH3_MAC_PCS_VENDOR_VL0_1 0x546F1A0
+
+#define NIC0_MAC_CH3_MAC_PCS_VENDOR_VL1_0 0x546F1A4
+
+#define NIC0_MAC_CH3_MAC_PCS_VENDOR_VL1_1 0x546F1A8
+
+#define NIC0_MAC_CH3_MAC_PCS_VENDOR_VL2_0 0x546F1AC
+
+#define NIC0_MAC_CH3_MAC_PCS_VENDOR_VL2_1 0x546F1B0
+
+#define NIC0_MAC_CH3_MAC_PCS_VENDOR_VL3_0 0x546F1B4
+
+#define NIC0_MAC_CH3_MAC_PCS_VENDOR_VL3_1 0x546F1B8
+
+#define NIC0_MAC_CH3_MAC_PCS_VENDOR_PCS_MODE 0x546F1BC
+
+#define NIC0_MAC_CH3_MAC_PCS_VL0_0 0x546F27C
+
+#define NIC0_MAC_CH3_MAC_PCS_VL0_1 0x546F280
+
+#define NIC0_MAC_CH3_MAC_PCS_VL1_0 0x546F284
+
+#define NIC0_MAC_CH3_MAC_PCS_VL1_1 0x546F288
+
+#define NIC0_MAC_CH3_MAC_PCS_VL2_0 0x546F28C
+
+#define NIC0_MAC_CH3_MAC_PCS_VL2_1 0x546F290
+
+#define NIC0_MAC_CH3_MAC_PCS_VL3_0 0x546F294
+
+#define NIC0_MAC_CH3_MAC_PCS_VL3_1 0x546F298
+
+#define NIC0_MAC_CH3_MAC_PCS_VL4_0 0x546F29C
+
+#define NIC0_MAC_CH3_MAC_PCS_VL4_1 0x546F2A0
+
+#define NIC0_MAC_CH3_MAC_PCS_VL5_0 0x546F2A4
+
+#define NIC0_MAC_CH3_MAC_PCS_VL5_1 0x546F2A8
+
+#define NIC0_MAC_CH3_MAC_PCS_VL6_0 0x546F2AC
+
+#define NIC0_MAC_CH3_MAC_PCS_VL6_1 0x546F2B0
+
+#define NIC0_MAC_CH3_MAC_PCS_VL7_0 0x546F2B4
+
+#define NIC0_MAC_CH3_MAC_PCS_VL7_1 0x546F2B8
+
+#define NIC0_MAC_CH3_MAC_PCS_VL8_0 0x546F2BC
+
+#define NIC0_MAC_CH3_MAC_PCS_VL8_1 0x546F2C0
+
+#define NIC0_MAC_CH3_MAC_PCS_VL9_0 0x546F2C4
+
+#define NIC0_MAC_CH3_MAC_PCS_VL9_1 0x546F2C8
+
+#define NIC0_MAC_CH3_MAC_PCS_VL10_0 0x546F2CC
+
+#define NIC0_MAC_CH3_MAC_PCS_VL10_1 0x546F2D0
+
+#define NIC0_MAC_CH3_MAC_PCS_VL11_0 0x546F2D4
+
+#define NIC0_MAC_CH3_MAC_PCS_VL11_1 0x546F2D8
+
+#define NIC0_MAC_CH3_MAC_PCS_VL12_0 0x546F2DC
+
+#define NIC0_MAC_CH3_MAC_PCS_VL12_1 0x546F2E0
+
+#define NIC0_MAC_CH3_MAC_PCS_VL13_0 0x546F2E4
+
+#define NIC0_MAC_CH3_MAC_PCS_VL13_1 0x546F2E8
+
+#define NIC0_MAC_CH3_MAC_PCS_VL14_0 0x546F2EC
+
+#define NIC0_MAC_CH3_MAC_PCS_VL14_1 0x546F2F0
+
+#define NIC0_MAC_CH3_MAC_PCS_VL15_0 0x546F2F4
+
+#define NIC0_MAC_CH3_MAC_PCS_VL15_1 0x546F2F8
+
+#define NIC0_MAC_CH3_MAC_PCS_VL16_0 0x546F2FC
+
+#define NIC0_MAC_CH3_MAC_PCS_VL16_1 0x546F300
+
+#define NIC0_MAC_CH3_MAC_PCS_VL17_0 0x546F304
+
+#define NIC0_MAC_CH3_MAC_PCS_VL17_1 0x546F308
+
+#define NIC0_MAC_CH3_MAC_PCS_VL18_0 0x546F30C
+
+#define NIC0_MAC_CH3_MAC_PCS_VL18_1 0x546F310
+
+#define NIC0_MAC_CH3_MAC_PCS_VL19_0 0x546F314
+
+#define NIC0_MAC_CH3_MAC_PCS_VL19_1 0x546F318
+
+#endif /* ASIC_REG_NIC0_MAC_CH3_MAC_PCS_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_control_reg_masks.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_control_reg_masks.h
new file mode 100644
index 000000000000..3b5876f375fa
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_control_reg_masks.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_MAC_GLOB_STAT_CONTROL_REG_MASKS_H_
+#define ASIC_REG_NIC0_MAC_GLOB_STAT_CONTROL_REG_MASKS_H_
+
+/*****************************************
+ * NIC0_MAC_GLOB_STAT_CONTROL_REG
+ * (Prototype: MAC_CONTROL_REG)
+ *****************************************
+ */
+
+/* NIC0_MAC_GLOB_STAT_CONTROL_REG_DATA_HI */
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_DATA_HI_DATAHI_SHIFT 0
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_DATA_HI_DATAHI_MASK 0xFFFFFFFF
+
+/* NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_STATUS */
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_STATUS_RXBUSY_SHIFT 0
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_STATUS_RXBUSY_MASK 0x1
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_STATUS_TXBUSY_SHIFT 1
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_STATUS_TXBUSY_MASK 0x2
+
+/* NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONFIG */
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONFIG_SATURATE_SHIFT 0
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONFIG_SATURATE_MASK 0x1
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONFIG_CLEARONREAD_SHIFT 1
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONFIG_CLEARONREAD_MASK 0x2
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONFIG_F_RESET_SHIFT 31
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONFIG_F_RESET_MASK 0x80000000
+
+/* NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONTROL */
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONTROL_PORTMASK_SHIFT 0
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONTROL_PORTMASK_MASK 0xFF
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONTROL_RESERVED_27_SHIFT 27
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONTROL_RESERVED_27_MASK 0x8000000
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONTROL_RESERVED_28_SHIFT 28
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONTROL_RESERVED_28_MASK 0x10000000
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONTROL_CLEARPRE_SHIFT 29
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONTROL_CLEARPRE_MASK 0x20000000
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONTROL_CMDCLEARRX_SHIFT 30
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONTROL_CMDCLEARRX_MASK 0x40000000
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONTROL_CMDCLEARTX_SHIFT 31
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONTROL_CMDCLEARTX_MASK 0x80000000
+
+/* NIC0_MAC_GLOB_STAT_CONTROL_REG_CVALUE_LO */
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_CVALUE_LO_CVALUELO_SHIFT 0
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_CVALUE_LO_CVALUELO_MASK 0xFFFFFFFF
+
+/* NIC0_MAC_GLOB_STAT_CONTROL_REG_CVALUE_HI */
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_CVALUE_HI_CVALUEHI_SHIFT 0
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_CVALUE_HI_CVALUEHI_MASK 0xFFFFFFFF
+
+/* NIC0_MAC_GLOB_STAT_CONTROL_REG_DATA_HI2 */
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_DATA_HI2_DATAHI2_SHIFT 0
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_DATA_HI2_DATAHI2_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_NIC0_MAC_GLOB_STAT_CONTROL_REG_MASKS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_control_reg_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_control_reg_regs.h
new file mode 100644
index 000000000000..aeab83dbff53
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_control_reg_regs.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_MAC_GLOB_STAT_CONTROL_REG_REGS_H_
+#define ASIC_REG_NIC0_MAC_GLOB_STAT_CONTROL_REG_REGS_H_
+
+/*****************************************
+ * NIC0_MAC_GLOB_STAT_CONTROL_REG
+ * (Prototype: MAC_CONTROL_REG)
+ *****************************************
+ */
+
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_DATA_HI 0x546B000
+
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_STATUS 0x546B004
+
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONFIG 0x546B008
+
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONTROL 0x546B00C
+
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_CVALUE_LO 0x546B010
+
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_CVALUE_HI 0x546B014
+
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_DATA_HI2 0x546B01C
+
+#endif /* ASIC_REG_NIC0_MAC_GLOB_STAT_CONTROL_REG_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_rx0_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_rx0_regs.h
new file mode 100644
index 000000000000..4434ca244092
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_rx0_regs.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_MAC_GLOB_STAT_RX0_REGS_H_
+#define ASIC_REG_NIC0_MAC_GLOB_STAT_RX0_REGS_H_
+
+/*****************************************
+ * NIC0_MAC_GLOB_STAT_RX0
+ * (Prototype: MAC_MAC0_RX_CNT)
+ *****************************************
+ */
+
+#define NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSOCTETS 0x546B100
+
+#define NIC0_MAC_GLOB_STAT_RX0_OCTETSRECEIVEDOK 0x546B104
+
+#define NIC0_MAC_GLOB_STAT_RX0_AALIGNMENTERRORS 0x546B108
+
+#define NIC0_MAC_GLOB_STAT_RX0_APAUSEMACCTRLFRAMESRECEIVED 0x546B10C
+
+#define NIC0_MAC_GLOB_STAT_RX0_AFRAMETOOLONGERRORS 0x546B110
+
+#define NIC0_MAC_GLOB_STAT_RX0_AINRANGELENGTHERRORS 0x546B114
+
+#define NIC0_MAC_GLOB_STAT_RX0_AFRAMESRECEIVEDOK 0x546B118
+
+#define NIC0_MAC_GLOB_STAT_RX0_AFRAMECHECKSEQUENCEERRORS 0x546B11C
+
+#define NIC0_MAC_GLOB_STAT_RX0_VLANRECEIVEDOK 0x546B120
+
+#define NIC0_MAC_GLOB_STAT_RX0_IFINERRORS 0x546B124
+
+#define NIC0_MAC_GLOB_STAT_RX0_IFINUCASTPKTS 0x546B128
+
+#define NIC0_MAC_GLOB_STAT_RX0_IFINMULTICASTPKTS 0x546B12C
+
+#define NIC0_MAC_GLOB_STAT_RX0_IFINBROADCASTPKTS 0x546B130
+
+#define NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSDROPEVENTS 0x546B134
+
+#define NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSPKTS 0x546B138
+
+#define NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSUNDERSIZEPKTS 0x546B13C
+
+#define NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSPKTS64OCTETS 0x546B140
+
+#define NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSPKTS65TO127OCTETS 0x546B144
+
+#define NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSPKTS128TO255OCTETS 0x546B148
+
+#define NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSPKTS256TO511OCTETS 0x546B14C
+
+#define NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSPKTS512TO1023OCTETS 0x546B150
+
+#define NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSPKTS1024TO1518OCTETS 0x546B154
+
+#define NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSPKTS1519TOMAXOCTETS 0x546B158
+
+#define NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSOVERSIZEPKTS 0x546B15C
+
+#define NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSJABBERS 0x546B160
+
+#define NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSFRAGMENTS 0x546B164
+
+#define NIC0_MAC_GLOB_STAT_RX0_ACBFCPAUSEFRAMESRECEIVED0 0x546B168
+
+#define NIC0_MAC_GLOB_STAT_RX0_ACBFCPAUSEFRAMESRECEIVED1 0x546B16C
+
+#define NIC0_MAC_GLOB_STAT_RX0_ACBFCPAUSEFRAMESRECEIVED2 0x546B170
+
+#define NIC0_MAC_GLOB_STAT_RX0_ACBFCPAUSEFRAMESRECEIVED3 0x546B174
+
+#define NIC0_MAC_GLOB_STAT_RX0_ACBFCPAUSEFRAMESRECEIVED4 0x546B178
+
+#define NIC0_MAC_GLOB_STAT_RX0_ACBFCPAUSEFRAMESRECEIVED5 0x546B17C
+
+#define NIC0_MAC_GLOB_STAT_RX0_ACBFCPAUSEFRAMESRECEIVED6 0x546B180
+
+#define NIC0_MAC_GLOB_STAT_RX0_ACBFCPAUSEFRAMESRECEIVED7 0x546B184
+
+#define NIC0_MAC_GLOB_STAT_RX0_AMACCONTROLFRAMESRECEIVED 0x546B188
+
+#endif /* ASIC_REG_NIC0_MAC_GLOB_STAT_RX0_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_rx2_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_rx2_regs.h
new file mode 100644
index 000000000000..19bfc04d3478
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_rx2_regs.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_MAC_GLOB_STAT_RX2_REGS_H_
+#define ASIC_REG_NIC0_MAC_GLOB_STAT_RX2_REGS_H_
+
+/*****************************************
+ * NIC0_MAC_GLOB_STAT_RX2
+ * (Prototype: MAC_MAC2_RX_CNT)
+ *****************************************
+ */
+
+#define NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSOCTETS_2 0x546B218
+
+#define NIC0_MAC_GLOB_STAT_RX2_OCTETSRECEIVEDOK_2 0x546B21C
+
+#define NIC0_MAC_GLOB_STAT_RX2_AALIGNMENTERRORS_2 0x546B220
+
+#define NIC0_MAC_GLOB_STAT_RX2_APAUSEMACCTRLFRAMESRECEIVED_2 0x546B224
+
+#define NIC0_MAC_GLOB_STAT_RX2_AFRAMETOOLONGERRORS_2 0x546B228
+
+#define NIC0_MAC_GLOB_STAT_RX2_AINRANGELENGTHERRORS_2 0x546B22C
+
+#define NIC0_MAC_GLOB_STAT_RX2_AFRAMESRECEIVEDOK_2 0x546B230
+
+#define NIC0_MAC_GLOB_STAT_RX2_AFRAMECHECKSEQUENCEERRORS_2 0x546B234
+
+#define NIC0_MAC_GLOB_STAT_RX2_VLANRECEIVEDOK_2 0x546B238
+
+#define NIC0_MAC_GLOB_STAT_RX2_IFINERRORS_2 0x546B23C
+
+#define NIC0_MAC_GLOB_STAT_RX2_IFINUCASTPKTS_2 0x546B240
+
+#define NIC0_MAC_GLOB_STAT_RX2_IFINMULTICASTPKTS_2 0x546B244
+
+#define NIC0_MAC_GLOB_STAT_RX2_IFINBROADCASTPKTS_2 0x546B248
+
+#define NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSDROPEVENTS_2 0x546B24C
+
+#define NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSPKTS_2 0x546B250
+
+#define NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSUNDERSIZEPKTS_2 0x546B254
+
+#define NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSPKTS64OCTETS_2 0x546B258
+
+#define NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSPKTS65TO127OCTETS_2 0x546B25C
+
+#define NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSPKTS128TO255OCTETS_2 0x546B260
+
+#define NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSPKTS256TO511OCTETS_2 0x546B264
+
+#define NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSPKTS512TO1023OCTETS_2 0x546B268
+
+#define NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSPKTS1024TO1518OCTETS_2 0x546B26C
+
+#define NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSPKTS1519TOMAXOCTETS_2 0x546B270
+
+#define NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSOVERSIZEPKTS_2 0x546B274
+
+#define NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSJABBERS_2 0x546B278
+
+#define NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSFRAGMENTS_2 0x546B27C
+
+#define NIC0_MAC_GLOB_STAT_RX2_ACBFCPAUSEFRAMESRECEIVED0_2 0x546B280
+
+#define NIC0_MAC_GLOB_STAT_RX2_ACBFCPAUSEFRAMESRECEIVED1_2 0x546B284
+
+#define NIC0_MAC_GLOB_STAT_RX2_ACBFCPAUSEFRAMESRECEIVED2_2 0x546B288
+
+#define NIC0_MAC_GLOB_STAT_RX2_ACBFCPAUSEFRAMESRECEIVED3_2 0x546B28C
+
+#define NIC0_MAC_GLOB_STAT_RX2_ACBFCPAUSEFRAMESRECEIVED4_2 0x546B290
+
+#define NIC0_MAC_GLOB_STAT_RX2_ACBFCPAUSEFRAMESRECEIVED5_2 0x546B294
+
+#define NIC0_MAC_GLOB_STAT_RX2_ACBFCPAUSEFRAMESRECEIVED6_2 0x546B298
+
+#define NIC0_MAC_GLOB_STAT_RX2_ACBFCPAUSEFRAMESRECEIVED7_2 0x546B29C
+
+#define NIC0_MAC_GLOB_STAT_RX2_AMACCONTROLFRAMESRECEIVED_2 0x546B2A0
+
+#endif /* ASIC_REG_NIC0_MAC_GLOB_STAT_RX2_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_tx0_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_tx0_regs.h
new file mode 100644
index 000000000000..545ceeddb014
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_tx0_regs.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_MAC_GLOB_STAT_TX0_REGS_H_
+#define ASIC_REG_NIC0_MAC_GLOB_STAT_TX0_REGS_H_
+
+/*****************************************
+ * NIC0_MAC_GLOB_STAT_TX0
+ * (Prototype: MAC_MAC0_TX_CNT)
+ *****************************************
+ */
+
+#define NIC0_MAC_GLOB_STAT_TX0_ETHERSTATSOCTETS_4 0x546B330
+
+#define NIC0_MAC_GLOB_STAT_TX0_OCTETSTRANSMITTEDOK 0x546B334
+
+#define NIC0_MAC_GLOB_STAT_TX0_APAUSEMACCTRLFRAMESTRANSMITTED 0x546B338
+
+#define NIC0_MAC_GLOB_STAT_TX0_AFRAMESTRANSMITTEDOK 0x546B33C
+
+#define NIC0_MAC_GLOB_STAT_TX0_VLANTRANSMITTEDOK 0x546B340
+
+#define NIC0_MAC_GLOB_STAT_TX0_IFOUTERRORS 0x546B344
+
+#define NIC0_MAC_GLOB_STAT_TX0_IFOUTUCASTPKTS 0x546B348
+
+#define NIC0_MAC_GLOB_STAT_TX0_IFOUTMULTICASTPKTS 0x546B34C
+
+#define NIC0_MAC_GLOB_STAT_TX0_IFOUTBROADCASTPKTS 0x546B350
+
+#define NIC0_MAC_GLOB_STAT_TX0_ETHERSTATSPKTS64OCTETS_4 0x546B354
+
+#define NIC0_MAC_GLOB_STAT_TX0_ETHERSTATSPKTS65TO127OCTETS_4 0x546B358
+
+#define NIC0_MAC_GLOB_STAT_TX0_ETHERSTATSPKTS128TO255OCTETS_4 0x546B35C
+
+#define NIC0_MAC_GLOB_STAT_TX0_ETHERSTATSPKTS256TO511OCTETS_4 0x546B360
+
+#define NIC0_MAC_GLOB_STAT_TX0_ETHERSTATSPKTS512TO1023OCTETS_4 0x546B364
+
+#define NIC0_MAC_GLOB_STAT_TX0_ETHERSTATSPKTS1024TO1518OCTETS_4 0x546B368
+
+#define NIC0_MAC_GLOB_STAT_TX0_ETHERSTATSPKTS1519TOMAXOCTETS_4 0x546B36C
+
+#define NIC0_MAC_GLOB_STAT_TX0_ACBFCPAUSEFRAMESTRANSMITTED0 0x546B370
+
+#define NIC0_MAC_GLOB_STAT_TX0_ACBFCPAUSEFRAMESTRANSMITTED1 0x546B374
+
+#define NIC0_MAC_GLOB_STAT_TX0_ACBFCPAUSEFRAMESTRANSMITTED2 0x546B378
+
+#define NIC0_MAC_GLOB_STAT_TX0_ACBFCPAUSEFRAMESTRANSMITTED3 0x546B37C
+
+#define NIC0_MAC_GLOB_STAT_TX0_ACBFCPAUSEFRAMESTRANSMITTED4 0x546B380
+
+#define NIC0_MAC_GLOB_STAT_TX0_ACBFCPAUSEFRAMESTRANSMITTED5 0x546B384
+
+#define NIC0_MAC_GLOB_STAT_TX0_ACBFCPAUSEFRAMESTRANSMITTED6 0x546B388
+
+#define NIC0_MAC_GLOB_STAT_TX0_ACBFCPAUSEFRAMESTRANSMITTED7 0x546B38C
+
+#define NIC0_MAC_GLOB_STAT_TX0_AMACCONTROLFRAMESTRANSMITTED 0x546B390
+
+#define NIC0_MAC_GLOB_STAT_TX0_ETHERSTATSPKTS_4 0x546B394
+
+#endif /* ASIC_REG_NIC0_MAC_GLOB_STAT_TX0_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_tx2_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_tx2_regs.h
new file mode 100644
index 000000000000..188d495c3a7e
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_tx2_regs.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_MAC_GLOB_STAT_TX2_REGS_H_
+#define ASIC_REG_NIC0_MAC_GLOB_STAT_TX2_REGS_H_
+
+/*****************************************
+ * NIC0_MAC_GLOB_STAT_TX2
+ * (Prototype: MAC_MAC2_TX_CNT)
+ *****************************************
+ */
+
+#define NIC0_MAC_GLOB_STAT_TX2_ETHERSTATSOCTETS_6 0x546B400
+
+#define NIC0_MAC_GLOB_STAT_TX2_OCTETSTRANSMITTEDOK_2 0x546B404
+
+#define NIC0_MAC_GLOB_STAT_TX2_APAUSEMACCTRLFRAMESTRANSMITTED_2 0x546B408
+
+#define NIC0_MAC_GLOB_STAT_TX2_AFRAMESTRANSMITTEDOK_2 0x546B40C
+
+#define NIC0_MAC_GLOB_STAT_TX2_VLANTRANSMITTEDOK_2 0x546B410
+
+#define NIC0_MAC_GLOB_STAT_TX2_IFOUTERRORS_2 0x546B414
+
+#define NIC0_MAC_GLOB_STAT_TX2_IFOUTUCASTPKTS_2 0x546B418
+
+#define NIC0_MAC_GLOB_STAT_TX2_IFOUTMULTICASTPKTS_2 0x546B41C
+
+#define NIC0_MAC_GLOB_STAT_TX2_IFOUTBROADCASTPKTS_2 0x546B420
+
+#define NIC0_MAC_GLOB_STAT_TX2_ETHERSTATSPKTS64OCTETS_6 0x546B424
+
+#define NIC0_MAC_GLOB_STAT_TX2_ETHERSTATSPKTS65TO127OCTETS_6 0x546B428
+
+#define NIC0_MAC_GLOB_STAT_TX2_ETHERSTATSPKTS128TO255OCTETS_6 0x546B42C
+
+#define NIC0_MAC_GLOB_STAT_TX2_ETHERSTATSPKTS256TO511OCTETS_6 0x546B430
+
+#define NIC0_MAC_GLOB_STAT_TX2_ETHERSTATSPKTS512TO1023OCTETS_6 0x546B434
+
+#define NIC0_MAC_GLOB_STAT_TX2_ETHERSTATSPKTS1024TO1518OCTETS_6 0x546B438
+
+#define NIC0_MAC_GLOB_STAT_TX2_ETHERSTATSPKTS1519TOMAXOCTETS_6 0x546B43C
+
+#define NIC0_MAC_GLOB_STAT_TX2_ACBFCPAUSEFRAMESTRANSMITTED0_2 0x546B440
+
+#define NIC0_MAC_GLOB_STAT_TX2_ACBFCPAUSEFRAMESTRANSMITTED1_2 0x546B444
+
+#define NIC0_MAC_GLOB_STAT_TX2_ACBFCPAUSEFRAMESTRANSMITTED2_2 0x546B448
+
+#define NIC0_MAC_GLOB_STAT_TX2_ACBFCPAUSEFRAMESTRANSMITTED3_2 0x546B44C
+
+#define NIC0_MAC_GLOB_STAT_TX2_ACBFCPAUSEFRAMESTRANSMITTED4_2 0x546B450
+
+#define NIC0_MAC_GLOB_STAT_TX2_ACBFCPAUSEFRAMESTRANSMITTED5_2 0x546B454
+
+#define NIC0_MAC_GLOB_STAT_TX2_ACBFCPAUSEFRAMESTRANSMITTED6_2 0x546B458
+
+#define NIC0_MAC_GLOB_STAT_TX2_ACBFCPAUSEFRAMESTRANSMITTED7_2 0x546B45C
+
+#define NIC0_MAC_GLOB_STAT_TX2_AMACCONTROLFRAMESTRANSMITTED_2 0x546B460
+
+#define NIC0_MAC_GLOB_STAT_TX2_ETHERSTATSPKTS_6 0x546B464
+
+#endif /* ASIC_REG_NIC0_MAC_GLOB_STAT_TX2_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_rs_fec_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_rs_fec_regs.h
new file mode 100644
index 000000000000..5955a40caedb
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_rs_fec_regs.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_MAC_RS_FEC_REGS_H_
+#define ASIC_REG_NIC0_MAC_RS_FEC_REGS_H_
+
+/*****************************************
+ * NIC0_MAC_RS_FEC
+ * (Prototype: NIC_MAC_RS_FEC)
+ *****************************************
+ */
+
+#define NIC0_MAC_RS_FEC_RSFEC_CONTROL 0x546A000
+
+#define NIC0_MAC_RS_FEC_RSFEC_STATUS 0x546A004
+
+#define NIC0_MAC_RS_FEC_RSFEC_CCW_LO 0x546A008
+
+#define NIC0_MAC_RS_FEC_RSFEC_CCW_HI 0x546A00C
+
+#define NIC0_MAC_RS_FEC_RSFEC_NCCW_LO 0x546A010
+
+#define NIC0_MAC_RS_FEC_RSFEC_NCCW_HI 0x546A014
+
+#define NIC0_MAC_RS_FEC_RSFEC_LANE_MAP 0x546A018
+
+#define NIC0_MAC_RS_FEC_RSFEC_DEC_THRESH 0x546A01C
+
+#define NIC0_MAC_RS_FEC_RSFEC1_CONTROL 0x546A020
+
+#define NIC0_MAC_RS_FEC_RSFEC1_STATUS 0x546A024
+
+#define NIC0_MAC_RS_FEC_RSFEC1_CCW_LO 0x546A028
+
+#define NIC0_MAC_RS_FEC_RSFEC1_CCW_HI 0x546A02C
+
+#define NIC0_MAC_RS_FEC_RSFEC1_NCCW_LO 0x546A030
+
+#define NIC0_MAC_RS_FEC_RSFEC1_NCCW_HI 0x546A034
+
+#define NIC0_MAC_RS_FEC_RSFEC1_LANE_MAP 0x546A038
+
+#define NIC0_MAC_RS_FEC_RSFEC1_DEC_THRESH 0x546A03C
+
+#define NIC0_MAC_RS_FEC_RSFEC2_CONTROL 0x546A040
+
+#define NIC0_MAC_RS_FEC_RSFEC2_STATUS 0x546A044
+
+#define NIC0_MAC_RS_FEC_RSFEC2_CCW_LO 0x546A048
+
+#define NIC0_MAC_RS_FEC_RSFEC2_CCW_HI 0x546A04C
+
+#define NIC0_MAC_RS_FEC_RSFEC2_NCCW_LO 0x546A050
+
+#define NIC0_MAC_RS_FEC_RSFEC2_NCCW_HI 0x546A054
+
+#define NIC0_MAC_RS_FEC_RSFEC2_LANE_MAP 0x546A058
+
+#define NIC0_MAC_RS_FEC_RSFEC2_DEC_THRESH 0x546A05C
+
+#define NIC0_MAC_RS_FEC_RSFEC3_CONTROL 0x546A060
+
+#define NIC0_MAC_RS_FEC_RSFEC3_STATUS 0x546A064
+
+#define NIC0_MAC_RS_FEC_RSFEC3_CCW_LO 0x546A068
+
+#define NIC0_MAC_RS_FEC_RSFEC3_CCW_HI 0x546A06C
+
+#define NIC0_MAC_RS_FEC_RSFEC3_NCCW_LO 0x546A070
+
+#define NIC0_MAC_RS_FEC_RSFEC3_NCCW_HI 0x546A074
+
+#define NIC0_MAC_RS_FEC_RSFEC3_LANE_MAP 0x546A078
+
+#define NIC0_MAC_RS_FEC_RSFEC3_DEC_THRESH 0x546A07C
+
+#define NIC0_MAC_RS_FEC_HISER_CW 0x546A100
+
+#define NIC0_MAC_RS_FEC_HISER_THRESH 0x546A104
+
+#define NIC0_MAC_RS_FEC_HISER_TIME 0x546A108
+
+#define NIC0_MAC_RS_FEC_DEGRADE_SET_CW 0x546A110
+
+#define NIC0_MAC_RS_FEC_DEGRADE_SET_CW_HI 0x546A114
+
+#define NIC0_MAC_RS_FEC_DEGRADE_SET_THRESH 0x546A118
+
+#define NIC0_MAC_RS_FEC_DEGRADE_SET_THRESH_HI 0x546A11C
+
+#define NIC0_MAC_RS_FEC_DEGRADE_CLEAR_CW 0x546A120
+
+#define NIC0_MAC_RS_FEC_DEGRADE_CLEAR_CW_HI 0x546A124
+
+#define NIC0_MAC_RS_FEC_DEGRADE_CLEAR_THRESH 0x546A128
+
+#define NIC0_MAC_RS_FEC_DEGRADE_CLEAR_THRESH_HI 0x546A12C
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR0_LO 0x546A200
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR0_HI 0x546A204
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR1_LO 0x546A208
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR1_HI 0x546A20C
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR2_LO 0x546A210
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR2_HI 0x546A214
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR3_LO 0x546A218
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR3_HI 0x546A21C
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR4_LO 0x546A220
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR4_HI 0x546A224
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR5_LO 0x546A228
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR5_HI 0x546A22C
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR6_LO 0x546A230
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR6_HI 0x546A234
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR7_LO 0x546A238
+
+#define NIC0_MAC_RS_FEC_RSFEC_SYMBLERR7_HI 0x546A23C
+
+#define NIC0_MAC_RS_FEC_RSFEC_VENDOR_INFO1 0x546A284
+
+#define NIC0_MAC_RS_FEC_RSFEC_VENDOR_INFO2 0x546A288
+
+#define NIC0_MAC_RS_FEC_RSFEC_VENDOR_REVISION 0x546A28C
+
+#define NIC0_MAC_RS_FEC_RSFEC_VENDOR_ALIGN_STATUS 0x546A290
+
+#define NIC0_MAC_RS_FEC_RSFEC_HISER_THRESHOLD0 0x546A2C0
+
+#define NIC0_MAC_RS_FEC_RSFEC_HISER_THRESHOLD1 0x546A2C8
+
+#define NIC0_MAC_RS_FEC_RSFEC_HISER_THRESHOLD2 0x546A2D0
+
+#define NIC0_MAC_RS_FEC_RSFEC_HISER_THRESHOLD3 0x546A2D8
+
+#endif /* ASIC_REG_NIC0_MAC_RS_FEC_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_phy_masks.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_phy_masks.h
new file mode 100644
index 000000000000..fbc8b9388ef3
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_phy_masks.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_PHY_MASKS_H_
+#define ASIC_REG_NIC0_PHY_MASKS_H_
+
+/*****************************************
+ * NIC0_PHY
+ * (Prototype: PRT_PHY)
+ *****************************************
+ */
+
+/* NIC0_PHY_PHY_RX_STS */
+#define NIC0_PHY_PHY_RX_STS_PHY_READY_SHIFT 0
+#define NIC0_PHY_PHY_RX_STS_PHY_READY_MASK 0x1
+#define NIC0_PHY_PHY_RX_STS_SIGNAL_DETECT_SHIFT 1
+#define NIC0_PHY_PHY_RX_STS_SIGNAL_DETECT_MASK 0x2
+#define NIC0_PHY_PHY_RX_STS_PLL_LOCK_SHIFT 2
+#define NIC0_PHY_PHY_RX_STS_PLL_LOCK_MASK 0x4
+#define NIC0_PHY_PHY_RX_STS_PHY_RX_CLK_TICK_SHIFT 3
+#define NIC0_PHY_PHY_RX_STS_PHY_RX_CLK_TICK_MASK 0x8
+
+/* NIC0_PHY_PHY_RX_CFG */
+#define NIC0_PHY_PHY_RX_CFG_SW_PHY_READY_SHIFT 0
+#define NIC0_PHY_PHY_RX_CFG_SW_PHY_READY_MASK 0x1
+#define NIC0_PHY_PHY_RX_CFG_SW_PHY_READY_OVERRIDE_SHIFT 1
+#define NIC0_PHY_PHY_RX_CFG_SW_PHY_READY_OVERRIDE_MASK 0x2
+
+/* NIC0_PHY_PHY_TX_STS */
+#define NIC0_PHY_PHY_TX_STS_PRT_TX_CLK_TICK_SHIFT 0
+#define NIC0_PHY_PHY_TX_STS_PRT_TX_CLK_TICK_MASK 0x1
+#define NIC0_PHY_PHY_TX_STS_PLL_LOCK_SHIFT 1
+#define NIC0_PHY_PHY_TX_STS_PLL_LOCK_MASK 0x2
+
+/* NIC0_PHY_PHY_RST_CFG */
+#define NIC0_PHY_PHY_RST_CFG_PHY_CFG_SW_RST_N_SHIFT 0
+#define NIC0_PHY_PHY_RST_CFG_PHY_CFG_SW_RST_N_MASK 0x1
+
+/* NIC0_PHY_PHY_CFG_ADDR */
+#define NIC0_PHY_PHY_CFG_ADDR_EN_PHY0_ADDR_OVRD_SHIFT 0
+#define NIC0_PHY_PHY_CFG_ADDR_EN_PHY0_ADDR_OVRD_MASK 0x1
+#define NIC0_PHY_PHY_CFG_ADDR_EN_PHY1_ADDR_OVRD_SHIFT 1
+#define NIC0_PHY_PHY_CFG_ADDR_EN_PHY1_ADDR_OVRD_MASK 0x2
+#define NIC0_PHY_PHY_CFG_ADDR_ADDR_OVRD_SHIFT 16
+#define NIC0_PHY_PHY_CFG_ADDR_ADDR_OVRD_MASK 0xFFFF0000
+
+/* NIC0_PHY_PHY_LINK_STS_INTR */
+#define NIC0_PHY_PHY_LINK_STS_INTR_MASK_SHIFT 0
+#define NIC0_PHY_PHY_LINK_STS_INTR_MASK_MASK 0x1
+#define NIC0_PHY_PHY_LINK_STS_INTR_CLEAR_SHIFT 1
+#define NIC0_PHY_PHY_LINK_STS_INTR_CLEAR_MASK 0x2
+
+/* NIC0_PHY_PHY_IDDQ */
+#define NIC0_PHY_PHY_IDDQ_IDDQ_SHIFT 0
+#define NIC0_PHY_PHY_IDDQ_IDDQ_MASK 0x1
+
+/* NIC0_PHY_PHY_ASYNC_LANE_SWAP */
+#define NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES0_TX0_SWAP_ID_SHIFT 0
+#define NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES0_TX0_SWAP_ID_MASK 0x3
+#define NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES0_TX1_SWAP_ID_SHIFT 2
+#define NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES0_TX1_SWAP_ID_MASK 0xC
+#define NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES1_TX0_SWAP_ID_SHIFT 4
+#define NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES1_TX0_SWAP_ID_MASK 0x30
+#define NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES1_TX1_SWAP_ID_SHIFT 6
+#define NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES1_TX1_SWAP_ID_MASK 0xC0
+
+#endif /* ASIC_REG_NIC0_PHY_MASKS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_phy_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_phy_regs.h
new file mode 100644
index 000000000000..31a3b48d89e1
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_phy_regs.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_PHY_REGS_H_
+#define ASIC_REG_NIC0_PHY_REGS_H_
+
+/*****************************************
+ * NIC0_PHY
+ * (Prototype: PRT_PHY)
+ *****************************************
+ */
+
+#define NIC0_PHY_PHY_RX_STS_0 0x5460000
+
+#define NIC0_PHY_PHY_RX_STS_1 0x5460004
+
+#define NIC0_PHY_PHY_RX_STS_2 0x5460008
+
+#define NIC0_PHY_PHY_RX_STS_3 0x546000C
+
+#define NIC0_PHY_PHY_RX_CFG_0 0x5460010
+
+#define NIC0_PHY_PHY_RX_CFG_1 0x5460014
+
+#define NIC0_PHY_PHY_RX_CFG_2 0x5460018
+
+#define NIC0_PHY_PHY_RX_CFG_3 0x546001C
+
+#define NIC0_PHY_PHY_TX_STS_0 0x5460020
+
+#define NIC0_PHY_PHY_TX_STS_1 0x5460024
+
+#define NIC0_PHY_PHY_TX_STS_2 0x5460028
+
+#define NIC0_PHY_PHY_TX_STS_3 0x546002C
+
+#define NIC0_PHY_PHY_RST_CFG 0x5460030
+
+#define NIC0_PHY_PHY_CFG_ADDR 0x5460040
+
+#define NIC0_PHY_PHY_LINK_STS_INTR 0x5460050
+
+#define NIC0_PHY_PHY_IDDQ_0 0x5460060
+
+#define NIC0_PHY_PHY_IDDQ_1 0x5460064
+
+#define NIC0_PHY_PHY_ASYNC_LANE_SWAP 0x5460068
+
+#endif /* ASIC_REG_NIC0_PHY_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qm0_axuser_nonsecured_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qm0_axuser_nonsecured_regs.h
new file mode 100644
index 000000000000..9d7a9f211110
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qm0_axuser_nonsecured_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QM0_AXUSER_NONSECURED_REGS_H_
+#define ASIC_REG_NIC0_QM0_AXUSER_NONSECURED_REGS_H_
+
+/*****************************************
+ * NIC0_QM0_AXUSER_NONSECURED
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_QM0_AXUSER_NONSECURED_HB_ASID 0x541AB80
+
+#define NIC0_QM0_AXUSER_NONSECURED_HB_MMU_BP 0x541AB84
+
+#define NIC0_QM0_AXUSER_NONSECURED_HB_STRONG_ORDER 0x541AB88
+
+#define NIC0_QM0_AXUSER_NONSECURED_HB_NO_SNOOP 0x541AB8C
+
+#define NIC0_QM0_AXUSER_NONSECURED_HB_WR_REDUCTION 0x541AB90
+
+#define NIC0_QM0_AXUSER_NONSECURED_HB_RD_ATOMIC 0x541AB94
+
+#define NIC0_QM0_AXUSER_NONSECURED_HB_QOS 0x541AB98
+
+#define NIC0_QM0_AXUSER_NONSECURED_HB_RSVD 0x541AB9C
+
+#define NIC0_QM0_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x541ABA0
+
+#define NIC0_QM0_AXUSER_NONSECURED_HB_CORE 0x541ABA4
+
+#define NIC0_QM0_AXUSER_NONSECURED_E2E_COORD 0x541ABA8
+
+#define NIC0_QM0_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x541ABB0
+
+#define NIC0_QM0_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x541ABB4
+
+#define NIC0_QM0_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x541ABB8
+
+#define NIC0_QM0_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x541ABBC
+
+#define NIC0_QM0_AXUSER_NONSECURED_LB_COORD 0x541ABC0
+
+#define NIC0_QM0_AXUSER_NONSECURED_LB_LOCK 0x541ABC4
+
+#define NIC0_QM0_AXUSER_NONSECURED_LB_RSVD 0x541ABC8
+
+#define NIC0_QM0_AXUSER_NONSECURED_LB_OVRD 0x541ABCC
+
+#endif /* ASIC_REG_NIC0_QM0_AXUSER_NONSECURED_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_cong_que_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_cong_que_regs.h
new file mode 100644
index 000000000000..8bc8aab6af77
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_cong_que_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC0_AXUSER_CONG_QUE_REGS_H_
+#define ASIC_REG_NIC0_QPC0_AXUSER_CONG_QUE_REGS_H_
+
+/*****************************************
+ * NIC0_QPC0_AXUSER_CONG_QUE
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_HB_ASID 0x541FB80
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_HB_MMU_BP 0x541FB84
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_HB_STRONG_ORDER 0x541FB88
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_HB_NO_SNOOP 0x541FB8C
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_HB_WR_REDUCTION 0x541FB90
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_HB_RD_ATOMIC 0x541FB94
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_HB_QOS 0x541FB98
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_HB_RSVD 0x541FB9C
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_HB_EMEM_CPAGE 0x541FBA0
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_HB_CORE 0x541FBA4
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_E2E_COORD 0x541FBA8
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_HB_WR_OVRD_LO 0x541FBB0
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_HB_WR_OVRD_HI 0x541FBB4
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_HB_RD_OVRD_LO 0x541FBB8
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_HB_RD_OVRD_HI 0x541FBBC
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_LB_COORD 0x541FBC0
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_LB_LOCK 0x541FBC4
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_LB_RSVD 0x541FBC8
+
+#define NIC0_QPC0_AXUSER_CONG_QUE_LB_OVRD 0x541FBCC
+
+#endif /* ASIC_REG_NIC0_QPC0_AXUSER_CONG_QUE_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_db_fifo_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_db_fifo_regs.h
new file mode 100644
index 000000000000..78938637c0fe
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_db_fifo_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC0_AXUSER_DB_FIFO_REGS_H_
+#define ASIC_REG_NIC0_QPC0_AXUSER_DB_FIFO_REGS_H_
+
+/*****************************************
+ * NIC0_QPC0_AXUSER_DB_FIFO
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_HB_ASID 0x541FCA0
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_HB_MMU_BP 0x541FCA4
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_HB_STRONG_ORDER 0x541FCA8
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_HB_NO_SNOOP 0x541FCAC
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_HB_WR_REDUCTION 0x541FCB0
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_HB_RD_ATOMIC 0x541FCB4
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_HB_QOS 0x541FCB8
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_HB_RSVD 0x541FCBC
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_HB_EMEM_CPAGE 0x541FCC0
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_HB_CORE 0x541FCC4
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_E2E_COORD 0x541FCC8
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_HB_WR_OVRD_LO 0x541FCD0
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_HB_WR_OVRD_HI 0x541FCD4
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_HB_RD_OVRD_LO 0x541FCD8
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_HB_RD_OVRD_HI 0x541FCDC
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_LB_COORD 0x541FCE0
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_LB_LOCK 0x541FCE4
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_LB_RSVD 0x541FCE8
+
+#define NIC0_QPC0_AXUSER_DB_FIFO_LB_OVRD 0x541FCEC
+
+#endif /* ASIC_REG_NIC0_QPC0_AXUSER_DB_FIFO_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_err_fifo_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_err_fifo_regs.h
new file mode 100644
index 000000000000..9597f9403497
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_err_fifo_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC0_AXUSER_ERR_FIFO_REGS_H_
+#define ASIC_REG_NIC0_QPC0_AXUSER_ERR_FIFO_REGS_H_
+
+/*****************************************
+ * NIC0_QPC0_AXUSER_ERR_FIFO
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_HB_ASID 0x541FD60
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_HB_MMU_BP 0x541FD64
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_HB_STRONG_ORDER 0x541FD68
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_HB_NO_SNOOP 0x541FD6C
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_HB_WR_REDUCTION 0x541FD70
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_HB_RD_ATOMIC 0x541FD74
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_HB_QOS 0x541FD78
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_HB_RSVD 0x541FD7C
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_HB_EMEM_CPAGE 0x541FD80
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_HB_CORE 0x541FD84
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_E2E_COORD 0x541FD88
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_HB_WR_OVRD_LO 0x541FD90
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_HB_WR_OVRD_HI 0x541FD94
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_HB_RD_OVRD_LO 0x541FD98
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_HB_RD_OVRD_HI 0x541FD9C
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_LB_COORD 0x541FDA0
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_LB_LOCK 0x541FDA4
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_LB_RSVD 0x541FDA8
+
+#define NIC0_QPC0_AXUSER_ERR_FIFO_LB_OVRD 0x541FDAC
+
+#endif /* ASIC_REG_NIC0_QPC0_AXUSER_ERR_FIFO_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_ev_que_lbw_intr_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_ev_que_lbw_intr_regs.h
new file mode 100644
index 000000000000..38f0b48ff8e8
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_ev_que_lbw_intr_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_REGS_H_
+#define ASIC_REG_NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_REGS_H_
+
+/*****************************************
+ * NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_ASID 0x541FD00
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_MMU_BP 0x541FD04
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_STRONG_ORDER 0x541FD08
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_NO_SNOOP 0x541FD0C
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_WR_REDUCTION 0x541FD10
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_RD_ATOMIC 0x541FD14
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_QOS 0x541FD18
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_RSVD 0x541FD1C
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_EMEM_CPAGE 0x541FD20
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_CORE 0x541FD24
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_E2E_COORD 0x541FD28
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_WR_OVRD_LO 0x541FD30
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_WR_OVRD_HI 0x541FD34
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_RD_OVRD_LO 0x541FD38
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_RD_OVRD_HI 0x541FD3C
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_LB_COORD 0x541FD40
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_LB_LOCK 0x541FD44
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_LB_RSVD 0x541FD48
+
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_LB_OVRD 0x541FD4C
+
+#endif /* ASIC_REG_NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_qpc_req_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_qpc_req_regs.h
new file mode 100644
index 000000000000..90b124171016
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_qpc_req_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC0_AXUSER_QPC_REQ_REGS_H_
+#define ASIC_REG_NIC0_QPC0_AXUSER_QPC_REQ_REGS_H_
+
+/*****************************************
+ * NIC0_QPC0_AXUSER_QPC_REQ
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_HB_ASID 0x541FE20
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_HB_MMU_BP 0x541FE24
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_HB_STRONG_ORDER 0x541FE28
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_HB_NO_SNOOP 0x541FE2C
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_HB_WR_REDUCTION 0x541FE30
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_HB_RD_ATOMIC 0x541FE34
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_HB_QOS 0x541FE38
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_HB_RSVD 0x541FE3C
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_HB_EMEM_CPAGE 0x541FE40
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_HB_CORE 0x541FE44
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_E2E_COORD 0x541FE48
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_HB_WR_OVRD_LO 0x541FE50
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_HB_WR_OVRD_HI 0x541FE54
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_HB_RD_OVRD_LO 0x541FE58
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_HB_RD_OVRD_HI 0x541FE5C
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_LB_COORD 0x541FE60
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_LB_LOCK 0x541FE64
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_LB_RSVD 0x541FE68
+
+#define NIC0_QPC0_AXUSER_QPC_REQ_LB_OVRD 0x541FE6C
+
+#endif /* ASIC_REG_NIC0_QPC0_AXUSER_QPC_REQ_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_qpc_resp_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_qpc_resp_regs.h
new file mode 100644
index 000000000000..eea5c05a3578
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_qpc_resp_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC0_AXUSER_QPC_RESP_REGS_H_
+#define ASIC_REG_NIC0_QPC0_AXUSER_QPC_RESP_REGS_H_
+
+/*****************************************
+ * NIC0_QPC0_AXUSER_QPC_RESP
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_HB_ASID 0x541FDC0
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_HB_MMU_BP 0x541FDC4
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_HB_STRONG_ORDER 0x541FDC8
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_HB_NO_SNOOP 0x541FDCC
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_HB_WR_REDUCTION 0x541FDD0
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_HB_RD_ATOMIC 0x541FDD4
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_HB_QOS 0x541FDD8
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_HB_RSVD 0x541FDDC
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_HB_EMEM_CPAGE 0x541FDE0
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_HB_CORE 0x541FDE4
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_E2E_COORD 0x541FDE8
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_HB_WR_OVRD_LO 0x541FDF0
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_HB_WR_OVRD_HI 0x541FDF4
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_HB_RD_OVRD_LO 0x541FDF8
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_HB_RD_OVRD_HI 0x541FDFC
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_LB_COORD 0x541FE00
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_LB_LOCK 0x541FE04
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_LB_RSVD 0x541FE08
+
+#define NIC0_QPC0_AXUSER_QPC_RESP_LB_OVRD 0x541FE0C
+
+#endif /* ASIC_REG_NIC0_QPC0_AXUSER_QPC_RESP_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_rxwqe_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_rxwqe_regs.h
new file mode 100644
index 000000000000..27af40754764
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_rxwqe_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC0_AXUSER_RXWQE_REGS_H_
+#define ASIC_REG_NIC0_QPC0_AXUSER_RXWQE_REGS_H_
+
+/*****************************************
+ * NIC0_QPC0_AXUSER_RXWQE
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_QPC0_AXUSER_RXWQE_HB_ASID 0x541FBE0
+
+#define NIC0_QPC0_AXUSER_RXWQE_HB_MMU_BP 0x541FBE4
+
+#define NIC0_QPC0_AXUSER_RXWQE_HB_STRONG_ORDER 0x541FBE8
+
+#define NIC0_QPC0_AXUSER_RXWQE_HB_NO_SNOOP 0x541FBEC
+
+#define NIC0_QPC0_AXUSER_RXWQE_HB_WR_REDUCTION 0x541FBF0
+
+#define NIC0_QPC0_AXUSER_RXWQE_HB_RD_ATOMIC 0x541FBF4
+
+#define NIC0_QPC0_AXUSER_RXWQE_HB_QOS 0x541FBF8
+
+#define NIC0_QPC0_AXUSER_RXWQE_HB_RSVD 0x541FBFC
+
+#define NIC0_QPC0_AXUSER_RXWQE_HB_EMEM_CPAGE 0x541FC00
+
+#define NIC0_QPC0_AXUSER_RXWQE_HB_CORE 0x541FC04
+
+#define NIC0_QPC0_AXUSER_RXWQE_E2E_COORD 0x541FC08
+
+#define NIC0_QPC0_AXUSER_RXWQE_HB_WR_OVRD_LO 0x541FC10
+
+#define NIC0_QPC0_AXUSER_RXWQE_HB_WR_OVRD_HI 0x541FC14
+
+#define NIC0_QPC0_AXUSER_RXWQE_HB_RD_OVRD_LO 0x541FC18
+
+#define NIC0_QPC0_AXUSER_RXWQE_HB_RD_OVRD_HI 0x541FC1C
+
+#define NIC0_QPC0_AXUSER_RXWQE_LB_COORD 0x541FC20
+
+#define NIC0_QPC0_AXUSER_RXWQE_LB_LOCK 0x541FC24
+
+#define NIC0_QPC0_AXUSER_RXWQE_LB_RSVD 0x541FC28
+
+#define NIC0_QPC0_AXUSER_RXWQE_LB_OVRD 0x541FC2C
+
+#endif /* ASIC_REG_NIC0_QPC0_AXUSER_RXWQE_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_txwqe_lbw_qman_bp_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_txwqe_lbw_qman_bp_regs.h
new file mode 100644
index 000000000000..4c3d502cddc9
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_txwqe_lbw_qman_bp_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_REGS_H_
+#define ASIC_REG_NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_REGS_H_
+
+/*****************************************
+ * NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_ASID 0x541FC40
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_MMU_BP 0x541FC44
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_STRONG_ORDER 0x541FC48
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_NO_SNOOP 0x541FC4C
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_WR_REDUCTION 0x541FC50
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_RD_ATOMIC 0x541FC54
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_QOS 0x541FC58
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_RSVD 0x541FC5C
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_EMEM_CPAGE 0x541FC60
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_CORE 0x541FC64
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_E2E_COORD 0x541FC68
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_WR_OVRD_LO 0x541FC70
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_WR_OVRD_HI 0x541FC74
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_RD_OVRD_LO 0x541FC78
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_RD_OVRD_HI 0x541FC7C
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_LB_COORD 0x541FC80
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_LB_LOCK 0x541FC84
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_LB_RSVD 0x541FC88
+
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_LB_OVRD 0x541FC8C
+
+#endif /* ASIC_REG_NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_dbfifo0_ci_upd_addr_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_dbfifo0_ci_upd_addr_regs.h
new file mode 100644
index 000000000000..63b52724260e
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_dbfifo0_ci_upd_addr_regs.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_REGS_H_
+#define ASIC_REG_NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_REGS_H_
+
+/*****************************************
+ * NIC0_QPC0_DBFIFO0_CI_UPD_ADDR
+ * (Prototype: DOORBELL_CONSUMER_INDEX_UPD)
+ *****************************************
+ */
+
+#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_DBFIFO_CI_UPD_ADDR_63_32 0x541F720
+
+#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_DBFIFO_CI_UPD_ADDR_31_7 0x541F724
+
+#endif /* ASIC_REG_NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_dbfifosecur_ci_upd_addr_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_dbfifosecur_ci_upd_addr_regs.h
new file mode 100644
index 000000000000..af310618d501
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_dbfifosecur_ci_upd_addr_regs.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_REGS_H_
+#define ASIC_REG_NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_REGS_H_
+
+/*****************************************
+ * NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR
+ * (Prototype: DOORBELL_CONSUMER_INDEX_UPD)
+ *****************************************
+ */
+
+#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_DBFIFO_CI_UPD_ADDR_63_32 0x541F810
+
+#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_DBFIFO_CI_UPD_ADDR_31_7 0x541F814
+
+#endif /* ASIC_REG_NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_masks.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_masks.h
new file mode 100644
index 000000000000..5ccfc36449fa
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_masks.h
@@ -0,0 +1,963 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC0_MASKS_H_
+#define ASIC_REG_NIC0_QPC0_MASKS_H_
+
+/*****************************************
+ * NIC0_QPC0
+ * (Prototype: NIC_QPC)
+ *****************************************
+ */
+
+/* NIC0_QPC0_REQ_QPC_CACHE_INVALIDATE */
+#define NIC0_QPC0_REQ_QPC_CACHE_INVALIDATE_R_SHIFT 0
+#define NIC0_QPC0_REQ_QPC_CACHE_INVALIDATE_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_REQ_QPC_CACHE_INV_STATUS */
+#define NIC0_QPC0_REQ_QPC_CACHE_INV_STATUS_INVALIDATE_DONE_SHIFT 0
+#define NIC0_QPC0_REQ_QPC_CACHE_INV_STATUS_INVALIDATE_DONE_MASK 0x1
+#define NIC0_QPC0_REQ_QPC_CACHE_INV_STATUS_CACHE_IDLE_SHIFT 1
+#define NIC0_QPC0_REQ_QPC_CACHE_INV_STATUS_CACHE_IDLE_MASK 0x2
+
+/* NIC0_QPC0_REQ_STATIC_CONFIG */
+#define NIC0_QPC0_REQ_STATIC_CONFIG_PLRU_EVICTION_SHIFT 0
+#define NIC0_QPC0_REQ_STATIC_CONFIG_PLRU_EVICTION_MASK 0x1
+#define NIC0_QPC0_REQ_STATIC_CONFIG_RELEASE_INVALIDATE_SHIFT 1
+#define NIC0_QPC0_REQ_STATIC_CONFIG_RELEASE_INVALIDATE_MASK 0x2
+#define NIC0_QPC0_REQ_STATIC_CONFIG_LINK_LIST_EN_SHIFT 2
+#define NIC0_QPC0_REQ_STATIC_CONFIG_LINK_LIST_EN_MASK 0x4
+#define NIC0_QPC0_REQ_STATIC_CONFIG_TIMER_EN_SHIFT 3
+#define NIC0_QPC0_REQ_STATIC_CONFIG_TIMER_EN_MASK 0x8
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_PUSH_TO_ERR_FIFO_NON_V_SHIFT 4
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_PUSH_TO_ERR_FIFO_NON_V_MASK 0x10
+#define NIC0_QPC0_REQ_STATIC_CONFIG_TX_PUSH_TO_ERR_FIFO_NON_V_SHIFT 5
+#define NIC0_QPC0_REQ_STATIC_CONFIG_TX_PUSH_TO_ERR_FIFO_NON_V_MASK 0x20
+#define NIC0_QPC0_REQ_STATIC_CONFIG_CACHE_STOP_SHIFT 6
+#define NIC0_QPC0_REQ_STATIC_CONFIG_CACHE_STOP_MASK 0x40
+#define NIC0_QPC0_REQ_STATIC_CONFIG_INVALIDATE_WRITEBACK_SHIFT 7
+#define NIC0_QPC0_REQ_STATIC_CONFIG_INVALIDATE_WRITEBACK_MASK 0x80
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_PUSH_TO_ERROR_SECURITY_SHIFT 8
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_PUSH_TO_ERROR_SECURITY_MASK 0x100
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_PUSH_ERR_PI_EX_LAST_SHIFT 9
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_PUSH_ERR_PI_EX_LAST_MASK 0x200
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_PUSH_ERR_UPDATE_WQ_RD_SHIFT 10
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_PUSH_ERR_UPDATE_WQ_RD_MASK 0x400
+#define NIC0_QPC0_REQ_STATIC_CONFIG_RDV_PUSH_ERR_RPI_EX_LAST_SHIFT 14
+#define NIC0_QPC0_REQ_STATIC_CONFIG_RDV_PUSH_ERR_RPI_EX_LAST_MASK 0x4000
+#define NIC0_QPC0_REQ_STATIC_CONFIG_RDV_PUSH_ERR_NON_VALID_SHIFT 15
+#define NIC0_QPC0_REQ_STATIC_CONFIG_RDV_PUSH_ERR_NON_VALID_MASK 0x8000
+#define NIC0_QPC0_REQ_STATIC_CONFIG_RDV_PUSH_ERR_WRONG_WQ_SHIFT 16
+#define NIC0_QPC0_REQ_STATIC_CONFIG_RDV_PUSH_ERR_WRONG_WQ_MASK 0x10000
+#define NIC0_QPC0_REQ_STATIC_CONFIG_RESEND_WQE_ON_ROLLBACK_SHIFT 19
+#define NIC0_QPC0_REQ_STATIC_CONFIG_RESEND_WQE_ON_ROLLBACK_MASK 0x80000
+#define NIC0_QPC0_REQ_STATIC_CONFIG_RX_PUSH_TO_ERR_FIFO_NON_V_SHIFT 20
+#define NIC0_QPC0_REQ_STATIC_CONFIG_RX_PUSH_TO_ERR_FIFO_NON_V_MASK 0x100000
+#define NIC0_QPC0_REQ_STATIC_CONFIG_TX_PUSH_ERR_FIFO_WQE_RDV_SHIFT 21
+#define NIC0_QPC0_REQ_STATIC_CONFIG_TX_PUSH_ERR_FIFO_WQE_RDV_MASK 0x200000
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_UPD_IGNORE_SECUR_ERR_SHIFT 22
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_UPD_IGNORE_SECUR_ERR_MASK 0x400000
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_MOVEQP2ERR_SECUR_ERR_SHIFT 23
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_MOVEQP2ERR_SECUR_ERR_MASK 0x800000
+#define NIC0_QPC0_REQ_STATIC_CONFIG_TX_PUSH_QP_IGNORE_ERROR_SHIFT 24
+#define NIC0_QPC0_REQ_STATIC_CONFIG_TX_PUSH_QP_IGNORE_ERROR_MASK 0x1000000
+#define NIC0_QPC0_REQ_STATIC_CONFIG_OVR_QP_VALID_TO_NOT_VALID_SHIFT 25
+#define NIC0_QPC0_REQ_STATIC_CONFIG_OVR_QP_VALID_TO_NOT_VALID_MASK 0x2000000
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_PUSH_TO_ERROR_ASID_SHIFT 26
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_PUSH_TO_ERROR_ASID_MASK 0x4000000
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_UPD_IGNORE_ASID_ERR_SHIFT 27
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_UPD_IGNORE_ASID_ERR_MASK 0x8000000
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_MOVEQP2ERR_ASID_ERR_SHIFT 28
+#define NIC0_QPC0_REQ_STATIC_CONFIG_QM_MOVEQP2ERR_ASID_ERR_MASK 0x10000000
+
+/* NIC0_QPC0_REQ_BASE_ADDRESS_63_32 */
+#define NIC0_QPC0_REQ_BASE_ADDRESS_63_32_R_SHIFT 0
+#define NIC0_QPC0_REQ_BASE_ADDRESS_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_REQ_BASE_ADDRESS_31_7 */
+#define NIC0_QPC0_REQ_BASE_ADDRESS_31_7_R_SHIFT 0
+#define NIC0_QPC0_REQ_BASE_ADDRESS_31_7_R_MASK 0x1FFFFFF
+
+/* NIC0_QPC0_REQ_CLEAN_LINK_LIST */
+#define NIC0_QPC0_REQ_CLEAN_LINK_LIST_R_SHIFT 0
+#define NIC0_QPC0_REQ_CLEAN_LINK_LIST_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_REQ_ERR_FIFO_PUSH_63_32 */
+#define NIC0_QPC0_REQ_ERR_FIFO_PUSH_63_32_R_SHIFT 0
+#define NIC0_QPC0_REQ_ERR_FIFO_PUSH_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_REQ_ERR_FIFO_PUSH_31_0 */
+#define NIC0_QPC0_REQ_ERR_FIFO_PUSH_31_0_R_SHIFT 0
+#define NIC0_QPC0_REQ_ERR_FIFO_PUSH_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_REQ_ERR_QP_STATE_63_32 */
+#define NIC0_QPC0_REQ_ERR_QP_STATE_63_32_R_SHIFT 0
+#define NIC0_QPC0_REQ_ERR_QP_STATE_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_REQ_ERR_QP_STATE_31_0 */
+#define NIC0_QPC0_REQ_ERR_QP_STATE_31_0_R_SHIFT 0
+#define NIC0_QPC0_REQ_ERR_QP_STATE_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_RETRY_COUNT_MAX */
+#define NIC0_QPC0_RETRY_COUNT_MAX_TIMEOUT_SHIFT 0
+#define NIC0_QPC0_RETRY_COUNT_MAX_TIMEOUT_MASK 0xFF
+#define NIC0_QPC0_RETRY_COUNT_MAX_SEQUENCE_ERROR_SHIFT 8
+#define NIC0_QPC0_RETRY_COUNT_MAX_SEQUENCE_ERROR_MASK 0xFF00
+
+/* NIC0_QPC0_AXI_PROT */
+#define NIC0_QPC0_AXI_PROT_REQ_RD_SHIFT 0
+#define NIC0_QPC0_AXI_PROT_REQ_RD_MASK 0x7
+#define NIC0_QPC0_AXI_PROT_REQ_WR_SHIFT 3
+#define NIC0_QPC0_AXI_PROT_REQ_WR_MASK 0x38
+#define NIC0_QPC0_AXI_PROT_RES_RD_SHIFT 6
+#define NIC0_QPC0_AXI_PROT_RES_RD_MASK 0x1C0
+#define NIC0_QPC0_AXI_PROT_RES_WR_SHIFT 9
+#define NIC0_QPC0_AXI_PROT_RES_WR_MASK 0xE00
+#define NIC0_QPC0_AXI_PROT_DB_WR_SHIFT 12
+#define NIC0_QPC0_AXI_PROT_DB_WR_MASK 0x7000
+#define NIC0_QPC0_AXI_PROT_EQ_WR_SHIFT 15
+#define NIC0_QPC0_AXI_PROT_EQ_WR_MASK 0x38000
+#define NIC0_QPC0_AXI_PROT_ERR_WR_SHIFT 18
+#define NIC0_QPC0_AXI_PROT_ERR_WR_MASK 0x1C0000
+#define NIC0_QPC0_AXI_PROT_CONGQ_WR_SHIFT 21
+#define NIC0_QPC0_AXI_PROT_CONGQ_WR_MASK 0xE00000
+
+/* NIC0_QPC0_RES_QPC_CACHE_INVALIDATE */
+#define NIC0_QPC0_RES_QPC_CACHE_INVALIDATE_R_SHIFT 0
+#define NIC0_QPC0_RES_QPC_CACHE_INVALIDATE_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_RES_QPC_CACHE_INV_STATUS */
+#define NIC0_QPC0_RES_QPC_CACHE_INV_STATUS_INVALIDATE_DONE_SHIFT 0
+#define NIC0_QPC0_RES_QPC_CACHE_INV_STATUS_INVALIDATE_DONE_MASK 0x1
+#define NIC0_QPC0_RES_QPC_CACHE_INV_STATUS_CACHE_IDLE_SHIFT 1
+#define NIC0_QPC0_RES_QPC_CACHE_INV_STATUS_CACHE_IDLE_MASK 0x2
+
+/* NIC0_QPC0_RES_STATIC_CONFIG */
+#define NIC0_QPC0_RES_STATIC_CONFIG_PLRU_EVICTION_SHIFT 0
+#define NIC0_QPC0_RES_STATIC_CONFIG_PLRU_EVICTION_MASK 0x1
+#define NIC0_QPC0_RES_STATIC_CONFIG_RELEASE_INVALIDATE_SHIFT 1
+#define NIC0_QPC0_RES_STATIC_CONFIG_RELEASE_INVALIDATE_MASK 0x2
+#define NIC0_QPC0_RES_STATIC_CONFIG_LINK_LIST_EN_SHIFT 2
+#define NIC0_QPC0_RES_STATIC_CONFIG_LINK_LIST_EN_MASK 0x4
+#define NIC0_QPC0_RES_STATIC_CONFIG_RX_PUSH_TO_ERR_FIFO_NON_V_SHIFT 3
+#define NIC0_QPC0_RES_STATIC_CONFIG_RX_PUSH_TO_ERR_FIFO_NON_V_MASK 0x8
+#define NIC0_QPC0_RES_STATIC_CONFIG_TX_PUSH_TO_ERR_FIFO_NON_V_SHIFT 4
+#define NIC0_QPC0_RES_STATIC_CONFIG_TX_PUSH_TO_ERR_FIFO_NON_V_MASK 0x10
+#define NIC0_QPC0_RES_STATIC_CONFIG_CACHE_STOP_SHIFT 5
+#define NIC0_QPC0_RES_STATIC_CONFIG_CACHE_STOP_MASK 0x20
+#define NIC0_QPC0_RES_STATIC_CONFIG_INVALIDATE_WRITEBACK_SHIFT 6
+#define NIC0_QPC0_RES_STATIC_CONFIG_INVALIDATE_WRITEBACK_MASK 0x40
+#define NIC0_QPC0_RES_STATIC_CONFIG_OVR_QP_VALID_TO_NOT_VALID_SHIFT 7
+#define NIC0_QPC0_RES_STATIC_CONFIG_OVR_QP_VALID_TO_NOT_VALID_MASK 0x80
+
+/* NIC0_QPC0_RES_BASE_ADDRESS_63_32 */
+#define NIC0_QPC0_RES_BASE_ADDRESS_63_32_R_SHIFT 0
+#define NIC0_QPC0_RES_BASE_ADDRESS_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_RES_BASE_ADDRESS_31_7 */
+#define NIC0_QPC0_RES_BASE_ADDRESS_31_7_R_SHIFT 0
+#define NIC0_QPC0_RES_BASE_ADDRESS_31_7_R_MASK 0x1FFFFFF
+
+/* NIC0_QPC0_RES_CLEAN_LINK_LIST */
+#define NIC0_QPC0_RES_CLEAN_LINK_LIST_R_SHIFT 0
+#define NIC0_QPC0_RES_CLEAN_LINK_LIST_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_ERR_FIFO_WRITE_INDEX */
+#define NIC0_QPC0_ERR_FIFO_WRITE_INDEX_R_SHIFT 0
+#define NIC0_QPC0_ERR_FIFO_WRITE_INDEX_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_ERR_FIFO_PRODUCER_INDEX */
+#define NIC0_QPC0_ERR_FIFO_PRODUCER_INDEX_R_SHIFT 0
+#define NIC0_QPC0_ERR_FIFO_PRODUCER_INDEX_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_ERR_FIFO_CONSUMER_INDEX */
+#define NIC0_QPC0_ERR_FIFO_CONSUMER_INDEX_R_SHIFT 0
+#define NIC0_QPC0_ERR_FIFO_CONSUMER_INDEX_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_ERR_FIFO_MASK */
+#define NIC0_QPC0_ERR_FIFO_MASK_R_SHIFT 0
+#define NIC0_QPC0_ERR_FIFO_MASK_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_ERR_FIFO_CREDIT */
+#define NIC0_QPC0_ERR_FIFO_CREDIT_MAX_CREDIT_SHIFT 0
+#define NIC0_QPC0_ERR_FIFO_CREDIT_MAX_CREDIT_MASK 0x1F
+#define NIC0_QPC0_ERR_FIFO_CREDIT_FORCE_FULL_SHIFT 5
+#define NIC0_QPC0_ERR_FIFO_CREDIT_FORCE_FULL_MASK 0x20
+
+/* NIC0_QPC0_ERR_FIFO_CFG */
+#define NIC0_QPC0_ERR_FIFO_CFG_ENABLE_SHIFT 0
+#define NIC0_QPC0_ERR_FIFO_CFG_ENABLE_MASK 0x1
+#define NIC0_QPC0_ERR_FIFO_CFG_WRAPAROUND_EN_SHIFT 1
+#define NIC0_QPC0_ERR_FIFO_CFG_WRAPAROUND_EN_MASK 0x2
+#define NIC0_QPC0_ERR_FIFO_CFG_WRAPAROUND_OCCURRED_SHIFT 2
+#define NIC0_QPC0_ERR_FIFO_CFG_WRAPAROUND_OCCURRED_MASK 0x4
+
+/* NIC0_QPC0_ERR_FIFO_INTR_MASK */
+#define NIC0_QPC0_ERR_FIFO_INTR_MASK_R_SHIFT 0
+#define NIC0_QPC0_ERR_FIFO_INTR_MASK_R_MASK 0x1
+
+/* NIC0_QPC0_ERR_FIFO_BASE_ADDR_63_32 */
+#define NIC0_QPC0_ERR_FIFO_BASE_ADDR_63_32_R_SHIFT 0
+#define NIC0_QPC0_ERR_FIFO_BASE_ADDR_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_ERR_FIFO_BASE_ADDR_31_7 */
+#define NIC0_QPC0_ERR_FIFO_BASE_ADDR_31_7_R_SHIFT 7
+#define NIC0_QPC0_ERR_FIFO_BASE_ADDR_31_7_R_MASK 0xFFFFFF80
+
+/* NIC0_QPC0_GW_BUSY */
+#define NIC0_QPC0_GW_BUSY_R_SHIFT 0
+#define NIC0_QPC0_GW_BUSY_R_MASK 0x1
+
+/* NIC0_QPC0_GW_CTRL */
+#define NIC0_QPC0_GW_CTRL_QPN_SHIFT 0
+#define NIC0_QPC0_GW_CTRL_QPN_MASK 0xFFFFFF
+#define NIC0_QPC0_GW_CTRL_REQUESTER_SHIFT 24
+#define NIC0_QPC0_GW_CTRL_REQUESTER_MASK 0x1000000
+#define NIC0_QPC0_GW_CTRL_DOORBELL_MASK_SHIFT 25
+#define NIC0_QPC0_GW_CTRL_DOORBELL_MASK_MASK 0x2000000
+#define NIC0_QPC0_GW_CTRL_DOORBELL_FORCE_SHIFT 26
+#define NIC0_QPC0_GW_CTRL_DOORBELL_FORCE_MASK 0x4000000
+
+/* NIC0_QPC0_GW_DATA */
+#define NIC0_QPC0_GW_DATA_R_SHIFT 0
+#define NIC0_QPC0_GW_DATA_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_GW_MASK */
+#define NIC0_QPC0_GW_MASK_R_SHIFT 0
+#define NIC0_QPC0_GW_MASK_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_CC_TIMEOUT */
+#define NIC0_QPC0_CC_TIMEOUT_HW_EN_SHIFT 0
+#define NIC0_QPC0_CC_TIMEOUT_HW_EN_MASK 0x1
+#define NIC0_QPC0_CC_TIMEOUT_SW_EN_SHIFT 1
+#define NIC0_QPC0_CC_TIMEOUT_SW_EN_MASK 0x2
+
+/* NIC0_QPC0_CC_WINDOW_INC_EN */
+#define NIC0_QPC0_CC_WINDOW_INC_EN_THERSHOLD_SHIFT 0
+#define NIC0_QPC0_CC_WINDOW_INC_EN_THERSHOLD_MASK 0xFFFFFF
+
+/* NIC0_QPC0_CC_TICK_WRAP */
+#define NIC0_QPC0_CC_TICK_WRAP_R_SHIFT 0
+#define NIC0_QPC0_CC_TICK_WRAP_R_MASK 0xFFFF
+
+/* NIC0_QPC0_CC_ROLLBACK */
+#define NIC0_QPC0_CC_ROLLBACK_MANTISSA_SHIFT 0
+#define NIC0_QPC0_CC_ROLLBACK_MANTISSA_MASK 0xFFFFFF
+#define NIC0_QPC0_CC_ROLLBACK_EXPONENT_SHIFT 24
+#define NIC0_QPC0_CC_ROLLBACK_EXPONENT_MASK 0x1F000000
+#define NIC0_QPC0_CC_ROLLBACK_HW_EN_SHIFT 29
+#define NIC0_QPC0_CC_ROLLBACK_HW_EN_MASK 0x20000000
+#define NIC0_QPC0_CC_ROLLBACK_SW_EN_SHIFT 30
+#define NIC0_QPC0_CC_ROLLBACK_SW_EN_MASK 0x40000000
+#define NIC0_QPC0_CC_ROLLBACK_TRIGGER_HW_EN_SHIFT 31
+#define NIC0_QPC0_CC_ROLLBACK_TRIGGER_HW_EN_MASK 0x80000000
+
+/* NIC0_QPC0_CC_MAX_WINDOW_SIZE */
+#define NIC0_QPC0_CC_MAX_WINDOW_SIZE_R_SHIFT 0
+#define NIC0_QPC0_CC_MAX_WINDOW_SIZE_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_CC_MIN_WINDOW_SIZE */
+#define NIC0_QPC0_CC_MIN_WINDOW_SIZE_R_SHIFT 0
+#define NIC0_QPC0_CC_MIN_WINDOW_SIZE_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_CC_ALPHA_LINEAR */
+#define NIC0_QPC0_CC_ALPHA_LINEAR_MANTISSA_SHIFT 0
+#define NIC0_QPC0_CC_ALPHA_LINEAR_MANTISSA_MASK 0xFFFFFF
+#define NIC0_QPC0_CC_ALPHA_LINEAR_EXPONENT_SHIFT 24
+#define NIC0_QPC0_CC_ALPHA_LINEAR_EXPONENT_MASK 0x1F000000
+
+/* NIC0_QPC0_CC_ALPHA_LOG */
+#define NIC0_QPC0_CC_ALPHA_LOG_MANTISSA_SHIFT 0
+#define NIC0_QPC0_CC_ALPHA_LOG_MANTISSA_MASK 0xFFFFFF
+#define NIC0_QPC0_CC_ALPHA_LOG_EXPONENT_SHIFT 24
+#define NIC0_QPC0_CC_ALPHA_LOG_EXPONENT_MASK 0x1F000000
+
+/* NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD */
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_R_SHIFT 0
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_R_MASK 0x1F
+
+/* NIC0_QPC0_CC_WINDOW_INC */
+#define NIC0_QPC0_CC_WINDOW_INC_R_SHIFT 0
+#define NIC0_QPC0_CC_WINDOW_INC_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_CC_WINDOW_IN_THRESHOLD */
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_R_SHIFT 0
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_R_MASK 0x1FFFFFF
+
+/* NIC0_QPC0_DB_FIFO_USER_OVRD */
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_0_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_0_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_1_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_1_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_2_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_2_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_3_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_3_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_4_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_4_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_5_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_5_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_6_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_6_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_7_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_7_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_8_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_8_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_9_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_9_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_10_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_10_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_11_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_11_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_12_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_12_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_13_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_13_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_14_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_14_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_15_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_15_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_16_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_16_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_17_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_17_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_18_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_18_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_19_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_19_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_20_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_20_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_21_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_21_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_22_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_22_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_23_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_23_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_24_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_24_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_25_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_25_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_26_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_26_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_27_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_27_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_28_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_28_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_29_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_29_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_30_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_30_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_31_ASID_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_31_ASID_MASK 0x3FF
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_MMU_BYPASS_SHIFT 10
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_MMU_BYPASS_MASK 0x400
+
+/* NIC0_QPC0_DB_FIFO_CFG */
+#define NIC0_QPC0_DB_FIFO_CFG_BBR_DB_SHIFT 0
+#define NIC0_QPC0_DB_FIFO_CFG_BBR_DB_MASK 0x1
+
+/* NIC0_QPC0_SECURED_DB_FIRST32 */
+#define NIC0_QPC0_SECURED_DB_FIRST32_DATA_SHIFT 0
+#define NIC0_QPC0_SECURED_DB_FIRST32_DATA_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_SECURED_DB_SECOND32 */
+#define NIC0_QPC0_SECURED_DB_SECOND32_DATA_SHIFT 0
+#define NIC0_QPC0_SECURED_DB_SECOND32_DATA_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_SECURED_DB_THIRD32 */
+#define NIC0_QPC0_SECURED_DB_THIRD32_DATA_SHIFT 0
+#define NIC0_QPC0_SECURED_DB_THIRD32_DATA_MASK 0xFFFF
+
+/* NIC0_QPC0_SECURED_DB_FOURTH32 */
+#define NIC0_QPC0_SECURED_DB_FOURTH32_DATA_SHIFT 0
+#define NIC0_QPC0_SECURED_DB_FOURTH32_DATA_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_PRIVILEGE_DB_FIRST32 */
+#define NIC0_QPC0_PRIVILEGE_DB_FIRST32_DATA_SHIFT 0
+#define NIC0_QPC0_PRIVILEGE_DB_FIRST32_DATA_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_PRIVILEGE_DB_SECOND32 */
+#define NIC0_QPC0_PRIVILEGE_DB_SECOND32_DATA_SHIFT 0
+#define NIC0_QPC0_PRIVILEGE_DB_SECOND32_DATA_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_PRIVILEGE_DB_THIRD32 */
+#define NIC0_QPC0_PRIVILEGE_DB_THIRD32_DATA_SHIFT 0
+#define NIC0_QPC0_PRIVILEGE_DB_THIRD32_DATA_MASK 0xFFFF
+
+/* NIC0_QPC0_PRIVILEGE_DB_FOURTH32 */
+#define NIC0_QPC0_PRIVILEGE_DB_FOURTH32_DATA_SHIFT 0
+#define NIC0_QPC0_PRIVILEGE_DB_FOURTH32_DATA_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_DBG_INDICATION */
+#define NIC0_QPC0_DBG_INDICATION_CLOCK_GATE_OPEN_SHIFT 0
+#define NIC0_QPC0_DBG_INDICATION_CLOCK_GATE_OPEN_MASK 0x1
+#define NIC0_QPC0_DBG_INDICATION_REQUESTER_ALL_SLICES_IDLE_SHIFT 1
+#define NIC0_QPC0_DBG_INDICATION_REQUESTER_ALL_SLICES_IDLE_MASK 0x2
+#define NIC0_QPC0_DBG_INDICATION_RESPONDER_ALL_SLICES_IDLE_SHIFT 2
+#define NIC0_QPC0_DBG_INDICATION_RESPONDER_ALL_SLICES_IDLE_MASK 0x4
+#define NIC0_QPC0_DBG_INDICATION_WTD_ALL_SLICES_IDLE_SHIFT 3
+#define NIC0_QPC0_DBG_INDICATION_WTD_ALL_SLICES_IDLE_MASK 0x8
+#define NIC0_QPC0_DBG_INDICATION_DB_FIFOS_EMPTY_SHIFT 4
+#define NIC0_QPC0_DBG_INDICATION_DB_FIFOS_EMPTY_MASK 0x10
+
+/* NIC0_QPC0_WTD_WC_FSM */
+#define NIC0_QPC0_WTD_WC_FSM_STATE_SHIFT 0
+#define NIC0_QPC0_WTD_WC_FSM_STATE_MASK 0x3
+
+/* NIC0_QPC0_WTD_SLICE_FSM */
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE0_STATE_SHIFT 0
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE0_STATE_MASK 0x7
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE1_STATE_SHIFT 4
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE1_STATE_MASK 0x70
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE2_STATE_SHIFT 8
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE2_STATE_MASK 0x700
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE3_STATE_SHIFT 12
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE3_STATE_MASK 0x7000
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE4_STATE_SHIFT 16
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE4_STATE_MASK 0x70000
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE5_STATE_SHIFT 20
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE5_STATE_MASK 0x700000
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE6_STATE_SHIFT 24
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE6_STATE_MASK 0x7000000
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE7_STATE_SHIFT 28
+#define NIC0_QPC0_WTD_SLICE_FSM_SLICE7_STATE_MASK 0x70000000
+
+/* NIC0_QPC0_REQ_TX_EMPTY_CNT */
+#define NIC0_QPC0_REQ_TX_EMPTY_CNT_CNT_SHIFT 0
+#define NIC0_QPC0_REQ_TX_EMPTY_CNT_CNT_MASK 0xFFFFFF
+
+/* NIC0_QPC0_RES_TX_EMPTY_CNT */
+#define NIC0_QPC0_RES_TX_EMPTY_CNT_CNT_SHIFT 0
+#define NIC0_QPC0_RES_TX_EMPTY_CNT_CNT_MASK 0xFFFFFF
+
+/* NIC0_QPC0_NUM_ROLLBACKS */
+#define NIC0_QPC0_NUM_ROLLBACKS_NUM_SHIFT 0
+#define NIC0_QPC0_NUM_ROLLBACKS_NUM_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_LAST_QP_ROLLED_BACK */
+#define NIC0_QPC0_LAST_QP_ROLLED_BACK_QPN_SHIFT 0
+#define NIC0_QPC0_LAST_QP_ROLLED_BACK_QPN_MASK 0xFFFFFF
+
+/* NIC0_QPC0_NUM_TIMEOUTS */
+#define NIC0_QPC0_NUM_TIMEOUTS_NUM_SHIFT 0
+#define NIC0_QPC0_NUM_TIMEOUTS_NUM_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_LAST_QP_TIMED_OUT */
+#define NIC0_QPC0_LAST_QP_TIMED_OUT_QPN_SHIFT 0
+#define NIC0_QPC0_LAST_QP_TIMED_OUT_QPN_MASK 0xFFFFFF
+
+/* NIC0_QPC0_WTD_SLICE_FSM_HI */
+#define NIC0_QPC0_WTD_SLICE_FSM_HI_SLICE8_STATE_SHIFT 0
+#define NIC0_QPC0_WTD_SLICE_FSM_HI_SLICE8_STATE_MASK 0x7
+#define NIC0_QPC0_WTD_SLICE_FSM_HI_SLICE9_STATE_SHIFT 3
+#define NIC0_QPC0_WTD_SLICE_FSM_HI_SLICE9_STATE_MASK 0x38
+
+/* NIC0_QPC0_INTERRUPT_BASE */
+#define NIC0_QPC0_INTERRUPT_BASE_R_SHIFT 0
+#define NIC0_QPC0_INTERRUPT_BASE_R_MASK 0xFFFFFFF
+
+/* NIC0_QPC0_INTERRUPT_DATA */
+#define NIC0_QPC0_INTERRUPT_DATA_R_SHIFT 0
+#define NIC0_QPC0_INTERRUPT_DATA_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_DBG_COUNT_SELECT */
+#define NIC0_QPC0_DBG_COUNT_SELECT_R_SHIFT 0
+#define NIC0_QPC0_DBG_COUNT_SELECT_R_MASK 0x3F
+
+/* NIC0_QPC0_DOORBELL_SECURITY */
+#define NIC0_QPC0_DOORBELL_SECURITY_QMAN_SHIFT 0
+#define NIC0_QPC0_DOORBELL_SECURITY_QMAN_MASK 0x3
+#define NIC0_QPC0_DOORBELL_SECURITY_UNSECURED_SHIFT 2
+#define NIC0_QPC0_DOORBELL_SECURITY_UNSECURED_MASK 0xC
+#define NIC0_QPC0_DOORBELL_SECURITY_SECURED_SHIFT 4
+#define NIC0_QPC0_DOORBELL_SECURITY_SECURED_MASK 0x30
+#define NIC0_QPC0_DOORBELL_SECURITY_PRIVILEGE_SHIFT 6
+#define NIC0_QPC0_DOORBELL_SECURITY_PRIVILEGE_MASK 0xC0
+#define NIC0_QPC0_DOORBELL_SECURITY_QMAN_ASID_SHIFT 8
+#define NIC0_QPC0_DOORBELL_SECURITY_QMAN_ASID_MASK 0x3FF00
+
+/* NIC0_QPC0_DBG_CFG */
+#define NIC0_QPC0_DBG_CFG_TRIG_SHIFT 0
+#define NIC0_QPC0_DBG_CFG_TRIG_MASK 0x7F
+#define NIC0_QPC0_DBG_CFG_REQ_DATA_EVENT_EVERY_UPD_SHIFT 7
+#define NIC0_QPC0_DBG_CFG_REQ_DATA_EVENT_EVERY_UPD_MASK 0x80
+#define NIC0_QPC0_DBG_CFG_SELECT_WTD_SLICE_SHIFT 8
+#define NIC0_QPC0_DBG_CFG_SELECT_WTD_SLICE_MASK 0x700
+
+/* NIC0_QPC0_RES_RING0_PI */
+#define NIC0_QPC0_RES_RING0_PI_R_SHIFT 0
+#define NIC0_QPC0_RES_RING0_PI_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_RES_RING0_CI */
+#define NIC0_QPC0_RES_RING0_CI_R_SHIFT 0
+#define NIC0_QPC0_RES_RING0_CI_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_RES_RING0_CFG */
+#define NIC0_QPC0_RES_RING0_CFG_QPN_SHIFT 0
+#define NIC0_QPC0_RES_RING0_CFG_QPN_MASK 0xFFFFFF
+#define NIC0_QPC0_RES_RING0_CFG_LOG_RING_BUF_SIZE_MASK_SHIFT 24
+#define NIC0_QPC0_RES_RING0_CFG_LOG_RING_BUF_SIZE_MASK_MASK 0x1F000000
+#define NIC0_QPC0_RES_RING0_CFG_WRAPAROUND_SHIFT 31
+#define NIC0_QPC0_RES_RING0_CFG_WRAPAROUND_MASK 0x80000000
+
+/* NIC0_QPC0_RES_RING1_PI */
+#define NIC0_QPC0_RES_RING1_PI_R_SHIFT 0
+#define NIC0_QPC0_RES_RING1_PI_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_RES_RING1_CI */
+#define NIC0_QPC0_RES_RING1_CI_R_SHIFT 0
+#define NIC0_QPC0_RES_RING1_CI_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_RES_RING1_CFG */
+#define NIC0_QPC0_RES_RING1_CFG_QPN_SHIFT 0
+#define NIC0_QPC0_RES_RING1_CFG_QPN_MASK 0xFFFFFF
+#define NIC0_QPC0_RES_RING1_CFG_WRAPAROUND_SHIFT 31
+#define NIC0_QPC0_RES_RING1_CFG_WRAPAROUND_MASK 0x80000000
+
+/* NIC0_QPC0_RES_RING2_PI */
+#define NIC0_QPC0_RES_RING2_PI_R_SHIFT 0
+#define NIC0_QPC0_RES_RING2_PI_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_RES_RING2_CI */
+#define NIC0_QPC0_RES_RING2_CI_R_SHIFT 0
+#define NIC0_QPC0_RES_RING2_CI_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_RES_RING2_CFG */
+#define NIC0_QPC0_RES_RING2_CFG_QPN_SHIFT 0
+#define NIC0_QPC0_RES_RING2_CFG_QPN_MASK 0xFFFFFF
+#define NIC0_QPC0_RES_RING2_CFG_WRAPAROUND_SHIFT 24
+#define NIC0_QPC0_RES_RING2_CFG_WRAPAROUND_MASK 0x1000000
+
+/* NIC0_QPC0_RES_RING3_PI */
+#define NIC0_QPC0_RES_RING3_PI_R_SHIFT 0
+#define NIC0_QPC0_RES_RING3_PI_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_RES_RING3_CI */
+#define NIC0_QPC0_RES_RING3_CI_R_SHIFT 0
+#define NIC0_QPC0_RES_RING3_CI_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_RES_RING3_CFG */
+#define NIC0_QPC0_RES_RING3_CFG_QPN_SHIFT 0
+#define NIC0_QPC0_RES_RING3_CFG_QPN_MASK 0xFFFFFF
+#define NIC0_QPC0_RES_RING3_CFG_WRAPAROUND_SHIFT 24
+#define NIC0_QPC0_RES_RING3_CFG_WRAPAROUND_MASK 0x1000000
+
+/* NIC0_QPC0_REQ_RING0_CI */
+#define NIC0_QPC0_REQ_RING0_CI_R_SHIFT 0
+#define NIC0_QPC0_REQ_RING0_CI_R_MASK 0x3FFFFF
+
+/* NIC0_QPC0_REQ_RING1_CI */
+#define NIC0_QPC0_REQ_RING1_CI_R_SHIFT 0
+#define NIC0_QPC0_REQ_RING1_CI_R_MASK 0x3FFFFF
+
+/* NIC0_QPC0_REQ_RING2_CI */
+#define NIC0_QPC0_REQ_RING2_CI_R_SHIFT 0
+#define NIC0_QPC0_REQ_RING2_CI_R_MASK 0x3FFFFF
+
+/* NIC0_QPC0_REQ_RING3_CI */
+#define NIC0_QPC0_REQ_RING3_CI_R_SHIFT 0
+#define NIC0_QPC0_REQ_RING3_CI_R_MASK 0x3FFFFF
+
+/* NIC0_QPC0_INTERRUPT_CAUSE */
+#define NIC0_QPC0_INTERRUPT_CAUSE_R_SHIFT 0
+#define NIC0_QPC0_INTERRUPT_CAUSE_R_MASK 0x7FF
+
+/* NIC0_QPC0_INTERRUPT_MASK */
+#define NIC0_QPC0_INTERRUPT_MASK_R_SHIFT 0
+#define NIC0_QPC0_INTERRUPT_MASK_R_MASK 0x7FF
+
+/* NIC0_QPC0_INTERRUPT_CLR */
+#define NIC0_QPC0_INTERRUPT_CLR_R_SHIFT 0
+#define NIC0_QPC0_INTERRUPT_CLR_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_INTERRUPT_EN */
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT0_WIRE_EN_SHIFT 0
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT0_WIRE_EN_MASK 0x1
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT0_MSI_EN_SHIFT 1
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT0_MSI_EN_MASK 0x2
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT1_WIRE_EN_SHIFT 2
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT1_WIRE_EN_MASK 0x4
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT1_MSI_EN_SHIFT 3
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT1_MSI_EN_MASK 0x8
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT2_WIRE_EN_SHIFT 4
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT2_WIRE_EN_MASK 0x10
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT2_MSI_EN_SHIFT 5
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT2_MSI_EN_MASK 0x20
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT3_WIRE_EN_SHIFT 6
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT3_WIRE_EN_MASK 0x40
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT3_MSI_EN_SHIFT 7
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT3_MSI_EN_MASK 0x80
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT4_WIRE_EN_SHIFT 8
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT4_WIRE_EN_MASK 0x100
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT4_MSI_EN_SHIFT 9
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT4_MSI_EN_MASK 0x200
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT5_WIRE_EN_SHIFT 10
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT5_WIRE_EN_MASK 0x400
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT5_MSI_EN_SHIFT 11
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT5_MSI_EN_MASK 0x800
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT6_WIRE_EN_SHIFT 12
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT6_WIRE_EN_MASK 0x1000
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT6_MSI_EN_SHIFT 13
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT6_MSI_EN_MASK 0x2000
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT7_WIRE_EN_SHIFT 14
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT7_WIRE_EN_MASK 0x4000
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT7_MSI_EN_SHIFT 15
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT7_MSI_EN_MASK 0x8000
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT8_WIRE_EN_SHIFT 16
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT8_WIRE_EN_MASK 0x10000
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT8_MSI_EN_SHIFT 17
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT8_MSI_EN_MASK 0x20000
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT9_WIRE_EN_SHIFT 18
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT9_WIRE_EN_MASK 0x40000
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT9_MSI_EN_SHIFT 19
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT9_MSI_EN_MASK 0x80000
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT10_WIRE_EN_SHIFT 20
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT10_WIRE_EN_MASK 0x100000
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT10_MSI_EN_SHIFT 21
+#define NIC0_QPC0_INTERRUPT_EN_INTERRUPT10_MSI_EN_MASK 0x200000
+
+/* NIC0_QPC0_INTERRUPT_CFG */
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT0_EACH_UPDATE_SHIFT 0
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT0_EACH_UPDATE_MASK 0x1
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT1_EACH_UPDATE_SHIFT 1
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT1_EACH_UPDATE_MASK 0x2
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT2_EACH_UPDATE_SHIFT 2
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT2_EACH_UPDATE_MASK 0x4
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT3_EACH_UPDATE_SHIFT 3
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT3_EACH_UPDATE_MASK 0x8
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT4_EACH_UPDATE_SHIFT 4
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT4_EACH_UPDATE_MASK 0x10
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT5_EACH_UPDATE_SHIFT 5
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT5_EACH_UPDATE_MASK 0x20
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT6_EACH_UPDATE_SHIFT 6
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT6_EACH_UPDATE_MASK 0x40
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT7_EACH_UPDATE_SHIFT 7
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT7_EACH_UPDATE_MASK 0x80
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT8_EACH_UPDATE_SHIFT 8
+#define NIC0_QPC0_INTERRUPT_CFG_INTERRUPT8_EACH_UPDATE_MASK 0x100
+
+/* NIC0_QPC0_INTERRUPT_RESP_ERR_CAUSE */
+#define NIC0_QPC0_INTERRUPT_RESP_ERR_CAUSE_R_SHIFT 0
+#define NIC0_QPC0_INTERRUPT_RESP_ERR_CAUSE_R_MASK 0x7F
+
+/* NIC0_QPC0_INTERRUPT_RESP_ERR_MASK */
+#define NIC0_QPC0_INTERRUPT_RESP_ERR_MASK_R_SHIFT 0
+#define NIC0_QPC0_INTERRUPT_RESP_ERR_MASK_R_MASK 0x7F
+
+/* NIC0_QPC0_INTERRUPR_RESP_ERR_CLR */
+#define NIC0_QPC0_INTERRUPR_RESP_ERR_CLR_R_SHIFT 0
+#define NIC0_QPC0_INTERRUPR_RESP_ERR_CLR_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_TMR_GW_VALID */
+#define NIC0_QPC0_TMR_GW_VALID_R_SHIFT 0
+#define NIC0_QPC0_TMR_GW_VALID_R_MASK 0x1
+
+/* NIC0_QPC0_TMR_GW_DATA0 */
+#define NIC0_QPC0_TMR_GW_DATA0_OPCODE_SHIFT 0
+#define NIC0_QPC0_TMR_GW_DATA0_OPCODE_MASK 0x3
+
+/* NIC0_QPC0_TMR_GW_DATA1 */
+#define NIC0_QPC0_TMR_GW_DATA1_QPN_SHIFT 0
+#define NIC0_QPC0_TMR_GW_DATA1_QPN_MASK 0xFFFFFF
+#define NIC0_QPC0_TMR_GW_DATA1_TIMER_GRANULARITY_SHIFT 24
+#define NIC0_QPC0_TMR_GW_DATA1_TIMER_GRANULARITY_MASK 0x7F000000
+
+/* NIC0_QPC0_RNR_RETRY_COUNT_EN */
+#define NIC0_QPC0_RNR_RETRY_COUNT_EN_R_SHIFT 0
+#define NIC0_QPC0_RNR_RETRY_COUNT_EN_R_MASK 0x1
+
+/* NIC0_QPC0_EVENT_QUE_BASE_ADDR_63_32 */
+#define NIC0_QPC0_EVENT_QUE_BASE_ADDR_63_32_R_SHIFT 0
+#define NIC0_QPC0_EVENT_QUE_BASE_ADDR_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_EVENT_QUE_BASE_ADDR_31_7 */
+#define NIC0_QPC0_EVENT_QUE_BASE_ADDR_31_7_R_SHIFT 0
+#define NIC0_QPC0_EVENT_QUE_BASE_ADDR_31_7_R_MASK 0x1FFFFFF
+
+/* NIC0_QPC0_EVENT_QUE_LOG_SIZE */
+#define NIC0_QPC0_EVENT_QUE_LOG_SIZE_R_SHIFT 0
+#define NIC0_QPC0_EVENT_QUE_LOG_SIZE_R_MASK 0x1F
+
+/* NIC0_QPC0_EVENT_QUE_WRITE_INDEX */
+#define NIC0_QPC0_EVENT_QUE_WRITE_INDEX_R_SHIFT 0
+#define NIC0_QPC0_EVENT_QUE_WRITE_INDEX_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_EVENT_QUE_PRODUCER_INDEX */
+#define NIC0_QPC0_EVENT_QUE_PRODUCER_INDEX_R_SHIFT 0
+#define NIC0_QPC0_EVENT_QUE_PRODUCER_INDEX_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_EVENT_QUE_PI_ADDR_63_32 */
+#define NIC0_QPC0_EVENT_QUE_PI_ADDR_63_32_R_SHIFT 0
+#define NIC0_QPC0_EVENT_QUE_PI_ADDR_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_EVENT_QUE_PI_ADDR_31_7 */
+#define NIC0_QPC0_EVENT_QUE_PI_ADDR_31_7_R_SHIFT 0
+#define NIC0_QPC0_EVENT_QUE_PI_ADDR_31_7_R_MASK 0x1FFFFFF
+
+/* NIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CB */
+#define NIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CB_R_SHIFT 0
+#define NIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CB_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_EVENT_QUE_CFG */
+#define NIC0_QPC0_EVENT_QUE_CFG_ENABLE_SHIFT 0
+#define NIC0_QPC0_EVENT_QUE_CFG_ENABLE_MASK 0x1
+#define NIC0_QPC0_EVENT_QUE_CFG_OVERRUN_EN_SHIFT 1
+#define NIC0_QPC0_EVENT_QUE_CFG_OVERRUN_EN_MASK 0x2
+#define NIC0_QPC0_EVENT_QUE_CFG_WINDOW_WRAPAROUND_EN_SHIFT 2
+#define NIC0_QPC0_EVENT_QUE_CFG_WINDOW_WRAPAROUND_EN_MASK 0x4
+#define NIC0_QPC0_EVENT_QUE_CFG_WRITE_PI_EN_SHIFT 3
+#define NIC0_QPC0_EVENT_QUE_CFG_WRITE_PI_EN_MASK 0x8
+#define NIC0_QPC0_EVENT_QUE_CFG_INTERRUPT_PER_EQE_SHIFT 4
+#define NIC0_QPC0_EVENT_QUE_CFG_INTERRUPT_PER_EQE_MASK 0x10
+#define NIC0_QPC0_EVENT_QUE_CFG_INTERRUPT_FIRST_EQE_SHIFT 5
+#define NIC0_QPC0_EVENT_QUE_CFG_INTERRUPT_FIRST_EQE_MASK 0x20
+#define NIC0_QPC0_EVENT_QUE_CFG_INTERRUPT_CI_UPDATE_SHIFT 6
+#define NIC0_QPC0_EVENT_QUE_CFG_INTERRUPT_CI_UPDATE_MASK 0x40
+
+/* NIC0_QPC0_LBW_PROT */
+#define NIC0_QPC0_LBW_PROT_INTERRUPT_SHIFT 0
+#define NIC0_QPC0_LBW_PROT_INTERRUPT_MASK 0x7
+#define NIC0_QPC0_LBW_PROT_WQE_BP_SHIFT 3
+#define NIC0_QPC0_LBW_PROT_WQE_BP_MASK 0x38
+
+/* NIC0_QPC0_MEM_WRITE_INIT */
+#define NIC0_QPC0_MEM_WRITE_INIT_REQ_MEM_WRITE_INIT_SHIFT 0
+#define NIC0_QPC0_MEM_WRITE_INIT_REQ_MEM_WRITE_INIT_MASK 0x3
+#define NIC0_QPC0_MEM_WRITE_INIT_RES_MEM_WRITE_INIT_SHIFT 2
+#define NIC0_QPC0_MEM_WRITE_INIT_RES_MEM_WRITE_INIT_MASK 0xC
+#define NIC0_QPC0_MEM_WRITE_INIT_DB_MEM_WRITE_INIT_SHIFT 4
+#define NIC0_QPC0_MEM_WRITE_INIT_DB_MEM_WRITE_INIT_MASK 0x10
+
+/* NIC0_QPC0_QMAN_DOORBELL */
+#define NIC0_QPC0_QMAN_DOORBELL_R_SHIFT 0
+#define NIC0_QPC0_QMAN_DOORBELL_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_QMAN_DOORBELL_QPN */
+#define NIC0_QPC0_QMAN_DOORBELL_QPN_R_SHIFT 0
+#define NIC0_QPC0_QMAN_DOORBELL_QPN_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_SECURED_CQ_NUMBER */
+#define NIC0_QPC0_SECURED_CQ_NUMBER_CQ_NUM_SHIFT 0
+#define NIC0_QPC0_SECURED_CQ_NUMBER_CQ_NUM_MASK 0xFFFF
+
+/* NIC0_QPC0_SECURED_CQ_CONSUMER_INDEX */
+#define NIC0_QPC0_SECURED_CQ_CONSUMER_INDEX_CONSUMER_INDEX_SHIFT 0
+#define NIC0_QPC0_SECURED_CQ_CONSUMER_INDEX_CONSUMER_INDEX_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_PRIVILEGE_CQ_NUMBER */
+#define NIC0_QPC0_PRIVILEGE_CQ_NUMBER_CQ_NUM_SHIFT 0
+#define NIC0_QPC0_PRIVILEGE_CQ_NUMBER_CQ_NUM_MASK 0xFFFF
+
+/* NIC0_QPC0_PRIVILEGE_CQ_CONSUMER_INDEX */
+#define NIC0_QPC0_PRIVILEGE_CQ_CONSUMER_INDEX_CONSUMER_INDEX_SHIFT 0
+#define NIC0_QPC0_PRIVILEGE_CQ_CONSUMER_INDEX_CONSUMER_INDEX_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_TX_WQ_BASE_ADDR_63_32 */
+#define NIC0_QPC0_TX_WQ_BASE_ADDR_63_32_VAL_SHIFT 0
+#define NIC0_QPC0_TX_WQ_BASE_ADDR_63_32_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_TX_WQ_BASE_ADDR_31_0 */
+#define NIC0_QPC0_TX_WQ_BASE_ADDR_31_0_VAL_SHIFT 0
+#define NIC0_QPC0_TX_WQ_BASE_ADDR_31_0_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_LOG_MAX_TX_WQ_SIZE */
+#define NIC0_QPC0_LOG_MAX_TX_WQ_SIZE_VAL_SHIFT 0
+#define NIC0_QPC0_LOG_MAX_TX_WQ_SIZE_VAL_MASK 0x1F
+
+/* NIC0_QPC0_MMU_BYPASS_TX_WQ */
+#define NIC0_QPC0_MMU_BYPASS_TX_WQ_VAL_SHIFT 0
+#define NIC0_QPC0_MMU_BYPASS_TX_WQ_VAL_MASK 0x1
+
+/* NIC0_QPC0_RX_WQ_BASE_ADDR_63_32 */
+#define NIC0_QPC0_RX_WQ_BASE_ADDR_63_32_VAL_SHIFT 0
+#define NIC0_QPC0_RX_WQ_BASE_ADDR_63_32_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_RX_WQ_BASE_ADDR_31_0 */
+#define NIC0_QPC0_RX_WQ_BASE_ADDR_31_0_VAL_SHIFT 0
+#define NIC0_QPC0_RX_WQ_BASE_ADDR_31_0_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_LOG_MAX_RX_WQ_SIZE */
+#define NIC0_QPC0_LOG_MAX_RX_WQ_SIZE_VAL_SHIFT 0
+#define NIC0_QPC0_LOG_MAX_RX_WQ_SIZE_VAL_MASK 0x1F
+
+/* NIC0_QPC0_MMU_BYPASS_RX_WQ */
+#define NIC0_QPC0_MMU_BYPASS_RX_WQ_VAL_SHIFT 0
+#define NIC0_QPC0_MMU_BYPASS_RX_WQ_VAL_MASK 0x1
+
+/* NIC0_QPC0_WQE_MEM_WRITE_AXI_PROT */
+#define NIC0_QPC0_WQE_MEM_WRITE_AXI_PROT_TX_PRIVILEGE_SHIFT 0
+#define NIC0_QPC0_WQE_MEM_WRITE_AXI_PROT_TX_PRIVILEGE_MASK 0x7
+#define NIC0_QPC0_WQE_MEM_WRITE_AXI_PROT_TX_SECURED_SHIFT 3
+#define NIC0_QPC0_WQE_MEM_WRITE_AXI_PROT_TX_SECURED_MASK 0x38
+#define NIC0_QPC0_WQE_MEM_WRITE_AXI_PROT_TX_UNSECURED_SHIFT 6
+#define NIC0_QPC0_WQE_MEM_WRITE_AXI_PROT_TX_UNSECURED_MASK 0x1C0
+#define NIC0_QPC0_WQE_MEM_WRITE_AXI_PROT_RX_PRIVILEGE_SHIFT 9
+#define NIC0_QPC0_WQE_MEM_WRITE_AXI_PROT_RX_PRIVILEGE_MASK 0xE00
+#define NIC0_QPC0_WQE_MEM_WRITE_AXI_PROT_RX_SECURED_SHIFT 12
+#define NIC0_QPC0_WQE_MEM_WRITE_AXI_PROT_RX_SECURED_MASK 0x7000
+#define NIC0_QPC0_WQE_MEM_WRITE_AXI_PROT_RX_UNSECURED_SHIFT 15
+#define NIC0_QPC0_WQE_MEM_WRITE_AXI_PROT_RX_UNSECURED_MASK 0x38000
+
+/* NIC0_QPC0_WQ_UPPER_THRESHOLD */
+#define NIC0_QPC0_WQ_UPPER_THRESHOLD_VAL_SHIFT 0
+#define NIC0_QPC0_WQ_UPPER_THRESHOLD_VAL_MASK 0x3FFFFF
+
+/* NIC0_QPC0_WQ_LOWER_THRESHOLD */
+#define NIC0_QPC0_WQ_LOWER_THRESHOLD_VAL_SHIFT 0
+#define NIC0_QPC0_WQ_LOWER_THRESHOLD_VAL_MASK 0x3FFFFF
+
+/* NIC0_QPC0_WQ_BP_2ARC_ADDR */
+#define NIC0_QPC0_WQ_BP_2ARC_ADDR_VAL_SHIFT 0
+#define NIC0_QPC0_WQ_BP_2ARC_ADDR_VAL_MASK 0xFFFFFFF
+
+/* NIC0_QPC0_WQ_BP_2QMAN_ADDR */
+#define NIC0_QPC0_WQ_BP_2QMAN_ADDR_VAL_SHIFT 0
+#define NIC0_QPC0_WQ_BP_2QMAN_ADDR_VAL_MASK 0xFFFFFFF
+
+/* NIC0_QPC0_WTD_CONFIG */
+#define NIC0_QPC0_WTD_CONFIG_TX_WQE_CACHE_EN_SHIFT 0
+#define NIC0_QPC0_WTD_CONFIG_TX_WQE_CACHE_EN_MASK 0x1
+#define NIC0_QPC0_WTD_CONFIG_IGNORE_QP_ERR_SEND2MEM_SHIFT 1
+#define NIC0_QPC0_WTD_CONFIG_IGNORE_QP_ERR_SEND2MEM_MASK 0x2
+#define NIC0_QPC0_WTD_CONFIG_IGNORE_QP_ERR_SEND2CACHE_SHIFT 2
+#define NIC0_QPC0_WTD_CONFIG_IGNORE_QP_ERR_SEND2CACHE_MASK 0x4
+#define NIC0_QPC0_WTD_CONFIG_WQ_BP_2ARC_EN_SHIFT 4
+#define NIC0_QPC0_WTD_CONFIG_WQ_BP_2ARC_EN_MASK 0x10
+#define NIC0_QPC0_WTD_CONFIG_WQ_BP_2QMAN_EN_SHIFT 5
+#define NIC0_QPC0_WTD_CONFIG_WQ_BP_2QMAN_EN_MASK 0x20
+#define NIC0_QPC0_WTD_CONFIG_WQ_BP_DB_ACCOUNTED_SHIFT 6
+#define NIC0_QPC0_WTD_CONFIG_WQ_BP_DB_ACCOUNTED_MASK 0x40
+#define NIC0_QPC0_WTD_CONFIG_WC_TIMEOUT_EN_SHIFT 7
+#define NIC0_QPC0_WTD_CONFIG_WC_TIMEOUT_EN_MASK 0x80
+#define NIC0_QPC0_WTD_CONFIG_WC_TIMER_WRAP_SHIFT 8
+#define NIC0_QPC0_WTD_CONFIG_WC_TIMER_WRAP_MASK 0xFFFF00
+#define NIC0_QPC0_WTD_CONFIG_WQ_BACKPRESS_IGNORE_QPERR_SHIFT 24
+#define NIC0_QPC0_WTD_CONFIG_WQ_BACKPRESS_IGNORE_QPERR_MASK 0x1000000
+#define NIC0_QPC0_WTD_CONFIG_WTD_WAIT_QPC_UPD_SHIFT 25
+#define NIC0_QPC0_WTD_CONFIG_WTD_WAIT_QPC_UPD_MASK 0x2000000
+
+/* NIC0_QPC0_REQTX_ERR_FIFO_PUSH_63_32 */
+#define NIC0_QPC0_REQTX_ERR_FIFO_PUSH_63_32_VAL_SHIFT 0
+#define NIC0_QPC0_REQTX_ERR_FIFO_PUSH_63_32_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_REQTX_ERR_FIFO_PUSH_31_0 */
+#define NIC0_QPC0_REQTX_ERR_FIFO_PUSH_31_0_VAL_SHIFT 0
+#define NIC0_QPC0_REQTX_ERR_FIFO_PUSH_31_0_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_REQTX_ERR_QP_STATE_63_32 */
+#define NIC0_QPC0_REQTX_ERR_QP_STATE_63_32_VAL_SHIFT 0
+#define NIC0_QPC0_REQTX_ERR_QP_STATE_63_32_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_REQTX_ERR_QP_STATE_31_0 */
+#define NIC0_QPC0_REQTX_ERR_QP_STATE_31_0_VAL_SHIFT 0
+#define NIC0_QPC0_REQTX_ERR_QP_STATE_31_0_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_EVENT_QUE_CONSUMER_INDEX */
+#define NIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CI_SHIFT 0
+#define NIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CI_MASK 0xFFFFFF
+#define NIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_EQ_NUM_SHIFT 24
+#define NIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_EQ_NUM_MASK 0xFF000000
+
+/* NIC0_QPC0_ARM_CQ_NUM */
+#define NIC0_QPC0_ARM_CQ_NUM_CQ_NUM_SHIFT 0
+#define NIC0_QPC0_ARM_CQ_NUM_CQ_NUM_MASK 0xFFFF
+
+/* NIC0_QPC0_ARM_CQ_INDEX */
+#define NIC0_QPC0_ARM_CQ_INDEX_ARM_INDEX_SHIFT 0
+#define NIC0_QPC0_ARM_CQ_INDEX_ARM_INDEX_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_QPC_CLOCK_GATE */
+#define NIC0_QPC0_QPC_CLOCK_GATE_STAY_OPEN_AFTER_TRIG_SHIFT 0
+#define NIC0_QPC0_QPC_CLOCK_GATE_STAY_OPEN_AFTER_TRIG_MASK 0xFFFF
+
+/* NIC0_QPC0_QPC_CLOCK_GATE_DIS */
+#define NIC0_QPC0_QPC_CLOCK_GATE_DIS_QPC_CG_DIS_SHIFT 0
+#define NIC0_QPC0_QPC_CLOCK_GATE_DIS_QPC_CG_DIS_MASK 0x1
+
+/* NIC0_QPC0_CONG_QUE_BASE_ADDR_63_32 */
+#define NIC0_QPC0_CONG_QUE_BASE_ADDR_63_32_R_SHIFT 0
+#define NIC0_QPC0_CONG_QUE_BASE_ADDR_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_CONG_QUE_BASE_ADDR_31_7 */
+#define NIC0_QPC0_CONG_QUE_BASE_ADDR_31_7_R_SHIFT 0
+#define NIC0_QPC0_CONG_QUE_BASE_ADDR_31_7_R_MASK 0x1FFFFFF
+
+/* NIC0_QPC0_CONG_QUE_LOG_SIZE */
+#define NIC0_QPC0_CONG_QUE_LOG_SIZE_R_SHIFT 0
+#define NIC0_QPC0_CONG_QUE_LOG_SIZE_R_MASK 0x1F
+
+/* NIC0_QPC0_CONG_QUE_WRITE_INDEX */
+#define NIC0_QPC0_CONG_QUE_WRITE_INDEX_R_SHIFT 0
+#define NIC0_QPC0_CONG_QUE_WRITE_INDEX_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_CONG_QUE_PRODUCER_INDEX */
+#define NIC0_QPC0_CONG_QUE_PRODUCER_INDEX_R_SHIFT 0
+#define NIC0_QPC0_CONG_QUE_PRODUCER_INDEX_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_CONG_QUE_PI_ADDR_63_32 */
+#define NIC0_QPC0_CONG_QUE_PI_ADDR_63_32_R_SHIFT 0
+#define NIC0_QPC0_CONG_QUE_PI_ADDR_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_CONG_QUE_PI_ADDR_31_7 */
+#define NIC0_QPC0_CONG_QUE_PI_ADDR_31_7_R_SHIFT 0
+#define NIC0_QPC0_CONG_QUE_PI_ADDR_31_7_R_MASK 0x1FFFFFF
+
+/* NIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CB */
+#define NIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CB_R_SHIFT 0
+#define NIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CB_R_MASK 0xFFFFFF
+
+/* NIC0_QPC0_CONG_QUE_CFG */
+#define NIC0_QPC0_CONG_QUE_CFG_ENABLE_SHIFT 0
+#define NIC0_QPC0_CONG_QUE_CFG_ENABLE_MASK 0x1
+#define NIC0_QPC0_CONG_QUE_CFG_OVERRUN_EN_SHIFT 1
+#define NIC0_QPC0_CONG_QUE_CFG_OVERRUN_EN_MASK 0x2
+#define NIC0_QPC0_CONG_QUE_CFG_WINDOW_WRAPAROUND_EN_SHIFT 2
+#define NIC0_QPC0_CONG_QUE_CFG_WINDOW_WRAPAROUND_EN_MASK 0x4
+#define NIC0_QPC0_CONG_QUE_CFG_WRITE_PI_EN_SHIFT 3
+#define NIC0_QPC0_CONG_QUE_CFG_WRITE_PI_EN_MASK 0x8
+#define NIC0_QPC0_CONG_QUE_CFG_EVENT_PER_EQE_SHIFT 4
+#define NIC0_QPC0_CONG_QUE_CFG_EVENT_PER_EQE_MASK 0x10
+#define NIC0_QPC0_CONG_QUE_CFG_EVENT_FIRST_EQE_SHIFT 5
+#define NIC0_QPC0_CONG_QUE_CFG_EVENT_FIRST_EQE_MASK 0x20
+#define NIC0_QPC0_CONG_QUE_CFG_EVENT_CI_UPDATE_SHIFT 6
+#define NIC0_QPC0_CONG_QUE_CFG_EVENT_CI_UPDATE_MASK 0x40
+
+/* NIC0_QPC0_CONG_QUE_CONSUMER_INDEX */
+#define NIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CI_SHIFT 0
+#define NIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CI_MASK 0xFFFFFF
+
+/* NIC0_QPC0_LINEAR_WQE_STATIC */
+#define NIC0_QPC0_LINEAR_WQE_STATIC_R_SHIFT 0
+#define NIC0_QPC0_LINEAR_WQE_STATIC_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_LINEAR_WQE_DYNAMIC */
+#define NIC0_QPC0_LINEAR_WQE_DYNAMIC_R_SHIFT 0
+#define NIC0_QPC0_LINEAR_WQE_DYNAMIC_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_LINEAR_WQE_QPN */
+#define NIC0_QPC0_LINEAR_WQE_QPN_R_SHIFT 0
+#define NIC0_QPC0_LINEAR_WQE_QPN_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_MULTI_STRIDE_WQE_STATIC */
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_R_SHIFT 0
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC */
+#define NIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_R_SHIFT 0
+#define NIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_R_MASK 0xFFFFFFFF
+
+/* NIC0_QPC0_MULTI_STRIDE_WQE_QPN */
+#define NIC0_QPC0_MULTI_STRIDE_WQE_QPN_R_SHIFT 0
+#define NIC0_QPC0_MULTI_STRIDE_WQE_QPN_R_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_NIC0_QPC0_MASKS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_regs.h
new file mode 100644
index 000000000000..1648271a42bc
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_regs.h
@@ -0,0 +1,905 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC0_REGS_H_
+#define ASIC_REG_NIC0_QPC0_REGS_H_
+
+/*****************************************
+ * NIC0_QPC0
+ * (Prototype: NIC_QPC)
+ *****************************************
+ */
+
+#define NIC0_QPC0_REQ_QPC_CACHE_INVALIDATE 0x541F000
+
+#define NIC0_QPC0_REQ_QPC_CACHE_INV_STATUS 0x541F004
+
+#define NIC0_QPC0_REQ_STATIC_CONFIG 0x541F008
+
+#define NIC0_QPC0_REQ_BASE_ADDRESS_63_32 0x541F00C
+
+#define NIC0_QPC0_REQ_BASE_ADDRESS_31_7 0x541F010
+
+#define NIC0_QPC0_REQ_CLEAN_LINK_LIST 0x541F014
+
+#define NIC0_QPC0_REQ_ERR_FIFO_PUSH_63_32 0x541F018
+
+#define NIC0_QPC0_REQ_ERR_FIFO_PUSH_31_0 0x541F01C
+
+#define NIC0_QPC0_REQ_ERR_QP_STATE_63_32 0x541F020
+
+#define NIC0_QPC0_REQ_ERR_QP_STATE_31_0 0x541F024
+
+#define NIC0_QPC0_RETRY_COUNT_MAX 0x541F028
+
+#define NIC0_QPC0_AXI_PROT 0x541F030
+
+#define NIC0_QPC0_RES_QPC_CACHE_INVALIDATE 0x541F034
+
+#define NIC0_QPC0_RES_QPC_CACHE_INV_STATUS 0x541F038
+
+#define NIC0_QPC0_RES_STATIC_CONFIG 0x541F03C
+
+#define NIC0_QPC0_RES_BASE_ADDRESS_63_32 0x541F040
+
+#define NIC0_QPC0_RES_BASE_ADDRESS_31_7 0x541F044
+
+#define NIC0_QPC0_RES_CLEAN_LINK_LIST 0x541F048
+
+#define NIC0_QPC0_ERR_FIFO_WRITE_INDEX 0x541F050
+
+#define NIC0_QPC0_ERR_FIFO_PRODUCER_INDEX 0x541F054
+
+#define NIC0_QPC0_ERR_FIFO_CONSUMER_INDEX 0x541F058
+
+#define NIC0_QPC0_ERR_FIFO_MASK 0x541F05C
+
+#define NIC0_QPC0_ERR_FIFO_CREDIT 0x541F060
+
+#define NIC0_QPC0_ERR_FIFO_CFG 0x541F064
+
+#define NIC0_QPC0_ERR_FIFO_INTR_MASK 0x541F068
+
+#define NIC0_QPC0_ERR_FIFO_BASE_ADDR_63_32 0x541F06C
+
+#define NIC0_QPC0_ERR_FIFO_BASE_ADDR_31_7 0x541F070
+
+#define NIC0_QPC0_GW_BUSY 0x541F080
+
+#define NIC0_QPC0_GW_CTRL 0x541F084
+
+#define NIC0_QPC0_GW_DATA_0 0x541F08C
+
+#define NIC0_QPC0_GW_DATA_1 0x541F090
+
+#define NIC0_QPC0_GW_DATA_2 0x541F094
+
+#define NIC0_QPC0_GW_DATA_3 0x541F098
+
+#define NIC0_QPC0_GW_DATA_4 0x541F09C
+
+#define NIC0_QPC0_GW_DATA_5 0x541F0A0
+
+#define NIC0_QPC0_GW_DATA_6 0x541F0A4
+
+#define NIC0_QPC0_GW_DATA_7 0x541F0A8
+
+#define NIC0_QPC0_GW_DATA_8 0x541F0AC
+
+#define NIC0_QPC0_GW_DATA_9 0x541F0B0
+
+#define NIC0_QPC0_GW_DATA_10 0x541F0B4
+
+#define NIC0_QPC0_GW_DATA_11 0x541F0B8
+
+#define NIC0_QPC0_GW_DATA_12 0x541F0BC
+
+#define NIC0_QPC0_GW_DATA_13 0x541F0C0
+
+#define NIC0_QPC0_GW_DATA_14 0x541F0C4
+
+#define NIC0_QPC0_GW_DATA_15 0x541F0C8
+
+#define NIC0_QPC0_GW_DATA_16 0x541F0CC
+
+#define NIC0_QPC0_GW_DATA_17 0x541F0D0
+
+#define NIC0_QPC0_GW_DATA_18 0x541F0D4
+
+#define NIC0_QPC0_GW_DATA_19 0x541F0D8
+
+#define NIC0_QPC0_GW_DATA_20 0x541F0DC
+
+#define NIC0_QPC0_GW_DATA_21 0x541F0E0
+
+#define NIC0_QPC0_GW_DATA_22 0x541F0E4
+
+#define NIC0_QPC0_GW_DATA_23 0x541F0E8
+
+#define NIC0_QPC0_GW_DATA_24 0x541F0EC
+
+#define NIC0_QPC0_GW_DATA_25 0x541F0F0
+
+#define NIC0_QPC0_GW_DATA_26 0x541F0F4
+
+#define NIC0_QPC0_GW_DATA_27 0x541F0F8
+
+#define NIC0_QPC0_GW_DATA_28 0x541F0FC
+
+#define NIC0_QPC0_GW_DATA_29 0x541F100
+
+#define NIC0_QPC0_GW_DATA_30 0x541F104
+
+#define NIC0_QPC0_GW_DATA_31 0x541F108
+
+#define NIC0_QPC0_GW_MASK_0 0x541F124
+
+#define NIC0_QPC0_GW_MASK_1 0x541F128
+
+#define NIC0_QPC0_GW_MASK_2 0x541F12C
+
+#define NIC0_QPC0_GW_MASK_3 0x541F130
+
+#define NIC0_QPC0_GW_MASK_4 0x541F134
+
+#define NIC0_QPC0_GW_MASK_5 0x541F138
+
+#define NIC0_QPC0_GW_MASK_6 0x541F13C
+
+#define NIC0_QPC0_GW_MASK_7 0x541F140
+
+#define NIC0_QPC0_GW_MASK_8 0x541F144
+
+#define NIC0_QPC0_GW_MASK_9 0x541F148
+
+#define NIC0_QPC0_GW_MASK_10 0x541F14C
+
+#define NIC0_QPC0_GW_MASK_11 0x541F150
+
+#define NIC0_QPC0_GW_MASK_12 0x541F154
+
+#define NIC0_QPC0_GW_MASK_13 0x541F158
+
+#define NIC0_QPC0_GW_MASK_14 0x541F15C
+
+#define NIC0_QPC0_GW_MASK_15 0x541F160
+
+#define NIC0_QPC0_GW_MASK_16 0x541F164
+
+#define NIC0_QPC0_GW_MASK_17 0x541F168
+
+#define NIC0_QPC0_GW_MASK_18 0x541F16C
+
+#define NIC0_QPC0_GW_MASK_19 0x541F170
+
+#define NIC0_QPC0_GW_MASK_20 0x541F174
+
+#define NIC0_QPC0_GW_MASK_21 0x541F178
+
+#define NIC0_QPC0_GW_MASK_22 0x541F17C
+
+#define NIC0_QPC0_GW_MASK_23 0x541F180
+
+#define NIC0_QPC0_GW_MASK_24 0x541F184
+
+#define NIC0_QPC0_GW_MASK_25 0x541F188
+
+#define NIC0_QPC0_GW_MASK_26 0x541F18C
+
+#define NIC0_QPC0_GW_MASK_27 0x541F190
+
+#define NIC0_QPC0_GW_MASK_28 0x541F194
+
+#define NIC0_QPC0_GW_MASK_29 0x541F198
+
+#define NIC0_QPC0_GW_MASK_30 0x541F19C
+
+#define NIC0_QPC0_GW_MASK_31 0x541F1A0
+
+#define NIC0_QPC0_CC_TIMEOUT 0x541F1B0
+
+#define NIC0_QPC0_CC_WINDOW_INC_EN 0x541F1FC
+
+#define NIC0_QPC0_CC_TICK_WRAP 0x541F200
+
+#define NIC0_QPC0_CC_ROLLBACK 0x541F204
+
+#define NIC0_QPC0_CC_MAX_WINDOW_SIZE 0x541F208
+
+#define NIC0_QPC0_CC_MIN_WINDOW_SIZE 0x541F20C
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_0 0x541F210
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_1 0x541F214
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_2 0x541F218
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_3 0x541F21C
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_4 0x541F220
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_5 0x541F224
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_6 0x541F228
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_7 0x541F22C
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_8 0x541F230
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_9 0x541F234
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_10 0x541F238
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_11 0x541F23C
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_12 0x541F240
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_13 0x541F244
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_14 0x541F248
+
+#define NIC0_QPC0_CC_ALPHA_LINEAR_15 0x541F24C
+
+#define NIC0_QPC0_CC_ALPHA_LOG_0 0x541F250
+
+#define NIC0_QPC0_CC_ALPHA_LOG_1 0x541F254
+
+#define NIC0_QPC0_CC_ALPHA_LOG_2 0x541F258
+
+#define NIC0_QPC0_CC_ALPHA_LOG_3 0x541F25C
+
+#define NIC0_QPC0_CC_ALPHA_LOG_4 0x541F260
+
+#define NIC0_QPC0_CC_ALPHA_LOG_5 0x541F264
+
+#define NIC0_QPC0_CC_ALPHA_LOG_6 0x541F268
+
+#define NIC0_QPC0_CC_ALPHA_LOG_7 0x541F26C
+
+#define NIC0_QPC0_CC_ALPHA_LOG_8 0x541F270
+
+#define NIC0_QPC0_CC_ALPHA_LOG_9 0x541F274
+
+#define NIC0_QPC0_CC_ALPHA_LOG_10 0x541F278
+
+#define NIC0_QPC0_CC_ALPHA_LOG_11 0x541F27C
+
+#define NIC0_QPC0_CC_ALPHA_LOG_12 0x541F280
+
+#define NIC0_QPC0_CC_ALPHA_LOG_13 0x541F284
+
+#define NIC0_QPC0_CC_ALPHA_LOG_14 0x541F288
+
+#define NIC0_QPC0_CC_ALPHA_LOG_15 0x541F28C
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_0 0x541F290
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_1 0x541F294
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_2 0x541F298
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_3 0x541F29C
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_4 0x541F2A0
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_5 0x541F2A4
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_6 0x541F2A8
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_7 0x541F2AC
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_8 0x541F2B0
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_9 0x541F2B4
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_10 0x541F2B8
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_11 0x541F2BC
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_12 0x541F2C0
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_13 0x541F2C4
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_14 0x541F2C8
+
+#define NIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_15 0x541F2CC
+
+#define NIC0_QPC0_CC_WINDOW_INC_0 0x541F2D0
+
+#define NIC0_QPC0_CC_WINDOW_INC_1 0x541F2D4
+
+#define NIC0_QPC0_CC_WINDOW_INC_2 0x541F2D8
+
+#define NIC0_QPC0_CC_WINDOW_INC_3 0x541F2DC
+
+#define NIC0_QPC0_CC_WINDOW_INC_4 0x541F2E0
+
+#define NIC0_QPC0_CC_WINDOW_INC_5 0x541F2E4
+
+#define NIC0_QPC0_CC_WINDOW_INC_6 0x541F2E8
+
+#define NIC0_QPC0_CC_WINDOW_INC_7 0x541F2EC
+
+#define NIC0_QPC0_CC_WINDOW_INC_8 0x541F2F0
+
+#define NIC0_QPC0_CC_WINDOW_INC_9 0x541F2F4
+
+#define NIC0_QPC0_CC_WINDOW_INC_10 0x541F2F8
+
+#define NIC0_QPC0_CC_WINDOW_INC_11 0x541F2FC
+
+#define NIC0_QPC0_CC_WINDOW_INC_12 0x541F300
+
+#define NIC0_QPC0_CC_WINDOW_INC_13 0x541F304
+
+#define NIC0_QPC0_CC_WINDOW_INC_14 0x541F308
+
+#define NIC0_QPC0_CC_WINDOW_INC_15 0x541F30C
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_0 0x541F310
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_1 0x541F314
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_2 0x541F318
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_3 0x541F31C
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_4 0x541F320
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_5 0x541F324
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_6 0x541F328
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_7 0x541F32C
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_8 0x541F330
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_9 0x541F334
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_10 0x541F338
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_11 0x541F33C
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_12 0x541F340
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_13 0x541F344
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_14 0x541F348
+
+#define NIC0_QPC0_CC_WINDOW_IN_THRESHOLD_15 0x541F34C
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_0 0x541F360
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_1 0x541F364
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_2 0x541F368
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_3 0x541F36C
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_4 0x541F370
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_5 0x541F374
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_6 0x541F378
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_7 0x541F37C
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_8 0x541F380
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_9 0x541F384
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_10 0x541F388
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_11 0x541F38C
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_12 0x541F390
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_13 0x541F394
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_14 0x541F398
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_15 0x541F39C
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_16 0x541F3A0
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_17 0x541F3A4
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_18 0x541F3A8
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_19 0x541F3AC
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_20 0x541F3B0
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_21 0x541F3B4
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_22 0x541F3B8
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_23 0x541F3BC
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_24 0x541F3C0
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_25 0x541F3C4
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_26 0x541F3C8
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_27 0x541F3CC
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_28 0x541F3D0
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_29 0x541F3D4
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_30 0x541F3D8
+
+#define NIC0_QPC0_DB_FIFO_USER_OVRD_31 0x541F3DC
+
+#define NIC0_QPC0_DB_FIFO_CFG_0 0x541F3E0
+
+#define NIC0_QPC0_DB_FIFO_CFG_1 0x541F3E4
+
+#define NIC0_QPC0_DB_FIFO_CFG_2 0x541F3E8
+
+#define NIC0_QPC0_DB_FIFO_CFG_3 0x541F3EC
+
+#define NIC0_QPC0_DB_FIFO_CFG_4 0x541F3F0
+
+#define NIC0_QPC0_DB_FIFO_CFG_5 0x541F3F4
+
+#define NIC0_QPC0_DB_FIFO_CFG_6 0x541F3F8
+
+#define NIC0_QPC0_DB_FIFO_CFG_7 0x541F3FC
+
+#define NIC0_QPC0_DB_FIFO_CFG_8 0x541F400
+
+#define NIC0_QPC0_DB_FIFO_CFG_9 0x541F404
+
+#define NIC0_QPC0_DB_FIFO_CFG_10 0x541F408
+
+#define NIC0_QPC0_DB_FIFO_CFG_11 0x541F40C
+
+#define NIC0_QPC0_DB_FIFO_CFG_12 0x541F410
+
+#define NIC0_QPC0_DB_FIFO_CFG_13 0x541F414
+
+#define NIC0_QPC0_DB_FIFO_CFG_14 0x541F418
+
+#define NIC0_QPC0_DB_FIFO_CFG_15 0x541F41C
+
+#define NIC0_QPC0_DB_FIFO_CFG_16 0x541F420
+
+#define NIC0_QPC0_DB_FIFO_CFG_17 0x541F424
+
+#define NIC0_QPC0_DB_FIFO_CFG_18 0x541F428
+
+#define NIC0_QPC0_DB_FIFO_CFG_19 0x541F42C
+
+#define NIC0_QPC0_DB_FIFO_CFG_20 0x541F430
+
+#define NIC0_QPC0_DB_FIFO_CFG_21 0x541F434
+
+#define NIC0_QPC0_DB_FIFO_CFG_22 0x541F438
+
+#define NIC0_QPC0_DB_FIFO_CFG_23 0x541F43C
+
+#define NIC0_QPC0_DB_FIFO_CFG_24 0x541F440
+
+#define NIC0_QPC0_DB_FIFO_CFG_25 0x541F444
+
+#define NIC0_QPC0_DB_FIFO_CFG_26 0x541F448
+
+#define NIC0_QPC0_DB_FIFO_CFG_27 0x541F44C
+
+#define NIC0_QPC0_DB_FIFO_CFG_28 0x541F450
+
+#define NIC0_QPC0_DB_FIFO_CFG_29 0x541F454
+
+#define NIC0_QPC0_DB_FIFO_CFG_30 0x541F458
+
+#define NIC0_QPC0_DB_FIFO_CFG_31 0x541F45C
+
+#define NIC0_QPC0_SECURED_DB_FIRST32 0x541F460
+
+#define NIC0_QPC0_SECURED_DB_SECOND32 0x541F464
+
+#define NIC0_QPC0_SECURED_DB_THIRD32 0x541F468
+
+#define NIC0_QPC0_SECURED_DB_FOURTH32 0x541F46C
+
+#define NIC0_QPC0_PRIVILEGE_DB_FIRST32 0x541F470
+
+#define NIC0_QPC0_PRIVILEGE_DB_SECOND32 0x541F474
+
+#define NIC0_QPC0_PRIVILEGE_DB_THIRD32 0x541F478
+
+#define NIC0_QPC0_PRIVILEGE_DB_FOURTH32 0x541F47C
+
+#define NIC0_QPC0_DBG_INDICATION 0x541F480
+
+#define NIC0_QPC0_WTD_WC_FSM 0x541F484
+
+#define NIC0_QPC0_WTD_SLICE_FSM 0x541F488
+
+#define NIC0_QPC0_REQ_TX_EMPTY_CNT 0x541F48C
+
+#define NIC0_QPC0_RES_TX_EMPTY_CNT 0x541F490
+
+#define NIC0_QPC0_NUM_ROLLBACKS 0x541F494
+
+#define NIC0_QPC0_LAST_QP_ROLLED_BACK 0x541F498
+
+#define NIC0_QPC0_NUM_TIMEOUTS 0x541F49C
+
+#define NIC0_QPC0_LAST_QP_TIMED_OUT 0x541F4A0
+
+#define NIC0_QPC0_WTD_SLICE_FSM_HI 0x541F4A4
+
+#define NIC0_QPC0_INTERRUPT_BASE_0 0x541F4B0
+
+#define NIC0_QPC0_INTERRUPT_BASE_1 0x541F4B4
+
+#define NIC0_QPC0_INTERRUPT_BASE_2 0x541F4B8
+
+#define NIC0_QPC0_INTERRUPT_BASE_3 0x541F4BC
+
+#define NIC0_QPC0_INTERRUPT_BASE_4 0x541F4C0
+
+#define NIC0_QPC0_INTERRUPT_BASE_5 0x541F4C4
+
+#define NIC0_QPC0_INTERRUPT_BASE_6 0x541F4C8
+
+#define NIC0_QPC0_INTERRUPT_BASE_7 0x541F4CC
+
+#define NIC0_QPC0_INTERRUPT_BASE_8 0x541F4D0
+
+#define NIC0_QPC0_INTERRUPT_BASE_9 0x541F4D4
+
+#define NIC0_QPC0_INTERRUPT_BASE_10 0x541F4D8
+
+#define NIC0_QPC0_INTERRUPT_DATA_0 0x541F4DC
+
+#define NIC0_QPC0_INTERRUPT_DATA_1 0x541F4E0
+
+#define NIC0_QPC0_INTERRUPT_DATA_2 0x541F4E4
+
+#define NIC0_QPC0_INTERRUPT_DATA_3 0x541F4E8
+
+#define NIC0_QPC0_INTERRUPT_DATA_4 0x541F4EC
+
+#define NIC0_QPC0_INTERRUPT_DATA_5 0x541F4F0
+
+#define NIC0_QPC0_INTERRUPT_DATA_6 0x541F4F4
+
+#define NIC0_QPC0_INTERRUPT_DATA_7 0x541F4F8
+
+#define NIC0_QPC0_INTERRUPT_DATA_8 0x541F4FC
+
+#define NIC0_QPC0_INTERRUPT_DATA_9 0x541F500
+
+#define NIC0_QPC0_INTERRUPT_DATA_10 0x541F504
+
+#define NIC0_QPC0_DBG_COUNT_SELECT_0 0x541F600
+
+#define NIC0_QPC0_DBG_COUNT_SELECT_1 0x541F604
+
+#define NIC0_QPC0_DBG_COUNT_SELECT_2 0x541F608
+
+#define NIC0_QPC0_DBG_COUNT_SELECT_3 0x541F60C
+
+#define NIC0_QPC0_DBG_COUNT_SELECT_4 0x541F610
+
+#define NIC0_QPC0_DBG_COUNT_SELECT_5 0x541F614
+
+#define NIC0_QPC0_DBG_COUNT_SELECT_6 0x541F618
+
+#define NIC0_QPC0_DBG_COUNT_SELECT_7 0x541F61C
+
+#define NIC0_QPC0_DBG_COUNT_SELECT_8 0x541F620
+
+#define NIC0_QPC0_DBG_COUNT_SELECT_9 0x541F624
+
+#define NIC0_QPC0_DBG_COUNT_SELECT_10 0x541F628
+
+#define NIC0_QPC0_DBG_COUNT_SELECT_11 0x541F62C
+
+#define NIC0_QPC0_DOORBELL_SECURITY 0x541F648
+
+#define NIC0_QPC0_DBG_CFG 0x541F64C
+
+#define NIC0_QPC0_RES_RING0_PI 0x541F650
+
+#define NIC0_QPC0_RES_RING0_CI 0x541F654
+
+#define NIC0_QPC0_RES_RING0_CFG 0x541F658
+
+#define NIC0_QPC0_RES_RING1_PI 0x541F65C
+
+#define NIC0_QPC0_RES_RING1_CI 0x541F660
+
+#define NIC0_QPC0_RES_RING1_CFG 0x541F664
+
+#define NIC0_QPC0_RES_RING2_PI 0x541F668
+
+#define NIC0_QPC0_RES_RING2_CI 0x541F66C
+
+#define NIC0_QPC0_RES_RING2_CFG 0x541F670
+
+#define NIC0_QPC0_RES_RING3_PI 0x541F674
+
+#define NIC0_QPC0_RES_RING3_CI 0x541F678
+
+#define NIC0_QPC0_RES_RING3_CFG 0x541F67C
+
+#define NIC0_QPC0_REQ_RING0_CI 0x541F680
+
+#define NIC0_QPC0_REQ_RING1_CI 0x541F684
+
+#define NIC0_QPC0_REQ_RING2_CI 0x541F688
+
+#define NIC0_QPC0_REQ_RING3_CI 0x541F68C
+
+#define NIC0_QPC0_INTERRUPT_CAUSE 0x541F690
+
+#define NIC0_QPC0_INTERRUPT_MASK 0x541F694
+
+#define NIC0_QPC0_INTERRUPT_CLR 0x541F698
+
+#define NIC0_QPC0_INTERRUPT_EN 0x541F69C
+
+#define NIC0_QPC0_INTERRUPT_CFG 0x541F6F0
+
+#define NIC0_QPC0_INTERRUPT_RESP_ERR_CAUSE 0x541F6F4
+
+#define NIC0_QPC0_INTERRUPT_RESP_ERR_MASK 0x541F6F8
+
+#define NIC0_QPC0_INTERRUPR_RESP_ERR_CLR 0x541F700
+
+#define NIC0_QPC0_TMR_GW_VALID 0x541F704
+
+#define NIC0_QPC0_TMR_GW_DATA0 0x541F708
+
+#define NIC0_QPC0_TMR_GW_DATA1 0x541F70C
+
+#define NIC0_QPC0_RNR_RETRY_COUNT_EN 0x541F710
+
+#define NIC0_QPC0_EVENT_QUE_BASE_ADDR_63_32 0x541F830
+
+#define NIC0_QPC0_EVENT_QUE_BASE_ADDR_31_7 0x541F834
+
+#define NIC0_QPC0_EVENT_QUE_LOG_SIZE 0x541F838
+
+#define NIC0_QPC0_EVENT_QUE_WRITE_INDEX 0x541F83C
+
+#define NIC0_QPC0_EVENT_QUE_PRODUCER_INDEX 0x541F840
+
+#define NIC0_QPC0_EVENT_QUE_PI_ADDR_63_32 0x541F844
+
+#define NIC0_QPC0_EVENT_QUE_PI_ADDR_31_7 0x541F848
+
+#define NIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CB 0x541F84C
+
+#define NIC0_QPC0_EVENT_QUE_CFG 0x541F850
+
+#define NIC0_QPC0_LBW_PROT 0x541F858
+
+#define NIC0_QPC0_MEM_WRITE_INIT 0x541F85C
+
+#define NIC0_QPC0_QMAN_DOORBELL 0x541F8E8
+
+#define NIC0_QPC0_QMAN_DOORBELL_QPN 0x541F8EC
+
+#define NIC0_QPC0_SECURED_CQ_NUMBER 0x541F8F0
+
+#define NIC0_QPC0_SECURED_CQ_CONSUMER_INDEX 0x541F8F4
+
+#define NIC0_QPC0_PRIVILEGE_CQ_NUMBER 0x541F8F8
+
+#define NIC0_QPC0_PRIVILEGE_CQ_CONSUMER_INDEX 0x541F8FC
+
+#define NIC0_QPC0_TX_WQ_BASE_ADDR_63_32_0 0x541F900
+
+#define NIC0_QPC0_TX_WQ_BASE_ADDR_63_32_1 0x541F904
+
+#define NIC0_QPC0_TX_WQ_BASE_ADDR_63_32_2 0x541F908
+
+#define NIC0_QPC0_TX_WQ_BASE_ADDR_63_32_3 0x541F90C
+
+#define NIC0_QPC0_TX_WQ_BASE_ADDR_31_0_0 0x541F910
+
+#define NIC0_QPC0_TX_WQ_BASE_ADDR_31_0_1 0x541F914
+
+#define NIC0_QPC0_TX_WQ_BASE_ADDR_31_0_2 0x541F918
+
+#define NIC0_QPC0_TX_WQ_BASE_ADDR_31_0_3 0x541F91C
+
+#define NIC0_QPC0_LOG_MAX_TX_WQ_SIZE_0 0x541F920
+
+#define NIC0_QPC0_LOG_MAX_TX_WQ_SIZE_1 0x541F924
+
+#define NIC0_QPC0_LOG_MAX_TX_WQ_SIZE_2 0x541F928
+
+#define NIC0_QPC0_LOG_MAX_TX_WQ_SIZE_3 0x541F92C
+
+#define NIC0_QPC0_MMU_BYPASS_TX_WQ_0 0x541F930
+
+#define NIC0_QPC0_MMU_BYPASS_TX_WQ_1 0x541F934
+
+#define NIC0_QPC0_MMU_BYPASS_TX_WQ_2 0x541F938
+
+#define NIC0_QPC0_MMU_BYPASS_TX_WQ_3 0x541F93C
+
+#define NIC0_QPC0_RX_WQ_BASE_ADDR_63_32_0 0x541F940
+
+#define NIC0_QPC0_RX_WQ_BASE_ADDR_63_32_1 0x541F944
+
+#define NIC0_QPC0_RX_WQ_BASE_ADDR_63_32_2 0x541F948
+
+#define NIC0_QPC0_RX_WQ_BASE_ADDR_63_32_3 0x541F94C
+
+#define NIC0_QPC0_RX_WQ_BASE_ADDR_31_0_0 0x541F950
+
+#define NIC0_QPC0_RX_WQ_BASE_ADDR_31_0_1 0x541F954
+
+#define NIC0_QPC0_RX_WQ_BASE_ADDR_31_0_2 0x541F958
+
+#define NIC0_QPC0_RX_WQ_BASE_ADDR_31_0_3 0x541F95C
+
+#define NIC0_QPC0_LOG_MAX_RX_WQ_SIZE_0 0x541F960
+
+#define NIC0_QPC0_LOG_MAX_RX_WQ_SIZE_1 0x541F964
+
+#define NIC0_QPC0_LOG_MAX_RX_WQ_SIZE_2 0x541F968
+
+#define NIC0_QPC0_LOG_MAX_RX_WQ_SIZE_3 0x541F96C
+
+#define NIC0_QPC0_MMU_BYPASS_RX_WQ_0 0x541F970
+
+#define NIC0_QPC0_MMU_BYPASS_RX_WQ_1 0x541F974
+
+#define NIC0_QPC0_MMU_BYPASS_RX_WQ_2 0x541F978
+
+#define NIC0_QPC0_MMU_BYPASS_RX_WQ_3 0x541F97C
+
+#define NIC0_QPC0_WQE_MEM_WRITE_AXI_PROT 0x541F980
+
+#define NIC0_QPC0_WQ_UPPER_THRESHOLD 0x541F984
+
+#define NIC0_QPC0_WQ_LOWER_THRESHOLD 0x541F988
+
+#define NIC0_QPC0_WQ_BP_2ARC_ADDR 0x541F98C
+
+#define NIC0_QPC0_WQ_BP_2QMAN_ADDR 0x541F990
+
+#define NIC0_QPC0_WTD_CONFIG 0x541F994
+
+#define NIC0_QPC0_REQTX_ERR_FIFO_PUSH_63_32 0x541F998
+
+#define NIC0_QPC0_REQTX_ERR_FIFO_PUSH_31_0 0x541F99C
+
+#define NIC0_QPC0_REQTX_ERR_QP_STATE_63_32 0x541F9A0
+
+#define NIC0_QPC0_REQTX_ERR_QP_STATE_31_0 0x541F9A4
+
+#define NIC0_QPC0_EVENT_QUE_CONSUMER_INDEX 0x541F9A8
+
+#define NIC0_QPC0_ARM_CQ_NUM 0x541F9AC
+
+#define NIC0_QPC0_ARM_CQ_INDEX 0x541F9B0
+
+#define NIC0_QPC0_QPC_CLOCK_GATE 0x541F9B4
+
+#define NIC0_QPC0_QPC_CLOCK_GATE_DIS 0x541F9B8
+
+#define NIC0_QPC0_CONG_QUE_BASE_ADDR_63_32 0x541F9BC
+
+#define NIC0_QPC0_CONG_QUE_BASE_ADDR_31_7 0x541F9C0
+
+#define NIC0_QPC0_CONG_QUE_LOG_SIZE 0x541F9C4
+
+#define NIC0_QPC0_CONG_QUE_WRITE_INDEX 0x541F9C8
+
+#define NIC0_QPC0_CONG_QUE_PRODUCER_INDEX 0x541F9CC
+
+#define NIC0_QPC0_CONG_QUE_PI_ADDR_63_32 0x541F9D0
+
+#define NIC0_QPC0_CONG_QUE_PI_ADDR_31_7 0x541F9D4
+
+#define NIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CB 0x541F9D8
+
+#define NIC0_QPC0_CONG_QUE_CFG 0x541F9DC
+
+#define NIC0_QPC0_CONG_QUE_CONSUMER_INDEX 0x541F9E0
+
+#define NIC0_QPC0_LINEAR_WQE_STATIC_0 0x541FA00
+
+#define NIC0_QPC0_LINEAR_WQE_STATIC_1 0x541FA04
+
+#define NIC0_QPC0_LINEAR_WQE_STATIC_2 0x541FA08
+
+#define NIC0_QPC0_LINEAR_WQE_STATIC_3 0x541FA0C
+
+#define NIC0_QPC0_LINEAR_WQE_STATIC_4 0x541FA10
+
+#define NIC0_QPC0_LINEAR_WQE_STATIC_5 0x541FA14
+
+#define NIC0_QPC0_LINEAR_WQE_STATIC_6 0x541FA18
+
+#define NIC0_QPC0_LINEAR_WQE_STATIC_7 0x541FA1C
+
+#define NIC0_QPC0_LINEAR_WQE_STATIC_8 0x541FA20
+
+#define NIC0_QPC0_LINEAR_WQE_STATIC_9 0x541FA24
+
+#define NIC0_QPC0_LINEAR_WQE_DYNAMIC_0 0x541FA40
+
+#define NIC0_QPC0_LINEAR_WQE_DYNAMIC_1 0x541FA44
+
+#define NIC0_QPC0_LINEAR_WQE_DYNAMIC_2 0x541FA48
+
+#define NIC0_QPC0_LINEAR_WQE_DYNAMIC_3 0x541FA4C
+
+#define NIC0_QPC0_LINEAR_WQE_DYNAMIC_4 0x541FA50
+
+#define NIC0_QPC0_LINEAR_WQE_DYNAMIC_5 0x541FA54
+
+#define NIC0_QPC0_LINEAR_WQE_QPN 0x541FA58
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0 0x541FA80
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1 0x541FA84
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2 0x541FA88
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3 0x541FA8C
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4 0x541FA90
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5 0x541FA94
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6 0x541FA98
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7 0x541FA9C
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8 0x541FAA0
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9 0x541FAA4
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10 0x541FAA8
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11 0x541FAAC
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12 0x541FAB0
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13 0x541FAB4
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14 0x541FAB8
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15 0x541FABC
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16 0x541FAC0
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17 0x541FAC4
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0 0x541FAE0
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1 0x541FAE4
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2 0x541FAE8
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3 0x541FAEC
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4 0x541FAF0
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5 0x541FAF4
+
+#define NIC0_QPC0_MULTI_STRIDE_WQE_QPN 0x541FAF8
+
+#endif /* ASIC_REG_NIC0_QPC0_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc1_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc1_regs.h
new file mode 100644
index 000000000000..643cff14447e
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc1_regs.h
@@ -0,0 +1,905 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC1_REGS_H_
+#define ASIC_REG_NIC0_QPC1_REGS_H_
+
+/*****************************************
+ * NIC0_QPC1
+ * (Prototype: NIC_QPC)
+ *****************************************
+ */
+
+#define NIC0_QPC1_REQ_QPC_CACHE_INVALIDATE 0x543F000
+
+#define NIC0_QPC1_REQ_QPC_CACHE_INV_STATUS 0x543F004
+
+#define NIC0_QPC1_REQ_STATIC_CONFIG 0x543F008
+
+#define NIC0_QPC1_REQ_BASE_ADDRESS_63_32 0x543F00C
+
+#define NIC0_QPC1_REQ_BASE_ADDRESS_31_7 0x543F010
+
+#define NIC0_QPC1_REQ_CLEAN_LINK_LIST 0x543F014
+
+#define NIC0_QPC1_REQ_ERR_FIFO_PUSH_63_32 0x543F018
+
+#define NIC0_QPC1_REQ_ERR_FIFO_PUSH_31_0 0x543F01C
+
+#define NIC0_QPC1_REQ_ERR_QP_STATE_63_32 0x543F020
+
+#define NIC0_QPC1_REQ_ERR_QP_STATE_31_0 0x543F024
+
+#define NIC0_QPC1_RETRY_COUNT_MAX 0x543F028
+
+#define NIC0_QPC1_AXI_PROT 0x543F030
+
+#define NIC0_QPC1_RES_QPC_CACHE_INVALIDATE 0x543F034
+
+#define NIC0_QPC1_RES_QPC_CACHE_INV_STATUS 0x543F038
+
+#define NIC0_QPC1_RES_STATIC_CONFIG 0x543F03C
+
+#define NIC0_QPC1_RES_BASE_ADDRESS_63_32 0x543F040
+
+#define NIC0_QPC1_RES_BASE_ADDRESS_31_7 0x543F044
+
+#define NIC0_QPC1_RES_CLEAN_LINK_LIST 0x543F048
+
+#define NIC0_QPC1_ERR_FIFO_WRITE_INDEX 0x543F050
+
+#define NIC0_QPC1_ERR_FIFO_PRODUCER_INDEX 0x543F054
+
+#define NIC0_QPC1_ERR_FIFO_CONSUMER_INDEX 0x543F058
+
+#define NIC0_QPC1_ERR_FIFO_MASK 0x543F05C
+
+#define NIC0_QPC1_ERR_FIFO_CREDIT 0x543F060
+
+#define NIC0_QPC1_ERR_FIFO_CFG 0x543F064
+
+#define NIC0_QPC1_ERR_FIFO_INTR_MASK 0x543F068
+
+#define NIC0_QPC1_ERR_FIFO_BASE_ADDR_63_32 0x543F06C
+
+#define NIC0_QPC1_ERR_FIFO_BASE_ADDR_31_7 0x543F070
+
+#define NIC0_QPC1_GW_BUSY 0x543F080
+
+#define NIC0_QPC1_GW_CTRL 0x543F084
+
+#define NIC0_QPC1_GW_DATA_0 0x543F08C
+
+#define NIC0_QPC1_GW_DATA_1 0x543F090
+
+#define NIC0_QPC1_GW_DATA_2 0x543F094
+
+#define NIC0_QPC1_GW_DATA_3 0x543F098
+
+#define NIC0_QPC1_GW_DATA_4 0x543F09C
+
+#define NIC0_QPC1_GW_DATA_5 0x543F0A0
+
+#define NIC0_QPC1_GW_DATA_6 0x543F0A4
+
+#define NIC0_QPC1_GW_DATA_7 0x543F0A8
+
+#define NIC0_QPC1_GW_DATA_8 0x543F0AC
+
+#define NIC0_QPC1_GW_DATA_9 0x543F0B0
+
+#define NIC0_QPC1_GW_DATA_10 0x543F0B4
+
+#define NIC0_QPC1_GW_DATA_11 0x543F0B8
+
+#define NIC0_QPC1_GW_DATA_12 0x543F0BC
+
+#define NIC0_QPC1_GW_DATA_13 0x543F0C0
+
+#define NIC0_QPC1_GW_DATA_14 0x543F0C4
+
+#define NIC0_QPC1_GW_DATA_15 0x543F0C8
+
+#define NIC0_QPC1_GW_DATA_16 0x543F0CC
+
+#define NIC0_QPC1_GW_DATA_17 0x543F0D0
+
+#define NIC0_QPC1_GW_DATA_18 0x543F0D4
+
+#define NIC0_QPC1_GW_DATA_19 0x543F0D8
+
+#define NIC0_QPC1_GW_DATA_20 0x543F0DC
+
+#define NIC0_QPC1_GW_DATA_21 0x543F0E0
+
+#define NIC0_QPC1_GW_DATA_22 0x543F0E4
+
+#define NIC0_QPC1_GW_DATA_23 0x543F0E8
+
+#define NIC0_QPC1_GW_DATA_24 0x543F0EC
+
+#define NIC0_QPC1_GW_DATA_25 0x543F0F0
+
+#define NIC0_QPC1_GW_DATA_26 0x543F0F4
+
+#define NIC0_QPC1_GW_DATA_27 0x543F0F8
+
+#define NIC0_QPC1_GW_DATA_28 0x543F0FC
+
+#define NIC0_QPC1_GW_DATA_29 0x543F100
+
+#define NIC0_QPC1_GW_DATA_30 0x543F104
+
+#define NIC0_QPC1_GW_DATA_31 0x543F108
+
+#define NIC0_QPC1_GW_MASK_0 0x543F124
+
+#define NIC0_QPC1_GW_MASK_1 0x543F128
+
+#define NIC0_QPC1_GW_MASK_2 0x543F12C
+
+#define NIC0_QPC1_GW_MASK_3 0x543F130
+
+#define NIC0_QPC1_GW_MASK_4 0x543F134
+
+#define NIC0_QPC1_GW_MASK_5 0x543F138
+
+#define NIC0_QPC1_GW_MASK_6 0x543F13C
+
+#define NIC0_QPC1_GW_MASK_7 0x543F140
+
+#define NIC0_QPC1_GW_MASK_8 0x543F144
+
+#define NIC0_QPC1_GW_MASK_9 0x543F148
+
+#define NIC0_QPC1_GW_MASK_10 0x543F14C
+
+#define NIC0_QPC1_GW_MASK_11 0x543F150
+
+#define NIC0_QPC1_GW_MASK_12 0x543F154
+
+#define NIC0_QPC1_GW_MASK_13 0x543F158
+
+#define NIC0_QPC1_GW_MASK_14 0x543F15C
+
+#define NIC0_QPC1_GW_MASK_15 0x543F160
+
+#define NIC0_QPC1_GW_MASK_16 0x543F164
+
+#define NIC0_QPC1_GW_MASK_17 0x543F168
+
+#define NIC0_QPC1_GW_MASK_18 0x543F16C
+
+#define NIC0_QPC1_GW_MASK_19 0x543F170
+
+#define NIC0_QPC1_GW_MASK_20 0x543F174
+
+#define NIC0_QPC1_GW_MASK_21 0x543F178
+
+#define NIC0_QPC1_GW_MASK_22 0x543F17C
+
+#define NIC0_QPC1_GW_MASK_23 0x543F180
+
+#define NIC0_QPC1_GW_MASK_24 0x543F184
+
+#define NIC0_QPC1_GW_MASK_25 0x543F188
+
+#define NIC0_QPC1_GW_MASK_26 0x543F18C
+
+#define NIC0_QPC1_GW_MASK_27 0x543F190
+
+#define NIC0_QPC1_GW_MASK_28 0x543F194
+
+#define NIC0_QPC1_GW_MASK_29 0x543F198
+
+#define NIC0_QPC1_GW_MASK_30 0x543F19C
+
+#define NIC0_QPC1_GW_MASK_31 0x543F1A0
+
+#define NIC0_QPC1_CC_TIMEOUT 0x543F1B0
+
+#define NIC0_QPC1_CC_WINDOW_INC_EN 0x543F1FC
+
+#define NIC0_QPC1_CC_TICK_WRAP 0x543F200
+
+#define NIC0_QPC1_CC_ROLLBACK 0x543F204
+
+#define NIC0_QPC1_CC_MAX_WINDOW_SIZE 0x543F208
+
+#define NIC0_QPC1_CC_MIN_WINDOW_SIZE 0x543F20C
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_0 0x543F210
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_1 0x543F214
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_2 0x543F218
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_3 0x543F21C
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_4 0x543F220
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_5 0x543F224
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_6 0x543F228
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_7 0x543F22C
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_8 0x543F230
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_9 0x543F234
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_10 0x543F238
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_11 0x543F23C
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_12 0x543F240
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_13 0x543F244
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_14 0x543F248
+
+#define NIC0_QPC1_CC_ALPHA_LINEAR_15 0x543F24C
+
+#define NIC0_QPC1_CC_ALPHA_LOG_0 0x543F250
+
+#define NIC0_QPC1_CC_ALPHA_LOG_1 0x543F254
+
+#define NIC0_QPC1_CC_ALPHA_LOG_2 0x543F258
+
+#define NIC0_QPC1_CC_ALPHA_LOG_3 0x543F25C
+
+#define NIC0_QPC1_CC_ALPHA_LOG_4 0x543F260
+
+#define NIC0_QPC1_CC_ALPHA_LOG_5 0x543F264
+
+#define NIC0_QPC1_CC_ALPHA_LOG_6 0x543F268
+
+#define NIC0_QPC1_CC_ALPHA_LOG_7 0x543F26C
+
+#define NIC0_QPC1_CC_ALPHA_LOG_8 0x543F270
+
+#define NIC0_QPC1_CC_ALPHA_LOG_9 0x543F274
+
+#define NIC0_QPC1_CC_ALPHA_LOG_10 0x543F278
+
+#define NIC0_QPC1_CC_ALPHA_LOG_11 0x543F27C
+
+#define NIC0_QPC1_CC_ALPHA_LOG_12 0x543F280
+
+#define NIC0_QPC1_CC_ALPHA_LOG_13 0x543F284
+
+#define NIC0_QPC1_CC_ALPHA_LOG_14 0x543F288
+
+#define NIC0_QPC1_CC_ALPHA_LOG_15 0x543F28C
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_0 0x543F290
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_1 0x543F294
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_2 0x543F298
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_3 0x543F29C
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_4 0x543F2A0
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_5 0x543F2A4
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_6 0x543F2A8
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_7 0x543F2AC
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_8 0x543F2B0
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_9 0x543F2B4
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_10 0x543F2B8
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_11 0x543F2BC
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_12 0x543F2C0
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_13 0x543F2C4
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_14 0x543F2C8
+
+#define NIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_15 0x543F2CC
+
+#define NIC0_QPC1_CC_WINDOW_INC_0 0x543F2D0
+
+#define NIC0_QPC1_CC_WINDOW_INC_1 0x543F2D4
+
+#define NIC0_QPC1_CC_WINDOW_INC_2 0x543F2D8
+
+#define NIC0_QPC1_CC_WINDOW_INC_3 0x543F2DC
+
+#define NIC0_QPC1_CC_WINDOW_INC_4 0x543F2E0
+
+#define NIC0_QPC1_CC_WINDOW_INC_5 0x543F2E4
+
+#define NIC0_QPC1_CC_WINDOW_INC_6 0x543F2E8
+
+#define NIC0_QPC1_CC_WINDOW_INC_7 0x543F2EC
+
+#define NIC0_QPC1_CC_WINDOW_INC_8 0x543F2F0
+
+#define NIC0_QPC1_CC_WINDOW_INC_9 0x543F2F4
+
+#define NIC0_QPC1_CC_WINDOW_INC_10 0x543F2F8
+
+#define NIC0_QPC1_CC_WINDOW_INC_11 0x543F2FC
+
+#define NIC0_QPC1_CC_WINDOW_INC_12 0x543F300
+
+#define NIC0_QPC1_CC_WINDOW_INC_13 0x543F304
+
+#define NIC0_QPC1_CC_WINDOW_INC_14 0x543F308
+
+#define NIC0_QPC1_CC_WINDOW_INC_15 0x543F30C
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_0 0x543F310
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_1 0x543F314
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_2 0x543F318
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_3 0x543F31C
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_4 0x543F320
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_5 0x543F324
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_6 0x543F328
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_7 0x543F32C
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_8 0x543F330
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_9 0x543F334
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_10 0x543F338
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_11 0x543F33C
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_12 0x543F340
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_13 0x543F344
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_14 0x543F348
+
+#define NIC0_QPC1_CC_WINDOW_IN_THRESHOLD_15 0x543F34C
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_0 0x543F360
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_1 0x543F364
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_2 0x543F368
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_3 0x543F36C
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_4 0x543F370
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_5 0x543F374
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_6 0x543F378
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_7 0x543F37C
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_8 0x543F380
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_9 0x543F384
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_10 0x543F388
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_11 0x543F38C
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_12 0x543F390
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_13 0x543F394
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_14 0x543F398
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_15 0x543F39C
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_16 0x543F3A0
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_17 0x543F3A4
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_18 0x543F3A8
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_19 0x543F3AC
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_20 0x543F3B0
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_21 0x543F3B4
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_22 0x543F3B8
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_23 0x543F3BC
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_24 0x543F3C0
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_25 0x543F3C4
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_26 0x543F3C8
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_27 0x543F3CC
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_28 0x543F3D0
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_29 0x543F3D4
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_30 0x543F3D8
+
+#define NIC0_QPC1_DB_FIFO_USER_OVRD_31 0x543F3DC
+
+#define NIC0_QPC1_DB_FIFO_CFG_0 0x543F3E0
+
+#define NIC0_QPC1_DB_FIFO_CFG_1 0x543F3E4
+
+#define NIC0_QPC1_DB_FIFO_CFG_2 0x543F3E8
+
+#define NIC0_QPC1_DB_FIFO_CFG_3 0x543F3EC
+
+#define NIC0_QPC1_DB_FIFO_CFG_4 0x543F3F0
+
+#define NIC0_QPC1_DB_FIFO_CFG_5 0x543F3F4
+
+#define NIC0_QPC1_DB_FIFO_CFG_6 0x543F3F8
+
+#define NIC0_QPC1_DB_FIFO_CFG_7 0x543F3FC
+
+#define NIC0_QPC1_DB_FIFO_CFG_8 0x543F400
+
+#define NIC0_QPC1_DB_FIFO_CFG_9 0x543F404
+
+#define NIC0_QPC1_DB_FIFO_CFG_10 0x543F408
+
+#define NIC0_QPC1_DB_FIFO_CFG_11 0x543F40C
+
+#define NIC0_QPC1_DB_FIFO_CFG_12 0x543F410
+
+#define NIC0_QPC1_DB_FIFO_CFG_13 0x543F414
+
+#define NIC0_QPC1_DB_FIFO_CFG_14 0x543F418
+
+#define NIC0_QPC1_DB_FIFO_CFG_15 0x543F41C
+
+#define NIC0_QPC1_DB_FIFO_CFG_16 0x543F420
+
+#define NIC0_QPC1_DB_FIFO_CFG_17 0x543F424
+
+#define NIC0_QPC1_DB_FIFO_CFG_18 0x543F428
+
+#define NIC0_QPC1_DB_FIFO_CFG_19 0x543F42C
+
+#define NIC0_QPC1_DB_FIFO_CFG_20 0x543F430
+
+#define NIC0_QPC1_DB_FIFO_CFG_21 0x543F434
+
+#define NIC0_QPC1_DB_FIFO_CFG_22 0x543F438
+
+#define NIC0_QPC1_DB_FIFO_CFG_23 0x543F43C
+
+#define NIC0_QPC1_DB_FIFO_CFG_24 0x543F440
+
+#define NIC0_QPC1_DB_FIFO_CFG_25 0x543F444
+
+#define NIC0_QPC1_DB_FIFO_CFG_26 0x543F448
+
+#define NIC0_QPC1_DB_FIFO_CFG_27 0x543F44C
+
+#define NIC0_QPC1_DB_FIFO_CFG_28 0x543F450
+
+#define NIC0_QPC1_DB_FIFO_CFG_29 0x543F454
+
+#define NIC0_QPC1_DB_FIFO_CFG_30 0x543F458
+
+#define NIC0_QPC1_DB_FIFO_CFG_31 0x543F45C
+
+#define NIC0_QPC1_SECURED_DB_FIRST32 0x543F460
+
+#define NIC0_QPC1_SECURED_DB_SECOND32 0x543F464
+
+#define NIC0_QPC1_SECURED_DB_THIRD32 0x543F468
+
+#define NIC0_QPC1_SECURED_DB_FOURTH32 0x543F46C
+
+#define NIC0_QPC1_PRIVILEGE_DB_FIRST32 0x543F470
+
+#define NIC0_QPC1_PRIVILEGE_DB_SECOND32 0x543F474
+
+#define NIC0_QPC1_PRIVILEGE_DB_THIRD32 0x543F478
+
+#define NIC0_QPC1_PRIVILEGE_DB_FOURTH32 0x543F47C
+
+#define NIC0_QPC1_DBG_INDICATION 0x543F480
+
+#define NIC0_QPC1_WTD_WC_FSM 0x543F484
+
+#define NIC0_QPC1_WTD_SLICE_FSM 0x543F488
+
+#define NIC0_QPC1_REQ_TX_EMPTY_CNT 0x543F48C
+
+#define NIC0_QPC1_RES_TX_EMPTY_CNT 0x543F490
+
+#define NIC0_QPC1_NUM_ROLLBACKS 0x543F494
+
+#define NIC0_QPC1_LAST_QP_ROLLED_BACK 0x543F498
+
+#define NIC0_QPC1_NUM_TIMEOUTS 0x543F49C
+
+#define NIC0_QPC1_LAST_QP_TIMED_OUT 0x543F4A0
+
+#define NIC0_QPC1_WTD_SLICE_FSM_HI 0x543F4A4
+
+#define NIC0_QPC1_INTERRUPT_BASE_0 0x543F4B0
+
+#define NIC0_QPC1_INTERRUPT_BASE_1 0x543F4B4
+
+#define NIC0_QPC1_INTERRUPT_BASE_2 0x543F4B8
+
+#define NIC0_QPC1_INTERRUPT_BASE_3 0x543F4BC
+
+#define NIC0_QPC1_INTERRUPT_BASE_4 0x543F4C0
+
+#define NIC0_QPC1_INTERRUPT_BASE_5 0x543F4C4
+
+#define NIC0_QPC1_INTERRUPT_BASE_6 0x543F4C8
+
+#define NIC0_QPC1_INTERRUPT_BASE_7 0x543F4CC
+
+#define NIC0_QPC1_INTERRUPT_BASE_8 0x543F4D0
+
+#define NIC0_QPC1_INTERRUPT_BASE_9 0x543F4D4
+
+#define NIC0_QPC1_INTERRUPT_BASE_10 0x543F4D8
+
+#define NIC0_QPC1_INTERRUPT_DATA_0 0x543F4DC
+
+#define NIC0_QPC1_INTERRUPT_DATA_1 0x543F4E0
+
+#define NIC0_QPC1_INTERRUPT_DATA_2 0x543F4E4
+
+#define NIC0_QPC1_INTERRUPT_DATA_3 0x543F4E8
+
+#define NIC0_QPC1_INTERRUPT_DATA_4 0x543F4EC
+
+#define NIC0_QPC1_INTERRUPT_DATA_5 0x543F4F0
+
+#define NIC0_QPC1_INTERRUPT_DATA_6 0x543F4F4
+
+#define NIC0_QPC1_INTERRUPT_DATA_7 0x543F4F8
+
+#define NIC0_QPC1_INTERRUPT_DATA_8 0x543F4FC
+
+#define NIC0_QPC1_INTERRUPT_DATA_9 0x543F500
+
+#define NIC0_QPC1_INTERRUPT_DATA_10 0x543F504
+
+#define NIC0_QPC1_DBG_COUNT_SELECT_0 0x543F600
+
+#define NIC0_QPC1_DBG_COUNT_SELECT_1 0x543F604
+
+#define NIC0_QPC1_DBG_COUNT_SELECT_2 0x543F608
+
+#define NIC0_QPC1_DBG_COUNT_SELECT_3 0x543F60C
+
+#define NIC0_QPC1_DBG_COUNT_SELECT_4 0x543F610
+
+#define NIC0_QPC1_DBG_COUNT_SELECT_5 0x543F614
+
+#define NIC0_QPC1_DBG_COUNT_SELECT_6 0x543F618
+
+#define NIC0_QPC1_DBG_COUNT_SELECT_7 0x543F61C
+
+#define NIC0_QPC1_DBG_COUNT_SELECT_8 0x543F620
+
+#define NIC0_QPC1_DBG_COUNT_SELECT_9 0x543F624
+
+#define NIC0_QPC1_DBG_COUNT_SELECT_10 0x543F628
+
+#define NIC0_QPC1_DBG_COUNT_SELECT_11 0x543F62C
+
+#define NIC0_QPC1_DOORBELL_SECURITY 0x543F648
+
+#define NIC0_QPC1_DBG_CFG 0x543F64C
+
+#define NIC0_QPC1_RES_RING0_PI 0x543F650
+
+#define NIC0_QPC1_RES_RING0_CI 0x543F654
+
+#define NIC0_QPC1_RES_RING0_CFG 0x543F658
+
+#define NIC0_QPC1_RES_RING1_PI 0x543F65C
+
+#define NIC0_QPC1_RES_RING1_CI 0x543F660
+
+#define NIC0_QPC1_RES_RING1_CFG 0x543F664
+
+#define NIC0_QPC1_RES_RING2_PI 0x543F668
+
+#define NIC0_QPC1_RES_RING2_CI 0x543F66C
+
+#define NIC0_QPC1_RES_RING2_CFG 0x543F670
+
+#define NIC0_QPC1_RES_RING3_PI 0x543F674
+
+#define NIC0_QPC1_RES_RING3_CI 0x543F678
+
+#define NIC0_QPC1_RES_RING3_CFG 0x543F67C
+
+#define NIC0_QPC1_REQ_RING0_CI 0x543F680
+
+#define NIC0_QPC1_REQ_RING1_CI 0x543F684
+
+#define NIC0_QPC1_REQ_RING2_CI 0x543F688
+
+#define NIC0_QPC1_REQ_RING3_CI 0x543F68C
+
+#define NIC0_QPC1_INTERRUPT_CAUSE 0x543F690
+
+#define NIC0_QPC1_INTERRUPT_MASK 0x543F694
+
+#define NIC0_QPC1_INTERRUPT_CLR 0x543F698
+
+#define NIC0_QPC1_INTERRUPT_EN 0x543F69C
+
+#define NIC0_QPC1_INTERRUPT_CFG 0x543F6F0
+
+#define NIC0_QPC1_INTERRUPT_RESP_ERR_CAUSE 0x543F6F4
+
+#define NIC0_QPC1_INTERRUPT_RESP_ERR_MASK 0x543F6F8
+
+#define NIC0_QPC1_INTERRUPR_RESP_ERR_CLR 0x543F700
+
+#define NIC0_QPC1_TMR_GW_VALID 0x543F704
+
+#define NIC0_QPC1_TMR_GW_DATA0 0x543F708
+
+#define NIC0_QPC1_TMR_GW_DATA1 0x543F70C
+
+#define NIC0_QPC1_RNR_RETRY_COUNT_EN 0x543F710
+
+#define NIC0_QPC1_EVENT_QUE_BASE_ADDR_63_32 0x543F830
+
+#define NIC0_QPC1_EVENT_QUE_BASE_ADDR_31_7 0x543F834
+
+#define NIC0_QPC1_EVENT_QUE_LOG_SIZE 0x543F838
+
+#define NIC0_QPC1_EVENT_QUE_WRITE_INDEX 0x543F83C
+
+#define NIC0_QPC1_EVENT_QUE_PRODUCER_INDEX 0x543F840
+
+#define NIC0_QPC1_EVENT_QUE_PI_ADDR_63_32 0x543F844
+
+#define NIC0_QPC1_EVENT_QUE_PI_ADDR_31_7 0x543F848
+
+#define NIC0_QPC1_EVENT_QUE_CONSUMER_INDEX_CB 0x543F84C
+
+#define NIC0_QPC1_EVENT_QUE_CFG 0x543F850
+
+#define NIC0_QPC1_LBW_PROT 0x543F858
+
+#define NIC0_QPC1_MEM_WRITE_INIT 0x543F85C
+
+#define NIC0_QPC1_QMAN_DOORBELL 0x543F8E8
+
+#define NIC0_QPC1_QMAN_DOORBELL_QPN 0x543F8EC
+
+#define NIC0_QPC1_SECURED_CQ_NUMBER 0x543F8F0
+
+#define NIC0_QPC1_SECURED_CQ_CONSUMER_INDEX 0x543F8F4
+
+#define NIC0_QPC1_PRIVILEGE_CQ_NUMBER 0x543F8F8
+
+#define NIC0_QPC1_PRIVILEGE_CQ_CONSUMER_INDEX 0x543F8FC
+
+#define NIC0_QPC1_TX_WQ_BASE_ADDR_63_32_0 0x543F900
+
+#define NIC0_QPC1_TX_WQ_BASE_ADDR_63_32_1 0x543F904
+
+#define NIC0_QPC1_TX_WQ_BASE_ADDR_63_32_2 0x543F908
+
+#define NIC0_QPC1_TX_WQ_BASE_ADDR_63_32_3 0x543F90C
+
+#define NIC0_QPC1_TX_WQ_BASE_ADDR_31_0_0 0x543F910
+
+#define NIC0_QPC1_TX_WQ_BASE_ADDR_31_0_1 0x543F914
+
+#define NIC0_QPC1_TX_WQ_BASE_ADDR_31_0_2 0x543F918
+
+#define NIC0_QPC1_TX_WQ_BASE_ADDR_31_0_3 0x543F91C
+
+#define NIC0_QPC1_LOG_MAX_TX_WQ_SIZE_0 0x543F920
+
+#define NIC0_QPC1_LOG_MAX_TX_WQ_SIZE_1 0x543F924
+
+#define NIC0_QPC1_LOG_MAX_TX_WQ_SIZE_2 0x543F928
+
+#define NIC0_QPC1_LOG_MAX_TX_WQ_SIZE_3 0x543F92C
+
+#define NIC0_QPC1_MMU_BYPASS_TX_WQ_0 0x543F930
+
+#define NIC0_QPC1_MMU_BYPASS_TX_WQ_1 0x543F934
+
+#define NIC0_QPC1_MMU_BYPASS_TX_WQ_2 0x543F938
+
+#define NIC0_QPC1_MMU_BYPASS_TX_WQ_3 0x543F93C
+
+#define NIC0_QPC1_RX_WQ_BASE_ADDR_63_32_0 0x543F940
+
+#define NIC0_QPC1_RX_WQ_BASE_ADDR_63_32_1 0x543F944
+
+#define NIC0_QPC1_RX_WQ_BASE_ADDR_63_32_2 0x543F948
+
+#define NIC0_QPC1_RX_WQ_BASE_ADDR_63_32_3 0x543F94C
+
+#define NIC0_QPC1_RX_WQ_BASE_ADDR_31_0_0 0x543F950
+
+#define NIC0_QPC1_RX_WQ_BASE_ADDR_31_0_1 0x543F954
+
+#define NIC0_QPC1_RX_WQ_BASE_ADDR_31_0_2 0x543F958
+
+#define NIC0_QPC1_RX_WQ_BASE_ADDR_31_0_3 0x543F95C
+
+#define NIC0_QPC1_LOG_MAX_RX_WQ_SIZE_0 0x543F960
+
+#define NIC0_QPC1_LOG_MAX_RX_WQ_SIZE_1 0x543F964
+
+#define NIC0_QPC1_LOG_MAX_RX_WQ_SIZE_2 0x543F968
+
+#define NIC0_QPC1_LOG_MAX_RX_WQ_SIZE_3 0x543F96C
+
+#define NIC0_QPC1_MMU_BYPASS_RX_WQ_0 0x543F970
+
+#define NIC0_QPC1_MMU_BYPASS_RX_WQ_1 0x543F974
+
+#define NIC0_QPC1_MMU_BYPASS_RX_WQ_2 0x543F978
+
+#define NIC0_QPC1_MMU_BYPASS_RX_WQ_3 0x543F97C
+
+#define NIC0_QPC1_WQE_MEM_WRITE_AXI_PROT 0x543F980
+
+#define NIC0_QPC1_WQ_UPPER_THRESHOLD 0x543F984
+
+#define NIC0_QPC1_WQ_LOWER_THRESHOLD 0x543F988
+
+#define NIC0_QPC1_WQ_BP_2ARC_ADDR 0x543F98C
+
+#define NIC0_QPC1_WQ_BP_2QMAN_ADDR 0x543F990
+
+#define NIC0_QPC1_WTD_CONFIG 0x543F994
+
+#define NIC0_QPC1_REQTX_ERR_FIFO_PUSH_63_32 0x543F998
+
+#define NIC0_QPC1_REQTX_ERR_FIFO_PUSH_31_0 0x543F99C
+
+#define NIC0_QPC1_REQTX_ERR_QP_STATE_63_32 0x543F9A0
+
+#define NIC0_QPC1_REQTX_ERR_QP_STATE_31_0 0x543F9A4
+
+#define NIC0_QPC1_EVENT_QUE_CONSUMER_INDEX 0x543F9A8
+
+#define NIC0_QPC1_ARM_CQ_NUM 0x543F9AC
+
+#define NIC0_QPC1_ARM_CQ_INDEX 0x543F9B0
+
+#define NIC0_QPC1_QPC_CLOCK_GATE 0x543F9B4
+
+#define NIC0_QPC1_QPC_CLOCK_GATE_DIS 0x543F9B8
+
+#define NIC0_QPC1_CONG_QUE_BASE_ADDR_63_32 0x543F9BC
+
+#define NIC0_QPC1_CONG_QUE_BASE_ADDR_31_7 0x543F9C0
+
+#define NIC0_QPC1_CONG_QUE_LOG_SIZE 0x543F9C4
+
+#define NIC0_QPC1_CONG_QUE_WRITE_INDEX 0x543F9C8
+
+#define NIC0_QPC1_CONG_QUE_PRODUCER_INDEX 0x543F9CC
+
+#define NIC0_QPC1_CONG_QUE_PI_ADDR_63_32 0x543F9D0
+
+#define NIC0_QPC1_CONG_QUE_PI_ADDR_31_7 0x543F9D4
+
+#define NIC0_QPC1_CONG_QUE_CONSUMER_INDEX_CB 0x543F9D8
+
+#define NIC0_QPC1_CONG_QUE_CFG 0x543F9DC
+
+#define NIC0_QPC1_CONG_QUE_CONSUMER_INDEX 0x543F9E0
+
+#define NIC0_QPC1_LINEAR_WQE_STATIC_0 0x543FA00
+
+#define NIC0_QPC1_LINEAR_WQE_STATIC_1 0x543FA04
+
+#define NIC0_QPC1_LINEAR_WQE_STATIC_2 0x543FA08
+
+#define NIC0_QPC1_LINEAR_WQE_STATIC_3 0x543FA0C
+
+#define NIC0_QPC1_LINEAR_WQE_STATIC_4 0x543FA10
+
+#define NIC0_QPC1_LINEAR_WQE_STATIC_5 0x543FA14
+
+#define NIC0_QPC1_LINEAR_WQE_STATIC_6 0x543FA18
+
+#define NIC0_QPC1_LINEAR_WQE_STATIC_7 0x543FA1C
+
+#define NIC0_QPC1_LINEAR_WQE_STATIC_8 0x543FA20
+
+#define NIC0_QPC1_LINEAR_WQE_STATIC_9 0x543FA24
+
+#define NIC0_QPC1_LINEAR_WQE_DYNAMIC_0 0x543FA40
+
+#define NIC0_QPC1_LINEAR_WQE_DYNAMIC_1 0x543FA44
+
+#define NIC0_QPC1_LINEAR_WQE_DYNAMIC_2 0x543FA48
+
+#define NIC0_QPC1_LINEAR_WQE_DYNAMIC_3 0x543FA4C
+
+#define NIC0_QPC1_LINEAR_WQE_DYNAMIC_4 0x543FA50
+
+#define NIC0_QPC1_LINEAR_WQE_DYNAMIC_5 0x543FA54
+
+#define NIC0_QPC1_LINEAR_WQE_QPN 0x543FA58
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_0 0x543FA80
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_1 0x543FA84
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_2 0x543FA88
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_3 0x543FA8C
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_4 0x543FA90
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_5 0x543FA94
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_6 0x543FA98
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_7 0x543FA9C
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_8 0x543FAA0
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_9 0x543FAA4
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_10 0x543FAA8
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_11 0x543FAAC
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_12 0x543FAB0
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_13 0x543FAB4
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_14 0x543FAB8
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_15 0x543FABC
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_16 0x543FAC0
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_STATIC_17 0x543FAC4
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_DYNAMIC_0 0x543FAE0
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_DYNAMIC_1 0x543FAE4
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_DYNAMIC_2 0x543FAE8
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_DYNAMIC_3 0x543FAEC
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_DYNAMIC_4 0x543FAF0
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_DYNAMIC_5 0x543FAF4
+
+#define NIC0_QPC1_MULTI_STRIDE_WQE_QPN 0x543FAF8
+
+#endif /* ASIC_REG_NIC0_QPC1_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxb_core_masks.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxb_core_masks.h
new file mode 100644
index 000000000000..25f3307330a5
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxb_core_masks.h
@@ -0,0 +1,459 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_RXB_CORE_MASKS_H_
+#define ASIC_REG_NIC0_RXB_CORE_MASKS_H_
+
+/*****************************************
+ * NIC0_RXB_CORE
+ * (Prototype: NIC_RXB_CORE)
+ *****************************************
+ */
+
+/* NIC0_RXB_CORE_RXB_CFG */
+#define NIC0_RXB_CORE_RXB_CFG_TAP_EN_SHIFT 0
+#define NIC0_RXB_CORE_RXB_CFG_TAP_EN_MASK 0x1
+
+/* NIC0_RXB_CORE_CG */
+#define NIC0_RXB_CORE_CG_DISABLE_SHIFT 0
+#define NIC0_RXB_CORE_CG_DISABLE_MASK 0x1
+#define NIC0_RXB_CORE_CG_GATED_CLK_ACTIVE_SHIFT 1
+#define NIC0_RXB_CORE_CG_GATED_CLK_ACTIVE_MASK 0x2
+
+/* NIC0_RXB_CORE_CG_TIMER */
+#define NIC0_RXB_CORE_CG_TIMER_VAL_SHIFT 0
+#define NIC0_RXB_CORE_CG_TIMER_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_SCT_RL */
+#define NIC0_RXB_CORE_SCT_RL_ENABLE_SHIFT 0
+#define NIC0_RXB_CORE_SCT_RL_ENABLE_MASK 0x1
+#define NIC0_RXB_CORE_SCT_RL_SATURATION_SHIFT 8
+#define NIC0_RXB_CORE_SCT_RL_SATURATION_MASK 0xFF00
+#define NIC0_RXB_CORE_SCT_RL_RST_TOKEN_SHIFT 16
+#define NIC0_RXB_CORE_SCT_RL_RST_TOKEN_MASK 0xFF0000
+#define NIC0_RXB_CORE_SCT_RL_TIMEOUT_SHIFT 24
+#define NIC0_RXB_CORE_SCT_RL_TIMEOUT_MASK 0xFF000000
+
+/* NIC0_RXB_CORE_APB_BASE_ADDR_TMR */
+#define NIC0_RXB_CORE_APB_BASE_ADDR_TMR_VAL_SHIFT 0
+#define NIC0_RXB_CORE_APB_BASE_ADDR_TMR_VAL_MASK 0x7FFFF
+
+/* NIC0_RXB_CORE_APB_BASE_ADDR_RXB */
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXB_VAL_SHIFT 0
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXB_VAL_MASK 0x7FFFF
+
+/* NIC0_RXB_CORE_APB_BASE_ADDR_RXE0 */
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXE0_VAL_SHIFT 0
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXE0_VAL_MASK 0x7FFFF
+
+/* NIC0_RXB_CORE_APB_BASE_ADDR_RXE1 */
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXE1_VAL_SHIFT 0
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXE1_VAL_MASK 0x7FFFF
+
+/* NIC0_RXB_CORE_APB_BASE_ADDR_RXE0_AXUSER */
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXE0_AXUSER_VAL_SHIFT 0
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXE0_AXUSER_VAL_MASK 0x7FFFF
+
+/* NIC0_RXB_CORE_APB_BASE_ADDR_RXE1_AXUSER */
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXE1_AXUSER_VAL_SHIFT 0
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXE1_AXUSER_VAL_MASK 0x7FFFF
+
+/* NIC0_RXB_CORE_APB_BASE_ADDR_RX_RSVD */
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RX_RSVD_VAL_SHIFT 0
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RX_RSVD_VAL_MASK 0x7FFFF
+
+/* NIC0_RXB_CORE_HL_ROCE_CONFIG */
+#define NIC0_RXB_CORE_HL_ROCE_CONFIG_PORT0_IS_HL_SHIFT 0
+#define NIC0_RXB_CORE_HL_ROCE_CONFIG_PORT0_IS_HL_MASK 0x1
+#define NIC0_RXB_CORE_HL_ROCE_CONFIG_PORT1_IS_HL_SHIFT 1
+#define NIC0_RXB_CORE_HL_ROCE_CONFIG_PORT1_IS_HL_MASK 0x2
+#define NIC0_RXB_CORE_HL_ROCE_CONFIG_PORT2_IS_HL_SHIFT 2
+#define NIC0_RXB_CORE_HL_ROCE_CONFIG_PORT2_IS_HL_MASK 0x4
+#define NIC0_RXB_CORE_HL_ROCE_CONFIG_PORT3_IS_HL_SHIFT 3
+#define NIC0_RXB_CORE_HL_ROCE_CONFIG_PORT3_IS_HL_MASK 0x8
+#define NIC0_RXB_CORE_HL_ROCE_CONFIG_HL_ETHERTYPE_SHIFT 4
+#define NIC0_RXB_CORE_HL_ROCE_CONFIG_HL_ETHERTYPE_MASK 0xFFFF0
+
+/* NIC0_RXB_CORE_DYNAMIC_CREDITS */
+#define NIC0_RXB_CORE_DYNAMIC_CREDITS_DYNAMIC_VALUE_SHIFT 0
+#define NIC0_RXB_CORE_DYNAMIC_CREDITS_DYNAMIC_VALUE_MASK 0x1FFF
+#define NIC0_RXB_CORE_DYNAMIC_CREDITS_DYNAMIC_VALUE_SET_SHIFT 13
+#define NIC0_RXB_CORE_DYNAMIC_CREDITS_DYNAMIC_VALUE_SET_MASK 0x2000
+
+/* NIC0_RXB_CORE_MAX_DYNAMIC */
+#define NIC0_RXB_CORE_MAX_DYNAMIC_DYNAMIC_MAX_SHIFT 0
+#define NIC0_RXB_CORE_MAX_DYNAMIC_DYNAMIC_MAX_MASK 0x1FFF
+
+/* NIC0_RXB_CORE_STATIC_CREDITS */
+#define NIC0_RXB_CORE_STATIC_CREDITS_STATIC_CREDITS_VALUE0_SHIFT 0
+#define NIC0_RXB_CORE_STATIC_CREDITS_STATIC_CREDITS_VALUE0_MASK 0x1FFF
+#define NIC0_RXB_CORE_STATIC_CREDITS_STATIC_CREDITS_VALUE0_SET_SHIFT 13
+#define NIC0_RXB_CORE_STATIC_CREDITS_STATIC_CREDITS_VALUE0_SET_MASK 0x2000
+#define NIC0_RXB_CORE_STATIC_CREDITS_STATIC_CREDITS_VALUE1_SHIFT 14
+#define NIC0_RXB_CORE_STATIC_CREDITS_STATIC_CREDITS_VALUE1_MASK 0x7FFC000
+#define NIC0_RXB_CORE_STATIC_CREDITS_STATIC_CREDITS_VALUE1_SET_SHIFT 27
+#define NIC0_RXB_CORE_STATIC_CREDITS_STATIC_CREDITS_VALUE1_SET_MASK 0x8000000
+
+/* NIC0_RXB_CORE_MAX_STATIC_CREDITS */
+#define NIC0_RXB_CORE_MAX_STATIC_CREDITS_MAX_STATIC_CREDITS0_SHIFT 0
+#define NIC0_RXB_CORE_MAX_STATIC_CREDITS_MAX_STATIC_CREDITS0_MASK 0x1FFF
+#define NIC0_RXB_CORE_MAX_STATIC_CREDITS_MAX_STATIC_CREDITS1_SHIFT 13
+#define NIC0_RXB_CORE_MAX_STATIC_CREDITS_MAX_STATIC_CREDITS1_MASK 0x3FFE000
+
+/* NIC0_RXB_CORE_XOFF_THRESHOLD */
+#define NIC0_RXB_CORE_XOFF_THRESHOLD_XOFF_THRESHOLD_FLOW0_SHIFT 0
+#define NIC0_RXB_CORE_XOFF_THRESHOLD_XOFF_THRESHOLD_FLOW0_MASK 0x1FFF
+#define NIC0_RXB_CORE_XOFF_THRESHOLD_XOFF_THRESHOLD_FLOW1_SHIFT 13
+#define NIC0_RXB_CORE_XOFF_THRESHOLD_XOFF_THRESHOLD_FLOW1_MASK 0x3FFE000
+
+/* NIC0_RXB_CORE_XON_THRESHOLD */
+#define NIC0_RXB_CORE_XON_THRESHOLD_XON_THRESHOLD_FLOW0_SHIFT 0
+#define NIC0_RXB_CORE_XON_THRESHOLD_XON_THRESHOLD_FLOW0_MASK 0x1FFF
+#define NIC0_RXB_CORE_XON_THRESHOLD_XON_THRESHOLD_FLOW1_SHIFT 13
+#define NIC0_RXB_CORE_XON_THRESHOLD_XON_THRESHOLD_FLOW1_MASK 0x3FFE000
+
+/* NIC0_RXB_CORE_DROP_THRESHOLD */
+#define NIC0_RXB_CORE_DROP_THRESHOLD_DROP_THRESHOLD_FLOW0_SHIFT 0
+#define NIC0_RXB_CORE_DROP_THRESHOLD_DROP_THRESHOLD_FLOW0_MASK 0x1FFF
+#define NIC0_RXB_CORE_DROP_THRESHOLD_DROP_THRESHOLD_FLOW1_SHIFT 13
+#define NIC0_RXB_CORE_DROP_THRESHOLD_DROP_THRESHOLD_FLOW1_MASK 0x3FFE000
+
+/* NIC0_RXB_CORE_DROP_SMALL_THRESHOLD */
+#define NIC0_RXB_CORE_DROP_SMALL_THRESHOLD_DROP_THRESHOLD_FLOW0_SHIFT 0
+#define NIC0_RXB_CORE_DROP_SMALL_THRESHOLD_DROP_THRESHOLD_FLOW0_MASK 0x1FFF
+#define NIC0_RXB_CORE_DROP_SMALL_THRESHOLD_DROP_THRESHOLD_FLOW1_SHIFT 13
+#define NIC0_RXB_CORE_DROP_SMALL_THRESHOLD_DROP_THRESHOLD_FLOW1_MASK 0x3FFE000
+
+/* NIC0_RXB_CORE_DYNAMIC_CREDITS_STAT */
+#define NIC0_RXB_CORE_DYNAMIC_CREDITS_STAT_LEVEL_SHIFT 0
+#define NIC0_RXB_CORE_DYNAMIC_CREDITS_STAT_LEVEL_MASK 0x1FFF
+
+/* NIC0_RXB_CORE_STATIC_CREDITS_STAT */
+#define NIC0_RXB_CORE_STATIC_CREDITS_STAT_LEVEL0_SHIFT 0
+#define NIC0_RXB_CORE_STATIC_CREDITS_STAT_LEVEL0_MASK 0x1FFF
+#define NIC0_RXB_CORE_STATIC_CREDITS_STAT_LEVEL1_SHIFT 13
+#define NIC0_RXB_CORE_STATIC_CREDITS_STAT_LEVEL1_MASK 0x3FFE000
+
+/* NIC0_RXB_CORE_MAC_PFC_MODE */
+#define NIC0_RXB_CORE_MAC_PFC_MODE_VAL_SHIFT 1
+#define NIC0_RXB_CORE_MAC_PFC_MODE_VAL_MASK 0x2
+
+/* NIC0_RXB_CORE_PORT_TRUST_LEVEL */
+#define NIC0_RXB_CORE_PORT_TRUST_LEVEL_PORT0_TRUST_LEVEL_SHIFT 0
+#define NIC0_RXB_CORE_PORT_TRUST_LEVEL_PORT0_TRUST_LEVEL_MASK 0x3
+#define NIC0_RXB_CORE_PORT_TRUST_LEVEL_PORT1_TRUST_LEVEL_SHIFT 2
+#define NIC0_RXB_CORE_PORT_TRUST_LEVEL_PORT1_TRUST_LEVEL_MASK 0xC
+#define NIC0_RXB_CORE_PORT_TRUST_LEVEL_PORT2_TRUST_LEVEL_SHIFT 4
+#define NIC0_RXB_CORE_PORT_TRUST_LEVEL_PORT2_TRUST_LEVEL_MASK 0x30
+#define NIC0_RXB_CORE_PORT_TRUST_LEVEL_PORT3_TRUST_LEVEL_SHIFT 6
+#define NIC0_RXB_CORE_PORT_TRUST_LEVEL_PORT3_TRUST_LEVEL_MASK 0xC0
+
+/* NIC0_RXB_CORE_PORT_DEFAULT_PRIO */
+#define NIC0_RXB_CORE_PORT_DEFAULT_PRIO_PORT0_DEFAULT_PRIO_SHIFT 0
+#define NIC0_RXB_CORE_PORT_DEFAULT_PRIO_PORT0_DEFAULT_PRIO_MASK 0x7
+#define NIC0_RXB_CORE_PORT_DEFAULT_PRIO_PORT1_DEFAULT_PRIO_SHIFT 3
+#define NIC0_RXB_CORE_PORT_DEFAULT_PRIO_PORT1_DEFAULT_PRIO_MASK 0x38
+#define NIC0_RXB_CORE_PORT_DEFAULT_PRIO_PORT2_DEFAULT_PRIO_SHIFT 6
+#define NIC0_RXB_CORE_PORT_DEFAULT_PRIO_PORT2_DEFAULT_PRIO_MASK 0x1C0
+#define NIC0_RXB_CORE_PORT_DEFAULT_PRIO_PORT3_DEFAULT_PRIO_SHIFT 9
+#define NIC0_RXB_CORE_PORT_DEFAULT_PRIO_PORT3_DEFAULT_PRIO_MASK 0xE00
+
+/* NIC0_RXB_CORE_DSCP2PRIO */
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO0_SHIFT 0
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO0_MASK 0x7
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO1_SHIFT 4
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO1_MASK 0x70
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO2_SHIFT 8
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO2_MASK 0x700
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO3_SHIFT 12
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO3_MASK 0x7000
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO4_SHIFT 16
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO4_MASK 0x70000
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO5_SHIFT 20
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO5_MASK 0x700000
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO6_SHIFT 24
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO6_MASK 0x7000000
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO7_SHIFT 28
+#define NIC0_RXB_CORE_DSCP2PRIO_DSCP2PRIO7_MASK 0x70000000
+
+/* NIC0_RXB_CORE_ICRC_CFG */
+#define NIC0_RXB_CORE_ICRC_CFG_ICRC_DISABLE_SHIFT 0
+#define NIC0_RXB_CORE_ICRC_CFG_ICRC_DISABLE_MASK 0x1
+#define NIC0_RXB_CORE_ICRC_CFG_ICRC_REV_BYTES_SHIFT 1
+#define NIC0_RXB_CORE_ICRC_CFG_ICRC_REV_BYTES_MASK 0x2
+
+/* NIC0_RXB_CORE_AXI_AWPROT_HBW */
+#define NIC0_RXB_CORE_AXI_AWPROT_HBW_UNSECURED_SHIFT 0
+#define NIC0_RXB_CORE_AXI_AWPROT_HBW_UNSECURED_MASK 0x7
+#define NIC0_RXB_CORE_AXI_AWPROT_HBW_SECURED_SHIFT 3
+#define NIC0_RXB_CORE_AXI_AWPROT_HBW_SECURED_MASK 0x38
+#define NIC0_RXB_CORE_AXI_AWPROT_HBW_PRIVILEGED_SHIFT 6
+#define NIC0_RXB_CORE_AXI_AWPROT_HBW_PRIVILEGED_MASK 0x1C0
+
+/* NIC0_RXB_CORE_AXI_AWPROT_LBW */
+#define NIC0_RXB_CORE_AXI_AWPROT_LBW_UNSECURED_SHIFT 0
+#define NIC0_RXB_CORE_AXI_AWPROT_LBW_UNSECURED_MASK 0x7
+#define NIC0_RXB_CORE_AXI_AWPROT_LBW_SECURED_SHIFT 3
+#define NIC0_RXB_CORE_AXI_AWPROT_LBW_SECURED_MASK 0x38
+#define NIC0_RXB_CORE_AXI_AWPROT_LBW_PRIVILEGED_SHIFT 6
+#define NIC0_RXB_CORE_AXI_AWPROT_LBW_PRIVILEGED_MASK 0x1C0
+
+/* NIC0_RXB_CORE_VLAN_ETHERTYPES */
+#define NIC0_RXB_CORE_VLAN_ETHERTYPES_CVLAN_SHIFT 0
+#define NIC0_RXB_CORE_VLAN_ETHERTYPES_CVLAN_MASK 0xFFFF
+#define NIC0_RXB_CORE_VLAN_ETHERTYPES_SVLAN_SHIFT 16
+#define NIC0_RXB_CORE_VLAN_ETHERTYPES_SVLAN_MASK 0xFFFF0000
+
+/* NIC0_RXB_CORE_TS_RC_MAC_31_0 */
+#define NIC0_RXB_CORE_TS_RC_MAC_31_0_MAC_31_0_SHIFT 0
+#define NIC0_RXB_CORE_TS_RC_MAC_31_0_MAC_31_0_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_TS_RC_MAC_47_32 */
+#define NIC0_RXB_CORE_TS_RC_MAC_47_32_MAC_47_32_SHIFT 0
+#define NIC0_RXB_CORE_TS_RC_MAC_47_32_MAC_47_32_MASK 0xFFFF
+
+/* NIC0_RXB_CORE_TS_RAW0_MAC_31_0 */
+#define NIC0_RXB_CORE_TS_RAW0_MAC_31_0_MAC_31_0_SHIFT 0
+#define NIC0_RXB_CORE_TS_RAW0_MAC_31_0_MAC_31_0_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_TS_RAW0_MAC_47_32 */
+#define NIC0_RXB_CORE_TS_RAW0_MAC_47_32_MAC_47_32_SHIFT 0
+#define NIC0_RXB_CORE_TS_RAW0_MAC_47_32_MAC_47_32_MASK 0xFFFF
+
+/* NIC0_RXB_CORE_TS_RC_MAC_31_0_MASK */
+#define NIC0_RXB_CORE_TS_RC_MAC_31_0_MASK_MASK_SHIFT 0
+#define NIC0_RXB_CORE_TS_RC_MAC_31_0_MASK_MASK_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_TS_RC_MAC_47_32_MASK */
+#define NIC0_RXB_CORE_TS_RC_MAC_47_32_MASK_MASK_SHIFT 0
+#define NIC0_RXB_CORE_TS_RC_MAC_47_32_MASK_MASK_MASK 0xFFFF
+
+/* NIC0_RXB_CORE_TS_RAW0_MAC_31_0_MASK */
+#define NIC0_RXB_CORE_TS_RAW0_MAC_31_0_MASK_MASK_SHIFT 0
+#define NIC0_RXB_CORE_TS_RAW0_MAC_31_0_MASK_MASK_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_TS_RAW0_MAC_47_32_MASK */
+#define NIC0_RXB_CORE_TS_RAW0_MAC_47_32_MASK_MASK_SHIFT 0
+#define NIC0_RXB_CORE_TS_RAW0_MAC_47_32_MASK_MASK_MASK 0xFFFF
+
+/* NIC0_RXB_CORE_DBG_SPMU_SELECT */
+#define NIC0_RXB_CORE_DBG_SPMU_SELECT_PORT_SEL_SHIFT 0
+#define NIC0_RXB_CORE_DBG_SPMU_SELECT_PORT_SEL_MASK 0x3
+#define NIC0_RXB_CORE_DBG_SPMU_SELECT_PRIO_SEL_SHIFT 2
+#define NIC0_RXB_CORE_DBG_SPMU_SELECT_PRIO_SEL_MASK 0xC
+#define NIC0_RXB_CORE_DBG_SPMU_SELECT_SPMU_GROUP_SEL_SHIFT 4
+#define NIC0_RXB_CORE_DBG_SPMU_SELECT_SPMU_GROUP_SEL_MASK 0x10
+#define NIC0_RXB_CORE_DBG_SPMU_SELECT_DATA_EVNT_GROUP_SEL_SHIFT 5
+#define NIC0_RXB_CORE_DBG_SPMU_SELECT_DATA_EVNT_GROUP_SEL_MASK 0x60
+
+/* NIC0_RXB_CORE_DBG_ERROR */
+#define NIC0_RXB_CORE_DBG_ERROR_FORCE_NO_ERROR_SHIFT 0
+#define NIC0_RXB_CORE_DBG_ERROR_FORCE_NO_ERROR_MASK 0x1
+#define NIC0_RXB_CORE_DBG_ERROR_FORCE_ERROR_SHIFT 1
+#define NIC0_RXB_CORE_DBG_ERROR_FORCE_ERROR_MASK 0x2
+
+/* NIC0_RXB_CORE_DBG_ENDIANNESS */
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_DW_REV_EN_RAW_SHIFT 0
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_DW_REV_EN_RAW_MASK 0x1
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_DW_REV_EN_LIN_SHIFT 1
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_DW_REV_EN_LIN_MASK 0x2
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_DW_REV_EN_SIN_SHIFT 2
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_DW_REV_EN_SIN_MASK 0x4
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_DW_REV_EN_MUL_SHIFT 3
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_DW_REV_EN_MUL_MASK 0x8
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_BYTE_REV_EN_RAW_SHIFT 16
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_BYTE_REV_EN_RAW_MASK 0x10000
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_BYTE_REV_EN_LIN_SHIFT 17
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_BYTE_REV_EN_LIN_MASK 0x20000
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_BYTE_REV_EN_SIN_SHIFT 18
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_BYTE_REV_EN_SIN_MASK 0x40000
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_BYTE_REV_EN_MUL_SHIFT 19
+#define NIC0_RXB_CORE_DBG_ENDIANNESS_BYTE_REV_EN_MUL_MASK 0x80000
+
+/* NIC0_RXB_CORE_DBG_LAST_PARSING */
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_PARSING_32_SHIFT 0
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_PARSING_32_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_DBG_LAST_CTRL */
+#define NIC0_RXB_CORE_DBG_LAST_CTRL_CTRL_32_SHIFT 0
+#define NIC0_RXB_CORE_DBG_LAST_CTRL_CTRL_32_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_DBG_LAST_SCATTER */
+#define NIC0_RXB_CORE_DBG_LAST_SCATTER_SCATTER_32_SHIFT 0
+#define NIC0_RXB_CORE_DBG_LAST_SCATTER_SCATTER_32_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_DBG_LAST_DONE */
+#define NIC0_RXB_CORE_DBG_LAST_DONE_DONE_32_SHIFT 0
+#define NIC0_RXB_CORE_DBG_LAST_DONE_DONE_32_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_DBG_EN */
+#define NIC0_RXB_CORE_DBG_EN_VAL_SHIFT 0
+#define NIC0_RXB_CORE_DBG_EN_VAL_MASK 0x1
+
+/* NIC0_RXB_CORE_DBG_RXE_CRDT */
+#define NIC0_RXB_CORE_DBG_RXE_CRDT_RXE0_CRDT_SHIFT 0
+#define NIC0_RXB_CORE_DBG_RXE_CRDT_RXE0_CRDT_MASK 0x1F
+#define NIC0_RXB_CORE_DBG_RXE_CRDT_RXE1_CRDT_SHIFT 5
+#define NIC0_RXB_CORE_DBG_RXE_CRDT_RXE1_CRDT_MASK 0x3E0
+
+/* NIC0_RXB_CORE_DBG_BUF_LVL */
+#define NIC0_RXB_CORE_DBG_BUF_LVL_VAL_SHIFT 0
+#define NIC0_RXB_CORE_DBG_BUF_LVL_VAL_MASK 0xFFF
+
+/* NIC0_RXB_CORE_DBG_SCT */
+#define NIC0_RXB_CORE_DBG_SCT_WR_IDS_IN_USE_SHIFT 0
+#define NIC0_RXB_CORE_DBG_SCT_WR_IDS_IN_USE_MASK 0x1FF
+
+/* NIC0_RXB_CORE_TNL_DECAP_IPV4 */
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_VALID_SHIFT 0
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_VALID_MASK 0x1
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_IPV4_PROTOCOL_SHIFT 1
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_IPV4_PROTOCOL_MASK 0x1FE
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_TNL_SIZE_SHIFT 9
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_TNL_SIZE_MASK 0x1E00
+
+/* NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR */
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_VAL_SHIFT 0
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK */
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_VAL_SHIFT 0
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_TNL_DECAP_UDP */
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_VALID_SHIFT 0
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_VALID_MASK 0x1
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_UDP_DEST_PORT_SHIFT 1
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_UDP_DEST_PORT_MASK 0x1FFFE
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_TNL_SIZE_SHIFT 17
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_TNL_SIZE_MASK 0x1E0000
+
+/* NIC0_RXB_CORE_TNL_DECAP_UDP_HDR */
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_VAL_SHIFT 0
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_TNL_DECAP_UDP_MASK */
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_VAL_SHIFT 0
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_TNL_DECAP_CFG */
+#define NIC0_RXB_CORE_TNL_DECAP_CFG_IPV4_HDR_CHK_EN_SHIFT 0
+#define NIC0_RXB_CORE_TNL_DECAP_CFG_IPV4_HDR_CHK_EN_MASK 0x1
+#define NIC0_RXB_CORE_TNL_DECAP_CFG_UDP_HDR_CHK_EN_SHIFT 1
+#define NIC0_RXB_CORE_TNL_DECAP_CFG_UDP_HDR_CHK_EN_MASK 0x2
+#define NIC0_RXB_CORE_TNL_DECAP_CFG_IPV4_HDR_REV_EN_SHIFT 2
+#define NIC0_RXB_CORE_TNL_DECAP_CFG_IPV4_HDR_REV_EN_MASK 0x4
+#define NIC0_RXB_CORE_TNL_DECAP_CFG_UDP_HDR_REV_EN_SHIFT 3
+#define NIC0_RXB_CORE_TNL_DECAP_CFG_UDP_HDR_REV_EN_MASK 0x8
+
+/* NIC0_RXB_CORE_STATS_CFG0 */
+#define NIC0_RXB_CORE_STATS_CFG0_MEAS_WIN_SIZE_SHIFT 0
+#define NIC0_RXB_CORE_STATS_CFG0_MEAS_WIN_SIZE_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_STATS_CFG1 */
+#define NIC0_RXB_CORE_STATS_CFG1_STATS_EN_SHIFT 0
+#define NIC0_RXB_CORE_STATS_CFG1_STATS_EN_MASK 0x1
+#define NIC0_RXB_CORE_STATS_CFG1_TOT_TYPE_SHIFT 1
+#define NIC0_RXB_CORE_STATS_CFG1_TOT_TYPE_MASK 0x6
+#define NIC0_RXB_CORE_STATS_CFG1_WIN_TYPE_SHIFT 4
+#define NIC0_RXB_CORE_STATS_CFG1_WIN_TYPE_MASK 0x30
+#define NIC0_RXB_CORE_STATS_CFG1_PORT_COUNT_EN_SHIFT 8
+#define NIC0_RXB_CORE_STATS_CFG1_PORT_COUNT_EN_MASK 0xF00
+#define NIC0_RXB_CORE_STATS_CFG1_MEASURE_RXE2RXB_SHIFT 12
+#define NIC0_RXB_CORE_STATS_CFG1_MEASURE_RXE2RXB_MASK 0x1000
+#define NIC0_RXB_CORE_STATS_CFG1_IGNORE_MIN_ZERO_SHIFT 13
+#define NIC0_RXB_CORE_STATS_CFG1_IGNORE_MIN_ZERO_MASK 0x2000
+#define NIC0_RXB_CORE_STATS_CFG1_CLEAR_SC_SHIFT 31
+#define NIC0_RXB_CORE_STATS_CFG1_CLEAR_SC_MASK 0x80000000
+
+/* NIC0_RXB_CORE_STATS_CFG2 */
+#define NIC0_RXB_CORE_STATS_CFG2_PORT_EN_SHIFT 0
+#define NIC0_RXB_CORE_STATS_CFG2_PORT_EN_MASK 0xF
+#define NIC0_RXB_CORE_STATS_CFG2_PRIO_EN_SHIFT 4
+#define NIC0_RXB_CORE_STATS_CFG2_PRIO_EN_MASK 0xF0
+#define NIC0_RXB_CORE_STATS_CFG2_TYPE_EN_SHIFT 8
+#define NIC0_RXB_CORE_STATS_CFG2_TYPE_EN_MASK 0xF00
+#define NIC0_RXB_CORE_STATS_CFG2_DROP_EN_SHIFT 12
+#define NIC0_RXB_CORE_STATS_CFG2_DROP_EN_MASK 0x3000
+
+/* NIC0_RXB_CORE_STATS_TOT_BYTES_LSB */
+#define NIC0_RXB_CORE_STATS_TOT_BYTES_LSB_R_SHIFT 0
+#define NIC0_RXB_CORE_STATS_TOT_BYTES_LSB_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_STATS_TOT_BYTES_MSB */
+#define NIC0_RXB_CORE_STATS_TOT_BYTES_MSB_R_SHIFT 0
+#define NIC0_RXB_CORE_STATS_TOT_BYTES_MSB_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_STATS_TOT_PKTS_LSB */
+#define NIC0_RXB_CORE_STATS_TOT_PKTS_LSB_R_SHIFT 0
+#define NIC0_RXB_CORE_STATS_TOT_PKTS_LSB_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_STATS_TOT_PKTS_MSB */
+#define NIC0_RXB_CORE_STATS_TOT_PKTS_MSB_R_SHIFT 0
+#define NIC0_RXB_CORE_STATS_TOT_PKTS_MSB_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_STATS_MEAS_WIN_BYTES_LSB */
+#define NIC0_RXB_CORE_STATS_MEAS_WIN_BYTES_LSB_R_SHIFT 0
+#define NIC0_RXB_CORE_STATS_MEAS_WIN_BYTES_LSB_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_STATS_MEAS_WIN_BYTES_MSB */
+#define NIC0_RXB_CORE_STATS_MEAS_WIN_BYTES_MSB_R_SHIFT 0
+#define NIC0_RXB_CORE_STATS_MEAS_WIN_BYTES_MSB_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_STATS_MEAS_WIN_PKTS */
+#define NIC0_RXB_CORE_STATS_MEAS_WIN_PKTS_R_SHIFT 0
+#define NIC0_RXB_CORE_STATS_MEAS_WIN_PKTS_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXB_CORE_SEI_INTR_CAUSE */
+#define NIC0_RXB_CORE_SEI_INTR_CAUSE_HBW_BRESP_ERR_SHIFT 0
+#define NIC0_RXB_CORE_SEI_INTR_CAUSE_HBW_BRESP_ERR_MASK 0x1
+#define NIC0_RXB_CORE_SEI_INTR_CAUSE_LBW_BRESP_ERR_SHIFT 1
+#define NIC0_RXB_CORE_SEI_INTR_CAUSE_LBW_BRESP_ERR_MASK 0x2
+
+/* NIC0_RXB_CORE_SEI_INTR_MASK */
+#define NIC0_RXB_CORE_SEI_INTR_MASK_HBW_BRESP_ERR_SHIFT 0
+#define NIC0_RXB_CORE_SEI_INTR_MASK_HBW_BRESP_ERR_MASK 0x1
+#define NIC0_RXB_CORE_SEI_INTR_MASK_LBW_BRESP_ERR_SHIFT 1
+#define NIC0_RXB_CORE_SEI_INTR_MASK_LBW_BRESP_ERR_MASK 0x2
+
+/* NIC0_RXB_CORE_SEI_INTR_CLEAR */
+#define NIC0_RXB_CORE_SEI_INTR_CLEAR_HBW_BRESP_ERR_SHIFT 0
+#define NIC0_RXB_CORE_SEI_INTR_CLEAR_HBW_BRESP_ERR_MASK 0x1
+#define NIC0_RXB_CORE_SEI_INTR_CLEAR_LBW_BRESP_ERR_SHIFT 1
+#define NIC0_RXB_CORE_SEI_INTR_CLEAR_LBW_BRESP_ERR_MASK 0x2
+
+/* NIC0_RXB_CORE_SPI_INTR_CAUSE */
+#define NIC0_RXB_CORE_SPI_INTR_CAUSE_PKT_DROP_NO_CRDT_SHIFT 0
+#define NIC0_RXB_CORE_SPI_INTR_CAUSE_PKT_DROP_NO_CRDT_MASK 0x1
+#define NIC0_RXB_CORE_SPI_INTR_CAUSE_BUILD_POINTERS_CNT_INV_SHIFT 1
+#define NIC0_RXB_CORE_SPI_INTR_CAUSE_BUILD_POINTERS_CNT_INV_MASK 0x1E
+#define NIC0_RXB_CORE_SPI_INTR_CAUSE_SCATTER_POINTERS_CNT_INV_SHIFT 5
+#define NIC0_RXB_CORE_SPI_INTR_CAUSE_SCATTER_POINTERS_CNT_INV_MASK 0x20
+
+/* NIC0_RXB_CORE_SPI_INTR_MASK */
+#define NIC0_RXB_CORE_SPI_INTR_MASK_PKT_DROP_NO_CRDT_SHIFT 0
+#define NIC0_RXB_CORE_SPI_INTR_MASK_PKT_DROP_NO_CRDT_MASK 0x1
+#define NIC0_RXB_CORE_SPI_INTR_MASK_BUILD_POINTERS_CNT_INV_SHIFT 1
+#define NIC0_RXB_CORE_SPI_INTR_MASK_BUILD_POINTERS_CNT_INV_MASK 0x1E
+#define NIC0_RXB_CORE_SPI_INTR_MASK_SCATTER_POINTERS_CNT_INV_SHIFT 5
+#define NIC0_RXB_CORE_SPI_INTR_MASK_SCATTER_POINTERS_CNT_INV_MASK 0x20
+
+/* NIC0_RXB_CORE_SPI_INTR_CLEAR */
+#define NIC0_RXB_CORE_SPI_INTR_CLEAR_PKT_DROP_NO_CRDT_SHIFT 0
+#define NIC0_RXB_CORE_SPI_INTR_CLEAR_PKT_DROP_NO_CRDT_MASK 0x1
+#define NIC0_RXB_CORE_SPI_INTR_CLEAR_BUILD_POINTERS_CNT_INV_SHIFT 1
+#define NIC0_RXB_CORE_SPI_INTR_CLEAR_BUILD_POINTERS_CNT_INV_MASK 0x1E
+#define NIC0_RXB_CORE_SPI_INTR_CLEAR_SCATTER_POINTERS_CNT_INV_SHIFT 5
+#define NIC0_RXB_CORE_SPI_INTR_CLEAR_SCATTER_POINTERS_CNT_INV_MASK 0x20
+
+#endif /* ASIC_REG_NIC0_RXB_CORE_MASKS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxb_core_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxb_core_regs.h
new file mode 100644
index 000000000000..106e61e36288
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxb_core_regs.h
@@ -0,0 +1,665 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_RXB_CORE_REGS_H_
+#define ASIC_REG_NIC0_RXB_CORE_REGS_H_
+
+/*****************************************
+ * NIC0_RXB_CORE
+ * (Prototype: NIC_RXB_CORE)
+ *****************************************
+ */
+
+#define NIC0_RXB_CORE_RXB_CFG 0x5449000
+
+#define NIC0_RXB_CORE_CG 0x5449004
+
+#define NIC0_RXB_CORE_CG_TIMER 0x5449008
+
+#define NIC0_RXB_CORE_SCT_RL 0x544900C
+
+#define NIC0_RXB_CORE_APB_BASE_ADDR_TMR 0x5449010
+
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXB 0x5449014
+
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXE0 0x5449018
+
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXE1 0x544901C
+
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXE0_AXUSER 0x5449020
+
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RXE1_AXUSER 0x5449024
+
+#define NIC0_RXB_CORE_APB_BASE_ADDR_RX_RSVD 0x5449028
+
+#define NIC0_RXB_CORE_HL_ROCE_CONFIG 0x5449100
+
+#define NIC0_RXB_CORE_DYNAMIC_CREDITS 0x5449104
+
+#define NIC0_RXB_CORE_MAX_DYNAMIC 0x5449108
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_0 0x544910C
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_1 0x5449110
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_2 0x5449114
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_3 0x5449118
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_4 0x544911C
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_5 0x5449120
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_6 0x5449124
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_7 0x5449128
+
+#define NIC0_RXB_CORE_MAX_STATIC_CREDITS_0 0x544912C
+
+#define NIC0_RXB_CORE_MAX_STATIC_CREDITS_1 0x5449130
+
+#define NIC0_RXB_CORE_MAX_STATIC_CREDITS_2 0x5449134
+
+#define NIC0_RXB_CORE_MAX_STATIC_CREDITS_3 0x5449138
+
+#define NIC0_RXB_CORE_MAX_STATIC_CREDITS_4 0x544913C
+
+#define NIC0_RXB_CORE_MAX_STATIC_CREDITS_5 0x5449140
+
+#define NIC0_RXB_CORE_MAX_STATIC_CREDITS_6 0x5449144
+
+#define NIC0_RXB_CORE_MAX_STATIC_CREDITS_7 0x5449148
+
+#define NIC0_RXB_CORE_XOFF_THRESHOLD_0 0x544914C
+
+#define NIC0_RXB_CORE_XOFF_THRESHOLD_1 0x5449150
+
+#define NIC0_RXB_CORE_XOFF_THRESHOLD_2 0x5449154
+
+#define NIC0_RXB_CORE_XOFF_THRESHOLD_3 0x5449158
+
+#define NIC0_RXB_CORE_XOFF_THRESHOLD_4 0x544915C
+
+#define NIC0_RXB_CORE_XOFF_THRESHOLD_5 0x5449160
+
+#define NIC0_RXB_CORE_XOFF_THRESHOLD_6 0x5449164
+
+#define NIC0_RXB_CORE_XOFF_THRESHOLD_7 0x5449168
+
+#define NIC0_RXB_CORE_XON_THRESHOLD_0 0x544916C
+
+#define NIC0_RXB_CORE_XON_THRESHOLD_1 0x5449170
+
+#define NIC0_RXB_CORE_XON_THRESHOLD_2 0x5449174
+
+#define NIC0_RXB_CORE_XON_THRESHOLD_3 0x5449178
+
+#define NIC0_RXB_CORE_XON_THRESHOLD_4 0x544917C
+
+#define NIC0_RXB_CORE_XON_THRESHOLD_5 0x5449180
+
+#define NIC0_RXB_CORE_XON_THRESHOLD_6 0x5449184
+
+#define NIC0_RXB_CORE_XON_THRESHOLD_7 0x5449188
+
+#define NIC0_RXB_CORE_DROP_THRESHOLD_0 0x544918C
+
+#define NIC0_RXB_CORE_DROP_THRESHOLD_1 0x5449190
+
+#define NIC0_RXB_CORE_DROP_THRESHOLD_2 0x5449194
+
+#define NIC0_RXB_CORE_DROP_THRESHOLD_3 0x5449198
+
+#define NIC0_RXB_CORE_DROP_THRESHOLD_4 0x544919C
+
+#define NIC0_RXB_CORE_DROP_THRESHOLD_5 0x54491A0
+
+#define NIC0_RXB_CORE_DROP_THRESHOLD_6 0x54491A4
+
+#define NIC0_RXB_CORE_DROP_THRESHOLD_7 0x54491A8
+
+#define NIC0_RXB_CORE_DROP_SMALL_THRESHOLD_0 0x54491AC
+
+#define NIC0_RXB_CORE_DROP_SMALL_THRESHOLD_1 0x54491B0
+
+#define NIC0_RXB_CORE_DROP_SMALL_THRESHOLD_2 0x54491B4
+
+#define NIC0_RXB_CORE_DROP_SMALL_THRESHOLD_3 0x54491B8
+
+#define NIC0_RXB_CORE_DROP_SMALL_THRESHOLD_4 0x54491BC
+
+#define NIC0_RXB_CORE_DROP_SMALL_THRESHOLD_5 0x54491C0
+
+#define NIC0_RXB_CORE_DROP_SMALL_THRESHOLD_6 0x54491C4
+
+#define NIC0_RXB_CORE_DROP_SMALL_THRESHOLD_7 0x54491C8
+
+#define NIC0_RXB_CORE_DYNAMIC_CREDITS_STAT 0x54491CC
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_STAT_0 0x54491D0
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_STAT_1 0x54491D4
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_STAT_2 0x54491D8
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_STAT_3 0x54491DC
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_STAT_4 0x54491E0
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_STAT_5 0x54491E4
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_STAT_6 0x54491E8
+
+#define NIC0_RXB_CORE_STATIC_CREDITS_STAT_7 0x54491EC
+
+#define NIC0_RXB_CORE_MAC_PFC_MODE 0x5449200
+
+#define NIC0_RXB_CORE_PORT_TRUST_LEVEL 0x5449240
+
+#define NIC0_RXB_CORE_PORT_DEFAULT_PRIO 0x5449250
+
+#define NIC0_RXB_CORE_DSCP2PRIO_0 0x5449260
+
+#define NIC0_RXB_CORE_DSCP2PRIO_1 0x5449264
+
+#define NIC0_RXB_CORE_DSCP2PRIO_2 0x5449268
+
+#define NIC0_RXB_CORE_DSCP2PRIO_3 0x544926C
+
+#define NIC0_RXB_CORE_DSCP2PRIO_4 0x5449270
+
+#define NIC0_RXB_CORE_DSCP2PRIO_5 0x5449274
+
+#define NIC0_RXB_CORE_DSCP2PRIO_6 0x5449278
+
+#define NIC0_RXB_CORE_DSCP2PRIO_7 0x544927C
+
+#define NIC0_RXB_CORE_ICRC_CFG 0x5449280
+
+#define NIC0_RXB_CORE_AXI_AWPROT_HBW 0x544928C
+
+#define NIC0_RXB_CORE_AXI_AWPROT_LBW 0x5449290
+
+#define NIC0_RXB_CORE_VLAN_ETHERTYPES 0x54492B0
+
+#define NIC0_RXB_CORE_TS_RC_MAC_31_0_0 0x54492C0
+
+#define NIC0_RXB_CORE_TS_RC_MAC_31_0_1 0x54492C4
+
+#define NIC0_RXB_CORE_TS_RC_MAC_31_0_2 0x54492C8
+
+#define NIC0_RXB_CORE_TS_RC_MAC_31_0_3 0x54492CC
+
+#define NIC0_RXB_CORE_TS_RC_MAC_47_32_0 0x54492D0
+
+#define NIC0_RXB_CORE_TS_RC_MAC_47_32_1 0x54492D4
+
+#define NIC0_RXB_CORE_TS_RC_MAC_47_32_2 0x54492D8
+
+#define NIC0_RXB_CORE_TS_RC_MAC_47_32_3 0x54492DC
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_31_0_0 0x54492E0
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_31_0_1 0x54492E4
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_31_0_2 0x54492E8
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_31_0_3 0x54492EC
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_47_32_0 0x54492F0
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_47_32_1 0x54492F4
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_47_32_2 0x54492F8
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_47_32_3 0x54492FC
+
+#define NIC0_RXB_CORE_TS_RC_MAC_31_0_MASK_0 0x5449320
+
+#define NIC0_RXB_CORE_TS_RC_MAC_31_0_MASK_1 0x5449324
+
+#define NIC0_RXB_CORE_TS_RC_MAC_31_0_MASK_2 0x5449328
+
+#define NIC0_RXB_CORE_TS_RC_MAC_31_0_MASK_3 0x544932C
+
+#define NIC0_RXB_CORE_TS_RC_MAC_47_32_MASK_0 0x5449330
+
+#define NIC0_RXB_CORE_TS_RC_MAC_47_32_MASK_1 0x5449334
+
+#define NIC0_RXB_CORE_TS_RC_MAC_47_32_MASK_2 0x5449338
+
+#define NIC0_RXB_CORE_TS_RC_MAC_47_32_MASK_3 0x544933C
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_31_0_MASK_0 0x5449340
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_31_0_MASK_1 0x5449344
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_31_0_MASK_2 0x5449348
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_31_0_MASK_3 0x544934C
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_47_32_MASK_0 0x5449350
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_47_32_MASK_1 0x5449354
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_47_32_MASK_2 0x5449358
+
+#define NIC0_RXB_CORE_TS_RAW0_MAC_47_32_MASK_3 0x544935C
+
+#define NIC0_RXB_CORE_DBG_SPMU_SELECT 0x5449400
+
+#define NIC0_RXB_CORE_DBG_ERROR 0x5449408
+
+#define NIC0_RXB_CORE_DBG_ENDIANNESS 0x5449410
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_0 0x5449480
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_1 0x5449484
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_2 0x5449488
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_3 0x544948C
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_4 0x5449490
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_5 0x5449494
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_6 0x5449498
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_7 0x544949C
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_8 0x54494A0
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_9 0x54494A4
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_10 0x54494A8
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_11 0x54494AC
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_12 0x54494B0
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_13 0x54494B4
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_14 0x54494B8
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_15 0x54494BC
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_16 0x54494C0
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_17 0x54494C4
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_18 0x54494C8
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_19 0x54494CC
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_20 0x54494D0
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_21 0x54494D4
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_22 0x54494D8
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_23 0x54494DC
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_24 0x54494E0
+
+#define NIC0_RXB_CORE_DBG_LAST_PARSING_25 0x54494E4
+
+#define NIC0_RXB_CORE_DBG_LAST_CTRL_0 0x5449500
+
+#define NIC0_RXB_CORE_DBG_LAST_CTRL_1 0x5449504
+
+#define NIC0_RXB_CORE_DBG_LAST_CTRL_2 0x5449508
+
+#define NIC0_RXB_CORE_DBG_LAST_CTRL_3 0x544950C
+
+#define NIC0_RXB_CORE_DBG_LAST_CTRL_4 0x5449510
+
+#define NIC0_RXB_CORE_DBG_LAST_CTRL_5 0x5449514
+
+#define NIC0_RXB_CORE_DBG_LAST_CTRL_6 0x5449518
+
+#define NIC0_RXB_CORE_DBG_LAST_CTRL_7 0x544951C
+
+#define NIC0_RXB_CORE_DBG_LAST_CTRL_8 0x5449520
+
+#define NIC0_RXB_CORE_DBG_LAST_CTRL_9 0x5449524
+
+#define NIC0_RXB_CORE_DBG_LAST_SCATTER_0 0x5449540
+
+#define NIC0_RXB_CORE_DBG_LAST_SCATTER_1 0x5449544
+
+#define NIC0_RXB_CORE_DBG_LAST_SCATTER_2 0x5449548
+
+#define NIC0_RXB_CORE_DBG_LAST_SCATTER_3 0x544954C
+
+#define NIC0_RXB_CORE_DBG_LAST_SCATTER_4 0x5449550
+
+#define NIC0_RXB_CORE_DBG_LAST_SCATTER_5 0x5449554
+
+#define NIC0_RXB_CORE_DBG_LAST_DONE 0x5449560
+
+#define NIC0_RXB_CORE_DBG_EN 0x5449564
+
+#define NIC0_RXB_CORE_DBG_RXE_CRDT 0x5449568
+
+#define NIC0_RXB_CORE_DBG_BUF_LVL 0x544956C
+
+#define NIC0_RXB_CORE_DBG_SCT 0x5449570
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_0 0x5449700
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_1 0x5449704
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_2 0x5449708
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_3 0x544970C
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_0 0x5449710
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_1 0x5449714
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_2 0x5449718
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_3 0x544971C
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_4 0x5449720
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_5 0x5449724
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_6 0x5449728
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_7 0x544972C
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_8 0x5449730
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_9 0x5449734
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_10 0x5449738
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_11 0x544973C
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_12 0x5449740
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_13 0x5449744
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_14 0x5449748
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_15 0x544974C
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_16 0x5449750
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_17 0x5449754
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_18 0x5449758
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_19 0x544975C
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_20 0x5449760
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_21 0x5449764
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_22 0x5449768
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_23 0x544976C
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_24 0x5449770
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_25 0x5449774
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_26 0x5449778
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_27 0x544977C
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_28 0x5449780
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_29 0x5449784
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_30 0x5449788
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_HDR_31 0x544978C
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_0 0x5449790
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_1 0x5449794
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_2 0x5449798
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_3 0x544979C
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_4 0x54497A0
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_5 0x54497A4
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_6 0x54497A8
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_7 0x54497AC
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_8 0x54497B0
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_9 0x54497B4
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_10 0x54497B8
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_11 0x54497BC
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_12 0x54497C0
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_13 0x54497C4
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_14 0x54497C8
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_15 0x54497CC
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_16 0x54497D0
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_17 0x54497D4
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_18 0x54497D8
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_19 0x54497DC
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_20 0x54497E0
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_21 0x54497E4
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_22 0x54497E8
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_23 0x54497EC
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_24 0x54497F0
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_25 0x54497F4
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_26 0x54497F8
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_27 0x54497FC
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_28 0x5449800
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_29 0x5449804
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_30 0x5449808
+
+#define NIC0_RXB_CORE_TNL_DECAP_IPV4_MASK_31 0x544980C
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_0 0x5449810
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_1 0x5449814
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_2 0x5449818
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_3 0x544981C
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_0 0x5449820
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_1 0x5449824
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_2 0x5449828
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_3 0x544982C
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_4 0x5449830
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_5 0x5449834
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_6 0x5449838
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_7 0x544983C
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_8 0x5449840
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_9 0x5449844
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_10 0x5449848
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_11 0x544984C
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_12 0x5449850
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_13 0x5449854
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_14 0x5449858
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_15 0x544985C
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_16 0x5449860
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_17 0x5449864
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_18 0x5449868
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_19 0x544986C
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_20 0x5449870
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_21 0x5449874
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_22 0x5449878
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_23 0x544987C
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_24 0x5449880
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_25 0x5449884
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_26 0x5449888
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_27 0x544988C
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_28 0x5449890
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_29 0x5449894
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_30 0x5449898
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_HDR_31 0x544989C
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_0 0x54498A0
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_1 0x54498A4
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_2 0x54498A8
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_3 0x54498AC
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_4 0x54498B0
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_5 0x54498B4
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_6 0x54498B8
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_7 0x54498BC
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_8 0x54498C0
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_9 0x54498C4
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_10 0x54498C8
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_11 0x54498CC
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_12 0x54498D0
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_13 0x54498D4
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_14 0x54498D8
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_15 0x54498DC
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_16 0x54498E0
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_17 0x54498E4
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_18 0x54498E8
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_19 0x54498EC
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_20 0x54498F0
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_21 0x54498F4
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_22 0x54498F8
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_23 0x54498FC
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_24 0x5449900
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_25 0x5449904
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_26 0x5449908
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_27 0x544990C
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_28 0x5449910
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_29 0x5449914
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_30 0x5449918
+
+#define NIC0_RXB_CORE_TNL_DECAP_UDP_MASK_31 0x544991C
+
+#define NIC0_RXB_CORE_TNL_DECAP_CFG 0x5449920
+
+#define NIC0_RXB_CORE_STATS_CFG0 0x5449940
+
+#define NIC0_RXB_CORE_STATS_CFG1 0x5449944
+
+#define NIC0_RXB_CORE_STATS_CFG2 0x5449948
+
+#define NIC0_RXB_CORE_STATS_TOT_BYTES_LSB 0x5449950
+
+#define NIC0_RXB_CORE_STATS_TOT_BYTES_MSB 0x5449954
+
+#define NIC0_RXB_CORE_STATS_TOT_PKTS_LSB 0x5449958
+
+#define NIC0_RXB_CORE_STATS_TOT_PKTS_MSB 0x544995C
+
+#define NIC0_RXB_CORE_STATS_MEAS_WIN_BYTES_LSB 0x5449960
+
+#define NIC0_RXB_CORE_STATS_MEAS_WIN_BYTES_MSB 0x5449964
+
+#define NIC0_RXB_CORE_STATS_MEAS_WIN_PKTS 0x5449968
+
+#define NIC0_RXB_CORE_SEI_INTR_CAUSE 0x5449980
+
+#define NIC0_RXB_CORE_SEI_INTR_MASK 0x5449984
+
+#define NIC0_RXB_CORE_SEI_INTR_CLEAR 0x5449988
+
+#define NIC0_RXB_CORE_SPI_INTR_CAUSE 0x5449990
+
+#define NIC0_RXB_CORE_SPI_INTR_MASK 0x5449994
+
+#define NIC0_RXB_CORE_SPI_INTR_CLEAR 0x5449998
+
+#endif /* ASIC_REG_NIC0_RXB_CORE_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_axuser_axuser_cq0_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_axuser_axuser_cq0_regs.h
new file mode 100644
index 000000000000..6c7cfa33c1fd
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_axuser_axuser_cq0_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_RXE0_AXUSER_AXUSER_CQ0_REGS_H_
+#define ASIC_REG_NIC0_RXE0_AXUSER_AXUSER_CQ0_REGS_H_
+
+/*****************************************
+ * NIC0_RXE0_AXUSER_AXUSER_CQ0
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_ASID 0x544C000
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_MMU_BP 0x544C004
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_STRONG_ORDER 0x544C008
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_NO_SNOOP 0x544C00C
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_WR_REDUCTION 0x544C010
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_RD_ATOMIC 0x544C014
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_QOS 0x544C018
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_RSVD 0x544C01C
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_EMEM_CPAGE 0x544C020
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_CORE 0x544C024
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_E2E_COORD 0x544C028
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_WR_OVRD_LO 0x544C030
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_WR_OVRD_HI 0x544C034
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_RD_OVRD_LO 0x544C038
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_RD_OVRD_HI 0x544C03C
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_LB_COORD 0x544C040
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_LB_LOCK 0x544C044
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_LB_RSVD 0x544C048
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_LB_OVRD 0x544C04C
+
+#endif /* ASIC_REG_NIC0_RXE0_AXUSER_AXUSER_CQ0_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_axuser_axuser_cq1_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_axuser_axuser_cq1_regs.h
new file mode 100644
index 000000000000..9b890275dc9a
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_axuser_axuser_cq1_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_RXE0_AXUSER_AXUSER_CQ1_REGS_H_
+#define ASIC_REG_NIC0_RXE0_AXUSER_AXUSER_CQ1_REGS_H_
+
+/*****************************************
+ * NIC0_RXE0_AXUSER_AXUSER_CQ1
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_ASID 0x544C050
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_MMU_BP 0x544C054
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_STRONG_ORDER 0x544C058
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_NO_SNOOP 0x544C05C
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_WR_REDUCTION 0x544C060
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_RD_ATOMIC 0x544C064
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_QOS 0x544C068
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_RSVD 0x544C06C
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_EMEM_CPAGE 0x544C070
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_CORE 0x544C074
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_E2E_COORD 0x544C078
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_WR_OVRD_LO 0x544C080
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_WR_OVRD_HI 0x544C084
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_RD_OVRD_LO 0x544C088
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_RD_OVRD_HI 0x544C08C
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_LB_COORD 0x544C090
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_LB_LOCK 0x544C094
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_LB_RSVD 0x544C098
+
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_LB_OVRD 0x544C09C
+
+#endif /* ASIC_REG_NIC0_RXE0_AXUSER_AXUSER_CQ1_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_masks.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_masks.h
new file mode 100644
index 000000000000..3e56b9d05262
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_masks.h
@@ -0,0 +1,705 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_RXE0_MASKS_H_
+#define ASIC_REG_NIC0_RXE0_MASKS_H_
+
+/*****************************************
+ * NIC0_RXE0
+ * (Prototype: NIC_RXE)
+ *****************************************
+ */
+
+/* NIC0_RXE0_CONTROL */
+#define NIC0_RXE0_CONTROL_SCATTER_BARRIER_SHIFT 0
+#define NIC0_RXE0_CONTROL_SCATTER_BARRIER_MASK 0x1
+#define NIC0_RXE0_CONTROL_IGNORE_RNR_NAK_SHIFT 1
+#define NIC0_RXE0_CONTROL_IGNORE_RNR_NAK_MASK 0x2
+#define NIC0_RXE0_CONTROL_SOB_CQ_MUTEX_SHIFT 2
+#define NIC0_RXE0_CONTROL_SOB_CQ_MUTEX_MASK 0x4
+#define NIC0_RXE0_CONTROL_SPARE0_SHIFT 3
+#define NIC0_RXE0_CONTROL_SPARE0_MASK 0xFFF8
+#define NIC0_RXE0_CONTROL_SPARE1_SHIFT 16
+#define NIC0_RXE0_CONTROL_SPARE1_MASK 0xFFFF0000
+
+/* NIC0_RXE0_SCATTER_CFG */
+#define NIC0_RXE0_SCATTER_CFG_FORCE_SOB_DATA_SHIFT 0
+#define NIC0_RXE0_SCATTER_CFG_FORCE_SOB_DATA_MASK 0x1
+#define NIC0_RXE0_SCATTER_CFG_SOB_ADDR_MSB_SHIFT 1
+#define NIC0_RXE0_SCATTER_CFG_SOB_ADDR_MSB_MASK 0x2
+#define NIC0_RXE0_SCATTER_CFG_REDUC_OP_NEW_DST_SHIFT 2
+#define NIC0_RXE0_SCATTER_CFG_REDUC_OP_NEW_DST_MASK 0x4
+#define NIC0_RXE0_SCATTER_CFG_RETH_VA_MSB_SHIFT 3
+#define NIC0_RXE0_SCATTER_CFG_RETH_VA_MSB_MASK 0x1FFF8
+
+/* NIC0_RXE0_SCATTER_CQ_ADDR */
+#define NIC0_RXE0_SCATTER_CQ_ADDR_VAL_SHIFT 0
+#define NIC0_RXE0_SCATTER_CQ_ADDR_VAL_MASK 0x3FFFFFF
+
+/* NIC0_RXE0_RAW_QPN_P0 */
+#define NIC0_RXE0_RAW_QPN_P0_RAW_QPN_P0_SHIFT 0
+#define NIC0_RXE0_RAW_QPN_P0_RAW_QPN_P0_MASK 0xFFFFFF
+
+/* NIC0_RXE0_RAW_QPN_P1 */
+#define NIC0_RXE0_RAW_QPN_P1_RAW_QPN_P1_SHIFT 0
+#define NIC0_RXE0_RAW_QPN_P1_RAW_QPN_P1_MASK 0xFFFFFF
+
+/* NIC0_RXE0_RAW_QPN_P2 */
+#define NIC0_RXE0_RAW_QPN_P2_RAW_QPN_P2_SHIFT 0
+#define NIC0_RXE0_RAW_QPN_P2_RAW_QPN_P2_MASK 0xFFFFFF
+
+/* NIC0_RXE0_RAW_QPN_P3 */
+#define NIC0_RXE0_RAW_QPN_P3_RAW_QPN_P3_SHIFT 0
+#define NIC0_RXE0_RAW_QPN_P3_RAW_QPN_P3_MASK 0xFFFFFF
+
+/* NIC0_RXE0_RXE_CHECKS */
+#define NIC0_RXE0_RXE_CHECKS_QP_INVALID_EN_SHIFT 0
+#define NIC0_RXE0_RXE_CHECKS_QP_INVALID_EN_MASK 0x1
+#define NIC0_RXE0_RXE_CHECKS_TS_MISMATCH_EN_SHIFT 1
+#define NIC0_RXE0_RXE_CHECKS_TS_MISMATCH_EN_MASK 0x2
+#define NIC0_RXE0_RXE_CHECKS_REQ_CS_INVALID_EN_SHIFT 2
+#define NIC0_RXE0_RXE_CHECKS_REQ_CS_INVALID_EN_MASK 0x4
+#define NIC0_RXE0_RXE_CHECKS_RES_CS_INVALID_EN_SHIFT 3
+#define NIC0_RXE0_RXE_CHECKS_RES_CS_INVALID_EN_MASK 0x8
+#define NIC0_RXE0_RXE_CHECKS_REQ_PSN_INVALID_EN_SHIFT 4
+#define NIC0_RXE0_RXE_CHECKS_REQ_PSN_INVALID_EN_MASK 0x10
+#define NIC0_RXE0_RXE_CHECKS_REQ_PSN_UNSENT_EN_SHIFT 5
+#define NIC0_RXE0_RXE_CHECKS_REQ_PSN_UNSENT_EN_MASK 0x20
+#define NIC0_RXE0_RXE_CHECKS_RES_RKEY_INVALID_EN_SHIFT 6
+#define NIC0_RXE0_RXE_CHECKS_RES_RKEY_INVALID_EN_MASK 0x40
+#define NIC0_RXE0_RXE_CHECKS_RES_RESYNC_INVALID_EN_SHIFT 7
+#define NIC0_RXE0_RXE_CHECKS_RES_RESYNC_INVALID_EN_MASK 0x80
+#define NIC0_RXE0_RXE_CHECKS_PKT_BAD_FORMAT_EN_SHIFT 8
+#define NIC0_RXE0_RXE_CHECKS_PKT_BAD_FORMAT_EN_MASK 0x100
+#define NIC0_RXE0_RXE_CHECKS_INV_OPCODE_EN_SHIFT 9
+#define NIC0_RXE0_RXE_CHECKS_INV_OPCODE_EN_MASK 0x200
+#define NIC0_RXE0_RXE_CHECKS_INV_SYNDROME_EN_SHIFT 10
+#define NIC0_RXE0_RXE_CHECKS_INV_SYNDROME_EN_MASK 0x400
+#define NIC0_RXE0_RXE_CHECKS_INV_MIN_PKT_SIZE_RC_EN_SHIFT 11
+#define NIC0_RXE0_RXE_CHECKS_INV_MIN_PKT_SIZE_RC_EN_MASK 0x800
+#define NIC0_RXE0_RXE_CHECKS_INV_MAX_PKT_SIZE_RC_EN_SHIFT 12
+#define NIC0_RXE0_RXE_CHECKS_INV_MAX_PKT_SIZE_RC_EN_MASK 0x1000
+#define NIC0_RXE0_RXE_CHECKS_INV_MIN_PKT_SIZE_RAW_EN_SHIFT 13
+#define NIC0_RXE0_RXE_CHECKS_INV_MIN_PKT_SIZE_RAW_EN_MASK 0x2000
+#define NIC0_RXE0_RXE_CHECKS_INV_MAX_PKT_SIZE_RAW_EN_SHIFT 14
+#define NIC0_RXE0_RXE_CHECKS_INV_MAX_PKT_SIZE_RAW_EN_MASK 0x4000
+#define NIC0_RXE0_RXE_CHECKS_TUNNEL_INV_EN_SHIFT 15
+#define NIC0_RXE0_RXE_CHECKS_TUNNEL_INV_EN_MASK 0x8000
+#define NIC0_RXE0_RXE_CHECKS_WQE_IDX_MISMATCH_EN_SHIFT 16
+#define NIC0_RXE0_RXE_CHECKS_WQE_IDX_MISMATCH_EN_MASK 0x10000
+#define NIC0_RXE0_RXE_CHECKS_WQ_WR_OPCODE_INV_EN_SHIFT 17
+#define NIC0_RXE0_RXE_CHECKS_WQ_WR_OPCODE_INV_EN_MASK 0x20000
+#define NIC0_RXE0_RXE_CHECKS_WQ_RDV_OPCODE_INV_EN_SHIFT 18
+#define NIC0_RXE0_RXE_CHECKS_WQ_RDV_OPCODE_INV_EN_MASK 0x40000
+#define NIC0_RXE0_RXE_CHECKS_WQ_RD_OPCODE_INV_EN_SHIFT 19
+#define NIC0_RXE0_RXE_CHECKS_WQ_RD_OPCODE_INV_EN_MASK 0x80000
+#define NIC0_RXE0_RXE_CHECKS_WQE_WR_ZERO_EN_SHIFT 20
+#define NIC0_RXE0_RXE_CHECKS_WQE_WR_ZERO_EN_MASK 0x100000
+#define NIC0_RXE0_RXE_CHECKS_WQE_MULTI_ZERO_EN_SHIFT 21
+#define NIC0_RXE0_RXE_CHECKS_WQE_MULTI_ZERO_EN_MASK 0x200000
+#define NIC0_RXE0_RXE_CHECKS_WQE_WR_SEND_BIG_EN_SHIFT 22
+#define NIC0_RXE0_RXE_CHECKS_WQE_WR_SEND_BIG_EN_MASK 0x400000
+#define NIC0_RXE0_RXE_CHECKS_WQE_MULTI_BIG_EN_SHIFT 23
+#define NIC0_RXE0_RXE_CHECKS_WQE_MULTI_BIG_EN_MASK 0x800000
+
+/* NIC0_RXE0_PKT_DROP */
+#define NIC0_RXE0_PKT_DROP_ERR_QP_INVALID_SHIFT 0
+#define NIC0_RXE0_PKT_DROP_ERR_QP_INVALID_MASK 0x1
+#define NIC0_RXE0_PKT_DROP_ERR_TS_MISMATCH_SHIFT 1
+#define NIC0_RXE0_PKT_DROP_ERR_TS_MISMATCH_MASK 0x2
+#define NIC0_RXE0_PKT_DROP_ERR_REQ_CS_INVALID_SHIFT 2
+#define NIC0_RXE0_PKT_DROP_ERR_REQ_CS_INVALID_MASK 0x4
+#define NIC0_RXE0_PKT_DROP_ERR_RES_CS_INVALID_SHIFT 3
+#define NIC0_RXE0_PKT_DROP_ERR_RES_CS_INVALID_MASK 0x8
+#define NIC0_RXE0_PKT_DROP_ERR_REQ_PSN_INVALID_SHIFT 4
+#define NIC0_RXE0_PKT_DROP_ERR_REQ_PSN_INVALID_MASK 0x10
+#define NIC0_RXE0_PKT_DROP_ERR_REQ_PSN_UNSENT_SHIFT 5
+#define NIC0_RXE0_PKT_DROP_ERR_REQ_PSN_UNSENT_MASK 0x20
+#define NIC0_RXE0_PKT_DROP_ERR_RES_RKEY_INVALID_SHIFT 6
+#define NIC0_RXE0_PKT_DROP_ERR_RES_RKEY_INVALID_MASK 0x40
+#define NIC0_RXE0_PKT_DROP_ERR_RES_RESYNC_INVALID_SHIFT 7
+#define NIC0_RXE0_PKT_DROP_ERR_RES_RESYNC_INVALID_MASK 0x80
+#define NIC0_RXE0_PKT_DROP_ERR_PKT_BAD_FORMAT_SHIFT 8
+#define NIC0_RXE0_PKT_DROP_ERR_PKT_BAD_FORMAT_MASK 0x100
+#define NIC0_RXE0_PKT_DROP_ERR_INV_OPCODE_SHIFT 9
+#define NIC0_RXE0_PKT_DROP_ERR_INV_OPCODE_MASK 0x200
+#define NIC0_RXE0_PKT_DROP_ERR_INV_SYNDROME_SHIFT 10
+#define NIC0_RXE0_PKT_DROP_ERR_INV_SYNDROME_MASK 0x400
+#define NIC0_RXE0_PKT_DROP_ERR_INV_MIN_PKT_SIZE_RC_SHIFT 11
+#define NIC0_RXE0_PKT_DROP_ERR_INV_MIN_PKT_SIZE_RC_MASK 0x800
+#define NIC0_RXE0_PKT_DROP_ERR_INV_MAX_PKT_SIZE_RC_SHIFT 12
+#define NIC0_RXE0_PKT_DROP_ERR_INV_MAX_PKT_SIZE_RC_MASK 0x1000
+#define NIC0_RXE0_PKT_DROP_ERR_INV_MIN_PKT_SIZE_RAW_SHIFT 13
+#define NIC0_RXE0_PKT_DROP_ERR_INV_MIN_PKT_SIZE_RAW_MASK 0x2000
+#define NIC0_RXE0_PKT_DROP_ERR_INV_MAX_PKT_SIZE_RAW_SHIFT 14
+#define NIC0_RXE0_PKT_DROP_ERR_INV_MAX_PKT_SIZE_RAW_MASK 0x4000
+#define NIC0_RXE0_PKT_DROP_ERR_TUNNEL_INV_SHIFT 15
+#define NIC0_RXE0_PKT_DROP_ERR_TUNNEL_INV_MASK 0x8000
+#define NIC0_RXE0_PKT_DROP_ERR_WQE_IDX_MISMATCH_SHIFT 16
+#define NIC0_RXE0_PKT_DROP_ERR_WQE_IDX_MISMATCH_MASK 0x10000
+#define NIC0_RXE0_PKT_DROP_ERR_WQ_WR_OPCODE_INV_SHIFT 17
+#define NIC0_RXE0_PKT_DROP_ERR_WQ_WR_OPCODE_INV_MASK 0x20000
+#define NIC0_RXE0_PKT_DROP_ERR_WQ_RDV_OPCODE_INV_SHIFT 18
+#define NIC0_RXE0_PKT_DROP_ERR_WQ_RDV_OPCODE_INV_MASK 0x40000
+#define NIC0_RXE0_PKT_DROP_ERR_WQ_RD_OPCODE_INV_SHIFT 19
+#define NIC0_RXE0_PKT_DROP_ERR_WQ_RD_OPCODE_INV_MASK 0x80000
+#define NIC0_RXE0_PKT_DROP_ERR_WQE_WR_ZERO_SHIFT 20
+#define NIC0_RXE0_PKT_DROP_ERR_WQE_WR_ZERO_MASK 0x100000
+#define NIC0_RXE0_PKT_DROP_ERR_WQE_MULTI_ZERO_SHIFT 21
+#define NIC0_RXE0_PKT_DROP_ERR_WQE_MULTI_ZERO_MASK 0x200000
+#define NIC0_RXE0_PKT_DROP_ERR_WQE_WR_SEND_BIG_SHIFT 22
+#define NIC0_RXE0_PKT_DROP_ERR_WQE_WR_SEND_BIG_MASK 0x400000
+#define NIC0_RXE0_PKT_DROP_ERR_WQE_MULTI_BIG_SHIFT 23
+#define NIC0_RXE0_PKT_DROP_ERR_WQE_MULTI_BIG_MASK 0x800000
+
+/* NIC0_RXE0_PKT_SIZE_CHECK_RC */
+#define NIC0_RXE0_PKT_SIZE_CHECK_RC_MIN_SHIFT 0
+#define NIC0_RXE0_PKT_SIZE_CHECK_RC_MIN_MASK 0xFFFF
+#define NIC0_RXE0_PKT_SIZE_CHECK_RC_MAX_SHIFT 16
+#define NIC0_RXE0_PKT_SIZE_CHECK_RC_MAX_MASK 0xFFFF0000
+
+/* NIC0_RXE0_PKT_SIZE_CHECK_RAW */
+#define NIC0_RXE0_PKT_SIZE_CHECK_RAW_MIN_SHIFT 0
+#define NIC0_RXE0_PKT_SIZE_CHECK_RAW_MIN_MASK 0xFFFF
+
+/* NIC0_RXE0_ARUSER_MMU_BP */
+#define NIC0_RXE0_ARUSER_MMU_BP_VAL_SHIFT 0
+#define NIC0_RXE0_ARUSER_MMU_BP_VAL_MASK 0xF
+
+/* NIC0_RXE0_AWUSER_LBW */
+#define NIC0_RXE0_AWUSER_LBW_AWUSER_LBW_SHIFT 0
+#define NIC0_RXE0_AWUSER_LBW_AWUSER_LBW_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_ARPROT_HBW */
+#define NIC0_RXE0_ARPROT_HBW_ARPROT_HBW_UNSECURED_SHIFT 0
+#define NIC0_RXE0_ARPROT_HBW_ARPROT_HBW_UNSECURED_MASK 0x7
+#define NIC0_RXE0_ARPROT_HBW_ARPROT_HBW_SECURED_SHIFT 4
+#define NIC0_RXE0_ARPROT_HBW_ARPROT_HBW_SECURED_MASK 0x70
+#define NIC0_RXE0_ARPROT_HBW_ARPROT_HBW_PRIVILEGED_SHIFT 8
+#define NIC0_RXE0_ARPROT_HBW_ARPROT_HBW_PRIVILEGED_MASK 0x700
+
+/* NIC0_RXE0_AWPROT_LBW */
+#define NIC0_RXE0_AWPROT_LBW_AWPROT_LBW_UNSECURED_SHIFT 0
+#define NIC0_RXE0_AWPROT_LBW_AWPROT_LBW_UNSECURED_MASK 0x7
+#define NIC0_RXE0_AWPROT_LBW_AWPROT_LBW_SECURED_SHIFT 4
+#define NIC0_RXE0_AWPROT_LBW_AWPROT_LBW_SECURED_MASK 0x70
+#define NIC0_RXE0_AWPROT_LBW_AWPROT_LBW_PRIVILEGED_SHIFT 8
+#define NIC0_RXE0_AWPROT_LBW_AWPROT_LBW_PRIVILEGED_MASK 0x700
+
+/* NIC0_RXE0_WIN0_WQ_BASE_LO */
+#define NIC0_RXE0_WIN0_WQ_BASE_LO_WQ_BASE_ADDR_LO_SHIFT 0
+#define NIC0_RXE0_WIN0_WQ_BASE_LO_WQ_BASE_ADDR_LO_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_WIN0_WQ_BASE_HI */
+#define NIC0_RXE0_WIN0_WQ_BASE_HI_WQ_BASE_ADDR_HI_SHIFT 0
+#define NIC0_RXE0_WIN0_WQ_BASE_HI_WQ_BASE_ADDR_HI_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_WIN0_WQ_MISC */
+#define NIC0_RXE0_WIN0_WQ_MISC_LOG_MAX_WQ_SIZE_SHIFT 0
+#define NIC0_RXE0_WIN0_WQ_MISC_LOG_MAX_WQ_SIZE_MASK 0x1F
+
+/* NIC0_RXE0_WIN1_WQ_BASE_LO */
+#define NIC0_RXE0_WIN1_WQ_BASE_LO_WQ_BASE_ADDR_LO_SHIFT 0
+#define NIC0_RXE0_WIN1_WQ_BASE_LO_WQ_BASE_ADDR_LO_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_WIN1_WQ_BASE_HI */
+#define NIC0_RXE0_WIN1_WQ_BASE_HI_WQ_BASE_ADDR_HI_SHIFT 0
+#define NIC0_RXE0_WIN1_WQ_BASE_HI_WQ_BASE_ADDR_HI_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_WIN1_WQ_MISC */
+#define NIC0_RXE0_WIN1_WQ_MISC_LOG_MAX_WQ_SIZE_SHIFT 0
+#define NIC0_RXE0_WIN1_WQ_MISC_LOG_MAX_WQ_SIZE_MASK 0x1F
+
+/* NIC0_RXE0_WIN2_WQ_BASE_LO */
+#define NIC0_RXE0_WIN2_WQ_BASE_LO_WQ_BASE_ADDR_LO_SHIFT 0
+#define NIC0_RXE0_WIN2_WQ_BASE_LO_WQ_BASE_ADDR_LO_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_WIN2_WQ_BASE_HI */
+#define NIC0_RXE0_WIN2_WQ_BASE_HI_WQ_BASE_ADDR_HI_SHIFT 0
+#define NIC0_RXE0_WIN2_WQ_BASE_HI_WQ_BASE_ADDR_HI_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_WIN2_WQ_MISC */
+#define NIC0_RXE0_WIN2_WQ_MISC_LOG_MAX_WQ_SIZE_SHIFT 0
+#define NIC0_RXE0_WIN2_WQ_MISC_LOG_MAX_WQ_SIZE_MASK 0x1F
+
+/* NIC0_RXE0_WIN3_WQ_BASE_LO */
+#define NIC0_RXE0_WIN3_WQ_BASE_LO_WQ_BASE_ADDR_LO_SHIFT 0
+#define NIC0_RXE0_WIN3_WQ_BASE_LO_WQ_BASE_ADDR_LO_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_WIN3_WQ_BASE_HI */
+#define NIC0_RXE0_WIN3_WQ_BASE_HI_WQ_BASE_ADDR_HI_SHIFT 0
+#define NIC0_RXE0_WIN3_WQ_BASE_HI_WQ_BASE_ADDR_HI_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_WIN3_WQ_MISC */
+#define NIC0_RXE0_WIN3_WQ_MISC_LOG_MAX_WQ_SIZE_SHIFT 0
+#define NIC0_RXE0_WIN3_WQ_MISC_LOG_MAX_WQ_SIZE_MASK 0x1F
+
+/* NIC0_RXE0_CG */
+#define NIC0_RXE0_CG_DISABLE_SHIFT 0
+#define NIC0_RXE0_CG_DISABLE_MASK 0x1
+#define NIC0_RXE0_CG_GATED_CLK_ACTIVE_SHIFT 1
+#define NIC0_RXE0_CG_GATED_CLK_ACTIVE_MASK 0x2
+
+/* NIC0_RXE0_CG_TIMER */
+#define NIC0_RXE0_CG_TIMER_VAL_SHIFT 0
+#define NIC0_RXE0_CG_TIMER_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_WQE_WQ_WR_OP_DISABLE */
+#define NIC0_RXE0_WQE_WQ_WR_OP_DISABLE_VAL_SHIFT 0
+#define NIC0_RXE0_WQE_WQ_WR_OP_DISABLE_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_WQE_WQ_RDV_OP_DISABLE */
+#define NIC0_RXE0_WQE_WQ_RDV_OP_DISABLE_VAL_SHIFT 0
+#define NIC0_RXE0_WQE_WQ_RDV_OP_DISABLE_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_WQE_WQ_RD_OP_DISABLE */
+#define NIC0_RXE0_WQE_WQ_RD_OP_DISABLE_VAL_SHIFT 0
+#define NIC0_RXE0_WQE_WQ_RD_OP_DISABLE_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_WQE_MAX_WRITE_SEND_SIZE */
+#define NIC0_RXE0_WQE_MAX_WRITE_SEND_SIZE_VAL_SHIFT 0
+#define NIC0_RXE0_WQE_MAX_WRITE_SEND_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_WQE_MAX_MULTI_STRIDE_SIZE */
+#define NIC0_RXE0_WQE_MAX_MULTI_STRIDE_SIZE_VAL_SHIFT 0
+#define NIC0_RXE0_WQE_MAX_MULTI_STRIDE_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_CACHE_CFG */
+#define NIC0_RXE0_CACHE_CFG_STOP_SHIFT 0
+#define NIC0_RXE0_CACHE_CFG_STOP_MASK 0x1
+#define NIC0_RXE0_CACHE_CFG_FORCE_BYPASS_SHIFT 1
+#define NIC0_RXE0_CACHE_CFG_FORCE_BYPASS_MASK 0x2
+#define NIC0_RXE0_CACHE_CFG_INVALIDATION_SHIFT 2
+#define NIC0_RXE0_CACHE_CFG_INVALIDATION_MASK 0x4
+#define NIC0_RXE0_CACHE_CFG_RELEASE_INVALIDATE_SHIFT 3
+#define NIC0_RXE0_CACHE_CFG_RELEASE_INVALIDATE_MASK 0x8
+#define NIC0_RXE0_CACHE_CFG_INVALIDATE_WRITEBACK_SHIFT 4
+#define NIC0_RXE0_CACHE_CFG_INVALIDATE_WRITEBACK_MASK 0x10
+#define NIC0_RXE0_CACHE_CFG_PLRU_EVICT_SHIFT 5
+#define NIC0_RXE0_CACHE_CFG_PLRU_EVICT_MASK 0x20
+#define NIC0_RXE0_CACHE_CFG_LOCK_SLICE_DIS_SHIFT 6
+#define NIC0_RXE0_CACHE_CFG_LOCK_SLICE_DIS_MASK 0x40
+
+/* NIC0_RXE0_CACHE_INFO */
+#define NIC0_RXE0_CACHE_INFO_INVALIDATION_DONE_SHIFT 0
+#define NIC0_RXE0_CACHE_INFO_INVALIDATION_DONE_MASK 0x1
+#define NIC0_RXE0_CACHE_INFO_IDLE_SHIFT 1
+#define NIC0_RXE0_CACHE_INFO_IDLE_MASK 0x2
+
+/* NIC0_RXE0_CACHE_ADDR_LO */
+#define NIC0_RXE0_CACHE_ADDR_LO_VAL_SHIFT 7
+#define NIC0_RXE0_CACHE_ADDR_LO_VAL_MASK 0xFFFFFF80
+
+/* NIC0_RXE0_CACHE_ADDR_HI */
+#define NIC0_RXE0_CACHE_ADDR_HI_VAL_SHIFT 0
+#define NIC0_RXE0_CACHE_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_CQ_BASE_ADDR_31_7 */
+#define NIC0_RXE0_CQ_BASE_ADDR_31_7_R_SHIFT 7
+#define NIC0_RXE0_CQ_BASE_ADDR_31_7_R_MASK 0xFFFFFF80
+
+/* NIC0_RXE0_CQ_BASE_ADDR_63_32 */
+#define NIC0_RXE0_CQ_BASE_ADDR_63_32_R_SHIFT 0
+#define NIC0_RXE0_CQ_BASE_ADDR_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_CQ_LOG_MAX_SIZE */
+#define NIC0_RXE0_CQ_LOG_MAX_SIZE_R_SHIFT 0
+#define NIC0_RXE0_CQ_LOG_MAX_SIZE_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_CQ_ARM_TIMEOUT_EN */
+#define NIC0_RXE0_CQ_ARM_TIMEOUT_EN_EN_SHIFT 0
+#define NIC0_RXE0_CQ_ARM_TIMEOUT_EN_EN_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_CQ_ARM_TIMEOUT */
+#define NIC0_RXE0_CQ_ARM_TIMEOUT_VAL_SHIFT 0
+#define NIC0_RXE0_CQ_ARM_TIMEOUT_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_CQ_CFG */
+#define NIC0_RXE0_CQ_CFG_ENABLE_SHIFT 0
+#define NIC0_RXE0_CQ_CFG_ENABLE_MASK 0x1
+#define NIC0_RXE0_CQ_CFG_OVERRUN_EN_SHIFT 1
+#define NIC0_RXE0_CQ_CFG_OVERRUN_EN_MASK 0x2
+#define NIC0_RXE0_CQ_CFG_WINDOW_WRAPAROUND_EN_SHIFT 2
+#define NIC0_RXE0_CQ_CFG_WINDOW_WRAPAROUND_EN_MASK 0x4
+#define NIC0_RXE0_CQ_CFG_WRITE_PI_EN_SHIFT 3
+#define NIC0_RXE0_CQ_CFG_WRITE_PI_EN_MASK 0x8
+#define NIC0_RXE0_CQ_CFG_CMPL_EVENT_PER_CQE_SHIFT 4
+#define NIC0_RXE0_CQ_CFG_CMPL_EVENT_PER_CQE_MASK 0x10
+#define NIC0_RXE0_CQ_CFG_CMPL_EVENT_FIRST_CQE_SHIFT 5
+#define NIC0_RXE0_CQ_CFG_CMPL_EVENT_FIRST_CQE_MASK 0x20
+#define NIC0_RXE0_CQ_CFG_CMPL_EVENT_CI_UPDATED_SHIFT 6
+#define NIC0_RXE0_CQ_CFG_CMPL_EVENT_CI_UPDATED_MASK 0x40
+
+/* NIC0_RXE0_CQ_WRITE_INDEX */
+#define NIC0_RXE0_CQ_WRITE_INDEX_R_SHIFT 0
+#define NIC0_RXE0_CQ_WRITE_INDEX_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_CQ_PRODUCER_INDEX */
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_R_SHIFT 0
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_CQ_CONSUMER_INDEX */
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_R_SHIFT 0
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_CQ_PI_ADDR_LO */
+#define NIC0_RXE0_CQ_PI_ADDR_LO_R_SHIFT 0
+#define NIC0_RXE0_CQ_PI_ADDR_LO_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_CQ_PI_ADDR_HI */
+#define NIC0_RXE0_CQ_PI_ADDR_HI_R_SHIFT 0
+#define NIC0_RXE0_CQ_PI_ADDR_HI_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_CQ_AXI_PROT */
+#define NIC0_RXE0_CQ_AXI_PROT_VAL_SHIFT 0
+#define NIC0_RXE0_CQ_AXI_PROT_VAL_MASK 0x7
+
+/* NIC0_RXE0_CQ_LOG_SIZE */
+#define NIC0_RXE0_CQ_LOG_SIZE_R_SHIFT 0
+#define NIC0_RXE0_CQ_LOG_SIZE_R_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_RDV_SEND_WQ_BASE_ADDR_LO */
+#define NIC0_RXE0_RDV_SEND_WQ_BASE_ADDR_LO_VAL_SHIFT 0
+#define NIC0_RXE0_RDV_SEND_WQ_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_RDV_SEND_WQ_BASE_ADDR_HI */
+#define NIC0_RXE0_RDV_SEND_WQ_BASE_ADDR_HI_VAL_SHIFT 0
+#define NIC0_RXE0_RDV_SEND_WQ_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_RDV_LOG_MAX_WQ_SIZE */
+#define NIC0_RXE0_RDV_LOG_MAX_WQ_SIZE_VAL_SHIFT 0
+#define NIC0_RXE0_RDV_LOG_MAX_WQ_SIZE_VAL_MASK 0x3F
+
+/* NIC0_RXE0_LBW_BASE_LO */
+#define NIC0_RXE0_LBW_BASE_LO_LBW_BASE_ADDR_LO_SHIFT 0
+#define NIC0_RXE0_LBW_BASE_LO_LBW_BASE_ADDR_LO_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_LBW_BASE_HI */
+#define NIC0_RXE0_LBW_BASE_HI_LBW_BASE_ADDR_HI_SHIFT 0
+#define NIC0_RXE0_LBW_BASE_HI_LBW_BASE_ADDR_HI_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_LBW_LOG_SIZE */
+#define NIC0_RXE0_LBW_LOG_SIZE_LBW_LOG_SIZE_SHIFT 0
+#define NIC0_RXE0_LBW_LOG_SIZE_LBW_LOG_SIZE_MASK 0x3F
+
+/* NIC0_RXE0_RAW_BASE_LO_P0 */
+#define NIC0_RXE0_RAW_BASE_LO_P0_RAW_BASE_ADDR_LO_P0_SHIFT 0
+#define NIC0_RXE0_RAW_BASE_LO_P0_RAW_BASE_ADDR_LO_P0_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_RAW_BASE_HI_P0 */
+#define NIC0_RXE0_RAW_BASE_HI_P0_RAW_BASE_ADDR_HI_P0_SHIFT 0
+#define NIC0_RXE0_RAW_BASE_HI_P0_RAW_BASE_ADDR_HI_P0_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_RAW_MISC_P0 */
+#define NIC0_RXE0_RAW_MISC_P0_LOG_RAW_ENTRY_SIZE_P0_SHIFT 0
+#define NIC0_RXE0_RAW_MISC_P0_LOG_RAW_ENTRY_SIZE_P0_MASK 0xF
+#define NIC0_RXE0_RAW_MISC_P0_RAW_REDUC_OP_P0_SHIFT 5
+#define NIC0_RXE0_RAW_MISC_P0_RAW_REDUC_OP_P0_MASK 0x7FE0
+#define NIC0_RXE0_RAW_MISC_P0_LOG_BUFFER_SIZE_MASK_P0_SHIFT 15
+#define NIC0_RXE0_RAW_MISC_P0_LOG_BUFFER_SIZE_MASK_P0_MASK 0xF8000
+
+/* NIC0_RXE0_RAW_BASE_LO_P1 */
+#define NIC0_RXE0_RAW_BASE_LO_P1_RAW_BASE_ADDR_LO_P1_SHIFT 0
+#define NIC0_RXE0_RAW_BASE_LO_P1_RAW_BASE_ADDR_LO_P1_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_RAW_BASE_HI_P1 */
+#define NIC0_RXE0_RAW_BASE_HI_P1_RAW_BASE_ADDR_HI_P1_SHIFT 0
+#define NIC0_RXE0_RAW_BASE_HI_P1_RAW_BASE_ADDR_HI_P1_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_RAW_MISC_P1 */
+#define NIC0_RXE0_RAW_MISC_P1_LOG_RAW_ENTRY_SIZE_P1_SHIFT 0
+#define NIC0_RXE0_RAW_MISC_P1_LOG_RAW_ENTRY_SIZE_P1_MASK 0xF
+#define NIC0_RXE0_RAW_MISC_P1_RAW_REDUC_OP_P1_SHIFT 5
+#define NIC0_RXE0_RAW_MISC_P1_RAW_REDUC_OP_P1_MASK 0x7FE0
+#define NIC0_RXE0_RAW_MISC_P1_LOG_BUFFER_SIZE_MASK_P1_SHIFT 15
+#define NIC0_RXE0_RAW_MISC_P1_LOG_BUFFER_SIZE_MASK_P1_MASK 0xF8000
+
+/* NIC0_RXE0_RAW_BASE_LO_P2 */
+#define NIC0_RXE0_RAW_BASE_LO_P2_RAW_BASE_ADDR_LO_P2_SHIFT 0
+#define NIC0_RXE0_RAW_BASE_LO_P2_RAW_BASE_ADDR_LO_P2_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_RAW_BASE_HI_P2 */
+#define NIC0_RXE0_RAW_BASE_HI_P2_RAW_BASE_ADDR_HI_P2_SHIFT 0
+#define NIC0_RXE0_RAW_BASE_HI_P2_RAW_BASE_ADDR_HI_P2_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_RAW_MISC_P2 */
+#define NIC0_RXE0_RAW_MISC_P2_LOG_RAW_ENTRY_SIZE_P2_SHIFT 0
+#define NIC0_RXE0_RAW_MISC_P2_LOG_RAW_ENTRY_SIZE_P2_MASK 0xF
+#define NIC0_RXE0_RAW_MISC_P2_RAW_REDUC_OP_P2_SHIFT 5
+#define NIC0_RXE0_RAW_MISC_P2_RAW_REDUC_OP_P2_MASK 0x7FE0
+#define NIC0_RXE0_RAW_MISC_P2_LOG_BUFFER_SIZE_MASK_P2_SHIFT 15
+#define NIC0_RXE0_RAW_MISC_P2_LOG_BUFFER_SIZE_MASK_P2_MASK 0xF8000
+
+/* NIC0_RXE0_RAW_BASE_LO_P3 */
+#define NIC0_RXE0_RAW_BASE_LO_P3_RAW_BASE_ADDR_LO_P3_SHIFT 0
+#define NIC0_RXE0_RAW_BASE_LO_P3_RAW_BASE_ADDR_LO_P3_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_RAW_BASE_HI_P3 */
+#define NIC0_RXE0_RAW_BASE_HI_P3_RAW_BASE_ADDR_HI_P3_SHIFT 0
+#define NIC0_RXE0_RAW_BASE_HI_P3_RAW_BASE_ADDR_HI_P3_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_RAW_MISC_P3 */
+#define NIC0_RXE0_RAW_MISC_P3_LOG_RAW_ENTRY_SIZE_P3_SHIFT 0
+#define NIC0_RXE0_RAW_MISC_P3_LOG_RAW_ENTRY_SIZE_P3_MASK 0xF
+#define NIC0_RXE0_RAW_MISC_P3_RAW_REDUC_OP_P3_SHIFT 5
+#define NIC0_RXE0_RAW_MISC_P3_RAW_REDUC_OP_P3_MASK 0x7FE0
+#define NIC0_RXE0_RAW_MISC_P3_LOG_BUFFER_SIZE_MASK_P3_SHIFT 15
+#define NIC0_RXE0_RAW_MISC_P3_LOG_BUFFER_SIZE_MASK_P3_MASK 0xF8000
+
+/* NIC0_RXE0_SEI_INTR_CAUSE */
+#define NIC0_RXE0_SEI_INTR_CAUSE_HBW_RRESP_ERR_WQE_SHIFT 0
+#define NIC0_RXE0_SEI_INTR_CAUSE_HBW_RRESP_ERR_WQE_MASK 0x1
+#define NIC0_RXE0_SEI_INTR_CAUSE_HBW_RRESP_ERR_FNA_SHIFT 1
+#define NIC0_RXE0_SEI_INTR_CAUSE_HBW_RRESP_ERR_FNA_MASK 0x2
+#define NIC0_RXE0_SEI_INTR_CAUSE_LBW_BRESP_ERR_SHIFT 2
+#define NIC0_RXE0_SEI_INTR_CAUSE_LBW_BRESP_ERR_MASK 0x4
+#define NIC0_RXE0_SEI_INTR_CAUSE_HBW_BRESP_ERR_SHIFT 3
+#define NIC0_RXE0_SEI_INTR_CAUSE_HBW_BRESP_ERR_MASK 0x8
+
+/* NIC0_RXE0_SEI_INTR_MASK */
+#define NIC0_RXE0_SEI_INTR_MASK_HBW_RRESP_ERR_WQE_SHIFT 0
+#define NIC0_RXE0_SEI_INTR_MASK_HBW_RRESP_ERR_WQE_MASK 0x1
+#define NIC0_RXE0_SEI_INTR_MASK_HBW_RRESP_ERR_FNA_SHIFT 1
+#define NIC0_RXE0_SEI_INTR_MASK_HBW_RRESP_ERR_FNA_MASK 0x2
+#define NIC0_RXE0_SEI_INTR_MASK_LBW_BRESP_ERR_SHIFT 2
+#define NIC0_RXE0_SEI_INTR_MASK_LBW_BRESP_ERR_MASK 0x4
+#define NIC0_RXE0_SEI_INTR_MASK_HBW_BRESP_ERR_SHIFT 3
+#define NIC0_RXE0_SEI_INTR_MASK_HBW_BRESP_ERR_MASK 0x8
+
+/* NIC0_RXE0_SEI_INTR_CLEAR */
+#define NIC0_RXE0_SEI_INTR_CLEAR_HBW_RRESP_ERR_WQE_SHIFT 0
+#define NIC0_RXE0_SEI_INTR_CLEAR_HBW_RRESP_ERR_WQE_MASK 0x1
+#define NIC0_RXE0_SEI_INTR_CLEAR_HBW_RRESP_ERR_FNA_SHIFT 1
+#define NIC0_RXE0_SEI_INTR_CLEAR_HBW_RRESP_ERR_FNA_MASK 0x2
+#define NIC0_RXE0_SEI_INTR_CLEAR_LBW_BRESP_ERR_SHIFT 2
+#define NIC0_RXE0_SEI_INTR_CLEAR_LBW_BRESP_ERR_MASK 0x4
+#define NIC0_RXE0_SEI_INTR_CLEAR_HBW_BRESP_ERR_SHIFT 3
+#define NIC0_RXE0_SEI_INTR_CLEAR_HBW_BRESP_ERR_MASK 0x8
+
+/* NIC0_RXE0_SPI_INTR_CAUSE */
+#define NIC0_RXE0_SPI_INTR_CAUSE_QP_INVALID_SHIFT 0
+#define NIC0_RXE0_SPI_INTR_CAUSE_QP_INVALID_MASK 0x1
+#define NIC0_RXE0_SPI_INTR_CAUSE_TS_MISMATCH_SHIFT 1
+#define NIC0_RXE0_SPI_INTR_CAUSE_TS_MISMATCH_MASK 0x2
+#define NIC0_RXE0_SPI_INTR_CAUSE_REQ_CS_INVALID_SHIFT 2
+#define NIC0_RXE0_SPI_INTR_CAUSE_REQ_CS_INVALID_MASK 0x4
+#define NIC0_RXE0_SPI_INTR_CAUSE_RES_CS_INVALID_SHIFT 3
+#define NIC0_RXE0_SPI_INTR_CAUSE_RES_CS_INVALID_MASK 0x8
+#define NIC0_RXE0_SPI_INTR_CAUSE_REQ_PSN_INVALID_SHIFT 4
+#define NIC0_RXE0_SPI_INTR_CAUSE_REQ_PSN_INVALID_MASK 0x10
+#define NIC0_RXE0_SPI_INTR_CAUSE_REQ_PSN_UNSENT_SHIFT 5
+#define NIC0_RXE0_SPI_INTR_CAUSE_REQ_PSN_UNSENT_MASK 0x20
+#define NIC0_RXE0_SPI_INTR_CAUSE_RES_RKEY_INVALID_SHIFT 6
+#define NIC0_RXE0_SPI_INTR_CAUSE_RES_RKEY_INVALID_MASK 0x40
+#define NIC0_RXE0_SPI_INTR_CAUSE_RES_RESYNC_INVALID_SHIFT 7
+#define NIC0_RXE0_SPI_INTR_CAUSE_RES_RESYNC_INVALID_MASK 0x80
+#define NIC0_RXE0_SPI_INTR_CAUSE_PKT_BAD_FORMAT_SHIFT 8
+#define NIC0_RXE0_SPI_INTR_CAUSE_PKT_BAD_FORMAT_MASK 0x100
+#define NIC0_RXE0_SPI_INTR_CAUSE_INV_OPCODE_SHIFT 9
+#define NIC0_RXE0_SPI_INTR_CAUSE_INV_OPCODE_MASK 0x200
+#define NIC0_RXE0_SPI_INTR_CAUSE_INV_SYNDROME_SHIFT 10
+#define NIC0_RXE0_SPI_INTR_CAUSE_INV_SYNDROME_MASK 0x400
+#define NIC0_RXE0_SPI_INTR_CAUSE_INV_MIN_PKT_SIZE_RC_SHIFT 11
+#define NIC0_RXE0_SPI_INTR_CAUSE_INV_MIN_PKT_SIZE_RC_MASK 0x800
+#define NIC0_RXE0_SPI_INTR_CAUSE_INV_MAX_PKT_SIZE_RC_SHIFT 12
+#define NIC0_RXE0_SPI_INTR_CAUSE_INV_MAX_PKT_SIZE_RC_MASK 0x1000
+#define NIC0_RXE0_SPI_INTR_CAUSE_INV_MIN_PKT_SIZE_RAW_SHIFT 13
+#define NIC0_RXE0_SPI_INTR_CAUSE_INV_MIN_PKT_SIZE_RAW_MASK 0x2000
+#define NIC0_RXE0_SPI_INTR_CAUSE_INV_MAX_PKT_SIZE_RAW_SHIFT 14
+#define NIC0_RXE0_SPI_INTR_CAUSE_INV_MAX_PKT_SIZE_RAW_MASK 0x4000
+#define NIC0_RXE0_SPI_INTR_CAUSE_TUNNEL_INV_SHIFT 15
+#define NIC0_RXE0_SPI_INTR_CAUSE_TUNNEL_INV_MASK 0x8000
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQE_IDX_MISMATCH_SHIFT 16
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQE_IDX_MISMATCH_MASK 0x10000
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQ_WR_OPCODE_INV_SHIFT 17
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQ_WR_OPCODE_INV_MASK 0x20000
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQ_RDV_OPCODE_INV_SHIFT 18
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQ_RDV_OPCODE_INV_MASK 0x40000
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQ_RD_OPCODE_INV_SHIFT 19
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQ_RD_OPCODE_INV_MASK 0x80000
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQE_WR_ZERO_SHIFT 20
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQE_WR_ZERO_MASK 0x100000
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQE_MULTI_ZERO_SHIFT 21
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQE_MULTI_ZERO_MASK 0x200000
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQE_WR_SEND_BIG_SHIFT 22
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQE_WR_SEND_BIG_MASK 0x400000
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQE_MULTI_BIG_SHIFT 23
+#define NIC0_RXE0_SPI_INTR_CAUSE_WQE_MULTI_BIG_MASK 0x800000
+
+/* NIC0_RXE0_SPI_INTR_MASK */
+#define NIC0_RXE0_SPI_INTR_MASK_QP_INVALID_SHIFT 0
+#define NIC0_RXE0_SPI_INTR_MASK_QP_INVALID_MASK 0x1
+#define NIC0_RXE0_SPI_INTR_MASK_TS_MISMATCH_SHIFT 1
+#define NIC0_RXE0_SPI_INTR_MASK_TS_MISMATCH_MASK 0x2
+#define NIC0_RXE0_SPI_INTR_MASK_REQ_CS_INVALID_SHIFT 2
+#define NIC0_RXE0_SPI_INTR_MASK_REQ_CS_INVALID_MASK 0x4
+#define NIC0_RXE0_SPI_INTR_MASK_RES_CS_INVALID_SHIFT 3
+#define NIC0_RXE0_SPI_INTR_MASK_RES_CS_INVALID_MASK 0x8
+#define NIC0_RXE0_SPI_INTR_MASK_REQ_PSN_INVALID_SHIFT 4
+#define NIC0_RXE0_SPI_INTR_MASK_REQ_PSN_INVALID_MASK 0x10
+#define NIC0_RXE0_SPI_INTR_MASK_REQ_PSN_UNSENT_SHIFT 5
+#define NIC0_RXE0_SPI_INTR_MASK_REQ_PSN_UNSENT_MASK 0x20
+#define NIC0_RXE0_SPI_INTR_MASK_RES_RKEY_INVALID_SHIFT 6
+#define NIC0_RXE0_SPI_INTR_MASK_RES_RKEY_INVALID_MASK 0x40
+#define NIC0_RXE0_SPI_INTR_MASK_RES_RESYNC_INVALID_SHIFT 7
+#define NIC0_RXE0_SPI_INTR_MASK_RES_RESYNC_INVALID_MASK 0x80
+#define NIC0_RXE0_SPI_INTR_MASK_PKT_BAD_FORMAT_SHIFT 8
+#define NIC0_RXE0_SPI_INTR_MASK_PKT_BAD_FORMAT_MASK 0x100
+#define NIC0_RXE0_SPI_INTR_MASK_INV_OPCODE_SHIFT 9
+#define NIC0_RXE0_SPI_INTR_MASK_INV_OPCODE_MASK 0x200
+#define NIC0_RXE0_SPI_INTR_MASK_INV_SYNDROME_SHIFT 10
+#define NIC0_RXE0_SPI_INTR_MASK_INV_SYNDROME_MASK 0x400
+#define NIC0_RXE0_SPI_INTR_MASK_INV_MIN_PKT_SIZE_RC_SHIFT 11
+#define NIC0_RXE0_SPI_INTR_MASK_INV_MIN_PKT_SIZE_RC_MASK 0x800
+#define NIC0_RXE0_SPI_INTR_MASK_INV_MAX_PKT_SIZE_RC_SHIFT 12
+#define NIC0_RXE0_SPI_INTR_MASK_INV_MAX_PKT_SIZE_RC_MASK 0x1000
+#define NIC0_RXE0_SPI_INTR_MASK_INV_MIN_PKT_SIZE_RAW_SHIFT 13
+#define NIC0_RXE0_SPI_INTR_MASK_INV_MIN_PKT_SIZE_RAW_MASK 0x2000
+#define NIC0_RXE0_SPI_INTR_MASK_INV_MAX_PKT_SIZE_RAW_SHIFT 14
+#define NIC0_RXE0_SPI_INTR_MASK_INV_MAX_PKT_SIZE_RAW_MASK 0x4000
+#define NIC0_RXE0_SPI_INTR_MASK_TUNNEL_INV_SHIFT 15
+#define NIC0_RXE0_SPI_INTR_MASK_TUNNEL_INV_MASK 0x8000
+#define NIC0_RXE0_SPI_INTR_MASK_WQE_IDX_MISMATCH_SHIFT 16
+#define NIC0_RXE0_SPI_INTR_MASK_WQE_IDX_MISMATCH_MASK 0x10000
+#define NIC0_RXE0_SPI_INTR_MASK_WQ_WR_OPCODE_INV_SHIFT 17
+#define NIC0_RXE0_SPI_INTR_MASK_WQ_WR_OPCODE_INV_MASK 0x20000
+#define NIC0_RXE0_SPI_INTR_MASK_WQ_RDV_OPCODE_INV_SHIFT 18
+#define NIC0_RXE0_SPI_INTR_MASK_WQ_RDV_OPCODE_INV_MASK 0x40000
+#define NIC0_RXE0_SPI_INTR_MASK_WQ_RD_OPCODE_INV_SHIFT 19
+#define NIC0_RXE0_SPI_INTR_MASK_WQ_RD_OPCODE_INV_MASK 0x80000
+#define NIC0_RXE0_SPI_INTR_MASK_WQE_WR_ZERO_SHIFT 20
+#define NIC0_RXE0_SPI_INTR_MASK_WQE_WR_ZERO_MASK 0x100000
+#define NIC0_RXE0_SPI_INTR_MASK_WQE_MULTI_ZERO_SHIFT 21
+#define NIC0_RXE0_SPI_INTR_MASK_WQE_MULTI_ZERO_MASK 0x200000
+#define NIC0_RXE0_SPI_INTR_MASK_WQE_WR_SEND_BIG_SHIFT 22
+#define NIC0_RXE0_SPI_INTR_MASK_WQE_WR_SEND_BIG_MASK 0x400000
+#define NIC0_RXE0_SPI_INTR_MASK_WQE_MULTI_BIG_SHIFT 23
+#define NIC0_RXE0_SPI_INTR_MASK_WQE_MULTI_BIG_MASK 0x800000
+
+/* NIC0_RXE0_SPI_INTR_CLEAR */
+#define NIC0_RXE0_SPI_INTR_CLEAR_QP_INVALID_SHIFT 0
+#define NIC0_RXE0_SPI_INTR_CLEAR_QP_INVALID_MASK 0x1
+#define NIC0_RXE0_SPI_INTR_CLEAR_TS_MISMATCH_SHIFT 1
+#define NIC0_RXE0_SPI_INTR_CLEAR_TS_MISMATCH_MASK 0x2
+#define NIC0_RXE0_SPI_INTR_CLEAR_REQ_CS_INVALID_SHIFT 2
+#define NIC0_RXE0_SPI_INTR_CLEAR_REQ_CS_INVALID_MASK 0x4
+#define NIC0_RXE0_SPI_INTR_CLEAR_RES_CS_INVALID_SHIFT 3
+#define NIC0_RXE0_SPI_INTR_CLEAR_RES_CS_INVALID_MASK 0x8
+#define NIC0_RXE0_SPI_INTR_CLEAR_REQ_PSN_INVALID_SHIFT 4
+#define NIC0_RXE0_SPI_INTR_CLEAR_REQ_PSN_INVALID_MASK 0x10
+#define NIC0_RXE0_SPI_INTR_CLEAR_REQ_PSN_UNSENT_SHIFT 5
+#define NIC0_RXE0_SPI_INTR_CLEAR_REQ_PSN_UNSENT_MASK 0x20
+#define NIC0_RXE0_SPI_INTR_CLEAR_RES_RKEY_INVALID_SHIFT 6
+#define NIC0_RXE0_SPI_INTR_CLEAR_RES_RKEY_INVALID_MASK 0x40
+#define NIC0_RXE0_SPI_INTR_CLEAR_RES_RESYNC_INVALID_SHIFT 7
+#define NIC0_RXE0_SPI_INTR_CLEAR_RES_RESYNC_INVALID_MASK 0x80
+#define NIC0_RXE0_SPI_INTR_CLEAR_PKT_BAD_FORMAT_SHIFT 8
+#define NIC0_RXE0_SPI_INTR_CLEAR_PKT_BAD_FORMAT_MASK 0x100
+#define NIC0_RXE0_SPI_INTR_CLEAR_INV_OPCODE_SHIFT 9
+#define NIC0_RXE0_SPI_INTR_CLEAR_INV_OPCODE_MASK 0x200
+#define NIC0_RXE0_SPI_INTR_CLEAR_INV_SYNDROME_SHIFT 10
+#define NIC0_RXE0_SPI_INTR_CLEAR_INV_SYNDROME_MASK 0x400
+#define NIC0_RXE0_SPI_INTR_CLEAR_INV_MIN_PKT_SIZE_RC_SHIFT 11
+#define NIC0_RXE0_SPI_INTR_CLEAR_INV_MIN_PKT_SIZE_RC_MASK 0x800
+#define NIC0_RXE0_SPI_INTR_CLEAR_INV_MAX_PKT_SIZE_RC_SHIFT 12
+#define NIC0_RXE0_SPI_INTR_CLEAR_INV_MAX_PKT_SIZE_RC_MASK 0x1000
+#define NIC0_RXE0_SPI_INTR_CLEAR_INV_MIN_PKT_SIZE_RAW_SHIFT 13
+#define NIC0_RXE0_SPI_INTR_CLEAR_INV_MIN_PKT_SIZE_RAW_MASK 0x2000
+#define NIC0_RXE0_SPI_INTR_CLEAR_INV_MAX_PKT_SIZE_RAW_SHIFT 14
+#define NIC0_RXE0_SPI_INTR_CLEAR_INV_MAX_PKT_SIZE_RAW_MASK 0x4000
+#define NIC0_RXE0_SPI_INTR_CLEAR_TUNNEL_INV_SHIFT 15
+#define NIC0_RXE0_SPI_INTR_CLEAR_TUNNEL_INV_MASK 0x8000
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQE_IDX_MISMATCH_SHIFT 16
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQE_IDX_MISMATCH_MASK 0x10000
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQ_WR_OPCODE_INV_SHIFT 17
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQ_WR_OPCODE_INV_MASK 0x20000
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQ_RDV_OPCODE_INV_SHIFT 18
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQ_RDV_OPCODE_INV_MASK 0x40000
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQ_RD_OPCODE_INV_SHIFT 19
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQ_RD_OPCODE_INV_MASK 0x80000
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQE_WR_ZERO_SHIFT 20
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQE_WR_ZERO_MASK 0x100000
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQE_MULTI_ZERO_SHIFT 21
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQE_MULTI_ZERO_MASK 0x200000
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQE_WR_SEND_BIG_SHIFT 22
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQE_WR_SEND_BIG_MASK 0x400000
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQE_MULTI_BIG_SHIFT 23
+#define NIC0_RXE0_SPI_INTR_CLEAR_WQE_MULTI_BIG_MASK 0x800000
+
+/* NIC0_RXE0_DBG_SPMU_SELECT */
+#define NIC0_RXE0_DBG_SPMU_SELECT_VAL_SHIFT 0
+#define NIC0_RXE0_DBG_SPMU_SELECT_VAL_MASK 0x3
+
+/* NIC0_RXE0_DBG_INV_OP_0 */
+#define NIC0_RXE0_DBG_INV_OP_0_DBG_INV_OP_PSN_SHIFT 0
+#define NIC0_RXE0_DBG_INV_OP_0_DBG_INV_OP_PSN_MASK 0xFFFFFF
+#define NIC0_RXE0_DBG_INV_OP_0_DBG_INV_OP_LATCHED_SHIFT 31
+#define NIC0_RXE0_DBG_INV_OP_0_DBG_INV_OP_LATCHED_MASK 0x80000000
+
+/* NIC0_RXE0_DBG_INV_OP_1 */
+#define NIC0_RXE0_DBG_INV_OP_1_DBG_INV_OP_QPN_SHIFT 0
+#define NIC0_RXE0_DBG_INV_OP_1_DBG_INV_OP_QPN_MASK 0xFFFFFF
+#define NIC0_RXE0_DBG_INV_OP_1_DBG_INV_OP_OPCODE_SHIFT 24
+#define NIC0_RXE0_DBG_INV_OP_1_DBG_INV_OP_OPCODE_MASK 0xFF000000
+
+/* NIC0_RXE0_DBG_AXI_ERR */
+#define NIC0_RXE0_DBG_AXI_ERR_HBW_RRESP_ERR_WQE_LATCHED_SHIFT 0
+#define NIC0_RXE0_DBG_AXI_ERR_HBW_RRESP_ERR_WQE_LATCHED_MASK 0x1
+#define NIC0_RXE0_DBG_AXI_ERR_HBW_RRESP_ERR_FNA_LATCHED_SHIFT 16
+#define NIC0_RXE0_DBG_AXI_ERR_HBW_RRESP_ERR_FNA_LATCHED_MASK 0xFFFF0000
+
+/* NIC0_RXE0_DBG_AXI_CQE_ERR */
+#define NIC0_RXE0_DBG_AXI_CQE_ERR_DBG_HBW_BRESP_ERR_LATCHED_SHIFT 0
+#define NIC0_RXE0_DBG_AXI_CQE_ERR_DBG_HBW_BRESP_ERR_LATCHED_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_DBG_AXI_LBW_ERR */
+#define NIC0_RXE0_DBG_AXI_LBW_ERR_DBG_LBW_BRESP_ERR_LATCHED_SHIFT 0
+#define NIC0_RXE0_DBG_AXI_LBW_ERR_DBG_LBW_BRESP_ERR_LATCHED_MASK 0xFFFF
+
+/* NIC0_RXE0_DBG_EN */
+#define NIC0_RXE0_DBG_EN_VAL_SHIFT 0
+#define NIC0_RXE0_DBG_EN_VAL_MASK 0x1
+
+/* NIC0_RXE0_DBG_CQ_ARM_ON */
+#define NIC0_RXE0_DBG_CQ_ARM_ON_STATE_SHIFT 0
+#define NIC0_RXE0_DBG_CQ_ARM_ON_STATE_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_DBG_CQ_ARM_SEL */
+#define NIC0_RXE0_DBG_CQ_ARM_SEL_VAL_SHIFT 0
+#define NIC0_RXE0_DBG_CQ_ARM_SEL_VAL_MASK 0x1F
+
+/* NIC0_RXE0_DBG_CQ_ARM_IDX */
+#define NIC0_RXE0_DBG_CQ_ARM_IDX_VAL_SHIFT 0
+#define NIC0_RXE0_DBG_CQ_ARM_IDX_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_RXE0_DBG_SLICE_MAIN */
+#define NIC0_RXE0_DBG_SLICE_MAIN_PQ_OCCUPANCY_SHIFT 0
+#define NIC0_RXE0_DBG_SLICE_MAIN_PQ_OCCUPANCY_MASK 0x1F
+#define NIC0_RXE0_DBG_SLICE_MAIN_MAIN_OCCUPANCY_SHIFT 5
+#define NIC0_RXE0_DBG_SLICE_MAIN_MAIN_OCCUPANCY_MASK 0x3E0
+#define NIC0_RXE0_DBG_SLICE_MAIN_SLICE_SEL_SHIFT 10
+#define NIC0_RXE0_DBG_SLICE_MAIN_SLICE_SEL_MASK 0x3C00
+#define NIC0_RXE0_DBG_SLICE_MAIN_MAIN_SLICE_STATE_SHIFT 14
+#define NIC0_RXE0_DBG_SLICE_MAIN_MAIN_SLICE_STATE_MASK 0x7C000
+#define NIC0_RXE0_DBG_SLICE_MAIN_WQE_SLICE_STATE_SHIFT 19
+#define NIC0_RXE0_DBG_SLICE_MAIN_WQE_SLICE_STATE_MASK 0x380000
+
+/* NIC0_RXE0_DBG_SLICE_SCT */
+#define NIC0_RXE0_DBG_SLICE_SCT_SQ_OCCUPANCY_SHIFT 0
+#define NIC0_RXE0_DBG_SLICE_SCT_SQ_OCCUPANCY_MASK 0x1F
+#define NIC0_RXE0_DBG_SLICE_SCT_SLICE_SEL_SHIFT 5
+#define NIC0_RXE0_DBG_SLICE_SCT_SLICE_SEL_MASK 0x1E0
+#define NIC0_RXE0_DBG_SLICE_SCT_SCT_SLICE_STATE_SHIFT 9
+#define NIC0_RXE0_DBG_SLICE_SCT_SCT_SLICE_STATE_MASK 0x600
+
+#endif /* ASIC_REG_NIC0_RXE0_MASKS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_regs.h
new file mode 100644
index 000000000000..05d7963ca6b4
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_regs.h
@@ -0,0 +1,725 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_RXE0_REGS_H_
+#define ASIC_REG_NIC0_RXE0_REGS_H_
+
+/*****************************************
+ * NIC0_RXE0
+ * (Prototype: NIC_RXE)
+ *****************************************
+ */
+
+#define NIC0_RXE0_CONTROL 0x544A000
+
+#define NIC0_RXE0_SCATTER_CFG 0x544A004
+
+#define NIC0_RXE0_SCATTER_CQ_ADDR 0x544A008
+
+#define NIC0_RXE0_RAW_QPN_P0_0 0x544A010
+
+#define NIC0_RXE0_RAW_QPN_P0_1 0x544A014
+
+#define NIC0_RXE0_RAW_QPN_P1_0 0x544A018
+
+#define NIC0_RXE0_RAW_QPN_P1_1 0x544A01C
+
+#define NIC0_RXE0_RAW_QPN_P2_0 0x544A020
+
+#define NIC0_RXE0_RAW_QPN_P2_1 0x544A024
+
+#define NIC0_RXE0_RAW_QPN_P3_0 0x544A028
+
+#define NIC0_RXE0_RAW_QPN_P3_1 0x544A02C
+
+#define NIC0_RXE0_RXE_CHECKS 0x544A030
+
+#define NIC0_RXE0_PKT_DROP 0x544A034
+
+#define NIC0_RXE0_PKT_SIZE_CHECK_RC 0x544A038
+
+#define NIC0_RXE0_PKT_SIZE_CHECK_RAW 0x544A03C
+
+#define NIC0_RXE0_ARUSER_MMU_BP 0x544A064
+
+#define NIC0_RXE0_AWUSER_LBW 0x544A068
+
+#define NIC0_RXE0_ARPROT_HBW 0x544A070
+
+#define NIC0_RXE0_AWPROT_LBW 0x544A074
+
+#define NIC0_RXE0_WIN0_WQ_BASE_LO 0x544A080
+
+#define NIC0_RXE0_WIN0_WQ_BASE_HI 0x544A084
+
+#define NIC0_RXE0_WIN0_WQ_MISC 0x544A088
+
+#define NIC0_RXE0_WIN1_WQ_BASE_LO 0x544A090
+
+#define NIC0_RXE0_WIN1_WQ_BASE_HI 0x544A094
+
+#define NIC0_RXE0_WIN1_WQ_MISC 0x544A098
+
+#define NIC0_RXE0_WIN2_WQ_BASE_LO 0x544A0A0
+
+#define NIC0_RXE0_WIN2_WQ_BASE_HI 0x544A0A4
+
+#define NIC0_RXE0_WIN2_WQ_MISC 0x544A0A8
+
+#define NIC0_RXE0_WIN3_WQ_BASE_LO 0x544A0B0
+
+#define NIC0_RXE0_WIN3_WQ_BASE_HI 0x544A0B4
+
+#define NIC0_RXE0_WIN3_WQ_MISC 0x544A0B8
+
+#define NIC0_RXE0_CG 0x544A0D0
+
+#define NIC0_RXE0_CG_TIMER 0x544A0D4
+
+#define NIC0_RXE0_WQE_WQ_WR_OP_DISABLE 0x544A0D8
+
+#define NIC0_RXE0_WQE_WQ_RDV_OP_DISABLE 0x544A0DC
+
+#define NIC0_RXE0_WQE_WQ_RD_OP_DISABLE 0x544A0E0
+
+#define NIC0_RXE0_WQE_MAX_WRITE_SEND_SIZE 0x544A0E4
+
+#define NIC0_RXE0_WQE_MAX_MULTI_STRIDE_SIZE 0x544A0E8
+
+#define NIC0_RXE0_CACHE_CFG 0x544A0F0
+
+#define NIC0_RXE0_CACHE_INFO 0x544A0F4
+
+#define NIC0_RXE0_CACHE_ADDR_LO 0x544A0F8
+
+#define NIC0_RXE0_CACHE_ADDR_HI 0x544A0FC
+
+#define NIC0_RXE0_CQ_BASE_ADDR_31_7 0x544A100
+
+#define NIC0_RXE0_CQ_BASE_ADDR_63_32 0x544A104
+
+#define NIC0_RXE0_CQ_LOG_MAX_SIZE 0x544A108
+
+#define NIC0_RXE0_CQ_ARM_TIMEOUT_EN 0x544A110
+
+#define NIC0_RXE0_CQ_ARM_TIMEOUT 0x544A114
+
+#define NIC0_RXE0_CQ_CFG_0 0x544A180
+
+#define NIC0_RXE0_CQ_CFG_1 0x544A184
+
+#define NIC0_RXE0_CQ_CFG_2 0x544A188
+
+#define NIC0_RXE0_CQ_CFG_3 0x544A18C
+
+#define NIC0_RXE0_CQ_CFG_4 0x544A190
+
+#define NIC0_RXE0_CQ_CFG_5 0x544A194
+
+#define NIC0_RXE0_CQ_CFG_6 0x544A198
+
+#define NIC0_RXE0_CQ_CFG_7 0x544A19C
+
+#define NIC0_RXE0_CQ_CFG_8 0x544A1A0
+
+#define NIC0_RXE0_CQ_CFG_9 0x544A1A4
+
+#define NIC0_RXE0_CQ_CFG_10 0x544A1A8
+
+#define NIC0_RXE0_CQ_CFG_11 0x544A1AC
+
+#define NIC0_RXE0_CQ_CFG_12 0x544A1B0
+
+#define NIC0_RXE0_CQ_CFG_13 0x544A1B4
+
+#define NIC0_RXE0_CQ_CFG_14 0x544A1B8
+
+#define NIC0_RXE0_CQ_CFG_15 0x544A1BC
+
+#define NIC0_RXE0_CQ_CFG_16 0x544A1C0
+
+#define NIC0_RXE0_CQ_CFG_17 0x544A1C4
+
+#define NIC0_RXE0_CQ_CFG_18 0x544A1C8
+
+#define NIC0_RXE0_CQ_CFG_19 0x544A1CC
+
+#define NIC0_RXE0_CQ_CFG_20 0x544A1D0
+
+#define NIC0_RXE0_CQ_CFG_21 0x544A1D4
+
+#define NIC0_RXE0_CQ_CFG_22 0x544A1D8
+
+#define NIC0_RXE0_CQ_CFG_23 0x544A1DC
+
+#define NIC0_RXE0_CQ_CFG_24 0x544A1E0
+
+#define NIC0_RXE0_CQ_CFG_25 0x544A1E4
+
+#define NIC0_RXE0_CQ_CFG_26 0x544A1E8
+
+#define NIC0_RXE0_CQ_CFG_27 0x544A1EC
+
+#define NIC0_RXE0_CQ_CFG_28 0x544A1F0
+
+#define NIC0_RXE0_CQ_CFG_29 0x544A1F4
+
+#define NIC0_RXE0_CQ_CFG_30 0x544A1F8
+
+#define NIC0_RXE0_CQ_CFG_31 0x544A1FC
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_0 0x544A200
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_1 0x544A204
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_2 0x544A208
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_3 0x544A20C
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_4 0x544A210
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_5 0x544A214
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_6 0x544A218
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_7 0x544A21C
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_8 0x544A220
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_9 0x544A224
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_10 0x544A228
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_11 0x544A22C
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_12 0x544A230
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_13 0x544A234
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_14 0x544A238
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_15 0x544A23C
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_16 0x544A240
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_17 0x544A244
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_18 0x544A248
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_19 0x544A24C
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_20 0x544A250
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_21 0x544A254
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_22 0x544A258
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_23 0x544A25C
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_24 0x544A260
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_25 0x544A264
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_26 0x544A268
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_27 0x544A26C
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_28 0x544A270
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_29 0x544A274
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_30 0x544A278
+
+#define NIC0_RXE0_CQ_WRITE_INDEX_31 0x544A27C
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_0 0x544A280
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_1 0x544A284
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_2 0x544A288
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_3 0x544A28C
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_4 0x544A290
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_5 0x544A294
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_6 0x544A298
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_7 0x544A29C
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_8 0x544A2A0
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_9 0x544A2A4
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_10 0x544A2A8
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_11 0x544A2AC
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_12 0x544A2B0
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_13 0x544A2B4
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_14 0x544A2B8
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_15 0x544A2BC
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_16 0x544A2C0
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_17 0x544A2C4
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_18 0x544A2C8
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_19 0x544A2CC
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_20 0x544A2D0
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_21 0x544A2D4
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_22 0x544A2D8
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_23 0x544A2DC
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_24 0x544A2E0
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_25 0x544A2E4
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_26 0x544A2E8
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_27 0x544A2EC
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_28 0x544A2F0
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_29 0x544A2F4
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_30 0x544A2F8
+
+#define NIC0_RXE0_CQ_PRODUCER_INDEX_31 0x544A2FC
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_0 0x544A300
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_1 0x544A304
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_2 0x544A308
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_3 0x544A30C
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_4 0x544A310
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_5 0x544A314
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_6 0x544A318
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_7 0x544A31C
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_8 0x544A320
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_9 0x544A324
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_10 0x544A328
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_11 0x544A32C
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_12 0x544A330
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_13 0x544A334
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_14 0x544A338
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_15 0x544A33C
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_16 0x544A340
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_17 0x544A344
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_18 0x544A348
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_19 0x544A34C
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_20 0x544A350
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_21 0x544A354
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_22 0x544A358
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_23 0x544A35C
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_24 0x544A360
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_25 0x544A364
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_26 0x544A368
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_27 0x544A36C
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_28 0x544A370
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_29 0x544A374
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_30 0x544A378
+
+#define NIC0_RXE0_CQ_CONSUMER_INDEX_31 0x544A37C
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_0 0x544A380
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_1 0x544A384
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_2 0x544A388
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_3 0x544A38C
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_4 0x544A390
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_5 0x544A394
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_6 0x544A398
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_7 0x544A39C
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_8 0x544A3A0
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_9 0x544A3A4
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_10 0x544A3A8
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_11 0x544A3AC
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_12 0x544A3B0
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_13 0x544A3B4
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_14 0x544A3B8
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_15 0x544A3BC
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_16 0x544A3C0
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_17 0x544A3C4
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_18 0x544A3C8
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_19 0x544A3CC
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_20 0x544A3D0
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_21 0x544A3D4
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_22 0x544A3D8
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_23 0x544A3DC
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_24 0x544A3E0
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_25 0x544A3E4
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_26 0x544A3E8
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_27 0x544A3EC
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_28 0x544A3F0
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_29 0x544A3F4
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_30 0x544A3F8
+
+#define NIC0_RXE0_CQ_PI_ADDR_LO_31 0x544A3FC
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_0 0x544A400
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_1 0x544A404
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_2 0x544A408
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_3 0x544A40C
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_4 0x544A410
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_5 0x544A414
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_6 0x544A418
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_7 0x544A41C
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_8 0x544A420
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_9 0x544A424
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_10 0x544A428
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_11 0x544A42C
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_12 0x544A430
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_13 0x544A434
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_14 0x544A438
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_15 0x544A43C
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_16 0x544A440
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_17 0x544A444
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_18 0x544A448
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_19 0x544A44C
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_20 0x544A450
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_21 0x544A454
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_22 0x544A458
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_23 0x544A45C
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_24 0x544A460
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_25 0x544A464
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_26 0x544A468
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_27 0x544A46C
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_28 0x544A470
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_29 0x544A474
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_30 0x544A478
+
+#define NIC0_RXE0_CQ_PI_ADDR_HI_31 0x544A47C
+
+#define NIC0_RXE0_CQ_AXI_PROT_0 0x544A480
+
+#define NIC0_RXE0_CQ_AXI_PROT_1 0x544A484
+
+#define NIC0_RXE0_CQ_AXI_PROT_2 0x544A488
+
+#define NIC0_RXE0_CQ_AXI_PROT_3 0x544A48C
+
+#define NIC0_RXE0_CQ_AXI_PROT_4 0x544A490
+
+#define NIC0_RXE0_CQ_AXI_PROT_5 0x544A494
+
+#define NIC0_RXE0_CQ_AXI_PROT_6 0x544A498
+
+#define NIC0_RXE0_CQ_AXI_PROT_7 0x544A49C
+
+#define NIC0_RXE0_CQ_AXI_PROT_8 0x544A4A0
+
+#define NIC0_RXE0_CQ_AXI_PROT_9 0x544A4A4
+
+#define NIC0_RXE0_CQ_AXI_PROT_10 0x544A4A8
+
+#define NIC0_RXE0_CQ_AXI_PROT_11 0x544A4AC
+
+#define NIC0_RXE0_CQ_AXI_PROT_12 0x544A4B0
+
+#define NIC0_RXE0_CQ_AXI_PROT_13 0x544A4B4
+
+#define NIC0_RXE0_CQ_AXI_PROT_14 0x544A4B8
+
+#define NIC0_RXE0_CQ_AXI_PROT_15 0x544A4BC
+
+#define NIC0_RXE0_CQ_AXI_PROT_16 0x544A4C0
+
+#define NIC0_RXE0_CQ_AXI_PROT_17 0x544A4C4
+
+#define NIC0_RXE0_CQ_AXI_PROT_18 0x544A4C8
+
+#define NIC0_RXE0_CQ_AXI_PROT_19 0x544A4CC
+
+#define NIC0_RXE0_CQ_AXI_PROT_20 0x544A4D0
+
+#define NIC0_RXE0_CQ_AXI_PROT_21 0x544A4D4
+
+#define NIC0_RXE0_CQ_AXI_PROT_22 0x544A4D8
+
+#define NIC0_RXE0_CQ_AXI_PROT_23 0x544A4DC
+
+#define NIC0_RXE0_CQ_AXI_PROT_24 0x544A4E0
+
+#define NIC0_RXE0_CQ_AXI_PROT_25 0x544A4E4
+
+#define NIC0_RXE0_CQ_AXI_PROT_26 0x544A4E8
+
+#define NIC0_RXE0_CQ_AXI_PROT_27 0x544A4EC
+
+#define NIC0_RXE0_CQ_AXI_PROT_28 0x544A4F0
+
+#define NIC0_RXE0_CQ_AXI_PROT_29 0x544A4F4
+
+#define NIC0_RXE0_CQ_AXI_PROT_30 0x544A4F8
+
+#define NIC0_RXE0_CQ_AXI_PROT_31 0x544A4FC
+
+#define NIC0_RXE0_CQ_LOG_SIZE_0 0x544A500
+
+#define NIC0_RXE0_CQ_LOG_SIZE_1 0x544A504
+
+#define NIC0_RXE0_CQ_LOG_SIZE_2 0x544A508
+
+#define NIC0_RXE0_CQ_LOG_SIZE_3 0x544A50C
+
+#define NIC0_RXE0_CQ_LOG_SIZE_4 0x544A510
+
+#define NIC0_RXE0_CQ_LOG_SIZE_5 0x544A514
+
+#define NIC0_RXE0_CQ_LOG_SIZE_6 0x544A518
+
+#define NIC0_RXE0_CQ_LOG_SIZE_7 0x544A51C
+
+#define NIC0_RXE0_CQ_LOG_SIZE_8 0x544A520
+
+#define NIC0_RXE0_CQ_LOG_SIZE_9 0x544A524
+
+#define NIC0_RXE0_CQ_LOG_SIZE_10 0x544A528
+
+#define NIC0_RXE0_CQ_LOG_SIZE_11 0x544A52C
+
+#define NIC0_RXE0_CQ_LOG_SIZE_12 0x544A530
+
+#define NIC0_RXE0_CQ_LOG_SIZE_13 0x544A534
+
+#define NIC0_RXE0_CQ_LOG_SIZE_14 0x544A538
+
+#define NIC0_RXE0_CQ_LOG_SIZE_15 0x544A53C
+
+#define NIC0_RXE0_CQ_LOG_SIZE_16 0x544A540
+
+#define NIC0_RXE0_CQ_LOG_SIZE_17 0x544A544
+
+#define NIC0_RXE0_CQ_LOG_SIZE_18 0x544A548
+
+#define NIC0_RXE0_CQ_LOG_SIZE_19 0x544A54C
+
+#define NIC0_RXE0_CQ_LOG_SIZE_20 0x544A550
+
+#define NIC0_RXE0_CQ_LOG_SIZE_21 0x544A554
+
+#define NIC0_RXE0_CQ_LOG_SIZE_22 0x544A558
+
+#define NIC0_RXE0_CQ_LOG_SIZE_23 0x544A55C
+
+#define NIC0_RXE0_CQ_LOG_SIZE_24 0x544A560
+
+#define NIC0_RXE0_CQ_LOG_SIZE_25 0x544A564
+
+#define NIC0_RXE0_CQ_LOG_SIZE_26 0x544A568
+
+#define NIC0_RXE0_CQ_LOG_SIZE_27 0x544A56C
+
+#define NIC0_RXE0_CQ_LOG_SIZE_28 0x544A570
+
+#define NIC0_RXE0_CQ_LOG_SIZE_29 0x544A574
+
+#define NIC0_RXE0_CQ_LOG_SIZE_30 0x544A578
+
+#define NIC0_RXE0_CQ_LOG_SIZE_31 0x544A57C
+
+#define NIC0_RXE0_RDV_SEND_WQ_BASE_ADDR_LO 0x544A600
+
+#define NIC0_RXE0_RDV_SEND_WQ_BASE_ADDR_HI 0x544A604
+
+#define NIC0_RXE0_RDV_LOG_MAX_WQ_SIZE 0x544A608
+
+#define NIC0_RXE0_LBW_BASE_LO 0x544A700
+
+#define NIC0_RXE0_LBW_BASE_HI 0x544A704
+
+#define NIC0_RXE0_LBW_LOG_SIZE 0x544A708
+
+#define NIC0_RXE0_RAW_BASE_LO_P0_0 0x544A710
+
+#define NIC0_RXE0_RAW_BASE_LO_P0_1 0x544A714
+
+#define NIC0_RXE0_RAW_BASE_HI_P0_0 0x544A720
+
+#define NIC0_RXE0_RAW_BASE_HI_P0_1 0x544A724
+
+#define NIC0_RXE0_RAW_MISC_P0_0 0x544A730
+
+#define NIC0_RXE0_RAW_MISC_P0_1 0x544A734
+
+#define NIC0_RXE0_RAW_BASE_LO_P1_0 0x544A750
+
+#define NIC0_RXE0_RAW_BASE_LO_P1_1 0x544A754
+
+#define NIC0_RXE0_RAW_BASE_HI_P1_0 0x544A760
+
+#define NIC0_RXE0_RAW_BASE_HI_P1_1 0x544A764
+
+#define NIC0_RXE0_RAW_MISC_P1_0 0x544A770
+
+#define NIC0_RXE0_RAW_MISC_P1_1 0x544A774
+
+#define NIC0_RXE0_RAW_BASE_LO_P2_0 0x544A790
+
+#define NIC0_RXE0_RAW_BASE_LO_P2_1 0x544A794
+
+#define NIC0_RXE0_RAW_BASE_HI_P2_0 0x544A7A0
+
+#define NIC0_RXE0_RAW_BASE_HI_P2_1 0x544A7A4
+
+#define NIC0_RXE0_RAW_MISC_P2_0 0x544A7B0
+
+#define NIC0_RXE0_RAW_MISC_P2_1 0x544A7B4
+
+#define NIC0_RXE0_RAW_BASE_LO_P3_0 0x544A7D0
+
+#define NIC0_RXE0_RAW_BASE_LO_P3_1 0x544A7D4
+
+#define NIC0_RXE0_RAW_BASE_HI_P3_0 0x544A7E0
+
+#define NIC0_RXE0_RAW_BASE_HI_P3_1 0x544A7E4
+
+#define NIC0_RXE0_RAW_MISC_P3_0 0x544A7F0
+
+#define NIC0_RXE0_RAW_MISC_P3_1 0x544A7F4
+
+#define NIC0_RXE0_SEI_INTR_CAUSE 0x544A800
+
+#define NIC0_RXE0_SEI_INTR_MASK 0x544A804
+
+#define NIC0_RXE0_SEI_INTR_CLEAR 0x544A808
+
+#define NIC0_RXE0_SPI_INTR_CAUSE 0x544A810
+
+#define NIC0_RXE0_SPI_INTR_MASK 0x544A814
+
+#define NIC0_RXE0_SPI_INTR_CLEAR 0x544A818
+
+#define NIC0_RXE0_DBG_SPMU_SELECT 0x544AA00
+
+#define NIC0_RXE0_DBG_INV_OP_0 0x544AA04
+
+#define NIC0_RXE0_DBG_INV_OP_1 0x544AA08
+
+#define NIC0_RXE0_DBG_AXI_ERR 0x544AA0C
+
+#define NIC0_RXE0_DBG_AXI_CQE_ERR 0x544AA10
+
+#define NIC0_RXE0_DBG_AXI_LBW_ERR 0x544AA14
+
+#define NIC0_RXE0_DBG_EN 0x544AA18
+
+#define NIC0_RXE0_DBG_CQ_ARM_ON 0x544AA1C
+
+#define NIC0_RXE0_DBG_CQ_ARM_SEL 0x544AA20
+
+#define NIC0_RXE0_DBG_CQ_ARM_IDX 0x544AA24
+
+#define NIC0_RXE0_DBG_SLICE_MAIN 0x544AA28
+
+#define NIC0_RXE0_DBG_SLICE_SCT 0x544AA2C
+
+#endif /* ASIC_REG_NIC0_RXE0_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_wqe_aruser_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_wqe_aruser_regs.h
new file mode 100644
index 000000000000..925ffb89e46f
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_wqe_aruser_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_RXE0_WQE_ARUSER_REGS_H_
+#define ASIC_REG_NIC0_RXE0_WQE_ARUSER_REGS_H_
+
+/*****************************************
+ * NIC0_RXE0_WQE_ARUSER
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_RXE0_WQE_ARUSER_HB_ASID 0x544A900
+
+#define NIC0_RXE0_WQE_ARUSER_HB_MMU_BP 0x544A904
+
+#define NIC0_RXE0_WQE_ARUSER_HB_STRONG_ORDER 0x544A908
+
+#define NIC0_RXE0_WQE_ARUSER_HB_NO_SNOOP 0x544A90C
+
+#define NIC0_RXE0_WQE_ARUSER_HB_WR_REDUCTION 0x544A910
+
+#define NIC0_RXE0_WQE_ARUSER_HB_RD_ATOMIC 0x544A914
+
+#define NIC0_RXE0_WQE_ARUSER_HB_QOS 0x544A918
+
+#define NIC0_RXE0_WQE_ARUSER_HB_RSVD 0x544A91C
+
+#define NIC0_RXE0_WQE_ARUSER_HB_EMEM_CPAGE 0x544A920
+
+#define NIC0_RXE0_WQE_ARUSER_HB_CORE 0x544A924
+
+#define NIC0_RXE0_WQE_ARUSER_E2E_COORD 0x544A928
+
+#define NIC0_RXE0_WQE_ARUSER_HB_WR_OVRD_LO 0x544A930
+
+#define NIC0_RXE0_WQE_ARUSER_HB_WR_OVRD_HI 0x544A934
+
+#define NIC0_RXE0_WQE_ARUSER_HB_RD_OVRD_LO 0x544A938
+
+#define NIC0_RXE0_WQE_ARUSER_HB_RD_OVRD_HI 0x544A93C
+
+#define NIC0_RXE0_WQE_ARUSER_LB_COORD 0x544A940
+
+#define NIC0_RXE0_WQE_ARUSER_LB_LOCK 0x544A944
+
+#define NIC0_RXE0_WQE_ARUSER_LB_RSVD 0x544A948
+
+#define NIC0_RXE0_WQE_ARUSER_LB_OVRD 0x544A94C
+
+#endif /* ASIC_REG_NIC0_RXE0_WQE_ARUSER_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe1_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe1_regs.h
new file mode 100644
index 000000000000..e1228f2bd0ee
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe1_regs.h
@@ -0,0 +1,725 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_RXE1_REGS_H_
+#define ASIC_REG_NIC0_RXE1_REGS_H_
+
+/*****************************************
+ * NIC0_RXE1
+ * (Prototype: NIC_RXE)
+ *****************************************
+ */
+
+#define NIC0_RXE1_CONTROL 0x544B000
+
+#define NIC0_RXE1_SCATTER_CFG 0x544B004
+
+#define NIC0_RXE1_SCATTER_CQ_ADDR 0x544B008
+
+#define NIC0_RXE1_RAW_QPN_P0_0 0x544B010
+
+#define NIC0_RXE1_RAW_QPN_P0_1 0x544B014
+
+#define NIC0_RXE1_RAW_QPN_P1_0 0x544B018
+
+#define NIC0_RXE1_RAW_QPN_P1_1 0x544B01C
+
+#define NIC0_RXE1_RAW_QPN_P2_0 0x544B020
+
+#define NIC0_RXE1_RAW_QPN_P2_1 0x544B024
+
+#define NIC0_RXE1_RAW_QPN_P3_0 0x544B028
+
+#define NIC0_RXE1_RAW_QPN_P3_1 0x544B02C
+
+#define NIC0_RXE1_RXE_CHECKS 0x544B030
+
+#define NIC0_RXE1_PKT_DROP 0x544B034
+
+#define NIC0_RXE1_PKT_SIZE_CHECK_RC 0x544B038
+
+#define NIC0_RXE1_PKT_SIZE_CHECK_RAW 0x544B03C
+
+#define NIC0_RXE1_ARUSER_MMU_BP 0x544B064
+
+#define NIC0_RXE1_AWUSER_LBW 0x544B068
+
+#define NIC0_RXE1_ARPROT_HBW 0x544B070
+
+#define NIC0_RXE1_AWPROT_LBW 0x544B074
+
+#define NIC0_RXE1_WIN0_WQ_BASE_LO 0x544B080
+
+#define NIC0_RXE1_WIN0_WQ_BASE_HI 0x544B084
+
+#define NIC0_RXE1_WIN0_WQ_MISC 0x544B088
+
+#define NIC0_RXE1_WIN1_WQ_BASE_LO 0x544B090
+
+#define NIC0_RXE1_WIN1_WQ_BASE_HI 0x544B094
+
+#define NIC0_RXE1_WIN1_WQ_MISC 0x544B098
+
+#define NIC0_RXE1_WIN2_WQ_BASE_LO 0x544B0A0
+
+#define NIC0_RXE1_WIN2_WQ_BASE_HI 0x544B0A4
+
+#define NIC0_RXE1_WIN2_WQ_MISC 0x544B0A8
+
+#define NIC0_RXE1_WIN3_WQ_BASE_LO 0x544B0B0
+
+#define NIC0_RXE1_WIN3_WQ_BASE_HI 0x544B0B4
+
+#define NIC0_RXE1_WIN3_WQ_MISC 0x544B0B8
+
+#define NIC0_RXE1_CG 0x544B0D0
+
+#define NIC0_RXE1_CG_TIMER 0x544B0D4
+
+#define NIC0_RXE1_WQE_WQ_WR_OP_DISABLE 0x544B0D8
+
+#define NIC0_RXE1_WQE_WQ_RDV_OP_DISABLE 0x544B0DC
+
+#define NIC0_RXE1_WQE_WQ_RD_OP_DISABLE 0x544B0E0
+
+#define NIC0_RXE1_WQE_MAX_WRITE_SEND_SIZE 0x544B0E4
+
+#define NIC0_RXE1_WQE_MAX_MULTI_STRIDE_SIZE 0x544B0E8
+
+#define NIC0_RXE1_CACHE_CFG 0x544B0F0
+
+#define NIC0_RXE1_CACHE_INFO 0x544B0F4
+
+#define NIC0_RXE1_CACHE_ADDR_LO 0x544B0F8
+
+#define NIC0_RXE1_CACHE_ADDR_HI 0x544B0FC
+
+#define NIC0_RXE1_CQ_BASE_ADDR_31_7 0x544B100
+
+#define NIC0_RXE1_CQ_BASE_ADDR_63_32 0x544B104
+
+#define NIC0_RXE1_CQ_LOG_MAX_SIZE 0x544B108
+
+#define NIC0_RXE1_CQ_ARM_TIMEOUT_EN 0x544B110
+
+#define NIC0_RXE1_CQ_ARM_TIMEOUT 0x544B114
+
+#define NIC0_RXE1_CQ_CFG_0 0x544B180
+
+#define NIC0_RXE1_CQ_CFG_1 0x544B184
+
+#define NIC0_RXE1_CQ_CFG_2 0x544B188
+
+#define NIC0_RXE1_CQ_CFG_3 0x544B18C
+
+#define NIC0_RXE1_CQ_CFG_4 0x544B190
+
+#define NIC0_RXE1_CQ_CFG_5 0x544B194
+
+#define NIC0_RXE1_CQ_CFG_6 0x544B198
+
+#define NIC0_RXE1_CQ_CFG_7 0x544B19C
+
+#define NIC0_RXE1_CQ_CFG_8 0x544B1A0
+
+#define NIC0_RXE1_CQ_CFG_9 0x544B1A4
+
+#define NIC0_RXE1_CQ_CFG_10 0x544B1A8
+
+#define NIC0_RXE1_CQ_CFG_11 0x544B1AC
+
+#define NIC0_RXE1_CQ_CFG_12 0x544B1B0
+
+#define NIC0_RXE1_CQ_CFG_13 0x544B1B4
+
+#define NIC0_RXE1_CQ_CFG_14 0x544B1B8
+
+#define NIC0_RXE1_CQ_CFG_15 0x544B1BC
+
+#define NIC0_RXE1_CQ_CFG_16 0x544B1C0
+
+#define NIC0_RXE1_CQ_CFG_17 0x544B1C4
+
+#define NIC0_RXE1_CQ_CFG_18 0x544B1C8
+
+#define NIC0_RXE1_CQ_CFG_19 0x544B1CC
+
+#define NIC0_RXE1_CQ_CFG_20 0x544B1D0
+
+#define NIC0_RXE1_CQ_CFG_21 0x544B1D4
+
+#define NIC0_RXE1_CQ_CFG_22 0x544B1D8
+
+#define NIC0_RXE1_CQ_CFG_23 0x544B1DC
+
+#define NIC0_RXE1_CQ_CFG_24 0x544B1E0
+
+#define NIC0_RXE1_CQ_CFG_25 0x544B1E4
+
+#define NIC0_RXE1_CQ_CFG_26 0x544B1E8
+
+#define NIC0_RXE1_CQ_CFG_27 0x544B1EC
+
+#define NIC0_RXE1_CQ_CFG_28 0x544B1F0
+
+#define NIC0_RXE1_CQ_CFG_29 0x544B1F4
+
+#define NIC0_RXE1_CQ_CFG_30 0x544B1F8
+
+#define NIC0_RXE1_CQ_CFG_31 0x544B1FC
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_0 0x544B200
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_1 0x544B204
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_2 0x544B208
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_3 0x544B20C
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_4 0x544B210
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_5 0x544B214
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_6 0x544B218
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_7 0x544B21C
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_8 0x544B220
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_9 0x544B224
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_10 0x544B228
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_11 0x544B22C
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_12 0x544B230
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_13 0x544B234
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_14 0x544B238
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_15 0x544B23C
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_16 0x544B240
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_17 0x544B244
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_18 0x544B248
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_19 0x544B24C
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_20 0x544B250
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_21 0x544B254
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_22 0x544B258
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_23 0x544B25C
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_24 0x544B260
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_25 0x544B264
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_26 0x544B268
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_27 0x544B26C
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_28 0x544B270
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_29 0x544B274
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_30 0x544B278
+
+#define NIC0_RXE1_CQ_WRITE_INDEX_31 0x544B27C
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_0 0x544B280
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_1 0x544B284
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_2 0x544B288
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_3 0x544B28C
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_4 0x544B290
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_5 0x544B294
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_6 0x544B298
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_7 0x544B29C
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_8 0x544B2A0
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_9 0x544B2A4
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_10 0x544B2A8
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_11 0x544B2AC
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_12 0x544B2B0
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_13 0x544B2B4
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_14 0x544B2B8
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_15 0x544B2BC
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_16 0x544B2C0
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_17 0x544B2C4
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_18 0x544B2C8
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_19 0x544B2CC
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_20 0x544B2D0
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_21 0x544B2D4
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_22 0x544B2D8
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_23 0x544B2DC
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_24 0x544B2E0
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_25 0x544B2E4
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_26 0x544B2E8
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_27 0x544B2EC
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_28 0x544B2F0
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_29 0x544B2F4
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_30 0x544B2F8
+
+#define NIC0_RXE1_CQ_PRODUCER_INDEX_31 0x544B2FC
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_0 0x544B300
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_1 0x544B304
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_2 0x544B308
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_3 0x544B30C
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_4 0x544B310
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_5 0x544B314
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_6 0x544B318
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_7 0x544B31C
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_8 0x544B320
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_9 0x544B324
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_10 0x544B328
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_11 0x544B32C
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_12 0x544B330
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_13 0x544B334
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_14 0x544B338
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_15 0x544B33C
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_16 0x544B340
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_17 0x544B344
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_18 0x544B348
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_19 0x544B34C
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_20 0x544B350
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_21 0x544B354
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_22 0x544B358
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_23 0x544B35C
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_24 0x544B360
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_25 0x544B364
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_26 0x544B368
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_27 0x544B36C
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_28 0x544B370
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_29 0x544B374
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_30 0x544B378
+
+#define NIC0_RXE1_CQ_CONSUMER_INDEX_31 0x544B37C
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_0 0x544B380
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_1 0x544B384
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_2 0x544B388
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_3 0x544B38C
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_4 0x544B390
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_5 0x544B394
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_6 0x544B398
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_7 0x544B39C
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_8 0x544B3A0
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_9 0x544B3A4
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_10 0x544B3A8
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_11 0x544B3AC
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_12 0x544B3B0
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_13 0x544B3B4
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_14 0x544B3B8
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_15 0x544B3BC
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_16 0x544B3C0
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_17 0x544B3C4
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_18 0x544B3C8
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_19 0x544B3CC
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_20 0x544B3D0
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_21 0x544B3D4
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_22 0x544B3D8
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_23 0x544B3DC
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_24 0x544B3E0
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_25 0x544B3E4
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_26 0x544B3E8
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_27 0x544B3EC
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_28 0x544B3F0
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_29 0x544B3F4
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_30 0x544B3F8
+
+#define NIC0_RXE1_CQ_PI_ADDR_LO_31 0x544B3FC
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_0 0x544B400
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_1 0x544B404
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_2 0x544B408
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_3 0x544B40C
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_4 0x544B410
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_5 0x544B414
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_6 0x544B418
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_7 0x544B41C
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_8 0x544B420
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_9 0x544B424
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_10 0x544B428
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_11 0x544B42C
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_12 0x544B430
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_13 0x544B434
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_14 0x544B438
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_15 0x544B43C
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_16 0x544B440
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_17 0x544B444
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_18 0x544B448
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_19 0x544B44C
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_20 0x544B450
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_21 0x544B454
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_22 0x544B458
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_23 0x544B45C
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_24 0x544B460
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_25 0x544B464
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_26 0x544B468
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_27 0x544B46C
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_28 0x544B470
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_29 0x544B474
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_30 0x544B478
+
+#define NIC0_RXE1_CQ_PI_ADDR_HI_31 0x544B47C
+
+#define NIC0_RXE1_CQ_AXI_PROT_0 0x544B480
+
+#define NIC0_RXE1_CQ_AXI_PROT_1 0x544B484
+
+#define NIC0_RXE1_CQ_AXI_PROT_2 0x544B488
+
+#define NIC0_RXE1_CQ_AXI_PROT_3 0x544B48C
+
+#define NIC0_RXE1_CQ_AXI_PROT_4 0x544B490
+
+#define NIC0_RXE1_CQ_AXI_PROT_5 0x544B494
+
+#define NIC0_RXE1_CQ_AXI_PROT_6 0x544B498
+
+#define NIC0_RXE1_CQ_AXI_PROT_7 0x544B49C
+
+#define NIC0_RXE1_CQ_AXI_PROT_8 0x544B4A0
+
+#define NIC0_RXE1_CQ_AXI_PROT_9 0x544B4A4
+
+#define NIC0_RXE1_CQ_AXI_PROT_10 0x544B4A8
+
+#define NIC0_RXE1_CQ_AXI_PROT_11 0x544B4AC
+
+#define NIC0_RXE1_CQ_AXI_PROT_12 0x544B4B0
+
+#define NIC0_RXE1_CQ_AXI_PROT_13 0x544B4B4
+
+#define NIC0_RXE1_CQ_AXI_PROT_14 0x544B4B8
+
+#define NIC0_RXE1_CQ_AXI_PROT_15 0x544B4BC
+
+#define NIC0_RXE1_CQ_AXI_PROT_16 0x544B4C0
+
+#define NIC0_RXE1_CQ_AXI_PROT_17 0x544B4C4
+
+#define NIC0_RXE1_CQ_AXI_PROT_18 0x544B4C8
+
+#define NIC0_RXE1_CQ_AXI_PROT_19 0x544B4CC
+
+#define NIC0_RXE1_CQ_AXI_PROT_20 0x544B4D0
+
+#define NIC0_RXE1_CQ_AXI_PROT_21 0x544B4D4
+
+#define NIC0_RXE1_CQ_AXI_PROT_22 0x544B4D8
+
+#define NIC0_RXE1_CQ_AXI_PROT_23 0x544B4DC
+
+#define NIC0_RXE1_CQ_AXI_PROT_24 0x544B4E0
+
+#define NIC0_RXE1_CQ_AXI_PROT_25 0x544B4E4
+
+#define NIC0_RXE1_CQ_AXI_PROT_26 0x544B4E8
+
+#define NIC0_RXE1_CQ_AXI_PROT_27 0x544B4EC
+
+#define NIC0_RXE1_CQ_AXI_PROT_28 0x544B4F0
+
+#define NIC0_RXE1_CQ_AXI_PROT_29 0x544B4F4
+
+#define NIC0_RXE1_CQ_AXI_PROT_30 0x544B4F8
+
+#define NIC0_RXE1_CQ_AXI_PROT_31 0x544B4FC
+
+#define NIC0_RXE1_CQ_LOG_SIZE_0 0x544B500
+
+#define NIC0_RXE1_CQ_LOG_SIZE_1 0x544B504
+
+#define NIC0_RXE1_CQ_LOG_SIZE_2 0x544B508
+
+#define NIC0_RXE1_CQ_LOG_SIZE_3 0x544B50C
+
+#define NIC0_RXE1_CQ_LOG_SIZE_4 0x544B510
+
+#define NIC0_RXE1_CQ_LOG_SIZE_5 0x544B514
+
+#define NIC0_RXE1_CQ_LOG_SIZE_6 0x544B518
+
+#define NIC0_RXE1_CQ_LOG_SIZE_7 0x544B51C
+
+#define NIC0_RXE1_CQ_LOG_SIZE_8 0x544B520
+
+#define NIC0_RXE1_CQ_LOG_SIZE_9 0x544B524
+
+#define NIC0_RXE1_CQ_LOG_SIZE_10 0x544B528
+
+#define NIC0_RXE1_CQ_LOG_SIZE_11 0x544B52C
+
+#define NIC0_RXE1_CQ_LOG_SIZE_12 0x544B530
+
+#define NIC0_RXE1_CQ_LOG_SIZE_13 0x544B534
+
+#define NIC0_RXE1_CQ_LOG_SIZE_14 0x544B538
+
+#define NIC0_RXE1_CQ_LOG_SIZE_15 0x544B53C
+
+#define NIC0_RXE1_CQ_LOG_SIZE_16 0x544B540
+
+#define NIC0_RXE1_CQ_LOG_SIZE_17 0x544B544
+
+#define NIC0_RXE1_CQ_LOG_SIZE_18 0x544B548
+
+#define NIC0_RXE1_CQ_LOG_SIZE_19 0x544B54C
+
+#define NIC0_RXE1_CQ_LOG_SIZE_20 0x544B550
+
+#define NIC0_RXE1_CQ_LOG_SIZE_21 0x544B554
+
+#define NIC0_RXE1_CQ_LOG_SIZE_22 0x544B558
+
+#define NIC0_RXE1_CQ_LOG_SIZE_23 0x544B55C
+
+#define NIC0_RXE1_CQ_LOG_SIZE_24 0x544B560
+
+#define NIC0_RXE1_CQ_LOG_SIZE_25 0x544B564
+
+#define NIC0_RXE1_CQ_LOG_SIZE_26 0x544B568
+
+#define NIC0_RXE1_CQ_LOG_SIZE_27 0x544B56C
+
+#define NIC0_RXE1_CQ_LOG_SIZE_28 0x544B570
+
+#define NIC0_RXE1_CQ_LOG_SIZE_29 0x544B574
+
+#define NIC0_RXE1_CQ_LOG_SIZE_30 0x544B578
+
+#define NIC0_RXE1_CQ_LOG_SIZE_31 0x544B57C
+
+#define NIC0_RXE1_RDV_SEND_WQ_BASE_ADDR_LO 0x544B600
+
+#define NIC0_RXE1_RDV_SEND_WQ_BASE_ADDR_HI 0x544B604
+
+#define NIC0_RXE1_RDV_LOG_MAX_WQ_SIZE 0x544B608
+
+#define NIC0_RXE1_LBW_BASE_LO 0x544B700
+
+#define NIC0_RXE1_LBW_BASE_HI 0x544B704
+
+#define NIC0_RXE1_LBW_LOG_SIZE 0x544B708
+
+#define NIC0_RXE1_RAW_BASE_LO_P0_0 0x544B710
+
+#define NIC0_RXE1_RAW_BASE_LO_P0_1 0x544B714
+
+#define NIC0_RXE1_RAW_BASE_HI_P0_0 0x544B720
+
+#define NIC0_RXE1_RAW_BASE_HI_P0_1 0x544B724
+
+#define NIC0_RXE1_RAW_MISC_P0_0 0x544B730
+
+#define NIC0_RXE1_RAW_MISC_P0_1 0x544B734
+
+#define NIC0_RXE1_RAW_BASE_LO_P1_0 0x544B750
+
+#define NIC0_RXE1_RAW_BASE_LO_P1_1 0x544B754
+
+#define NIC0_RXE1_RAW_BASE_HI_P1_0 0x544B760
+
+#define NIC0_RXE1_RAW_BASE_HI_P1_1 0x544B764
+
+#define NIC0_RXE1_RAW_MISC_P1_0 0x544B770
+
+#define NIC0_RXE1_RAW_MISC_P1_1 0x544B774
+
+#define NIC0_RXE1_RAW_BASE_LO_P2_0 0x544B790
+
+#define NIC0_RXE1_RAW_BASE_LO_P2_1 0x544B794
+
+#define NIC0_RXE1_RAW_BASE_HI_P2_0 0x544B7A0
+
+#define NIC0_RXE1_RAW_BASE_HI_P2_1 0x544B7A4
+
+#define NIC0_RXE1_RAW_MISC_P2_0 0x544B7B0
+
+#define NIC0_RXE1_RAW_MISC_P2_1 0x544B7B4
+
+#define NIC0_RXE1_RAW_BASE_LO_P3_0 0x544B7D0
+
+#define NIC0_RXE1_RAW_BASE_LO_P3_1 0x544B7D4
+
+#define NIC0_RXE1_RAW_BASE_HI_P3_0 0x544B7E0
+
+#define NIC0_RXE1_RAW_BASE_HI_P3_1 0x544B7E4
+
+#define NIC0_RXE1_RAW_MISC_P3_0 0x544B7F0
+
+#define NIC0_RXE1_RAW_MISC_P3_1 0x544B7F4
+
+#define NIC0_RXE1_SEI_INTR_CAUSE 0x544B800
+
+#define NIC0_RXE1_SEI_INTR_MASK 0x544B804
+
+#define NIC0_RXE1_SEI_INTR_CLEAR 0x544B808
+
+#define NIC0_RXE1_SPI_INTR_CAUSE 0x544B810
+
+#define NIC0_RXE1_SPI_INTR_MASK 0x544B814
+
+#define NIC0_RXE1_SPI_INTR_CLEAR 0x544B818
+
+#define NIC0_RXE1_DBG_SPMU_SELECT 0x544BA00
+
+#define NIC0_RXE1_DBG_INV_OP_0 0x544BA04
+
+#define NIC0_RXE1_DBG_INV_OP_1 0x544BA08
+
+#define NIC0_RXE1_DBG_AXI_ERR 0x544BA0C
+
+#define NIC0_RXE1_DBG_AXI_CQE_ERR 0x544BA10
+
+#define NIC0_RXE1_DBG_AXI_LBW_ERR 0x544BA14
+
+#define NIC0_RXE1_DBG_EN 0x544BA18
+
+#define NIC0_RXE1_DBG_CQ_ARM_ON 0x544BA1C
+
+#define NIC0_RXE1_DBG_CQ_ARM_SEL 0x544BA20
+
+#define NIC0_RXE1_DBG_CQ_ARM_IDX 0x544BA24
+
+#define NIC0_RXE1_DBG_SLICE_MAIN 0x544BA28
+
+#define NIC0_RXE1_DBG_SLICE_SCT 0x544BA2C
+
+#endif /* ASIC_REG_NIC0_RXE1_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes0_masks.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes0_masks.h
new file mode 100644
index 000000000000..6b5538ebe25e
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes0_masks.h
@@ -0,0 +1,7163 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_SERDES0_MASKS_H_
+#define ASIC_REG_NIC0_SERDES0_MASKS_H_
+
+/*****************************************
+ * NIC0_SERDES0
+ * (Prototype: NIC_SERDES)
+ *****************************************
+ */
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P00 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P00_RSVD_0P00_06_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P00_RSVD_0P00_06_00_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0P00_DFE_MODE_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P00_DFE_MODE_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0P00_DATA_THR_INIT_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P00_DATA_THR_INIT_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P00_PAM4_SM_RESET_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P00_PAM4_SM_RESET_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P01 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P01_CNTR_TARGET_INIT_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P01_CNTR_TARGET_INIT_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P02 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P02_CNTR_TARGET_FINAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P02_CNTR_TARGET_FINAL_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P03 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P03_RX_PAM4_SD_THR_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P03_RX_PAM4_SD_THR_MASK 0x7FF
+#define NIC0_SERDES0_LANE0_REGISTER_0P03_RSVD_0P03_15_11_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0P03_RSVD_0P03_15_11_MASK 0xF800
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P04 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P04_RSVD_0P04_04_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P04_RSVD_0P04_04_00_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_0P04_DFE_INIT_VAL_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0P04_DFE_INIT_VAL_MASK 0xFE0
+#define NIC0_SERDES0_LANE0_REGISTER_0P04_SD_PERIOD_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0P04_SD_PERIOD_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P05 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P05_RSVD_0P05_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P05_RSVD_0P05_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0P05_KP_S4_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P05_KP_S4_MASK 0x700
+#define NIC0_SERDES0_LANE0_REGISTER_0P05_RSVD_0P05_15_11_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0P05_RSVD_0P05_15_11_MASK 0xF800
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P06 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P06_KP_S6_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P06_KP_S6_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_0P06_RSVD_0P06_06_03_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0P06_RSVD_0P06_06_03_MASK 0x78
+#define NIC0_SERDES0_LANE0_REGISTER_0P06_KP_S5_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P06_KP_S5_MASK 0x380
+#define NIC0_SERDES0_LANE0_REGISTER_0P06_RSVD_0P06_11_10_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0P06_RSVD_0P06_11_10_MASK 0xC00
+#define NIC0_SERDES0_LANE0_REGISTER_0P06_ITERATION_COUNT_S4_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0P06_ITERATION_COUNT_S4_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P07 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P07_RSVD_0P07_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P07_RSVD_0P07_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_0P07_TIMER_MEAS_S6_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0P07_TIMER_MEAS_S6_MASK 0x78
+#define NIC0_SERDES0_LANE0_REGISTER_0P07_RSVD_0P07_10_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P07_RSVD_0P07_10_07_MASK 0x780
+#define NIC0_SERDES0_LANE0_REGISTER_0P07_TIMER_MEAS_S5_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0P07_TIMER_MEAS_S5_MASK 0x7800
+#define NIC0_SERDES0_LANE0_REGISTER_0P07_RSVD_0P07_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P07_RSVD_0P07_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P08 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P08_RSVD_0P08_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P08_RSVD_0P08_00_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0P08_FREQ_INIT_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0P08_FREQ_INIT_MASK 0xFFE
+#define NIC0_SERDES0_LANE0_REGISTER_0P08_RSVD_0P08_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0P08_RSVD_0P08_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P09 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P09_ITERATION_COUNT_S6_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P09_ITERATION_COUNT_S6_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0P09_RSVD_0P09_07_04_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0P09_RSVD_0P09_07_04_MASK 0xF0
+#define NIC0_SERDES0_LANE0_REGISTER_0P09_DAC_SETTLING_PERIOD_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P09_DAC_SETTLING_PERIOD_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0P09_ITERATION_COUNT_S5_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0P09_ITERATION_COUNT_S5_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P0A */
+#define NIC0_SERDES0_LANE0_REGISTER_0P0A_HF_PERIOD_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P0A_HF_PERIOD_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_0P0A_OVERFLOW_PERIOD_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0P0A_OVERFLOW_PERIOD_MASK 0x3E0
+#define NIC0_SERDES0_LANE0_REGISTER_0P0A_TIMER_MEAS_S7_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0P0A_TIMER_MEAS_S7_MASK 0x3C00
+#define NIC0_SERDES0_LANE0_REGISTER_0P0A_MU_MARGIN_S6_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P0A_MU_MARGIN_S6_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P0B */
+#define NIC0_SERDES0_LANE0_REGISTER_0P0B_HF_THR_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P0B_HF_THR_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0P0B_RSVD_0P0B_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P0B_RSVD_0P0B_07_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0P0B_OVERFLOW_THR_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P0B_OVERFLOW_THR_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P0B_RSVD_0P0B_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P0B_RSVD_0P0B_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P0C */
+#define NIC0_SERDES0_LANE0_REGISTER_0P0C_OVERFLOW_CNTR_UPPER_LIMIT_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P0C_OVERFLOW_CNTR_UPPER_LIMIT_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P0D */
+#define NIC0_SERDES0_LANE0_REGISTER_0P0D_OVERFLOW_CNTR_LOWER_LIMIT_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P0D_OVERFLOW_CNTR_LOWER_LIMIT_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P0E */
+#define NIC0_SERDES0_LANE0_REGISTER_0P0E_HF_CNTR_TARGET_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P0E_HF_CNTR_TARGET_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P0F */
+#define NIC0_SERDES0_LANE0_REGISTER_0P0F_RSVD_0P0F_13_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P0F_RSVD_0P0F_13_00_MASK 0x3FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0P0F_EM_CNTR_RESET_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P0F_EM_CNTR_RESET_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0P0F_DFE_FREEZE_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P0F_DFE_FREEZE_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P11 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P11_PAM4_BP2_STATE_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P11_PAM4_BP2_STATE_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_0P11_RSVD_0P11_07_05_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0P11_RSVD_0P11_07_05_MASK 0xE0
+#define NIC0_SERDES0_LANE0_REGISTER_0P11_PAM4_BP1_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P11_PAM4_BP1_STATE_MASK 0x1F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P11_PAM4_SM_CONT_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0P11_PAM4_SM_CONT_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0P11_PAM4_BP2_EN_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P11_PAM4_BP2_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0P11_PAM4_BP1_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P11_PAM4_BP1_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P12 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P12_FORCE_SM_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P12_FORCE_SM_VAL_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_0P12_FORCE_SM_VAL_EN_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0P12_FORCE_SM_VAL_EN_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_0P12_DELTA_OW_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0P12_DELTA_OW_MASK 0x1FC0
+#define NIC0_SERDES0_LANE0_REGISTER_0P12_DELTA_OWEN_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0P12_DELTA_OWEN_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0P12_CTH_OWEN_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P12_CTH_OWEN_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0P12_THS_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P12_THS_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P13 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P13_RSVD_0P13_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P13_RSVD_0P13_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0P13_THS_OW_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0P13_THS_OW_MASK 0xFFF0
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P15 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P15_CTH_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P15_CTH_OW_MASK 0xFFF
+#define NIC0_SERDES0_LANE0_REGISTER_0P15_RSVD_0P15_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0P15_RSVD_0P15_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P16 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P16_RSVD_0P16_06_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P16_RSVD_0P16_06_00_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0P16_HF_CNTR_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P16_HF_CNTR_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0P16_RSVD_0P16_13_08_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P16_RSVD_0P16_13_08_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P16_EM_BM1_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P16_EM_BM1_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P1F */
+#define NIC0_SERDES0_LANE0_REGISTER_0P1F_ADC_CAL_START_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P1F_ADC_CAL_START_OW_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0P1F_ADC_CAL_START_OWEN_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0P1F_ADC_CAL_START_OWEN_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_0P1F_FORCE_FREQ_OW_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0P1F_FORCE_FREQ_OW_MASK 0x1FFC
+#define NIC0_SERDES0_LANE0_REGISTER_0P1F_FORCE_FREQ_OWEN_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0P1F_FORCE_FREQ_OWEN_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0P1F_DTL_RELOAD_OW_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P1F_DTL_RELOAD_OW_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0P1F_DTL_RELOAD_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P1F_DTL_RELOAD_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P20 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KTHETA3_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KTHETA3_OW_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KTHETA3_OWEN_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KTHETA3_OWEN_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KTHETA2_OW_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KTHETA2_OW_MASK 0x18
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KTHETA2_OWEN_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KTHETA2_OWEN_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KP_OW_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KP_OW_MASK 0x1C0
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KP_OWEN_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KP_OWEN_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KF_OW_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KF_OW_MASK 0xC00
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KF_OWEN_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_KF_OWEN_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_MU_MARGIN_OW_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_MU_MARGIN_OW_MASK 0x6000
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_MU_MARGIN_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P20_MU_MARGIN_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P21 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_RSVD_0P21_01_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_RSVD_0P21_01_00_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_MARGIN_PAT_DIS_OW_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_MARGIN_PAT_DIS_OW_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_MARGIN_PAT_DIS_OWEN_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_MARGIN_PAT_DIS_OWEN_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_RX_PAM4_CTLE_OVER_VAL_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_RX_PAM4_CTLE_OVER_VAL_MASK 0x70
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_RX_PAM4_CTLE_OVER_EN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_RX_PAM4_CTLE_OVER_EN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_DAC_SEL_OW_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_DAC_SEL_OW_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_DAC_SEL_OWEN_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_DAC_SEL_OWEN_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_KTHETA4_OW_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_KTHETA4_OW_MASK 0x6000
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_KTHETA4_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P21_KTHETA4_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P23 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P23_RSVD_0P23_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P23_RSVD_0P23_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0P23_PAM4_PHY_READY_OW_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0P23_PAM4_PHY_READY_OW_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_0P23_PAM4_PHY_READY_OWEN_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0P23_PAM4_PHY_READY_OWEN_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_0P23_RSVD_0P23_15_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0P23_RSVD_0P23_15_06_MASK 0xFFC0
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P24 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P24_PAM4_SIG_DET_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P24_PAM4_SIG_DET_OW_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0P24_PAM4_SIG_DET_OWEN_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0P24_PAM4_SIG_DET_OWEN_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_0P24_RSVD_0P24_15_02_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0P24_RSVD_0P24_15_02_MASK 0xFFFC
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P28 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P28_RSVD_0P28_04_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P28_RSVD_0P28_04_00_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_0P28_READ_DAC_SEL_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0P28_READ_DAC_SEL_MASK 0x1E0
+#define NIC0_SERDES0_LANE0_REGISTER_0P28_PAM4_CURRENT_STATE_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0P28_PAM4_CURRENT_STATE_MASK 0x3E00
+#define NIC0_SERDES0_LANE0_REGISTER_0P28_PAM4_BP2_REACHED_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P28_PAM4_BP2_REACHED_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0P28_PAM4_BP1_REACHED_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P28_PAM4_BP1_REACHED_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P2D */
+#define NIC0_SERDES0_LANE0_REGISTER_0P2D_READ_STATE_CNTR_HIGH_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P2D_READ_STATE_CNTR_HIGH_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P2E */
+#define NIC0_SERDES0_LANE0_REGISTER_0P2E_READ_STATE_CNTR_LOW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P2E_READ_STATE_CNTR_LOW_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P2F */
+#define NIC0_SERDES0_LANE0_REGISTER_0P2F_RSVD_0P2F_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P2F_RSVD_0P2F_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0P2F_READ_THS_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0P2F_READ_THS_MASK 0xFFF0
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P32 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P32_READ_MINUS_MARGIN_MSB_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P32_READ_MINUS_MARGIN_MSB_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0P32_READ_PLUS_MARGIN_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0P32_READ_PLUS_MARGIN_MASK 0xFFF0
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P33 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P33_RSVD_0P33_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P33_RSVD_0P33_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0P33_READ_MINUS_MARGIN_LSB_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P33_READ_MINUS_MARGIN_LSB_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P36 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P36_READ_FIXED_PAT_PLUS_MARGIN_MSB_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P36_READ_FIXED_PAT_PLUS_MARGIN_MSB_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0P36_RSVD_0P36_11_08_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P36_RSVD_0P36_11_08_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0P36_PAM4_BP_6_REACHED_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0P36_PAM4_BP_6_REACHED_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_0P36_PAM4_BP_5_REACHED_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0P36_PAM4_BP_5_REACHED_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0P36_PAM4_BP_4_REACHED_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P36_PAM4_BP_4_REACHED_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0P36_PAM4_BP_3_REACHED_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P36_PAM4_BP_3_REACHED_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P37 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P37_READ_FIXED_PAT_MINUS_MARGIN_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P37_READ_FIXED_PAT_MINUS_MARGIN_MASK 0xFFF
+#define NIC0_SERDES0_LANE0_REGISTER_0P37_READ_FIXED_PAT_PLUS_MARGIN_LSB_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0P37_READ_FIXED_PAT_PLUS_MARGIN_LSB_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P38 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P38_READ_EM_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P38_READ_EM_MASK 0x7FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0P38_RSVD_0P38_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P38_RSVD_0P38_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P40 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P40_READ_FM1_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P40_READ_FM1_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0P40_READ_DELTA_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P40_READ_DELTA_MASK 0x3F80
+#define NIC0_SERDES0_LANE0_REGISTER_0P40_RSVD_0P40_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P40_RSVD_0P40_14_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0P40_READ_PHY_READY_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P40_READ_PHY_READY_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P41 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_RSVD_0P41_01_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_RSVD_0P41_01_00_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_THETA4_UPDATE_FLIP_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_THETA4_UPDATE_FLIP_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_THETA3_UPDATE_FLIP_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_THETA3_UPDATE_FLIP_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_THETA2_UPDATE_FLIP_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_THETA2_UPDATE_FLIP_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_RSVD_0P41_09_05_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_RSVD_0P41_09_05_MASK 0x3E0
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_THETA4_UPDATE_MODE_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_THETA4_UPDATE_MODE_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_THETA3_UPDATE_MODE_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_THETA3_UPDATE_MODE_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_THETA2_UPDATE_MODE_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_THETA2_UPDATE_MODE_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_RSVD_0P41_14_13_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_RSVD_0P41_14_13_MASK 0x6000
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_PAM4_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P41_PAM4_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P42 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_RX_GRAYCODE_EN_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_RX_GRAYCODE_EN_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_RX_PRECODE_EN_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_RX_PRECODE_EN_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR8_EN_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR8_EN_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR7_EN_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR7_EN_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR6_EN_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR6_EN_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR5_EN_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR5_EN_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR4_EN_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR4_EN_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR3_EN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR3_EN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR2_EN_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR2_EN_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR1_EN_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_CNTR1_EN_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_RSVD_0P42_15_10_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0P42_RSVD_0P42_15_10_MASK 0xFC00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P43 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_PRBS_SYNC_CNTR_RESET_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_PRBS_SYNC_CNTR_RESET_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_RX_PRBS_AUTO_SYNC_EN_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_RX_PRBS_AUTO_SYNC_EN_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_RX_PRBS_FORCE_RELOAD_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_RX_PRBS_FORCE_RELOAD_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_PU_PRBS_SYNC_CHKR_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_PU_PRBS_SYNC_CHKR_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_PU_PRBS_CHKR_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_PU_PRBS_CHKR_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_PRBS_MODE_SEL_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_PRBS_MODE_SEL_MASK 0x60
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_RX_DATA_FLIP_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_RX_DATA_FLIP_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_RX_DATA_FW_FLIP_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_RX_DATA_FW_FLIP_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_PRBS_CHECK_CNTR_RESET_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_PRBS_CHECK_CNTR_RESET_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_RSVD_0P43_14_10_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_RSVD_0P43_14_10_MASK 0x7C00
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_RX_SWAP_MSB_LSB_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P43_RX_SWAP_MSB_LSB_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P44 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P44_RSVD_0P44_01_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P44_RSVD_0P44_01_00_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_0P44_PRBS_SYNC_LOSS_THR_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0P44_PRBS_SYNC_LOSS_THR_MASK 0xFC
+#define NIC0_SERDES0_LANE0_REGISTER_0P44_PRBS_MISMATCH_THR_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P44_PRBS_MISMATCH_THR_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P45 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P45_RX_ASIC_DATA_FLIP_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P45_RX_ASIC_DATA_FLIP_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0P45_RSVD_0P45_02_01_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0P45_RSVD_0P45_02_01_MASK 0x6
+#define NIC0_SERDES0_LANE0_REGISTER_0P45_FIXED_PAT_MODE_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0P45_FIXED_PAT_MODE_MASK 0x78
+#define NIC0_SERDES0_LANE0_REGISTER_0P45_RSVD_0P45_09_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P45_RSVD_0P45_09_07_MASK 0x380
+#define NIC0_SERDES0_LANE0_REGISTER_0P45_PRBS_PAT_CNTR_RESET_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0P45_PRBS_PAT_CNTR_RESET_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_0P45_PRBS_SYNC_THR_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0P45_PRBS_SYNC_THR_MASK 0xF800
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P46 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P46_THETA2_ACC_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P46_THETA2_ACC_OW_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0P46_THETA2_ACC_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P46_THETA2_ACC_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0P46_PH1_ACC_OW_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P46_PH1_ACC_OW_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P46_PH1_ACC_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P46_PH1_ACC_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P47 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P47_THETA4_ACC_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P47_THETA4_ACC_OW_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0P47_THETA4_ACC_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P47_THETA4_ACC_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0P47_THETA3_ACC_OW_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P47_THETA3_ACC_OW_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P47_THETA3_ACC_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P47_THETA3_ACC_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P48 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P48_AGC_SETTING2_MSB_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P48_AGC_SETTING2_MSB_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0P48_AGC_SETTING1_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0P48_AGC_SETTING1_MASK 0x3F0
+#define NIC0_SERDES0_LANE0_REGISTER_0P48_AGC_SETTING0_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0P48_AGC_SETTING0_MASK 0xFC00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P49 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P49_AGC_SETTING5_MSB_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P49_AGC_SETTING5_MSB_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_0P49_AGC_SETTING4_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0P49_AGC_SETTING4_MASK 0xFC
+#define NIC0_SERDES0_LANE0_REGISTER_0P49_AGC_SETTING3_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P49_AGC_SETTING3_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P49_AGC_SETTING2_LSB_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P49_AGC_SETTING2_LSB_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P4A */
+#define NIC0_SERDES0_LANE0_REGISTER_0P4A_AGC_SETTING7_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P4A_AGC_SETTING7_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_0P4A_AGC_SETTING6_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0P4A_AGC_SETTING6_MASK 0xFC0
+#define NIC0_SERDES0_LANE0_REGISTER_0P4A_AGC_SETTING5_LSB_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0P4A_AGC_SETTING5_LSB_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P4B */
+#define NIC0_SERDES0_LANE0_REGISTER_0P4B_SD_CNTR_LIMIT_MSB_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P4B_SD_CNTR_LIMIT_MSB_MASK 0x7FF
+#define NIC0_SERDES0_LANE0_REGISTER_0P4B_RX_FREQ_EN_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0P4B_RX_FREQ_EN_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_0P4B_TOP_ROTR_EN_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0P4B_TOP_ROTR_EN_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_0P4B_DTL_LOST_LOCK_MODE_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0P4B_DTL_LOST_LOCK_MODE_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0P4B_RSVD_0P4B_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P4B_RSVD_0P4B_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P4C */
+#define NIC0_SERDES0_LANE0_REGISTER_0P4C_RSVD_0P4C_06_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P4C_RSVD_0P4C_06_00_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0P4C_SD_CNTR_LIMIT_LSB_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P4C_SD_CNTR_LIMIT_LSB_MASK 0xFF80
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P4E */
+#define NIC0_SERDES0_LANE0_REGISTER_0P4E_RX_PRBS_ERR_CHKR_MSB_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P4E_RX_PRBS_ERR_CHKR_MSB_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P4F */
+#define NIC0_SERDES0_LANE0_REGISTER_0P4F_RX_PRBS_ERR_CHKR_LSB_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P4F_RX_PRBS_ERR_CHKR_LSB_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P50 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P50_PRBS_READ_SYNC_ERR_CNTR_MSB_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P50_PRBS_READ_SYNC_ERR_CNTR_MSB_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P51 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P51_PRBS_READ_SYNC_ERR_CNTR_LSB_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P51_PRBS_READ_SYNC_ERR_CNTR_LSB_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P6A */
+#define NIC0_SERDES0_LANE0_REGISTER_0P6A_RSVD_0P6A_06_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P6A_RSVD_0P6A_06_00_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0P6A_READ_SIG_DET_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P6A_READ_SIG_DET_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0P6A_RSVD_0P6A_14_08_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P6A_RSVD_0P6A_14_08_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P6A_RX_READ_PHY_READY_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P6A_RX_READ_PHY_READY_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P6C */
+#define NIC0_SERDES0_LANE0_REGISTER_0P6C_READ_THETA2_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P6C_READ_THETA2_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0P6C_RSVD_0P6C_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P6C_RSVD_0P6C_07_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0P6C_READ_PH1_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P6C_READ_PH1_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P6D */
+#define NIC0_SERDES0_LANE0_REGISTER_0P6D_READ_THETA4_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P6D_READ_THETA4_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0P6D_RSVD_0P6D_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P6D_RSVD_0P6D_07_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0P6D_READ_THETA3_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P6D_READ_THETA3_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P6D_PRBS_SYNC_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P6D_PRBS_SYNC_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P6E */
+#define NIC0_SERDES0_LANE0_REGISTER_0P6E_RSVD_0P6E_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P6E_RSVD_0P6E_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0P6E_READOUT_CAPTURE_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P6E_READOUT_CAPTURE_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_0P6E_READOUT_SYNC_EN_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0P6E_READOUT_SYNC_EN_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_0P6E_RSVD_0P6E_15_10_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0P6E_RSVD_0P6E_15_10_MASK 0xFC00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P73 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P73_READ_FREQ_ACC_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P73_READ_FREQ_ACC_MASK 0x7FF
+#define NIC0_SERDES0_LANE0_REGISTER_0P73_RSVD_0P73_15_11_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0P73_RSVD_0P73_15_11_MASK 0xF800
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P74 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P74_READ_PH_WANDER_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P74_READ_PH_WANDER_MASK 0x7FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0P74_CORR_CNTR_FREEZE_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P74_CORR_CNTR_FREEZE_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P79 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P79_RSVD_0P79_12_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P79_RSVD_0P79_12_00_MASK 0x1FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0P79_TED_QUAL_OFF_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0P79_TED_QUAL_OFF_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0P79_TED12_EN_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P79_TED12_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0P79_RSVD_0P79_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P79_RSVD_0P79_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P80 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P80_PAM4_BP6_STATE_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P80_PAM4_BP6_STATE_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_0P80_RSVD_0P80_06_05_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0P80_RSVD_0P80_06_05_MASK 0x60
+#define NIC0_SERDES0_LANE0_REGISTER_0P80_PAM4_BP6_EN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P80_PAM4_BP6_EN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0P80_PAM4_BP5_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P80_PAM4_BP5_STATE_MASK 0x1F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P80_RSVD_0P80_14_13_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0P80_RSVD_0P80_14_13_MASK 0x6000
+#define NIC0_SERDES0_LANE0_REGISTER_0P80_PAM4_BP5_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P80_PAM4_BP5_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P81 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P81_COUNT_0_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P81_COUNT_0_OW_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P82 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P82_COUNT_POS_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P82_COUNT_POS_OW_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P83 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P83_RSVD_0P83_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P83_RSVD_0P83_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_0P83_C_PLUS_MARGIN_OW_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0P83_C_PLUS_MARGIN_OW_MASK 0x7FF8
+#define NIC0_SERDES0_LANE0_REGISTER_0P83_RSVD_0P83_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P83_RSVD_0P83_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P8F */
+#define NIC0_SERDES0_LANE0_REGISTER_0P8F_PAM4_BP4_STATE_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P8F_PAM4_BP4_STATE_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_0P8F_RSVD_0P8F_06_05_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0P8F_RSVD_0P8F_06_05_MASK 0x60
+#define NIC0_SERDES0_LANE0_REGISTER_0P8F_PAM4_BP4_EN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P8F_PAM4_BP4_EN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0P8F_PAM4_BP3_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P8F_PAM4_BP3_STATE_MASK 0x1F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P8F_RSVD_0P8F_14_13_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0P8F_RSVD_0P8F_14_13_MASK 0x6000
+#define NIC0_SERDES0_LANE0_REGISTER_0P8F_PAM4_BP3_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P8F_PAM4_BP3_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P94 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P94_MM_F1_FGT_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P94_MM_F1_FGT_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_0P94_MM_LEV_UPDATE_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0P94_MM_LEV_UPDATE_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0P94_MM_POL_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0P94_MM_POL_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0P94_MM_F0_FGT_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P94_MM_F0_FGT_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P94_MM_QUALI_MODE_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P94_MM_QUALI_MODE_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0P94_MM_DTL_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0P94_MM_DTL_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P95 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P95_MM_QUANT_LEV1_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P95_MM_QUANT_LEV1_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_0P95_RSVD_0P95_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0P95_RSVD_0P95_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_0P95_MM_QUANT_LEV0_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P95_MM_QUANT_LEV0_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P95_RSVD_0P95_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P95_RSVD_0P95_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P96 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P96_MM_QUANT_LEV3_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P96_MM_QUANT_LEV3_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_0P96_RSVD_0P96_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0P96_RSVD_0P96_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_0P96_MM_QUANT_LEV2_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P96_MM_QUANT_LEV2_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P96_RSVD_0P96_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P96_RSVD_0P96_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P97 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P97_MM_QUANT_LEV5_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P97_MM_QUANT_LEV5_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_0P97_RSVD_0P97_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0P97_RSVD_0P97_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_0P97_MM_QUANT_LEV4_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P97_MM_QUANT_LEV4_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P97_RSVD_0P97_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P97_RSVD_0P97_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P98 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P98_MM_QUANT_LEV7_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P98_MM_QUANT_LEV7_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_0P98_RSVD_0P98_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0P98_RSVD_0P98_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_0P98_MM_QUANT_LEV6_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P98_MM_QUANT_LEV6_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P98_RSVD_0P98_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P98_RSVD_0P98_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P99 */
+#define NIC0_SERDES0_LANE0_REGISTER_0P99_MM_QUANT_LEV9_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P99_MM_QUANT_LEV9_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_0P99_RSVD_0P99_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0P99_RSVD_0P99_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_0P99_MM_QUANT_LEV8_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P99_MM_QUANT_LEV8_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P99_RSVD_0P99_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P99_RSVD_0P99_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P9A */
+#define NIC0_SERDES0_LANE0_REGISTER_0P9A_MM_QUANT_LEV11_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P9A_MM_QUANT_LEV11_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_0P9A_RSVD_0P9A_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0P9A_RSVD_0P9A_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_0P9A_MM_QUANT_LEV10_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P9A_MM_QUANT_LEV10_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P9A_RSVD_0P9A_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P9A_RSVD_0P9A_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0P9B */
+#define NIC0_SERDES0_LANE0_REGISTER_0P9B_RSVD_0P9B_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0P9B_RSVD_0P9B_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0P9B_MM_QUANT_LEV12_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0P9B_MM_QUANT_LEV12_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_0P9B_RSVD_0P9B_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0P9B_RSVD_0P9B_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PA0 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_SPEED_MODE_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_SPEED_MODE_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_PAM4_TEST_PAT_MODE_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_PAM4_TEST_PAT_MODE_MASK 0xC
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_RSVD_0PA0_04_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_RSVD_0PA0_04_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_ANA_OUT_FLIP_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_ANA_OUT_FLIP_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_RSVD_0PA0_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_RSVD_0PA0_06_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_DATA_POL_FLIP_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_DATA_POL_FLIP_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_MODE_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_MODE_MASK 0x300
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_GEN_ERR_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_GEN_ERR_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_GEN_EN_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_GEN_EN_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_RSVD_0PA0_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_RSVD_0PA0_12_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PAM4_TEST_EN_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PAM4_TEST_EN_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_CLK_EN_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_CLK_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_TEST_DATA_SRC_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_TEST_DATA_SRC_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PA1 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PA1_TX_TEST_PAT_3_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PA1_TX_TEST_PAT_3_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PA2 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PA2_TX_TEST_PAT_2_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PA2_TX_TEST_PAT_2_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PA3 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PA3_TX_TEST_PAT_1_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PA3_TX_TEST_PAT_1_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PA4 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PA4_TX_TEST_PAT_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PA4_TX_TEST_PAT_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PA5 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PA5_TX_PRE_2_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PA5_TX_PRE_2_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0PA5_TX_PRE_2_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PA5_TX_PRE_2_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PA6 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PA6_TX_PRE_2_3X_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PA6_TX_PRE_2_3X_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0PA6_TX_PRE_2_3X_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PA6_TX_PRE_2_3X_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PA7 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PA7_TX_PRE_1_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PA7_TX_PRE_1_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0PA7_TX_PRE_1_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PA7_TX_PRE_1_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PA8 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PA8_TX_PRE_1_3X_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PA8_TX_PRE_1_3X_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0PA8_TX_PRE_1_3X_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PA8_TX_PRE_1_3X_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PA9 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PA9_TX_MAIN_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PA9_TX_MAIN_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0PA9_TX_MAIN_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PA9_TX_MAIN_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PAA */
+#define NIC0_SERDES0_LANE0_REGISTER_0PAA_TX_MAIN_3X_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PAA_TX_MAIN_3X_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0PAA_TX_MAIN_3X_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PAA_TX_MAIN_3X_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PAB */
+#define NIC0_SERDES0_LANE0_REGISTER_0PAB_TX_POST_1_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PAB_TX_POST_1_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0PAB_TX_POST_1_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PAB_TX_POST_1_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PAC */
+#define NIC0_SERDES0_LANE0_REGISTER_0PAC_TX_POST_1_3X_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PAC_TX_POST_1_3X_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0PAC_TX_POST_1_3X_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PAC_TX_POST_1_3X_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PAD */
+#define NIC0_SERDES0_LANE0_REGISTER_0PAD_TX_POST_2_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PAD_TX_POST_2_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0PAD_TX_POST_2_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PAD_TX_POST_2_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PAE */
+#define NIC0_SERDES0_LANE0_REGISTER_0PAE_TX_POST_2_3X_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PAE_TX_POST_2_3X_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0PAE_TX_POST_2_3X_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PAE_TX_POST_2_3X_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PAF */
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_RSVD_0PAF_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_RSVD_0PAF_00_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_PRE2_SCALE_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_PRE2_SCALE_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_PRE1_SCALE_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_PRE1_SCALE_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_MAIN_SCALE_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_MAIN_SCALE_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_POST1_SCALE_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_POST1_SCALE_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_POST2_SCALE_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_POST2_SCALE_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_RSVD_0PAF_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_RSVD_0PAF_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_PRECODE_EN_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_PRECODE_EN_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_GRAYCODE_EN_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_GRAYCODE_EN_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_SWAP_MSB_LSB_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_SWAP_MSB_LSB_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_PRE2_AUTO_SEL_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_PRE2_AUTO_SEL_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_PRE1_AUTO_SEL_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_PRE1_AUTO_SEL_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_MAIN_AUTO_SEL_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_MAIN_AUTO_SEL_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_POST1_AUTO_SEL_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_POST1_AUTO_SEL_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_POST2_AUTO_SEL_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_POST2_AUTO_SEL_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PB0 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_HALF_RATE_EN_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_HALF_RATE_EN_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_MODE_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_MODE_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_RSVD_0PB0_09_02_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_RSVD_0PB0_09_02_MASK 0x3FC
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_PRBS_GERR_EN_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_PRBS_GERR_EN_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_PRBS_GEN_EN_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_PRBS_GEN_EN_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_RSVD_0PB0_13_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_RSVD_0PB0_13_12_MASK 0x3000
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_PRBS_CLK_EN_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_PRBS_CLK_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_RSVD_0PB0_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0_RSVD_0PB0_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PB1 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PB1_TX_POST6_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PB1_TX_POST6_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0PB1_TX_POST5_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PB1_TX_POST5_MASK 0xF0
+#define NIC0_SERDES0_LANE0_REGISTER_0PB1_TX_POST4_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PB1_TX_POST4_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0PB1_TX_POST3_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PB1_TX_POST3_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PB2 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PB2_RSVD_0PB2_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PB2_RSVD_0PB2_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0PB2_TX_POST8_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PB2_TX_POST8_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0PB2_TX_POST7_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PB2_TX_POST7_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PB3 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PB3_KR_SM_COEF_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PB3_KR_SM_COEF_0_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_0PB3_RSVD_0PB3_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0PB3_RSVD_0PB3_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_0PB3_KR_SM_COEF_1_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PB3_KR_SM_COEF_1_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_0PB3_RSVD_0PB3_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0PB3_RSVD_0PB3_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PC1 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PC1_AGC_DEGEN_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PC1_AGC_DEGEN_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0PC1_RSVD_0PC1_15_08_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PC1_RSVD_0PC1_15_08_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PC3 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PC3_EOM_TEST_EN_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PC3_EOM_TEST_EN_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0PC3_EOM_DLL_CAL_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0PC3_EOM_DLL_CAL_MASK 0xE
+#define NIC0_SERDES0_LANE0_REGISTER_0PC3_EOM_DLL_CTRL_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PC3_EOM_DLL_CTRL_MASK 0xFFF0
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PC4 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PC4_DEGENDL9_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PC4_DEGENDL9_0_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0PC4_DEGENDL9_1_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PC4_DEGENDL9_1_MASK 0xF0
+#define NIC0_SERDES0_LANE0_REGISTER_0PC4_DEGENDL8_0_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PC4_DEGENDL8_0_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0PC4_DEGENDL8_1_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PC4_DEGENDL8_1_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PC9 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PC9_VREF0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PC9_VREF0_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0PC9_EOM_MUX_CTRL_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0PC9_EOM_MUX_CTRL_MASK 0x780
+#define NIC0_SERDES0_LANE0_REGISTER_0PC9_RSVD_0PC9_15_11_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0PC9_RSVD_0PC9_15_11_MASK 0xF800
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PCA */
+#define NIC0_SERDES0_LANE0_REGISTER_0PCA_HPF_MODE_SEL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PCA_HPF_MODE_SEL_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_0PCA_VCOMREFSEL_EX_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0PCA_VCOMREFSEL_EX_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_0PCA_SKEF_VAL_MSB_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0PCA_SKEF_VAL_MSB_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_0PCA_ATTN_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PCA_ATTN_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_0PCA_RSVD_0PCA_15_05_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0PCA_RSVD_0PCA_15_05_MASK 0xFFE0
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PCC */
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC_RSVD_0PCC_09_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC_RSVD_0PCC_09_00_MASK 0x3FF
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC_EN2TO1_4_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC_EN2TO1_4_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC_EN1TO2_4_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC_EN1TO2_4_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC_EN2TO1_3_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC_EN2TO1_3_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC_EN1TO2_3_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC_EN1TO2_3_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC_EN2TO1_2_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC_EN2TO1_2_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC_EN1TO2_2_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC_EN1TO2_2_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PCD */
+#define NIC0_SERDES0_LANE0_REGISTER_0PCD_RSVD_0PCD_06_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PCD_RSVD_0PCD_06_00_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0PCD_REFCLK_SRC_SEL_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0PCD_REFCLK_SRC_SEL_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0PCD_VGAVDSAT_SUM3_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PCD_VGAVDSAT_SUM3_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0PCD_VGAVDSAT_MAIN3_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PCD_VGAVDSAT_MAIN3_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PCF */
+#define NIC0_SERDES0_LANE0_REGISTER_0PCF_EOM_DLL_SEG_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PCF_EOM_DLL_SEG_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_0PCF_RSVD_0PCF_15_02_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0PCF_RSVD_0PCF_15_02_MASK 0xFFFC
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PD8 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PD8_RSVD_0PD8_13_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PD8_RSVD_0PD8_13_00_MASK 0x3FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0PD8_RSVD_0PD8_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0PD8_RSVD_0PD8_14_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0PD8_PU_ADCCAL_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0PD8_PU_ADCCAL_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PD9 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PD9_ADC_ROW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PD9_ADC_ROW_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0PD9_RSVD_0PD9_15_04_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PD9_RSVD_0PD9_15_04_MASK 0xFFF0
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PE5 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PE5_RSVD_0PE5_05_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PE5_RSVD_0PE5_05_00_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_0PE5_RX_TEST_EN_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0PE5_RX_TEST_EN_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0PE5_RX_VTSTGROUP_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0PE5_RX_VTSTGROUP_MASK 0x1F80
+#define NIC0_SERDES0_LANE0_REGISTER_0PE5_RX_TESTMODE_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0PE5_RX_TESTMODE_MASK 0xE000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PE6 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_EDGE4_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_EDGE4_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_RSVD_0PE6_03_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_RSVD_0PE6_03_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_EDGE3_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_EDGE3_MASK 0x70
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_RSVD_0PE6_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_RSVD_0PE6_07_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_EDGE2_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_EDGE2_MASK 0x700
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_RSVD_0PE6_11_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_RSVD_0PE6_11_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_EDGE1_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_EDGE1_MASK 0x7000
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_RSVD_0PE6_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6_RSVD_0PE6_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PE7 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PE7_RSVD_0PE7_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PE7_RSVD_0PE7_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_0PE7_CALNBS_BOT_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0PE7_CALNBS_BOT_MASK 0x38
+#define NIC0_SERDES0_LANE0_REGISTER_0PE7_CALNBS_TOP_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0PE7_CALNBS_TOP_MASK 0x1C0
+#define NIC0_SERDES0_LANE0_REGISTER_0PE7_RSVD_0PE7_15_09_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0PE7_RSVD_0PE7_15_09_MASK 0xFE00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PE9 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PE9_RSVD_0PE9_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PE9_RSVD_0PE9_00_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0PE9_IDACZ_EYE_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0PE9_IDACZ_EYE_MASK 0x3E
+#define NIC0_SERDES0_LANE0_REGISTER_0PE9_IDACY_EYE_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0PE9_IDACY_EYE_MASK 0x7C0
+#define NIC0_SERDES0_LANE0_REGISTER_0PE9_IDACX_EYE_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0PE9_IDACX_EYE_MASK 0xF800
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PEA */
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_RSVD_0PEA_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_RSVD_0PEA_00_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_EYE_EN_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_EYE_EN_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_PU_CLKCOMPREG_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_PU_CLKCOMPREG_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_PU_CLKCOMP_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_PU_CLKCOMP_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_RSVD_0PEA_04_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_RSVD_0PEA_04_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_PU_ADC_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_PU_ADC_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_VDACCLKPHASE0_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_VDACCLKPHASE0_MASK 0x1FC0
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_PLL_BIAS0_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA_PLL_BIAS0_MASK 0xE000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PEB */
+#define NIC0_SERDES0_LANE0_REGISTER_0PEB_RSVD_0PEB_08_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PEB_RSVD_0PEB_08_00_MASK 0x1FF
+#define NIC0_SERDES0_LANE0_REGISTER_0PEB_VREFVDDINTP3_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0PEB_VREFVDDINTP3_MASK 0x1E00
+#define NIC0_SERDES0_LANE0_REGISTER_0PEB_RSVD_0PEB_15_13_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0PEB_RSVD_0PEB_15_13_MASK 0xE000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PEC */
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_RSVD_0PEC_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_RSVD_0PEC_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_DACBIAS0_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_DACBIAS0_MASK 0x70
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_DACBIAS1_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_DACBIAS1_MASK 0x380
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_RSVD_0PEC_11_10_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_RSVD_0PEC_11_10_MASK 0xC00
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_EXRESET_INTP_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_EXRESET_INTP_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_RSVD_0PEC_13_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_RSVD_0PEC_13_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_RX_DCC_EN_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_RX_DCC_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_PU_INTP_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC_PU_INTP_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PED */
+#define NIC0_SERDES0_LANE0_REGISTER_0PED_SKEF_ADDCAP_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PED_SKEF_ADDCAP_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_0PED_SKEF_VAL_LSB_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0PED_SKEF_VAL_LSB_MASK 0x38
+#define NIC0_SERDES0_LANE0_REGISTER_0PED_SKEF_EN_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0PED_SKEF_EN_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0PED_RSVD_0PED_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0PED_RSVD_0PED_07_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0PED_DEGENDL7_0_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PED_DEGENDL7_0_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0PED_DEGENDL7_1_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PED_DEGENDL7_1_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PEE */
+#define NIC0_SERDES0_LANE0_REGISTER_0PEE_DEGENDL6_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PEE_DEGENDL6_0_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0PEE_DEGENDL6_1_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PEE_DEGENDL6_1_MASK 0xF0
+#define NIC0_SERDES0_LANE0_REGISTER_0PEE_DEGENDL5_0_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PEE_DEGENDL5_0_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0PEE_DEGENDL5_1_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PEE_DEGENDL5_1_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PEF */
+#define NIC0_SERDES0_LANE0_REGISTER_0PEF_DEGENDL4_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PEF_DEGENDL4_0_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0PEF_DEGENDL4_1_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PEF_DEGENDL4_1_MASK 0xF0
+#define NIC0_SERDES0_LANE0_REGISTER_0PEF_DEGENDL3_0_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PEF_DEGENDL3_0_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0PEF_DEGENDL3_1_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PEF_DEGENDL3_1_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PF0 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PF0_DEGENDL2_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF0_DEGENDL2_0_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0PF0_DEGENDL2_1_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PF0_DEGENDL2_1_MASK 0xF0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF0_DEGENDL1_0_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PF0_DEGENDL1_0_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0PF0_DEGENDL1_1_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PF0_DEGENDL1_1_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PF1 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1_POL_MUX4_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1_POL_MUX4_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1_POL_MUX3_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1_POL_MUX3_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1_POL_MUX2_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1_POL_MUX2_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1_POL_MUX1_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1_POL_MUX1_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1_DEGENSUM_SUM4_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1_DEGENSUM_SUM4_MASK 0xF0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1_DEGENMAIN_SUM4_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1_DEGENMAIN_SUM4_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1_DEGENSUM1_SUM1_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1_DEGENSUM1_SUM1_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PF2 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PF2_DEGENSUM0_SUM3_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF2_DEGENSUM0_SUM3_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0PF2_DEGENSUM1_SUM3_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PF2_DEGENSUM1_SUM3_MASK 0xF0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF2_DEGENMAIN0_SUM3_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PF2_DEGENMAIN0_SUM3_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0PF2_DEGENMAIN1_SUM3_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PF2_DEGENMAIN1_SUM3_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PF3 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PF3_DEGENMAIN1_SUM2_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF3_DEGENMAIN1_SUM2_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0PF3_DEGENSUM0_SUM2_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PF3_DEGENSUM0_SUM2_MASK 0xF0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF3_DEGENSUM1_SUM2_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PF3_DEGENSUM1_SUM2_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0PF3_DEGENMAIN0_SUM2_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PF3_DEGENMAIN0_SUM2_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PF4 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PF4_AGCGAIN2_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF4_AGCGAIN2_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0PF4_RSVD_0PF4_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0PF4_RSVD_0PF4_07_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0PF4_AGCGAIN1_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PF4_AGCGAIN1_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0PF4_RSVD_0PF4_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0PF4_RSVD_0PF4_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PF5 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PF5_DEGENMAIN0_SUM1_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF5_DEGENMAIN0_SUM1_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0PF5_DEGENMAIN1_SUM1_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PF5_DEGENMAIN1_SUM1_MASK 0xF0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF5_DEGENSUM0_SUM1_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PF5_DEGENSUM0_SUM1_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0PF5_RSVD_0PF5_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PF5_RSVD_0PF5_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PF6 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PF6_RSVD_0PF6_05_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF6_RSVD_0PF6_05_00_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_0PF6_VREFAGCREG_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0PF6_VREFAGCREG_MASK 0x1C0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF6_RSVD_0PF6_10_09_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0PF6_RSVD_0PF6_10_09_MASK 0x600
+#define NIC0_SERDES0_LANE0_REGISTER_0PF6_AGCOFFSETLPF_EN_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0PF6_AGCOFFSETLPF_EN_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_0PF6_VGAVDSAT_DL_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PF6_VGAVDSAT_DL_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PF7 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PF7_RSVD_0PF7_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF7_RSVD_0PF7_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_0PF7_VGAVDSAT_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0PF7_VGAVDSAT_MASK 0x78
+#define NIC0_SERDES0_LANE0_REGISTER_0PF7_VAGCBUFDAC_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0PF7_VAGCBUFDAC_MASK 0x380
+#define NIC0_SERDES0_LANE0_REGISTER_0PF7_VCASGA5X_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0PF7_VCASGA5X_MASK 0x1C00
+#define NIC0_SERDES0_LANE0_REGISTER_0PF7_CTLE_CM2_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0PF7_CTLE_CM2_MASK 0xE000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PF8 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_RSVD_0PF8_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_RSVD_0PF8_00_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_CTLE_CM1_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_CTLE_CM1_MASK 0xE
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_RSVD_0PF8_09_04_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_RSVD_0PF8_09_04_MASK 0x3F0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_AC_COUPLE_EN_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_AC_COUPLE_EN_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_PU_PMOS_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_PU_PMOS_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_RSVD_0PF8_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_RSVD_0PF8_12_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_PU_AGCDL2_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_PU_AGCDL2_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_PU_AGCDL1_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_PU_AGCDL1_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_PU_AGC_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8_PU_AGC_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PF9 */
+#define NIC0_SERDES0_LANE0_REGISTER_0PF9_PU_ACJTAG_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF9_PU_ACJTAG_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0PF9_IDAC_ACJTAG_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0PF9_IDAC_ACJTAG_MASK 0x6
+#define NIC0_SERDES0_LANE0_REGISTER_0PF9_RX_PLL_TEST_EN_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0PF9_RX_PLL_TEST_EN_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_0PF9_RX_PLL_VTSTGROUP_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PF9_RX_PLL_VTSTGROUP_MASK 0x1F0
+#define NIC0_SERDES0_LANE0_REGISTER_0PF9_RX_PLL_TESTMODE_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0PF9_RX_PLL_TESTMODE_MASK 0xE00
+#define NIC0_SERDES0_LANE0_REGISTER_0PF9_RSVD_0PF9_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PF9_RSVD_0PF9_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PFA */
+#define NIC0_SERDES0_LANE0_REGISTER_0PFA_RSVD_0PFA_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PFA_RSVD_0PFA_00_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0PFA_RX_VREFPDET_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0PFA_RX_VREFPDET_MASK 0xE
+#define NIC0_SERDES0_LANE0_REGISTER_0PFA_RSVD_0PFA_06_04_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PFA_RSVD_0PFA_06_04_MASK 0x70
+#define NIC0_SERDES0_LANE0_REGISTER_0PFA_RX_VREFVCOBUF_MA_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0PFA_RX_VREFVCOBUF_MA_MASK 0x380
+#define NIC0_SERDES0_LANE0_REGISTER_0PFA_RSVD_0PFA_12_10_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0PFA_RSVD_0PFA_12_10_MASK 0x1C00
+#define NIC0_SERDES0_LANE0_REGISTER_0PFA_RX_VVCOREG3_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0PFA_RX_VVCOREG3_MASK 0xE000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PFB */
+#define NIC0_SERDES0_LANE0_REGISTER_0PFB_RSVD_0PFB_04_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PFB_RSVD_0PFB_04_00_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_0PFB_RX_VPLLPMP2_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0PFB_RX_VPLLPMP2_MASK 0xE0
+#define NIC0_SERDES0_LANE0_REGISTER_0PFB_RSVD_0PFB_15_08_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0PFB_RSVD_0PFB_15_08_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PFC */
+#define NIC0_SERDES0_LANE0_REGISTER_0PFC_RSVD_0PFC_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PFC_RSVD_0PFC_00_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0PFC_RX_BYPASS_PLLPMP_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0PFC_RX_BYPASS_PLLPMP_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_0PFC_RSVD_0PFC_04_02_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0PFC_RSVD_0PFC_04_02_MASK 0x1C
+#define NIC0_SERDES0_LANE0_REGISTER_0PFC_RX_BYPASS_DIV2PI_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0PFC_RX_BYPASS_DIV2PI_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_0PFC_RSVD_0PFC_08_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0PFC_RSVD_0PFC_08_06_MASK 0x1C0
+#define NIC0_SERDES0_LANE0_REGISTER_0PFC_RX_PLL_VCO_RANGE_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0PFC_RX_PLL_VCO_RANGE_MASK 0xFE00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PFD */
+#define NIC0_SERDES0_LANE0_REGISTER_0PFD_RX_VCO_CURRENT_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PFD_RX_VCO_CURRENT_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_0PFD_RX_CHARGE_PUMP_CUR_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0PFD_RX_CHARGE_PUMP_CUR_MASK 0x38
+#define NIC0_SERDES0_LANE0_REGISTER_0PFD_PU_RX_PLL_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0PFD_PU_RX_PLL_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0PFD_RX_PLL_N_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0PFD_RX_PLL_N_MASK 0xFF80
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PFE */
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE_RSVD_0PFE_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE_RSVD_0PFE_00_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE_RX_LPF_RZ_SEL_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE_RX_LPF_RZ_SEL_MASK 0x6
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE_RX_LPF_R2_SEL_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE_RX_LPF_R2_SEL_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE_RX_LPF_CZ_SEL_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE_RX_LPF_CZ_SEL_MASK 0x30
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE_RX_LPF_C3_SEL_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE_RX_LPF_C3_SEL_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE_RX_LPF_C2_SEL_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE_RX_LPF_C2_SEL_MASK 0x180
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE_RSVD_0PFE_15_09_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE_RSVD_0PFE_15_09_MASK 0xFE00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0PFF */
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_RSVD_0PFF_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_RSVD_0PFF_00_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_PU_ADC_MA_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_PU_ADC_MA_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_PU_INTP_MA_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_PU_INTP_MA_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_RSVD_0PFF_04_03_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_RSVD_0PFF_04_03_MASK 0x18
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_PU_AGC_MA_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_PU_AGC_MA_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_RSVD_0PFF_11_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_RSVD_0PFF_11_06_MASK 0xFC0
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_PU_RX_BG_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_PU_RX_BG_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_RX_VBG_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF_RX_VBG_MASK 0xE000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N00 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N00_DFE_INIT_1_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N00_DFE_INIT_1_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N00_RSVD_0N00_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N00_RSVD_0N00_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N01 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N01_TLOOP_CONST_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N01_TLOOP_CONST_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0N01_DELTA_MIN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N01_DELTA_MIN_MASK 0x3F80
+#define NIC0_SERDES0_LANE0_REGISTER_0N01_DELTA_ADAPT_EN_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N01_DELTA_ADAPT_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0N01_ADC_RECAL_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N01_ADC_RECAL_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N02 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N02_AGC_PERIOD_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N02_AGC_PERIOD_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0N02_TARGET_CTRL_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0N02_TARGET_CTRL_MASK 0xFFF0
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N03 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N03_RX_NRZ_SD_THR_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N03_RX_NRZ_SD_THR_MASK 0x7FF
+#define NIC0_SERDES0_LANE0_REGISTER_0N03_RSVD_0N03_15_11_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0N03_RSVD_0N03_15_11_MASK 0xF800
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N04 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N04_RX_SD_CROSSOVER_COUNT_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N04_RX_SD_CROSSOVER_COUNT_MASK 0xFFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N04_RX_SD_CLK_CYCLES_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0N04_RX_SD_CLK_CYCLES_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N05 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N05_TIMER4_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N05_TIMER4_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N06 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N06_RSVD_0N06_11_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N06_RSVD_0N06_11_00_MASK 0xFFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N06_ITR_CNT4_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0N06_ITR_CNT4_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N07 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N07_DFE_INIT_2_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N07_DFE_INIT_2_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N07_RSVD_0N07_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N07_RSVD_0N07_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N08 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N08_MEAS_TIMER7_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N08_MEAS_TIMER7_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0N08_MEAS_TIMER6_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0N08_MEAS_TIMER6_MASK 0xF0
+#define NIC0_SERDES0_LANE0_REGISTER_0N08_MEAS_TIMER5_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N08_MEAS_TIMER5_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_0N08_ITR_CNT5_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0N08_ITR_CNT5_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N09 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N09_RSVD_0N09_14_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N09_RSVD_0N09_14_00_MASK 0x7FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N09_EM_MODE_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N09_EM_MODE_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N0B */
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B_NRZ_BP2_STATE_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B_NRZ_BP2_STATE_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B_RSVD_0N0B_05_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B_RSVD_0N0B_05_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B_RX_DFE_OVER_EN_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B_RX_DFE_OVER_EN_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B_NRZ_BP2_EN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B_NRZ_BP2_EN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B_NRZ_BP1_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B_NRZ_BP1_STATE_MASK 0x1F00
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B_RSVD_0N0B_14_13_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B_RSVD_0N0B_14_13_MASK 0x6000
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B_NRZ_BP1_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B_NRZ_BP1_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N0C */
+#define NIC0_SERDES0_LANE0_REGISTER_0N0C_RSVD_0N0C_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N0C_RSVD_0N0C_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0N0C_NRZ_PHY_READY_OW_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0N0C_NRZ_PHY_READY_OW_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_0N0C_NRZ_PHY_READY_OWEN_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0N0C_NRZ_PHY_READY_OWEN_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_0N0C_RSVD_0N0C_14_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0N0C_RSVD_0N0C_14_06_MASK 0x7FC0
+#define NIC0_SERDES0_LANE0_REGISTER_0N0C_NRZ_SM_CONT_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N0C_NRZ_SM_CONT_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N0D */
+#define NIC0_SERDES0_LANE0_REGISTER_0N0D_DELTA_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N0D_DELTA_VAL_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0N0D_RSVD_0N0D_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N0D_RSVD_0N0D_07_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N0D_NRZ_CURRENT_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N0D_NRZ_CURRENT_STATE_MASK 0x1F00
+#define NIC0_SERDES0_LANE0_REGISTER_0N0D_RSVD_0N0D_13_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0N0D_RSVD_0N0D_13_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0N0D_NRZ_BP2_REACHED_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N0D_NRZ_BP2_REACHED_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0N0D_NRZ_BP1_REACHED_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N0D_NRZ_BP1_REACHED_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N27 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N27_READ_FIXED_PAT_PLUS_MARGIN_BIT_11_8_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N27_READ_FIXED_PAT_PLUS_MARGIN_BIT_11_8_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0N27_READ_CTH_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0N27_READ_CTH_MASK 0xFFF0
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N28 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N28_READ_FIXED_PAT_MINUS_MARGIN_BIT_11_4_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N28_READ_FIXED_PAT_MINUS_MARGIN_BIT_11_4_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N28_READ_FIXED_PAT_PLUS_MARGIN_BIT_7_0_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N28_READ_FIXED_PAT_PLUS_MARGIN_BIT_7_0_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N29 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N29_RSVD_0N29_11_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N29_RSVD_0N29_11_00_MASK 0xFFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N29_READ_FIXED_PAT_MINUS_MARGIN_BIT_3_0_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0N29_READ_FIXED_PAT_MINUS_MARGIN_BIT_3_0_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N2A */
+#define NIC0_SERDES0_LANE0_REGISTER_0N2A_RX_READ_EM_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N2A_RX_READ_EM_MASK 0x7FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N2A_RSVD_0N2A_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N2A_RSVD_0N2A_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N2B */
+#define NIC0_SERDES0_LANE0_REGISTER_0N2B_RX_DFE_TAP_1_CURR_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N2B_RX_DFE_TAP_1_CURR_VAL_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0N2B_RSVD_0N2B_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N2B_RSVD_0N2B_07_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N2B_RSVD_0N2B_14_08_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N2B_RSVD_0N2B_14_08_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0N2B_RSVD_0N2B_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N2B_RSVD_0N2B_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N2C */
+#define NIC0_SERDES0_LANE0_REGISTER_0N2C_RX_DFE_TAP_3_CURR_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N2C_RX_DFE_TAP_3_CURR_VAL_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0N2C_RSVD_0N2C_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N2C_RSVD_0N2C_07_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N2C_RX_DFE_TAP_2_CURR_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N2C_RX_DFE_TAP_2_CURR_VAL_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0N2C_RSVD_0N2C_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N2C_RSVD_0N2C_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N2E */
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_RSVD_0N2E_01_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_RSVD_0N2E_01_00_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_NRZ_READ_PHY_READY_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_NRZ_READ_PHY_READY_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_NRZ_READ_SIG_DET_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_NRZ_READ_SIG_DET_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_RSVD_0N2E_05_04_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_RSVD_0N2E_05_04_MASK 0x30
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_RSVD_0N2E_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_RSVD_0N2E_06_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_READ_KF_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_READ_KF_MASK 0x180
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_RSVD_0N2E_11_09_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_RSVD_0N2E_11_09_MASK 0xE00
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_READ_KP_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_READ_KP_MASK 0x7000
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_RSVD_0N2E_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E_RSVD_0N2E_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N3B */
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RSVD_0N3B_04_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RSVD_0N3B_04_00_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RX_CDR_FREQ_OVER_VAL_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RX_CDR_FREQ_OVER_VAL_MASK 0x60
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RX_CDR_OVER_FREQ_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RX_CDR_OVER_FREQ_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RX_CDR_OVER_PH_K_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RX_CDR_OVER_PH_K_VAL_MASK 0x300
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RX_CDR_OVER_PH_K_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RX_CDR_OVER_PH_K_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RSVD_0N3B_11_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RSVD_0N3B_11_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RX_CDR_BW_OVER_VAL_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RX_CDR_BW_OVER_VAL_MASK 0x7000
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RX_CDR_OVER_BW_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B_RX_CDR_OVER_BW_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N4D */
+#define NIC0_SERDES0_LANE0_REGISTER_0N4D_NRZ_FREQ_INIT1_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N4D_NRZ_FREQ_INIT1_MASK 0x7FF
+#define NIC0_SERDES0_LANE0_REGISTER_0N4D_RSVD_0N4D_14_11_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0N4D_RSVD_0N4D_14_11_MASK 0x7800
+#define NIC0_SERDES0_LANE0_REGISTER_0N4D_RX_NRZ_CTLE_OVER_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N4D_RX_NRZ_CTLE_OVER_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N4E */
+#define NIC0_SERDES0_LANE0_REGISTER_0N4E_NRZ_FREQ_INIT2_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N4E_NRZ_FREQ_INIT2_MASK 0x7FF
+#define NIC0_SERDES0_LANE0_REGISTER_0N4E_RX_NRZ_CTLE_OVER_VAL_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0N4E_RX_NRZ_CTLE_OVER_VAL_MASK 0x3800
+#define NIC0_SERDES0_LANE0_REGISTER_0N4E_RSVD_0N4E_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N4E_RSVD_0N4E_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N4F */
+#define NIC0_SERDES0_LANE0_REGISTER_0N4F_EM_SEARCH_PARAM_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N4F_EM_SEARCH_PARAM_MASK 0xFFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N4F_DAC_SEL_OW_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0N4F_DAC_SEL_OW_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N50 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N50_EM_THR_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N50_EM_THR_MASK 0xFFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N50_RSVD_0N50_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0N50_RSVD_0N50_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N5D */
+#define NIC0_SERDES0_LANE0_REGISTER_0N5D_RX_DFE_TAP_2_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N5D_RX_DFE_TAP_2_VAL_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0N5D_RSVD_0N5D_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N5D_RSVD_0N5D_07_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N5D_RX_DFE_TAP_1_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N5D_RX_DFE_TAP_1_VAL_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0N5D_RSVD_0N5D_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N5D_RSVD_0N5D_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N5E */
+#define NIC0_SERDES0_LANE0_REGISTER_0N5E_RSVD_0N5E_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N5E_RSVD_0N5E_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N5E_RX_DFE_TAP_3_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N5E_RX_DFE_TAP_3_VAL_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0N5E_RSVD_0N5E_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N5E_RSVD_0N5E_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N60 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N60_TLOOP_CTRL4_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N60_TLOOP_CTRL4_MASK 0xFFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N60_RSVD_0N60_13_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0N60_RSVD_0N60_13_12_MASK 0x3000
+#define NIC0_SERDES0_LANE0_REGISTER_0N60_NRZ_SIG_DET_OW_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N60_NRZ_SIG_DET_OW_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0N60_NRZ_SIG_DET_OW_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N60_NRZ_SIG_DET_OW_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N61 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_NRZ_THETA2_ACC_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_NRZ_THETA2_ACC_OW_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_NRZ_THETA2_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_NRZ_THETA2_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_RSVD_0N61_09_08_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_RSVD_0N61_09_08_MASK 0x300
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_PRBS_CHKR_EN_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_PRBS_CHKR_EN_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_RSVD_0N61_11_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_RSVD_0N61_11_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_NRZ_PRBS_MODE_SEL_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_NRZ_PRBS_MODE_SEL_MASK 0x3000
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_PRBS_CHECK_FLIP_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_PRBS_CHECK_FLIP_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_PRBS_CNTR_RESET_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N61_PRBS_CNTR_RESET_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N62 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N62_NRZ_THETA4_ACC_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N62_NRZ_THETA4_ACC_OW_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0N62_NRZ_THETA4_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N62_NRZ_THETA4_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N62_NRZ_THETA3_ACC_OW_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N62_NRZ_THETA3_ACC_OW_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0N62_NRZ_THETA3_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N62_NRZ_THETA3_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N63 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N63_PH_OUT2_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N63_PH_OUT2_OW_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0N63_NRZ_THETA2_UPDATE_FLIP_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N63_NRZ_THETA2_UPDATE_FLIP_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N63_RSVD_0N63_15_08_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N63_RSVD_0N63_15_08_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N64 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N64_PH_OUT4_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N64_PH_OUT4_OW_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0N64_NRZ_THETA4_UPDATE_FLIP_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N64_NRZ_THETA4_UPDATE_FLIP_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N64_PH_OUT3_OW_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N64_PH_OUT3_OW_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0N64_NRZ_THETA3_UPDATE_FLIP_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N64_NRZ_THETA3_UPDATE_FLIP_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N65 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N65_RSVD_0N65_04_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N65_RSVD_0N65_04_00_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_0N65_NRZ_THETA4_UPDATE_MODE_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0N65_NRZ_THETA4_UPDATE_MODE_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_0N65_NRZ_THETA3_UPDATE_MODE_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0N65_NRZ_THETA3_UPDATE_MODE_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0N65_NRZ_THETA2_UPDATE_MODE_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N65_NRZ_THETA2_UPDATE_MODE_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N65_RSVD_0N65_15_08_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N65_RSVD_0N65_15_08_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N66 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N66_RX_NRZ_PRBS_READ_ERR_HIGH_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N66_RX_NRZ_PRBS_READ_ERR_HIGH_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N67 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N67_RX_NRZ_PRBS_READ_ERR_LOW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N67_RX_NRZ_PRBS_READ_ERR_LOW_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N6E */
+#define NIC0_SERDES0_LANE0_REGISTER_0N6E_READ_PH2_GRAY_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N6E_READ_PH2_GRAY_VAL_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0N6E_RSVD_0N6E_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N6E_RSVD_0N6E_07_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N6E_NRZ_READ_PH1_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N6E_NRZ_READ_PH1_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N6F */
+#define NIC0_SERDES0_LANE0_REGISTER_0N6F_READ_PH4_GRAY_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N6F_READ_PH4_GRAY_VAL_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0N6F_RSVD_0N6F_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N6F_RSVD_0N6F_07_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N6F_READ_PH3_GRAY_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N6F_READ_PH3_GRAY_VAL_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0N6F_RSVD_0N6F_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N6F_RSVD_0N6F_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N71 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N71_READ_THETA3_ACC_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N71_READ_THETA3_ACC_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0N71_RSVD_0N71_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N71_RSVD_0N71_07_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N71_READ_THETA2_ACC_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N71_READ_THETA2_ACC_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0N71_RSVD_0N71_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N71_RSVD_0N71_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N72 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N72_RSVD_0N72_05_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N72_RSVD_0N72_05_00_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_0N72_RSVD_0N72_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0N72_RSVD_0N72_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_0N72_READ_THETA4_ACC_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N72_READ_THETA4_ACC_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_0N72_RSVD_0N72_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N72_RSVD_0N72_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N73 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N73_READ_FREQ_ACCU_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N73_READ_FREQ_ACCU_MASK 0x7FF
+#define NIC0_SERDES0_LANE0_REGISTER_0N73_RSVD_0N73_15_11_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0N73_RSVD_0N73_15_11_MASK 0xF800
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N75 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N75_TLOOP_CTRL3_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N75_TLOOP_CTRL3_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0N75_TLOOP_CTRL2_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0N75_TLOOP_CTRL2_MASK 0xF0
+#define NIC0_SERDES0_LANE0_REGISTER_0N75_TLOOP_CTRL1_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N75_TLOOP_CTRL1_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_0N75_RSVD_0N75_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N75_RSVD_0N75_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N76 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N76_CTLE_MAP_TABLE_3_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N76_CTLE_MAP_TABLE_3_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N77 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N77_CTLE_MAP_TABLE_2_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N77_CTLE_MAP_TABLE_2_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N78 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N78_CTLE_MAP_TABLE_1_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N78_CTLE_MAP_TABLE_1_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N79 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N79_RX_HALF_RATE_EN_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N79_RX_HALF_RATE_EN_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0N79_RSVD_0N79_04_01_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0N79_RSVD_0N79_04_01_MASK 0x1E
+#define NIC0_SERDES0_LANE0_REGISTER_0N79_RX_NRZ_MODE_EN_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0N79_RX_NRZ_MODE_EN_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_0N79_RX_25G_EN_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0N79_RX_25G_EN_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0N79_RX_SUB_RATE_MODE_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N79_RX_SUB_RATE_MODE_MASK 0x180
+#define NIC0_SERDES0_LANE0_REGISTER_0N79_RSVD_0N79_15_09_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0N79_RSVD_0N79_15_09_MASK 0xFE00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N7A */
+#define NIC0_SERDES0_LANE0_REGISTER_0N7A_RSVD_0N7A_12_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N7A_RSVD_0N7A_12_00_MASK 0x1FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N7A_SPEED_MODE_ST2_EN_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0N7A_SPEED_MODE_ST2_EN_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0N7A_SPEED_MODE_ST2_SEL_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N7A_SPEED_MODE_ST2_SEL_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N7D */
+#define NIC0_SERDES0_LANE0_REGISTER_0N7D_NRZ_BP4_STATE_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N7D_NRZ_BP4_STATE_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_0N7D_RSVD_0N7D_06_05_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0N7D_RSVD_0N7D_06_05_MASK 0x60
+#define NIC0_SERDES0_LANE0_REGISTER_0N7D_NRZ_BP4_EN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N7D_NRZ_BP4_EN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N7D_NRZ_BP3_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N7D_NRZ_BP3_STATE_MASK 0x1F00
+#define NIC0_SERDES0_LANE0_REGISTER_0N7D_RSVD_0N7D_14_13_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0N7D_RSVD_0N7D_14_13_MASK 0x6000
+#define NIC0_SERDES0_LANE0_REGISTER_0N7D_NRZ_BP3_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N7D_NRZ_BP3_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N7E */
+#define NIC0_SERDES0_LANE0_REGISTER_0N7E_NRZ_BP6_STATE_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N7E_NRZ_BP6_STATE_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_0N7E_RSVD_0N7E_06_05_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0N7E_RSVD_0N7E_06_05_MASK 0x60
+#define NIC0_SERDES0_LANE0_REGISTER_0N7E_NRZ_BP6_EN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N7E_NRZ_BP6_EN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0N7E_NRZ_BP5_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0N7E_NRZ_BP5_STATE_MASK 0x1F00
+#define NIC0_SERDES0_LANE0_REGISTER_0N7E_RSVD_0N7E_14_13_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0N7E_RSVD_0N7E_14_13_MASK 0x6000
+#define NIC0_SERDES0_LANE0_REGISTER_0N7E_NRZ_BP5_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N7E_NRZ_BP5_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N7F */
+#define NIC0_SERDES0_LANE0_REGISTER_0N7F_RSVD_0N7F_05_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N7F_RSVD_0N7F_05_00_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_0N7F_RSVD_0N7F_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0N7F_RSVD_0N7F_06_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0N7F_RSVD_0N7F_08_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0N7F_RSVD_0N7F_08_07_MASK 0x180
+#define NIC0_SERDES0_LANE0_REGISTER_0N7F_CTLE_READ_CURR_VAL_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0N7F_CTLE_READ_CURR_VAL_MASK 0xE00
+#define NIC0_SERDES0_LANE0_REGISTER_0N7F_DAC_SEL_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0N7F_DAC_SEL_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N80 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N80_RSVD_0N80_08_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N80_RSVD_0N80_08_00_MASK 0x1FF
+#define NIC0_SERDES0_LANE0_REGISTER_0N80_DELTA_MAX_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0N80_DELTA_MAX_MASK 0xFE00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N81 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N81_NRZ_FREQ_INIT3_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N81_NRZ_FREQ_INIT3_MASK 0x7FF
+#define NIC0_SERDES0_LANE0_REGISTER_0N81_NRZ_SM_RESET_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0N81_NRZ_SM_RESET_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_0N81_RSVD_0N81_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0N81_RSVD_0N81_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N82 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N82_NRZ_FREQ_INIT4_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N82_NRZ_FREQ_INIT4_MASK 0x7FF
+#define NIC0_SERDES0_LANE0_REGISTER_0N82_RSVD_0N82_15_11_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0N82_RSVD_0N82_15_11_MASK 0xF800
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N83 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N83_DFE_INIT_3_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N83_DFE_INIT_3_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N83_RSVD_0N83_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N83_RSVD_0N83_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N84 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N84_DFE_INIT_4_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N84_DFE_INIT_4_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N84_RSVD_0N84_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N84_RSVD_0N84_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N85 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N85_DFE_INIT_5_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N85_DFE_INIT_5_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N85_RSVD_0N85_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N85_RSVD_0N85_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N86 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N86_DFE_INIT_6_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N86_DFE_INIT_6_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N86_RSVD_0N86_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N86_RSVD_0N86_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N87 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N87_DFE_INIT_7_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N87_DFE_INIT_7_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N87_RSVD_0N87_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N87_RSVD_0N87_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N88 */
+#define NIC0_SERDES0_LANE0_REGISTER_0N88_DFE_INIT_8_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N88_DFE_INIT_8_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N88_RSVD_0N88_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N88_RSVD_0N88_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N8C */
+#define NIC0_SERDES0_LANE0_REGISTER_0N8C_RSVD_0N8C_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N8C_RSVD_0N8C_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_0N8C_MAX_EM_ADAPT_OW_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0N8C_MAX_EM_ADAPT_OW_MASK 0x7FF8
+#define NIC0_SERDES0_LANE0_REGISTER_0N8C_MAX_EM_ADAPT_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N8C_MAX_EM_ADAPT_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0N8F */
+#define NIC0_SERDES0_LANE0_REGISTER_0N8F_RSVD_0N8F_11_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0N8F_RSVD_0N8F_11_00_MASK 0xFFF
+#define NIC0_SERDES0_LANE0_REGISTER_0N8F_NRZ_BP6_REACHED_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0N8F_NRZ_BP6_REACHED_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_0N8F_NRZ_BP5_REACHED_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0N8F_NRZ_BP5_REACHED_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0N8F_NRZ_BP4_REACHED_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0N8F_NRZ_BP4_REACHED_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0N8F_NRZ_BP3_REACHED_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0N8F_NRZ_BP3_REACHED_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0NF2 */
+#define NIC0_SERDES0_LANE0_REGISTER_0NF2_RSVD_0NF2_01_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0NF2_RSVD_0NF2_01_00_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_0NF2_RX_REFCLK_DIV4_INT_EN_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0NF2_RX_REFCLK_DIV4_INT_EN_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_0NF2_RSVD_0NF2_13_03_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0NF2_RSVD_0NF2_13_03_MASK 0x3FF8
+#define NIC0_SERDES0_LANE0_REGISTER_0NF2_TX_REFCLK_DIV4_INT_EN_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0NF2_TX_REFCLK_DIV4_INT_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0NF2_RSVD_0NF2_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0NF2_RSVD_0NF2_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0NF3 */
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_RSVD_0NF3_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_RSVD_0NF3_00_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_BM_VCO_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_BM_VCO_MASK 0x3E
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_EN2TO1_1_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_EN2TO1_1_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_EN1TO2_1_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_EN1TO2_1_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_VREFREFCLKBUF_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_VREFREFCLKBUF_MASK 0x700
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_VREF1P3REFCLKBUF_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_VREF1P3REFCLKBUF_MASK 0x3800
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_RSVD_0NF3_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_RSVD_0NF3_14_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_PU_TX_REFCLKBUF_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3_PU_TX_REFCLKBUF_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0NF6 */
+#define NIC0_SERDES0_LANE0_REGISTER_0NF6_RSVD_0NF6_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0NF6_RSVD_0NF6_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_0NF6_TX_TEST_EN_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0NF6_TX_TEST_EN_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_0NF6_TX_VTSTGROUP_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0NF6_TX_VTSTGROUP_MASK 0x1E00
+#define NIC0_SERDES0_LANE0_REGISTER_0NF6_TX_TESTMODE_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0NF6_TX_TESTMODE_MASK 0xE000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0NF7 */
+#define NIC0_SERDES0_LANE0_REGISTER_0NF7_RSVD_0NF7_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0NF7_RSVD_0NF7_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_0NF7_VDDRREG_IBIAS_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0NF7_VDDRREG_IBIAS_MASK 0x38
+#define NIC0_SERDES0_LANE0_REGISTER_0NF7_PU_HIMODE_VDDR_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0NF7_PU_HIMODE_VDDR_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0NF7_VREFVDRVBUF_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0NF7_VREFVDRVBUF_MASK 0x380
+#define NIC0_SERDES0_LANE0_REGISTER_0NF7_V1P3REGVDRVBUF_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0NF7_V1P3REGVDRVBUF_MASK 0x1C00
+#define NIC0_SERDES0_LANE0_REGISTER_0NF7_VDRV_1P3REG_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0NF7_VDRV_1P3REG_MASK 0xE000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0NF8 */
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_RSVD_0NF8_01_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_RSVD_0NF8_01_00_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_VDRV_VDDR3REG_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_VDRV_VDDR3REG_MASK 0x1C
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_VDRV_VDDR2REG_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_VDRV_VDDR2REG_MASK 0xE0
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_VDRV_VDDRREG_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_VDRV_VDDRREG_MASK 0x700
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_RSVD_0NF8_12_11_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_RSVD_0NF8_12_11_MASK 0x1800
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_PU_VDRV_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_PU_VDRV_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_TX_ENDCC_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_TX_ENDCC_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_RSVD_0NF8_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8_RSVD_0NF8_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0NF9 */
+#define NIC0_SERDES0_LANE0_REGISTER_0NF9_RSVD_0NF9_06_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0NF9_RSVD_0NF9_06_00_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_0NF9_TX_PLL_TEST_EN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0NF9_TX_PLL_TEST_EN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0NF9_TX_PLL_VTSTGROUP_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0NF9_TX_PLL_VTSTGROUP_MASK 0x1F00
+#define NIC0_SERDES0_LANE0_REGISTER_0NF9_TX_PLL_TESTMODE_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0NF9_TX_PLL_TESTMODE_MASK 0xE000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0NFA */
+#define NIC0_SERDES0_LANE0_REGISTER_0NFA_RSVD_0NFA_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0NFA_RSVD_0NFA_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_0NFA_TX_VREFPDET_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0NFA_TX_VREFPDET_MASK 0x70
+#define NIC0_SERDES0_LANE0_REGISTER_0NFA_TX_VREF1P3PDET_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0NFA_TX_VREF1P3PDET_MASK 0x380
+#define NIC0_SERDES0_LANE0_REGISTER_0NFA_TX_VREFVCOBUF_MA_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0NFA_TX_VREFVCOBUF_MA_MASK 0x1C00
+#define NIC0_SERDES0_LANE0_REGISTER_0NFA_TX_VREF1P3VCOBUF_MA_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0NFA_TX_VREF1P3VCOBUF_MA_MASK 0xE000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0NFB */
+#define NIC0_SERDES0_LANE0_REGISTER_0NFB_RSVD_0NFB_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0NFB_RSVD_0NFB_00_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0NFB_TX_VVCOREG3_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0NFB_TX_VVCOREG3_MASK 0xE
+#define NIC0_SERDES0_LANE0_REGISTER_0NFB_TX_VVCOREG1_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0NFB_TX_VVCOREG1_MASK 0x70
+#define NIC0_SERDES0_LANE0_REGISTER_0NFB_TX_VPLLPMP2_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0NFB_TX_VPLLPMP2_MASK 0x380
+#define NIC0_SERDES0_LANE0_REGISTER_0NFB_TX_VPLLPMP1_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0NFB_TX_VPLLPMP1_MASK 0x1C00
+#define NIC0_SERDES0_LANE0_REGISTER_0NFB_TX_VRVDD_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0NFB_TX_VRVDD_MASK 0xE000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0NFC */
+#define NIC0_SERDES0_LANE0_REGISTER_0NFC_RSVD_0NFC_01_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0NFC_RSVD_0NFC_01_00_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_0NFC_TX_BYPASS_PLLPMP_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0NFC_TX_BYPASS_PLLPMP_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_0NFC_RSVD_0NFC_08_03_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0NFC_RSVD_0NFC_08_03_MASK 0x1F8
+#define NIC0_SERDES0_LANE0_REGISTER_0NFC_TX_PLL_VCO_RANGE_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0NFC_TX_PLL_VCO_RANGE_MASK 0xFE00
+
+/* NIC0_SERDES0_LANE0_REGISTER_0NFD */
+#define NIC0_SERDES0_LANE0_REGISTER_0NFD_TX_VCO_CURRENT_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0NFD_TX_VCO_CURRENT_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_0NFD_TX_CHARGE_PUMP_CUR_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_0NFD_TX_CHARGE_PUMP_CUR_MASK 0x38
+#define NIC0_SERDES0_LANE0_REGISTER_0NFD_PU_TX_PLL_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0NFD_PU_TX_PLL_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0NFD_TX_PLL_N_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0NFD_TX_PLL_N_MASK 0xFF80
+
+/* NIC0_SERDES0_LANE0_REGISTER_0NFE */
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_TX_BYPASS_DIV2PI_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_TX_BYPASS_DIV2PI_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_RSVD_0NFE_03_01_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_RSVD_0NFE_03_01_MASK 0xE
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_TX_LPF_RZ_SEL_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_TX_LPF_RZ_SEL_MASK 0x30
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_TX_LPF_R2_SEL_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_TX_LPF_R2_SEL_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_TX_LPF_CZ_SEL_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_TX_LPF_CZ_SEL_MASK 0x180
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_TX_LPF_C3_SEL_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_TX_LPF_C3_SEL_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_TX_LPF_C2_SEL_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_TX_LPF_C2_SEL_MASK 0xC00
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_RSVD_0NFE_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_RSVD_0NFE_12_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_TX_BM_POFFDAC_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE_TX_BM_POFFDAC_MASK 0xE000
+
+/* NIC0_SERDES0_LANE0_REGISTER_0NFF */
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_RSVD_0NFF_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_RSVD_0NFF_00_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_TX_LOOPBACK_EN_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_TX_LOOPBACK_EN_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_TX_BM_NOFFDAC_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_TX_BM_NOFFDAC_MASK 0x1C
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_PU_VDRV_MA_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_PU_VDRV_MA_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_TX_RVDDCLAMP_EN_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_TX_RVDDCLAMP_EN_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_PU_TX_RVDDLOOP_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_PU_TX_RVDDLOOP_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_TX_CHPMPCLK_SEL_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_TX_CHPMPCLK_SEL_MASK 0x300
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_TX_RVDDVCO_EN_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_TX_RVDDVCO_EN_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_PU_TX_RVDD_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_PU_TX_RVDD_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_PU_TX_BG_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_PU_TX_BG_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_TX_VBG_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF_TX_VBG_MASK 0xE000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P00 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P00_RSVD_0P00_06_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P00_RSVD_0P00_06_00_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0P00_DFE_MODE_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P00_DFE_MODE_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0P00_DATA_THR_INIT_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P00_DATA_THR_INIT_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P00_PAM4_SM_RESET_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P00_PAM4_SM_RESET_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P01 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P01_CNTR_TARGET_INIT_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P01_CNTR_TARGET_INIT_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P02 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P02_CNTR_TARGET_FINAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P02_CNTR_TARGET_FINAL_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P03 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P03_RX_PAM4_SD_THR_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P03_RX_PAM4_SD_THR_MASK 0x7FF
+#define NIC0_SERDES0_LANE1_REGISTER_0P03_RSVD_0P03_15_11_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0P03_RSVD_0P03_15_11_MASK 0xF800
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P04 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P04_RSVD_0P04_04_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P04_RSVD_0P04_04_00_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_0P04_DFE_INIT_VAL_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0P04_DFE_INIT_VAL_MASK 0xFE0
+#define NIC0_SERDES0_LANE1_REGISTER_0P04_SD_PERIOD_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0P04_SD_PERIOD_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P05 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P05_RSVD_0P05_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P05_RSVD_0P05_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0P05_KP_S4_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P05_KP_S4_MASK 0x700
+#define NIC0_SERDES0_LANE1_REGISTER_0P05_RSVD_0P05_15_11_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0P05_RSVD_0P05_15_11_MASK 0xF800
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P06 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P06_KP_S6_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P06_KP_S6_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_0P06_RSVD_0P06_06_03_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0P06_RSVD_0P06_06_03_MASK 0x78
+#define NIC0_SERDES0_LANE1_REGISTER_0P06_KP_S5_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P06_KP_S5_MASK 0x380
+#define NIC0_SERDES0_LANE1_REGISTER_0P06_RSVD_0P06_11_10_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0P06_RSVD_0P06_11_10_MASK 0xC00
+#define NIC0_SERDES0_LANE1_REGISTER_0P06_ITERATION_COUNT_S4_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0P06_ITERATION_COUNT_S4_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P07 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P07_RSVD_0P07_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P07_RSVD_0P07_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_0P07_TIMER_MEAS_S6_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0P07_TIMER_MEAS_S6_MASK 0x78
+#define NIC0_SERDES0_LANE1_REGISTER_0P07_RSVD_0P07_10_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P07_RSVD_0P07_10_07_MASK 0x780
+#define NIC0_SERDES0_LANE1_REGISTER_0P07_TIMER_MEAS_S5_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0P07_TIMER_MEAS_S5_MASK 0x7800
+#define NIC0_SERDES0_LANE1_REGISTER_0P07_RSVD_0P07_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P07_RSVD_0P07_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P08 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P08_RSVD_0P08_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P08_RSVD_0P08_00_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0P08_FREQ_INIT_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0P08_FREQ_INIT_MASK 0xFFE
+#define NIC0_SERDES0_LANE1_REGISTER_0P08_RSVD_0P08_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0P08_RSVD_0P08_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P09 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P09_ITERATION_COUNT_S6_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P09_ITERATION_COUNT_S6_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0P09_RSVD_0P09_07_04_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0P09_RSVD_0P09_07_04_MASK 0xF0
+#define NIC0_SERDES0_LANE1_REGISTER_0P09_DAC_SETTLING_PERIOD_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P09_DAC_SETTLING_PERIOD_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0P09_ITERATION_COUNT_S5_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0P09_ITERATION_COUNT_S5_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P0A */
+#define NIC0_SERDES0_LANE1_REGISTER_0P0A_HF_PERIOD_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P0A_HF_PERIOD_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_0P0A_OVERFLOW_PERIOD_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0P0A_OVERFLOW_PERIOD_MASK 0x3E0
+#define NIC0_SERDES0_LANE1_REGISTER_0P0A_TIMER_MEAS_S7_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0P0A_TIMER_MEAS_S7_MASK 0x3C00
+#define NIC0_SERDES0_LANE1_REGISTER_0P0A_MU_MARGIN_S6_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P0A_MU_MARGIN_S6_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P0B */
+#define NIC0_SERDES0_LANE1_REGISTER_0P0B_HF_THR_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P0B_HF_THR_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0P0B_RSVD_0P0B_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P0B_RSVD_0P0B_07_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0P0B_OVERFLOW_THR_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P0B_OVERFLOW_THR_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P0B_RSVD_0P0B_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P0B_RSVD_0P0B_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P0C */
+#define NIC0_SERDES0_LANE1_REGISTER_0P0C_OVERFLOW_CNTR_UPPER_LIMIT_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P0C_OVERFLOW_CNTR_UPPER_LIMIT_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P0D */
+#define NIC0_SERDES0_LANE1_REGISTER_0P0D_OVERFLOW_CNTR_LOWER_LIMIT_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P0D_OVERFLOW_CNTR_LOWER_LIMIT_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P0E */
+#define NIC0_SERDES0_LANE1_REGISTER_0P0E_HF_CNTR_TARGET_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P0E_HF_CNTR_TARGET_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P0F */
+#define NIC0_SERDES0_LANE1_REGISTER_0P0F_RSVD_0P0F_13_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P0F_RSVD_0P0F_13_00_MASK 0x3FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0P0F_EM_CNTR_RESET_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P0F_EM_CNTR_RESET_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0P0F_DFE_FREEZE_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P0F_DFE_FREEZE_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P11 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P11_PAM4_BP2_STATE_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P11_PAM4_BP2_STATE_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_0P11_RSVD_0P11_07_05_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0P11_RSVD_0P11_07_05_MASK 0xE0
+#define NIC0_SERDES0_LANE1_REGISTER_0P11_PAM4_BP1_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P11_PAM4_BP1_STATE_MASK 0x1F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P11_PAM4_SM_CONT_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0P11_PAM4_SM_CONT_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0P11_PAM4_BP2_EN_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P11_PAM4_BP2_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0P11_PAM4_BP1_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P11_PAM4_BP1_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P12 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P12_FORCE_SM_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P12_FORCE_SM_VAL_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_0P12_FORCE_SM_VAL_EN_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0P12_FORCE_SM_VAL_EN_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_0P12_DELTA_OW_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0P12_DELTA_OW_MASK 0x1FC0
+#define NIC0_SERDES0_LANE1_REGISTER_0P12_DELTA_OWEN_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0P12_DELTA_OWEN_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0P12_CTH_OWEN_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P12_CTH_OWEN_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0P12_THS_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P12_THS_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P13 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P13_RSVD_0P13_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P13_RSVD_0P13_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0P13_THS_OW_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0P13_THS_OW_MASK 0xFFF0
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P15 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P15_CTH_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P15_CTH_OW_MASK 0xFFF
+#define NIC0_SERDES0_LANE1_REGISTER_0P15_RSVD_0P15_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0P15_RSVD_0P15_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P16 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P16_RSVD_0P16_06_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P16_RSVD_0P16_06_00_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0P16_HF_CNTR_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P16_HF_CNTR_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0P16_RSVD_0P16_13_08_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P16_RSVD_0P16_13_08_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P16_EM_BM1_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P16_EM_BM1_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P1F */
+#define NIC0_SERDES0_LANE1_REGISTER_0P1F_ADC_CAL_START_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P1F_ADC_CAL_START_OW_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0P1F_ADC_CAL_START_OWEN_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0P1F_ADC_CAL_START_OWEN_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_0P1F_FORCE_FREQ_OW_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0P1F_FORCE_FREQ_OW_MASK 0x1FFC
+#define NIC0_SERDES0_LANE1_REGISTER_0P1F_FORCE_FREQ_OWEN_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0P1F_FORCE_FREQ_OWEN_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0P1F_DTL_RELOAD_OW_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P1F_DTL_RELOAD_OW_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0P1F_DTL_RELOAD_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P1F_DTL_RELOAD_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P20 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KTHETA3_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KTHETA3_OW_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KTHETA3_OWEN_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KTHETA3_OWEN_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KTHETA2_OW_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KTHETA2_OW_MASK 0x18
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KTHETA2_OWEN_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KTHETA2_OWEN_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KP_OW_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KP_OW_MASK 0x1C0
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KP_OWEN_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KP_OWEN_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KF_OW_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KF_OW_MASK 0xC00
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KF_OWEN_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_KF_OWEN_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_MU_MARGIN_OW_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_MU_MARGIN_OW_MASK 0x6000
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_MU_MARGIN_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P20_MU_MARGIN_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P21 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_RSVD_0P21_01_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_RSVD_0P21_01_00_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_MARGIN_PAT_DIS_OW_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_MARGIN_PAT_DIS_OW_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_MARGIN_PAT_DIS_OWEN_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_MARGIN_PAT_DIS_OWEN_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_RX_PAM4_CTLE_OVER_VAL_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_RX_PAM4_CTLE_OVER_VAL_MASK 0x70
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_RX_PAM4_CTLE_OVER_EN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_RX_PAM4_CTLE_OVER_EN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_DAC_SEL_OW_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_DAC_SEL_OW_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_DAC_SEL_OWEN_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_DAC_SEL_OWEN_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_KTHETA4_OW_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_KTHETA4_OW_MASK 0x6000
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_KTHETA4_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P21_KTHETA4_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P23 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P23_RSVD_0P23_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P23_RSVD_0P23_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0P23_PAM4_PHY_READY_OW_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0P23_PAM4_PHY_READY_OW_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_0P23_PAM4_PHY_READY_OWEN_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0P23_PAM4_PHY_READY_OWEN_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_0P23_RSVD_0P23_15_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0P23_RSVD_0P23_15_06_MASK 0xFFC0
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P24 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P24_PAM4_SIG_DET_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P24_PAM4_SIG_DET_OW_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0P24_PAM4_SIG_DET_OWEN_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0P24_PAM4_SIG_DET_OWEN_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_0P24_RSVD_0P24_15_02_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0P24_RSVD_0P24_15_02_MASK 0xFFFC
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P28 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P28_RSVD_0P28_04_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P28_RSVD_0P28_04_00_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_0P28_READ_DAC_SEL_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0P28_READ_DAC_SEL_MASK 0x1E0
+#define NIC0_SERDES0_LANE1_REGISTER_0P28_PAM4_CURRENT_STATE_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0P28_PAM4_CURRENT_STATE_MASK 0x3E00
+#define NIC0_SERDES0_LANE1_REGISTER_0P28_PAM4_BP2_REACHED_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P28_PAM4_BP2_REACHED_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0P28_PAM4_BP1_REACHED_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P28_PAM4_BP1_REACHED_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P2D */
+#define NIC0_SERDES0_LANE1_REGISTER_0P2D_READ_STATE_CNTR_HIGH_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P2D_READ_STATE_CNTR_HIGH_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P2E */
+#define NIC0_SERDES0_LANE1_REGISTER_0P2E_READ_STATE_CNTR_LOW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P2E_READ_STATE_CNTR_LOW_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P2F */
+#define NIC0_SERDES0_LANE1_REGISTER_0P2F_RSVD_0P2F_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P2F_RSVD_0P2F_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0P2F_READ_THS_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0P2F_READ_THS_MASK 0xFFF0
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P32 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P32_READ_MINUS_MARGIN_MSB_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P32_READ_MINUS_MARGIN_MSB_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0P32_READ_PLUS_MARGIN_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0P32_READ_PLUS_MARGIN_MASK 0xFFF0
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P33 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P33_RSVD_0P33_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P33_RSVD_0P33_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0P33_READ_MINUS_MARGIN_LSB_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P33_READ_MINUS_MARGIN_LSB_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P36 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P36_READ_FIXED_PAT_PLUS_MARGIN_MSB_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P36_READ_FIXED_PAT_PLUS_MARGIN_MSB_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0P36_RSVD_0P36_11_08_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P36_RSVD_0P36_11_08_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0P36_PAM4_BP_6_REACHED_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0P36_PAM4_BP_6_REACHED_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_0P36_PAM4_BP_5_REACHED_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0P36_PAM4_BP_5_REACHED_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0P36_PAM4_BP_4_REACHED_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P36_PAM4_BP_4_REACHED_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0P36_PAM4_BP_3_REACHED_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P36_PAM4_BP_3_REACHED_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P37 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P37_READ_FIXED_PAT_MINUS_MARGIN_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P37_READ_FIXED_PAT_MINUS_MARGIN_MASK 0xFFF
+#define NIC0_SERDES0_LANE1_REGISTER_0P37_READ_FIXED_PAT_PLUS_MARGIN_LSB_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0P37_READ_FIXED_PAT_PLUS_MARGIN_LSB_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P38 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P38_READ_EM_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P38_READ_EM_MASK 0x7FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0P38_RSVD_0P38_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P38_RSVD_0P38_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P40 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P40_READ_FM1_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P40_READ_FM1_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0P40_READ_DELTA_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P40_READ_DELTA_MASK 0x3F80
+#define NIC0_SERDES0_LANE1_REGISTER_0P40_RSVD_0P40_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P40_RSVD_0P40_14_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0P40_READ_PHY_READY_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P40_READ_PHY_READY_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P41 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_RSVD_0P41_01_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_RSVD_0P41_01_00_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_THETA4_UPDATE_FLIP_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_THETA4_UPDATE_FLIP_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_THETA3_UPDATE_FLIP_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_THETA3_UPDATE_FLIP_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_THETA2_UPDATE_FLIP_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_THETA2_UPDATE_FLIP_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_RSVD_0P41_09_05_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_RSVD_0P41_09_05_MASK 0x3E0
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_THETA4_UPDATE_MODE_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_THETA4_UPDATE_MODE_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_THETA3_UPDATE_MODE_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_THETA3_UPDATE_MODE_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_THETA2_UPDATE_MODE_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_THETA2_UPDATE_MODE_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_RSVD_0P41_14_13_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_RSVD_0P41_14_13_MASK 0x6000
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_PAM4_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P41_PAM4_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P42 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_RX_GRAYCODE_EN_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_RX_GRAYCODE_EN_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_RX_PRECODE_EN_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_RX_PRECODE_EN_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR8_EN_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR8_EN_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR7_EN_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR7_EN_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR6_EN_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR6_EN_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR5_EN_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR5_EN_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR4_EN_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR4_EN_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR3_EN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR3_EN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR2_EN_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR2_EN_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR1_EN_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_CNTR1_EN_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_RSVD_0P42_15_10_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0P42_RSVD_0P42_15_10_MASK 0xFC00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P43 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_PRBS_SYNC_CNTR_RESET_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_PRBS_SYNC_CNTR_RESET_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_RX_PRBS_AUTO_SYNC_EN_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_RX_PRBS_AUTO_SYNC_EN_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_RX_PRBS_FORCE_RELOAD_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_RX_PRBS_FORCE_RELOAD_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_PU_PRBS_SYNC_CHKR_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_PU_PRBS_SYNC_CHKR_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_PU_PRBS_CHKR_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_PU_PRBS_CHKR_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_PRBS_MODE_SEL_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_PRBS_MODE_SEL_MASK 0x60
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_RX_DATA_FLIP_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_RX_DATA_FLIP_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_RX_DATA_FW_FLIP_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_RX_DATA_FW_FLIP_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_PRBS_CHECK_CNTR_RESET_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_PRBS_CHECK_CNTR_RESET_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_RSVD_0P43_14_10_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_RSVD_0P43_14_10_MASK 0x7C00
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_RX_SWAP_MSB_LSB_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P43_RX_SWAP_MSB_LSB_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P44 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P44_RSVD_0P44_01_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P44_RSVD_0P44_01_00_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_0P44_PRBS_SYNC_LOSS_THR_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0P44_PRBS_SYNC_LOSS_THR_MASK 0xFC
+#define NIC0_SERDES0_LANE1_REGISTER_0P44_PRBS_MISMATCH_THR_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P44_PRBS_MISMATCH_THR_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P45 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P45_RX_ASIC_DATA_FLIP_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P45_RX_ASIC_DATA_FLIP_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0P45_RSVD_0P45_02_01_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0P45_RSVD_0P45_02_01_MASK 0x6
+#define NIC0_SERDES0_LANE1_REGISTER_0P45_FIXED_PAT_MODE_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0P45_FIXED_PAT_MODE_MASK 0x78
+#define NIC0_SERDES0_LANE1_REGISTER_0P45_RSVD_0P45_09_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P45_RSVD_0P45_09_07_MASK 0x380
+#define NIC0_SERDES0_LANE1_REGISTER_0P45_PRBS_PAT_CNTR_RESET_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0P45_PRBS_PAT_CNTR_RESET_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_0P45_PRBS_SYNC_THR_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0P45_PRBS_SYNC_THR_MASK 0xF800
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P46 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P46_THETA2_ACC_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P46_THETA2_ACC_OW_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0P46_THETA2_ACC_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P46_THETA2_ACC_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0P46_PH1_ACC_OW_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P46_PH1_ACC_OW_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P46_PH1_ACC_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P46_PH1_ACC_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P47 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P47_THETA4_ACC_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P47_THETA4_ACC_OW_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0P47_THETA4_ACC_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P47_THETA4_ACC_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0P47_THETA3_ACC_OW_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P47_THETA3_ACC_OW_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P47_THETA3_ACC_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P47_THETA3_ACC_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P48 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P48_AGC_SETTING2_MSB_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P48_AGC_SETTING2_MSB_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0P48_AGC_SETTING1_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0P48_AGC_SETTING1_MASK 0x3F0
+#define NIC0_SERDES0_LANE1_REGISTER_0P48_AGC_SETTING0_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0P48_AGC_SETTING0_MASK 0xFC00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P49 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P49_AGC_SETTING5_MSB_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P49_AGC_SETTING5_MSB_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_0P49_AGC_SETTING4_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0P49_AGC_SETTING4_MASK 0xFC
+#define NIC0_SERDES0_LANE1_REGISTER_0P49_AGC_SETTING3_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P49_AGC_SETTING3_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P49_AGC_SETTING2_LSB_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P49_AGC_SETTING2_LSB_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P4A */
+#define NIC0_SERDES0_LANE1_REGISTER_0P4A_AGC_SETTING7_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P4A_AGC_SETTING7_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_0P4A_AGC_SETTING6_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0P4A_AGC_SETTING6_MASK 0xFC0
+#define NIC0_SERDES0_LANE1_REGISTER_0P4A_AGC_SETTING5_LSB_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0P4A_AGC_SETTING5_LSB_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P4B */
+#define NIC0_SERDES0_LANE1_REGISTER_0P4B_SD_CNTR_LIMIT_MSB_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P4B_SD_CNTR_LIMIT_MSB_MASK 0x7FF
+#define NIC0_SERDES0_LANE1_REGISTER_0P4B_RX_FREQ_EN_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0P4B_RX_FREQ_EN_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_0P4B_TOP_ROTR_EN_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0P4B_TOP_ROTR_EN_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_0P4B_DTL_LOST_LOCK_MODE_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0P4B_DTL_LOST_LOCK_MODE_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0P4B_RSVD_0P4B_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P4B_RSVD_0P4B_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P4C */
+#define NIC0_SERDES0_LANE1_REGISTER_0P4C_RSVD_0P4C_06_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P4C_RSVD_0P4C_06_00_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0P4C_SD_CNTR_LIMIT_LSB_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P4C_SD_CNTR_LIMIT_LSB_MASK 0xFF80
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P4E */
+#define NIC0_SERDES0_LANE1_REGISTER_0P4E_RX_PRBS_ERR_CHKR_MSB_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P4E_RX_PRBS_ERR_CHKR_MSB_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P4F */
+#define NIC0_SERDES0_LANE1_REGISTER_0P4F_RX_PRBS_ERR_CHKR_LSB_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P4F_RX_PRBS_ERR_CHKR_LSB_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P50 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P50_PRBS_READ_SYNC_ERR_CNTR_MSB_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P50_PRBS_READ_SYNC_ERR_CNTR_MSB_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P51 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P51_PRBS_READ_SYNC_ERR_CNTR_LSB_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P51_PRBS_READ_SYNC_ERR_CNTR_LSB_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P6A */
+#define NIC0_SERDES0_LANE1_REGISTER_0P6A_RSVD_0P6A_06_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P6A_RSVD_0P6A_06_00_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0P6A_READ_SIG_DET_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P6A_READ_SIG_DET_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0P6A_RSVD_0P6A_14_08_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P6A_RSVD_0P6A_14_08_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P6A_RX_READ_PHY_READY_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P6A_RX_READ_PHY_READY_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P6C */
+#define NIC0_SERDES0_LANE1_REGISTER_0P6C_READ_THETA2_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P6C_READ_THETA2_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0P6C_RSVD_0P6C_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P6C_RSVD_0P6C_07_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0P6C_READ_PH1_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P6C_READ_PH1_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P6D */
+#define NIC0_SERDES0_LANE1_REGISTER_0P6D_READ_THETA4_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P6D_READ_THETA4_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0P6D_RSVD_0P6D_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P6D_RSVD_0P6D_07_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0P6D_READ_THETA3_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P6D_READ_THETA3_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P6D_PRBS_SYNC_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P6D_PRBS_SYNC_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P6E */
+#define NIC0_SERDES0_LANE1_REGISTER_0P6E_RSVD_0P6E_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P6E_RSVD_0P6E_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0P6E_READOUT_CAPTURE_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P6E_READOUT_CAPTURE_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_0P6E_READOUT_SYNC_EN_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0P6E_READOUT_SYNC_EN_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_0P6E_RSVD_0P6E_15_10_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0P6E_RSVD_0P6E_15_10_MASK 0xFC00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P73 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P73_READ_FREQ_ACC_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P73_READ_FREQ_ACC_MASK 0x7FF
+#define NIC0_SERDES0_LANE1_REGISTER_0P73_RSVD_0P73_15_11_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0P73_RSVD_0P73_15_11_MASK 0xF800
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P74 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P74_READ_PH_WANDER_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P74_READ_PH_WANDER_MASK 0x7FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0P74_CORR_CNTR_FREEZE_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P74_CORR_CNTR_FREEZE_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P79 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P79_RSVD_0P79_12_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P79_RSVD_0P79_12_00_MASK 0x1FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0P79_TED_QUAL_OFF_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0P79_TED_QUAL_OFF_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0P79_TED12_EN_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P79_TED12_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0P79_RSVD_0P79_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P79_RSVD_0P79_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P80 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P80_PAM4_BP6_STATE_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P80_PAM4_BP6_STATE_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_0P80_RSVD_0P80_06_05_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0P80_RSVD_0P80_06_05_MASK 0x60
+#define NIC0_SERDES0_LANE1_REGISTER_0P80_PAM4_BP6_EN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P80_PAM4_BP6_EN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0P80_PAM4_BP5_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P80_PAM4_BP5_STATE_MASK 0x1F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P80_RSVD_0P80_14_13_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0P80_RSVD_0P80_14_13_MASK 0x6000
+#define NIC0_SERDES0_LANE1_REGISTER_0P80_PAM4_BP5_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P80_PAM4_BP5_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P81 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P81_COUNT_0_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P81_COUNT_0_OW_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P82 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P82_COUNT_POS_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P82_COUNT_POS_OW_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P83 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P83_RSVD_0P83_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P83_RSVD_0P83_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_0P83_C_PLUS_MARGIN_OW_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0P83_C_PLUS_MARGIN_OW_MASK 0x7FF8
+#define NIC0_SERDES0_LANE1_REGISTER_0P83_RSVD_0P83_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P83_RSVD_0P83_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P8F */
+#define NIC0_SERDES0_LANE1_REGISTER_0P8F_PAM4_BP4_STATE_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P8F_PAM4_BP4_STATE_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_0P8F_RSVD_0P8F_06_05_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0P8F_RSVD_0P8F_06_05_MASK 0x60
+#define NIC0_SERDES0_LANE1_REGISTER_0P8F_PAM4_BP4_EN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P8F_PAM4_BP4_EN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0P8F_PAM4_BP3_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P8F_PAM4_BP3_STATE_MASK 0x1F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P8F_RSVD_0P8F_14_13_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0P8F_RSVD_0P8F_14_13_MASK 0x6000
+#define NIC0_SERDES0_LANE1_REGISTER_0P8F_PAM4_BP3_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P8F_PAM4_BP3_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P94 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P94_MM_F1_FGT_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P94_MM_F1_FGT_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_0P94_MM_LEV_UPDATE_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0P94_MM_LEV_UPDATE_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0P94_MM_POL_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0P94_MM_POL_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0P94_MM_F0_FGT_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P94_MM_F0_FGT_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P94_MM_QUALI_MODE_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P94_MM_QUALI_MODE_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0P94_MM_DTL_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0P94_MM_DTL_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P95 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P95_MM_QUANT_LEV1_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P95_MM_QUANT_LEV1_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_0P95_RSVD_0P95_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0P95_RSVD_0P95_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_0P95_MM_QUANT_LEV0_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P95_MM_QUANT_LEV0_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P95_RSVD_0P95_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P95_RSVD_0P95_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P96 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P96_MM_QUANT_LEV3_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P96_MM_QUANT_LEV3_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_0P96_RSVD_0P96_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0P96_RSVD_0P96_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_0P96_MM_QUANT_LEV2_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P96_MM_QUANT_LEV2_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P96_RSVD_0P96_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P96_RSVD_0P96_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P97 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P97_MM_QUANT_LEV5_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P97_MM_QUANT_LEV5_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_0P97_RSVD_0P97_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0P97_RSVD_0P97_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_0P97_MM_QUANT_LEV4_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P97_MM_QUANT_LEV4_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P97_RSVD_0P97_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P97_RSVD_0P97_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P98 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P98_MM_QUANT_LEV7_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P98_MM_QUANT_LEV7_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_0P98_RSVD_0P98_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0P98_RSVD_0P98_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_0P98_MM_QUANT_LEV6_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P98_MM_QUANT_LEV6_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P98_RSVD_0P98_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P98_RSVD_0P98_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P99 */
+#define NIC0_SERDES0_LANE1_REGISTER_0P99_MM_QUANT_LEV9_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P99_MM_QUANT_LEV9_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_0P99_RSVD_0P99_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0P99_RSVD_0P99_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_0P99_MM_QUANT_LEV8_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P99_MM_QUANT_LEV8_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P99_RSVD_0P99_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P99_RSVD_0P99_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P9A */
+#define NIC0_SERDES0_LANE1_REGISTER_0P9A_MM_QUANT_LEV11_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P9A_MM_QUANT_LEV11_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_0P9A_RSVD_0P9A_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0P9A_RSVD_0P9A_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_0P9A_MM_QUANT_LEV10_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P9A_MM_QUANT_LEV10_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P9A_RSVD_0P9A_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P9A_RSVD_0P9A_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0P9B */
+#define NIC0_SERDES0_LANE1_REGISTER_0P9B_RSVD_0P9B_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0P9B_RSVD_0P9B_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0P9B_MM_QUANT_LEV12_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0P9B_MM_QUANT_LEV12_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_0P9B_RSVD_0P9B_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0P9B_RSVD_0P9B_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PA0 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_SPEED_MODE_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_SPEED_MODE_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_PAM4_TEST_PAT_MODE_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_PAM4_TEST_PAT_MODE_MASK 0xC
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_RSVD_0PA0_04_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_RSVD_0PA0_04_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_ANA_OUT_FLIP_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_ANA_OUT_FLIP_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_RSVD_0PA0_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_RSVD_0PA0_06_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_DATA_POL_FLIP_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_DATA_POL_FLIP_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_PRBS_MODE_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_PRBS_MODE_MASK 0x300
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_PRBS_GEN_ERR_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_PRBS_GEN_ERR_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_PRBS_GEN_EN_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_PRBS_GEN_EN_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_RSVD_0PA0_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_RSVD_0PA0_12_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_PAM4_TEST_EN_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_PAM4_TEST_EN_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_PRBS_CLK_EN_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_PRBS_CLK_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_TEST_DATA_SRC_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0_TX_TEST_DATA_SRC_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PA1 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PA1_TX_TEST_PAT_3_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PA1_TX_TEST_PAT_3_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PA2 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PA2_TX_TEST_PAT_2_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PA2_TX_TEST_PAT_2_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PA3 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PA3_TX_TEST_PAT_1_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PA3_TX_TEST_PAT_1_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PA4 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PA4_TX_TEST_PAT_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PA4_TX_TEST_PAT_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PA5 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PA5_TX_PRE_2_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PA5_TX_PRE_2_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0PA5_TX_PRE_2_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PA5_TX_PRE_2_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PA6 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PA6_TX_PRE_2_3X_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PA6_TX_PRE_2_3X_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0PA6_TX_PRE_2_3X_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PA6_TX_PRE_2_3X_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PA7 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PA7_TX_PRE_1_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PA7_TX_PRE_1_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0PA7_TX_PRE_1_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PA7_TX_PRE_1_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PA8 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PA8_TX_PRE_1_3X_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PA8_TX_PRE_1_3X_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0PA8_TX_PRE_1_3X_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PA8_TX_PRE_1_3X_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PA9 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PA9_TX_MAIN_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PA9_TX_MAIN_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0PA9_TX_MAIN_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PA9_TX_MAIN_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PAA */
+#define NIC0_SERDES0_LANE1_REGISTER_0PAA_TX_MAIN_3X_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PAA_TX_MAIN_3X_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0PAA_TX_MAIN_3X_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PAA_TX_MAIN_3X_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PAB */
+#define NIC0_SERDES0_LANE1_REGISTER_0PAB_TX_POST_1_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PAB_TX_POST_1_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0PAB_TX_POST_1_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PAB_TX_POST_1_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PAC */
+#define NIC0_SERDES0_LANE1_REGISTER_0PAC_TX_POST_1_3X_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PAC_TX_POST_1_3X_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0PAC_TX_POST_1_3X_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PAC_TX_POST_1_3X_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PAD */
+#define NIC0_SERDES0_LANE1_REGISTER_0PAD_TX_POST_2_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PAD_TX_POST_2_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0PAD_TX_POST_2_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PAD_TX_POST_2_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PAE */
+#define NIC0_SERDES0_LANE1_REGISTER_0PAE_TX_POST_2_3X_COMP_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PAE_TX_POST_2_3X_COMP_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0PAE_TX_POST_2_3X_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PAE_TX_POST_2_3X_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PAF */
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_RSVD_0PAF_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_RSVD_0PAF_00_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_PRE2_SCALE_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_PRE2_SCALE_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_PRE1_SCALE_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_PRE1_SCALE_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_MAIN_SCALE_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_MAIN_SCALE_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_POST1_SCALE_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_POST1_SCALE_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_POST2_SCALE_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_POST2_SCALE_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_RSVD_0PAF_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_RSVD_0PAF_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_PRECODE_EN_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_PRECODE_EN_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_GRAYCODE_EN_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_GRAYCODE_EN_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_SWAP_MSB_LSB_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_SWAP_MSB_LSB_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_PRE2_AUTO_SEL_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_PRE2_AUTO_SEL_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_PRE1_AUTO_SEL_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_PRE1_AUTO_SEL_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_MAIN_AUTO_SEL_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_MAIN_AUTO_SEL_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_POST1_AUTO_SEL_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_POST1_AUTO_SEL_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_POST2_AUTO_SEL_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF_TX_POST2_AUTO_SEL_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PB0 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_TX_HALF_RATE_EN_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_TX_HALF_RATE_EN_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_TX_NRZ_MODE_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_TX_NRZ_MODE_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_RSVD_0PB0_09_02_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_RSVD_0PB0_09_02_MASK 0x3FC
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_TX_NRZ_PRBS_GERR_EN_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_TX_NRZ_PRBS_GERR_EN_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_TX_NRZ_PRBS_GEN_EN_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_TX_NRZ_PRBS_GEN_EN_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_RSVD_0PB0_13_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_RSVD_0PB0_13_12_MASK 0x3000
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_TX_NRZ_PRBS_CLK_EN_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_TX_NRZ_PRBS_CLK_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_RSVD_0PB0_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0_RSVD_0PB0_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PB1 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PB1_TX_POST6_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PB1_TX_POST6_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0PB1_TX_POST5_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PB1_TX_POST5_MASK 0xF0
+#define NIC0_SERDES0_LANE1_REGISTER_0PB1_TX_POST4_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PB1_TX_POST4_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0PB1_TX_POST3_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PB1_TX_POST3_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PB2 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PB2_RSVD_0PB2_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PB2_RSVD_0PB2_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0PB2_TX_POST8_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PB2_TX_POST8_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0PB2_TX_POST7_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PB2_TX_POST7_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PB3 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PB3_KR_SM_COEF_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PB3_KR_SM_COEF_0_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_0PB3_RSVD_0PB3_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0PB3_RSVD_0PB3_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_0PB3_KR_SM_COEF_1_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PB3_KR_SM_COEF_1_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_0PB3_RSVD_0PB3_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0PB3_RSVD_0PB3_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PC1 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PC1_AGC_DEGEN_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PC1_AGC_DEGEN_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0PC1_RSVD_0PC1_15_08_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PC1_RSVD_0PC1_15_08_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PC3 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PC3_EOM_TEST_EN_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PC3_EOM_TEST_EN_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0PC3_EOM_DLL_CAL_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0PC3_EOM_DLL_CAL_MASK 0xE
+#define NIC0_SERDES0_LANE1_REGISTER_0PC3_EOM_DLL_CTRL_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PC3_EOM_DLL_CTRL_MASK 0xFFF0
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PC4 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PC4_DEGENDL9_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PC4_DEGENDL9_0_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0PC4_DEGENDL9_1_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PC4_DEGENDL9_1_MASK 0xF0
+#define NIC0_SERDES0_LANE1_REGISTER_0PC4_DEGENDL8_0_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PC4_DEGENDL8_0_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0PC4_DEGENDL8_1_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PC4_DEGENDL8_1_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PC9 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PC9_VREF0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PC9_VREF0_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0PC9_EOM_MUX_CTRL_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0PC9_EOM_MUX_CTRL_MASK 0x780
+#define NIC0_SERDES0_LANE1_REGISTER_0PC9_RSVD_0PC9_15_11_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0PC9_RSVD_0PC9_15_11_MASK 0xF800
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PCA */
+#define NIC0_SERDES0_LANE1_REGISTER_0PCA_HPF_MODE_SEL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PCA_HPF_MODE_SEL_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_0PCA_VCOMREFSEL_EX_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0PCA_VCOMREFSEL_EX_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_0PCA_SKEF_VAL_MSB_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0PCA_SKEF_VAL_MSB_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_0PCA_ATTN_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PCA_ATTN_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_0PCA_RSVD_0PCA_15_05_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0PCA_RSVD_0PCA_15_05_MASK 0xFFE0
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PCC */
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC_RSVD_0PCC_09_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC_RSVD_0PCC_09_00_MASK 0x3FF
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC_EN2TO1_4_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC_EN2TO1_4_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC_EN1TO2_4_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC_EN1TO2_4_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC_EN2TO1_3_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC_EN2TO1_3_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC_EN1TO2_3_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC_EN1TO2_3_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC_EN2TO1_2_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC_EN2TO1_2_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC_EN1TO2_2_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC_EN1TO2_2_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PCD */
+#define NIC0_SERDES0_LANE1_REGISTER_0PCD_RSVD_0PCD_06_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PCD_RSVD_0PCD_06_00_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0PCD_REFCLK_SRC_SEL_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0PCD_REFCLK_SRC_SEL_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0PCD_VGAVDSAT_SUM3_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PCD_VGAVDSAT_SUM3_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0PCD_VGAVDSAT_MAIN3_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PCD_VGAVDSAT_MAIN3_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PCF */
+#define NIC0_SERDES0_LANE1_REGISTER_0PCF_EOM_DLL_SEG_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PCF_EOM_DLL_SEG_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_0PCF_RSVD_0PCF_15_02_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0PCF_RSVD_0PCF_15_02_MASK 0xFFFC
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PD8 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PD8_RSVD_0PD8_13_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PD8_RSVD_0PD8_13_00_MASK 0x3FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0PD8_RSVD_0PD8_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0PD8_RSVD_0PD8_14_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0PD8_PU_ADCCAL_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0PD8_PU_ADCCAL_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PD9 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PD9_ADC_ROW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PD9_ADC_ROW_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0PD9_RSVD_0PD9_15_04_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PD9_RSVD_0PD9_15_04_MASK 0xFFF0
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PE5 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PE5_RSVD_0PE5_05_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PE5_RSVD_0PE5_05_00_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_0PE5_RX_TEST_EN_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0PE5_RX_TEST_EN_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0PE5_RX_VTSTGROUP_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0PE5_RX_VTSTGROUP_MASK 0x1F80
+#define NIC0_SERDES0_LANE1_REGISTER_0PE5_RX_TESTMODE_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0PE5_RX_TESTMODE_MASK 0xE000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PE6 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_EDGE4_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_EDGE4_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_RSVD_0PE6_03_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_RSVD_0PE6_03_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_EDGE3_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_EDGE3_MASK 0x70
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_RSVD_0PE6_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_RSVD_0PE6_07_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_EDGE2_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_EDGE2_MASK 0x700
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_RSVD_0PE6_11_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_RSVD_0PE6_11_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_EDGE1_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_EDGE1_MASK 0x7000
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_RSVD_0PE6_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6_RSVD_0PE6_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PE7 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PE7_RSVD_0PE7_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PE7_RSVD_0PE7_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_0PE7_CALNBS_BOT_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0PE7_CALNBS_BOT_MASK 0x38
+#define NIC0_SERDES0_LANE1_REGISTER_0PE7_CALNBS_TOP_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0PE7_CALNBS_TOP_MASK 0x1C0
+#define NIC0_SERDES0_LANE1_REGISTER_0PE7_RSVD_0PE7_15_09_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0PE7_RSVD_0PE7_15_09_MASK 0xFE00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PE9 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PE9_RSVD_0PE9_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PE9_RSVD_0PE9_00_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0PE9_IDACZ_EYE_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0PE9_IDACZ_EYE_MASK 0x3E
+#define NIC0_SERDES0_LANE1_REGISTER_0PE9_IDACY_EYE_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0PE9_IDACY_EYE_MASK 0x7C0
+#define NIC0_SERDES0_LANE1_REGISTER_0PE9_IDACX_EYE_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0PE9_IDACX_EYE_MASK 0xF800
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PEA */
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_RSVD_0PEA_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_RSVD_0PEA_00_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_EYE_EN_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_EYE_EN_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_PU_CLKCOMPREG_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_PU_CLKCOMPREG_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_PU_CLKCOMP_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_PU_CLKCOMP_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_RSVD_0PEA_04_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_RSVD_0PEA_04_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_PU_ADC_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_PU_ADC_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_VDACCLKPHASE0_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_VDACCLKPHASE0_MASK 0x1FC0
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_PLL_BIAS0_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA_PLL_BIAS0_MASK 0xE000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PEB */
+#define NIC0_SERDES0_LANE1_REGISTER_0PEB_RSVD_0PEB_08_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PEB_RSVD_0PEB_08_00_MASK 0x1FF
+#define NIC0_SERDES0_LANE1_REGISTER_0PEB_VREFVDDINTP3_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0PEB_VREFVDDINTP3_MASK 0x1E00
+#define NIC0_SERDES0_LANE1_REGISTER_0PEB_RSVD_0PEB_15_13_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0PEB_RSVD_0PEB_15_13_MASK 0xE000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PEC */
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_RSVD_0PEC_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_RSVD_0PEC_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_DACBIAS0_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_DACBIAS0_MASK 0x70
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_DACBIAS1_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_DACBIAS1_MASK 0x380
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_RSVD_0PEC_11_10_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_RSVD_0PEC_11_10_MASK 0xC00
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_EXRESET_INTP_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_EXRESET_INTP_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_RSVD_0PEC_13_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_RSVD_0PEC_13_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_RX_DCC_EN_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_RX_DCC_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_PU_INTP_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC_PU_INTP_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PED */
+#define NIC0_SERDES0_LANE1_REGISTER_0PED_SKEF_ADDCAP_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PED_SKEF_ADDCAP_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_0PED_SKEF_VAL_LSB_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0PED_SKEF_VAL_LSB_MASK 0x38
+#define NIC0_SERDES0_LANE1_REGISTER_0PED_SKEF_EN_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0PED_SKEF_EN_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0PED_RSVD_0PED_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0PED_RSVD_0PED_07_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0PED_DEGENDL7_0_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PED_DEGENDL7_0_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0PED_DEGENDL7_1_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PED_DEGENDL7_1_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PEE */
+#define NIC0_SERDES0_LANE1_REGISTER_0PEE_DEGENDL6_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PEE_DEGENDL6_0_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0PEE_DEGENDL6_1_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PEE_DEGENDL6_1_MASK 0xF0
+#define NIC0_SERDES0_LANE1_REGISTER_0PEE_DEGENDL5_0_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PEE_DEGENDL5_0_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0PEE_DEGENDL5_1_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PEE_DEGENDL5_1_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PEF */
+#define NIC0_SERDES0_LANE1_REGISTER_0PEF_DEGENDL4_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PEF_DEGENDL4_0_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0PEF_DEGENDL4_1_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PEF_DEGENDL4_1_MASK 0xF0
+#define NIC0_SERDES0_LANE1_REGISTER_0PEF_DEGENDL3_0_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PEF_DEGENDL3_0_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0PEF_DEGENDL3_1_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PEF_DEGENDL3_1_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PF0 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PF0_DEGENDL2_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF0_DEGENDL2_0_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0PF0_DEGENDL2_1_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PF0_DEGENDL2_1_MASK 0xF0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF0_DEGENDL1_0_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PF0_DEGENDL1_0_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0PF0_DEGENDL1_1_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PF0_DEGENDL1_1_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PF1 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1_POL_MUX4_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1_POL_MUX4_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1_POL_MUX3_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1_POL_MUX3_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1_POL_MUX2_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1_POL_MUX2_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1_POL_MUX1_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1_POL_MUX1_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1_DEGENSUM_SUM4_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1_DEGENSUM_SUM4_MASK 0xF0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1_DEGENMAIN_SUM4_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1_DEGENMAIN_SUM4_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1_DEGENSUM1_SUM1_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1_DEGENSUM1_SUM1_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PF2 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PF2_DEGENSUM0_SUM3_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF2_DEGENSUM0_SUM3_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0PF2_DEGENSUM1_SUM3_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PF2_DEGENSUM1_SUM3_MASK 0xF0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF2_DEGENMAIN0_SUM3_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PF2_DEGENMAIN0_SUM3_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0PF2_DEGENMAIN1_SUM3_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PF2_DEGENMAIN1_SUM3_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PF3 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PF3_DEGENMAIN1_SUM2_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF3_DEGENMAIN1_SUM2_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0PF3_DEGENSUM0_SUM2_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PF3_DEGENSUM0_SUM2_MASK 0xF0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF3_DEGENSUM1_SUM2_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PF3_DEGENSUM1_SUM2_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0PF3_DEGENMAIN0_SUM2_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PF3_DEGENMAIN0_SUM2_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PF4 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PF4_AGCGAIN2_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF4_AGCGAIN2_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0PF4_RSVD_0PF4_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0PF4_RSVD_0PF4_07_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0PF4_AGCGAIN1_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PF4_AGCGAIN1_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0PF4_RSVD_0PF4_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0PF4_RSVD_0PF4_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PF5 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PF5_DEGENMAIN0_SUM1_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF5_DEGENMAIN0_SUM1_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0PF5_DEGENMAIN1_SUM1_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PF5_DEGENMAIN1_SUM1_MASK 0xF0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF5_DEGENSUM0_SUM1_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PF5_DEGENSUM0_SUM1_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0PF5_RSVD_0PF5_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PF5_RSVD_0PF5_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PF6 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PF6_RSVD_0PF6_05_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF6_RSVD_0PF6_05_00_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_0PF6_VREFAGCREG_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0PF6_VREFAGCREG_MASK 0x1C0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF6_RSVD_0PF6_10_09_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0PF6_RSVD_0PF6_10_09_MASK 0x600
+#define NIC0_SERDES0_LANE1_REGISTER_0PF6_AGCOFFSETLPF_EN_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0PF6_AGCOFFSETLPF_EN_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_0PF6_VGAVDSAT_DL_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PF6_VGAVDSAT_DL_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PF7 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PF7_RSVD_0PF7_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF7_RSVD_0PF7_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_0PF7_VGAVDSAT_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0PF7_VGAVDSAT_MASK 0x78
+#define NIC0_SERDES0_LANE1_REGISTER_0PF7_VAGCBUFDAC_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0PF7_VAGCBUFDAC_MASK 0x380
+#define NIC0_SERDES0_LANE1_REGISTER_0PF7_VCASGA5X_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0PF7_VCASGA5X_MASK 0x1C00
+#define NIC0_SERDES0_LANE1_REGISTER_0PF7_CTLE_CM2_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0PF7_CTLE_CM2_MASK 0xE000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PF8 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_RSVD_0PF8_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_RSVD_0PF8_00_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_CTLE_CM1_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_CTLE_CM1_MASK 0xE
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_RSVD_0PF8_09_04_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_RSVD_0PF8_09_04_MASK 0x3F0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_AC_COUPLE_EN_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_AC_COUPLE_EN_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_PU_PMOS_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_PU_PMOS_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_RSVD_0PF8_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_RSVD_0PF8_12_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_PU_AGCDL2_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_PU_AGCDL2_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_PU_AGCDL1_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_PU_AGCDL1_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_PU_AGC_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8_PU_AGC_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PF9 */
+#define NIC0_SERDES0_LANE1_REGISTER_0PF9_PU_ACJTAG_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF9_PU_ACJTAG_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0PF9_IDAC_ACJTAG_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0PF9_IDAC_ACJTAG_MASK 0x6
+#define NIC0_SERDES0_LANE1_REGISTER_0PF9_RX_PLL_TEST_EN_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0PF9_RX_PLL_TEST_EN_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_0PF9_RX_PLL_VTSTGROUP_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PF9_RX_PLL_VTSTGROUP_MASK 0x1F0
+#define NIC0_SERDES0_LANE1_REGISTER_0PF9_RX_PLL_TESTMODE_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0PF9_RX_PLL_TESTMODE_MASK 0xE00
+#define NIC0_SERDES0_LANE1_REGISTER_0PF9_RSVD_0PF9_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PF9_RSVD_0PF9_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PFA */
+#define NIC0_SERDES0_LANE1_REGISTER_0PFA_RSVD_0PFA_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PFA_RSVD_0PFA_00_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0PFA_RX_VREFPDET_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0PFA_RX_VREFPDET_MASK 0xE
+#define NIC0_SERDES0_LANE1_REGISTER_0PFA_RSVD_0PFA_06_04_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PFA_RSVD_0PFA_06_04_MASK 0x70
+#define NIC0_SERDES0_LANE1_REGISTER_0PFA_RX_VREFVCOBUF_MA_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0PFA_RX_VREFVCOBUF_MA_MASK 0x380
+#define NIC0_SERDES0_LANE1_REGISTER_0PFA_RSVD_0PFA_12_10_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0PFA_RSVD_0PFA_12_10_MASK 0x1C00
+#define NIC0_SERDES0_LANE1_REGISTER_0PFA_RX_VVCOREG3_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0PFA_RX_VVCOREG3_MASK 0xE000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PFB */
+#define NIC0_SERDES0_LANE1_REGISTER_0PFB_RSVD_0PFB_04_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PFB_RSVD_0PFB_04_00_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_0PFB_RX_VPLLPMP2_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0PFB_RX_VPLLPMP2_MASK 0xE0
+#define NIC0_SERDES0_LANE1_REGISTER_0PFB_RSVD_0PFB_15_08_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0PFB_RSVD_0PFB_15_08_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PFC */
+#define NIC0_SERDES0_LANE1_REGISTER_0PFC_RSVD_0PFC_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PFC_RSVD_0PFC_00_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0PFC_RX_BYPASS_PLLPMP_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0PFC_RX_BYPASS_PLLPMP_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_0PFC_RSVD_0PFC_04_02_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0PFC_RSVD_0PFC_04_02_MASK 0x1C
+#define NIC0_SERDES0_LANE1_REGISTER_0PFC_RX_BYPASS_DIV2PI_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0PFC_RX_BYPASS_DIV2PI_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_0PFC_RSVD_0PFC_08_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0PFC_RSVD_0PFC_08_06_MASK 0x1C0
+#define NIC0_SERDES0_LANE1_REGISTER_0PFC_RX_PLL_VCO_RANGE_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0PFC_RX_PLL_VCO_RANGE_MASK 0xFE00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PFD */
+#define NIC0_SERDES0_LANE1_REGISTER_0PFD_RX_VCO_CURRENT_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PFD_RX_VCO_CURRENT_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_0PFD_RX_CHARGE_PUMP_CUR_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0PFD_RX_CHARGE_PUMP_CUR_MASK 0x38
+#define NIC0_SERDES0_LANE1_REGISTER_0PFD_PU_RX_PLL_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0PFD_PU_RX_PLL_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0PFD_RX_PLL_N_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0PFD_RX_PLL_N_MASK 0xFF80
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PFE */
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE_RSVD_0PFE_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE_RSVD_0PFE_00_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE_RX_LPF_RZ_SEL_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE_RX_LPF_RZ_SEL_MASK 0x6
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE_RX_LPF_R2_SEL_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE_RX_LPF_R2_SEL_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE_RX_LPF_CZ_SEL_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE_RX_LPF_CZ_SEL_MASK 0x30
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE_RX_LPF_C3_SEL_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE_RX_LPF_C3_SEL_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE_RX_LPF_C2_SEL_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE_RX_LPF_C2_SEL_MASK 0x180
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE_RSVD_0PFE_15_09_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE_RSVD_0PFE_15_09_MASK 0xFE00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0PFF */
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_RSVD_0PFF_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_RSVD_0PFF_00_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_PU_ADC_MA_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_PU_ADC_MA_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_PU_INTP_MA_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_PU_INTP_MA_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_RSVD_0PFF_04_03_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_RSVD_0PFF_04_03_MASK 0x18
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_PU_AGC_MA_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_PU_AGC_MA_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_RSVD_0PFF_11_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_RSVD_0PFF_11_06_MASK 0xFC0
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_PU_RX_BG_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_PU_RX_BG_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_RX_VBG_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF_RX_VBG_MASK 0xE000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N00 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N00_DFE_INIT_1_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N00_DFE_INIT_1_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N00_RSVD_0N00_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N00_RSVD_0N00_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N01 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N01_TLOOP_CONST_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N01_TLOOP_CONST_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0N01_DELTA_MIN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N01_DELTA_MIN_MASK 0x3F80
+#define NIC0_SERDES0_LANE1_REGISTER_0N01_DELTA_ADAPT_EN_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N01_DELTA_ADAPT_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0N01_ADC_RECAL_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N01_ADC_RECAL_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N02 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N02_AGC_PERIOD_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N02_AGC_PERIOD_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0N02_TARGET_CTRL_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0N02_TARGET_CTRL_MASK 0xFFF0
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N03 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N03_RX_NRZ_SD_THR_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N03_RX_NRZ_SD_THR_MASK 0x7FF
+#define NIC0_SERDES0_LANE1_REGISTER_0N03_RSVD_0N03_15_11_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0N03_RSVD_0N03_15_11_MASK 0xF800
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N04 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N04_RX_SD_CROSSOVER_COUNT_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N04_RX_SD_CROSSOVER_COUNT_MASK 0xFFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N04_RX_SD_CLK_CYCLES_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0N04_RX_SD_CLK_CYCLES_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N05 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N05_TIMER4_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N05_TIMER4_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N06 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N06_RSVD_0N06_11_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N06_RSVD_0N06_11_00_MASK 0xFFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N06_ITR_CNT4_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0N06_ITR_CNT4_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N07 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N07_DFE_INIT_2_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N07_DFE_INIT_2_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N07_RSVD_0N07_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N07_RSVD_0N07_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N08 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N08_MEAS_TIMER7_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N08_MEAS_TIMER7_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0N08_MEAS_TIMER6_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0N08_MEAS_TIMER6_MASK 0xF0
+#define NIC0_SERDES0_LANE1_REGISTER_0N08_MEAS_TIMER5_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N08_MEAS_TIMER5_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_0N08_ITR_CNT5_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0N08_ITR_CNT5_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N09 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N09_RSVD_0N09_14_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N09_RSVD_0N09_14_00_MASK 0x7FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N09_EM_MODE_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N09_EM_MODE_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N0B */
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B_NRZ_BP2_STATE_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B_NRZ_BP2_STATE_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B_RSVD_0N0B_05_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B_RSVD_0N0B_05_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B_RX_DFE_OVER_EN_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B_RX_DFE_OVER_EN_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B_NRZ_BP2_EN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B_NRZ_BP2_EN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B_NRZ_BP1_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B_NRZ_BP1_STATE_MASK 0x1F00
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B_RSVD_0N0B_14_13_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B_RSVD_0N0B_14_13_MASK 0x6000
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B_NRZ_BP1_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B_NRZ_BP1_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N0C */
+#define NIC0_SERDES0_LANE1_REGISTER_0N0C_RSVD_0N0C_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N0C_RSVD_0N0C_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0N0C_NRZ_PHY_READY_OW_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0N0C_NRZ_PHY_READY_OW_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_0N0C_NRZ_PHY_READY_OWEN_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0N0C_NRZ_PHY_READY_OWEN_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_0N0C_RSVD_0N0C_14_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0N0C_RSVD_0N0C_14_06_MASK 0x7FC0
+#define NIC0_SERDES0_LANE1_REGISTER_0N0C_NRZ_SM_CONT_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N0C_NRZ_SM_CONT_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N0D */
+#define NIC0_SERDES0_LANE1_REGISTER_0N0D_DELTA_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N0D_DELTA_VAL_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0N0D_RSVD_0N0D_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N0D_RSVD_0N0D_07_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N0D_NRZ_CURRENT_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N0D_NRZ_CURRENT_STATE_MASK 0x1F00
+#define NIC0_SERDES0_LANE1_REGISTER_0N0D_RSVD_0N0D_13_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0N0D_RSVD_0N0D_13_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0N0D_NRZ_BP2_REACHED_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N0D_NRZ_BP2_REACHED_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0N0D_NRZ_BP1_REACHED_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N0D_NRZ_BP1_REACHED_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N27 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N27_READ_FIXED_PAT_PLUS_MARGIN_BIT_11_8_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N27_READ_FIXED_PAT_PLUS_MARGIN_BIT_11_8_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0N27_READ_CTH_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0N27_READ_CTH_MASK 0xFFF0
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N28 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N28_READ_FIXED_PAT_MINUS_MARGIN_BIT_11_4_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N28_READ_FIXED_PAT_MINUS_MARGIN_BIT_11_4_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N28_READ_FIXED_PAT_PLUS_MARGIN_BIT_7_0_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N28_READ_FIXED_PAT_PLUS_MARGIN_BIT_7_0_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N29 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N29_RSVD_0N29_11_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N29_RSVD_0N29_11_00_MASK 0xFFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N29_READ_FIXED_PAT_MINUS_MARGIN_BIT_3_0_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0N29_READ_FIXED_PAT_MINUS_MARGIN_BIT_3_0_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N2A */
+#define NIC0_SERDES0_LANE1_REGISTER_0N2A_RX_READ_EM_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N2A_RX_READ_EM_MASK 0x7FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N2A_RSVD_0N2A_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N2A_RSVD_0N2A_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N2B */
+#define NIC0_SERDES0_LANE1_REGISTER_0N2B_RX_DFE_TAP_1_CURR_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N2B_RX_DFE_TAP_1_CURR_VAL_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0N2B_RSVD_0N2B_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N2B_RSVD_0N2B_07_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N2B_RSVD_0N2B_14_08_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N2B_RSVD_0N2B_14_08_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0N2B_RSVD_0N2B_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N2B_RSVD_0N2B_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N2C */
+#define NIC0_SERDES0_LANE1_REGISTER_0N2C_RX_DFE_TAP_3_CURR_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N2C_RX_DFE_TAP_3_CURR_VAL_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0N2C_RSVD_0N2C_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N2C_RSVD_0N2C_07_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N2C_RX_DFE_TAP_2_CURR_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N2C_RX_DFE_TAP_2_CURR_VAL_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0N2C_RSVD_0N2C_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N2C_RSVD_0N2C_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N2E */
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_RSVD_0N2E_01_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_RSVD_0N2E_01_00_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_NRZ_READ_PHY_READY_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_NRZ_READ_PHY_READY_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_NRZ_READ_SIG_DET_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_NRZ_READ_SIG_DET_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_RSVD_0N2E_05_04_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_RSVD_0N2E_05_04_MASK 0x30
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_RSVD_0N2E_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_RSVD_0N2E_06_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_READ_KF_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_READ_KF_MASK 0x180
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_RSVD_0N2E_11_09_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_RSVD_0N2E_11_09_MASK 0xE00
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_READ_KP_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_READ_KP_MASK 0x7000
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_RSVD_0N2E_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E_RSVD_0N2E_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N3B */
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RSVD_0N3B_04_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RSVD_0N3B_04_00_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RX_CDR_FREQ_OVER_VAL_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RX_CDR_FREQ_OVER_VAL_MASK 0x60
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RX_CDR_OVER_FREQ_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RX_CDR_OVER_FREQ_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RX_CDR_OVER_PH_K_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RX_CDR_OVER_PH_K_VAL_MASK 0x300
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RX_CDR_OVER_PH_K_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RX_CDR_OVER_PH_K_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RSVD_0N3B_11_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RSVD_0N3B_11_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RX_CDR_BW_OVER_VAL_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RX_CDR_BW_OVER_VAL_MASK 0x7000
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RX_CDR_OVER_BW_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B_RX_CDR_OVER_BW_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N4D */
+#define NIC0_SERDES0_LANE1_REGISTER_0N4D_NRZ_FREQ_INIT1_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N4D_NRZ_FREQ_INIT1_MASK 0x7FF
+#define NIC0_SERDES0_LANE1_REGISTER_0N4D_RSVD_0N4D_14_11_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0N4D_RSVD_0N4D_14_11_MASK 0x7800
+#define NIC0_SERDES0_LANE1_REGISTER_0N4D_RX_NRZ_CTLE_OVER_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N4D_RX_NRZ_CTLE_OVER_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N4E */
+#define NIC0_SERDES0_LANE1_REGISTER_0N4E_NRZ_FREQ_INIT2_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N4E_NRZ_FREQ_INIT2_MASK 0x7FF
+#define NIC0_SERDES0_LANE1_REGISTER_0N4E_RX_NRZ_CTLE_OVER_VAL_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0N4E_RX_NRZ_CTLE_OVER_VAL_MASK 0x3800
+#define NIC0_SERDES0_LANE1_REGISTER_0N4E_RSVD_0N4E_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N4E_RSVD_0N4E_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N4F */
+#define NIC0_SERDES0_LANE1_REGISTER_0N4F_EM_SEARCH_PARAM_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N4F_EM_SEARCH_PARAM_MASK 0xFFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N4F_DAC_SEL_OW_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0N4F_DAC_SEL_OW_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N50 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N50_EM_THR_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N50_EM_THR_MASK 0xFFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N50_RSVD_0N50_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0N50_RSVD_0N50_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N5D */
+#define NIC0_SERDES0_LANE1_REGISTER_0N5D_RX_DFE_TAP_2_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N5D_RX_DFE_TAP_2_VAL_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0N5D_RSVD_0N5D_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N5D_RSVD_0N5D_07_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N5D_RX_DFE_TAP_1_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N5D_RX_DFE_TAP_1_VAL_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0N5D_RSVD_0N5D_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N5D_RSVD_0N5D_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N5E */
+#define NIC0_SERDES0_LANE1_REGISTER_0N5E_RSVD_0N5E_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N5E_RSVD_0N5E_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N5E_RX_DFE_TAP_3_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N5E_RX_DFE_TAP_3_VAL_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0N5E_RSVD_0N5E_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N5E_RSVD_0N5E_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N60 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N60_TLOOP_CTRL4_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N60_TLOOP_CTRL4_MASK 0xFFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N60_RSVD_0N60_13_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0N60_RSVD_0N60_13_12_MASK 0x3000
+#define NIC0_SERDES0_LANE1_REGISTER_0N60_NRZ_SIG_DET_OW_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N60_NRZ_SIG_DET_OW_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0N60_NRZ_SIG_DET_OW_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N60_NRZ_SIG_DET_OW_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N61 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_NRZ_THETA2_ACC_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_NRZ_THETA2_ACC_OW_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_NRZ_THETA2_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_NRZ_THETA2_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_RSVD_0N61_09_08_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_RSVD_0N61_09_08_MASK 0x300
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_PRBS_CHKR_EN_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_PRBS_CHKR_EN_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_RSVD_0N61_11_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_RSVD_0N61_11_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_NRZ_PRBS_MODE_SEL_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_NRZ_PRBS_MODE_SEL_MASK 0x3000
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_PRBS_CHECK_FLIP_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_PRBS_CHECK_FLIP_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_PRBS_CNTR_RESET_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N61_PRBS_CNTR_RESET_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N62 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N62_NRZ_THETA4_ACC_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N62_NRZ_THETA4_ACC_OW_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0N62_NRZ_THETA4_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N62_NRZ_THETA4_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N62_NRZ_THETA3_ACC_OW_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N62_NRZ_THETA3_ACC_OW_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0N62_NRZ_THETA3_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N62_NRZ_THETA3_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N63 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N63_PH_OUT2_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N63_PH_OUT2_OW_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0N63_NRZ_THETA2_UPDATE_FLIP_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N63_NRZ_THETA2_UPDATE_FLIP_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N63_RSVD_0N63_15_08_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N63_RSVD_0N63_15_08_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N64 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N64_PH_OUT4_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N64_PH_OUT4_OW_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0N64_NRZ_THETA4_UPDATE_FLIP_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N64_NRZ_THETA4_UPDATE_FLIP_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N64_PH_OUT3_OW_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N64_PH_OUT3_OW_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0N64_NRZ_THETA3_UPDATE_FLIP_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N64_NRZ_THETA3_UPDATE_FLIP_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N65 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N65_RSVD_0N65_04_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N65_RSVD_0N65_04_00_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_0N65_NRZ_THETA4_UPDATE_MODE_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0N65_NRZ_THETA4_UPDATE_MODE_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_0N65_NRZ_THETA3_UPDATE_MODE_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0N65_NRZ_THETA3_UPDATE_MODE_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0N65_NRZ_THETA2_UPDATE_MODE_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N65_NRZ_THETA2_UPDATE_MODE_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N65_RSVD_0N65_15_08_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N65_RSVD_0N65_15_08_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N66 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N66_RX_NRZ_PRBS_READ_ERR_HIGH_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N66_RX_NRZ_PRBS_READ_ERR_HIGH_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N67 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N67_RX_NRZ_PRBS_READ_ERR_LOW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N67_RX_NRZ_PRBS_READ_ERR_LOW_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N6E */
+#define NIC0_SERDES0_LANE1_REGISTER_0N6E_READ_PH2_GRAY_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N6E_READ_PH2_GRAY_VAL_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0N6E_RSVD_0N6E_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N6E_RSVD_0N6E_07_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N6E_NRZ_READ_PH1_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N6E_NRZ_READ_PH1_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N6F */
+#define NIC0_SERDES0_LANE1_REGISTER_0N6F_READ_PH4_GRAY_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N6F_READ_PH4_GRAY_VAL_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0N6F_RSVD_0N6F_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N6F_RSVD_0N6F_07_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N6F_READ_PH3_GRAY_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N6F_READ_PH3_GRAY_VAL_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0N6F_RSVD_0N6F_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N6F_RSVD_0N6F_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N71 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N71_READ_THETA3_ACC_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N71_READ_THETA3_ACC_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0N71_RSVD_0N71_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N71_RSVD_0N71_07_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N71_READ_THETA2_ACC_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N71_READ_THETA2_ACC_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0N71_RSVD_0N71_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N71_RSVD_0N71_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N72 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N72_RSVD_0N72_05_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N72_RSVD_0N72_05_00_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_0N72_RSVD_0N72_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0N72_RSVD_0N72_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_0N72_READ_THETA4_ACC_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N72_READ_THETA4_ACC_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_0N72_RSVD_0N72_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N72_RSVD_0N72_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N73 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N73_READ_FREQ_ACCU_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N73_READ_FREQ_ACCU_MASK 0x7FF
+#define NIC0_SERDES0_LANE1_REGISTER_0N73_RSVD_0N73_15_11_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0N73_RSVD_0N73_15_11_MASK 0xF800
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N75 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N75_TLOOP_CTRL3_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N75_TLOOP_CTRL3_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0N75_TLOOP_CTRL2_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0N75_TLOOP_CTRL2_MASK 0xF0
+#define NIC0_SERDES0_LANE1_REGISTER_0N75_TLOOP_CTRL1_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N75_TLOOP_CTRL1_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_0N75_RSVD_0N75_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N75_RSVD_0N75_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N76 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N76_CTLE_MAP_TABLE_3_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N76_CTLE_MAP_TABLE_3_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N77 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N77_CTLE_MAP_TABLE_2_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N77_CTLE_MAP_TABLE_2_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N78 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N78_CTLE_MAP_TABLE_1_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N78_CTLE_MAP_TABLE_1_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N79 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N79_RX_HALF_RATE_EN_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N79_RX_HALF_RATE_EN_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0N79_RSVD_0N79_04_01_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0N79_RSVD_0N79_04_01_MASK 0x1E
+#define NIC0_SERDES0_LANE1_REGISTER_0N79_RX_NRZ_MODE_EN_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0N79_RX_NRZ_MODE_EN_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_0N79_RX_25G_EN_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0N79_RX_25G_EN_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0N79_RX_SUB_RATE_MODE_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N79_RX_SUB_RATE_MODE_MASK 0x180
+#define NIC0_SERDES0_LANE1_REGISTER_0N79_RSVD_0N79_15_09_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0N79_RSVD_0N79_15_09_MASK 0xFE00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N7A */
+#define NIC0_SERDES0_LANE1_REGISTER_0N7A_RSVD_0N7A_12_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N7A_RSVD_0N7A_12_00_MASK 0x1FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N7A_SPEED_MODE_ST2_EN_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0N7A_SPEED_MODE_ST2_EN_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0N7A_SPEED_MODE_ST2_SEL_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N7A_SPEED_MODE_ST2_SEL_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N7D */
+#define NIC0_SERDES0_LANE1_REGISTER_0N7D_NRZ_BP4_STATE_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N7D_NRZ_BP4_STATE_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_0N7D_RSVD_0N7D_06_05_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0N7D_RSVD_0N7D_06_05_MASK 0x60
+#define NIC0_SERDES0_LANE1_REGISTER_0N7D_NRZ_BP4_EN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N7D_NRZ_BP4_EN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N7D_NRZ_BP3_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N7D_NRZ_BP3_STATE_MASK 0x1F00
+#define NIC0_SERDES0_LANE1_REGISTER_0N7D_RSVD_0N7D_14_13_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0N7D_RSVD_0N7D_14_13_MASK 0x6000
+#define NIC0_SERDES0_LANE1_REGISTER_0N7D_NRZ_BP3_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N7D_NRZ_BP3_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N7E */
+#define NIC0_SERDES0_LANE1_REGISTER_0N7E_NRZ_BP6_STATE_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N7E_NRZ_BP6_STATE_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_0N7E_RSVD_0N7E_06_05_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0N7E_RSVD_0N7E_06_05_MASK 0x60
+#define NIC0_SERDES0_LANE1_REGISTER_0N7E_NRZ_BP6_EN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N7E_NRZ_BP6_EN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0N7E_NRZ_BP5_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0N7E_NRZ_BP5_STATE_MASK 0x1F00
+#define NIC0_SERDES0_LANE1_REGISTER_0N7E_RSVD_0N7E_14_13_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0N7E_RSVD_0N7E_14_13_MASK 0x6000
+#define NIC0_SERDES0_LANE1_REGISTER_0N7E_NRZ_BP5_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N7E_NRZ_BP5_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N7F */
+#define NIC0_SERDES0_LANE1_REGISTER_0N7F_RSVD_0N7F_05_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N7F_RSVD_0N7F_05_00_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_0N7F_RSVD_0N7F_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0N7F_RSVD_0N7F_06_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0N7F_RSVD_0N7F_08_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0N7F_RSVD_0N7F_08_07_MASK 0x180
+#define NIC0_SERDES0_LANE1_REGISTER_0N7F_CTLE_READ_CURR_VAL_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0N7F_CTLE_READ_CURR_VAL_MASK 0xE00
+#define NIC0_SERDES0_LANE1_REGISTER_0N7F_DAC_SEL_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0N7F_DAC_SEL_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N80 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N80_RSVD_0N80_08_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N80_RSVD_0N80_08_00_MASK 0x1FF
+#define NIC0_SERDES0_LANE1_REGISTER_0N80_DELTA_MAX_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0N80_DELTA_MAX_MASK 0xFE00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N81 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N81_NRZ_FREQ_INIT3_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N81_NRZ_FREQ_INIT3_MASK 0x7FF
+#define NIC0_SERDES0_LANE1_REGISTER_0N81_NRZ_SM_RESET_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0N81_NRZ_SM_RESET_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_0N81_RSVD_0N81_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0N81_RSVD_0N81_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N82 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N82_NRZ_FREQ_INIT4_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N82_NRZ_FREQ_INIT4_MASK 0x7FF
+#define NIC0_SERDES0_LANE1_REGISTER_0N82_RSVD_0N82_15_11_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0N82_RSVD_0N82_15_11_MASK 0xF800
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N83 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N83_DFE_INIT_3_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N83_DFE_INIT_3_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N83_RSVD_0N83_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N83_RSVD_0N83_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N84 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N84_DFE_INIT_4_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N84_DFE_INIT_4_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N84_RSVD_0N84_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N84_RSVD_0N84_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N85 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N85_DFE_INIT_5_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N85_DFE_INIT_5_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N85_RSVD_0N85_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N85_RSVD_0N85_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N86 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N86_DFE_INIT_6_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N86_DFE_INIT_6_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N86_RSVD_0N86_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N86_RSVD_0N86_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N87 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N87_DFE_INIT_7_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N87_DFE_INIT_7_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N87_RSVD_0N87_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N87_RSVD_0N87_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N88 */
+#define NIC0_SERDES0_LANE1_REGISTER_0N88_DFE_INIT_8_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N88_DFE_INIT_8_VAL_MASK 0x3FFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N88_RSVD_0N88_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N88_RSVD_0N88_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N8C */
+#define NIC0_SERDES0_LANE1_REGISTER_0N8C_RSVD_0N8C_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N8C_RSVD_0N8C_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_0N8C_MAX_EM_ADAPT_OW_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0N8C_MAX_EM_ADAPT_OW_MASK 0x7FF8
+#define NIC0_SERDES0_LANE1_REGISTER_0N8C_MAX_EM_ADAPT_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N8C_MAX_EM_ADAPT_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0N8F */
+#define NIC0_SERDES0_LANE1_REGISTER_0N8F_RSVD_0N8F_11_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0N8F_RSVD_0N8F_11_00_MASK 0xFFF
+#define NIC0_SERDES0_LANE1_REGISTER_0N8F_NRZ_BP6_REACHED_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0N8F_NRZ_BP6_REACHED_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_0N8F_NRZ_BP5_REACHED_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0N8F_NRZ_BP5_REACHED_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0N8F_NRZ_BP4_REACHED_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0N8F_NRZ_BP4_REACHED_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0N8F_NRZ_BP3_REACHED_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0N8F_NRZ_BP3_REACHED_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0NF2 */
+#define NIC0_SERDES0_LANE1_REGISTER_0NF2_RSVD_0NF2_01_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0NF2_RSVD_0NF2_01_00_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_0NF2_RX_REFCLK_DIV4_INT_EN_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0NF2_RX_REFCLK_DIV4_INT_EN_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_0NF2_RSVD_0NF2_13_03_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0NF2_RSVD_0NF2_13_03_MASK 0x3FF8
+#define NIC0_SERDES0_LANE1_REGISTER_0NF2_TX_REFCLK_DIV4_INT_EN_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0NF2_TX_REFCLK_DIV4_INT_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0NF2_RSVD_0NF2_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0NF2_RSVD_0NF2_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0NF3 */
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_RSVD_0NF3_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_RSVD_0NF3_00_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_BM_VCO_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_BM_VCO_MASK 0x3E
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_EN2TO1_1_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_EN2TO1_1_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_EN1TO2_1_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_EN1TO2_1_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_VREFREFCLKBUF_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_VREFREFCLKBUF_MASK 0x700
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_VREF1P3REFCLKBUF_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_VREF1P3REFCLKBUF_MASK 0x3800
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_RSVD_0NF3_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_RSVD_0NF3_14_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_PU_TX_REFCLKBUF_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3_PU_TX_REFCLKBUF_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0NF6 */
+#define NIC0_SERDES0_LANE1_REGISTER_0NF6_RSVD_0NF6_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0NF6_RSVD_0NF6_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_0NF6_TX_TEST_EN_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0NF6_TX_TEST_EN_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_0NF6_TX_VTSTGROUP_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0NF6_TX_VTSTGROUP_MASK 0x1E00
+#define NIC0_SERDES0_LANE1_REGISTER_0NF6_TX_TESTMODE_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0NF6_TX_TESTMODE_MASK 0xE000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0NF7 */
+#define NIC0_SERDES0_LANE1_REGISTER_0NF7_RSVD_0NF7_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0NF7_RSVD_0NF7_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_0NF7_VDDRREG_IBIAS_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0NF7_VDDRREG_IBIAS_MASK 0x38
+#define NIC0_SERDES0_LANE1_REGISTER_0NF7_PU_HIMODE_VDDR_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0NF7_PU_HIMODE_VDDR_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0NF7_VREFVDRVBUF_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0NF7_VREFVDRVBUF_MASK 0x380
+#define NIC0_SERDES0_LANE1_REGISTER_0NF7_V1P3REGVDRVBUF_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0NF7_V1P3REGVDRVBUF_MASK 0x1C00
+#define NIC0_SERDES0_LANE1_REGISTER_0NF7_VDRV_1P3REG_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0NF7_VDRV_1P3REG_MASK 0xE000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0NF8 */
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_RSVD_0NF8_01_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_RSVD_0NF8_01_00_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_VDRV_VDDR3REG_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_VDRV_VDDR3REG_MASK 0x1C
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_VDRV_VDDR2REG_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_VDRV_VDDR2REG_MASK 0xE0
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_VDRV_VDDRREG_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_VDRV_VDDRREG_MASK 0x700
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_RSVD_0NF8_12_11_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_RSVD_0NF8_12_11_MASK 0x1800
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_PU_VDRV_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_PU_VDRV_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_TX_ENDCC_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_TX_ENDCC_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_RSVD_0NF8_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8_RSVD_0NF8_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0NF9 */
+#define NIC0_SERDES0_LANE1_REGISTER_0NF9_RSVD_0NF9_06_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0NF9_RSVD_0NF9_06_00_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_0NF9_TX_PLL_TEST_EN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0NF9_TX_PLL_TEST_EN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0NF9_TX_PLL_VTSTGROUP_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0NF9_TX_PLL_VTSTGROUP_MASK 0x1F00
+#define NIC0_SERDES0_LANE1_REGISTER_0NF9_TX_PLL_TESTMODE_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0NF9_TX_PLL_TESTMODE_MASK 0xE000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0NFA */
+#define NIC0_SERDES0_LANE1_REGISTER_0NFA_RSVD_0NFA_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0NFA_RSVD_0NFA_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_0NFA_TX_VREFPDET_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0NFA_TX_VREFPDET_MASK 0x70
+#define NIC0_SERDES0_LANE1_REGISTER_0NFA_TX_VREF1P3PDET_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0NFA_TX_VREF1P3PDET_MASK 0x380
+#define NIC0_SERDES0_LANE1_REGISTER_0NFA_TX_VREFVCOBUF_MA_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0NFA_TX_VREFVCOBUF_MA_MASK 0x1C00
+#define NIC0_SERDES0_LANE1_REGISTER_0NFA_TX_VREF1P3VCOBUF_MA_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0NFA_TX_VREF1P3VCOBUF_MA_MASK 0xE000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0NFB */
+#define NIC0_SERDES0_LANE1_REGISTER_0NFB_RSVD_0NFB_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0NFB_RSVD_0NFB_00_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0NFB_TX_VVCOREG3_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0NFB_TX_VVCOREG3_MASK 0xE
+#define NIC0_SERDES0_LANE1_REGISTER_0NFB_TX_VVCOREG1_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0NFB_TX_VVCOREG1_MASK 0x70
+#define NIC0_SERDES0_LANE1_REGISTER_0NFB_TX_VPLLPMP2_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0NFB_TX_VPLLPMP2_MASK 0x380
+#define NIC0_SERDES0_LANE1_REGISTER_0NFB_TX_VPLLPMP1_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0NFB_TX_VPLLPMP1_MASK 0x1C00
+#define NIC0_SERDES0_LANE1_REGISTER_0NFB_TX_VRVDD_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0NFB_TX_VRVDD_MASK 0xE000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0NFC */
+#define NIC0_SERDES0_LANE1_REGISTER_0NFC_RSVD_0NFC_01_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0NFC_RSVD_0NFC_01_00_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_0NFC_TX_BYPASS_PLLPMP_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0NFC_TX_BYPASS_PLLPMP_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_0NFC_RSVD_0NFC_08_03_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0NFC_RSVD_0NFC_08_03_MASK 0x1F8
+#define NIC0_SERDES0_LANE1_REGISTER_0NFC_TX_PLL_VCO_RANGE_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0NFC_TX_PLL_VCO_RANGE_MASK 0xFE00
+
+/* NIC0_SERDES0_LANE1_REGISTER_0NFD */
+#define NIC0_SERDES0_LANE1_REGISTER_0NFD_TX_VCO_CURRENT_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0NFD_TX_VCO_CURRENT_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_0NFD_TX_CHARGE_PUMP_CUR_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_0NFD_TX_CHARGE_PUMP_CUR_MASK 0x38
+#define NIC0_SERDES0_LANE1_REGISTER_0NFD_PU_TX_PLL_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0NFD_PU_TX_PLL_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0NFD_TX_PLL_N_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0NFD_TX_PLL_N_MASK 0xFF80
+
+/* NIC0_SERDES0_LANE1_REGISTER_0NFE */
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_TX_BYPASS_DIV2PI_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_TX_BYPASS_DIV2PI_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_RSVD_0NFE_03_01_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_RSVD_0NFE_03_01_MASK 0xE
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_TX_LPF_RZ_SEL_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_TX_LPF_RZ_SEL_MASK 0x30
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_TX_LPF_R2_SEL_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_TX_LPF_R2_SEL_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_TX_LPF_CZ_SEL_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_TX_LPF_CZ_SEL_MASK 0x180
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_TX_LPF_C3_SEL_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_TX_LPF_C3_SEL_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_TX_LPF_C2_SEL_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_TX_LPF_C2_SEL_MASK 0xC00
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_RSVD_0NFE_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_RSVD_0NFE_12_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_TX_BM_POFFDAC_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE_TX_BM_POFFDAC_MASK 0xE000
+
+/* NIC0_SERDES0_LANE1_REGISTER_0NFF */
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_RSVD_0NFF_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_RSVD_0NFF_00_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_TX_LOOPBACK_EN_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_TX_LOOPBACK_EN_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_TX_BM_NOFFDAC_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_TX_BM_NOFFDAC_MASK 0x1C
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_PU_VDRV_MA_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_PU_VDRV_MA_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_TX_RVDDCLAMP_EN_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_TX_RVDDCLAMP_EN_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_PU_TX_RVDDLOOP_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_PU_TX_RVDDLOOP_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_TX_CHPMPCLK_SEL_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_TX_CHPMPCLK_SEL_MASK 0x300
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_TX_RVDDVCO_EN_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_TX_RVDDVCO_EN_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_PU_TX_RVDD_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_PU_TX_RVDD_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_PU_TX_BG_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_PU_TX_BG_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_TX_VBG_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF_TX_VBG_MASK 0xE000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI00 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI00_RSVD_AI00_08_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI00_RSVD_AI00_08_00_MASK 0x1FF
+#define NIC0_SERDES0_LANE0_REGISTER_AI00_AN_RESTART_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_AI00_AN_RESTART_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_AI00_RSVD_AI00_11_10_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_AI00_RSVD_AI00_11_10_MASK 0xC00
+#define NIC0_SERDES0_LANE0_REGISTER_AI00_AN_EN_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_AI00_AN_EN_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_AI00_EXTNP_CTRL_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_AI00_EXTNP_CTRL_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_AI00_RSVD_AI00_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_AI00_RSVD_AI00_14_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_AI00_AN_RESET_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_AI00_AN_RESET_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI01 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_LP_AN_ABILITY_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_LP_AN_ABILITY_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_RSVD_AI01_01_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_RSVD_AI01_01_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_LINK_STATUS_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_LINK_STATUS_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_AN_ABLILITY_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_AN_ABLILITY_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_REMOTE_FAULT_STATUS_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_REMOTE_FAULT_STATUS_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_AN_COMPLETE_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_AN_COMPLETE_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_PAGE_RECEIVED_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_PAGE_RECEIVED_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_EXTNP_STATUS_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_EXTNP_STATUS_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_RSVD_AI01_08_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_RSVD_AI01_08_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_PARALLEL_DETECTION_FAULT_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_PARALLEL_DETECTION_FAULT_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_RSVD_AI01_15_10_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_AI01_RSVD_AI01_15_10_MASK 0xFC00
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI02 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI02_OUI_2_17_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI02_OUI_2_17_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI03 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI03_REV_NUM_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI03_REV_NUM_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_AI03_MODEL_NUM_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_AI03_MODEL_NUM_MASK 0x3F0
+#define NIC0_SERDES0_LANE0_REGISTER_AI03_OUI_18_23_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_AI03_OUI_18_23_MASK 0xFC00
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI05 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_CL22_REG_PRESENT_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_CL22_REG_PRESENT_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_PMD_PMA_PRESENT_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_PMD_PMA_PRESENT_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_WIS_PRESENT_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_WIS_PRESENT_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_PCS_PRESENT_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_PCS_PRESENT_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_PHY_XS_PRESENT_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_PHY_XS_PRESENT_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_DTE_XS_PRESENT_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_DTE_XS_PRESENT_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_TC_PRESENT_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_TC_PRESENT_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_AN_PRESENT_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_AN_PRESENT_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_PMA1_PRESENT_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_PMA1_PRESENT_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_PMA2_PRESENT_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_PMA2_PRESENT_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_PMA3_PRESENT_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_PMA3_PRESENT_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_PMA4_PRESENT_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_PMA4_PRESENT_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_RSVD_AI05_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_AI05_RSVD_AI05_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI06 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI06_RSVD_AI06_12_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI06_RSVD_AI06_12_00_MASK 0x1FFF
+#define NIC0_SERDES0_LANE0_REGISTER_AI06_CL22_EXT_PRESENT_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_AI06_CL22_EXT_PRESENT_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_AI06_VENDOR_DEV1_PRESENT_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_AI06_VENDOR_DEV1_PRESENT_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_AI06_VENDOR_DEV2_PRESENT_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_AI06_VENDOR_DEV2_PRESENT_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI10 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI10_AN_SELECTOR_FIELD_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI10_AN_SELECTOR_FIELD_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_AI10_AN_D_12_5_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_AI10_AN_D_12_5_MASK 0x1FE0
+#define NIC0_SERDES0_LANE0_REGISTER_AI10_AN_REMOTE_FAULT_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_AI10_AN_REMOTE_FAULT_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_AI10_AN_ACK_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_AI10_AN_ACK_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_AI10_AN_NP_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_AI10_AN_NP_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI11 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI11_AN_D_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI11_AN_D_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI12 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI12_AN_D_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI12_AN_D_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI13 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI13_AN_D_LP_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI13_AN_D_LP_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI14 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI14_AN_D_LP_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI14_AN_D_LP_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI15 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI15_AN_D_LP_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI15_AN_D_LP_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI16 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI16_MSG_UFC_FIELD_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI16_MSG_UFC_FIELD_MASK 0x7FF
+#define NIC0_SERDES0_LANE0_REGISTER_AI16_TOGGLE_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_AI16_TOGGLE_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_AI16_ACK2_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_AI16_ACK2_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_AI16_MSG_PAGE_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_AI16_MSG_PAGE_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_AI16_RSVD_AI16_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_AI16_RSVD_AI16_14_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_AI16_NEXT_PAGE_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_AI16_NEXT_PAGE_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI17 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI17_UFC_FIELD_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI17_UFC_FIELD_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI18 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI18_UFC_FIELD2_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI18_UFC_FIELD2_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI19 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI19_MSG_UFC_FIELD_LP_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI19_MSG_UFC_FIELD_LP_MASK 0x7FF
+#define NIC0_SERDES0_LANE0_REGISTER_AI19_TOGGLE_LP_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_AI19_TOGGLE_LP_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_AI19_ACK2_LP_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_AI19_ACK2_LP_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_AI19_MSG_PAGE_LP_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_AI19_MSG_PAGE_LP_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_AI19_ACK_LP_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_AI19_ACK_LP_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_AI19_NEXT_PAGE_LP_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_AI19_NEXT_PAGE_LP_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI1A */
+#define NIC0_SERDES0_LANE0_REGISTER_AI1A_UFC1_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI1A_UFC1_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI1B */
+#define NIC0_SERDES0_LANE0_REGISTER_AI1B_UFC2_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI1B_UFC2_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI30 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BP_AN_ABILITY_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BP_AN_ABILITY_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_1000_KX_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_1000_KX_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_10G_KX4_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_10G_KX4_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_10G_KR_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_10G_KR_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_R_FEC_NEGOTIATED_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_R_FEC_NEGOTIATED_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_40G_KR4_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_40G_KR4_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_40G_CR4_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_40G_CR4_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_RS_FEC_NEGOTIATED_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_RS_FEC_NEGOTIATED_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_100G_CR10_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_100G_CR10_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_100G_KP4_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_100G_KP4_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_100G_KR4_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_100G_KR4_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_100G_CR4_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_100G_CR4_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_25G_KRS_CRS_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_25G_KRS_CRS_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_25G_KR_CR_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_25G_KR_CR_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_2P5_KX_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_2P5_KX_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_5G_KR_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_AI30_BASE_5G_KR_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI31 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI31_BASE_50G_KR_CR_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI31_BASE_50G_KR_CR_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_AI31_BASE_100G_KR2_CR2_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_AI31_BASE_100G_KR2_CR2_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_AI31_BASE_200G_KR4_CR4_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_AI31_BASE_200G_KR4_CR4_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_AI31_RSVD_AI31_15_03_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_AI31_RSVD_AI31_15_03_MASK 0xFFF8
+
+/* NIC0_SERDES0_LANE0_REGISTER_AI40 */
+#define NIC0_SERDES0_LANE0_REGISTER_AI40_RSVD_AI40_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AI40_RSVD_AI40_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_AI40_BASE_25G_KR1_CONSORTIUM_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_AI40_BASE_25G_KR1_CONSORTIUM_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_AI40_BASE_25G_CR1_CONSORTIUM_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_AI40_BASE_25G_CR1_CONSORTIUM_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_AI40_BASE_50G_KR2_CONSORTIUM_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_AI40_BASE_50G_KR2_CONSORTIUM_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_AI40_BASE_50G_CR2_CONSORTIUM_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_AI40_BASE_50G_CR2_CONSORTIUM_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_AI40_RSVD_AI40_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_AI40_RSVD_AI40_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AIF0 */
+#define NIC0_SERDES0_LANE0_REGISTER_AIF0_AN_NEXT_PAGE_C_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AIF0_AN_NEXT_PAGE_C_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AIF1 */
+#define NIC0_SERDES0_LANE0_REGISTER_AIF1_AN_NEXT_PAGE_C_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AIF1_AN_NEXT_PAGE_C_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AIF2 */
+#define NIC0_SERDES0_LANE0_REGISTER_AIF2_AN_NEXT_PAGE_C_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AIF2_AN_NEXT_PAGE_C_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AIF3 */
+#define NIC0_SERDES0_LANE0_REGISTER_AIF3_AN_NP_UF_C_14_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AIF3_AN_NP_UF_C_14_0_MASK 0x7FFF
+#define NIC0_SERDES0_LANE0_REGISTER_AIF3_NP_C_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_AIF3_NP_C_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AIF4 */
+#define NIC0_SERDES0_LANE0_REGISTER_AIF4_AN_NP_UF_C_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AIF4_AN_NP_UF_C_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AIF5 */
+#define NIC0_SERDES0_LANE0_REGISTER_AIF5_AN_NP_UF_C_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AIF5_AN_NP_UF_C_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AIF6 */
+#define NIC0_SERDES0_LANE0_REGISTER_AIF6_OUI_MP4_VALID_CODE_C_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AIF6_OUI_MP4_VALID_CODE_C_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AIF7 */
+#define NIC0_SERDES0_LANE0_REGISTER_AIF7_OUI_MP5_VALID_CODE_C_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AIF7_OUI_MP5_VALID_CODE_C_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AIF8 */
+#define NIC0_SERDES0_LANE0_REGISTER_AIF8_OUI_MP5_VALID_CODE_C_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AIF8_OUI_MP5_VALID_CODE_C_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AIF9 */
+#define NIC0_SERDES0_LANE0_REGISTER_AIF9_TX_ARG_NULL_MP_S_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AIF9_TX_ARG_NULL_MP_S_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AIFA */
+#define NIC0_SERDES0_LANE0_REGISTER_AIFA_TX_ARG_NULL_MP_S_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AIFA_TX_ARG_NULL_MP_S_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AIFB */
+#define NIC0_SERDES0_LANE0_REGISTER_AIFB_TX_ARG_NULL_MP_S_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AIFB_TX_ARG_NULL_MP_S_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AIFC */
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_1000_KX_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_1000_KX_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_10G_KX4_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_10G_KX4_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_10G_KR_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_10G_KR_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_40G_KR4_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_40G_KR4_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_40G_CR4_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_40G_CR4_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_100G_CR10_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_100G_CR10_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_100G_KP4_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_100G_KP4_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_100G_KR4_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_100G_KR4_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_100G_CR4_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_100G_CR4_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_25G_KRS_CRS_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_25G_KRS_CRS_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_25G_KR_CR_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_25G_KR_CR_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_2P5G_KX_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_2P5G_KX_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_5G_KR_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_5G_KR_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_50G_KR_CR_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_50G_KR_CR_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_100G_KR2_CR2_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_100G_KR2_CR2_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_200G_KR4_CR4_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC_READ_BACK_BASE_200G_KR4_CR4_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT00 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT00_TRAINING_RESTART_SC_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT00_TRAINING_RESTART_SC_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_LT00_TRAINING_EN_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_LT00_TRAINING_EN_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_LT00_RSVD_LT00_15_02_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_LT00_RSVD_LT00_15_02_MASK 0xFFFC
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT04 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_READOUT_TXSTATE_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_READOUT_TXSTATE_MASK 0x1F
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_SIG_DET_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_SIG_DET_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_TX_TRAINING_DATA_EN_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_TX_TRAINING_DATA_EN_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_TRAINING_FAILURE_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_TRAINING_FAILURE_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_READOUT_TRAINING_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_READOUT_TRAINING_STATE_MASK 0x700
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_RX_TRAINED_FLAG_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_RX_TRAINED_FLAG_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_FRAME_LOCK_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_FRAME_LOCK_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_RSVD_LT04_15_13_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_LT04_RSVD_LT04_15_13_MASK 0xE000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT05 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT05_DME_ERROR_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT05_DME_ERROR_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT06 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT06_MAX_WAIT_TIMER_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT06_MAX_WAIT_TIMER_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT07 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT07_MAX_WAIT_TIMER_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT07_MAX_WAIT_TIMER_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT08 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT08_WAIT_TIMER_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT08_WAIT_TIMER_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT09 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT09_WAIT_TIMER_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT09_WAIT_TIMER_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT0A */
+#define NIC0_SERDES0_LANE0_REGISTER_LT0A_RSVD_LT0A_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT0A_RSVD_LT0A_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_LT0A_RSVD_LT0A_04_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_LT0A_RSVD_LT0A_04_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_LT0A_TOTAL_POWER_MAX_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_LT0A_TOTAL_POWER_MAX_MASK 0x7E0
+#define NIC0_SERDES0_LANE0_REGISTER_LT0A_RSVD_LT0A_11_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_LT0A_RSVD_LT0A_11_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_LT0A_TRAINING_STATE_OW_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT0A_TRAINING_STATE_OW_MASK 0x7000
+#define NIC0_SERDES0_LANE0_REGISTER_LT0A_TRAINING_STATE_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT0A_TRAINING_STATE_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT0B */
+#define NIC0_SERDES0_LANE0_REGISTER_LT0B_TAPM1_MIN_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT0B_TAPM1_MIN_VAL_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_LT0B_RSVD_LT0B_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT0B_RSVD_LT0B_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT0B_TAPM1_MAX_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT0B_TAPM1_MAX_VAL_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT0B_RSVD_LT0B_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT0B_RSVD_LT0B_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT0C */
+#define NIC0_SERDES0_LANE0_REGISTER_LT0C_TAPM1_INI_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT0C_TAPM1_INI_VAL_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_LT0C_RSVD_LT0C_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT0C_RSVD_LT0C_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT0C_TAPM1_PRESET_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT0C_TAPM1_PRESET_VAL_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT0C_RSVD_LT0C_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT0C_RSVD_LT0C_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT0D */
+#define NIC0_SERDES0_LANE0_REGISTER_LT0D_TAP0_MIN_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT0D_TAP0_MIN_VAL_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_LT0D_RSVD_LT0D_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT0D_RSVD_LT0D_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT0D_TAP0_MAX_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT0D_TAP0_MAX_VAL_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT0D_RSVD_LT0D_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT0D_RSVD_LT0D_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT0E */
+#define NIC0_SERDES0_LANE0_REGISTER_LT0E_TAP0_INI_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT0E_TAP0_INI_VAL_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_LT0E_RSVD_LT0E_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT0E_RSVD_LT0E_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT0E_TAP0_PRESET_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT0E_TAP0_PRESET_VAL_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT0E_RSVD_LT0E_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT0E_RSVD_LT0E_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT0F */
+#define NIC0_SERDES0_LANE0_REGISTER_LT0F_TAP1_MIN_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT0F_TAP1_MIN_VAL_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_LT0F_RSVD_LT0F_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT0F_RSVD_LT0F_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT0F_TAP1_MAX_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT0F_TAP1_MAX_VAL_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT0F_RSVD_LT0F_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT0F_RSVD_LT0F_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT10 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT10_TAP1_INI_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT10_TAP1_INI_VAL_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_LT10_RSVD_LT10_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT10_RSVD_LT10_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT10_TAP1_PRESET_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT10_TAP1_PRESET_VAL_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT10_RSVD_LT10_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT10_RSVD_LT10_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT11 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT11_LP_COEFF_M1UPDATE_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT11_LP_COEFF_M1UPDATE_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_LT11_LP_COEFF_0UPDATE_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_LT11_LP_COEFF_0UPDATE_MASK 0xC
+#define NIC0_SERDES0_LANE0_REGISTER_LT11_LP_COEFF_1UPDATE_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_LT11_LP_COEFF_1UPDATE_MASK 0x30
+#define NIC0_SERDES0_LANE0_REGISTER_LT11_RSVD_LT11_11_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT11_RSVD_LT11_11_06_MASK 0xFC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT11_LP_INIT_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT11_LP_INIT_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_LT11_LP_PRESET_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_LT11_LP_PRESET_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_LT11_RSVD_LT11_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT11_RSVD_LT11_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT12 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_COEFF_M1UPDATE_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_COEFF_M1UPDATE_OW_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_COEFF_0UPDATE_OW_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_COEFF_0UPDATE_OW_MASK 0xC
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_COEFF_1UPDATE_OW_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_COEFF_1UPDATE_OW_MASK 0x30
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_COEFF_M1UPDATE_OWEN_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_COEFF_M1UPDATE_OWEN_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_COEFF_0UPDATE_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_COEFF_0UPDATE_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_COEFF_1UPDATE_OWEN_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_COEFF_1UPDATE_OWEN_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_RSVD_LT12_11_09_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_RSVD_LT12_11_09_MASK 0xE00
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_INIT_OW_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_INIT_OW_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_PRESET_OW_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_PRESET_OW_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_INIT_OWEN_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_INIT_OWEN_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_PRESET_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT12_LP_PRESET_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT13 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT13_LP_COEFF_M1STATUS_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT13_LP_COEFF_M1STATUS_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_LT13_LP_COEFF_0STATUS_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_LT13_LP_COEFF_0STATUS_MASK 0xC
+#define NIC0_SERDES0_LANE0_REGISTER_LT13_LP_COEFF_1STATUS_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_LT13_LP_COEFF_1STATUS_MASK 0x30
+#define NIC0_SERDES0_LANE0_REGISTER_LT13_RSVD_LT13_14_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT13_RSVD_LT13_14_06_MASK 0x7FC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT13_LP_RECEIVER_READY_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT13_LP_RECEIVER_READY_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT14 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_COEFF_M1STATUS_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_COEFF_M1STATUS_OW_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_COEFF_0STATUS_OW_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_COEFF_0STATUS_OW_MASK 0xC
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_COEFF_1STATUS_OW_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_COEFF_1STATUS_OW_MASK 0x30
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_COEFF_M1STATUS_OWEN_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_COEFF_M1STATUS_OWEN_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_COEFF_0STATUS_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_COEFF_0STATUS_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_COEFF_1STATUS_OWEN_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_COEFF_1STATUS_OWEN_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_RSVD_LT14_13_09_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_RSVD_LT14_13_09_MASK 0x3E00
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_RECEIVER_READY_OW_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_RECEIVER_READY_OW_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_RECEIVER_READY_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT14_LP_RECEIVER_READY_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT15 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT15_LD_COEFF_M1UPDATE_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT15_LD_COEFF_M1UPDATE_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_LT15_LD_COEFF_0UPDATE_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_LT15_LD_COEFF_0UPDATE_MASK 0xC
+#define NIC0_SERDES0_LANE0_REGISTER_LT15_LD_COEFF_1UPDATE_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_LT15_LD_COEFF_1UPDATE_MASK 0x30
+#define NIC0_SERDES0_LANE0_REGISTER_LT15_RSVD_LT15_11_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT15_RSVD_LT15_11_06_MASK 0xFC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT15_LD_INIT_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT15_LD_INIT_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_LT15_LD_PRESET_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_LT15_LD_PRESET_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_LT15_RSVD_LT15_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT15_RSVD_LT15_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT16 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_COEFF_M1UPDATE_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_COEFF_M1UPDATE_OW_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_COEFF_0UPDATE_OW_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_COEFF_0UPDATE_OW_MASK 0xC
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_COEFF_1UPDATE_OW_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_COEFF_1UPDATE_OW_MASK 0x30
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_COEFF_M1UPDATE_OWEN_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_COEFF_M1UPDATE_OWEN_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_COEFF_0UPDATE_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_COEFF_0UPDATE_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_COEFF_1UPDATE_OWEN_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_COEFF_1UPDATE_OWEN_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_RSVD_LT16_11_09_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_RSVD_LT16_11_09_MASK 0xE00
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_INIT_OW_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_INIT_OW_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_PRESET_OW_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_PRESET_OW_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_INIT_OWEN_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_INIT_OWEN_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_PRESET_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT16_LD_PRESET_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT17 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT17_LD_COEFF_M1STATUS_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT17_LD_COEFF_M1STATUS_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_LT17_LD_COEFF_0STATUS_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_LT17_LD_COEFF_0STATUS_MASK 0xC
+#define NIC0_SERDES0_LANE0_REGISTER_LT17_LD_COEFF_1STATUS_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_LT17_LD_COEFF_1STATUS_MASK 0x30
+#define NIC0_SERDES0_LANE0_REGISTER_LT17_RSVD_LT17_14_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT17_RSVD_LT17_14_06_MASK 0x7FC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT17_LD_RECEIVER_READY_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT17_LD_RECEIVER_READY_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT18 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_COEFF_M1STATUS_OW_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_COEFF_M1STATUS_OW_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_COEFF_0STATUS_OW_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_COEFF_0STATUS_OW_MASK 0xC
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_COEFF_1STATUS_OW_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_COEFF_1STATUS_OW_MASK 0x30
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_COEFF_M1STATUS_OWEN_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_COEFF_M1STATUS_OWEN_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_COEFF_0STATUS_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_COEFF_0STATUS_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_COEFF_1STATUS_OWEN_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_COEFF_1STATUS_OWEN_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_RSVD_LT18_13_09_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_RSVD_LT18_13_09_MASK 0x3E00
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_RECEIVER_READY_OW_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_RECEIVER_READY_OW_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_RECEIVER_READY_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT18_LD_RECEIVER_READY_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT19 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_SEND_CLEAR_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_SEND_CLEAR_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_RX_TRAINED_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_RX_TRAINED_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_AUTO_FINISH_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_AUTO_FINISH_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_COEFF1_FRAME_DEC_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_COEFF1_FRAME_DEC_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_COEFF1_FRAME_INC_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_COEFF1_FRAME_INC_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_COEFFM1_FRAME_DEC_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_COEFFM1_FRAME_DEC_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_COEFFM1_FRAME_INC_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_COEFFM1_FRAME_INC_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_COEFF0_FRAME_DEC_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_COEFF0_FRAME_DEC_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_COEFF0_FRAME_INC_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_COEFF0_FRAME_INC_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_INI_FRAME_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_INI_FRAME_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_PRESET_FRAME_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_PRESET_FRAME_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_HOLD_FRAME_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_HOLD_FRAME_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_DIS_AN_START_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_DIS_AN_START_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_TRAINING_RESET_ALL_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_TRAINING_RESET_ALL_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_RSVD_LT19_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT19_RSVD_LT19_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT1A */
+#define NIC0_SERDES0_LANE0_REGISTER_LT1A_FINISH_CNTR_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT1A_FINISH_CNTR_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT1B */
+#define NIC0_SERDES0_LANE0_REGISTER_LT1B_FINISH_CNTR_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT1B_FINISH_CNTR_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT1C */
+#define NIC0_SERDES0_LANE0_REGISTER_LT1C_TRAIN_INST_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT1C_TRAIN_INST_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT1D */
+#define NIC0_SERDES0_LANE0_REGISTER_LT1D_TRAIN_INST_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT1D_TRAIN_INST_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT1E */
+#define NIC0_SERDES0_LANE0_REGISTER_LT1E_TRAIN_INST_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT1E_TRAIN_INST_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT1F */
+#define NIC0_SERDES0_LANE0_REGISTER_LT1F_TRAIN_INST_63_48_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT1F_TRAIN_INST_63_48_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT20 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT20_TRAIN_INST_79_64_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT20_TRAIN_INST_79_64_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT21 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT21_TRAIN_INST_95_80_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT21_TRAIN_INST_95_80_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT22 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT22_TRAIN_INST_111_96_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT22_TRAIN_INST_111_96_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT23 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT23_TRAIN_INST_127_112_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT23_TRAIN_INST_127_112_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT24 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT24_RSVD_LT24_13_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT24_RSVD_LT24_13_00_MASK 0x3FFF
+#define NIC0_SERDES0_LANE0_REGISTER_LT24_TRAIN_MODE_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT24_TRAIN_MODE_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT25 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT25_HOLDOFF_TIMER_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT25_HOLDOFF_TIMER_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT26 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT26_HOLDOFF_TIMER_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT26_HOLDOFF_TIMER_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT29 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT29_RSVD_LT29_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT29_RSVD_LT29_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_LT29_RSVD_LT29_07_04_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_LT29_RSVD_LT29_07_04_MASK 0xF0
+#define NIC0_SERDES0_LANE0_REGISTER_LT29_TOTAL_POWER_MAX_50G_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT29_TOTAL_POWER_MAX_50G_MASK 0x7F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT29_RSVD_LT29_15_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT29_RSVD_LT29_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT2A */
+#define NIC0_SERDES0_LANE0_REGISTER_LT2A_TAP0_MIN_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT2A_TAP0_MIN_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_LT2A_RSVD_LT2A_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT2A_RSVD_LT2A_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT2A_TAP0_MAX_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT2A_TAP0_MAX_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT2A_RSVD_LT2A_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT2A_RSVD_LT2A_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT2B */
+#define NIC0_SERDES0_LANE0_REGISTER_LT2B_TAP0_PRESET2_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT2B_TAP0_PRESET2_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_LT2B_RSVD_LT2B_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT2B_RSVD_LT2B_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT2B_TAP0_PRESET1_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT2B_TAP0_PRESET1_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT2B_RSVD_LT2B_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT2B_RSVD_LT2B_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT2C */
+#define NIC0_SERDES0_LANE0_REGISTER_LT2C_RSVD_LT2C_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT2C_RSVD_LT2C_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_LT2C_TAP0_PRESET3_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT2C_TAP0_PRESET3_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT2C_RSVD_LT2C_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT2C_RSVD_LT2C_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT2D */
+#define NIC0_SERDES0_LANE0_REGISTER_LT2D_TAP1_MIN_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT2D_TAP1_MIN_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_LT2D_RSVD_LT2D_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT2D_RSVD_LT2D_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT2D_TAP1_MAX_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT2D_TAP1_MAX_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT2D_RSVD_LT2D_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT2D_RSVD_LT2D_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT2E */
+#define NIC0_SERDES0_LANE0_REGISTER_LT2E_TAP1_PRESET2_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT2E_TAP1_PRESET2_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_LT2E_RSVD_LT2E_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT2E_RSVD_LT2E_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT2E_TAP1_PRESET1_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT2E_TAP1_PRESET1_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT2E_RSVD_LT2E_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT2E_RSVD_LT2E_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT2F */
+#define NIC0_SERDES0_LANE0_REGISTER_LT2F_RSVD_LT2F_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT2F_RSVD_LT2F_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_LT2F_TAP1_PRESET3_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT2F_TAP1_PRESET3_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT2F_RSVD_LT2F_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT2F_RSVD_LT2F_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT30 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT30_TAPM1_MIN_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT30_TAPM1_MIN_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_LT30_RSVD_LT30_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT30_RSVD_LT30_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT30_TAPM1_MAX_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT30_TAPM1_MAX_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT30_RSVD_LT30_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT30_RSVD_LT30_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT31 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT31_TAPM1_PRESET2_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT31_TAPM1_PRESET2_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_LT31_RSVD_LT31_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT31_RSVD_LT31_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT31_TAPM1_PRESET1_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT31_TAPM1_PRESET1_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT31_RSVD_LT31_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT31_RSVD_LT31_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT32 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT32_RSVD_LT32_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT32_RSVD_LT32_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_LT32_TAPM1_PRESET3_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT32_TAPM1_PRESET3_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT32_RSVD_LT32_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT32_RSVD_LT32_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT33 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT33_TAPM2_MIN_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT33_TAPM2_MIN_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_LT33_RSVD_LT33_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT33_RSVD_LT33_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT33_TAPM2_MAX_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT33_TAPM2_MAX_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT33_RSVD_LT33_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT33_RSVD_LT33_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT34 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT34_TAPM2_PRESET2_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT34_TAPM2_PRESET2_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE0_REGISTER_LT34_RSVD_LT34_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT34_RSVD_LT34_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE0_REGISTER_LT34_TAPM2_PRESET1_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT34_TAPM2_PRESET1_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT34_RSVD_LT34_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT34_RSVD_LT34_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT35 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT35_RSVD_LT35_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT35_RSVD_LT35_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_LT35_TAPM2_PRESET3_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT35_TAPM2_PRESET3_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE0_REGISTER_LT35_RSVD_LT35_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT35_RSVD_LT35_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT36 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT36_FINISH_CNTR_50G_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT36_FINISH_CNTR_50G_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT37 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT37_FINISH_CNTR_50G_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT37_FINISH_CNTR_50G_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT38 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT38_TRAIN_INST_50G_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT38_TRAIN_INST_50G_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT39 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT39_TRAIN_INST_50G_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT39_TRAIN_INST_50G_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT3A */
+#define NIC0_SERDES0_LANE0_REGISTER_LT3A_TRAIN_INST_50G_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT3A_TRAIN_INST_50G_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT3B */
+#define NIC0_SERDES0_LANE0_REGISTER_LT3B_TRAIN_INST_50G_63_48_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT3B_TRAIN_INST_50G_63_48_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT3C */
+#define NIC0_SERDES0_LANE0_REGISTER_LT3C_TRAIN_INST_50G_79_64_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT3C_TRAIN_INST_50G_79_64_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT3D */
+#define NIC0_SERDES0_LANE0_REGISTER_LT3D_TRAIN_INST_50G_95_80_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT3D_TRAIN_INST_50G_95_80_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT3E */
+#define NIC0_SERDES0_LANE0_REGISTER_LT3E_TRAIN_INST_50G_111_96_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT3E_TRAIN_INST_50G_111_96_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT3F */
+#define NIC0_SERDES0_LANE0_REGISTER_LT3F_TRAIN_INST_50G_127_112_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT3F_TRAIN_INST_50G_127_112_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT40 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT40_TRAIN_INST_50G_143_128_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT40_TRAIN_INST_50G_143_128_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT41 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT41_TRAIN_INST_50G_159_144_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT41_TRAIN_INST_50G_159_144_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT42 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_RSVD_LT42_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_RSVD_LT42_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_COEFF_REQ_OW_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_COEFF_REQ_OW_MASK 0x18
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_COEFF_REQ_OWEN_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_COEFF_REQ_OWEN_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_COEFF_SEL_OW_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_COEFF_SEL_OW_MASK 0x1C0
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_COEFF_SEL_OWEN_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_COEFF_SEL_OWEN_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_MOD_PREC_REQ_OW_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_MOD_PREC_REQ_OW_MASK 0xC00
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_MOD_PREC_REQ_OWEN_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_MOD_PREC_REQ_OWEN_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_IC_REQ_OW_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_IC_REQ_OW_MASK 0x6000
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_IC_REQ_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT42_LP_IC_REQ_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT43 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_RSVD_LT43_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_RSVD_LT43_00_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_RCV_TF_LOCK_STS_OW_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_RCV_TF_LOCK_STS_OW_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_RCV_TF_LOCK_STS_OWEN_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_RCV_TF_LOCK_STS_OWEN_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_COEFF_STS_OW_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_COEFF_STS_OW_MASK 0x38
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_COEFF_STS_OWEN_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_COEFF_STS_OWEN_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_COEFF_STS_SEL_OW_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_COEFF_STS_SEL_OW_MASK 0x380
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_COEFF_STS_SEL_OWEN_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_COEFF_STS_SEL_OWEN_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_IC_STS_OW_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_IC_STS_OW_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_IC_STS_OWEN_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_IC_STS_OWEN_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_MOD_PREC_STS_OW_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_MOD_PREC_STS_OW_MASK 0x6000
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_MOD_PREC_STS_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT43_LP_MOD_PREC_STS_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT44 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_RSVD_LT44_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_RSVD_LT44_00_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_RCV_TF_LOCK_STS_OW_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_RCV_TF_LOCK_STS_OW_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_RCV_TF_LOCK_STS_OWEN_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_RCV_TF_LOCK_STS_OWEN_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_COEFF_REQ_OW_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_COEFF_REQ_OW_MASK 0x18
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_COEFF_REQ_OWEN_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_COEFF_REQ_OWEN_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_COEFF_SEL_OW_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_COEFF_SEL_OW_MASK 0x1C0
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_COEFF_SEL_OWEN_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_COEFF_SEL_OWEN_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_MOD_PREC_REQ_OW_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_MOD_PREC_REQ_OW_MASK 0xC00
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_MOD_PREC_REQ_OWEN_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_MOD_PREC_REQ_OWEN_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_IC_REQ_OW_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_IC_REQ_OW_MASK 0x6000
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_IC_REQ_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT44_LD_IC_REQ_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT45 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_RSVD_LT45_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_RSVD_LT45_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_COEFF_STS_OW_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_COEFF_STS_OW_MASK 0x38
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_COEFF_STS_OWEN_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_COEFF_STS_OWEN_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_COEFF_STS_SEL_OW_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_COEFF_STS_SEL_OW_MASK 0x380
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_COEFF_STS_SEL_OWEN_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_COEFF_STS_SEL_OWEN_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_IC_STS_OW_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_IC_STS_OW_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_IC_STS_OWEN_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_IC_STS_OWEN_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_MOD_PREC_STS_OW_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_MOD_PREC_STS_OW_MASK 0x6000
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_MOD_PREC_STS_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT45_LD_MOD_PREC_STS_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT4E */
+#define NIC0_SERDES0_LANE0_REGISTER_LT4E_SEED_10_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT4E_SEED_10_0_MASK 0x7FF
+#define NIC0_SERDES0_LANE0_REGISTER_LT4E_POLYNOMIAL_IDENTIFIER_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_LT4E_POLYNOMIAL_IDENTIFIER_MASK 0x1800
+#define NIC0_SERDES0_LANE0_REGISTER_LT4E_RSVD_LT4E_13_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_LT4E_RSVD_LT4E_13_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_LT4E_SEED_12_11_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT4E_SEED_12_11_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT4F */
+#define NIC0_SERDES0_LANE0_REGISTER_LT4F_CNTR_25G_START_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT4F_CNTR_25G_START_MASK 0x3FFF
+#define NIC0_SERDES0_LANE0_REGISTER_LT4F_RECORD_CLEAR_25G_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT4F_RECORD_CLEAR_25G_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_LT4F_RECORD_25G_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT4F_RECORD_25G_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT50 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT50_RECORD_FRAME_25G_119_104_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT50_RECORD_FRAME_25G_119_104_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT51 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT51_RECORD_FRAME_25G_103_88_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT51_RECORD_FRAME_25G_103_88_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT52 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT52_RECORD_FRAME_25G_87_72_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT52_RECORD_FRAME_25G_87_72_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT53 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT53_RECORD_FRAME_25G_71_56_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT53_RECORD_FRAME_25G_71_56_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT54 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT54_RECORD_FRAME_25G_55_40_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT54_RECORD_FRAME_25G_55_40_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT55 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT55_RECORD_FRAME_25G_39_24_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT55_RECORD_FRAME_25G_39_24_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT56 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT56_RECORD_FRAME_25G_23_8_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT56_RECORD_FRAME_25G_23_8_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT57 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT57_RSVD_LT57_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT57_RSVD_LT57_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_LT57_RECORD_FRAME_25G_7_0_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT57_RECORD_FRAME_25G_7_0_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT58 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT58_CNTR_50G_START_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT58_CNTR_50G_START_MASK 0x3FFF
+#define NIC0_SERDES0_LANE0_REGISTER_LT58_RECORD_CLEAR_50G_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT58_RECORD_CLEAR_50G_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_LT58_RECORD_50G_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT58_RECORD_50G_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT59 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT59_RECORD_FRAME_50G_191_176_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT59_RECORD_FRAME_50G_191_176_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT5A */
+#define NIC0_SERDES0_LANE0_REGISTER_LT5A_RECORD_FRAME_50G_175_160_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT5A_RECORD_FRAME_50G_175_160_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT5B */
+#define NIC0_SERDES0_LANE0_REGISTER_LT5B_RECORD_FRAME_50G_159_144_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT5B_RECORD_FRAME_50G_159_144_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT5C */
+#define NIC0_SERDES0_LANE0_REGISTER_LT5C_RECORD_FRAME_50G_143_128_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT5C_RECORD_FRAME_50G_143_128_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT5D */
+#define NIC0_SERDES0_LANE0_REGISTER_LT5D_RECORD_FRAME_50G_127_112_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT5D_RECORD_FRAME_50G_127_112_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT5E */
+#define NIC0_SERDES0_LANE0_REGISTER_LT5E_RECORD_FRAME_50G_111_96_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT5E_RECORD_FRAME_50G_111_96_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT5F */
+#define NIC0_SERDES0_LANE0_REGISTER_LT5F_RECORD_FRAME_50G_95_80_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT5F_RECORD_FRAME_50G_95_80_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT60 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT60_RECORD_FRAME_50G_79_64_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT60_RECORD_FRAME_50G_79_64_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT61 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT61_RECORD_FRAME_50G_63_48_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT61_RECORD_FRAME_50G_63_48_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT62 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT62_RECORD_FRAME_50G_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT62_RECORD_FRAME_50G_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT63 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT63_RECORD_FRAME_50G_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT63_RECORD_FRAME_50G_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT64 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT64_RECORD_FRAME_50G_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT64_RECORD_FRAME_50G_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT67 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT67_LP_COEFF_REQ_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT67_LP_COEFF_REQ_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_LT67_LP_COEFF_SEL_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_LT67_LP_COEFF_SEL_MASK 0x1C
+#define NIC0_SERDES0_LANE0_REGISTER_LT67_RSVD_LT67_07_05_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_LT67_RSVD_LT67_07_05_MASK 0xE0
+#define NIC0_SERDES0_LANE0_REGISTER_LT67_LP_MOD_PREC_REQ_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT67_LP_MOD_PREC_REQ_MASK 0x300
+#define NIC0_SERDES0_LANE0_REGISTER_LT67_RSVD_LT67_11_10_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_LT67_RSVD_LT67_11_10_MASK 0xC00
+#define NIC0_SERDES0_LANE0_REGISTER_LT67_LP_IC_REQ_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT67_LP_IC_REQ_MASK 0x3000
+#define NIC0_SERDES0_LANE0_REGISTER_LT67_RSVD_LT67_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT67_RSVD_LT67_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT68 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_LP_COEFF_STS_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_LP_COEFF_STS_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_LP_COEFF_STS_SEL_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_LP_COEFF_STS_SEL_MASK 0x38
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_RSVD_LT68_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_RSVD_LT68_06_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_LP_PARITY_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_LP_PARITY_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_LP_IC_STS_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_LP_IC_STS_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_LP_RCV_TF_LOCK_STS_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_LP_RCV_TF_LOCK_STS_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_LP_MOD_PREC_STS_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_LP_MOD_PREC_STS_MASK 0xC00
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_RSVD_LT68_14_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_RSVD_LT68_14_12_MASK 0x7000
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_LP_RECEIVER_READY_50G_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT68_LP_RECEIVER_READY_50G_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT69 */
+#define NIC0_SERDES0_LANE0_REGISTER_LT69_LD_COEFF_REQ_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT69_LD_COEFF_REQ_MASK 0x3
+#define NIC0_SERDES0_LANE0_REGISTER_LT69_LD_COEFF_SEL_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_LT69_LD_COEFF_SEL_MASK 0x1C
+#define NIC0_SERDES0_LANE0_REGISTER_LT69_RSVD_LT69_07_05_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_LT69_RSVD_LT69_07_05_MASK 0xE0
+#define NIC0_SERDES0_LANE0_REGISTER_LT69_LD_MOD_PREC_REQ_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT69_LD_MOD_PREC_REQ_MASK 0x300
+#define NIC0_SERDES0_LANE0_REGISTER_LT69_RSVD_LT69_11_10_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_LT69_RSVD_LT69_11_10_MASK 0xC00
+#define NIC0_SERDES0_LANE0_REGISTER_LT69_LD_IC_REQ_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT69_LD_IC_REQ_MASK 0x3000
+#define NIC0_SERDES0_LANE0_REGISTER_LT69_RSVD_LT69_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_LT69_RSVD_LT69_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE0_REGISTER_LT6A */
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_LD_COEFF_STS_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_LD_COEFF_STS_MASK 0x7
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_LD_COEFF_STS_SEL_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_LD_COEFF_STS_SEL_MASK 0x38
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_RSVD_LT6A_06_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_RSVD_LT6A_06_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_LD_PARITY_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_LD_PARITY_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_LD_IC_STS_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_LD_IC_STS_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_LD_RCV_TF_LOCK_STS_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_LD_RCV_TF_LOCK_STS_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_LD_MOD_PREC_STS_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_LD_MOD_PREC_STS_MASK 0xC00
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_RSVD_LT6A_14_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_RSVD_LT6A_14_12_MASK 0x7000
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_LD_RECEIVER_READY_50G_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A_LD_RECEIVER_READY_50G_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AN01 */
+#define NIC0_SERDES0_LANE0_REGISTER_AN01_AA_HCD_RESOLVED_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AN01_AA_HCD_RESOLVED_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_AN01_AN_FINISHED_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_AN01_AN_FINISHED_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_AN01_LINK_TRAINING_DONE_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_AN01_LINK_TRAINING_DONE_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_AN01_RSVD_AN01_15_03_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_AN01_RSVD_AN01_15_03_MASK 0xFFF8
+
+/* NIC0_SERDES0_LANE0_REGISTER_AN02 */
+#define NIC0_SERDES0_LANE0_REGISTER_AN02_COMPANY_OUI_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AN02_COMPANY_OUI_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AN03 */
+#define NIC0_SERDES0_LANE0_REGISTER_AN03_RSVD_AN03_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AN03_RSVD_AN03_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_AN03_COMPANY_OUI_BIT_23_16_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_AN03_COMPANY_OUI_BIT_23_16_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_AN04 */
+#define NIC0_SERDES0_LANE0_REGISTER_AN04_REVISION_NUM_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AN04_REVISION_NUM_MASK 0xF
+#define NIC0_SERDES0_LANE0_REGISTER_AN04_MODEL_NUM_ANEG_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_AN04_MODEL_NUM_ANEG_MASK 0x3F0
+#define NIC0_SERDES0_LANE0_REGISTER_AN04_RSVD_AN04_15_10_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_AN04_RSVD_AN04_15_10_MASK 0xFC00
+
+/* NIC0_SERDES0_LANE0_REGISTER_AN05 */
+#define NIC0_SERDES0_LANE0_REGISTER_AN05_PCS_ADVERTISE_ABILITY_S_BIT_22_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AN05_PCS_ADVERTISE_ABILITY_S_BIT_22_16_MASK 0x7F
+#define NIC0_SERDES0_LANE0_REGISTER_AN05_RSVD_AN05_07_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_AN05_RSVD_AN05_07_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_AN05_PCS_ADVERTISE_CONSORTIUM_25G_S_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_AN05_PCS_ADVERTISE_CONSORTIUM_25G_S_MASK 0x300
+#define NIC0_SERDES0_LANE0_REGISTER_AN05_PCS_ADVERTISE_CONSORTIUM_50G_S_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_AN05_PCS_ADVERTISE_CONSORTIUM_50G_S_MASK 0xC00
+#define NIC0_SERDES0_LANE0_REGISTER_AN05_RSVD_AN05_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_AN05_RSVD_AN05_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AN06 */
+#define NIC0_SERDES0_LANE0_REGISTER_AN06_PCS_ADVERTISE_ABILITY_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AN06_PCS_ADVERTISE_ABILITY_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AN07 */
+#define NIC0_SERDES0_LANE0_REGISTER_AN07_RSVD_AN07_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AN07_RSVD_AN07_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE0_REGISTER_AN07_PCS_ADVERTISE_FEC_S_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_AN07_PCS_ADVERTISE_FEC_S_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_AN07_PCS_ADVERTISE_CONSORTIUM_FEC_S_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_AN07_PCS_ADVERTISE_CONSORTIUM_FEC_S_MASK 0xF000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AN08 */
+#define NIC0_SERDES0_LANE0_REGISTER_AN08_MODE_25G_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AN08_MODE_25G_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_AN08_PCS_AUTONEG_S_EN_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_AN08_PCS_AUTONEG_S_EN_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_AN08_PCS_RESTART_AUTONEG_S_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_AN08_PCS_RESTART_AUTONEG_S_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_AN08_TX_NONCE_SEED_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_AN08_TX_NONCE_SEED_MASK 0xF8
+#define NIC0_SERDES0_LANE0_REGISTER_AN08_RSVD_AN08_15_08_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_AN08_RSVD_AN08_15_08_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE0_REGISTER_AN09 */
+#define NIC0_SERDES0_LANE0_REGISTER_AN09_PCS_LINK_STATUS_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AN09_PCS_LINK_STATUS_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AN0A */
+#define NIC0_SERDES0_LANE0_REGISTER_AN0A_PCS_LINK_STATUS_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AN0A_PCS_LINK_STATUS_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AN10 */
+#define NIC0_SERDES0_LANE0_REGISTER_AN10_TX_AN_OR_LT_EN_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AN10_TX_AN_OR_LT_EN_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_AN10_TX_DW_SEL_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_AN10_TX_DW_SEL_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_AN10_RX_DW_SEL_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_AN10_RX_DW_SEL_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_AN10_RSVD_AN10_15_03_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_AN10_RSVD_AN10_15_03_MASK 0xFFF8
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK00 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_LINK_FAIL_INHIBIT_TIMER_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_LINK_FAIL_INHIBIT_TIMER_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_CONSORTIUM_RESOLUTION_S_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_CONSORTIUM_RESOLUTION_S_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_BP_RESOLUTION_S_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_BP_RESOLUTION_S_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_ACK_MATCH_IN_S2_S5_S_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_ACK_MATCH_IN_S2_S5_S_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_ACK2_CONSISTENCY_MATCH_S_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_ACK2_CONSISTENCY_MATCH_S_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_ACK2_CTRL_S_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_ACK2_CTRL_S_MASK 0x60
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_ECHO_NONCE_CHECK_S_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_ECHO_NONCE_CHECK_S_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_RX_ARG_DIS_TOGGLE_CHECK_S_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_RX_ARG_DIS_TOGGLE_CHECK_S_MASK 0x100
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_TX_ARG_DIS_TOGGLE_S_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_TX_ARG_DIS_TOGGLE_S_MASK 0x200
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_NONCE_MATCH_S_SHIFT 10
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_NONCE_MATCH_S_MASK 0x400
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_ANEG_SPEEDUP_S_SHIFT 11
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_ANEG_SPEEDUP_S_MASK 0x800
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_ANEG_IEEE_MODE_S_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_ANEG_IEEE_MODE_S_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_REG_RESET_ANEG_S_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_REG_RESET_ANEG_S_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_RESET_ANG_CSTM_REGS_S_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_RESET_ANG_CSTM_REGS_S_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_RESET_ANG_IEEE_REGS_S_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_RESET_ANG_IEEE_REGS_S_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK02 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_HCD_BIT_OW_VAL_BIT_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_HCD_BIT_OW_VAL_BIT_0_MASK 0x1
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_DIS_BP_FEC_BITS_FOR_CONSORTIUM_SPEED_SHIFT 1
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_DIS_BP_FEC_BITS_FOR_CONSORTIUM_SPEED_MASK 0x2
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_AA_MR_AUTONEG_COMPLETE_S_OW_VAL_SHIFT 2
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_AA_MR_AUTONEG_COMPLETE_S_OW_VAL_MASK 0x4
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_AA_MR_AUTONEG_COMPLETE_S_OW_EN_SHIFT 3
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_AA_MR_AUTONEG_COMPLETE_S_OW_EN_MASK 0x8
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_AA_AN_LINK_GOOD_S_OW_VAL_SHIFT 4
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_AA_AN_LINK_GOOD_S_OW_VAL_MASK 0x10
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_AA_AN_LINK_GOOD_S_OW_EN_SHIFT 5
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_AA_AN_LINK_GOOD_S_OW_EN_MASK 0x20
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_AA_HCD_RESOLVED_S_OW_VAL_SHIFT 6
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_AA_HCD_RESOLVED_S_OW_VAL_MASK 0x40
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_AA_HCD_RESOLVED_S_OW_EN_SHIFT 7
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_AA_HCD_RESOLVED_S_OW_EN_MASK 0x80
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_HCD_BIT_OW_VAL_BIT_4_1_SHIFT 8
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_HCD_BIT_OW_VAL_BIT_4_1_MASK 0xF00
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_FEC_KR_OW_VAL_SHIFT 12
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_FEC_KR_OW_VAL_MASK 0x1000
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_FEC_RS_OW_VAL_SHIFT 13
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_FEC_RS_OW_VAL_MASK 0x2000
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_FEC_RESOLUTION_OW_EN_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_FEC_RESOLUTION_OW_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_HCD_BIT_OW_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_AK02_HCD_BIT_OW_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK11 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK11_AA_TX_PAGE_0_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK11_AA_TX_PAGE_0_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK12 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK12_AA_TX_PAGE_0_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK12_AA_TX_PAGE_0_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK13 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK13_AA_TX_PAGE_0_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK13_AA_TX_PAGE_0_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK14 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK14_AA_TX_PAGE_1_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK14_AA_TX_PAGE_1_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK15 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK15_AA_TX_PAGE_1_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK15_AA_TX_PAGE_1_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK16 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK16_AA_TX_PAGE_1_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK16_AA_TX_PAGE_1_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK17 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK17_AA_TX_PAGE_2_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK17_AA_TX_PAGE_2_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK18 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK18_AA_TX_PAGE_2_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK18_AA_TX_PAGE_2_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK19 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK19_AA_TX_PAGE_2_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK19_AA_TX_PAGE_2_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK1A */
+#define NIC0_SERDES0_LANE0_REGISTER_AK1A_AA_TX_PAGE_3_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK1A_AA_TX_PAGE_3_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK1B */
+#define NIC0_SERDES0_LANE0_REGISTER_AK1B_AA_TX_PAGE_3_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK1B_AA_TX_PAGE_3_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK1C */
+#define NIC0_SERDES0_LANE0_REGISTER_AK1C_AA_TX_PAGE_3_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK1C_AA_TX_PAGE_3_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK1D */
+#define NIC0_SERDES0_LANE0_REGISTER_AK1D_AA_TX_PAGE_4_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK1D_AA_TX_PAGE_4_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK1E */
+#define NIC0_SERDES0_LANE0_REGISTER_AK1E_AA_TX_PAGE_4_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK1E_AA_TX_PAGE_4_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK1F */
+#define NIC0_SERDES0_LANE0_REGISTER_AK1F_AA_TX_PAGE_4_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK1F_AA_TX_PAGE_4_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK20 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK20_AA_TX_PAGE_5_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK20_AA_TX_PAGE_5_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK21 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK21_AA_TX_PAGE_5_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK21_AA_TX_PAGE_5_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK22 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK22_AA_TX_PAGE_5_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK22_AA_TX_PAGE_5_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK23 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK23_AA_TX_PAGE_6_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK23_AA_TX_PAGE_6_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK24 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK24_AA_TX_PAGE_6_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK24_AA_TX_PAGE_6_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK25 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK25_AA_TX_PAGE_6_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK25_AA_TX_PAGE_6_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK26 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK26_AA_TX_PAGE_7_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK26_AA_TX_PAGE_7_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK27 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK27_AA_TX_PAGE_7_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK27_AA_TX_PAGE_7_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK28 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK28_AA_TX_PAGE_7_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK28_AA_TX_PAGE_7_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK30 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK30_AA_RX_PAGE_0_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK30_AA_RX_PAGE_0_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK31 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK31_AA_RX_PAGE_0_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK31_AA_RX_PAGE_0_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK32 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK32_AA_RX_PAGE_0_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK32_AA_RX_PAGE_0_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK33 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK33_AA_RX_PAGE_1_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK33_AA_RX_PAGE_1_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK34 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK34_AA_RX_PAGE_1_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK34_AA_RX_PAGE_1_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK35 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK35_AA_RX_PAGE_1_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK35_AA_RX_PAGE_1_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK36 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK36_AA_RX_PAGE_2_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK36_AA_RX_PAGE_2_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK37 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK37_AA_RX_PAGE_2_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK37_AA_RX_PAGE_2_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK38 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK38_AA_RX_PAGE_2_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK38_AA_RX_PAGE_2_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK39 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK39_AA_RX_PAGE_3_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK39_AA_RX_PAGE_3_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK3A */
+#define NIC0_SERDES0_LANE0_REGISTER_AK3A_AA_RX_PAGE_3_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK3A_AA_RX_PAGE_3_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK3B */
+#define NIC0_SERDES0_LANE0_REGISTER_AK3B_AA_RX_PAGE_3_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK3B_AA_RX_PAGE_3_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK3C */
+#define NIC0_SERDES0_LANE0_REGISTER_AK3C_AA_RX_PAGE_4_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK3C_AA_RX_PAGE_4_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK3D */
+#define NIC0_SERDES0_LANE0_REGISTER_AK3D_AA_RX_PAGE_4_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK3D_AA_RX_PAGE_4_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK3E */
+#define NIC0_SERDES0_LANE0_REGISTER_AK3E_AA_RX_PAGE_4_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK3E_AA_RX_PAGE_4_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK3F */
+#define NIC0_SERDES0_LANE0_REGISTER_AK3F_AA_RX_PAGE_5_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK3F_AA_RX_PAGE_5_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK40 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK40_AA_RX_PAGE_5_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK40_AA_RX_PAGE_5_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK41 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK41_AA_RX_PAGE_5_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK41_AA_RX_PAGE_5_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK42 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK42_AA_RX_PAGE_6_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK42_AA_RX_PAGE_6_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK43 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK43_AA_RX_PAGE_6_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK43_AA_RX_PAGE_6_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK44 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK44_AA_RX_PAGE_6_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK44_AA_RX_PAGE_6_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK45 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK45_AA_RX_PAGE_7_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK45_AA_RX_PAGE_7_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK46 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK46_AA_RX_PAGE_7_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK46_AA_RX_PAGE_7_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AK47 */
+#define NIC0_SERDES0_LANE0_REGISTER_AK47_AA_RX_PAGE_7_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AK47_AA_RX_PAGE_7_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE0_REGISTER_AJ40 */
+#define NIC0_SERDES0_LANE0_REGISTER_AJ40_RSVD_AJ40_08_00_SHIFT 0
+#define NIC0_SERDES0_LANE0_REGISTER_AJ40_RSVD_AJ40_08_00_MASK 0x1FF
+#define NIC0_SERDES0_LANE0_REGISTER_AJ40_RSVD_AJ40_13_09_SHIFT 9
+#define NIC0_SERDES0_LANE0_REGISTER_AJ40_RSVD_AJ40_13_09_MASK 0x3E00
+#define NIC0_SERDES0_LANE0_REGISTER_AJ40_ANLT_REF_CLK_SEL_SHIFT 14
+#define NIC0_SERDES0_LANE0_REGISTER_AJ40_ANLT_REF_CLK_SEL_MASK 0x4000
+#define NIC0_SERDES0_LANE0_REGISTER_AJ40_ANLT_LANE_SWAPPING_EN_SHIFT 15
+#define NIC0_SERDES0_LANE0_REGISTER_AJ40_ANLT_LANE_SWAPPING_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI00 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI00_RSVD_AI00_08_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI00_RSVD_AI00_08_00_MASK 0x1FF
+#define NIC0_SERDES0_LANE1_REGISTER_AI00_AN_RESTART_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_AI00_AN_RESTART_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_AI00_RSVD_AI00_11_10_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_AI00_RSVD_AI00_11_10_MASK 0xC00
+#define NIC0_SERDES0_LANE1_REGISTER_AI00_AN_EN_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_AI00_AN_EN_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_AI00_EXTNP_CTRL_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_AI00_EXTNP_CTRL_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_AI00_RSVD_AI00_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_AI00_RSVD_AI00_14_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_AI00_AN_RESET_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_AI00_AN_RESET_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI01 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_LP_AN_ABILITY_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_LP_AN_ABILITY_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_RSVD_AI01_01_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_RSVD_AI01_01_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_LINK_STATUS_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_LINK_STATUS_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_AN_ABLILITY_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_AN_ABLILITY_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_REMOTE_FAULT_STATUS_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_REMOTE_FAULT_STATUS_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_AN_COMPLETE_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_AN_COMPLETE_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_PAGE_RECEIVED_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_PAGE_RECEIVED_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_EXTNP_STATUS_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_EXTNP_STATUS_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_RSVD_AI01_08_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_RSVD_AI01_08_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_PARALLEL_DETECTION_FAULT_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_PARALLEL_DETECTION_FAULT_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_RSVD_AI01_15_10_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_AI01_RSVD_AI01_15_10_MASK 0xFC00
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI02 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI02_OUI_2_17_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI02_OUI_2_17_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI03 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI03_REV_NUM_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI03_REV_NUM_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_AI03_MODEL_NUM_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_AI03_MODEL_NUM_MASK 0x3F0
+#define NIC0_SERDES0_LANE1_REGISTER_AI03_OUI_18_23_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_AI03_OUI_18_23_MASK 0xFC00
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI05 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_CL22_REG_PRESENT_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_CL22_REG_PRESENT_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_PMD_PMA_PRESENT_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_PMD_PMA_PRESENT_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_WIS_PRESENT_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_WIS_PRESENT_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_PCS_PRESENT_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_PCS_PRESENT_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_PHY_XS_PRESENT_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_PHY_XS_PRESENT_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_DTE_XS_PRESENT_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_DTE_XS_PRESENT_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_TC_PRESENT_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_TC_PRESENT_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_AN_PRESENT_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_AN_PRESENT_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_PMA1_PRESENT_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_PMA1_PRESENT_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_PMA2_PRESENT_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_PMA2_PRESENT_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_PMA3_PRESENT_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_PMA3_PRESENT_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_PMA4_PRESENT_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_PMA4_PRESENT_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_RSVD_AI05_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_AI05_RSVD_AI05_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI06 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI06_RSVD_AI06_12_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI06_RSVD_AI06_12_00_MASK 0x1FFF
+#define NIC0_SERDES0_LANE1_REGISTER_AI06_CL22_EXT_PRESENT_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_AI06_CL22_EXT_PRESENT_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_AI06_VENDOR_DEV1_PRESENT_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_AI06_VENDOR_DEV1_PRESENT_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_AI06_VENDOR_DEV2_PRESENT_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_AI06_VENDOR_DEV2_PRESENT_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI10 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI10_AN_SELECTOR_FIELD_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI10_AN_SELECTOR_FIELD_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_AI10_AN_D_12_5_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_AI10_AN_D_12_5_MASK 0x1FE0
+#define NIC0_SERDES0_LANE1_REGISTER_AI10_AN_REMOTE_FAULT_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_AI10_AN_REMOTE_FAULT_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_AI10_AN_ACK_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_AI10_AN_ACK_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_AI10_AN_NP_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_AI10_AN_NP_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI11 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI11_AN_D_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI11_AN_D_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI12 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI12_AN_D_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI12_AN_D_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI13 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI13_AN_D_LP_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI13_AN_D_LP_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI14 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI14_AN_D_LP_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI14_AN_D_LP_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI15 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI15_AN_D_LP_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI15_AN_D_LP_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI16 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI16_MSG_UFC_FIELD_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI16_MSG_UFC_FIELD_MASK 0x7FF
+#define NIC0_SERDES0_LANE1_REGISTER_AI16_TOGGLE_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_AI16_TOGGLE_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_AI16_ACK2_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_AI16_ACK2_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_AI16_MSG_PAGE_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_AI16_MSG_PAGE_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_AI16_RSVD_AI16_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_AI16_RSVD_AI16_14_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_AI16_NEXT_PAGE_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_AI16_NEXT_PAGE_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI17 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI17_UFC_FIELD_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI17_UFC_FIELD_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI18 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI18_UFC_FIELD2_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI18_UFC_FIELD2_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI19 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI19_MSG_UFC_FIELD_LP_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI19_MSG_UFC_FIELD_LP_MASK 0x7FF
+#define NIC0_SERDES0_LANE1_REGISTER_AI19_TOGGLE_LP_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_AI19_TOGGLE_LP_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_AI19_ACK2_LP_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_AI19_ACK2_LP_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_AI19_MSG_PAGE_LP_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_AI19_MSG_PAGE_LP_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_AI19_ACK_LP_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_AI19_ACK_LP_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_AI19_NEXT_PAGE_LP_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_AI19_NEXT_PAGE_LP_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI1A */
+#define NIC0_SERDES0_LANE1_REGISTER_AI1A_UFC1_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI1A_UFC1_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI1B */
+#define NIC0_SERDES0_LANE1_REGISTER_AI1B_UFC2_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI1B_UFC2_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI30 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BP_AN_ABILITY_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BP_AN_ABILITY_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_1000_KX_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_1000_KX_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_10G_KX4_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_10G_KX4_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_10G_KR_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_10G_KR_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_R_FEC_NEGOTIATED_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_R_FEC_NEGOTIATED_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_40G_KR4_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_40G_KR4_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_40G_CR4_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_40G_CR4_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_RS_FEC_NEGOTIATED_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_RS_FEC_NEGOTIATED_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_100G_CR10_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_100G_CR10_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_100G_KP4_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_100G_KP4_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_100G_KR4_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_100G_KR4_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_100G_CR4_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_100G_CR4_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_25G_KRS_CRS_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_25G_KRS_CRS_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_25G_KR_CR_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_25G_KR_CR_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_2P5_KX_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_2P5_KX_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_5G_KR_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_AI30_BASE_5G_KR_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI31 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI31_BASE_50G_KR_CR_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI31_BASE_50G_KR_CR_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_AI31_BASE_100G_KR2_CR2_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_AI31_BASE_100G_KR2_CR2_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_AI31_BASE_200G_KR4_CR4_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_AI31_BASE_200G_KR4_CR4_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_AI31_RSVD_AI31_15_03_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_AI31_RSVD_AI31_15_03_MASK 0xFFF8
+
+/* NIC0_SERDES0_LANE1_REGISTER_AI40 */
+#define NIC0_SERDES0_LANE1_REGISTER_AI40_RSVD_AI40_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AI40_RSVD_AI40_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_AI40_BASE_25G_KR1_CONSORTIUM_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_AI40_BASE_25G_KR1_CONSORTIUM_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_AI40_BASE_25G_CR1_CONSORTIUM_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_AI40_BASE_25G_CR1_CONSORTIUM_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_AI40_BASE_50G_KR2_CONSORTIUM_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_AI40_BASE_50G_KR2_CONSORTIUM_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_AI40_BASE_50G_CR2_CONSORTIUM_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_AI40_BASE_50G_CR2_CONSORTIUM_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_AI40_RSVD_AI40_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_AI40_RSVD_AI40_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AIF0 */
+#define NIC0_SERDES0_LANE1_REGISTER_AIF0_AN_NEXT_PAGE_C_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AIF0_AN_NEXT_PAGE_C_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AIF1 */
+#define NIC0_SERDES0_LANE1_REGISTER_AIF1_AN_NEXT_PAGE_C_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AIF1_AN_NEXT_PAGE_C_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AIF2 */
+#define NIC0_SERDES0_LANE1_REGISTER_AIF2_AN_NEXT_PAGE_C_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AIF2_AN_NEXT_PAGE_C_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AIF3 */
+#define NIC0_SERDES0_LANE1_REGISTER_AIF3_AN_NP_UF_C_14_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AIF3_AN_NP_UF_C_14_0_MASK 0x7FFF
+#define NIC0_SERDES0_LANE1_REGISTER_AIF3_NP_C_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_AIF3_NP_C_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AIF4 */
+#define NIC0_SERDES0_LANE1_REGISTER_AIF4_AN_NP_UF_C_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AIF4_AN_NP_UF_C_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AIF5 */
+#define NIC0_SERDES0_LANE1_REGISTER_AIF5_AN_NP_UF_C_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AIF5_AN_NP_UF_C_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AIF6 */
+#define NIC0_SERDES0_LANE1_REGISTER_AIF6_OUI_MP4_VALID_CODE_C_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AIF6_OUI_MP4_VALID_CODE_C_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AIF7 */
+#define NIC0_SERDES0_LANE1_REGISTER_AIF7_OUI_MP5_VALID_CODE_C_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AIF7_OUI_MP5_VALID_CODE_C_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AIF8 */
+#define NIC0_SERDES0_LANE1_REGISTER_AIF8_OUI_MP5_VALID_CODE_C_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AIF8_OUI_MP5_VALID_CODE_C_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AIF9 */
+#define NIC0_SERDES0_LANE1_REGISTER_AIF9_TX_ARG_NULL_MP_S_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AIF9_TX_ARG_NULL_MP_S_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AIFA */
+#define NIC0_SERDES0_LANE1_REGISTER_AIFA_TX_ARG_NULL_MP_S_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AIFA_TX_ARG_NULL_MP_S_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AIFB */
+#define NIC0_SERDES0_LANE1_REGISTER_AIFB_TX_ARG_NULL_MP_S_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AIFB_TX_ARG_NULL_MP_S_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AIFC */
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_1000_KX_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_1000_KX_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_10G_KX4_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_10G_KX4_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_10G_KR_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_10G_KR_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_40G_KR4_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_40G_KR4_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_40G_CR4_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_40G_CR4_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_100G_CR10_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_100G_CR10_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_100G_KP4_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_100G_KP4_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_100G_KR4_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_100G_KR4_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_100G_CR4_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_100G_CR4_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_25G_KRS_CRS_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_25G_KRS_CRS_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_25G_KR_CR_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_25G_KR_CR_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_2P5G_KX_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_2P5G_KX_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_5G_KR_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_5G_KR_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_50G_KR_CR_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_50G_KR_CR_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_100G_KR2_CR2_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_100G_KR2_CR2_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_200G_KR4_CR4_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC_READ_BACK_BASE_200G_KR4_CR4_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT00 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT00_TRAINING_RESTART_SC_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT00_TRAINING_RESTART_SC_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_LT00_TRAINING_EN_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_LT00_TRAINING_EN_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_LT00_RSVD_LT00_15_02_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_LT00_RSVD_LT00_15_02_MASK 0xFFFC
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT04 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_READOUT_TXSTATE_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_READOUT_TXSTATE_MASK 0x1F
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_SIG_DET_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_SIG_DET_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_TX_TRAINING_DATA_EN_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_TX_TRAINING_DATA_EN_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_TRAINING_FAILURE_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_TRAINING_FAILURE_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_READOUT_TRAINING_STATE_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_READOUT_TRAINING_STATE_MASK 0x700
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_RX_TRAINED_FLAG_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_RX_TRAINED_FLAG_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_FRAME_LOCK_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_FRAME_LOCK_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_RSVD_LT04_15_13_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_LT04_RSVD_LT04_15_13_MASK 0xE000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT05 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT05_DME_ERROR_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT05_DME_ERROR_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT06 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT06_MAX_WAIT_TIMER_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT06_MAX_WAIT_TIMER_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT07 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT07_MAX_WAIT_TIMER_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT07_MAX_WAIT_TIMER_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT08 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT08_WAIT_TIMER_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT08_WAIT_TIMER_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT09 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT09_WAIT_TIMER_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT09_WAIT_TIMER_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT0A */
+#define NIC0_SERDES0_LANE1_REGISTER_LT0A_RSVD_LT0A_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT0A_RSVD_LT0A_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_LT0A_RSVD_LT0A_04_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_LT0A_RSVD_LT0A_04_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_LT0A_TOTAL_POWER_MAX_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_LT0A_TOTAL_POWER_MAX_MASK 0x7E0
+#define NIC0_SERDES0_LANE1_REGISTER_LT0A_RSVD_LT0A_11_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_LT0A_RSVD_LT0A_11_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_LT0A_TRAINING_STATE_OW_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT0A_TRAINING_STATE_OW_MASK 0x7000
+#define NIC0_SERDES0_LANE1_REGISTER_LT0A_TRAINING_STATE_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT0A_TRAINING_STATE_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT0B */
+#define NIC0_SERDES0_LANE1_REGISTER_LT0B_TAPM1_MIN_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT0B_TAPM1_MIN_VAL_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_LT0B_RSVD_LT0B_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT0B_RSVD_LT0B_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT0B_TAPM1_MAX_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT0B_TAPM1_MAX_VAL_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT0B_RSVD_LT0B_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT0B_RSVD_LT0B_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT0C */
+#define NIC0_SERDES0_LANE1_REGISTER_LT0C_TAPM1_INI_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT0C_TAPM1_INI_VAL_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_LT0C_RSVD_LT0C_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT0C_RSVD_LT0C_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT0C_TAPM1_PRESET_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT0C_TAPM1_PRESET_VAL_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT0C_RSVD_LT0C_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT0C_RSVD_LT0C_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT0D */
+#define NIC0_SERDES0_LANE1_REGISTER_LT0D_TAP0_MIN_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT0D_TAP0_MIN_VAL_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_LT0D_RSVD_LT0D_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT0D_RSVD_LT0D_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT0D_TAP0_MAX_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT0D_TAP0_MAX_VAL_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT0D_RSVD_LT0D_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT0D_RSVD_LT0D_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT0E */
+#define NIC0_SERDES0_LANE1_REGISTER_LT0E_TAP0_INI_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT0E_TAP0_INI_VAL_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_LT0E_RSVD_LT0E_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT0E_RSVD_LT0E_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT0E_TAP0_PRESET_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT0E_TAP0_PRESET_VAL_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT0E_RSVD_LT0E_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT0E_RSVD_LT0E_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT0F */
+#define NIC0_SERDES0_LANE1_REGISTER_LT0F_TAP1_MIN_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT0F_TAP1_MIN_VAL_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_LT0F_RSVD_LT0F_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT0F_RSVD_LT0F_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT0F_TAP1_MAX_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT0F_TAP1_MAX_VAL_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT0F_RSVD_LT0F_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT0F_RSVD_LT0F_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT10 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT10_TAP1_INI_VAL_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT10_TAP1_INI_VAL_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_LT10_RSVD_LT10_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT10_RSVD_LT10_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT10_TAP1_PRESET_VAL_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT10_TAP1_PRESET_VAL_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT10_RSVD_LT10_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT10_RSVD_LT10_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT11 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT11_LP_COEFF_M1UPDATE_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT11_LP_COEFF_M1UPDATE_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_LT11_LP_COEFF_0UPDATE_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_LT11_LP_COEFF_0UPDATE_MASK 0xC
+#define NIC0_SERDES0_LANE1_REGISTER_LT11_LP_COEFF_1UPDATE_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_LT11_LP_COEFF_1UPDATE_MASK 0x30
+#define NIC0_SERDES0_LANE1_REGISTER_LT11_RSVD_LT11_11_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT11_RSVD_LT11_11_06_MASK 0xFC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT11_LP_INIT_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT11_LP_INIT_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_LT11_LP_PRESET_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_LT11_LP_PRESET_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_LT11_RSVD_LT11_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT11_RSVD_LT11_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT12 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_COEFF_M1UPDATE_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_COEFF_M1UPDATE_OW_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_COEFF_0UPDATE_OW_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_COEFF_0UPDATE_OW_MASK 0xC
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_COEFF_1UPDATE_OW_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_COEFF_1UPDATE_OW_MASK 0x30
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_COEFF_M1UPDATE_OWEN_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_COEFF_M1UPDATE_OWEN_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_COEFF_0UPDATE_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_COEFF_0UPDATE_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_COEFF_1UPDATE_OWEN_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_COEFF_1UPDATE_OWEN_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_RSVD_LT12_11_09_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_RSVD_LT12_11_09_MASK 0xE00
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_INIT_OW_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_INIT_OW_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_PRESET_OW_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_PRESET_OW_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_INIT_OWEN_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_INIT_OWEN_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_PRESET_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT12_LP_PRESET_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT13 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT13_LP_COEFF_M1STATUS_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT13_LP_COEFF_M1STATUS_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_LT13_LP_COEFF_0STATUS_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_LT13_LP_COEFF_0STATUS_MASK 0xC
+#define NIC0_SERDES0_LANE1_REGISTER_LT13_LP_COEFF_1STATUS_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_LT13_LP_COEFF_1STATUS_MASK 0x30
+#define NIC0_SERDES0_LANE1_REGISTER_LT13_RSVD_LT13_14_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT13_RSVD_LT13_14_06_MASK 0x7FC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT13_LP_RECEIVER_READY_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT13_LP_RECEIVER_READY_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT14 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_COEFF_M1STATUS_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_COEFF_M1STATUS_OW_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_COEFF_0STATUS_OW_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_COEFF_0STATUS_OW_MASK 0xC
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_COEFF_1STATUS_OW_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_COEFF_1STATUS_OW_MASK 0x30
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_COEFF_M1STATUS_OWEN_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_COEFF_M1STATUS_OWEN_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_COEFF_0STATUS_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_COEFF_0STATUS_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_COEFF_1STATUS_OWEN_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_COEFF_1STATUS_OWEN_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_RSVD_LT14_13_09_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_RSVD_LT14_13_09_MASK 0x3E00
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_RECEIVER_READY_OW_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_RECEIVER_READY_OW_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_RECEIVER_READY_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT14_LP_RECEIVER_READY_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT15 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT15_LD_COEFF_M1UPDATE_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT15_LD_COEFF_M1UPDATE_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_LT15_LD_COEFF_0UPDATE_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_LT15_LD_COEFF_0UPDATE_MASK 0xC
+#define NIC0_SERDES0_LANE1_REGISTER_LT15_LD_COEFF_1UPDATE_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_LT15_LD_COEFF_1UPDATE_MASK 0x30
+#define NIC0_SERDES0_LANE1_REGISTER_LT15_RSVD_LT15_11_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT15_RSVD_LT15_11_06_MASK 0xFC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT15_LD_INIT_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT15_LD_INIT_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_LT15_LD_PRESET_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_LT15_LD_PRESET_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_LT15_RSVD_LT15_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT15_RSVD_LT15_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT16 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_COEFF_M1UPDATE_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_COEFF_M1UPDATE_OW_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_COEFF_0UPDATE_OW_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_COEFF_0UPDATE_OW_MASK 0xC
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_COEFF_1UPDATE_OW_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_COEFF_1UPDATE_OW_MASK 0x30
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_COEFF_M1UPDATE_OWEN_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_COEFF_M1UPDATE_OWEN_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_COEFF_0UPDATE_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_COEFF_0UPDATE_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_COEFF_1UPDATE_OWEN_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_COEFF_1UPDATE_OWEN_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_RSVD_LT16_11_09_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_RSVD_LT16_11_09_MASK 0xE00
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_INIT_OW_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_INIT_OW_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_PRESET_OW_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_PRESET_OW_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_INIT_OWEN_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_INIT_OWEN_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_PRESET_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT16_LD_PRESET_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT17 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT17_LD_COEFF_M1STATUS_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT17_LD_COEFF_M1STATUS_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_LT17_LD_COEFF_0STATUS_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_LT17_LD_COEFF_0STATUS_MASK 0xC
+#define NIC0_SERDES0_LANE1_REGISTER_LT17_LD_COEFF_1STATUS_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_LT17_LD_COEFF_1STATUS_MASK 0x30
+#define NIC0_SERDES0_LANE1_REGISTER_LT17_RSVD_LT17_14_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT17_RSVD_LT17_14_06_MASK 0x7FC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT17_LD_RECEIVER_READY_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT17_LD_RECEIVER_READY_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT18 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_COEFF_M1STATUS_OW_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_COEFF_M1STATUS_OW_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_COEFF_0STATUS_OW_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_COEFF_0STATUS_OW_MASK 0xC
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_COEFF_1STATUS_OW_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_COEFF_1STATUS_OW_MASK 0x30
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_COEFF_M1STATUS_OWEN_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_COEFF_M1STATUS_OWEN_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_COEFF_0STATUS_OWEN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_COEFF_0STATUS_OWEN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_COEFF_1STATUS_OWEN_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_COEFF_1STATUS_OWEN_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_RSVD_LT18_13_09_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_RSVD_LT18_13_09_MASK 0x3E00
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_RECEIVER_READY_OW_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_RECEIVER_READY_OW_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_RECEIVER_READY_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT18_LD_RECEIVER_READY_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT19 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_SEND_CLEAR_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_SEND_CLEAR_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_RX_TRAINED_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_RX_TRAINED_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_AUTO_FINISH_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_AUTO_FINISH_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_COEFF1_FRAME_DEC_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_COEFF1_FRAME_DEC_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_COEFF1_FRAME_INC_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_COEFF1_FRAME_INC_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_COEFFM1_FRAME_DEC_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_COEFFM1_FRAME_DEC_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_COEFFM1_FRAME_INC_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_COEFFM1_FRAME_INC_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_COEFF0_FRAME_DEC_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_COEFF0_FRAME_DEC_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_COEFF0_FRAME_INC_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_COEFF0_FRAME_INC_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_INI_FRAME_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_INI_FRAME_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_PRESET_FRAME_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_PRESET_FRAME_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_HOLD_FRAME_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_HOLD_FRAME_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_DIS_AN_START_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_DIS_AN_START_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_TRAINING_RESET_ALL_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_TRAINING_RESET_ALL_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_RSVD_LT19_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT19_RSVD_LT19_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT1A */
+#define NIC0_SERDES0_LANE1_REGISTER_LT1A_FINISH_CNTR_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT1A_FINISH_CNTR_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT1B */
+#define NIC0_SERDES0_LANE1_REGISTER_LT1B_FINISH_CNTR_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT1B_FINISH_CNTR_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT1C */
+#define NIC0_SERDES0_LANE1_REGISTER_LT1C_TRAIN_INST_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT1C_TRAIN_INST_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT1D */
+#define NIC0_SERDES0_LANE1_REGISTER_LT1D_TRAIN_INST_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT1D_TRAIN_INST_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT1E */
+#define NIC0_SERDES0_LANE1_REGISTER_LT1E_TRAIN_INST_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT1E_TRAIN_INST_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT1F */
+#define NIC0_SERDES0_LANE1_REGISTER_LT1F_TRAIN_INST_63_48_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT1F_TRAIN_INST_63_48_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT20 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT20_TRAIN_INST_79_64_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT20_TRAIN_INST_79_64_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT21 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT21_TRAIN_INST_95_80_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT21_TRAIN_INST_95_80_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT22 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT22_TRAIN_INST_111_96_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT22_TRAIN_INST_111_96_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT23 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT23_TRAIN_INST_127_112_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT23_TRAIN_INST_127_112_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT24 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT24_RSVD_LT24_13_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT24_RSVD_LT24_13_00_MASK 0x3FFF
+#define NIC0_SERDES0_LANE1_REGISTER_LT24_TRAIN_MODE_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT24_TRAIN_MODE_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT25 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT25_HOLDOFF_TIMER_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT25_HOLDOFF_TIMER_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT26 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT26_HOLDOFF_TIMER_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT26_HOLDOFF_TIMER_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT29 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT29_RSVD_LT29_03_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT29_RSVD_LT29_03_00_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_LT29_RSVD_LT29_07_04_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_LT29_RSVD_LT29_07_04_MASK 0xF0
+#define NIC0_SERDES0_LANE1_REGISTER_LT29_TOTAL_POWER_MAX_50G_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT29_TOTAL_POWER_MAX_50G_MASK 0x7F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT29_RSVD_LT29_15_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT29_RSVD_LT29_15_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT2A */
+#define NIC0_SERDES0_LANE1_REGISTER_LT2A_TAP0_MIN_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT2A_TAP0_MIN_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_LT2A_RSVD_LT2A_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT2A_RSVD_LT2A_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT2A_TAP0_MAX_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT2A_TAP0_MAX_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT2A_RSVD_LT2A_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT2A_RSVD_LT2A_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT2B */
+#define NIC0_SERDES0_LANE1_REGISTER_LT2B_TAP0_PRESET2_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT2B_TAP0_PRESET2_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_LT2B_RSVD_LT2B_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT2B_RSVD_LT2B_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT2B_TAP0_PRESET1_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT2B_TAP0_PRESET1_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT2B_RSVD_LT2B_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT2B_RSVD_LT2B_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT2C */
+#define NIC0_SERDES0_LANE1_REGISTER_LT2C_RSVD_LT2C_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT2C_RSVD_LT2C_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_LT2C_TAP0_PRESET3_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT2C_TAP0_PRESET3_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT2C_RSVD_LT2C_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT2C_RSVD_LT2C_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT2D */
+#define NIC0_SERDES0_LANE1_REGISTER_LT2D_TAP1_MIN_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT2D_TAP1_MIN_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_LT2D_RSVD_LT2D_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT2D_RSVD_LT2D_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT2D_TAP1_MAX_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT2D_TAP1_MAX_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT2D_RSVD_LT2D_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT2D_RSVD_LT2D_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT2E */
+#define NIC0_SERDES0_LANE1_REGISTER_LT2E_TAP1_PRESET2_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT2E_TAP1_PRESET2_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_LT2E_RSVD_LT2E_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT2E_RSVD_LT2E_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT2E_TAP1_PRESET1_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT2E_TAP1_PRESET1_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT2E_RSVD_LT2E_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT2E_RSVD_LT2E_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT2F */
+#define NIC0_SERDES0_LANE1_REGISTER_LT2F_RSVD_LT2F_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT2F_RSVD_LT2F_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_LT2F_TAP1_PRESET3_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT2F_TAP1_PRESET3_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT2F_RSVD_LT2F_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT2F_RSVD_LT2F_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT30 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT30_TAPM1_MIN_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT30_TAPM1_MIN_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_LT30_RSVD_LT30_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT30_RSVD_LT30_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT30_TAPM1_MAX_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT30_TAPM1_MAX_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT30_RSVD_LT30_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT30_RSVD_LT30_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT31 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT31_TAPM1_PRESET2_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT31_TAPM1_PRESET2_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_LT31_RSVD_LT31_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT31_RSVD_LT31_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT31_TAPM1_PRESET1_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT31_TAPM1_PRESET1_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT31_RSVD_LT31_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT31_RSVD_LT31_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT32 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT32_RSVD_LT32_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT32_RSVD_LT32_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_LT32_TAPM1_PRESET3_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT32_TAPM1_PRESET3_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT32_RSVD_LT32_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT32_RSVD_LT32_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT33 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT33_TAPM2_MIN_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT33_TAPM2_MIN_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_LT33_RSVD_LT33_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT33_RSVD_LT33_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT33_TAPM2_MAX_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT33_TAPM2_MAX_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT33_RSVD_LT33_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT33_RSVD_LT33_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT34 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT34_TAPM2_PRESET2_VAL_50G_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT34_TAPM2_PRESET2_VAL_50G_MASK 0x3F
+#define NIC0_SERDES0_LANE1_REGISTER_LT34_RSVD_LT34_07_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT34_RSVD_LT34_07_06_MASK 0xC0
+#define NIC0_SERDES0_LANE1_REGISTER_LT34_TAPM2_PRESET1_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT34_TAPM2_PRESET1_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT34_RSVD_LT34_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT34_RSVD_LT34_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT35 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT35_RSVD_LT35_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT35_RSVD_LT35_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_LT35_TAPM2_PRESET3_VAL_50G_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT35_TAPM2_PRESET3_VAL_50G_MASK 0x3F00
+#define NIC0_SERDES0_LANE1_REGISTER_LT35_RSVD_LT35_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT35_RSVD_LT35_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT36 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT36_FINISH_CNTR_50G_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT36_FINISH_CNTR_50G_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT37 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT37_FINISH_CNTR_50G_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT37_FINISH_CNTR_50G_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT38 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT38_TRAIN_INST_50G_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT38_TRAIN_INST_50G_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT39 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT39_TRAIN_INST_50G_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT39_TRAIN_INST_50G_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT3A */
+#define NIC0_SERDES0_LANE1_REGISTER_LT3A_TRAIN_INST_50G_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT3A_TRAIN_INST_50G_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT3B */
+#define NIC0_SERDES0_LANE1_REGISTER_LT3B_TRAIN_INST_50G_63_48_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT3B_TRAIN_INST_50G_63_48_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT3C */
+#define NIC0_SERDES0_LANE1_REGISTER_LT3C_TRAIN_INST_50G_79_64_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT3C_TRAIN_INST_50G_79_64_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT3D */
+#define NIC0_SERDES0_LANE1_REGISTER_LT3D_TRAIN_INST_50G_95_80_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT3D_TRAIN_INST_50G_95_80_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT3E */
+#define NIC0_SERDES0_LANE1_REGISTER_LT3E_TRAIN_INST_50G_111_96_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT3E_TRAIN_INST_50G_111_96_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT3F */
+#define NIC0_SERDES0_LANE1_REGISTER_LT3F_TRAIN_INST_50G_127_112_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT3F_TRAIN_INST_50G_127_112_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT40 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT40_TRAIN_INST_50G_143_128_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT40_TRAIN_INST_50G_143_128_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT41 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT41_TRAIN_INST_50G_159_144_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT41_TRAIN_INST_50G_159_144_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT42 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_RSVD_LT42_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_RSVD_LT42_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_COEFF_REQ_OW_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_COEFF_REQ_OW_MASK 0x18
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_COEFF_REQ_OWEN_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_COEFF_REQ_OWEN_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_COEFF_SEL_OW_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_COEFF_SEL_OW_MASK 0x1C0
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_COEFF_SEL_OWEN_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_COEFF_SEL_OWEN_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_MOD_PREC_REQ_OW_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_MOD_PREC_REQ_OW_MASK 0xC00
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_MOD_PREC_REQ_OWEN_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_MOD_PREC_REQ_OWEN_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_IC_REQ_OW_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_IC_REQ_OW_MASK 0x6000
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_IC_REQ_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT42_LP_IC_REQ_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT43 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_RSVD_LT43_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_RSVD_LT43_00_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_RCV_TF_LOCK_STS_OW_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_RCV_TF_LOCK_STS_OW_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_RCV_TF_LOCK_STS_OWEN_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_RCV_TF_LOCK_STS_OWEN_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_COEFF_STS_OW_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_COEFF_STS_OW_MASK 0x38
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_COEFF_STS_OWEN_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_COEFF_STS_OWEN_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_COEFF_STS_SEL_OW_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_COEFF_STS_SEL_OW_MASK 0x380
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_COEFF_STS_SEL_OWEN_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_COEFF_STS_SEL_OWEN_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_IC_STS_OW_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_IC_STS_OW_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_IC_STS_OWEN_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_IC_STS_OWEN_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_MOD_PREC_STS_OW_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_MOD_PREC_STS_OW_MASK 0x6000
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_MOD_PREC_STS_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT43_LP_MOD_PREC_STS_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT44 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_RSVD_LT44_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_RSVD_LT44_00_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_RCV_TF_LOCK_STS_OW_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_RCV_TF_LOCK_STS_OW_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_RCV_TF_LOCK_STS_OWEN_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_RCV_TF_LOCK_STS_OWEN_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_COEFF_REQ_OW_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_COEFF_REQ_OW_MASK 0x18
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_COEFF_REQ_OWEN_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_COEFF_REQ_OWEN_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_COEFF_SEL_OW_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_COEFF_SEL_OW_MASK 0x1C0
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_COEFF_SEL_OWEN_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_COEFF_SEL_OWEN_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_MOD_PREC_REQ_OW_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_MOD_PREC_REQ_OW_MASK 0xC00
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_MOD_PREC_REQ_OWEN_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_MOD_PREC_REQ_OWEN_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_IC_REQ_OW_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_IC_REQ_OW_MASK 0x6000
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_IC_REQ_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT44_LD_IC_REQ_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT45 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_RSVD_LT45_02_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_RSVD_LT45_02_00_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_COEFF_STS_OW_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_COEFF_STS_OW_MASK 0x38
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_COEFF_STS_OWEN_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_COEFF_STS_OWEN_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_COEFF_STS_SEL_OW_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_COEFF_STS_SEL_OW_MASK 0x380
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_COEFF_STS_SEL_OWEN_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_COEFF_STS_SEL_OWEN_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_IC_STS_OW_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_IC_STS_OW_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_IC_STS_OWEN_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_IC_STS_OWEN_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_MOD_PREC_STS_OW_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_MOD_PREC_STS_OW_MASK 0x6000
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_MOD_PREC_STS_OWEN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT45_LD_MOD_PREC_STS_OWEN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT4E */
+#define NIC0_SERDES0_LANE1_REGISTER_LT4E_SEED_10_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT4E_SEED_10_0_MASK 0x7FF
+#define NIC0_SERDES0_LANE1_REGISTER_LT4E_POLYNOMIAL_IDENTIFIER_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_LT4E_POLYNOMIAL_IDENTIFIER_MASK 0x1800
+#define NIC0_SERDES0_LANE1_REGISTER_LT4E_RSVD_LT4E_13_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_LT4E_RSVD_LT4E_13_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_LT4E_SEED_12_11_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT4E_SEED_12_11_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT4F */
+#define NIC0_SERDES0_LANE1_REGISTER_LT4F_CNTR_25G_START_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT4F_CNTR_25G_START_MASK 0x3FFF
+#define NIC0_SERDES0_LANE1_REGISTER_LT4F_RECORD_CLEAR_25G_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT4F_RECORD_CLEAR_25G_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_LT4F_RECORD_25G_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT4F_RECORD_25G_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT50 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT50_RECORD_FRAME_25G_119_104_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT50_RECORD_FRAME_25G_119_104_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT51 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT51_RECORD_FRAME_25G_103_88_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT51_RECORD_FRAME_25G_103_88_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT52 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT52_RECORD_FRAME_25G_87_72_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT52_RECORD_FRAME_25G_87_72_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT53 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT53_RECORD_FRAME_25G_71_56_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT53_RECORD_FRAME_25G_71_56_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT54 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT54_RECORD_FRAME_25G_55_40_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT54_RECORD_FRAME_25G_55_40_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT55 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT55_RECORD_FRAME_25G_39_24_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT55_RECORD_FRAME_25G_39_24_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT56 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT56_RECORD_FRAME_25G_23_8_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT56_RECORD_FRAME_25G_23_8_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT57 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT57_RSVD_LT57_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT57_RSVD_LT57_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_LT57_RECORD_FRAME_25G_7_0_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT57_RECORD_FRAME_25G_7_0_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT58 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT58_CNTR_50G_START_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT58_CNTR_50G_START_MASK 0x3FFF
+#define NIC0_SERDES0_LANE1_REGISTER_LT58_RECORD_CLEAR_50G_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT58_RECORD_CLEAR_50G_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_LT58_RECORD_50G_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT58_RECORD_50G_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT59 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT59_RECORD_FRAME_50G_191_176_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT59_RECORD_FRAME_50G_191_176_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT5A */
+#define NIC0_SERDES0_LANE1_REGISTER_LT5A_RECORD_FRAME_50G_175_160_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT5A_RECORD_FRAME_50G_175_160_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT5B */
+#define NIC0_SERDES0_LANE1_REGISTER_LT5B_RECORD_FRAME_50G_159_144_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT5B_RECORD_FRAME_50G_159_144_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT5C */
+#define NIC0_SERDES0_LANE1_REGISTER_LT5C_RECORD_FRAME_50G_143_128_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT5C_RECORD_FRAME_50G_143_128_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT5D */
+#define NIC0_SERDES0_LANE1_REGISTER_LT5D_RECORD_FRAME_50G_127_112_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT5D_RECORD_FRAME_50G_127_112_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT5E */
+#define NIC0_SERDES0_LANE1_REGISTER_LT5E_RECORD_FRAME_50G_111_96_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT5E_RECORD_FRAME_50G_111_96_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT5F */
+#define NIC0_SERDES0_LANE1_REGISTER_LT5F_RECORD_FRAME_50G_95_80_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT5F_RECORD_FRAME_50G_95_80_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT60 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT60_RECORD_FRAME_50G_79_64_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT60_RECORD_FRAME_50G_79_64_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT61 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT61_RECORD_FRAME_50G_63_48_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT61_RECORD_FRAME_50G_63_48_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT62 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT62_RECORD_FRAME_50G_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT62_RECORD_FRAME_50G_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT63 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT63_RECORD_FRAME_50G_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT63_RECORD_FRAME_50G_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT64 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT64_RECORD_FRAME_50G_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT64_RECORD_FRAME_50G_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT67 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT67_LP_COEFF_REQ_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT67_LP_COEFF_REQ_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_LT67_LP_COEFF_SEL_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_LT67_LP_COEFF_SEL_MASK 0x1C
+#define NIC0_SERDES0_LANE1_REGISTER_LT67_RSVD_LT67_07_05_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_LT67_RSVD_LT67_07_05_MASK 0xE0
+#define NIC0_SERDES0_LANE1_REGISTER_LT67_LP_MOD_PREC_REQ_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT67_LP_MOD_PREC_REQ_MASK 0x300
+#define NIC0_SERDES0_LANE1_REGISTER_LT67_RSVD_LT67_11_10_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_LT67_RSVD_LT67_11_10_MASK 0xC00
+#define NIC0_SERDES0_LANE1_REGISTER_LT67_LP_IC_REQ_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT67_LP_IC_REQ_MASK 0x3000
+#define NIC0_SERDES0_LANE1_REGISTER_LT67_RSVD_LT67_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT67_RSVD_LT67_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT68 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_LP_COEFF_STS_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_LP_COEFF_STS_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_LP_COEFF_STS_SEL_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_LP_COEFF_STS_SEL_MASK 0x38
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_RSVD_LT68_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_RSVD_LT68_06_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_LP_PARITY_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_LP_PARITY_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_LP_IC_STS_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_LP_IC_STS_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_LP_RCV_TF_LOCK_STS_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_LP_RCV_TF_LOCK_STS_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_LP_MOD_PREC_STS_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_LP_MOD_PREC_STS_MASK 0xC00
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_RSVD_LT68_14_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_RSVD_LT68_14_12_MASK 0x7000
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_LP_RECEIVER_READY_50G_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT68_LP_RECEIVER_READY_50G_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT69 */
+#define NIC0_SERDES0_LANE1_REGISTER_LT69_LD_COEFF_REQ_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT69_LD_COEFF_REQ_MASK 0x3
+#define NIC0_SERDES0_LANE1_REGISTER_LT69_LD_COEFF_SEL_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_LT69_LD_COEFF_SEL_MASK 0x1C
+#define NIC0_SERDES0_LANE1_REGISTER_LT69_RSVD_LT69_07_05_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_LT69_RSVD_LT69_07_05_MASK 0xE0
+#define NIC0_SERDES0_LANE1_REGISTER_LT69_LD_MOD_PREC_REQ_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT69_LD_MOD_PREC_REQ_MASK 0x300
+#define NIC0_SERDES0_LANE1_REGISTER_LT69_RSVD_LT69_11_10_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_LT69_RSVD_LT69_11_10_MASK 0xC00
+#define NIC0_SERDES0_LANE1_REGISTER_LT69_LD_IC_REQ_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT69_LD_IC_REQ_MASK 0x3000
+#define NIC0_SERDES0_LANE1_REGISTER_LT69_RSVD_LT69_15_14_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_LT69_RSVD_LT69_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_LANE1_REGISTER_LT6A */
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_LD_COEFF_STS_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_LD_COEFF_STS_MASK 0x7
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_LD_COEFF_STS_SEL_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_LD_COEFF_STS_SEL_MASK 0x38
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_RSVD_LT6A_06_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_RSVD_LT6A_06_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_LD_PARITY_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_LD_PARITY_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_LD_IC_STS_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_LD_IC_STS_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_LD_RCV_TF_LOCK_STS_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_LD_RCV_TF_LOCK_STS_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_LD_MOD_PREC_STS_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_LD_MOD_PREC_STS_MASK 0xC00
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_RSVD_LT6A_14_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_RSVD_LT6A_14_12_MASK 0x7000
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_LD_RECEIVER_READY_50G_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A_LD_RECEIVER_READY_50G_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AN01 */
+#define NIC0_SERDES0_LANE1_REGISTER_AN01_AA_HCD_RESOLVED_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AN01_AA_HCD_RESOLVED_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_AN01_AN_FINISHED_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_AN01_AN_FINISHED_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_AN01_LINK_TRAINING_DONE_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_AN01_LINK_TRAINING_DONE_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_AN01_RSVD_AN01_15_03_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_AN01_RSVD_AN01_15_03_MASK 0xFFF8
+
+/* NIC0_SERDES0_LANE1_REGISTER_AN02 */
+#define NIC0_SERDES0_LANE1_REGISTER_AN02_COMPANY_OUI_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AN02_COMPANY_OUI_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AN03 */
+#define NIC0_SERDES0_LANE1_REGISTER_AN03_RSVD_AN03_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AN03_RSVD_AN03_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_AN03_COMPANY_OUI_BIT_23_16_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_AN03_COMPANY_OUI_BIT_23_16_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_AN04 */
+#define NIC0_SERDES0_LANE1_REGISTER_AN04_REVISION_NUM_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AN04_REVISION_NUM_MASK 0xF
+#define NIC0_SERDES0_LANE1_REGISTER_AN04_MODEL_NUM_ANEG_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_AN04_MODEL_NUM_ANEG_MASK 0x3F0
+#define NIC0_SERDES0_LANE1_REGISTER_AN04_RSVD_AN04_15_10_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_AN04_RSVD_AN04_15_10_MASK 0xFC00
+
+/* NIC0_SERDES0_LANE1_REGISTER_AN05 */
+#define NIC0_SERDES0_LANE1_REGISTER_AN05_PCS_ADVERTISE_ABILITY_S_BIT_22_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AN05_PCS_ADVERTISE_ABILITY_S_BIT_22_16_MASK 0x7F
+#define NIC0_SERDES0_LANE1_REGISTER_AN05_RSVD_AN05_07_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_AN05_RSVD_AN05_07_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_AN05_PCS_ADVERTISE_CONSORTIUM_25G_S_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_AN05_PCS_ADVERTISE_CONSORTIUM_25G_S_MASK 0x300
+#define NIC0_SERDES0_LANE1_REGISTER_AN05_PCS_ADVERTISE_CONSORTIUM_50G_S_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_AN05_PCS_ADVERTISE_CONSORTIUM_50G_S_MASK 0xC00
+#define NIC0_SERDES0_LANE1_REGISTER_AN05_RSVD_AN05_15_12_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_AN05_RSVD_AN05_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AN06 */
+#define NIC0_SERDES0_LANE1_REGISTER_AN06_PCS_ADVERTISE_ABILITY_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AN06_PCS_ADVERTISE_ABILITY_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AN07 */
+#define NIC0_SERDES0_LANE1_REGISTER_AN07_RSVD_AN07_07_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AN07_RSVD_AN07_07_00_MASK 0xFF
+#define NIC0_SERDES0_LANE1_REGISTER_AN07_PCS_ADVERTISE_FEC_S_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_AN07_PCS_ADVERTISE_FEC_S_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_AN07_PCS_ADVERTISE_CONSORTIUM_FEC_S_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_AN07_PCS_ADVERTISE_CONSORTIUM_FEC_S_MASK 0xF000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AN08 */
+#define NIC0_SERDES0_LANE1_REGISTER_AN08_MODE_25G_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AN08_MODE_25G_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_AN08_PCS_AUTONEG_S_EN_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_AN08_PCS_AUTONEG_S_EN_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_AN08_PCS_RESTART_AUTONEG_S_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_AN08_PCS_RESTART_AUTONEG_S_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_AN08_TX_NONCE_SEED_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_AN08_TX_NONCE_SEED_MASK 0xF8
+#define NIC0_SERDES0_LANE1_REGISTER_AN08_RSVD_AN08_15_08_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_AN08_RSVD_AN08_15_08_MASK 0xFF00
+
+/* NIC0_SERDES0_LANE1_REGISTER_AN09 */
+#define NIC0_SERDES0_LANE1_REGISTER_AN09_PCS_LINK_STATUS_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AN09_PCS_LINK_STATUS_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AN0A */
+#define NIC0_SERDES0_LANE1_REGISTER_AN0A_PCS_LINK_STATUS_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AN0A_PCS_LINK_STATUS_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AN10 */
+#define NIC0_SERDES0_LANE1_REGISTER_AN10_TX_AN_OR_LT_EN_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AN10_TX_AN_OR_LT_EN_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_AN10_TX_DW_SEL_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_AN10_TX_DW_SEL_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_AN10_RX_DW_SEL_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_AN10_RX_DW_SEL_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_AN10_RSVD_AN10_15_03_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_AN10_RSVD_AN10_15_03_MASK 0xFFF8
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK00 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_DIS_LINK_FAIL_INHIBIT_TIMER_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_DIS_LINK_FAIL_INHIBIT_TIMER_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_DIS_CONSORTIUM_RESOLUTION_S_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_DIS_CONSORTIUM_RESOLUTION_S_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_DIS_BP_RESOLUTION_S_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_DIS_BP_RESOLUTION_S_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_DIS_ACK_MATCH_IN_S2_S5_S_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_DIS_ACK_MATCH_IN_S2_S5_S_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_DIS_ACK2_CONSISTENCY_MATCH_S_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_DIS_ACK2_CONSISTENCY_MATCH_S_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_ACK2_CTRL_S_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_ACK2_CTRL_S_MASK 0x60
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_DIS_ECHO_NONCE_CHECK_S_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_DIS_ECHO_NONCE_CHECK_S_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_RX_ARG_DIS_TOGGLE_CHECK_S_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_RX_ARG_DIS_TOGGLE_CHECK_S_MASK 0x100
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_TX_ARG_DIS_TOGGLE_S_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_TX_ARG_DIS_TOGGLE_S_MASK 0x200
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_DIS_NONCE_MATCH_S_SHIFT 10
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_DIS_NONCE_MATCH_S_MASK 0x400
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_ANEG_SPEEDUP_S_SHIFT 11
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_ANEG_SPEEDUP_S_MASK 0x800
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_ANEG_IEEE_MODE_S_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_ANEG_IEEE_MODE_S_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_REG_RESET_ANEG_S_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_REG_RESET_ANEG_S_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_RESET_ANG_CSTM_REGS_S_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_RESET_ANG_CSTM_REGS_S_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_RESET_ANG_IEEE_REGS_S_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_AK00_ARG_RESET_ANG_IEEE_REGS_S_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK02 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_HCD_BIT_OW_VAL_BIT_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_HCD_BIT_OW_VAL_BIT_0_MASK 0x1
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_DIS_BP_FEC_BITS_FOR_CONSORTIUM_SPEED_SHIFT 1
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_DIS_BP_FEC_BITS_FOR_CONSORTIUM_SPEED_MASK 0x2
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_AA_MR_AUTONEG_COMPLETE_S_OW_VAL_SHIFT 2
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_AA_MR_AUTONEG_COMPLETE_S_OW_VAL_MASK 0x4
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_AA_MR_AUTONEG_COMPLETE_S_OW_EN_SHIFT 3
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_AA_MR_AUTONEG_COMPLETE_S_OW_EN_MASK 0x8
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_AA_AN_LINK_GOOD_S_OW_VAL_SHIFT 4
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_AA_AN_LINK_GOOD_S_OW_VAL_MASK 0x10
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_AA_AN_LINK_GOOD_S_OW_EN_SHIFT 5
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_AA_AN_LINK_GOOD_S_OW_EN_MASK 0x20
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_AA_HCD_RESOLVED_S_OW_VAL_SHIFT 6
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_AA_HCD_RESOLVED_S_OW_VAL_MASK 0x40
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_AA_HCD_RESOLVED_S_OW_EN_SHIFT 7
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_AA_HCD_RESOLVED_S_OW_EN_MASK 0x80
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_HCD_BIT_OW_VAL_BIT_4_1_SHIFT 8
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_HCD_BIT_OW_VAL_BIT_4_1_MASK 0xF00
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_FEC_KR_OW_VAL_SHIFT 12
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_FEC_KR_OW_VAL_MASK 0x1000
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_FEC_RS_OW_VAL_SHIFT 13
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_FEC_RS_OW_VAL_MASK 0x2000
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_FEC_RESOLUTION_OW_EN_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_FEC_RESOLUTION_OW_EN_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_HCD_BIT_OW_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_AK02_HCD_BIT_OW_EN_MASK 0x8000
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK11 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK11_AA_TX_PAGE_0_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK11_AA_TX_PAGE_0_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK12 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK12_AA_TX_PAGE_0_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK12_AA_TX_PAGE_0_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK13 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK13_AA_TX_PAGE_0_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK13_AA_TX_PAGE_0_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK14 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK14_AA_TX_PAGE_1_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK14_AA_TX_PAGE_1_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK15 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK15_AA_TX_PAGE_1_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK15_AA_TX_PAGE_1_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK16 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK16_AA_TX_PAGE_1_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK16_AA_TX_PAGE_1_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK17 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK17_AA_TX_PAGE_2_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK17_AA_TX_PAGE_2_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK18 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK18_AA_TX_PAGE_2_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK18_AA_TX_PAGE_2_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK19 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK19_AA_TX_PAGE_2_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK19_AA_TX_PAGE_2_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK1A */
+#define NIC0_SERDES0_LANE1_REGISTER_AK1A_AA_TX_PAGE_3_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK1A_AA_TX_PAGE_3_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK1B */
+#define NIC0_SERDES0_LANE1_REGISTER_AK1B_AA_TX_PAGE_3_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK1B_AA_TX_PAGE_3_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK1C */
+#define NIC0_SERDES0_LANE1_REGISTER_AK1C_AA_TX_PAGE_3_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK1C_AA_TX_PAGE_3_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK1D */
+#define NIC0_SERDES0_LANE1_REGISTER_AK1D_AA_TX_PAGE_4_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK1D_AA_TX_PAGE_4_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK1E */
+#define NIC0_SERDES0_LANE1_REGISTER_AK1E_AA_TX_PAGE_4_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK1E_AA_TX_PAGE_4_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK1F */
+#define NIC0_SERDES0_LANE1_REGISTER_AK1F_AA_TX_PAGE_4_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK1F_AA_TX_PAGE_4_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK20 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK20_AA_TX_PAGE_5_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK20_AA_TX_PAGE_5_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK21 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK21_AA_TX_PAGE_5_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK21_AA_TX_PAGE_5_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK22 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK22_AA_TX_PAGE_5_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK22_AA_TX_PAGE_5_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK23 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK23_AA_TX_PAGE_6_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK23_AA_TX_PAGE_6_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK24 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK24_AA_TX_PAGE_6_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK24_AA_TX_PAGE_6_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK25 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK25_AA_TX_PAGE_6_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK25_AA_TX_PAGE_6_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK26 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK26_AA_TX_PAGE_7_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK26_AA_TX_PAGE_7_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK27 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK27_AA_TX_PAGE_7_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK27_AA_TX_PAGE_7_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK28 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK28_AA_TX_PAGE_7_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK28_AA_TX_PAGE_7_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK30 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK30_AA_RX_PAGE_0_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK30_AA_RX_PAGE_0_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK31 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK31_AA_RX_PAGE_0_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK31_AA_RX_PAGE_0_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK32 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK32_AA_RX_PAGE_0_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK32_AA_RX_PAGE_0_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK33 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK33_AA_RX_PAGE_1_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK33_AA_RX_PAGE_1_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK34 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK34_AA_RX_PAGE_1_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK34_AA_RX_PAGE_1_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK35 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK35_AA_RX_PAGE_1_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK35_AA_RX_PAGE_1_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK36 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK36_AA_RX_PAGE_2_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK36_AA_RX_PAGE_2_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK37 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK37_AA_RX_PAGE_2_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK37_AA_RX_PAGE_2_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK38 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK38_AA_RX_PAGE_2_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK38_AA_RX_PAGE_2_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK39 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK39_AA_RX_PAGE_3_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK39_AA_RX_PAGE_3_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK3A */
+#define NIC0_SERDES0_LANE1_REGISTER_AK3A_AA_RX_PAGE_3_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK3A_AA_RX_PAGE_3_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK3B */
+#define NIC0_SERDES0_LANE1_REGISTER_AK3B_AA_RX_PAGE_3_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK3B_AA_RX_PAGE_3_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK3C */
+#define NIC0_SERDES0_LANE1_REGISTER_AK3C_AA_RX_PAGE_4_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK3C_AA_RX_PAGE_4_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK3D */
+#define NIC0_SERDES0_LANE1_REGISTER_AK3D_AA_RX_PAGE_4_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK3D_AA_RX_PAGE_4_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK3E */
+#define NIC0_SERDES0_LANE1_REGISTER_AK3E_AA_RX_PAGE_4_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK3E_AA_RX_PAGE_4_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK3F */
+#define NIC0_SERDES0_LANE1_REGISTER_AK3F_AA_RX_PAGE_5_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK3F_AA_RX_PAGE_5_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK40 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK40_AA_RX_PAGE_5_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK40_AA_RX_PAGE_5_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK41 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK41_AA_RX_PAGE_5_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK41_AA_RX_PAGE_5_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK42 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK42_AA_RX_PAGE_6_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK42_AA_RX_PAGE_6_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK43 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK43_AA_RX_PAGE_6_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK43_AA_RX_PAGE_6_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK44 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK44_AA_RX_PAGE_6_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK44_AA_RX_PAGE_6_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK45 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK45_AA_RX_PAGE_7_S_BIT_15_0_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK45_AA_RX_PAGE_7_S_BIT_15_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK46 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK46_AA_RX_PAGE_7_S_BIT_31_16_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK46_AA_RX_PAGE_7_S_BIT_31_16_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AK47 */
+#define NIC0_SERDES0_LANE1_REGISTER_AK47_AA_RX_PAGE_7_S_BIT_47_32_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AK47_AA_RX_PAGE_7_S_BIT_47_32_MASK 0xFFFF
+
+/* NIC0_SERDES0_LANE1_REGISTER_AJ40 */
+#define NIC0_SERDES0_LANE1_REGISTER_AJ40_RSVD_AJ40_08_00_SHIFT 0
+#define NIC0_SERDES0_LANE1_REGISTER_AJ40_RSVD_AJ40_08_00_MASK 0x1FF
+#define NIC0_SERDES0_LANE1_REGISTER_AJ40_RSVD_AJ40_13_09_SHIFT 9
+#define NIC0_SERDES0_LANE1_REGISTER_AJ40_RSVD_AJ40_13_09_MASK 0x3E00
+#define NIC0_SERDES0_LANE1_REGISTER_AJ40_ANLT_REF_CLK_SEL_SHIFT 14
+#define NIC0_SERDES0_LANE1_REGISTER_AJ40_ANLT_REF_CLK_SEL_MASK 0x4000
+#define NIC0_SERDES0_LANE1_REGISTER_AJ40_ANLT_LANE_SWAPPING_EN_SHIFT 15
+#define NIC0_SERDES0_LANE1_REGISTER_AJ40_ANLT_LANE_SWAPPING_EN_MASK 0x8000
+
+/* NIC0_SERDES0_REGISTER_9700 */
+#define NIC0_SERDES0_REGISTER_9700_RSVD_9700_12_00_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9700_RSVD_9700_12_00_MASK 0x1FFF
+#define NIC0_SERDES0_REGISTER_9700_SRAM_ECC_TEST_SHIFT 13
+#define NIC0_SERDES0_REGISTER_9700_SRAM_ECC_TEST_MASK 0x6000
+#define NIC0_SERDES0_REGISTER_9700_SRAM_ECC_EN_SHIFT 15
+#define NIC0_SERDES0_REGISTER_9700_SRAM_ECC_EN_MASK 0x8000
+
+/* NIC0_SERDES0_REGISTER_9701 */
+#define NIC0_SERDES0_REGISTER_9701_RSVD_9701_13_00_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9701_RSVD_9701_13_00_MASK 0x3FFF
+#define NIC0_SERDES0_REGISTER_9701_SRAM_ECC_ERR_SHIFT 14
+#define NIC0_SERDES0_REGISTER_9701_SRAM_ECC_ERR_MASK 0x4000
+#define NIC0_SERDES0_REGISTER_9701_SRAM_ECC_CORR_SHIFT 15
+#define NIC0_SERDES0_REGISTER_9701_SRAM_ECC_CORR_MASK 0x8000
+
+/* NIC0_SERDES0_REGISTER_9803 */
+#define NIC0_SERDES0_REGISTER_9803_RSVD_9803_10_00_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9803_RSVD_9803_10_00_MASK 0x7FF
+#define NIC0_SERDES0_REGISTER_9803_LOOPBACK_1_EN_SHIFT 11
+#define NIC0_SERDES0_REGISTER_9803_LOOPBACK_1_EN_MASK 0x800
+#define NIC0_SERDES0_REGISTER_9803_RSVD_9803_12_SHIFT 12
+#define NIC0_SERDES0_REGISTER_9803_RSVD_9803_12_MASK 0x1000
+#define NIC0_SERDES0_REGISTER_9803_TX_IDLE_OWEN_SHIFT 13
+#define NIC0_SERDES0_REGISTER_9803_TX_IDLE_OWEN_MASK 0x2000
+#define NIC0_SERDES0_REGISTER_9803_TX_IDLE_OW_SHIFT 14
+#define NIC0_SERDES0_REGISTER_9803_TX_IDLE_OW_MASK 0x4000
+#define NIC0_SERDES0_REGISTER_9803_LOOPBACK_0_EN_SHIFT 15
+#define NIC0_SERDES0_REGISTER_9803_LOOPBACK_0_EN_MASK 0x8000
+
+/* NIC0_SERDES0_REGISTER_9804 */
+#define NIC0_SERDES0_REGISTER_9804_RSVD_9804_11_00_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9804_RSVD_9804_11_00_MASK 0xFFF
+#define NIC0_SERDES0_REGISTER_9804_GPO1_SHIFT 12
+#define NIC0_SERDES0_REGISTER_9804_GPO1_MASK 0x1000
+#define NIC0_SERDES0_REGISTER_9804_GPO0_SHIFT 13
+#define NIC0_SERDES0_REGISTER_9804_GPO0_MASK 0x2000
+#define NIC0_SERDES0_REGISTER_9804_RSVD_9804_15_14_SHIFT 14
+#define NIC0_SERDES0_REGISTER_9804_RSVD_9804_15_14_MASK 0xC000
+
+/* NIC0_SERDES0_REGISTER_9805 */
+#define NIC0_SERDES0_REGISTER_9805_RSVD_9805_00_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9805_RSVD_9805_00_MASK 0x1
+#define NIC0_SERDES0_REGISTER_9805_GPI1_SHIFT 1
+#define NIC0_SERDES0_REGISTER_9805_GPI1_MASK 0x2
+#define NIC0_SERDES0_REGISTER_9805_GPI0_SHIFT 2
+#define NIC0_SERDES0_REGISTER_9805_GPI0_MASK 0x4
+#define NIC0_SERDES0_REGISTER_9805_RSVD_9805_15_03_SHIFT 3
+#define NIC0_SERDES0_REGISTER_9805_RSVD_9805_15_03_MASK 0xFFF8
+
+/* NIC0_SERDES0_REGISTER_980D */
+#define NIC0_SERDES0_REGISTER_980D_DOMAIN_RESET_SHIFT 0
+#define NIC0_SERDES0_REGISTER_980D_DOMAIN_RESET_MASK 0xFFF
+#define NIC0_SERDES0_REGISTER_980D_RSVD_980D_15_12_SHIFT 12
+#define NIC0_SERDES0_REGISTER_980D_RSVD_980D_15_12_MASK 0xF000
+
+/* NIC0_SERDES0_REGISTER_980E */
+#define NIC0_SERDES0_REGISTER_980E_FIRMWARE_LOAD_MAGIC_WORD_ADDR_SHIFT 0
+#define NIC0_SERDES0_REGISTER_980E_FIRMWARE_LOAD_MAGIC_WORD_ADDR_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_980F */
+#define NIC0_SERDES0_REGISTER_980F_FIRMWARE_CTLE_MODE_ADDR_SHIFT 0
+#define NIC0_SERDES0_REGISTER_980F_FIRMWARE_CTLE_MODE_ADDR_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9810 */
+#define NIC0_SERDES0_REGISTER_9810_FIRMWARE_WATCHDOG_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9810_FIRMWARE_WATCHDOG_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9811 */
+#define NIC0_SERDES0_REGISTER_9811_FIRMWARE_CTLE_DONE_ADDR_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9811_FIRMWARE_CTLE_DONE_ADDR_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9812 */
+#define NIC0_SERDES0_REGISTER_9812_SPI_DATA_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9812_SPI_DATA_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9814 */
+#define NIC0_SERDES0_REGISTER_9814_FIRMWARE_EXEC_CTRL_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9814_FIRMWARE_EXEC_CTRL_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9815 */
+#define NIC0_SERDES0_REGISTER_9815_CMD_PARAM_OR_STATUSA_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9815_CMD_PARAM_OR_STATUSA_MASK 0xFF
+#define NIC0_SERDES0_REGISTER_9815_RESPONSE_SHIFT 8
+#define NIC0_SERDES0_REGISTER_9815_RESPONSE_MASK 0xF00
+#define NIC0_SERDES0_REGISTER_9815_COMMAND_SHIFT 12
+#define NIC0_SERDES0_REGISTER_9815_COMMAND_MASK 0xF000
+
+/* NIC0_SERDES0_REGISTER_9816 */
+#define NIC0_SERDES0_REGISTER_9816_CMD_PARAM_OR_STATUSB_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9816_CMD_PARAM_OR_STATUSB_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9817 */
+#define NIC0_SERDES0_REGISTER_9817_RSVD_9817_11_00_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9817_RSVD_9817_11_00_MASK 0xFFF
+#define NIC0_SERDES0_REGISTER_9817_SRAM_TEST_1_EN_SHIFT 12
+#define NIC0_SERDES0_REGISTER_9817_SRAM_TEST_1_EN_MASK 0x1000
+#define NIC0_SERDES0_REGISTER_9817_SRAM_BIST_1_EN_SHIFT 13
+#define NIC0_SERDES0_REGISTER_9817_SRAM_BIST_1_EN_MASK 0x2000
+#define NIC0_SERDES0_REGISTER_9817_SRAM_TEST_0_EN_SHIFT 14
+#define NIC0_SERDES0_REGISTER_9817_SRAM_TEST_0_EN_MASK 0x4000
+#define NIC0_SERDES0_REGISTER_9817_SRAM_BIST_0_EN_SHIFT 15
+#define NIC0_SERDES0_REGISTER_9817_SRAM_BIST_0_EN_MASK 0x8000
+
+/* NIC0_SERDES0_REGISTER_9818 */
+#define NIC0_SERDES0_REGISTER_9818_RSVD_9818_09_00_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9818_RSVD_9818_09_00_MASK 0x3FF
+#define NIC0_SERDES0_REGISTER_9818_SELF_REPAIR_STS_1_SHIFT 10
+#define NIC0_SERDES0_REGISTER_9818_SELF_REPAIR_STS_1_MASK 0x400
+#define NIC0_SERDES0_REGISTER_9818_SELF_REPAIR_STS_0_SHIFT 11
+#define NIC0_SERDES0_REGISTER_9818_SELF_REPAIR_STS_0_MASK 0x800
+#define NIC0_SERDES0_REGISTER_9818_SRAM_BIST_1_STATUS_SHIFT 12
+#define NIC0_SERDES0_REGISTER_9818_SRAM_BIST_1_STATUS_MASK 0x1000
+#define NIC0_SERDES0_REGISTER_9818_SRAM_BIST_1_DONE_SHIFT 13
+#define NIC0_SERDES0_REGISTER_9818_SRAM_BIST_1_DONE_MASK 0x2000
+#define NIC0_SERDES0_REGISTER_9818_SRAM_BIST_0_STATUS_SHIFT 14
+#define NIC0_SERDES0_REGISTER_9818_SRAM_BIST_0_STATUS_MASK 0x4000
+#define NIC0_SERDES0_REGISTER_9818_SRAM_BIST_0_DONE_SHIFT 15
+#define NIC0_SERDES0_REGISTER_9818_SRAM_BIST_0_DONE_MASK 0x8000
+
+/* NIC0_SERDES0_REGISTER_9819 */
+#define NIC0_SERDES0_REGISTER_9819_RSVD_9819_11_00_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9819_RSVD_9819_11_00_MASK 0xFFF
+#define NIC0_SERDES0_REGISTER_9819_ROM_TEST_1_EN_SHIFT 12
+#define NIC0_SERDES0_REGISTER_9819_ROM_TEST_1_EN_MASK 0x1000
+#define NIC0_SERDES0_REGISTER_9819_ROM_BIST_1_EN_SHIFT 13
+#define NIC0_SERDES0_REGISTER_9819_ROM_BIST_1_EN_MASK 0x2000
+#define NIC0_SERDES0_REGISTER_9819_ROM_TEST_0_EN_SHIFT 14
+#define NIC0_SERDES0_REGISTER_9819_ROM_TEST_0_EN_MASK 0x4000
+#define NIC0_SERDES0_REGISTER_9819_ROM_BIST_0_EN_SHIFT 15
+#define NIC0_SERDES0_REGISTER_9819_ROM_BIST_0_EN_MASK 0x8000
+
+/* NIC0_SERDES0_REGISTER_981A */
+#define NIC0_SERDES0_REGISTER_981A_RSVD_981A_13_00_SHIFT 0
+#define NIC0_SERDES0_REGISTER_981A_RSVD_981A_13_00_MASK 0x3FFF
+#define NIC0_SERDES0_REGISTER_981A_ROM_TEST_1_DONE_SHIFT 14
+#define NIC0_SERDES0_REGISTER_981A_ROM_TEST_1_DONE_MASK 0x4000
+#define NIC0_SERDES0_REGISTER_981A_ROM_TEST_0_DONE_SHIFT 15
+#define NIC0_SERDES0_REGISTER_981A_ROM_TEST_0_DONE_MASK 0x8000
+
+/* NIC0_SERDES0_REGISTER_981B */
+#define NIC0_SERDES0_REGISTER_981B_ROM_TEST_RESULT_LOW_SHIFT 0
+#define NIC0_SERDES0_REGISTER_981B_ROM_TEST_RESULT_LOW_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_981C */
+#define NIC0_SERDES0_REGISTER_981C_ROM_TEST_RESULT_HIGH_SHIFT 0
+#define NIC0_SERDES0_REGISTER_981C_ROM_TEST_RESULT_HIGH_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_981F */
+#define NIC0_SERDES0_REGISTER_981F_RSVD_981F_11_00_SHIFT 0
+#define NIC0_SERDES0_REGISTER_981F_RSVD_981F_11_00_MASK 0xFFF
+#define NIC0_SERDES0_REGISTER_981F_DRO_CNTR_TARGET_SHIFT 12
+#define NIC0_SERDES0_REGISTER_981F_DRO_CNTR_TARGET_MASK 0x3000
+#define NIC0_SERDES0_REGISTER_981F_DRO_CNTR_EN_SHIFT 14
+#define NIC0_SERDES0_REGISTER_981F_DRO_CNTR_EN_MASK 0x4000
+#define NIC0_SERDES0_REGISTER_981F_DRO_OSC_EN_SHIFT 15
+#define NIC0_SERDES0_REGISTER_981F_DRO_OSC_EN_MASK 0x8000
+
+/* NIC0_SERDES0_REGISTER_9820 */
+#define NIC0_SERDES0_REGISTER_9820_DRO_VAL_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9820_DRO_VAL_MASK 0x7FFF
+#define NIC0_SERDES0_REGISTER_9820_DRO_DONE_SHIFT 15
+#define NIC0_SERDES0_REGISTER_9820_DRO_DONE_MASK 0x8000
+
+/* NIC0_SERDES0_REGISTER_9822 */
+#define NIC0_SERDES0_REGISTER_9822_PLL_0_LOCK_TARGET_HIGH_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9822_PLL_0_LOCK_TARGET_HIGH_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9823 */
+#define NIC0_SERDES0_REGISTER_9823_PLL_0_LOCK_TARGET_LOW_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9823_PLL_0_LOCK_TARGET_LOW_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9824 */
+#define NIC0_SERDES0_REGISTER_9824_PLL_0_LOCK_TARGET_MARGIN_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9824_PLL_0_LOCK_TARGET_MARGIN_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9825 */
+#define NIC0_SERDES0_REGISTER_9825_PLL_LOCK_SRC_SEL_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9825_PLL_LOCK_SRC_SEL_MASK 0x3
+#define NIC0_SERDES0_REGISTER_9825_RSVD_9825_06_02_SHIFT 2
+#define NIC0_SERDES0_REGISTER_9825_RSVD_9825_06_02_MASK 0x7C
+#define NIC0_SERDES0_REGISTER_9825_AUTO_TRI_0_SHIFT 7
+#define NIC0_SERDES0_REGISTER_9825_AUTO_TRI_0_MASK 0x80
+#define NIC0_SERDES0_REGISTER_9825_PLL_0_LOCK_EN_SHIFT 8
+#define NIC0_SERDES0_REGISTER_9825_PLL_0_LOCK_EN_MASK 0x100
+#define NIC0_SERDES0_REGISTER_9825_SRAM_ECC_CORR_OW_SHIFT 9
+#define NIC0_SERDES0_REGISTER_9825_SRAM_ECC_CORR_OW_MASK 0x200
+#define NIC0_SERDES0_REGISTER_9825_SRAM_ECC_CORR_PIN_OWEN_SHIFT 10
+#define NIC0_SERDES0_REGISTER_9825_SRAM_ECC_CORR_PIN_OWEN_MASK 0x400
+#define NIC0_SERDES0_REGISTER_9825_SRAM_ECC_UNCORR_OW_SHIFT 11
+#define NIC0_SERDES0_REGISTER_9825_SRAM_ECC_UNCORR_OW_MASK 0x800
+#define NIC0_SERDES0_REGISTER_9825_SRAM_ECC_UNCORR_PIN_OWEN_SHIFT 12
+#define NIC0_SERDES0_REGISTER_9825_SRAM_ECC_UNCORR_PIN_OWEN_MASK 0x1000
+#define NIC0_SERDES0_REGISTER_9825_PLL_0_LOCK_OW_SHIFT 13
+#define NIC0_SERDES0_REGISTER_9825_PLL_0_LOCK_OW_MASK 0x2000
+#define NIC0_SERDES0_REGISTER_9825_PLL_0_LOCK_OWEN_SHIFT 14
+#define NIC0_SERDES0_REGISTER_9825_PLL_0_LOCK_OWEN_MASK 0x4000
+#define NIC0_SERDES0_REGISTER_9825_PLL_0_LOCK_32T_CLK_SEL_SHIFT 15
+#define NIC0_SERDES0_REGISTER_9825_PLL_0_LOCK_32T_CLK_SEL_MASK 0x8000
+
+/* NIC0_SERDES0_REGISTER_9826 */
+#define NIC0_SERDES0_REGISTER_9826_PLL_0_LOCK_REFCLK_INIT_COUNT_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9826_PLL_0_LOCK_REFCLK_INIT_COUNT_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9827 */
+#define NIC0_SERDES0_REGISTER_9827_PLL_0_LOCK_32T_COUNT_HIGH_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9827_PLL_0_LOCK_32T_COUNT_HIGH_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9828 */
+#define NIC0_SERDES0_REGISTER_9828_PLL_0_LOCK_32T_COUNT_LOW_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9828_PLL_0_LOCK_32T_COUNT_LOW_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9829 */
+#define NIC0_SERDES0_REGISTER_9829_RSVD_9829_13_00_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9829_RSVD_9829_13_00_MASK 0x3FFF
+#define NIC0_SERDES0_REGISTER_9829_PLL_0_LOCK_DONE_SHIFT 14
+#define NIC0_SERDES0_REGISTER_9829_PLL_0_LOCK_DONE_MASK 0x4000
+#define NIC0_SERDES0_REGISTER_9829_PLL_0_LOCK_STATUS_SHIFT 15
+#define NIC0_SERDES0_REGISTER_9829_PLL_0_LOCK_STATUS_MASK 0x8000
+
+/* NIC0_SERDES0_REGISTER_982B */
+#define NIC0_SERDES0_REGISTER_982B_PLL_1_LOCK_TARGET_HIGH_SHIFT 0
+#define NIC0_SERDES0_REGISTER_982B_PLL_1_LOCK_TARGET_HIGH_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_982C */
+#define NIC0_SERDES0_REGISTER_982C_PLL_1_LOCK_TARGET_LOW_SHIFT 0
+#define NIC0_SERDES0_REGISTER_982C_PLL_1_LOCK_TARGET_LOW_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_982D */
+#define NIC0_SERDES0_REGISTER_982D_PLL_1_LOCK_TARGET_MARGIN_SHIFT 0
+#define NIC0_SERDES0_REGISTER_982D_PLL_1_LOCK_TARGET_MARGIN_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_982E */
+#define NIC0_SERDES0_REGISTER_982E_RSVD_982E_06_00_SHIFT 0
+#define NIC0_SERDES0_REGISTER_982E_RSVD_982E_06_00_MASK 0x7F
+#define NIC0_SERDES0_REGISTER_982E_AUTO_TRI_1_SHIFT 7
+#define NIC0_SERDES0_REGISTER_982E_AUTO_TRI_1_MASK 0x80
+#define NIC0_SERDES0_REGISTER_982E_PLL_1_LOCK_EN_SHIFT 8
+#define NIC0_SERDES0_REGISTER_982E_PLL_1_LOCK_EN_MASK 0x100
+#define NIC0_SERDES0_REGISTER_982E_RSVD_982E_12_09_SHIFT 9
+#define NIC0_SERDES0_REGISTER_982E_RSVD_982E_12_09_MASK 0x1E00
+#define NIC0_SERDES0_REGISTER_982E_PLL_1_LOCK_OW_SHIFT 13
+#define NIC0_SERDES0_REGISTER_982E_PLL_1_LOCK_OW_MASK 0x2000
+#define NIC0_SERDES0_REGISTER_982E_PLL_1_LOCK_OWEN_SHIFT 14
+#define NIC0_SERDES0_REGISTER_982E_PLL_1_LOCK_OWEN_MASK 0x4000
+#define NIC0_SERDES0_REGISTER_982E_PLL_1_LOCK_32T_CLK_SEL_SHIFT 15
+#define NIC0_SERDES0_REGISTER_982E_PLL_1_LOCK_32T_CLK_SEL_MASK 0x8000
+
+/* NIC0_SERDES0_REGISTER_982F */
+#define NIC0_SERDES0_REGISTER_982F_PLL_1_LOCK_REFCLK_INIT_COUNT_SHIFT 0
+#define NIC0_SERDES0_REGISTER_982F_PLL_1_LOCK_REFCLK_INIT_COUNT_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9832 */
+#define NIC0_SERDES0_REGISTER_9832_RSVD_9832_13_00_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9832_RSVD_9832_13_00_MASK 0x3FFF
+#define NIC0_SERDES0_REGISTER_9832_PLL_1_LOCK_DONE_SHIFT 14
+#define NIC0_SERDES0_REGISTER_9832_PLL_1_LOCK_DONE_MASK 0x4000
+#define NIC0_SERDES0_REGISTER_9832_PLL_1_LOCK_STATUS_SHIFT 15
+#define NIC0_SERDES0_REGISTER_9832_PLL_1_LOCK_STATUS_MASK 0x8000
+
+/* NIC0_SERDES0_REGISTER_9F00 */
+#define NIC0_SERDES0_REGISTER_9F00_FIRMWARE_DATA_0_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F00_FIRMWARE_DATA_0_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F01 */
+#define NIC0_SERDES0_REGISTER_9F01_FIRMWARE_DATA_1_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F01_FIRMWARE_DATA_1_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F02 */
+#define NIC0_SERDES0_REGISTER_9F02_FIRMWARE_DATA_2_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F02_FIRMWARE_DATA_2_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F03 */
+#define NIC0_SERDES0_REGISTER_9F03_FIRMWARE_DATA_3_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F03_FIRMWARE_DATA_3_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F04 */
+#define NIC0_SERDES0_REGISTER_9F04_FIRMWARE_DATA_4_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F04_FIRMWARE_DATA_4_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F05 */
+#define NIC0_SERDES0_REGISTER_9F05_FIRMWARE_DATA_5_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F05_FIRMWARE_DATA_5_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F06 */
+#define NIC0_SERDES0_REGISTER_9F06_FIRMWARE_DATA_6_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F06_FIRMWARE_DATA_6_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F07 */
+#define NIC0_SERDES0_REGISTER_9F07_FIRMWARE_DATA_7_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F07_FIRMWARE_DATA_7_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F08 */
+#define NIC0_SERDES0_REGISTER_9F08_FIRMWARE_DATA_8_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F08_FIRMWARE_DATA_8_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F09 */
+#define NIC0_SERDES0_REGISTER_9F09_FIRMWARE_DATA_9_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F09_FIRMWARE_DATA_9_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F0A */
+#define NIC0_SERDES0_REGISTER_9F0A_FIRMWARE_DATA_A_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F0A_FIRMWARE_DATA_A_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F0B */
+#define NIC0_SERDES0_REGISTER_9F0B_FIRMWARE_DATA_B_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F0B_FIRMWARE_DATA_B_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F0C */
+#define NIC0_SERDES0_REGISTER_9F0C_FIRMWARE_DATA_C_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F0C_FIRMWARE_DATA_C_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F0D */
+#define NIC0_SERDES0_REGISTER_9F0D_FIRMWARE_DATA_D_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F0D_FIRMWARE_DATA_D_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F0E */
+#define NIC0_SERDES0_REGISTER_9F0E_FIRMWARE_DATA_E_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F0E_FIRMWARE_DATA_E_MASK 0xFFFF
+
+/* NIC0_SERDES0_REGISTER_9F0F */
+#define NIC0_SERDES0_REGISTER_9F0F_FIRMWARE_DATA_F_SHIFT 0
+#define NIC0_SERDES0_REGISTER_9F0F_FIRMWARE_DATA_F_MASK 0xFFFF
+
+#endif /* ASIC_REG_NIC0_SERDES0_MASKS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes0_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes0_regs.h
new file mode 100644
index 000000000000..746b3c709c36
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes0_regs.h
@@ -0,0 +1,1679 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_SERDES0_REGS_H_
+#define ASIC_REG_NIC0_SERDES0_REGS_H_
+
+/*****************************************
+ * NIC0_SERDES0
+ * (Prototype: NIC_SERDES)
+ *****************************************
+ */
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P00 0x5458000
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P01 0x5458004
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P02 0x5458008
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P03 0x545800C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P04 0x5458010
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P05 0x5458014
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P06 0x5458018
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P07 0x545801C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P08 0x5458020
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P09 0x5458024
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P0A 0x5458028
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P0B 0x545802C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P0C 0x5458030
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P0D 0x5458034
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P0E 0x5458038
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P0F 0x545803C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P11 0x5458044
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P12 0x5458048
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P13 0x545804C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P15 0x5458054
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P16 0x5458058
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P1F 0x545807C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P20 0x5458080
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P21 0x5458084
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P23 0x545808C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P24 0x5458090
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P28 0x54580A0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P2D 0x54580B4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P2E 0x54580B8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P2F 0x54580BC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P32 0x54580C8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P33 0x54580CC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P36 0x54580D8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P37 0x54580DC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P38 0x54580E0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P40 0x5458100
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P41 0x5458104
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P42 0x5458108
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P43 0x545810C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P44 0x5458110
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P45 0x5458114
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P46 0x5458118
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P47 0x545811C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P48 0x5458120
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P49 0x5458124
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P4A 0x5458128
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P4B 0x545812C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P4C 0x5458130
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P4E 0x5458138
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P4F 0x545813C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P50 0x5458140
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P51 0x5458144
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P6A 0x54581A8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P6C 0x54581B0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P6D 0x54581B4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P6E 0x54581B8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P73 0x54581CC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P74 0x54581D0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P79 0x54581E4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P80 0x5458200
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P81 0x5458204
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P82 0x5458208
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P83 0x545820C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P8F 0x545823C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P94 0x5458250
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P95 0x5458254
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P96 0x5458258
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P97 0x545825C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P98 0x5458260
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P99 0x5458264
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P9A 0x5458268
+
+#define NIC0_SERDES0_LANE0_REGISTER_0P9B 0x545826C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PA0 0x5458280
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PA1 0x5458284
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PA2 0x5458288
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PA3 0x545828C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PA4 0x5458290
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PA5 0x5458294
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PA6 0x5458298
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PA7 0x545829C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PA8 0x54582A0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PA9 0x54582A4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PAA 0x54582A8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PAB 0x54582AC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PAC 0x54582B0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PAD 0x54582B4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PAE 0x54582B8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PAF 0x54582BC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PB0 0x54582C0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PB1 0x54582C4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PB2 0x54582C8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PB3 0x54582CC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PC1 0x5458304
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PC3 0x545830C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PC4 0x5458310
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PC9 0x5458324
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PCA 0x5458328
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PCC 0x5458330
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PCD 0x5458334
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PCF 0x545833C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PD8 0x5458360
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PD9 0x5458364
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PE5 0x5458394
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PE6 0x5458398
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PE7 0x545839C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PE9 0x54583A4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PEA 0x54583A8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PEB 0x54583AC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PEC 0x54583B0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PED 0x54583B4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PEE 0x54583B8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PEF 0x54583BC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PF0 0x54583C0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PF1 0x54583C4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PF2 0x54583C8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PF3 0x54583CC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PF4 0x54583D0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PF5 0x54583D4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PF6 0x54583D8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PF7 0x54583DC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PF8 0x54583E0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PF9 0x54583E4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PFA 0x54583E8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PFB 0x54583EC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PFC 0x54583F0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PFD 0x54583F4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PFE 0x54583F8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0PFF 0x54583FC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N00 0x5458400
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N01 0x5458404
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N02 0x5458408
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N03 0x545840C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N04 0x5458410
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N05 0x5458414
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N06 0x5458418
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N07 0x545841C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N08 0x5458420
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N09 0x5458424
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N0B 0x545842C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N0C 0x5458430
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N0D 0x5458434
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N27 0x545849C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N28 0x54584A0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N29 0x54584A4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N2A 0x54584A8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N2B 0x54584AC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N2C 0x54584B0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N2E 0x54584B8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N3B 0x54584EC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N4D 0x5458534
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N4E 0x5458538
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N4F 0x545853C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N50 0x5458540
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N5D 0x5458574
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N5E 0x5458578
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N60 0x5458580
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N61 0x5458584
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N62 0x5458588
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N63 0x545858C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N64 0x5458590
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N65 0x5458594
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N66 0x5458598
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N67 0x545859C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N6E 0x54585B8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N6F 0x54585BC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N71 0x54585C4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N72 0x54585C8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N73 0x54585CC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N75 0x54585D4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N76 0x54585D8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N77 0x54585DC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N78 0x54585E0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N79 0x54585E4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N7A 0x54585E8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N7D 0x54585F4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N7E 0x54585F8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N7F 0x54585FC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N80 0x5458600
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N81 0x5458604
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N82 0x5458608
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N83 0x545860C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N84 0x5458610
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N85 0x5458614
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N86 0x5458618
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N87 0x545861C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N88 0x5458620
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N8C 0x5458630
+
+#define NIC0_SERDES0_LANE0_REGISTER_0N8F 0x545863C
+
+#define NIC0_SERDES0_LANE0_REGISTER_0NF2 0x54587C8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0NF3 0x54587CC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0NF6 0x54587D8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0NF7 0x54587DC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0NF8 0x54587E0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0NF9 0x54587E4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0NFA 0x54587E8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0NFB 0x54587EC
+
+#define NIC0_SERDES0_LANE0_REGISTER_0NFC 0x54587F0
+
+#define NIC0_SERDES0_LANE0_REGISTER_0NFD 0x54587F4
+
+#define NIC0_SERDES0_LANE0_REGISTER_0NFE 0x54587F8
+
+#define NIC0_SERDES0_LANE0_REGISTER_0NFF 0x54587FC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P00 0x5458800
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P01 0x5458804
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P02 0x5458808
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P03 0x545880C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P04 0x5458810
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P05 0x5458814
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P06 0x5458818
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P07 0x545881C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P08 0x5458820
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P09 0x5458824
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P0A 0x5458828
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P0B 0x545882C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P0C 0x5458830
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P0D 0x5458834
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P0E 0x5458838
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P0F 0x545883C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P11 0x5458844
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P12 0x5458848
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P13 0x545884C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P15 0x5458854
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P16 0x5458858
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P1F 0x545887C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P20 0x5458880
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P21 0x5458884
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P23 0x545888C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P24 0x5458890
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P28 0x54588A0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P2D 0x54588B4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P2E 0x54588B8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P2F 0x54588BC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P32 0x54588C8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P33 0x54588CC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P36 0x54588D8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P37 0x54588DC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P38 0x54588E0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P40 0x5458900
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P41 0x5458904
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P42 0x5458908
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P43 0x545890C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P44 0x5458910
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P45 0x5458914
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P46 0x5458918
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P47 0x545891C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P48 0x5458920
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P49 0x5458924
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P4A 0x5458928
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P4B 0x545892C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P4C 0x5458930
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P4E 0x5458938
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P4F 0x545893C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P50 0x5458940
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P51 0x5458944
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P6A 0x54589A8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P6C 0x54589B0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P6D 0x54589B4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P6E 0x54589B8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P73 0x54589CC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P74 0x54589D0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P79 0x54589E4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P80 0x5458A00
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P81 0x5458A04
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P82 0x5458A08
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P83 0x5458A0C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P8F 0x5458A3C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P94 0x5458A50
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P95 0x5458A54
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P96 0x5458A58
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P97 0x5458A5C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P98 0x5458A60
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P99 0x5458A64
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P9A 0x5458A68
+
+#define NIC0_SERDES0_LANE1_REGISTER_0P9B 0x5458A6C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PA0 0x5458A80
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PA1 0x5458A84
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PA2 0x5458A88
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PA3 0x5458A8C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PA4 0x5458A90
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PA5 0x5458A94
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PA6 0x5458A98
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PA7 0x5458A9C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PA8 0x5458AA0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PA9 0x5458AA4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PAA 0x5458AA8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PAB 0x5458AAC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PAC 0x5458AB0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PAD 0x5458AB4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PAE 0x5458AB8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PAF 0x5458ABC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PB0 0x5458AC0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PB1 0x5458AC4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PB2 0x5458AC8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PB3 0x5458ACC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PC1 0x5458B04
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PC3 0x5458B0C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PC4 0x5458B10
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PC9 0x5458B24
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PCA 0x5458B28
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PCC 0x5458B30
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PCD 0x5458B34
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PCF 0x5458B3C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PD8 0x5458B60
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PD9 0x5458B64
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PE5 0x5458B94
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PE6 0x5458B98
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PE7 0x5458B9C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PE9 0x5458BA4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PEA 0x5458BA8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PEB 0x5458BAC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PEC 0x5458BB0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PED 0x5458BB4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PEE 0x5458BB8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PEF 0x5458BBC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PF0 0x5458BC0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PF1 0x5458BC4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PF2 0x5458BC8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PF3 0x5458BCC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PF4 0x5458BD0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PF5 0x5458BD4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PF6 0x5458BD8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PF7 0x5458BDC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PF8 0x5458BE0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PF9 0x5458BE4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PFA 0x5458BE8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PFB 0x5458BEC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PFC 0x5458BF0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PFD 0x5458BF4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PFE 0x5458BF8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0PFF 0x5458BFC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N00 0x5458C00
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N01 0x5458C04
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N02 0x5458C08
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N03 0x5458C0C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N04 0x5458C10
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N05 0x5458C14
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N06 0x5458C18
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N07 0x5458C1C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N08 0x5458C20
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N09 0x5458C24
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N0B 0x5458C2C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N0C 0x5458C30
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N0D 0x5458C34
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N27 0x5458C9C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N28 0x5458CA0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N29 0x5458CA4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N2A 0x5458CA8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N2B 0x5458CAC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N2C 0x5458CB0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N2E 0x5458CB8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N3B 0x5458CEC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N4D 0x5458D34
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N4E 0x5458D38
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N4F 0x5458D3C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N50 0x5458D40
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N5D 0x5458D74
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N5E 0x5458D78
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N60 0x5458D80
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N61 0x5458D84
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N62 0x5458D88
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N63 0x5458D8C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N64 0x5458D90
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N65 0x5458D94
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N66 0x5458D98
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N67 0x5458D9C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N6E 0x5458DB8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N6F 0x5458DBC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N71 0x5458DC4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N72 0x5458DC8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N73 0x5458DCC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N75 0x5458DD4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N76 0x5458DD8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N77 0x5458DDC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N78 0x5458DE0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N79 0x5458DE4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N7A 0x5458DE8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N7D 0x5458DF4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N7E 0x5458DF8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N7F 0x5458DFC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N80 0x5458E00
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N81 0x5458E04
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N82 0x5458E08
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N83 0x5458E0C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N84 0x5458E10
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N85 0x5458E14
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N86 0x5458E18
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N87 0x5458E1C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N88 0x5458E20
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N8C 0x5458E30
+
+#define NIC0_SERDES0_LANE1_REGISTER_0N8F 0x5458E3C
+
+#define NIC0_SERDES0_LANE1_REGISTER_0NF2 0x5458FC8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0NF3 0x5458FCC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0NF6 0x5458FD8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0NF7 0x5458FDC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0NF8 0x5458FE0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0NF9 0x5458FE4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0NFA 0x5458FE8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0NFB 0x5458FEC
+
+#define NIC0_SERDES0_LANE1_REGISTER_0NFC 0x5458FF0
+
+#define NIC0_SERDES0_LANE1_REGISTER_0NFD 0x5458FF4
+
+#define NIC0_SERDES0_LANE1_REGISTER_0NFE 0x5458FF8
+
+#define NIC0_SERDES0_LANE1_REGISTER_0NFF 0x5458FFC
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI00 0x5459000
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI01 0x5459004
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI02 0x5459008
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI03 0x545900C
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI05 0x5459014
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI06 0x5459018
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI10 0x5459040
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI11 0x5459044
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI12 0x5459048
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI13 0x545904C
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI14 0x5459050
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI15 0x5459054
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI16 0x5459058
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI17 0x545905C
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI18 0x5459060
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI19 0x5459064
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI1A 0x5459068
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI1B 0x545906C
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI30 0x54590C0
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI31 0x54590C4
+
+#define NIC0_SERDES0_LANE0_REGISTER_AI40 0x5459100
+
+#define NIC0_SERDES0_LANE0_REGISTER_AIF0 0x54593C0
+
+#define NIC0_SERDES0_LANE0_REGISTER_AIF1 0x54593C4
+
+#define NIC0_SERDES0_LANE0_REGISTER_AIF2 0x54593C8
+
+#define NIC0_SERDES0_LANE0_REGISTER_AIF3 0x54593CC
+
+#define NIC0_SERDES0_LANE0_REGISTER_AIF4 0x54593D0
+
+#define NIC0_SERDES0_LANE0_REGISTER_AIF5 0x54593D4
+
+#define NIC0_SERDES0_LANE0_REGISTER_AIF6 0x54593D8
+
+#define NIC0_SERDES0_LANE0_REGISTER_AIF7 0x54593DC
+
+#define NIC0_SERDES0_LANE0_REGISTER_AIF8 0x54593E0
+
+#define NIC0_SERDES0_LANE0_REGISTER_AIF9 0x54593E4
+
+#define NIC0_SERDES0_LANE0_REGISTER_AIFA 0x54593E8
+
+#define NIC0_SERDES0_LANE0_REGISTER_AIFB 0x54593EC
+
+#define NIC0_SERDES0_LANE0_REGISTER_AIFC 0x54593F0
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT00 0x5459400
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT04 0x5459410
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT05 0x5459414
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT06 0x5459418
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT07 0x545941C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT08 0x5459420
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT09 0x5459424
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT0A 0x5459428
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT0B 0x545942C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT0C 0x5459430
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT0D 0x5459434
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT0E 0x5459438
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT0F 0x545943C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT10 0x5459440
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT11 0x5459444
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT12 0x5459448
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT13 0x545944C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT14 0x5459450
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT15 0x5459454
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT16 0x5459458
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT17 0x545945C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT18 0x5459460
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT19 0x5459464
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT1A 0x5459468
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT1B 0x545946C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT1C 0x5459470
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT1D 0x5459474
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT1E 0x5459478
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT1F 0x545947C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT20 0x5459480
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT21 0x5459484
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT22 0x5459488
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT23 0x545948C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT24 0x5459490
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT25 0x5459494
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT26 0x5459498
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT29 0x54594A4
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT2A 0x54594A8
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT2B 0x54594AC
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT2C 0x54594B0
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT2D 0x54594B4
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT2E 0x54594B8
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT2F 0x54594BC
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT30 0x54594C0
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT31 0x54594C4
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT32 0x54594C8
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT33 0x54594CC
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT34 0x54594D0
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT35 0x54594D4
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT36 0x54594D8
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT37 0x54594DC
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT38 0x54594E0
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT39 0x54594E4
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT3A 0x54594E8
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT3B 0x54594EC
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT3C 0x54594F0
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT3D 0x54594F4
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT3E 0x54594F8
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT3F 0x54594FC
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT40 0x5459500
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT41 0x5459504
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT42 0x5459508
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT43 0x545950C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT44 0x5459510
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT45 0x5459514
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT4E 0x5459538
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT4F 0x545953C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT50 0x5459540
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT51 0x5459544
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT52 0x5459548
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT53 0x545954C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT54 0x5459550
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT55 0x5459554
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT56 0x5459558
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT57 0x545955C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT58 0x5459560
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT59 0x5459564
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT5A 0x5459568
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT5B 0x545956C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT5C 0x5459570
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT5D 0x5459574
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT5E 0x5459578
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT5F 0x545957C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT60 0x5459580
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT61 0x5459584
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT62 0x5459588
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT63 0x545958C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT64 0x5459590
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT67 0x545959C
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT68 0x54595A0
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT69 0x54595A4
+
+#define NIC0_SERDES0_LANE0_REGISTER_LT6A 0x54595A8
+
+#define NIC0_SERDES0_LANE0_REGISTER_AN01 0x5459804
+
+#define NIC0_SERDES0_LANE0_REGISTER_AN02 0x5459808
+
+#define NIC0_SERDES0_LANE0_REGISTER_AN03 0x545980C
+
+#define NIC0_SERDES0_LANE0_REGISTER_AN04 0x5459810
+
+#define NIC0_SERDES0_LANE0_REGISTER_AN05 0x5459814
+
+#define NIC0_SERDES0_LANE0_REGISTER_AN06 0x5459818
+
+#define NIC0_SERDES0_LANE0_REGISTER_AN07 0x545981C
+
+#define NIC0_SERDES0_LANE0_REGISTER_AN08 0x5459820
+
+#define NIC0_SERDES0_LANE0_REGISTER_AN09 0x5459824
+
+#define NIC0_SERDES0_LANE0_REGISTER_AN0A 0x5459828
+
+#define NIC0_SERDES0_LANE0_REGISTER_AN10 0x5459840
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK00 0x5459C00
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK02 0x5459C08
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK11 0x5459C44
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK12 0x5459C48
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK13 0x5459C4C
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK14 0x5459C50
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK15 0x5459C54
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK16 0x5459C58
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK17 0x5459C5C
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK18 0x5459C60
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK19 0x5459C64
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK1A 0x5459C68
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK1B 0x5459C6C
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK1C 0x5459C70
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK1D 0x5459C74
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK1E 0x5459C78
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK1F 0x5459C7C
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK20 0x5459C80
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK21 0x5459C84
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK22 0x5459C88
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK23 0x5459C8C
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK24 0x5459C90
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK25 0x5459C94
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK26 0x5459C98
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK27 0x5459C9C
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK28 0x5459CA0
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK30 0x5459CC0
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK31 0x5459CC4
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK32 0x5459CC8
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK33 0x5459CCC
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK34 0x5459CD0
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK35 0x5459CD4
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK36 0x5459CD8
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK37 0x5459CDC
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK38 0x5459CE0
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK39 0x5459CE4
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK3A 0x5459CE8
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK3B 0x5459CEC
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK3C 0x5459CF0
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK3D 0x5459CF4
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK3E 0x5459CF8
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK3F 0x5459CFC
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK40 0x5459D00
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK41 0x5459D04
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK42 0x5459D08
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK43 0x5459D0C
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK44 0x5459D10
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK45 0x5459D14
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK46 0x5459D18
+
+#define NIC0_SERDES0_LANE0_REGISTER_AK47 0x5459D1C
+
+#define NIC0_SERDES0_LANE0_REGISTER_AJ40 0x545A100
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI00 0x545A400
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI01 0x545A404
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI02 0x545A408
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI03 0x545A40C
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI05 0x545A414
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI06 0x545A418
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI10 0x545A440
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI11 0x545A444
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI12 0x545A448
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI13 0x545A44C
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI14 0x545A450
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI15 0x545A454
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI16 0x545A458
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI17 0x545A45C
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI18 0x545A460
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI19 0x545A464
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI1A 0x545A468
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI1B 0x545A46C
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI30 0x545A4C0
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI31 0x545A4C4
+
+#define NIC0_SERDES0_LANE1_REGISTER_AI40 0x545A500
+
+#define NIC0_SERDES0_LANE1_REGISTER_AIF0 0x545A7C0
+
+#define NIC0_SERDES0_LANE1_REGISTER_AIF1 0x545A7C4
+
+#define NIC0_SERDES0_LANE1_REGISTER_AIF2 0x545A7C8
+
+#define NIC0_SERDES0_LANE1_REGISTER_AIF3 0x545A7CC
+
+#define NIC0_SERDES0_LANE1_REGISTER_AIF4 0x545A7D0
+
+#define NIC0_SERDES0_LANE1_REGISTER_AIF5 0x545A7D4
+
+#define NIC0_SERDES0_LANE1_REGISTER_AIF6 0x545A7D8
+
+#define NIC0_SERDES0_LANE1_REGISTER_AIF7 0x545A7DC
+
+#define NIC0_SERDES0_LANE1_REGISTER_AIF8 0x545A7E0
+
+#define NIC0_SERDES0_LANE1_REGISTER_AIF9 0x545A7E4
+
+#define NIC0_SERDES0_LANE1_REGISTER_AIFA 0x545A7E8
+
+#define NIC0_SERDES0_LANE1_REGISTER_AIFB 0x545A7EC
+
+#define NIC0_SERDES0_LANE1_REGISTER_AIFC 0x545A7F0
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT00 0x545A800
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT04 0x545A810
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT05 0x545A814
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT06 0x545A818
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT07 0x545A81C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT08 0x545A820
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT09 0x545A824
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT0A 0x545A828
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT0B 0x545A82C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT0C 0x545A830
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT0D 0x545A834
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT0E 0x545A838
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT0F 0x545A83C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT10 0x545A840
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT11 0x545A844
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT12 0x545A848
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT13 0x545A84C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT14 0x545A850
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT15 0x545A854
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT16 0x545A858
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT17 0x545A85C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT18 0x545A860
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT19 0x545A864
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT1A 0x545A868
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT1B 0x545A86C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT1C 0x545A870
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT1D 0x545A874
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT1E 0x545A878
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT1F 0x545A87C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT20 0x545A880
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT21 0x545A884
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT22 0x545A888
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT23 0x545A88C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT24 0x545A890
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT25 0x545A894
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT26 0x545A898
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT29 0x545A8A4
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT2A 0x545A8A8
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT2B 0x545A8AC
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT2C 0x545A8B0
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT2D 0x545A8B4
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT2E 0x545A8B8
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT2F 0x545A8BC
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT30 0x545A8C0
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT31 0x545A8C4
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT32 0x545A8C8
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT33 0x545A8CC
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT34 0x545A8D0
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT35 0x545A8D4
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT36 0x545A8D8
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT37 0x545A8DC
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT38 0x545A8E0
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT39 0x545A8E4
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT3A 0x545A8E8
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT3B 0x545A8EC
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT3C 0x545A8F0
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT3D 0x545A8F4
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT3E 0x545A8F8
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT3F 0x545A8FC
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT40 0x545A900
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT41 0x545A904
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT42 0x545A908
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT43 0x545A90C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT44 0x545A910
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT45 0x545A914
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT4E 0x545A938
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT4F 0x545A93C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT50 0x545A940
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT51 0x545A944
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT52 0x545A948
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT53 0x545A94C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT54 0x545A950
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT55 0x545A954
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT56 0x545A958
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT57 0x545A95C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT58 0x545A960
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT59 0x545A964
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT5A 0x545A968
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT5B 0x545A96C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT5C 0x545A970
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT5D 0x545A974
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT5E 0x545A978
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT5F 0x545A97C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT60 0x545A980
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT61 0x545A984
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT62 0x545A988
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT63 0x545A98C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT64 0x545A990
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT67 0x545A99C
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT68 0x545A9A0
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT69 0x545A9A4
+
+#define NIC0_SERDES0_LANE1_REGISTER_LT6A 0x545A9A8
+
+#define NIC0_SERDES0_LANE1_REGISTER_AN01 0x545AC04
+
+#define NIC0_SERDES0_LANE1_REGISTER_AN02 0x545AC08
+
+#define NIC0_SERDES0_LANE1_REGISTER_AN03 0x545AC0C
+
+#define NIC0_SERDES0_LANE1_REGISTER_AN04 0x545AC10
+
+#define NIC0_SERDES0_LANE1_REGISTER_AN05 0x545AC14
+
+#define NIC0_SERDES0_LANE1_REGISTER_AN06 0x545AC18
+
+#define NIC0_SERDES0_LANE1_REGISTER_AN07 0x545AC1C
+
+#define NIC0_SERDES0_LANE1_REGISTER_AN08 0x545AC20
+
+#define NIC0_SERDES0_LANE1_REGISTER_AN09 0x545AC24
+
+#define NIC0_SERDES0_LANE1_REGISTER_AN0A 0x545AC28
+
+#define NIC0_SERDES0_LANE1_REGISTER_AN10 0x545AC40
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK00 0x545B000
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK02 0x545B008
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK11 0x545B044
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK12 0x545B048
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK13 0x545B04C
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK14 0x545B050
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK15 0x545B054
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK16 0x545B058
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK17 0x545B05C
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK18 0x545B060
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK19 0x545B064
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK1A 0x545B068
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK1B 0x545B06C
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK1C 0x545B070
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK1D 0x545B074
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK1E 0x545B078
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK1F 0x545B07C
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK20 0x545B080
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK21 0x545B084
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK22 0x545B088
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK23 0x545B08C
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK24 0x545B090
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK25 0x545B094
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK26 0x545B098
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK27 0x545B09C
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK28 0x545B0A0
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK30 0x545B0C0
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK31 0x545B0C4
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK32 0x545B0C8
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK33 0x545B0CC
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK34 0x545B0D0
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK35 0x545B0D4
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK36 0x545B0D8
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK37 0x545B0DC
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK38 0x545B0E0
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK39 0x545B0E4
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK3A 0x545B0E8
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK3B 0x545B0EC
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK3C 0x545B0F0
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK3D 0x545B0F4
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK3E 0x545B0F8
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK3F 0x545B0FC
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK40 0x545B100
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK41 0x545B104
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK42 0x545B108
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK43 0x545B10C
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK44 0x545B110
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK45 0x545B114
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK46 0x545B118
+
+#define NIC0_SERDES0_LANE1_REGISTER_AK47 0x545B11C
+
+#define NIC0_SERDES0_LANE1_REGISTER_AJ40 0x545B500
+
+#define NIC0_SERDES0_REGISTER_9700 0x545B800
+
+#define NIC0_SERDES0_REGISTER_9701 0x545B804
+
+#define NIC0_SERDES0_REGISTER_9803 0x545BC0C
+
+#define NIC0_SERDES0_REGISTER_9804 0x545BC10
+
+#define NIC0_SERDES0_REGISTER_9805 0x545BC14
+
+#define NIC0_SERDES0_REGISTER_980D 0x545BC34
+
+#define NIC0_SERDES0_REGISTER_980E 0x545BC38
+
+#define NIC0_SERDES0_REGISTER_980F 0x545BC3C
+
+#define NIC0_SERDES0_REGISTER_9810 0x545BC40
+
+#define NIC0_SERDES0_REGISTER_9811 0x545BC44
+
+#define NIC0_SERDES0_REGISTER_9812 0x545BC48
+
+#define NIC0_SERDES0_REGISTER_9814 0x545BC50
+
+#define NIC0_SERDES0_REGISTER_9815 0x545BC54
+
+#define NIC0_SERDES0_REGISTER_9816 0x545BC58
+
+#define NIC0_SERDES0_REGISTER_9817 0x545BC5C
+
+#define NIC0_SERDES0_REGISTER_9818 0x545BC60
+
+#define NIC0_SERDES0_REGISTER_9819 0x545BC64
+
+#define NIC0_SERDES0_REGISTER_981A 0x545BC68
+
+#define NIC0_SERDES0_REGISTER_981B 0x545BC6C
+
+#define NIC0_SERDES0_REGISTER_981C 0x545BC70
+
+#define NIC0_SERDES0_REGISTER_981F 0x545BC7C
+
+#define NIC0_SERDES0_REGISTER_9820 0x545BC80
+
+#define NIC0_SERDES0_REGISTER_9822 0x545BC88
+
+#define NIC0_SERDES0_REGISTER_9823 0x545BC8C
+
+#define NIC0_SERDES0_REGISTER_9824 0x545BC90
+
+#define NIC0_SERDES0_REGISTER_9825 0x545BC94
+
+#define NIC0_SERDES0_REGISTER_9826 0x545BC98
+
+#define NIC0_SERDES0_REGISTER_9827 0x545BC9C
+
+#define NIC0_SERDES0_REGISTER_9828 0x545BCA0
+
+#define NIC0_SERDES0_REGISTER_9829 0x545BCA4
+
+#define NIC0_SERDES0_REGISTER_982B 0x545BCAC
+
+#define NIC0_SERDES0_REGISTER_982C 0x545BCB0
+
+#define NIC0_SERDES0_REGISTER_982D 0x545BCB4
+
+#define NIC0_SERDES0_REGISTER_982E 0x545BCB8
+
+#define NIC0_SERDES0_REGISTER_982F 0x545BCBC
+
+#define NIC0_SERDES0_REGISTER_9832 0x545BCC8
+
+#define NIC0_SERDES0_REGISTER_9F00 0x545BE00
+
+#define NIC0_SERDES0_REGISTER_9F01 0x545BE04
+
+#define NIC0_SERDES0_REGISTER_9F02 0x545BE08
+
+#define NIC0_SERDES0_REGISTER_9F03 0x545BE0C
+
+#define NIC0_SERDES0_REGISTER_9F04 0x545BE10
+
+#define NIC0_SERDES0_REGISTER_9F05 0x545BE14
+
+#define NIC0_SERDES0_REGISTER_9F06 0x545BE18
+
+#define NIC0_SERDES0_REGISTER_9F07 0x545BE1C
+
+#define NIC0_SERDES0_REGISTER_9F08 0x545BE20
+
+#define NIC0_SERDES0_REGISTER_9F09 0x545BE24
+
+#define NIC0_SERDES0_REGISTER_9F0A 0x545BE28
+
+#define NIC0_SERDES0_REGISTER_9F0B 0x545BE2C
+
+#define NIC0_SERDES0_REGISTER_9F0C 0x545BE30
+
+#define NIC0_SERDES0_REGISTER_9F0D 0x545BE34
+
+#define NIC0_SERDES0_REGISTER_9F0E 0x545BE38
+
+#define NIC0_SERDES0_REGISTER_9F0F 0x545BE3C
+
+#endif /* ASIC_REG_NIC0_SERDES0_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes1_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes1_regs.h
new file mode 100644
index 000000000000..5fa7e6d9b11a
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes1_regs.h
@@ -0,0 +1,1679 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_SERDES1_REGS_H_
+#define ASIC_REG_NIC0_SERDES1_REGS_H_
+
+/*****************************************
+ * NIC0_SERDES1
+ * (Prototype: NIC_SERDES)
+ *****************************************
+ */
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P00 0x545C000
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P01 0x545C004
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P02 0x545C008
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P03 0x545C00C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P04 0x545C010
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P05 0x545C014
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P06 0x545C018
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P07 0x545C01C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P08 0x545C020
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P09 0x545C024
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P0A 0x545C028
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P0B 0x545C02C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P0C 0x545C030
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P0D 0x545C034
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P0E 0x545C038
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P0F 0x545C03C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P11 0x545C044
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P12 0x545C048
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P13 0x545C04C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P15 0x545C054
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P16 0x545C058
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P1F 0x545C07C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P20 0x545C080
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P21 0x545C084
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P23 0x545C08C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P24 0x545C090
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P28 0x545C0A0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P2D 0x545C0B4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P2E 0x545C0B8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P2F 0x545C0BC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P32 0x545C0C8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P33 0x545C0CC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P36 0x545C0D8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P37 0x545C0DC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P38 0x545C0E0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P40 0x545C100
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P41 0x545C104
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P42 0x545C108
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P43 0x545C10C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P44 0x545C110
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P45 0x545C114
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P46 0x545C118
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P47 0x545C11C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P48 0x545C120
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P49 0x545C124
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P4A 0x545C128
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P4B 0x545C12C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P4C 0x545C130
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P4E 0x545C138
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P4F 0x545C13C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P50 0x545C140
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P51 0x545C144
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P6A 0x545C1A8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P6C 0x545C1B0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P6D 0x545C1B4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P6E 0x545C1B8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P73 0x545C1CC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P74 0x545C1D0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P79 0x545C1E4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P80 0x545C200
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P81 0x545C204
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P82 0x545C208
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P83 0x545C20C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P8F 0x545C23C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P94 0x545C250
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P95 0x545C254
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P96 0x545C258
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P97 0x545C25C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P98 0x545C260
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P99 0x545C264
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P9A 0x545C268
+
+#define NIC0_SERDES1_LANE0_REGISTER_0P9B 0x545C26C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PA0 0x545C280
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PA1 0x545C284
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PA2 0x545C288
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PA3 0x545C28C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PA4 0x545C290
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PA5 0x545C294
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PA6 0x545C298
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PA7 0x545C29C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PA8 0x545C2A0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PA9 0x545C2A4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PAA 0x545C2A8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PAB 0x545C2AC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PAC 0x545C2B0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PAD 0x545C2B4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PAE 0x545C2B8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PAF 0x545C2BC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PB0 0x545C2C0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PB1 0x545C2C4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PB2 0x545C2C8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PB3 0x545C2CC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PC1 0x545C304
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PC3 0x545C30C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PC4 0x545C310
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PC9 0x545C324
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PCA 0x545C328
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PCC 0x545C330
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PCD 0x545C334
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PCF 0x545C33C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PD8 0x545C360
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PD9 0x545C364
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PE5 0x545C394
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PE6 0x545C398
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PE7 0x545C39C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PE9 0x545C3A4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PEA 0x545C3A8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PEB 0x545C3AC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PEC 0x545C3B0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PED 0x545C3B4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PEE 0x545C3B8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PEF 0x545C3BC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PF0 0x545C3C0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PF1 0x545C3C4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PF2 0x545C3C8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PF3 0x545C3CC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PF4 0x545C3D0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PF5 0x545C3D4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PF6 0x545C3D8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PF7 0x545C3DC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PF8 0x545C3E0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PF9 0x545C3E4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PFA 0x545C3E8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PFB 0x545C3EC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PFC 0x545C3F0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PFD 0x545C3F4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PFE 0x545C3F8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0PFF 0x545C3FC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N00 0x545C400
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N01 0x545C404
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N02 0x545C408
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N03 0x545C40C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N04 0x545C410
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N05 0x545C414
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N06 0x545C418
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N07 0x545C41C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N08 0x545C420
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N09 0x545C424
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N0B 0x545C42C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N0C 0x545C430
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N0D 0x545C434
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N27 0x545C49C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N28 0x545C4A0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N29 0x545C4A4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N2A 0x545C4A8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N2B 0x545C4AC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N2C 0x545C4B0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N2E 0x545C4B8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N3B 0x545C4EC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N4D 0x545C534
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N4E 0x545C538
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N4F 0x545C53C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N50 0x545C540
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N5D 0x545C574
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N5E 0x545C578
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N60 0x545C580
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N61 0x545C584
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N62 0x545C588
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N63 0x545C58C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N64 0x545C590
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N65 0x545C594
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N66 0x545C598
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N67 0x545C59C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N6E 0x545C5B8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N6F 0x545C5BC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N71 0x545C5C4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N72 0x545C5C8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N73 0x545C5CC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N75 0x545C5D4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N76 0x545C5D8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N77 0x545C5DC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N78 0x545C5E0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N79 0x545C5E4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N7A 0x545C5E8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N7D 0x545C5F4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N7E 0x545C5F8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N7F 0x545C5FC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N80 0x545C600
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N81 0x545C604
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N82 0x545C608
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N83 0x545C60C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N84 0x545C610
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N85 0x545C614
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N86 0x545C618
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N87 0x545C61C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N88 0x545C620
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N8C 0x545C630
+
+#define NIC0_SERDES1_LANE0_REGISTER_0N8F 0x545C63C
+
+#define NIC0_SERDES1_LANE0_REGISTER_0NF2 0x545C7C8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0NF3 0x545C7CC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0NF6 0x545C7D8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0NF7 0x545C7DC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0NF8 0x545C7E0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0NF9 0x545C7E4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0NFA 0x545C7E8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0NFB 0x545C7EC
+
+#define NIC0_SERDES1_LANE0_REGISTER_0NFC 0x545C7F0
+
+#define NIC0_SERDES1_LANE0_REGISTER_0NFD 0x545C7F4
+
+#define NIC0_SERDES1_LANE0_REGISTER_0NFE 0x545C7F8
+
+#define NIC0_SERDES1_LANE0_REGISTER_0NFF 0x545C7FC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P00 0x545C800
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P01 0x545C804
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P02 0x545C808
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P03 0x545C80C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P04 0x545C810
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P05 0x545C814
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P06 0x545C818
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P07 0x545C81C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P08 0x545C820
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P09 0x545C824
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P0A 0x545C828
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P0B 0x545C82C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P0C 0x545C830
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P0D 0x545C834
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P0E 0x545C838
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P0F 0x545C83C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P11 0x545C844
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P12 0x545C848
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P13 0x545C84C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P15 0x545C854
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P16 0x545C858
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P1F 0x545C87C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P20 0x545C880
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P21 0x545C884
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P23 0x545C88C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P24 0x545C890
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P28 0x545C8A0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P2D 0x545C8B4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P2E 0x545C8B8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P2F 0x545C8BC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P32 0x545C8C8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P33 0x545C8CC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P36 0x545C8D8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P37 0x545C8DC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P38 0x545C8E0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P40 0x545C900
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P41 0x545C904
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P42 0x545C908
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P43 0x545C90C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P44 0x545C910
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P45 0x545C914
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P46 0x545C918
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P47 0x545C91C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P48 0x545C920
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P49 0x545C924
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P4A 0x545C928
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P4B 0x545C92C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P4C 0x545C930
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P4E 0x545C938
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P4F 0x545C93C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P50 0x545C940
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P51 0x545C944
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P6A 0x545C9A8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P6C 0x545C9B0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P6D 0x545C9B4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P6E 0x545C9B8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P73 0x545C9CC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P74 0x545C9D0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P79 0x545C9E4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P80 0x545CA00
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P81 0x545CA04
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P82 0x545CA08
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P83 0x545CA0C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P8F 0x545CA3C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P94 0x545CA50
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P95 0x545CA54
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P96 0x545CA58
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P97 0x545CA5C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P98 0x545CA60
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P99 0x545CA64
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P9A 0x545CA68
+
+#define NIC0_SERDES1_LANE1_REGISTER_0P9B 0x545CA6C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PA0 0x545CA80
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PA1 0x545CA84
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PA2 0x545CA88
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PA3 0x545CA8C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PA4 0x545CA90
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PA5 0x545CA94
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PA6 0x545CA98
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PA7 0x545CA9C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PA8 0x545CAA0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PA9 0x545CAA4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PAA 0x545CAA8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PAB 0x545CAAC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PAC 0x545CAB0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PAD 0x545CAB4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PAE 0x545CAB8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PAF 0x545CABC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PB0 0x545CAC0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PB1 0x545CAC4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PB2 0x545CAC8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PB3 0x545CACC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PC1 0x545CB04
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PC3 0x545CB0C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PC4 0x545CB10
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PC9 0x545CB24
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PCA 0x545CB28
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PCC 0x545CB30
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PCD 0x545CB34
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PCF 0x545CB3C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PD8 0x545CB60
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PD9 0x545CB64
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PE5 0x545CB94
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PE6 0x545CB98
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PE7 0x545CB9C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PE9 0x545CBA4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PEA 0x545CBA8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PEB 0x545CBAC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PEC 0x545CBB0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PED 0x545CBB4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PEE 0x545CBB8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PEF 0x545CBBC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PF0 0x545CBC0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PF1 0x545CBC4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PF2 0x545CBC8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PF3 0x545CBCC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PF4 0x545CBD0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PF5 0x545CBD4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PF6 0x545CBD8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PF7 0x545CBDC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PF8 0x545CBE0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PF9 0x545CBE4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PFA 0x545CBE8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PFB 0x545CBEC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PFC 0x545CBF0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PFD 0x545CBF4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PFE 0x545CBF8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0PFF 0x545CBFC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N00 0x545CC00
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N01 0x545CC04
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N02 0x545CC08
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N03 0x545CC0C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N04 0x545CC10
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N05 0x545CC14
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N06 0x545CC18
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N07 0x545CC1C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N08 0x545CC20
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N09 0x545CC24
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N0B 0x545CC2C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N0C 0x545CC30
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N0D 0x545CC34
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N27 0x545CC9C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N28 0x545CCA0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N29 0x545CCA4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N2A 0x545CCA8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N2B 0x545CCAC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N2C 0x545CCB0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N2E 0x545CCB8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N3B 0x545CCEC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N4D 0x545CD34
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N4E 0x545CD38
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N4F 0x545CD3C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N50 0x545CD40
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N5D 0x545CD74
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N5E 0x545CD78
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N60 0x545CD80
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N61 0x545CD84
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N62 0x545CD88
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N63 0x545CD8C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N64 0x545CD90
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N65 0x545CD94
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N66 0x545CD98
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N67 0x545CD9C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N6E 0x545CDB8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N6F 0x545CDBC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N71 0x545CDC4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N72 0x545CDC8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N73 0x545CDCC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N75 0x545CDD4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N76 0x545CDD8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N77 0x545CDDC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N78 0x545CDE0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N79 0x545CDE4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N7A 0x545CDE8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N7D 0x545CDF4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N7E 0x545CDF8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N7F 0x545CDFC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N80 0x545CE00
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N81 0x545CE04
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N82 0x545CE08
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N83 0x545CE0C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N84 0x545CE10
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N85 0x545CE14
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N86 0x545CE18
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N87 0x545CE1C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N88 0x545CE20
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N8C 0x545CE30
+
+#define NIC0_SERDES1_LANE1_REGISTER_0N8F 0x545CE3C
+
+#define NIC0_SERDES1_LANE1_REGISTER_0NF2 0x545CFC8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0NF3 0x545CFCC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0NF6 0x545CFD8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0NF7 0x545CFDC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0NF8 0x545CFE0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0NF9 0x545CFE4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0NFA 0x545CFE8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0NFB 0x545CFEC
+
+#define NIC0_SERDES1_LANE1_REGISTER_0NFC 0x545CFF0
+
+#define NIC0_SERDES1_LANE1_REGISTER_0NFD 0x545CFF4
+
+#define NIC0_SERDES1_LANE1_REGISTER_0NFE 0x545CFF8
+
+#define NIC0_SERDES1_LANE1_REGISTER_0NFF 0x545CFFC
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI00 0x545D000
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI01 0x545D004
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI02 0x545D008
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI03 0x545D00C
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI05 0x545D014
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI06 0x545D018
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI10 0x545D040
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI11 0x545D044
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI12 0x545D048
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI13 0x545D04C
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI14 0x545D050
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI15 0x545D054
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI16 0x545D058
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI17 0x545D05C
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI18 0x545D060
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI19 0x545D064
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI1A 0x545D068
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI1B 0x545D06C
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI30 0x545D0C0
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI31 0x545D0C4
+
+#define NIC0_SERDES1_LANE0_REGISTER_AI40 0x545D100
+
+#define NIC0_SERDES1_LANE0_REGISTER_AIF0 0x545D3C0
+
+#define NIC0_SERDES1_LANE0_REGISTER_AIF1 0x545D3C4
+
+#define NIC0_SERDES1_LANE0_REGISTER_AIF2 0x545D3C8
+
+#define NIC0_SERDES1_LANE0_REGISTER_AIF3 0x545D3CC
+
+#define NIC0_SERDES1_LANE0_REGISTER_AIF4 0x545D3D0
+
+#define NIC0_SERDES1_LANE0_REGISTER_AIF5 0x545D3D4
+
+#define NIC0_SERDES1_LANE0_REGISTER_AIF6 0x545D3D8
+
+#define NIC0_SERDES1_LANE0_REGISTER_AIF7 0x545D3DC
+
+#define NIC0_SERDES1_LANE0_REGISTER_AIF8 0x545D3E0
+
+#define NIC0_SERDES1_LANE0_REGISTER_AIF9 0x545D3E4
+
+#define NIC0_SERDES1_LANE0_REGISTER_AIFA 0x545D3E8
+
+#define NIC0_SERDES1_LANE0_REGISTER_AIFB 0x545D3EC
+
+#define NIC0_SERDES1_LANE0_REGISTER_AIFC 0x545D3F0
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT00 0x545D400
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT04 0x545D410
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT05 0x545D414
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT06 0x545D418
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT07 0x545D41C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT08 0x545D420
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT09 0x545D424
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT0A 0x545D428
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT0B 0x545D42C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT0C 0x545D430
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT0D 0x545D434
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT0E 0x545D438
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT0F 0x545D43C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT10 0x545D440
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT11 0x545D444
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT12 0x545D448
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT13 0x545D44C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT14 0x545D450
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT15 0x545D454
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT16 0x545D458
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT17 0x545D45C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT18 0x545D460
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT19 0x545D464
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT1A 0x545D468
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT1B 0x545D46C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT1C 0x545D470
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT1D 0x545D474
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT1E 0x545D478
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT1F 0x545D47C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT20 0x545D480
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT21 0x545D484
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT22 0x545D488
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT23 0x545D48C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT24 0x545D490
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT25 0x545D494
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT26 0x545D498
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT29 0x545D4A4
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT2A 0x545D4A8
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT2B 0x545D4AC
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT2C 0x545D4B0
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT2D 0x545D4B4
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT2E 0x545D4B8
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT2F 0x545D4BC
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT30 0x545D4C0
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT31 0x545D4C4
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT32 0x545D4C8
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT33 0x545D4CC
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT34 0x545D4D0
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT35 0x545D4D4
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT36 0x545D4D8
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT37 0x545D4DC
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT38 0x545D4E0
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT39 0x545D4E4
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT3A 0x545D4E8
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT3B 0x545D4EC
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT3C 0x545D4F0
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT3D 0x545D4F4
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT3E 0x545D4F8
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT3F 0x545D4FC
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT40 0x545D500
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT41 0x545D504
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT42 0x545D508
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT43 0x545D50C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT44 0x545D510
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT45 0x545D514
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT4E 0x545D538
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT4F 0x545D53C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT50 0x545D540
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT51 0x545D544
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT52 0x545D548
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT53 0x545D54C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT54 0x545D550
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT55 0x545D554
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT56 0x545D558
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT57 0x545D55C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT58 0x545D560
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT59 0x545D564
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT5A 0x545D568
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT5B 0x545D56C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT5C 0x545D570
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT5D 0x545D574
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT5E 0x545D578
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT5F 0x545D57C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT60 0x545D580
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT61 0x545D584
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT62 0x545D588
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT63 0x545D58C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT64 0x545D590
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT67 0x545D59C
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT68 0x545D5A0
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT69 0x545D5A4
+
+#define NIC0_SERDES1_LANE0_REGISTER_LT6A 0x545D5A8
+
+#define NIC0_SERDES1_LANE0_REGISTER_AN01 0x545D804
+
+#define NIC0_SERDES1_LANE0_REGISTER_AN02 0x545D808
+
+#define NIC0_SERDES1_LANE0_REGISTER_AN03 0x545D80C
+
+#define NIC0_SERDES1_LANE0_REGISTER_AN04 0x545D810
+
+#define NIC0_SERDES1_LANE0_REGISTER_AN05 0x545D814
+
+#define NIC0_SERDES1_LANE0_REGISTER_AN06 0x545D818
+
+#define NIC0_SERDES1_LANE0_REGISTER_AN07 0x545D81C
+
+#define NIC0_SERDES1_LANE0_REGISTER_AN08 0x545D820
+
+#define NIC0_SERDES1_LANE0_REGISTER_AN09 0x545D824
+
+#define NIC0_SERDES1_LANE0_REGISTER_AN0A 0x545D828
+
+#define NIC0_SERDES1_LANE0_REGISTER_AN10 0x545D840
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK00 0x545DC00
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK02 0x545DC08
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK11 0x545DC44
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK12 0x545DC48
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK13 0x545DC4C
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK14 0x545DC50
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK15 0x545DC54
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK16 0x545DC58
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK17 0x545DC5C
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK18 0x545DC60
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK19 0x545DC64
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK1A 0x545DC68
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK1B 0x545DC6C
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK1C 0x545DC70
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK1D 0x545DC74
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK1E 0x545DC78
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK1F 0x545DC7C
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK20 0x545DC80
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK21 0x545DC84
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK22 0x545DC88
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK23 0x545DC8C
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK24 0x545DC90
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK25 0x545DC94
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK26 0x545DC98
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK27 0x545DC9C
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK28 0x545DCA0
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK30 0x545DCC0
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK31 0x545DCC4
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK32 0x545DCC8
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK33 0x545DCCC
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK34 0x545DCD0
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK35 0x545DCD4
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK36 0x545DCD8
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK37 0x545DCDC
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK38 0x545DCE0
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK39 0x545DCE4
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK3A 0x545DCE8
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK3B 0x545DCEC
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK3C 0x545DCF0
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK3D 0x545DCF4
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK3E 0x545DCF8
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK3F 0x545DCFC
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK40 0x545DD00
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK41 0x545DD04
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK42 0x545DD08
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK43 0x545DD0C
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK44 0x545DD10
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK45 0x545DD14
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK46 0x545DD18
+
+#define NIC0_SERDES1_LANE0_REGISTER_AK47 0x545DD1C
+
+#define NIC0_SERDES1_LANE0_REGISTER_AJ40 0x545E100
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI00 0x545E400
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI01 0x545E404
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI02 0x545E408
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI03 0x545E40C
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI05 0x545E414
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI06 0x545E418
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI10 0x545E440
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI11 0x545E444
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI12 0x545E448
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI13 0x545E44C
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI14 0x545E450
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI15 0x545E454
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI16 0x545E458
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI17 0x545E45C
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI18 0x545E460
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI19 0x545E464
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI1A 0x545E468
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI1B 0x545E46C
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI30 0x545E4C0
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI31 0x545E4C4
+
+#define NIC0_SERDES1_LANE1_REGISTER_AI40 0x545E500
+
+#define NIC0_SERDES1_LANE1_REGISTER_AIF0 0x545E7C0
+
+#define NIC0_SERDES1_LANE1_REGISTER_AIF1 0x545E7C4
+
+#define NIC0_SERDES1_LANE1_REGISTER_AIF2 0x545E7C8
+
+#define NIC0_SERDES1_LANE1_REGISTER_AIF3 0x545E7CC
+
+#define NIC0_SERDES1_LANE1_REGISTER_AIF4 0x545E7D0
+
+#define NIC0_SERDES1_LANE1_REGISTER_AIF5 0x545E7D4
+
+#define NIC0_SERDES1_LANE1_REGISTER_AIF6 0x545E7D8
+
+#define NIC0_SERDES1_LANE1_REGISTER_AIF7 0x545E7DC
+
+#define NIC0_SERDES1_LANE1_REGISTER_AIF8 0x545E7E0
+
+#define NIC0_SERDES1_LANE1_REGISTER_AIF9 0x545E7E4
+
+#define NIC0_SERDES1_LANE1_REGISTER_AIFA 0x545E7E8
+
+#define NIC0_SERDES1_LANE1_REGISTER_AIFB 0x545E7EC
+
+#define NIC0_SERDES1_LANE1_REGISTER_AIFC 0x545E7F0
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT00 0x545E800
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT04 0x545E810
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT05 0x545E814
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT06 0x545E818
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT07 0x545E81C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT08 0x545E820
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT09 0x545E824
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT0A 0x545E828
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT0B 0x545E82C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT0C 0x545E830
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT0D 0x545E834
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT0E 0x545E838
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT0F 0x545E83C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT10 0x545E840
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT11 0x545E844
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT12 0x545E848
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT13 0x545E84C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT14 0x545E850
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT15 0x545E854
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT16 0x545E858
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT17 0x545E85C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT18 0x545E860
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT19 0x545E864
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT1A 0x545E868
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT1B 0x545E86C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT1C 0x545E870
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT1D 0x545E874
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT1E 0x545E878
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT1F 0x545E87C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT20 0x545E880
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT21 0x545E884
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT22 0x545E888
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT23 0x545E88C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT24 0x545E890
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT25 0x545E894
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT26 0x545E898
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT29 0x545E8A4
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT2A 0x545E8A8
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT2B 0x545E8AC
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT2C 0x545E8B0
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT2D 0x545E8B4
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT2E 0x545E8B8
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT2F 0x545E8BC
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT30 0x545E8C0
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT31 0x545E8C4
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT32 0x545E8C8
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT33 0x545E8CC
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT34 0x545E8D0
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT35 0x545E8D4
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT36 0x545E8D8
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT37 0x545E8DC
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT38 0x545E8E0
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT39 0x545E8E4
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT3A 0x545E8E8
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT3B 0x545E8EC
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT3C 0x545E8F0
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT3D 0x545E8F4
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT3E 0x545E8F8
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT3F 0x545E8FC
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT40 0x545E900
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT41 0x545E904
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT42 0x545E908
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT43 0x545E90C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT44 0x545E910
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT45 0x545E914
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT4E 0x545E938
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT4F 0x545E93C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT50 0x545E940
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT51 0x545E944
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT52 0x545E948
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT53 0x545E94C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT54 0x545E950
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT55 0x545E954
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT56 0x545E958
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT57 0x545E95C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT58 0x545E960
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT59 0x545E964
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT5A 0x545E968
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT5B 0x545E96C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT5C 0x545E970
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT5D 0x545E974
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT5E 0x545E978
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT5F 0x545E97C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT60 0x545E980
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT61 0x545E984
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT62 0x545E988
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT63 0x545E98C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT64 0x545E990
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT67 0x545E99C
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT68 0x545E9A0
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT69 0x545E9A4
+
+#define NIC0_SERDES1_LANE1_REGISTER_LT6A 0x545E9A8
+
+#define NIC0_SERDES1_LANE1_REGISTER_AN01 0x545EC04
+
+#define NIC0_SERDES1_LANE1_REGISTER_AN02 0x545EC08
+
+#define NIC0_SERDES1_LANE1_REGISTER_AN03 0x545EC0C
+
+#define NIC0_SERDES1_LANE1_REGISTER_AN04 0x545EC10
+
+#define NIC0_SERDES1_LANE1_REGISTER_AN05 0x545EC14
+
+#define NIC0_SERDES1_LANE1_REGISTER_AN06 0x545EC18
+
+#define NIC0_SERDES1_LANE1_REGISTER_AN07 0x545EC1C
+
+#define NIC0_SERDES1_LANE1_REGISTER_AN08 0x545EC20
+
+#define NIC0_SERDES1_LANE1_REGISTER_AN09 0x545EC24
+
+#define NIC0_SERDES1_LANE1_REGISTER_AN0A 0x545EC28
+
+#define NIC0_SERDES1_LANE1_REGISTER_AN10 0x545EC40
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK00 0x545F000
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK02 0x545F008
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK11 0x545F044
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK12 0x545F048
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK13 0x545F04C
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK14 0x545F050
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK15 0x545F054
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK16 0x545F058
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK17 0x545F05C
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK18 0x545F060
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK19 0x545F064
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK1A 0x545F068
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK1B 0x545F06C
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK1C 0x545F070
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK1D 0x545F074
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK1E 0x545F078
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK1F 0x545F07C
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK20 0x545F080
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK21 0x545F084
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK22 0x545F088
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK23 0x545F08C
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK24 0x545F090
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK25 0x545F094
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK26 0x545F098
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK27 0x545F09C
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK28 0x545F0A0
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK30 0x545F0C0
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK31 0x545F0C4
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK32 0x545F0C8
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK33 0x545F0CC
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK34 0x545F0D0
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK35 0x545F0D4
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK36 0x545F0D8
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK37 0x545F0DC
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK38 0x545F0E0
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK39 0x545F0E4
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK3A 0x545F0E8
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK3B 0x545F0EC
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK3C 0x545F0F0
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK3D 0x545F0F4
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK3E 0x545F0F8
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK3F 0x545F0FC
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK40 0x545F100
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK41 0x545F104
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK42 0x545F108
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK43 0x545F10C
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK44 0x545F110
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK45 0x545F114
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK46 0x545F118
+
+#define NIC0_SERDES1_LANE1_REGISTER_AK47 0x545F11C
+
+#define NIC0_SERDES1_LANE1_REGISTER_AJ40 0x545F500
+
+#define NIC0_SERDES1_REGISTER_9700 0x545F800
+
+#define NIC0_SERDES1_REGISTER_9701 0x545F804
+
+#define NIC0_SERDES1_REGISTER_9803 0x545FC0C
+
+#define NIC0_SERDES1_REGISTER_9804 0x545FC10
+
+#define NIC0_SERDES1_REGISTER_9805 0x545FC14
+
+#define NIC0_SERDES1_REGISTER_980D 0x545FC34
+
+#define NIC0_SERDES1_REGISTER_980E 0x545FC38
+
+#define NIC0_SERDES1_REGISTER_980F 0x545FC3C
+
+#define NIC0_SERDES1_REGISTER_9810 0x545FC40
+
+#define NIC0_SERDES1_REGISTER_9811 0x545FC44
+
+#define NIC0_SERDES1_REGISTER_9812 0x545FC48
+
+#define NIC0_SERDES1_REGISTER_9814 0x545FC50
+
+#define NIC0_SERDES1_REGISTER_9815 0x545FC54
+
+#define NIC0_SERDES1_REGISTER_9816 0x545FC58
+
+#define NIC0_SERDES1_REGISTER_9817 0x545FC5C
+
+#define NIC0_SERDES1_REGISTER_9818 0x545FC60
+
+#define NIC0_SERDES1_REGISTER_9819 0x545FC64
+
+#define NIC0_SERDES1_REGISTER_981A 0x545FC68
+
+#define NIC0_SERDES1_REGISTER_981B 0x545FC6C
+
+#define NIC0_SERDES1_REGISTER_981C 0x545FC70
+
+#define NIC0_SERDES1_REGISTER_981F 0x545FC7C
+
+#define NIC0_SERDES1_REGISTER_9820 0x545FC80
+
+#define NIC0_SERDES1_REGISTER_9822 0x545FC88
+
+#define NIC0_SERDES1_REGISTER_9823 0x545FC8C
+
+#define NIC0_SERDES1_REGISTER_9824 0x545FC90
+
+#define NIC0_SERDES1_REGISTER_9825 0x545FC94
+
+#define NIC0_SERDES1_REGISTER_9826 0x545FC98
+
+#define NIC0_SERDES1_REGISTER_9827 0x545FC9C
+
+#define NIC0_SERDES1_REGISTER_9828 0x545FCA0
+
+#define NIC0_SERDES1_REGISTER_9829 0x545FCA4
+
+#define NIC0_SERDES1_REGISTER_982B 0x545FCAC
+
+#define NIC0_SERDES1_REGISTER_982C 0x545FCB0
+
+#define NIC0_SERDES1_REGISTER_982D 0x545FCB4
+
+#define NIC0_SERDES1_REGISTER_982E 0x545FCB8
+
+#define NIC0_SERDES1_REGISTER_982F 0x545FCBC
+
+#define NIC0_SERDES1_REGISTER_9832 0x545FCC8
+
+#define NIC0_SERDES1_REGISTER_9F00 0x545FE00
+
+#define NIC0_SERDES1_REGISTER_9F01 0x545FE04
+
+#define NIC0_SERDES1_REGISTER_9F02 0x545FE08
+
+#define NIC0_SERDES1_REGISTER_9F03 0x545FE0C
+
+#define NIC0_SERDES1_REGISTER_9F04 0x545FE10
+
+#define NIC0_SERDES1_REGISTER_9F05 0x545FE14
+
+#define NIC0_SERDES1_REGISTER_9F06 0x545FE18
+
+#define NIC0_SERDES1_REGISTER_9F07 0x545FE1C
+
+#define NIC0_SERDES1_REGISTER_9F08 0x545FE20
+
+#define NIC0_SERDES1_REGISTER_9F09 0x545FE24
+
+#define NIC0_SERDES1_REGISTER_9F0A 0x545FE28
+
+#define NIC0_SERDES1_REGISTER_9F0B 0x545FE2C
+
+#define NIC0_SERDES1_REGISTER_9F0C 0x545FE30
+
+#define NIC0_SERDES1_REGISTER_9F0D 0x545FE34
+
+#define NIC0_SERDES1_REGISTER_9F0E 0x545FE38
+
+#define NIC0_SERDES1_REGISTER_9F0F 0x545FE3C
+
+#endif /* ASIC_REG_NIC0_SERDES1_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_fifo_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_fifo_regs.h
new file mode 100644
index 000000000000..3819b3684fb0
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_fifo_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_TMR_AXUSER_TMR_FIFO_REGS_H_
+#define ASIC_REG_NIC0_TMR_AXUSER_TMR_FIFO_REGS_H_
+
+/*****************************************
+ * NIC0_TMR_AXUSER_TMR_FIFO
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_HB_ASID 0x5448DC0
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_HB_MMU_BP 0x5448DC4
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_HB_STRONG_ORDER 0x5448DC8
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_HB_NO_SNOOP 0x5448DCC
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_HB_WR_REDUCTION 0x5448DD0
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_HB_RD_ATOMIC 0x5448DD4
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_HB_QOS 0x5448DD8
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_HB_RSVD 0x5448DDC
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_HB_EMEM_CPAGE 0x5448DE0
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_HB_CORE 0x5448DE4
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_E2E_COORD 0x5448DE8
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_HB_WR_OVRD_LO 0x5448DF0
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_HB_WR_OVRD_HI 0x5448DF4
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_HB_RD_OVRD_LO 0x5448DF8
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_HB_RD_OVRD_HI 0x5448DFC
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_LB_COORD 0x5448E00
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_LB_LOCK 0x5448E04
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_LB_RSVD 0x5448E08
+
+#define NIC0_TMR_AXUSER_TMR_FIFO_LB_OVRD 0x5448E0C
+
+#endif /* ASIC_REG_NIC0_TMR_AXUSER_TMR_FIFO_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_free_list_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_free_list_regs.h
new file mode 100644
index 000000000000..871149ba4982
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_free_list_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_TMR_AXUSER_TMR_FREE_LIST_REGS_H_
+#define ASIC_REG_NIC0_TMR_AXUSER_TMR_FREE_LIST_REGS_H_
+
+/*****************************************
+ * NIC0_TMR_AXUSER_TMR_FREE_LIST
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_ASID 0x5448D60
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_MMU_BP 0x5448D64
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_STRONG_ORDER 0x5448D68
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_NO_SNOOP 0x5448D6C
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_WR_REDUCTION 0x5448D70
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_RD_ATOMIC 0x5448D74
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_QOS 0x5448D78
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_RSVD 0x5448D7C
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_EMEM_CPAGE 0x5448D80
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_CORE 0x5448D84
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_E2E_COORD 0x5448D88
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_WR_OVRD_LO 0x5448D90
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_WR_OVRD_HI 0x5448D94
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_RD_OVRD_LO 0x5448D98
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_RD_OVRD_HI 0x5448D9C
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_LB_COORD 0x5448DA0
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_LB_LOCK 0x5448DA4
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_LB_RSVD 0x5448DA8
+
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_LB_OVRD 0x5448DAC
+
+#endif /* ASIC_REG_NIC0_TMR_AXUSER_TMR_FREE_LIST_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_fsm_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_fsm_regs.h
new file mode 100644
index 000000000000..b06f7de95d72
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_fsm_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_TMR_AXUSER_TMR_FSM_REGS_H_
+#define ASIC_REG_NIC0_TMR_AXUSER_TMR_FSM_REGS_H_
+
+/*****************************************
+ * NIC0_TMR_AXUSER_TMR_FSM
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define NIC0_TMR_AXUSER_TMR_FSM_HB_ASID 0x5448E20
+
+#define NIC0_TMR_AXUSER_TMR_FSM_HB_MMU_BP 0x5448E24
+
+#define NIC0_TMR_AXUSER_TMR_FSM_HB_STRONG_ORDER 0x5448E28
+
+#define NIC0_TMR_AXUSER_TMR_FSM_HB_NO_SNOOP 0x5448E2C
+
+#define NIC0_TMR_AXUSER_TMR_FSM_HB_WR_REDUCTION 0x5448E30
+
+#define NIC0_TMR_AXUSER_TMR_FSM_HB_RD_ATOMIC 0x5448E34
+
+#define NIC0_TMR_AXUSER_TMR_FSM_HB_QOS 0x5448E38
+
+#define NIC0_TMR_AXUSER_TMR_FSM_HB_RSVD 0x5448E3C
+
+#define NIC0_TMR_AXUSER_TMR_FSM_HB_EMEM_CPAGE 0x5448E40
+
+#define NIC0_TMR_AXUSER_TMR_FSM_HB_CORE 0x5448E44
+
+#define NIC0_TMR_AXUSER_TMR_FSM_E2E_COORD 0x5448E48
+
+#define NIC0_TMR_AXUSER_TMR_FSM_HB_WR_OVRD_LO 0x5448E50
+
+#define NIC0_TMR_AXUSER_TMR_FSM_HB_WR_OVRD_HI 0x5448E54
+
+#define NIC0_TMR_AXUSER_TMR_FSM_HB_RD_OVRD_LO 0x5448E58
+
+#define NIC0_TMR_AXUSER_TMR_FSM_HB_RD_OVRD_HI 0x5448E5C
+
+#define NIC0_TMR_AXUSER_TMR_FSM_LB_COORD 0x5448E60
+
+#define NIC0_TMR_AXUSER_TMR_FSM_LB_LOCK 0x5448E64
+
+#define NIC0_TMR_AXUSER_TMR_FSM_LB_RSVD 0x5448E68
+
+#define NIC0_TMR_AXUSER_TMR_FSM_LB_OVRD 0x5448E6C
+
+#endif /* ASIC_REG_NIC0_TMR_AXUSER_TMR_FSM_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_masks.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_masks.h
new file mode 100644
index 000000000000..c21c2c675932
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_masks.h
@@ -0,0 +1,361 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_TMR_MASKS_H_
+#define ASIC_REG_NIC0_TMR_MASKS_H_
+
+/*****************************************
+ * NIC0_TMR
+ * (Prototype: NIC_TMR)
+ *****************************************
+ */
+
+/* NIC0_TMR_TMR_PUSH_MASK */
+#define NIC0_TMR_TMR_PUSH_MASK_R_SHIFT 0
+#define NIC0_TMR_TMR_PUSH_MASK_R_MASK 0x1
+
+/* NIC0_TMR_TMR_POP_MASK */
+#define NIC0_TMR_TMR_POP_MASK_R_SHIFT 0
+#define NIC0_TMR_TMR_POP_MASK_R_MASK 0x1
+
+/* NIC0_TMR_TMR_PUSH_RELEASE_INVALIDATE */
+#define NIC0_TMR_TMR_PUSH_RELEASE_INVALIDATE_R_SHIFT 0
+#define NIC0_TMR_TMR_PUSH_RELEASE_INVALIDATE_R_MASK 0x1
+
+/* NIC0_TMR_TMR_POP_RELEASE_INVALIDATE */
+#define NIC0_TMR_TMR_POP_RELEASE_INVALIDATE_R_SHIFT 0
+#define NIC0_TMR_TMR_POP_RELEASE_INVALIDATE_R_MASK 0x1
+
+/* NIC0_TMR_TMR_LIST_MEM_READ_MASK */
+#define NIC0_TMR_TMR_LIST_MEM_READ_MASK_R_SHIFT 0
+#define NIC0_TMR_TMR_LIST_MEM_READ_MASK_R_MASK 0x1
+
+/* NIC0_TMR_TMR_FIFO_MEM_READ_MASK */
+#define NIC0_TMR_TMR_FIFO_MEM_READ_MASK_R_SHIFT 0
+#define NIC0_TMR_TMR_FIFO_MEM_READ_MASK_R_MASK 0x1
+
+/* NIC0_TMR_TMR_LIST_MEM_WRITE_MASK */
+#define NIC0_TMR_TMR_LIST_MEM_WRITE_MASK_R_SHIFT 0
+#define NIC0_TMR_TMR_LIST_MEM_WRITE_MASK_R_MASK 0x1
+
+/* NIC0_TMR_TMR_FIFO_MEM_WRITE_MASK */
+#define NIC0_TMR_TMR_FIFO_MEM_WRITE_MASK_R_SHIFT 0
+#define NIC0_TMR_TMR_FIFO_MEM_WRITE_MASK_R_MASK 0x1
+
+/* NIC0_TMR_TMR_BASE_ADDRESS_63_32 */
+#define NIC0_TMR_TMR_BASE_ADDRESS_63_32_R_SHIFT 0
+#define NIC0_TMR_TMR_BASE_ADDRESS_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_BASE_ADDRESS_31_7 */
+#define NIC0_TMR_TMR_BASE_ADDRESS_31_7_R_SHIFT 0
+#define NIC0_TMR_TMR_BASE_ADDRESS_31_7_R_MASK 0x1FFFFFF
+
+/* NIC0_TMR_TMR_LIST_AXI_PROT */
+#define NIC0_TMR_TMR_LIST_AXI_PROT_R_SHIFT 0
+#define NIC0_TMR_TMR_LIST_AXI_PROT_R_MASK 0x7
+
+/* NIC0_TMR_TMR_STATE_AXI_PROT */
+#define NIC0_TMR_TMR_STATE_AXI_PROT_R_SHIFT 0
+#define NIC0_TMR_TMR_STATE_AXI_PROT_R_MASK 0x7
+
+/* NIC0_TMR_TMR_SCHEDQ_UPDATE_EN */
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_EN_R_SHIFT 0
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_EN_R_MASK 0x1
+
+/* NIC0_TMR_TMR_SCHEDQ_UPDATE_FIFO */
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_FIFO_R_SHIFT 0
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_FIFO_R_MASK 0xFF
+
+/* NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_31_0 */
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_31_0_R_SHIFT 0
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_63_32 */
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_63_32_R_SHIFT 0
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_95_64 */
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_95_64_R_SHIFT 0
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_95_64_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_127_96 */
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_127_96_R_SHIFT 0
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_127_96_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_159_128 */
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_159_128_R_SHIFT 0
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_159_128_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_191_160 */
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_191_160_R_SHIFT 0
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_191_160_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_216_192 */
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_216_192_R_SHIFT 0
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_216_192_R_MASK 0x1FFFFFF
+
+/* NIC0_TMR_TMR_FORCE_HIT_EN */
+#define NIC0_TMR_TMR_FORCE_HIT_EN_R_SHIFT 0
+#define NIC0_TMR_TMR_FORCE_HIT_EN_R_MASK 0x1
+
+/* NIC0_TMR_TMR_INVALIDATE_LIST */
+#define NIC0_TMR_TMR_INVALIDATE_LIST_R_SHIFT 0
+#define NIC0_TMR_TMR_INVALIDATE_LIST_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_INVALIDATE_LIST_STAT */
+#define NIC0_TMR_TMR_INVALIDATE_LIST_STAT_INVALIDATE_DONE_SHIFT 0
+#define NIC0_TMR_TMR_INVALIDATE_LIST_STAT_INVALIDATE_DONE_MASK 0x1
+#define NIC0_TMR_TMR_INVALIDATE_LIST_STAT_CACHE_IDLE_SHIFT 1
+#define NIC0_TMR_TMR_INVALIDATE_LIST_STAT_CACHE_IDLE_MASK 0x2
+
+/* NIC0_TMR_TMR_INVALIDATE_FREE */
+#define NIC0_TMR_TMR_INVALIDATE_FREE_R_SHIFT 0
+#define NIC0_TMR_TMR_INVALIDATE_FREE_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_INVALIDATE_FREE_STAT */
+#define NIC0_TMR_TMR_INVALIDATE_FREE_STAT_INVALIDATE_DONE_SHIFT 0
+#define NIC0_TMR_TMR_INVALIDATE_FREE_STAT_INVALIDATE_DONE_MASK 0x1
+#define NIC0_TMR_TMR_INVALIDATE_FREE_STAT_CACHE_IDLE_SHIFT 1
+#define NIC0_TMR_TMR_INVALIDATE_FREE_STAT_CACHE_IDLE_MASK 0x2
+
+/* NIC0_TMR_TMR_PUSH_PREFETCH_EN */
+#define NIC0_TMR_TMR_PUSH_PREFETCH_EN_R_SHIFT 0
+#define NIC0_TMR_TMR_PUSH_PREFETCH_EN_R_MASK 0x1
+
+/* NIC0_TMR_TMR_PUSH_RELEASE_EN */
+#define NIC0_TMR_TMR_PUSH_RELEASE_EN_R_SHIFT 0
+#define NIC0_TMR_TMR_PUSH_RELEASE_EN_R_MASK 0x1
+
+/* NIC0_TMR_TMR_PUSH_LOCK_EN */
+#define NIC0_TMR_TMR_PUSH_LOCK_EN_R_SHIFT 0
+#define NIC0_TMR_TMR_PUSH_LOCK_EN_R_MASK 0x1
+
+/* NIC0_TMR_TMR_PUSH_PREFETCH_NEXT_EN */
+#define NIC0_TMR_TMR_PUSH_PREFETCH_NEXT_EN_R_SHIFT 0
+#define NIC0_TMR_TMR_PUSH_PREFETCH_NEXT_EN_R_MASK 0x1
+
+/* NIC0_TMR_TMR_POP_PREFETCH_EN */
+#define NIC0_TMR_TMR_POP_PREFETCH_EN_R_SHIFT 0
+#define NIC0_TMR_TMR_POP_PREFETCH_EN_R_MASK 0x1
+
+/* NIC0_TMR_TMR_POP_RELEASE_EN */
+#define NIC0_TMR_TMR_POP_RELEASE_EN_R_SHIFT 0
+#define NIC0_TMR_TMR_POP_RELEASE_EN_R_MASK 0x1
+
+/* NIC0_TMR_TMR_POP_LOCK_EN */
+#define NIC0_TMR_TMR_POP_LOCK_EN_R_SHIFT 0
+#define NIC0_TMR_TMR_POP_LOCK_EN_R_MASK 0x1
+
+/* NIC0_TMR_TMR_POP_PREFETCH_NEXT_EN */
+#define NIC0_TMR_TMR_POP_PREFETCH_NEXT_EN_R_SHIFT 0
+#define NIC0_TMR_TMR_POP_PREFETCH_NEXT_EN_R_MASK 0x1
+
+/* NIC0_TMR_TMR_LIST_MASK */
+#define NIC0_TMR_TMR_LIST_MASK_R_SHIFT 0
+#define NIC0_TMR_TMR_LIST_MASK_R_MASK 0x7FFFFFF
+
+/* NIC0_TMR_TMR_RELEASE_INCALIDATE */
+#define NIC0_TMR_TMR_RELEASE_INCALIDATE_R_SHIFT 0
+#define NIC0_TMR_TMR_RELEASE_INCALIDATE_R_MASK 0x1
+
+/* NIC0_TMR_TMR_BASE_ADDRESS_FREE_LIST_63_32 */
+#define NIC0_TMR_TMR_BASE_ADDRESS_FREE_LIST_63_32_R_SHIFT 0
+#define NIC0_TMR_TMR_BASE_ADDRESS_FREE_LIST_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_BASE_ADDRESS_FREE_LIST_31_0 */
+#define NIC0_TMR_TMR_BASE_ADDRESS_FREE_LIST_31_0_R_SHIFT 0
+#define NIC0_TMR_TMR_BASE_ADDRESS_FREE_LIST_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_FREE_LIST_EN */
+#define NIC0_TMR_TMR_FREE_LIST_EN_R_SHIFT 0
+#define NIC0_TMR_TMR_FREE_LIST_EN_R_MASK 0x1
+
+/* NIC0_TMR_TMR_PUSH_FORCE_HIT_EN */
+#define NIC0_TMR_TMR_PUSH_FORCE_HIT_EN_R_SHIFT 0
+#define NIC0_TMR_TMR_PUSH_FORCE_HIT_EN_R_MASK 0x1
+
+/* NIC0_TMR_TMR_PRODUCER_UPDATE_EN */
+#define NIC0_TMR_TMR_PRODUCER_UPDATE_EN_R_SHIFT 0
+#define NIC0_TMR_TMR_PRODUCER_UPDATE_EN_R_MASK 0x1
+
+/* NIC0_TMR_TMR_PRODUCER_UPDATE */
+#define NIC0_TMR_TMR_PRODUCER_UPDATE_R_SHIFT 0
+#define NIC0_TMR_TMR_PRODUCER_UPDATE_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_CAHE_INVALIDATE */
+#define NIC0_TMR_TMR_CAHE_INVALIDATE_R_SHIFT 0
+#define NIC0_TMR_TMR_CAHE_INVALIDATE_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_CAHE_INVALIDATE_STAT */
+#define NIC0_TMR_TMR_CAHE_INVALIDATE_STAT_INVALIDATE_DONE_SHIFT 0
+#define NIC0_TMR_TMR_CAHE_INVALIDATE_STAT_INVALIDATE_DONE_MASK 0x1
+#define NIC0_TMR_TMR_CAHE_INVALIDATE_STAT_CACHE_IDLE_SHIFT 1
+#define NIC0_TMR_TMR_CAHE_INVALIDATE_STAT_CACHE_IDLE_MASK 0x2
+
+/* NIC0_TMR_TMR_CACHE_CLEAR_LINK_LIST */
+#define NIC0_TMR_TMR_CACHE_CLEAR_LINK_LIST_R_SHIFT 0
+#define NIC0_TMR_TMR_CACHE_CLEAR_LINK_LIST_R_MASK 0x1
+
+/* NIC0_TMR_TMR_CACHE_CFG */
+#define NIC0_TMR_TMR_CACHE_CFG_RELEASE_INVALIDATE_SHIFT 0
+#define NIC0_TMR_TMR_CACHE_CFG_RELEASE_INVALIDATE_MASK 0x1
+
+/* NIC0_TMR_TMR_CACHE_BASE_ADDR_63_32 */
+#define NIC0_TMR_TMR_CACHE_BASE_ADDR_63_32_R_SHIFT 0
+#define NIC0_TMR_TMR_CACHE_BASE_ADDR_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_CACHE_BASE_ADDR_31_7 */
+#define NIC0_TMR_TMR_CACHE_BASE_ADDR_31_7_R_SHIFT 0
+#define NIC0_TMR_TMR_CACHE_BASE_ADDR_31_7_R_MASK 0x1FFFFFF
+
+/* NIC0_TMR_TMR_TIMER_EN */
+#define NIC0_TMR_TMR_TIMER_EN_R_SHIFT 0
+#define NIC0_TMR_TMR_TIMER_EN_R_MASK 0x1
+
+/* NIC0_TMR_TMR_TICK_WRAP */
+#define NIC0_TMR_TMR_TICK_WRAP_R_SHIFT 0
+#define NIC0_TMR_TMR_TICK_WRAP_R_MASK 0xFFFF
+
+/* NIC0_TMR_TMR_SCAN_TIMER_COMP_47_32 */
+#define NIC0_TMR_TMR_SCAN_TIMER_COMP_47_32_R_SHIFT 0
+#define NIC0_TMR_TMR_SCAN_TIMER_COMP_47_32_R_MASK 0xFFFF
+
+/* NIC0_TMR_TMR_SCAN_TIMER_COMP_31_0 */
+#define NIC0_TMR_TMR_SCAN_TIMER_COMP_31_0_R_SHIFT 0
+#define NIC0_TMR_TMR_SCAN_TIMER_COMP_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TMR_SCHEDQS_0 */
+#define NIC0_TMR_TMR_SCHEDQS_0_FIRST_SHIFT 0
+#define NIC0_TMR_TMR_SCHEDQS_0_FIRST_MASK 0x1F
+#define NIC0_TMR_TMR_SCHEDQS_0_LAST_SHIFT 5
+#define NIC0_TMR_TMR_SCHEDQS_0_LAST_MASK 0x3E0
+
+/* NIC0_TMR_TMR_SCHEDQS_1 */
+#define NIC0_TMR_TMR_SCHEDQS_1_FIRST_SHIFT 0
+#define NIC0_TMR_TMR_SCHEDQS_1_FIRST_MASK 0x1F
+#define NIC0_TMR_TMR_SCHEDQS_1_LAST_SHIFT 5
+#define NIC0_TMR_TMR_SCHEDQS_1_LAST_MASK 0x3E0
+
+/* NIC0_TMR_TMR_SCHEDQS_2 */
+#define NIC0_TMR_TMR_SCHEDQS_2_FIRST_SHIFT 0
+#define NIC0_TMR_TMR_SCHEDQS_2_FIRST_MASK 0x1F
+#define NIC0_TMR_TMR_SCHEDQS_2_LAST_SHIFT 5
+#define NIC0_TMR_TMR_SCHEDQS_2_LAST_MASK 0x3E0
+
+/* NIC0_TMR_TMR_SCHEDQS_3 */
+#define NIC0_TMR_TMR_SCHEDQS_3_FIRST_SHIFT 0
+#define NIC0_TMR_TMR_SCHEDQS_3_FIRST_MASK 0x1F
+#define NIC0_TMR_TMR_SCHEDQS_3_LAST_SHIFT 5
+#define NIC0_TMR_TMR_SCHEDQS_3_LAST_MASK 0x3E0
+
+/* NIC0_TMR_TMR_CACHES_CFG */
+#define NIC0_TMR_TMR_CACHES_CFG_STATE_CACHE_PLRU_EVICTION_SHIFT 0
+#define NIC0_TMR_TMR_CACHES_CFG_STATE_CACHE_PLRU_EVICTION_MASK 0x1
+#define NIC0_TMR_TMR_CACHES_CFG_STATE_CACHE_STOP_SHIFT 1
+#define NIC0_TMR_TMR_CACHES_CFG_STATE_CACHE_STOP_MASK 0x2
+#define NIC0_TMR_TMR_CACHES_CFG_STATE_CACHE_INV_WRITEBACK_SHIFT 2
+#define NIC0_TMR_TMR_CACHES_CFG_STATE_CACHE_INV_WRITEBACK_MASK 0x4
+#define NIC0_TMR_TMR_CACHES_CFG_LIST_PLRU_EVICTION_SHIFT 3
+#define NIC0_TMR_TMR_CACHES_CFG_LIST_PLRU_EVICTION_MASK 0x8
+#define NIC0_TMR_TMR_CACHES_CFG_LIST_CACHE_STOP_SHIFT 4
+#define NIC0_TMR_TMR_CACHES_CFG_LIST_CACHE_STOP_MASK 0x10
+#define NIC0_TMR_TMR_CACHES_CFG_LIST_INV_WRITEBACK_SHIFT 5
+#define NIC0_TMR_TMR_CACHES_CFG_LIST_INV_WRITEBACK_MASK 0x20
+#define NIC0_TMR_TMR_CACHES_CFG_FREE_LIST_PLRU_EVICTION_SHIFT 6
+#define NIC0_TMR_TMR_CACHES_CFG_FREE_LIST_PLRU_EVICTION_MASK 0x40
+#define NIC0_TMR_TMR_CACHES_CFG_FREE_LIST_CACHE_STOP_SHIFT 7
+#define NIC0_TMR_TMR_CACHES_CFG_FREE_LIST_CACHE_STOP_MASK 0x80
+#define NIC0_TMR_TMR_CACHES_CFG_FREE_LIST_INV_WRITEBACK_SHIFT 8
+#define NIC0_TMR_TMR_CACHES_CFG_FREE_LIST_INV_WRITEBACK_MASK 0x100
+
+/* NIC0_TMR_TMR_DBG_COUNT_SELECT */
+#define NIC0_TMR_TMR_DBG_COUNT_SELECT_R_SHIFT 0
+#define NIC0_TMR_TMR_DBG_COUNT_SELECT_R_MASK 0x3F
+
+/* NIC0_TMR_TMR_POP_CACHE_CREDIT */
+#define NIC0_TMR_TMR_POP_CACHE_CREDIT_CREDIT_SHIFT 0
+#define NIC0_TMR_TMR_POP_CACHE_CREDIT_CREDIT_MASK 0x3F
+#define NIC0_TMR_TMR_POP_CACHE_CREDIT_FORCE_FULL_SHIFT 6
+#define NIC0_TMR_TMR_POP_CACHE_CREDIT_FORCE_FULL_MASK 0x40
+
+/* NIC0_TMR_TMR_PIPE_CREDIT */
+#define NIC0_TMR_TMR_PIPE_CREDIT_SCAN_QPC_CREDIT_SHIFT 0
+#define NIC0_TMR_TMR_PIPE_CREDIT_SCAN_QPC_CREDIT_MASK 0x3F
+#define NIC0_TMR_TMR_PIPE_CREDIT_SCAN_QPC_FORCE_FULL_SHIFT 7
+#define NIC0_TMR_TMR_PIPE_CREDIT_SCAN_QPC_FORCE_FULL_MASK 0x80
+#define NIC0_TMR_TMR_PIPE_CREDIT_SCAN_PUSH_CREDIT_SHIFT 8
+#define NIC0_TMR_TMR_PIPE_CREDIT_SCAN_PUSH_CREDIT_MASK 0x3F00
+#define NIC0_TMR_TMR_PIPE_CREDIT_SCAN_PUSH_FORCE_FULL_SHIFT 15
+#define NIC0_TMR_TMR_PIPE_CREDIT_SCAN_PUSH_FORCE_FULL_MASK 0x8000
+#define NIC0_TMR_TMR_PIPE_CREDIT_QPC_PUSH_CREDIT_SHIFT 16
+#define NIC0_TMR_TMR_PIPE_CREDIT_QPC_PUSH_CREDIT_MASK 0x3F0000
+#define NIC0_TMR_TMR_PIPE_CREDIT_QPC_PUSH_FORCE_FULL_SHIFT 24
+#define NIC0_TMR_TMR_PIPE_CREDIT_QPC_PUSH_FORCE_FULL_MASK 0x1000000
+#define NIC0_TMR_TMR_PIPE_CREDIT_QPC_CREDIT_EN_SHIFT 28
+#define NIC0_TMR_TMR_PIPE_CREDIT_QPC_CREDIT_EN_MASK 0x10000000
+#define NIC0_TMR_TMR_PIPE_CREDIT_SCAN_CREDIT_EN_SHIFT 29
+#define NIC0_TMR_TMR_PIPE_CREDIT_SCAN_CREDIT_EN_MASK 0x20000000
+#define NIC0_TMR_TMR_PIPE_CREDIT_FLOW_ARB_EN_SHIFT 30
+#define NIC0_TMR_TMR_PIPE_CREDIT_FLOW_ARB_EN_MASK 0x40000000
+
+/* NIC0_TMR_TMR_DBG_TRIG */
+#define NIC0_TMR_TMR_DBG_TRIG_R_SHIFT 0
+#define NIC0_TMR_TMR_DBG_TRIG_R_MASK 0xF
+
+/* NIC0_TMR_INTERRUPT_CAUSE */
+#define NIC0_TMR_INTERRUPT_CAUSE_R_SHIFT 0
+#define NIC0_TMR_INTERRUPT_CAUSE_R_MASK 0xF
+
+/* NIC0_TMR_INTERRUPT_MASK */
+#define NIC0_TMR_INTERRUPT_MASK_R_SHIFT 0
+#define NIC0_TMR_INTERRUPT_MASK_R_MASK 0xF
+
+/* NIC0_TMR_INTERRUPT_CLR */
+#define NIC0_TMR_INTERRUPT_CLR_R_SHIFT 0
+#define NIC0_TMR_INTERRUPT_CLR_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_TRM_SLICE_CREDIT */
+#define NIC0_TMR_TRM_SLICE_CREDIT_QPC_CREDIT_SHIFT 0
+#define NIC0_TMR_TRM_SLICE_CREDIT_QPC_CREDIT_MASK 0x7F
+#define NIC0_TMR_TRM_SLICE_CREDIT_QPC_FORCE_FULL_SHIFT 7
+#define NIC0_TMR_TRM_SLICE_CREDIT_QPC_FORCE_FULL_MASK 0x80
+#define NIC0_TMR_TRM_SLICE_CREDIT_SCAN_CREDIT_SHIFT 8
+#define NIC0_TMR_TRM_SLICE_CREDIT_SCAN_CREDIT_MASK 0x7F00
+#define NIC0_TMR_TRM_SLICE_CREDIT_SCAN_FORCE_FULL_SHIFT 15
+#define NIC0_TMR_TRM_SLICE_CREDIT_SCAN_FORCE_FULL_MASK 0x8000
+#define NIC0_TMR_TRM_SLICE_CREDIT_TOTAL_CREDIT_SHIFT 24
+#define NIC0_TMR_TRM_SLICE_CREDIT_TOTAL_CREDIT_MASK 0x7F000000
+#define NIC0_TMR_TRM_SLICE_CREDIT_TOTAL_FORCE_FULL_SHIFT 31
+#define NIC0_TMR_TRM_SLICE_CREDIT_TOTAL_FORCE_FULL_MASK 0x80000000
+
+/* NIC0_TMR_TMR_AXI_CACHE */
+#define NIC0_TMR_TMR_AXI_CACHE_R_SHIFT 0
+#define NIC0_TMR_TMR_AXI_CACHE_R_MASK 0xF
+
+/* NIC0_TMR_FREE_LIST_PUSH_MASK_EN */
+#define NIC0_TMR_FREE_LIST_PUSH_MASK_EN_R_SHIFT 0
+#define NIC0_TMR_FREE_LIST_PUSH_MASK_EN_R_MASK 0x1
+
+/* NIC0_TMR_FREE_AEMPTY_THRESHOLD */
+#define NIC0_TMR_FREE_AEMPTY_THRESHOLD_R_SHIFT 0
+#define NIC0_TMR_FREE_AEMPTY_THRESHOLD_R_MASK 0xFFFFFFFF
+
+/* NIC0_TMR_MEM_WRITE_INIT */
+#define NIC0_TMR_MEM_WRITE_INIT_CACHE_MEM_WRITE_INIT_SHIFT 0
+#define NIC0_TMR_MEM_WRITE_INIT_CACHE_MEM_WRITE_INIT_MASK 0x3
+#define NIC0_TMR_MEM_WRITE_INIT_SCHEDQFIFO_MEM_WRITE_INIT_SHIFT 2
+#define NIC0_TMR_MEM_WRITE_INIT_SCHEDQFIFO_MEM_WRITE_INIT_MASK 0x1C
+#define NIC0_TMR_MEM_WRITE_INIT_TIMERS_MEM_WRITE_INIT_SHIFT 5
+#define NIC0_TMR_MEM_WRITE_INIT_TIMERS_MEM_WRITE_INIT_MASK 0x1E0
+
+#endif /* ASIC_REG_NIC0_TMR_MASKS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_regs.h
new file mode 100644
index 000000000000..496d209565b9
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_regs.h
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_TMR_REGS_H_
+#define ASIC_REG_NIC0_TMR_REGS_H_
+
+/*****************************************
+ * NIC0_TMR
+ * (Prototype: NIC_TMR)
+ *****************************************
+ */
+
+#define NIC0_TMR_TMR_PUSH_MASK 0x5448000
+
+#define NIC0_TMR_TMR_POP_MASK 0x5448004
+
+#define NIC0_TMR_TMR_PUSH_RELEASE_INVALIDATE 0x5448008
+
+#define NIC0_TMR_TMR_POP_RELEASE_INVALIDATE 0x544800C
+
+#define NIC0_TMR_TMR_LIST_MEM_READ_MASK 0x5448010
+
+#define NIC0_TMR_TMR_FIFO_MEM_READ_MASK 0x5448014
+
+#define NIC0_TMR_TMR_LIST_MEM_WRITE_MASK 0x5448018
+
+#define NIC0_TMR_TMR_FIFO_MEM_WRITE_MASK 0x544801C
+
+#define NIC0_TMR_TMR_BASE_ADDRESS_63_32 0x5448020
+
+#define NIC0_TMR_TMR_BASE_ADDRESS_31_7 0x5448024
+
+#define NIC0_TMR_TMR_LIST_AXI_PROT 0x544802C
+
+#define NIC0_TMR_TMR_STATE_AXI_PROT 0x5448034
+
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_EN 0x544803C
+
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_FIFO 0x5448040
+
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_31_0 0x5448044
+
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_63_32 0x5448048
+
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_95_64 0x544804C
+
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_127_96 0x5448050
+
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_159_128 0x5448054
+
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_191_160 0x5448058
+
+#define NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_216_192 0x544805C
+
+#define NIC0_TMR_TMR_FORCE_HIT_EN 0x5448060
+
+#define NIC0_TMR_TMR_INVALIDATE_LIST 0x5448064
+
+#define NIC0_TMR_TMR_INVALIDATE_LIST_STAT 0x5448068
+
+#define NIC0_TMR_TMR_INVALIDATE_FREE 0x544806C
+
+#define NIC0_TMR_TMR_INVALIDATE_FREE_STAT 0x5448070
+
+#define NIC0_TMR_TMR_PUSH_PREFETCH_EN 0x5448074
+
+#define NIC0_TMR_TMR_PUSH_RELEASE_EN 0x5448078
+
+#define NIC0_TMR_TMR_PUSH_LOCK_EN 0x544807C
+
+#define NIC0_TMR_TMR_PUSH_PREFETCH_NEXT_EN 0x5448080
+
+#define NIC0_TMR_TMR_POP_PREFETCH_EN 0x5448084
+
+#define NIC0_TMR_TMR_POP_RELEASE_EN 0x5448088
+
+#define NIC0_TMR_TMR_POP_LOCK_EN 0x544808C
+
+#define NIC0_TMR_TMR_POP_PREFETCH_NEXT_EN 0x5448090
+
+#define NIC0_TMR_TMR_LIST_MASK 0x5448094
+
+#define NIC0_TMR_TMR_RELEASE_INCALIDATE 0x5448098
+
+#define NIC0_TMR_TMR_BASE_ADDRESS_FREE_LIST_63_32 0x544809C
+
+#define NIC0_TMR_TMR_BASE_ADDRESS_FREE_LIST_31_0 0x54480A0
+
+#define NIC0_TMR_TMR_FREE_LIST_EN 0x54480A4
+
+#define NIC0_TMR_TMR_PUSH_FORCE_HIT_EN 0x54480A8
+
+#define NIC0_TMR_TMR_PRODUCER_UPDATE_EN 0x54480AC
+
+#define NIC0_TMR_TMR_PRODUCER_UPDATE 0x54480B0
+
+#define NIC0_TMR_TMR_CAHE_INVALIDATE 0x54480B4
+
+#define NIC0_TMR_TMR_CAHE_INVALIDATE_STAT 0x54480B8
+
+#define NIC0_TMR_TMR_CACHE_CLEAR_LINK_LIST 0x54480BC
+
+#define NIC0_TMR_TMR_CACHE_CFG 0x54480C0
+
+#define NIC0_TMR_TMR_CACHE_BASE_ADDR_63_32 0x54480C4
+
+#define NIC0_TMR_TMR_CACHE_BASE_ADDR_31_7 0x54480C8
+
+#define NIC0_TMR_TMR_TIMER_EN 0x54480CC
+
+#define NIC0_TMR_TMR_TICK_WRAP 0x54480D0
+
+#define NIC0_TMR_TMR_SCAN_TIMER_COMP_47_32 0x54480D4
+
+#define NIC0_TMR_TMR_SCAN_TIMER_COMP_31_0 0x54480D8
+
+#define NIC0_TMR_TMR_SCHEDQS_0 0x54480DC
+
+#define NIC0_TMR_TMR_SCHEDQS_1 0x54480E0
+
+#define NIC0_TMR_TMR_SCHEDQS_2 0x54480E4
+
+#define NIC0_TMR_TMR_SCHEDQS_3 0x54480E8
+
+#define NIC0_TMR_TMR_CACHES_CFG 0x54480EC
+
+#define NIC0_TMR_TMR_DBG_COUNT_SELECT_0 0x54480F0
+
+#define NIC0_TMR_TMR_DBG_COUNT_SELECT_1 0x54480F4
+
+#define NIC0_TMR_TMR_DBG_COUNT_SELECT_2 0x54480F8
+
+#define NIC0_TMR_TMR_DBG_COUNT_SELECT_3 0x54480FC
+
+#define NIC0_TMR_TMR_DBG_COUNT_SELECT_4 0x5448100
+
+#define NIC0_TMR_TMR_DBG_COUNT_SELECT_5 0x5448104
+
+#define NIC0_TMR_TMR_DBG_COUNT_SELECT_6 0x5448108
+
+#define NIC0_TMR_TMR_DBG_COUNT_SELECT_7 0x544810C
+
+#define NIC0_TMR_TMR_DBG_COUNT_SELECT_8 0x5448110
+
+#define NIC0_TMR_TMR_DBG_COUNT_SELECT_9 0x5448114
+
+#define NIC0_TMR_TMR_DBG_COUNT_SELECT_10 0x5448118
+
+#define NIC0_TMR_TMR_DBG_COUNT_SELECT_11 0x544811C
+
+#define NIC0_TMR_TMR_POP_CACHE_CREDIT 0x5448138
+
+#define NIC0_TMR_TMR_PIPE_CREDIT 0x544813C
+
+#define NIC0_TMR_TMR_DBG_TRIG 0x5448140
+
+#define NIC0_TMR_INTERRUPT_CAUSE 0x5448144
+
+#define NIC0_TMR_INTERRUPT_MASK 0x5448148
+
+#define NIC0_TMR_INTERRUPT_CLR 0x544814C
+
+#define NIC0_TMR_TRM_SLICE_CREDIT 0x5448150
+
+#define NIC0_TMR_TMR_AXI_CACHE 0x5448154
+
+#define NIC0_TMR_FREE_LIST_PUSH_MASK_EN 0x5448158
+
+#define NIC0_TMR_FREE_AEMPTY_THRESHOLD 0x544815C
+
+#define NIC0_TMR_MEM_WRITE_INIT 0x5448170
+
+#endif /* ASIC_REG_NIC0_TMR_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txb_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txb_regs.h
new file mode 100644
index 000000000000..f049cfce8c56
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txb_regs.h
@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_TXB_REGS_H_
+#define ASIC_REG_NIC0_TXB_REGS_H_
+
+/*****************************************
+ * NIC0_TXB
+ * (Prototype: NIC_TXB)
+ *****************************************
+ */
+
+#define NIC0_TXB_ADD_ERROR_TO_PACKET 0x5454000
+
+#define NIC0_TXB_DBG_TRIG_0 0x5454004
+
+#define NIC0_TXB_DBG_TRIG_1 0x5454008
+
+#define NIC0_TXB_GLOBAL_PAUSE 0x545400C
+
+#define NIC0_TXB_PORT_DATA_COUNT_31_0_0 0x5454010
+
+#define NIC0_TXB_PORT_DATA_COUNT_31_0_1 0x5454014
+
+#define NIC0_TXB_PORT_DATA_COUNT_31_0_2 0x5454018
+
+#define NIC0_TXB_PORT_DATA_COUNT_31_0_3 0x545401C
+
+#define NIC0_TXB_PORT_DATA_COUNT_63_32_0 0x5454020
+
+#define NIC0_TXB_PORT_DATA_COUNT_63_32_1 0x5454024
+
+#define NIC0_TXB_PORT_DATA_COUNT_63_32_2 0x5454028
+
+#define NIC0_TXB_PORT_DATA_COUNT_63_32_3 0x545402C
+
+#define NIC0_TXB_PORT_TIME_COUNT_31_0_0 0x5454030
+
+#define NIC0_TXB_PORT_TIME_COUNT_31_0_1 0x5454034
+
+#define NIC0_TXB_PORT_TIME_COUNT_31_0_2 0x5454038
+
+#define NIC0_TXB_PORT_TIME_COUNT_31_0_3 0x545403C
+
+#define NIC0_TXB_PORT_TIME_COUNT_63_32_0 0x5454040
+
+#define NIC0_TXB_PORT_TIME_COUNT_63_32_1 0x5454044
+
+#define NIC0_TXB_PORT_TIME_COUNT_63_32_2 0x5454048
+
+#define NIC0_TXB_PORT_TIME_COUNT_63_32_3 0x545404C
+
+#define NIC0_TXB_CLEAR_PORT_COUNT 0x5454050
+
+#define NIC0_TXB_DBG_COUNT_SELECT_0 0x5454060
+
+#define NIC0_TXB_DBG_COUNT_SELECT_1 0x5454064
+
+#define NIC0_TXB_DBG_COUNT_SELECT_2 0x5454068
+
+#define NIC0_TXB_DBG_COUNT_SELECT_3 0x545406C
+
+#define NIC0_TXB_DBG_COUNT_SELECT_4 0x5454070
+
+#define NIC0_TXB_DBG_COUNT_SELECT_5 0x5454074
+
+#define NIC0_TXB_DBG_COUNT_SELECT_6 0x5454078
+
+#define NIC0_TXB_DBG_COUNT_SELECT_7 0x545407C
+
+#define NIC0_TXB_DBG_COUNT_SELECT_8 0x5454080
+
+#define NIC0_TXB_DBG_COUNT_SELECT_9 0x5454084
+
+#define NIC0_TXB_DBG_COUNT_SELECT_10 0x5454088
+
+#define NIC0_TXB_DBG_COUNT_SELECT_11 0x545408C
+
+#define NIC0_TXB_DBG_COUNT_SELECT_12 0x5454090
+
+#define NIC0_TXB_DBG_COUNT_SELECT_13 0x5454094
+
+#define NIC0_TXB_DBG_COUNT_SELECT_14 0x5454098
+
+#define NIC0_TXB_DBG_COUNT_SELECT_15 0x545409C
+
+#define NIC0_TXB_DBG_COUNT_SELECT_16 0x54540A0
+
+#define NIC0_TXB_DBG_COUNT_SELECT_17 0x54540A4
+
+#define NIC0_TXB_DBG_COUNT_SELECT_18 0x54540A8
+
+#define NIC0_TXB_DBG_COUNT_SELECT_19 0x54540AC
+
+#define NIC0_TXB_DBG_COUNT_SELECT_20 0x54540B0
+
+#define NIC0_TXB_DBG_COUNT_SELECT_21 0x54540B4
+
+#define NIC0_TXB_DBG_COUNT_SELECT_22 0x54540B8
+
+#define NIC0_TXB_DBG_COUNT_SELECT_23 0x54540BC
+
+#define NIC0_TXB_READ_CREDIT_0 0x54540C0
+
+#define NIC0_TXB_READ_CREDIT_1 0x54540C4
+
+#define NIC0_TXB_READ_CREDIT_2 0x54540C8
+
+#define NIC0_TXB_READ_CREDIT_3 0x54540CC
+
+#define NIC0_TXB_ICRC_CFG 0x54540D0
+
+#define NIC0_TXB_RL_PORT_EN_0 0x54540E0
+
+#define NIC0_TXB_RL_PORT_EN_1 0x54540E4
+
+#define NIC0_TXB_RL_PORT_EN_2 0x54540E8
+
+#define NIC0_TXB_RL_PORT_EN_3 0x54540EC
+
+#define NIC0_TXB_RL_PORT_SAT_0 0x54540F0
+
+#define NIC0_TXB_RL_PORT_SAT_1 0x54540F4
+
+#define NIC0_TXB_RL_PORT_SAT_2 0x54540F8
+
+#define NIC0_TXB_RL_PORT_SAT_3 0x54540FC
+
+#define NIC0_TXB_RL_PORT_RST_0 0x5454100
+
+#define NIC0_TXB_RL_PORT_RST_1 0x5454104
+
+#define NIC0_TXB_RL_PORT_RST_2 0x5454108
+
+#define NIC0_TXB_RL_PORT_RST_3 0x545410C
+
+#define NIC0_TXB_RL_PORT_TIMEOUT_0 0x5454110
+
+#define NIC0_TXB_RL_PORT_TIMEOUT_1 0x5454114
+
+#define NIC0_TXB_RL_PORT_TIMEOUT_2 0x5454118
+
+#define NIC0_TXB_RL_PORT_TIMEOUT_3 0x545411C
+
+#define NIC0_TXB_PORT_INIT 0x5454120
+
+#define NIC0_TXB_PORT_INIT_STATUS 0x5454124
+
+#define NIC0_TXB_CLK_GATE_FORCE_OPEN 0x5454130
+
+#define NIC0_TXB_CLK_GATE_CLOSE_DELAY 0x5454134
+
+#define NIC0_TXB_CLK_GATE_STATUS 0x5454138
+
+#define NIC0_TXB_TDM_PORT_ARB_MASK 0x545413C
+
+#endif /* ASIC_REG_NIC0_TXB_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txe0_masks.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txe0_masks.h
new file mode 100644
index 000000000000..64bea9bb3c91
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txe0_masks.h
@@ -0,0 +1,759 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_TXE0_MASKS_H_
+#define ASIC_REG_NIC0_TXE0_MASKS_H_
+
+/*****************************************
+ * NIC0_TXE0
+ * (Prototype: NIC_TXE)
+ *****************************************
+ */
+
+/* NIC0_TXE0_WQE_FETCH_REQ_MASK_31_0 */
+#define NIC0_TXE0_WQE_FETCH_REQ_MASK_31_0_R_SHIFT 0
+#define NIC0_TXE0_WQE_FETCH_REQ_MASK_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_FETCH_REQ_MASK_47_32 */
+#define NIC0_TXE0_WQE_FETCH_REQ_MASK_47_32_R_SHIFT 0
+#define NIC0_TXE0_WQE_FETCH_REQ_MASK_47_32_R_MASK 0xFFFF
+
+/* NIC0_TXE0_LOCAL_WQ_BUFFER_SIZE */
+#define NIC0_TXE0_LOCAL_WQ_BUFFER_SIZE_R_SHIFT 0
+#define NIC0_TXE0_LOCAL_WQ_BUFFER_SIZE_R_MASK 0xF
+
+/* NIC0_TXE0_LOCAL_WQ_LINE_SIZE */
+#define NIC0_TXE0_LOCAL_WQ_LINE_SIZE_R_SHIFT 0
+#define NIC0_TXE0_LOCAL_WQ_LINE_SIZE_R_MASK 0xF
+
+/* NIC0_TXE0_LOG_MAX_WQ_SIZE */
+#define NIC0_TXE0_LOG_MAX_WQ_SIZE_R_SHIFT 0
+#define NIC0_TXE0_LOG_MAX_WQ_SIZE_R_MASK 0x1F
+
+/* NIC0_TXE0_SQ_BASE_ADDRESS_63_32 */
+#define NIC0_TXE0_SQ_BASE_ADDRESS_63_32_R_SHIFT 0
+#define NIC0_TXE0_SQ_BASE_ADDRESS_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_SQ_BASE_ADDRESS_31_0 */
+#define NIC0_TXE0_SQ_BASE_ADDRESS_31_0_R_SHIFT 0
+#define NIC0_TXE0_SQ_BASE_ADDRESS_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_USER_CFG */
+#define NIC0_TXE0_WQE_USER_CFG_MMU_BYPASS_SHIFT 0
+#define NIC0_TXE0_WQE_USER_CFG_MMU_BYPASS_MASK 0xF
+
+/* NIC0_TXE0_ALLOC_CREDIT */
+#define NIC0_TXE0_ALLOC_CREDIT_R_SHIFT 0
+#define NIC0_TXE0_ALLOC_CREDIT_R_MASK 0xFF
+
+/* NIC0_TXE0_ALLOC_CREDIT_FORCE_FULL */
+#define NIC0_TXE0_ALLOC_CREDIT_FORCE_FULL_R_SHIFT 0
+#define NIC0_TXE0_ALLOC_CREDIT_FORCE_FULL_R_MASK 0x1
+
+/* NIC0_TXE0_READ_CREDIT */
+#define NIC0_TXE0_READ_CREDIT_R_SHIFT 0
+#define NIC0_TXE0_READ_CREDIT_R_MASK 0x7FF
+
+/* NIC0_TXE0_READ_CREDIT_FORCE_FULL */
+#define NIC0_TXE0_READ_CREDIT_FORCE_FULL_R_SHIFT 0
+#define NIC0_TXE0_READ_CREDIT_FORCE_FULL_R_MASK 0x1
+
+/* NIC0_TXE0_BURST_ENABLE */
+#define NIC0_TXE0_BURST_ENABLE_R_SHIFT 0
+#define NIC0_TXE0_BURST_ENABLE_R_MASK 0x1
+
+/* NIC0_TXE0_WR_INIT_BUSY */
+#define NIC0_TXE0_WR_INIT_BUSY_R_SHIFT 0
+#define NIC0_TXE0_WR_INIT_BUSY_R_MASK 0x3
+
+/* NIC0_TXE0_READ_RES_WT_INIT_BUSY */
+#define NIC0_TXE0_READ_RES_WT_INIT_BUSY_R_SHIFT 0
+#define NIC0_TXE0_READ_RES_WT_INIT_BUSY_R_MASK 0x1
+
+/* NIC0_TXE0_BTH_TVER */
+#define NIC0_TXE0_BTH_TVER_R_SHIFT 0
+#define NIC0_TXE0_BTH_TVER_R_MASK 0xF
+
+/* NIC0_TXE0_IPV4_IDENTIFICATION */
+#define NIC0_TXE0_IPV4_IDENTIFICATION_R_SHIFT 0
+#define NIC0_TXE0_IPV4_IDENTIFICATION_R_MASK 0xFFFF
+
+/* NIC0_TXE0_IPV4_FLAGS */
+#define NIC0_TXE0_IPV4_FLAGS_R_SHIFT 0
+#define NIC0_TXE0_IPV4_FLAGS_R_MASK 0x7
+
+/* NIC0_TXE0_PAD */
+#define NIC0_TXE0_PAD_ENABLE_SHIFT 0
+#define NIC0_TXE0_PAD_ENABLE_MASK 0x1
+#define NIC0_TXE0_PAD_RAW_QP_ENABLE_SHIFT 1
+#define NIC0_TXE0_PAD_RAW_QP_ENABLE_MASK 0x2
+
+/* NIC0_TXE0_ADD_PAD_TO_IPV4_LEN */
+#define NIC0_TXE0_ADD_PAD_TO_IPV4_LEN_R_SHIFT 0
+#define NIC0_TXE0_ADD_PAD_TO_IPV4_LEN_R_MASK 0x1
+
+/* NIC0_TXE0_ADD_PAD_TO_UDP_LEN */
+#define NIC0_TXE0_ADD_PAD_TO_UDP_LEN_R_SHIFT 0
+#define NIC0_TXE0_ADD_PAD_TO_UDP_LEN_R_MASK 0x1
+
+/* NIC0_TXE0_ICRC_EN */
+#define NIC0_TXE0_ICRC_EN_R_SHIFT 0
+#define NIC0_TXE0_ICRC_EN_R_MASK 0x1
+
+/* NIC0_TXE0_UDP_MASK_S_PORT */
+#define NIC0_TXE0_UDP_MASK_S_PORT_R_SHIFT 0
+#define NIC0_TXE0_UDP_MASK_S_PORT_R_MASK 0xFFFF
+
+/* NIC0_TXE0_UDP_CHECKSUM */
+#define NIC0_TXE0_UDP_CHECKSUM_R_SHIFT 0
+#define NIC0_TXE0_UDP_CHECKSUM_R_MASK 0xFFFF
+
+/* NIC0_TXE0_UDP_DEST_PORT */
+#define NIC0_TXE0_UDP_DEST_PORT_R_SHIFT 0
+#define NIC0_TXE0_UDP_DEST_PORT_R_MASK 0xFFFF
+
+/* NIC0_TXE0_PORT0_MAC_CFG_47_32 */
+#define NIC0_TXE0_PORT0_MAC_CFG_47_32_R_SHIFT 0
+#define NIC0_TXE0_PORT0_MAC_CFG_47_32_R_MASK 0xFFFF
+
+/* NIC0_TXE0_PORT0_MAC_CFG_31_0 */
+#define NIC0_TXE0_PORT0_MAC_CFG_31_0_R_SHIFT 0
+#define NIC0_TXE0_PORT0_MAC_CFG_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_PORT1_MAC_CFG_47_32 */
+#define NIC0_TXE0_PORT1_MAC_CFG_47_32_R_SHIFT 0
+#define NIC0_TXE0_PORT1_MAC_CFG_47_32_R_MASK 0xFFFF
+
+/* NIC0_TXE0_PORT1_MAC_CFG_31_0 */
+#define NIC0_TXE0_PORT1_MAC_CFG_31_0_R_SHIFT 0
+#define NIC0_TXE0_PORT1_MAC_CFG_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_PRIO_TO_DSCP */
+#define NIC0_TXE0_PRIO_TO_DSCP_PRIO0_SHIFT 0
+#define NIC0_TXE0_PRIO_TO_DSCP_PRIO0_MASK 0x3F
+#define NIC0_TXE0_PRIO_TO_DSCP_PRIO1_SHIFT 8
+#define NIC0_TXE0_PRIO_TO_DSCP_PRIO1_MASK 0x3F00
+#define NIC0_TXE0_PRIO_TO_DSCP_PRIO2_SHIFT 16
+#define NIC0_TXE0_PRIO_TO_DSCP_PRIO2_MASK 0x3F0000
+#define NIC0_TXE0_PRIO_TO_DSCP_PRIO3_SHIFT 24
+#define NIC0_TXE0_PRIO_TO_DSCP_PRIO3_MASK 0x3F000000
+
+/* NIC0_TXE0_PRIO_TO_PCP */
+#define NIC0_TXE0_PRIO_TO_PCP_PORT0_PRIO0_SHIFT 0
+#define NIC0_TXE0_PRIO_TO_PCP_PORT0_PRIO0_MASK 0x7
+#define NIC0_TXE0_PRIO_TO_PCP_PORT0_PRIO1_SHIFT 3
+#define NIC0_TXE0_PRIO_TO_PCP_PORT0_PRIO1_MASK 0x38
+#define NIC0_TXE0_PRIO_TO_PCP_PORT0_PRIO2_SHIFT 6
+#define NIC0_TXE0_PRIO_TO_PCP_PORT0_PRIO2_MASK 0x1C0
+#define NIC0_TXE0_PRIO_TO_PCP_PORT0_PRIO3_SHIFT 9
+#define NIC0_TXE0_PRIO_TO_PCP_PORT0_PRIO3_MASK 0xE00
+#define NIC0_TXE0_PRIO_TO_PCP_PORT1_PRIO0_SHIFT 12
+#define NIC0_TXE0_PRIO_TO_PCP_PORT1_PRIO0_MASK 0x7000
+#define NIC0_TXE0_PRIO_TO_PCP_PORT1_PRIO1_SHIFT 15
+#define NIC0_TXE0_PRIO_TO_PCP_PORT1_PRIO1_MASK 0x38000
+#define NIC0_TXE0_PRIO_TO_PCP_PORT1_PRIO2_SHIFT 18
+#define NIC0_TXE0_PRIO_TO_PCP_PORT1_PRIO2_MASK 0x1C0000
+#define NIC0_TXE0_PRIO_TO_PCP_PORT1_PRIO3_SHIFT 21
+#define NIC0_TXE0_PRIO_TO_PCP_PORT1_PRIO3_MASK 0xE00000
+
+/* NIC0_TXE0_MAC_ETHER_TYPE */
+#define NIC0_TXE0_MAC_ETHER_TYPE_R_SHIFT 0
+#define NIC0_TXE0_MAC_ETHER_TYPE_R_MASK 0xFFFF
+
+/* NIC0_TXE0_MAC_ETHER_TYPE_VLAN */
+#define NIC0_TXE0_MAC_ETHER_TYPE_VLAN_R_SHIFT 0
+#define NIC0_TXE0_MAC_ETHER_TYPE_VLAN_R_MASK 0xFFFF
+
+/* NIC0_TXE0_ECN_0 */
+#define NIC0_TXE0_ECN_0_R_SHIFT 0
+#define NIC0_TXE0_ECN_0_R_MASK 0x3
+
+/* NIC0_TXE0_ECN_1 */
+#define NIC0_TXE0_ECN_1_R_SHIFT 0
+#define NIC0_TXE0_ECN_1_R_MASK 0x3
+
+/* NIC0_TXE0_IPV4_TIME_TO_LIVE_0 */
+#define NIC0_TXE0_IPV4_TIME_TO_LIVE_0_R_SHIFT 0
+#define NIC0_TXE0_IPV4_TIME_TO_LIVE_0_R_MASK 0xFF
+
+/* NIC0_TXE0_IPV4_TIME_TO_LIVE_1 */
+#define NIC0_TXE0_IPV4_TIME_TO_LIVE_1_R_SHIFT 0
+#define NIC0_TXE0_IPV4_TIME_TO_LIVE_1_R_MASK 0xFF
+
+/* NIC0_TXE0_PRIO_PORT_CREDIT_FORCE */
+#define NIC0_TXE0_PRIO_PORT_CREDIT_FORCE_FORCE_FULL_SHIFT 0
+#define NIC0_TXE0_PRIO_PORT_CREDIT_FORCE_FORCE_FULL_MASK 0xFF
+
+/* NIC0_TXE0_PRIO_PORT_CRDIT */
+#define NIC0_TXE0_PRIO_PORT_CRDIT_R_SHIFT 0
+#define NIC0_TXE0_PRIO_PORT_CRDIT_R_MASK 0xFF
+
+/* NIC0_TXE0_WQE_FETCH_TOKEN_EN */
+#define NIC0_TXE0_WQE_FETCH_TOKEN_EN_R_SHIFT 0
+#define NIC0_TXE0_WQE_FETCH_TOKEN_EN_R_MASK 0x1
+
+/* NIC0_TXE0_NACK_SYNDROME */
+#define NIC0_TXE0_NACK_SYNDROME_SYNDROME_0_SHIFT 0
+#define NIC0_TXE0_NACK_SYNDROME_SYNDROME_0_MASK 0xFF
+#define NIC0_TXE0_NACK_SYNDROME_SYNDROME_1_SHIFT 8
+#define NIC0_TXE0_NACK_SYNDROME_SYNDROME_1_MASK 0xFF00
+#define NIC0_TXE0_NACK_SYNDROME_SYNDROME_2_SHIFT 16
+#define NIC0_TXE0_NACK_SYNDROME_SYNDROME_2_MASK 0xFF0000
+#define NIC0_TXE0_NACK_SYNDROME_SYNDROME_3_SHIFT 24
+#define NIC0_TXE0_NACK_SYNDROME_SYNDROME_3_MASK 0xFF000000
+
+/* NIC0_TXE0_WQE_FETCH_AXI_PROT */
+#define NIC0_TXE0_WQE_FETCH_AXI_PROT_PRIVILEGE_SHIFT 0
+#define NIC0_TXE0_WQE_FETCH_AXI_PROT_PRIVILEGE_MASK 0x7
+#define NIC0_TXE0_WQE_FETCH_AXI_PROT_SECURED_SHIFT 3
+#define NIC0_TXE0_WQE_FETCH_AXI_PROT_SECURED_MASK 0x38
+#define NIC0_TXE0_WQE_FETCH_AXI_PROT_UNSECURED_SHIFT 6
+#define NIC0_TXE0_WQE_FETCH_AXI_PROT_UNSECURED_MASK 0x1C0
+
+/* NIC0_TXE0_DATA_FETCH_AXI_PROT */
+#define NIC0_TXE0_DATA_FETCH_AXI_PROT_PRIVILEGE_SHIFT 0
+#define NIC0_TXE0_DATA_FETCH_AXI_PROT_PRIVILEGE_MASK 0x7
+#define NIC0_TXE0_DATA_FETCH_AXI_PROT_SECURED_SHIFT 3
+#define NIC0_TXE0_DATA_FETCH_AXI_PROT_SECURED_MASK 0x38
+#define NIC0_TXE0_DATA_FETCH_AXI_PROT_UNSECURED_SHIFT 6
+#define NIC0_TXE0_DATA_FETCH_AXI_PROT_UNSECURED_MASK 0x1C0
+
+/* NIC0_TXE0_FETCH_OUT_OF_TOKEN */
+#define NIC0_TXE0_FETCH_OUT_OF_TOKEN_R_SHIFT 0
+#define NIC0_TXE0_FETCH_OUT_OF_TOKEN_R_MASK 0x7
+
+/* NIC0_TXE0_ECN_COUNT_EN */
+#define NIC0_TXE0_ECN_COUNT_EN_R_SHIFT 0
+#define NIC0_TXE0_ECN_COUNT_EN_R_MASK 0x1
+
+/* NIC0_TXE0_INERRUPT_CAUSE */
+#define NIC0_TXE0_INERRUPT_CAUSE_R_SHIFT 0
+#define NIC0_TXE0_INERRUPT_CAUSE_R_MASK 0x7F
+
+/* NIC0_TXE0_INTERRUPT_MASK */
+#define NIC0_TXE0_INTERRUPT_MASK_R_SHIFT 0
+#define NIC0_TXE0_INTERRUPT_MASK_R_MASK 0x7F
+
+/* NIC0_TXE0_INTERRUPT_CLR */
+#define NIC0_TXE0_INTERRUPT_CLR_R_SHIFT 0
+#define NIC0_TXE0_INTERRUPT_CLR_R_MASK 0x1
+
+/* NIC0_TXE0_VLAN_TAG_QPN_OFFSET */
+#define NIC0_TXE0_VLAN_TAG_QPN_OFFSET_R_SHIFT 0
+#define NIC0_TXE0_VLAN_TAG_QPN_OFFSET_R_MASK 0x1F
+
+/* NIC0_TXE0_VALN_TAG_CFG */
+#define NIC0_TXE0_VALN_TAG_CFG_TPD_SHIFT 0
+#define NIC0_TXE0_VALN_TAG_CFG_TPD_MASK 0xFFFF
+#define NIC0_TXE0_VALN_TAG_CFG_VLAN_ID_SHIFT 16
+#define NIC0_TXE0_VALN_TAG_CFG_VLAN_ID_MASK 0xFFF0000
+#define NIC0_TXE0_VALN_TAG_CFG_DEI_SHIFT 28
+#define NIC0_TXE0_VALN_TAG_CFG_DEI_MASK 0x10000000
+#define NIC0_TXE0_VALN_TAG_CFG_ENABLE_SHIFT 31
+#define NIC0_TXE0_VALN_TAG_CFG_ENABLE_MASK 0x80000000
+
+/* NIC0_TXE0_DBG_TRIG */
+#define NIC0_TXE0_DBG_TRIG_R_SHIFT 0
+#define NIC0_TXE0_DBG_TRIG_R_MASK 0xF
+
+/* NIC0_TXE0_WQE_PREFETCH_CFG */
+#define NIC0_TXE0_WQE_PREFETCH_CFG_ENABLE_SHIFT 0
+#define NIC0_TXE0_WQE_PREFETCH_CFG_ENABLE_MASK 0x1
+#define NIC0_TXE0_WQE_PREFETCH_CFG_ALWAYS_ENABLE_SHIFT 1
+#define NIC0_TXE0_WQE_PREFETCH_CFG_ALWAYS_ENABLE_MASK 0x2
+
+/* NIC0_TXE0_WQE_PREFETCH_INVALIDATE */
+#define NIC0_TXE0_WQE_PREFETCH_INVALIDATE_R_SHIFT 0
+#define NIC0_TXE0_WQE_PREFETCH_INVALIDATE_R_MASK 0x1
+
+/* NIC0_TXE0_SWAP_MEMORY_ENDIANNESS */
+#define NIC0_TXE0_SWAP_MEMORY_ENDIANNESS_RAW_SHIFT 0
+#define NIC0_TXE0_SWAP_MEMORY_ENDIANNESS_RAW_MASK 0x1
+#define NIC0_TXE0_SWAP_MEMORY_ENDIANNESS_RDMA_SHIFT 1
+#define NIC0_TXE0_SWAP_MEMORY_ENDIANNESS_RDMA_MASK 0x2
+
+/* NIC0_TXE0_WQE_FETCH_SLICE_47_32 */
+#define NIC0_TXE0_WQE_FETCH_SLICE_47_32_R_SHIFT 0
+#define NIC0_TXE0_WQE_FETCH_SLICE_47_32_R_MASK 0xFFFF
+
+/* NIC0_TXE0_WQE_FETCH_SLICE_31_0 */
+#define NIC0_TXE0_WQE_FETCH_SLICE_31_0_R_SHIFT 0
+#define NIC0_TXE0_WQE_FETCH_SLICE_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_EXE_SLICE_47_32 */
+#define NIC0_TXE0_WQE_EXE_SLICE_47_32_R_SHIFT 0
+#define NIC0_TXE0_WQE_EXE_SLICE_47_32_R_MASK 0xFFFF
+
+/* NIC0_TXE0_WQE_EXE_SLICE_31_0 */
+#define NIC0_TXE0_WQE_EXE_SLICE_31_0_R_SHIFT 0
+#define NIC0_TXE0_WQE_EXE_SLICE_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_DBG_COUNT_SELECT0 */
+#define NIC0_TXE0_DBG_COUNT_SELECT0_R_SHIFT 0
+#define NIC0_TXE0_DBG_COUNT_SELECT0_R_MASK 0x3F
+
+/* NIC0_TXE0_DBG_COUNT_SELECT1 */
+#define NIC0_TXE0_DBG_COUNT_SELECT1_R_SHIFT 0
+#define NIC0_TXE0_DBG_COUNT_SELECT1_R_MASK 0x3F
+
+/* NIC0_TXE0_DBG_COUNT_SELECT2 */
+#define NIC0_TXE0_DBG_COUNT_SELECT2_R_SHIFT 0
+#define NIC0_TXE0_DBG_COUNT_SELECT2_R_MASK 0x3F
+
+/* NIC0_TXE0_DBG_COUNT_SELECT3 */
+#define NIC0_TXE0_DBG_COUNT_SELECT3_R_SHIFT 0
+#define NIC0_TXE0_DBG_COUNT_SELECT3_R_MASK 0x3F
+
+/* NIC0_TXE0_DBG_COUNT_SELECT4 */
+#define NIC0_TXE0_DBG_COUNT_SELECT4_R_SHIFT 0
+#define NIC0_TXE0_DBG_COUNT_SELECT4_R_MASK 0x3F
+
+/* NIC0_TXE0_DBG_COUNT_SELECT5 */
+#define NIC0_TXE0_DBG_COUNT_SELECT5_R_SHIFT 0
+#define NIC0_TXE0_DBG_COUNT_SELECT5_R_MASK 0x3F
+
+/* NIC0_TXE0_DBG_COUNT_SELECT6 */
+#define NIC0_TXE0_DBG_COUNT_SELECT6_R_SHIFT 0
+#define NIC0_TXE0_DBG_COUNT_SELECT6_R_MASK 0x3F
+
+/* NIC0_TXE0_DBG_COUNT_SELECT7 */
+#define NIC0_TXE0_DBG_COUNT_SELECT7_R_SHIFT 0
+#define NIC0_TXE0_DBG_COUNT_SELECT7_R_MASK 0x3F
+
+/* NIC0_TXE0_DBG_COUNT_SELECT8 */
+#define NIC0_TXE0_DBG_COUNT_SELECT8_R_SHIFT 0
+#define NIC0_TXE0_DBG_COUNT_SELECT8_R_MASK 0x3F
+
+/* NIC0_TXE0_DBG_COUNT_SELECT9 */
+#define NIC0_TXE0_DBG_COUNT_SELECT9_R_SHIFT 0
+#define NIC0_TXE0_DBG_COUNT_SELECT9_R_MASK 0x3F
+
+/* NIC0_TXE0_DBG_COUNT_SELECT10 */
+#define NIC0_TXE0_DBG_COUNT_SELECT10_R_SHIFT 0
+#define NIC0_TXE0_DBG_COUNT_SELECT10_R_MASK 0x3F
+
+/* NIC0_TXE0_DBG_COUNT_SELECT11 */
+#define NIC0_TXE0_DBG_COUNT_SELECT11_R_SHIFT 0
+#define NIC0_TXE0_DBG_COUNT_SELECT11_R_MASK 0x3F
+
+/* NIC0_TXE0_BTH_MKEY */
+#define NIC0_TXE0_BTH_MKEY_R_SHIFT 0
+#define NIC0_TXE0_BTH_MKEY_R_MASK 0xFFFF
+
+/* NIC0_TXE0_WQE_BUFF_FLUSH_SLICE_47_3 */
+#define NIC0_TXE0_WQE_BUFF_FLUSH_SLICE_47_3_R_SHIFT 0
+#define NIC0_TXE0_WQE_BUFF_FLUSH_SLICE_47_3_R_MASK 0xFFFF
+
+/* NIC0_TXE0_WQE_BUFF_FLUSH_SLICE_31_0 */
+#define NIC0_TXE0_WQE_BUFF_FLUSH_SLICE_31_0_R_SHIFT 0
+#define NIC0_TXE0_WQE_BUFF_FLUSH_SLICE_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_INTERRUPT_INDEX_MASK_RING */
+#define NIC0_TXE0_INTERRUPT_INDEX_MASK_RING_R_SHIFT 0
+#define NIC0_TXE0_INTERRUPT_INDEX_MASK_RING_R_MASK 0x3FFFFF
+
+/* NIC0_TXE0_QPN_RING */
+#define NIC0_TXE0_QPN_RING_R_SHIFT 0
+#define NIC0_TXE0_QPN_RING_R_MASK 0xFFFFFF
+
+/* NIC0_TXE0_INTERRUPT_EACH_PACKET */
+#define NIC0_TXE0_INTERRUPT_EACH_PACKET_R_SHIFT 0
+#define NIC0_TXE0_INTERRUPT_EACH_PACKET_R_MASK 0x1F
+
+/* NIC0_TXE0_EXECUTIN_INDEX_RING */
+#define NIC0_TXE0_EXECUTIN_INDEX_RING_R_SHIFT 0
+#define NIC0_TXE0_EXECUTIN_INDEX_RING_R_MASK 0x3FFFFF
+
+/* NIC0_TXE0_WQE_FETCH_AXI_USER_LO */
+#define NIC0_TXE0_WQE_FETCH_AXI_USER_LO_R_SHIFT 0
+#define NIC0_TXE0_WQE_FETCH_AXI_USER_LO_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_FETCH_AXI_USER_HI */
+#define NIC0_TXE0_WQE_FETCH_AXI_USER_HI_R_SHIFT 0
+#define NIC0_TXE0_WQE_FETCH_AXI_USER_HI_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_DATA_FETCH_AXI_USER_LO */
+#define NIC0_TXE0_DATA_FETCH_AXI_USER_LO_R_SHIFT 0
+#define NIC0_TXE0_DATA_FETCH_AXI_USER_LO_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_DATA_FETCH_AXI_USER_HI */
+#define NIC0_TXE0_DATA_FETCH_AXI_USER_HI_R_SHIFT 0
+#define NIC0_TXE0_DATA_FETCH_AXI_USER_HI_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_CHICKEN_BITS */
+#define NIC0_TXE0_CHICKEN_BITS_BUS_SHIFT 0
+#define NIC0_TXE0_CHICKEN_BITS_BUS_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_CHICKEN_BITS2 */
+#define NIC0_TXE0_CHICKEN_BITS2_BUS_SHIFT 0
+#define NIC0_TXE0_CHICKEN_BITS2_BUS_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_CHECK_EN */
+#define NIC0_TXE0_WQE_CHECK_EN_WRITE_VALID_OPCODE_EN_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_EN_WRITE_VALID_OPCODE_EN_MASK 0x1
+#define NIC0_TXE0_WQE_CHECK_EN_RDV_VALID_OPCODE_EN_SHIFT 1
+#define NIC0_TXE0_WQE_CHECK_EN_RDV_VALID_OPCODE_EN_MASK 0x2
+#define NIC0_TXE0_WQE_CHECK_EN_READ_VALID_OPCODE_EN_SHIFT 2
+#define NIC0_TXE0_WQE_CHECK_EN_READ_VALID_OPCODE_EN_MASK 0x4
+#define NIC0_TXE0_WQE_CHECK_EN_GAUDI1_VALID_OPCODE_EN_SHIFT 3
+#define NIC0_TXE0_WQE_CHECK_EN_GAUDI1_VALID_OPCODE_EN_MASK 0x8
+#define NIC0_TXE0_WQE_CHECK_EN_WRITE_SIZE_ZERO_EN_SHIFT 4
+#define NIC0_TXE0_WQE_CHECK_EN_WRITE_SIZE_ZERO_EN_MASK 0x10
+#define NIC0_TXE0_WQE_CHECK_EN_STRIDE_SIZE_ZERO_EN_SHIFT 5
+#define NIC0_TXE0_WQE_CHECK_EN_STRIDE_SIZE_ZERO_EN_MASK 0x20
+#define NIC0_TXE0_WQE_CHECK_EN_SEND_SIZE_ZERO_EN_SHIFT 6
+#define NIC0_TXE0_WQE_CHECK_EN_SEND_SIZE_ZERO_EN_MASK 0x40
+#define NIC0_TXE0_WQE_CHECK_EN_RDV_WR_RD_SIZE_ZERO_EN_SHIFT 7
+#define NIC0_TXE0_WQE_CHECK_EN_RDV_WR_RD_SIZE_ZERO_EN_MASK 0x80
+#define NIC0_TXE0_WQE_CHECK_EN_WRITE_SEND_SIZE_2BIG_EN_SHIFT 8
+#define NIC0_TXE0_WQE_CHECK_EN_WRITE_SEND_SIZE_2BIG_EN_MASK 0x100
+#define NIC0_TXE0_WQE_CHECK_EN_STRIDE_SIZE_2BIG_EN_SHIFT 9
+#define NIC0_TXE0_WQE_CHECK_EN_STRIDE_SIZE_2BIG_EN_MASK 0x200
+#define NIC0_TXE0_WQE_CHECK_EN_RDV_REMOTE_LOG_SIZE_EN_SHIFT 10
+#define NIC0_TXE0_WQE_CHECK_EN_RDV_REMOTE_LOG_SIZE_EN_MASK 0x400
+#define NIC0_TXE0_WQE_CHECK_EN_RDV_WR_SIZE_BAD_EN_SHIFT 11
+#define NIC0_TXE0_WQE_CHECK_EN_RDV_WR_SIZE_BAD_EN_MASK 0x800
+#define NIC0_TXE0_WQE_CHECK_EN_RDV_RD_SIZE_BAD_EN_SHIFT 12
+#define NIC0_TXE0_WQE_CHECK_EN_RDV_RD_SIZE_BAD_EN_MASK 0x1000
+#define NIC0_TXE0_WQE_CHECK_EN_INLINE_SIZE_BAD_EN_SHIFT 13
+#define NIC0_TXE0_WQE_CHECK_EN_INLINE_SIZE_BAD_EN_MASK 0x2000
+#define NIC0_TXE0_WQE_CHECK_EN_GAUDI1_INLINE_VALID_EN_SHIFT 14
+#define NIC0_TXE0_WQE_CHECK_EN_GAUDI1_INLINE_VALID_EN_MASK 0x4000
+#define NIC0_TXE0_WQE_CHECK_EN_STRIDE_BAD_GRAN_EN_SHIFT 15
+#define NIC0_TXE0_WQE_CHECK_EN_STRIDE_BAD_GRAN_EN_MASK 0x8000
+#define NIC0_TXE0_WQE_CHECK_EN_WQE_RESERVED_NOT_ZERO_EN_SHIFT 16
+#define NIC0_TXE0_WQE_CHECK_EN_WQE_RESERVED_NOT_ZERO_EN_MASK 0x10000
+#define NIC0_TXE0_WQE_CHECK_EN_WQE_INDEX_EN_SHIFT 17
+#define NIC0_TXE0_WQE_CHECK_EN_WQE_INDEX_EN_MASK 0x20000
+#define NIC0_TXE0_WQE_CHECK_EN_STRIDE_WQE_SIZE_SMALL_EN_SHIFT 18
+#define NIC0_TXE0_WQE_CHECK_EN_STRIDE_WQE_SIZE_SMALL_EN_MASK 0x40000
+#define NIC0_TXE0_WQE_CHECK_EN_UPSCALE_ALIGN_EN_SHIFT 19
+#define NIC0_TXE0_WQE_CHECK_EN_UPSCALE_ALIGN_EN_MASK 0x80000
+#define NIC0_TXE0_WQE_CHECK_EN_UPSCALE_VALID_OPCODE_EN_SHIFT 20
+#define NIC0_TXE0_WQE_CHECK_EN_UPSCALE_VALID_OPCODE_EN_MASK 0x100000
+#define NIC0_TXE0_WQE_CHECK_EN_RAW_UNSUPPORTED_SIZE_EN_SHIFT 21
+#define NIC0_TXE0_WQE_CHECK_EN_RAW_UNSUPPORTED_SIZE_EN_MASK 0x200000
+#define NIC0_TXE0_WQE_CHECK_EN_RESERVED_SHIFT 22
+#define NIC0_TXE0_WQE_CHECK_EN_RESERVED_MASK 0xFFC00000
+
+/* NIC0_TXE0_WQE_CHECK_EN2 */
+#define NIC0_TXE0_WQE_CHECK_EN2_RESERVED_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_EN2_RESERVED_MASK 0x7FFF
+#define NIC0_TXE0_WQE_CHECK_EN2_QOS_INLINE_ERR_SHIFT 15
+#define NIC0_TXE0_WQE_CHECK_EN2_QOS_INLINE_ERR_MASK 0x8000
+#define NIC0_TXE0_WQE_CHECK_EN2_OPCODE_ABOVE_15_ERR_SHIFT 16
+#define NIC0_TXE0_WQE_CHECK_EN2_OPCODE_ABOVE_15_ERR_MASK 0x10000
+#define NIC0_TXE0_WQE_CHECK_EN2_RAW_ABOVE_MIN_RAW_UNSUPPO_SHIFT 17
+#define NIC0_TXE0_WQE_CHECK_EN2_RAW_ABOVE_MIN_RAW_UNSUPPO_MASK 0x20000
+#define NIC0_TXE0_WQE_CHECK_EN2_RAW_BELOW_MAX_RAW_UNSUPPO_SHIFT 18
+#define NIC0_TXE0_WQE_CHECK_EN2_RAW_BELOW_MAX_RAW_UNSUPPO_MASK 0x40000
+#define NIC0_TXE0_WQE_CHECK_EN2_DIS_REDUCTION_NOT_ZERO_ER_SHIFT 19
+#define NIC0_TXE0_WQE_CHECK_EN2_DIS_REDUCTION_NOT_ZERO_ER_MASK 0x80000
+#define NIC0_TXE0_WQE_CHECK_EN2_RDV_READ_AND_INLINE_ERR_SHIFT 20
+#define NIC0_TXE0_WQE_CHECK_EN2_RDV_READ_AND_INLINE_ERR_MASK 0x100000
+#define NIC0_TXE0_WQE_CHECK_EN2_RDV_FETCH_AND_INLINE_ERR_SHIFT 21
+#define NIC0_TXE0_WQE_CHECK_EN2_RDV_FETCH_AND_INLINE_ERR_MASK 0x200000
+#define NIC0_TXE0_WQE_CHECK_EN2_WQE_FETCH_WR_SIZE_NOT4_ER_SHIFT 22
+#define NIC0_TXE0_WQE_CHECK_EN2_WQE_FETCH_WR_SIZE_NOT4_ER_MASK 0x400000
+#define NIC0_TXE0_WQE_CHECK_EN2_WQE_FETCH_WR_ADDR_MOD4_ER_SHIFT 23
+#define NIC0_TXE0_WQE_CHECK_EN2_WQE_FETCH_WR_ADDR_MOD4_ER_MASK 0x800000
+#define NIC0_TXE0_WQE_CHECK_EN2_LAST_INDEX_RDV_ERR_SHIFT 24
+#define NIC0_TXE0_WQE_CHECK_EN2_LAST_INDEX_RDV_ERR_MASK 0x1000000
+#define NIC0_TXE0_WQE_CHECK_EN2_GUADI1_MULTI_DUAL_ERR_SHIFT 25
+#define NIC0_TXE0_WQE_CHECK_EN2_GUADI1_MULTI_DUAL_ERR_MASK 0x2000000
+#define NIC0_TXE0_WQE_CHECK_EN2_WQE_BAD_OPCODE_ERR_SHIFT 26
+#define NIC0_TXE0_WQE_CHECK_EN2_WQE_BAD_OPCODE_ERR_MASK 0x4000000
+#define NIC0_TXE0_WQE_CHECK_EN2_WQE_BAD_SIZE_ERR_SHIFT 27
+#define NIC0_TXE0_WQE_CHECK_EN2_WQE_BAD_SIZE_ERR_MASK 0x8000000
+#define NIC0_TXE0_WQE_CHECK_EN2_WQE_SE_NOT_RAW_SHIFT 28
+#define NIC0_TXE0_WQE_CHECK_EN2_WQE_SE_NOT_RAW_MASK 0x10000000
+#define NIC0_TXE0_WQE_CHECK_EN2_GAUDI1_TUNNEL_ERR_SHIFT 29
+#define NIC0_TXE0_WQE_CHECK_EN2_GAUDI1_TUNNEL_ERR_MASK 0x20000000
+#define NIC0_TXE0_WQE_CHECK_EN2_TUNNEL_ZERO_SIZE_ERR_SHIFT 30
+#define NIC0_TXE0_WQE_CHECK_EN2_TUNNEL_ZERO_SIZE_ERR_MASK 0x40000000
+#define NIC0_TXE0_WQE_CHECK_EN2_TUNNEL_MAX_SIZE_ERR_SHIFT 31
+#define NIC0_TXE0_WQE_CHECK_EN2_TUNNEL_MAX_SIZE_ERR_MASK 0x80000000
+
+/* NIC0_TXE0_WQE_CHECK_CFG1 */
+#define NIC0_TXE0_WQE_CHECK_CFG1_QPC_OPC_WR_WQE_TYPE_ERR_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_CFG1_QPC_OPC_WR_WQE_TYPE_ERR_MASK 0xFFFF
+#define NIC0_TXE0_WQE_CHECK_CFG1_QPC_OPC_RD_WQE_TYPE_ERR_SHIFT 16
+#define NIC0_TXE0_WQE_CHECK_CFG1_QPC_OPC_RD_WQE_TYPE_ERR_MASK 0xFFFF0000
+
+/* NIC0_TXE0_WQE_CHECK_CFG2 */
+#define NIC0_TXE0_WQE_CHECK_CFG2_ERR_WQE_OPCODE_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_CFG2_ERR_WQE_OPCODE_MASK 0xFFFF
+#define NIC0_TXE0_WQE_CHECK_CFG2_ERR_WQE_SIZE_OPCODE_EN_SHIFT 16
+#define NIC0_TXE0_WQE_CHECK_CFG2_ERR_WQE_SIZE_OPCODE_EN_MASK 0xFFFF0000
+
+/* NIC0_TXE0_WQE_CHECK_CFG3 */
+#define NIC0_TXE0_WQE_CHECK_CFG3_QPC_GAUDI1_WQE_TYPE_ERR_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_CFG3_QPC_GAUDI1_WQE_TYPE_ERR_MASK 0xFFFF
+#define NIC0_TXE0_WQE_CHECK_CFG3_UPSCALE_WQE_TYPE_ERR_SHIFT 16
+#define NIC0_TXE0_WQE_CHECK_CFG3_UPSCALE_WQE_TYPE_ERR_MASK 0xFFFF0000
+
+/* NIC0_TXE0_WQE_CHECK_CONST1 */
+#define NIC0_TXE0_WQE_CHECK_CONST1_WRITE_SEND_MAX_SIZE_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_CONST1_WRITE_SEND_MAX_SIZE_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_CHECK_CONST2 */
+#define NIC0_TXE0_WQE_CHECK_CONST2_STRIDE_MAX_WQE_SIZE_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_CONST2_STRIDE_MAX_WQE_SIZE_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_CHECK_CONST3 */
+#define NIC0_TXE0_WQE_CHECK_CONST3_RDV_GRAN1_WQE_SIZE_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_CONST3_RDV_GRAN1_WQE_SIZE_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_CHECK_CONST4 */
+#define NIC0_TXE0_WQE_CHECK_CONST4_RDV_GRAN0_WQE_SIZE_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_CONST4_RDV_GRAN0_WQE_SIZE_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_CHECK_CONST5 */
+#define NIC0_TXE0_WQE_CHECK_CONST5_INL_GRAN1_WQE_SIZE_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_CONST5_INL_GRAN1_WQE_SIZE_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_CHECK_CONST6 */
+#define NIC0_TXE0_WQE_CHECK_CONST6_INL_GRAN0_WQE_SIZE_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_CONST6_INL_GRAN0_WQE_SIZE_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_CHECK_CONST7 */
+#define NIC0_TXE0_WQE_CHECK_CONST7_ERR_WQE_SIZE_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_CONST7_ERR_WQE_SIZE_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_SOURCE_IP_PORT0 */
+#define NIC0_TXE0_SOURCE_IP_PORT0_SOURCE_IP_SHIFT 0
+#define NIC0_TXE0_SOURCE_IP_PORT0_SOURCE_IP_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_SOURCE_IP_PORT1 */
+#define NIC0_TXE0_SOURCE_IP_PORT1_SOURCE_IP_SHIFT 0
+#define NIC0_TXE0_SOURCE_IP_PORT1_SOURCE_IP_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_BTH_RSVD */
+#define NIC0_TXE0_BTH_RSVD_REQ_RSVD2_SHIFT 0
+#define NIC0_TXE0_BTH_RSVD_REQ_RSVD2_MASK 0x3
+#define NIC0_TXE0_BTH_RSVD_REQ_RSVD6_SHIFT 2
+#define NIC0_TXE0_BTH_RSVD_REQ_RSVD6_MASK 0xFC
+#define NIC0_TXE0_BTH_RSVD_RES_RSVD2_SHIFT 8
+#define NIC0_TXE0_BTH_RSVD_RES_RSVD2_MASK 0x300
+#define NIC0_TXE0_BTH_RSVD_RES_RSVD6_SHIFT 10
+#define NIC0_TXE0_BTH_RSVD_RES_RSVD6_MASK 0xFC00
+#define NIC0_TXE0_BTH_RSVD_RES_RSVD7_SHIFT 16
+#define NIC0_TXE0_BTH_RSVD_RES_RSVD7_MASK 0x7F0000
+#define NIC0_TXE0_BTH_RSVD_RES_SOB_EN_SHIFT 23
+#define NIC0_TXE0_BTH_RSVD_RES_SOB_EN_MASK 0x800000
+#define NIC0_TXE0_BTH_RSVD_RES_LEG_SOB_EN_SHIFT 24
+#define NIC0_TXE0_BTH_RSVD_RES_LEG_SOB_EN_MASK 0x1000000
+#define NIC0_TXE0_BTH_RSVD_RES_CI_VALID_SHIFT 25
+#define NIC0_TXE0_BTH_RSVD_RES_CI_VALID_MASK 0x2000000
+
+/* NIC0_TXE0_MULTI_PKT_WQE */
+#define NIC0_TXE0_MULTI_PKT_WQE_ACKREQ_ON_LAST_PKT_SHIFT 0
+#define NIC0_TXE0_MULTI_PKT_WQE_ACKREQ_ON_LAST_PKT_MASK 0x1
+#define NIC0_TXE0_MULTI_PKT_WQE_QP_LIMIT_CC_GUARD_SHIFT 8
+#define NIC0_TXE0_MULTI_PKT_WQE_QP_LIMIT_CC_GUARD_MASK 0xF00
+#define NIC0_TXE0_MULTI_PKT_WQE_RDV_REMOTE_BUF_GUARD_SHIFT 12
+#define NIC0_TXE0_MULTI_PKT_WQE_RDV_REMOTE_BUF_GUARD_MASK 0xF000
+#define NIC0_TXE0_MULTI_PKT_WQE_RDV_QUARTER_GUARD_SHIFT 16
+#define NIC0_TXE0_MULTI_PKT_WQE_RDV_QUARTER_GUARD_MASK 0xF0000
+
+/* NIC0_TXE0_TXWQC */
+#define NIC0_TXE0_TXWQC_EN_SHIFT 0
+#define NIC0_TXE0_TXWQC_EN_MASK 0x1
+#define NIC0_TXE0_TXWQC_PRIO_BASED_EVICTION_EN_SHIFT 1
+#define NIC0_TXE0_TXWQC_PRIO_BASED_EVICTION_EN_MASK 0x2
+
+/* NIC0_TXE0_TXWQC_STATUS */
+#define NIC0_TXE0_TXWQC_STATUS_INVALIDATE_DONE_SHIFT 0
+#define NIC0_TXE0_TXWQC_STATUS_INVALIDATE_DONE_MASK 0x1
+#define NIC0_TXE0_TXWQC_STATUS_CACHE_WR_IDLE_SHIFT 1
+#define NIC0_TXE0_TXWQC_STATUS_CACHE_WR_IDLE_MASK 0x2
+#define NIC0_TXE0_TXWQC_STATUS_CACHE_RD_IDLE_SHIFT 2
+#define NIC0_TXE0_TXWQC_STATUS_CACHE_RD_IDLE_MASK 0x4
+#define NIC0_TXE0_TXWQC_STATUS_CACHE_USED_ENTRY_SHIFT 8
+#define NIC0_TXE0_TXWQC_STATUS_CACHE_USED_ENTRY_MASK 0xFF00
+#define NIC0_TXE0_TXWQC_STATUS_CACHE_STATS_SHIFT 16
+#define NIC0_TXE0_TXWQC_STATUS_CACHE_STATS_MASK 0x3F0000
+
+/* NIC0_TXE0_TXWQC_INVALIDATE */
+#define NIC0_TXE0_TXWQC_INVALIDATE_INVALIDATE_SC_SHIFT 0
+#define NIC0_TXE0_TXWQC_INVALIDATE_INVALIDATE_SC_MASK 0x1
+
+/* NIC0_TXE0_STATS_CFG0 */
+#define NIC0_TXE0_STATS_CFG0_MEAS_WIN_SIZE_SHIFT 0
+#define NIC0_TXE0_STATS_CFG0_MEAS_WIN_SIZE_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_STATS_CFG1 */
+#define NIC0_TXE0_STATS_CFG1_TOT_TYPE_SHIFT 0
+#define NIC0_TXE0_STATS_CFG1_TOT_TYPE_MASK 0x3
+#define NIC0_TXE0_STATS_CFG1_WIN_TYPE_SHIFT 4
+#define NIC0_TXE0_STATS_CFG1_WIN_TYPE_MASK 0x30
+#define NIC0_TXE0_STATS_CFG1_ENABLE_SHIFT 8
+#define NIC0_TXE0_STATS_CFG1_ENABLE_MASK 0x100
+#define NIC0_TXE0_STATS_CFG1_WIN_SAMP_LATENCY_SHIFT 9
+#define NIC0_TXE0_STATS_CFG1_WIN_SAMP_LATENCY_MASK 0x200
+#define NIC0_TXE0_STATS_CFG1_IGNORE_MIN_ZERO_SHIFT 10
+#define NIC0_TXE0_STATS_CFG1_IGNORE_MIN_ZERO_MASK 0x400
+#define NIC0_TXE0_STATS_CFG1_LATENCY_ENABLE_SHIFT 11
+#define NIC0_TXE0_STATS_CFG1_LATENCY_ENABLE_MASK 0x800
+#define NIC0_TXE0_STATS_CFG1_CLEAR_SC_SHIFT 31
+#define NIC0_TXE0_STATS_CFG1_CLEAR_SC_MASK 0x80000000
+
+/* NIC0_TXE0_STATS_CFG2 */
+#define NIC0_TXE0_STATS_CFG2_LATENCY_MAX_VAL_SHIFT 0
+#define NIC0_TXE0_STATS_CFG2_LATENCY_MAX_VAL_MASK 0xFFFF
+#define NIC0_TXE0_STATS_CFG2_LATENCY_WRAP_EN_SHIFT 16
+#define NIC0_TXE0_STATS_CFG2_LATENCY_WRAP_EN_MASK 0x10000
+
+/* NIC0_TXE0_STATS_TOT_BYTES_LSB */
+#define NIC0_TXE0_STATS_TOT_BYTES_LSB_R_SHIFT 0
+#define NIC0_TXE0_STATS_TOT_BYTES_LSB_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_STATS_TOT_BYTES_MSB */
+#define NIC0_TXE0_STATS_TOT_BYTES_MSB_R_SHIFT 0
+#define NIC0_TXE0_STATS_TOT_BYTES_MSB_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_STATS_TOT_PKTS_LSB */
+#define NIC0_TXE0_STATS_TOT_PKTS_LSB_R_SHIFT 0
+#define NIC0_TXE0_STATS_TOT_PKTS_LSB_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_STATS_TOT_PKTS_MSB */
+#define NIC0_TXE0_STATS_TOT_PKTS_MSB_R_SHIFT 0
+#define NIC0_TXE0_STATS_TOT_PKTS_MSB_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_STATS_MEAS_WIN_BYTES_LSB */
+#define NIC0_TXE0_STATS_MEAS_WIN_BYTES_LSB_R_SHIFT 0
+#define NIC0_TXE0_STATS_MEAS_WIN_BYTES_LSB_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_STATS_MEAS_WIN_BYTES_MSB */
+#define NIC0_TXE0_STATS_MEAS_WIN_BYTES_MSB_R_SHIFT 0
+#define NIC0_TXE0_STATS_MEAS_WIN_BYTES_MSB_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_STATS_MEAS_WIN_PKTS */
+#define NIC0_TXE0_STATS_MEAS_WIN_PKTS_R_SHIFT 0
+#define NIC0_TXE0_STATS_MEAS_WIN_PKTS_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_STATS_MEAS_LATENCY */
+#define NIC0_TXE0_STATS_MEAS_LATENCY_ERROR_CNTR_SHIFT 0
+#define NIC0_TXE0_STATS_MEAS_LATENCY_ERROR_CNTR_MASK 0xFFFF
+
+/* NIC0_TXE0_HW_EVENT_CFG */
+#define NIC0_TXE0_HW_EVENT_CFG_EVENT_ID_SHIFT 0
+#define NIC0_TXE0_HW_EVENT_CFG_EVENT_ID_MASK 0xFFFF
+#define NIC0_TXE0_HW_EVENT_CFG_DBG_SELECT0_SHIFT 16
+#define NIC0_TXE0_HW_EVENT_CFG_DBG_SELECT0_MASK 0xF0000
+#define NIC0_TXE0_HW_EVENT_CFG_DBG_SELECT1_SHIFT 20
+#define NIC0_TXE0_HW_EVENT_CFG_DBG_SELECT1_MASK 0xF00000
+#define NIC0_TXE0_HW_EVENT_CFG_DBG_SELECT2_SHIFT 24
+#define NIC0_TXE0_HW_EVENT_CFG_DBG_SELECT2_MASK 0xF000000
+
+/* NIC0_TXE0_ENCAP_CFG */
+#define NIC0_TXE0_ENCAP_CFG_IPV4_PROTOCOL_UDP_DEST_SHIFT 0
+#define NIC0_TXE0_ENCAP_CFG_IPV4_PROTOCOL_UDP_DEST_MASK 0xFFFF
+#define NIC0_TXE0_ENCAP_CFG_ENCAP_SIZE_SHIFT 24
+#define NIC0_TXE0_ENCAP_CFG_ENCAP_SIZE_MASK 0xF000000
+#define NIC0_TXE0_ENCAP_CFG_HDR_FORMAT_SHIFT 28
+#define NIC0_TXE0_ENCAP_CFG_HDR_FORMAT_MASK 0x10000000
+
+/* NIC0_TXE0_ENCAP_DATA_31_0 */
+#define NIC0_TXE0_ENCAP_DATA_31_0_R_SHIFT 0
+#define NIC0_TXE0_ENCAP_DATA_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_ENCAP_DATA_63_32 */
+#define NIC0_TXE0_ENCAP_DATA_63_32_R_SHIFT 0
+#define NIC0_TXE0_ENCAP_DATA_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_ENCAP_DATA_95_64 */
+#define NIC0_TXE0_ENCAP_DATA_95_64_R_SHIFT 0
+#define NIC0_TXE0_ENCAP_DATA_95_64_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_ENCAP_DATA_127_96 */
+#define NIC0_TXE0_ENCAP_DATA_127_96_R_SHIFT 0
+#define NIC0_TXE0_ENCAP_DATA_127_96_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_ENCAP_DATA_159_128 */
+#define NIC0_TXE0_ENCAP_DATA_159_128_R_SHIFT 0
+#define NIC0_TXE0_ENCAP_DATA_159_128_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_ENCAP_DATA_191_160 */
+#define NIC0_TXE0_ENCAP_DATA_191_160_R_SHIFT 0
+#define NIC0_TXE0_ENCAP_DATA_191_160_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_ENCAP_DATA_223_192 */
+#define NIC0_TXE0_ENCAP_DATA_223_192_R_SHIFT 0
+#define NIC0_TXE0_ENCAP_DATA_223_192_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_ENCAP_DATA_255_224 */
+#define NIC0_TXE0_ENCAP_DATA_255_224_R_SHIFT 0
+#define NIC0_TXE0_ENCAP_DATA_255_224_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_ENCAP_CFG2 */
+#define NIC0_TXE0_ENCAP_CFG2_CHECKSUM_SHIFT 0
+#define NIC0_TXE0_ENCAP_CFG2_CHECKSUM_MASK 0xFFFF
+#define NIC0_TXE0_ENCAP_CFG2_MASK_S_PORT_SHIFT 16
+#define NIC0_TXE0_ENCAP_CFG2_MASK_S_PORT_MASK 0xFFFF0000
+
+/* NIC0_TXE0_MTD_DUAL_STRIDE3 */
+#define NIC0_TXE0_MTD_DUAL_STRIDE3_R_SHIFT 0
+#define NIC0_TXE0_MTD_DUAL_STRIDE3_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_MTD_DUAL_STRIDE4 */
+#define NIC0_TXE0_MTD_DUAL_STRIDE4_R_SHIFT 0
+#define NIC0_TXE0_MTD_DUAL_STRIDE4_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_MTD_DUAL_NUM_OF_STRIDES */
+#define NIC0_TXE0_MTD_DUAL_NUM_OF_STRIDES_R3_SHIFT 0
+#define NIC0_TXE0_MTD_DUAL_NUM_OF_STRIDES_R3_MASK 0xFFFF
+#define NIC0_TXE0_MTD_DUAL_NUM_OF_STRIDES_R4_SHIFT 16
+#define NIC0_TXE0_MTD_DUAL_NUM_OF_STRIDES_R4_MASK 0xFFFF0000
+
+/* NIC0_TXE0_CLK_GATE_CFG */
+#define NIC0_TXE0_CLK_GATE_CFG_CLOSE_DELAY_SHIFT 0
+#define NIC0_TXE0_CLK_GATE_CFG_CLOSE_DELAY_MASK 0x3FFFFFFF
+#define NIC0_TXE0_CLK_GATE_CFG_CGM_DIS_SHIFT 30
+#define NIC0_TXE0_CLK_GATE_CFG_CGM_DIS_MASK 0x40000000
+#define NIC0_TXE0_CLK_GATE_CFG_FORCE_OPEN_SHIFT 31
+#define NIC0_TXE0_CLK_GATE_CFG_FORCE_OPEN_MASK 0x80000000
+
+/* NIC0_TXE0_WQE_CHECK_NOTIFY_EN */
+#define NIC0_TXE0_WQE_CHECK_NOTIFY_EN_BUS_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_NOTIFY_EN_BUS_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_CHECK_NOTIFY_EN2 */
+#define NIC0_TXE0_WQE_CHECK_NOTIFY_EN2_BUS_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_NOTIFY_EN2_BUS_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_CHECK_CFG4 */
+#define NIC0_TXE0_WQE_CHECK_CFG4_MIN_RAW_UNSUPPORTED_SIZE_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_CFG4_MIN_RAW_UNSUPPORTED_SIZE_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_CHECK_CFG5 */
+#define NIC0_TXE0_WQE_CHECK_CFG5_MAX_RAW_UNSUPPORTED_SIZE_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_CFG5_MAX_RAW_UNSUPPORTED_SIZE_MASK 0xFFFFFFFF
+
+/* NIC0_TXE0_WQE_CHECK_CFG6 */
+#define NIC0_TXE0_WQE_CHECK_CFG6_QPC_OPC_RDV_WQE_TYPE_ERR_SHIFT 0
+#define NIC0_TXE0_WQE_CHECK_CFG6_QPC_OPC_RDV_WQE_TYPE_ERR_MASK 0xFFFF
+#define NIC0_TXE0_WQE_CHECK_CFG6_MIN_REMOTE_LOG_SIZE_SHIFT 16
+#define NIC0_TXE0_WQE_CHECK_CFG6_MIN_REMOTE_LOG_SIZE_MASK 0x1F0000
+
+/* NIC0_TXE0_DATA_READ_RL_CFG */
+#define NIC0_TXE0_DATA_READ_RL_CFG_EN_SHIFT 0
+#define NIC0_TXE0_DATA_READ_RL_CFG_EN_MASK 0x1
+#define NIC0_TXE0_DATA_READ_RL_CFG_SATURATION_SHIFT 8
+#define NIC0_TXE0_DATA_READ_RL_CFG_SATURATION_MASK 0xFF00
+#define NIC0_TXE0_DATA_READ_RL_CFG_RST_TOKEN_SHIFT 16
+#define NIC0_TXE0_DATA_READ_RL_CFG_RST_TOKEN_MASK 0xFF0000
+#define NIC0_TXE0_DATA_READ_RL_CFG_TIMEOUT_SHIFT 24
+#define NIC0_TXE0_DATA_READ_RL_CFG_TIMEOUT_MASK 0xFF000000
+
+#endif /* ASIC_REG_NIC0_TXE0_MASKS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txe0_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txe0_regs.h
new file mode 100644
index 000000000000..52c8b58781cd
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txe0_regs.h
@@ -0,0 +1,529 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_TXE0_REGS_H_
+#define ASIC_REG_NIC0_TXE0_REGS_H_
+
+/*****************************************
+ * NIC0_TXE0
+ * (Prototype: NIC_TXE)
+ *****************************************
+ */
+
+#define NIC0_TXE0_WQE_FETCH_REQ_MASK_31_0 0x5452000
+
+#define NIC0_TXE0_WQE_FETCH_REQ_MASK_47_32 0x5452004
+
+#define NIC0_TXE0_LOCAL_WQ_BUFFER_SIZE 0x5452008
+
+#define NIC0_TXE0_LOCAL_WQ_LINE_SIZE 0x545200C
+
+#define NIC0_TXE0_LOG_MAX_WQ_SIZE_0 0x5452010
+
+#define NIC0_TXE0_LOG_MAX_WQ_SIZE_1 0x5452014
+
+#define NIC0_TXE0_LOG_MAX_WQ_SIZE_2 0x5452018
+
+#define NIC0_TXE0_LOG_MAX_WQ_SIZE_3 0x545201C
+
+#define NIC0_TXE0_SQ_BASE_ADDRESS_63_32_0 0x5452020
+
+#define NIC0_TXE0_SQ_BASE_ADDRESS_63_32_1 0x5452024
+
+#define NIC0_TXE0_SQ_BASE_ADDRESS_63_32_2 0x5452028
+
+#define NIC0_TXE0_SQ_BASE_ADDRESS_63_32_3 0x545202C
+
+#define NIC0_TXE0_SQ_BASE_ADDRESS_31_0_0 0x5452030
+
+#define NIC0_TXE0_SQ_BASE_ADDRESS_31_0_1 0x5452034
+
+#define NIC0_TXE0_SQ_BASE_ADDRESS_31_0_2 0x5452038
+
+#define NIC0_TXE0_SQ_BASE_ADDRESS_31_0_3 0x545203C
+
+#define NIC0_TXE0_WQE_USER_CFG 0x5452040
+
+#define NIC0_TXE0_ALLOC_CREDIT 0x5452044
+
+#define NIC0_TXE0_ALLOC_CREDIT_FORCE_FULL 0x5452048
+
+#define NIC0_TXE0_READ_CREDIT 0x545204C
+
+#define NIC0_TXE0_READ_CREDIT_FORCE_FULL 0x5452050
+
+#define NIC0_TXE0_BURST_ENABLE 0x5452054
+
+#define NIC0_TXE0_WR_INIT_BUSY 0x5452058
+
+#define NIC0_TXE0_READ_RES_WT_INIT_BUSY 0x545205C
+
+#define NIC0_TXE0_BTH_TVER 0x5452060
+
+#define NIC0_TXE0_IPV4_IDENTIFICATION 0x5452064
+
+#define NIC0_TXE0_IPV4_FLAGS 0x5452068
+
+#define NIC0_TXE0_PAD 0x545206C
+
+#define NIC0_TXE0_ADD_PAD_TO_IPV4_LEN 0x5452070
+
+#define NIC0_TXE0_ADD_PAD_TO_UDP_LEN 0x5452074
+
+#define NIC0_TXE0_ICRC_EN 0x5452078
+
+#define NIC0_TXE0_UDP_MASK_S_PORT 0x545207C
+
+#define NIC0_TXE0_UDP_CHECKSUM 0x5452080
+
+#define NIC0_TXE0_UDP_DEST_PORT 0x5452084
+
+#define NIC0_TXE0_PORT0_MAC_CFG_47_32 0x5452088
+
+#define NIC0_TXE0_PORT0_MAC_CFG_31_0 0x545208C
+
+#define NIC0_TXE0_PORT1_MAC_CFG_47_32 0x5452090
+
+#define NIC0_TXE0_PORT1_MAC_CFG_31_0 0x5452094
+
+#define NIC0_TXE0_PRIO_TO_DSCP_0 0x545209C
+
+#define NIC0_TXE0_PRIO_TO_DSCP_1 0x54520A0
+
+#define NIC0_TXE0_PRIO_TO_PCP 0x54520B0
+
+#define NIC0_TXE0_MAC_ETHER_TYPE 0x54520B4
+
+#define NIC0_TXE0_MAC_ETHER_TYPE_VLAN 0x54520B8
+
+#define NIC0_TXE0_ECN_0 0x54520BC
+
+#define NIC0_TXE0_ECN_1 0x54520C0
+
+#define NIC0_TXE0_IPV4_TIME_TO_LIVE_0 0x54520C4
+
+#define NIC0_TXE0_IPV4_TIME_TO_LIVE_1 0x54520C8
+
+#define NIC0_TXE0_PRIO_PORT_CREDIT_FORCE 0x54520CC
+
+#define NIC0_TXE0_PRIO_PORT_CRDIT_0 0x54520D0
+
+#define NIC0_TXE0_PRIO_PORT_CRDIT_1 0x54520D4
+
+#define NIC0_TXE0_PRIO_PORT_CRDIT_2 0x54520D8
+
+#define NIC0_TXE0_PRIO_PORT_CRDIT_3 0x54520DC
+
+#define NIC0_TXE0_PRIO_PORT_CRDIT_4 0x54520E0
+
+#define NIC0_TXE0_PRIO_PORT_CRDIT_5 0x54520E4
+
+#define NIC0_TXE0_PRIO_PORT_CRDIT_6 0x54520E8
+
+#define NIC0_TXE0_PRIO_PORT_CRDIT_7 0x54520EC
+
+#define NIC0_TXE0_WQE_FETCH_TOKEN_EN 0x54520F0
+
+#define NIC0_TXE0_NACK_SYNDROME 0x54520F4
+
+#define NIC0_TXE0_WQE_FETCH_AXI_PROT 0x54520FC
+
+#define NIC0_TXE0_DATA_FETCH_AXI_PROT 0x5452104
+
+#define NIC0_TXE0_FETCH_OUT_OF_TOKEN 0x5452108
+
+#define NIC0_TXE0_ECN_COUNT_EN 0x545210C
+
+#define NIC0_TXE0_INERRUPT_CAUSE 0x5452110
+
+#define NIC0_TXE0_INTERRUPT_MASK 0x5452114
+
+#define NIC0_TXE0_INTERRUPT_CLR 0x5452118
+
+#define NIC0_TXE0_VLAN_TAG_QPN_OFFSET 0x545211C
+
+#define NIC0_TXE0_VALN_TAG_CFG_0 0x5452120
+
+#define NIC0_TXE0_VALN_TAG_CFG_1 0x5452124
+
+#define NIC0_TXE0_VALN_TAG_CFG_2 0x5452128
+
+#define NIC0_TXE0_VALN_TAG_CFG_3 0x545212C
+
+#define NIC0_TXE0_VALN_TAG_CFG_4 0x5452130
+
+#define NIC0_TXE0_VALN_TAG_CFG_5 0x5452134
+
+#define NIC0_TXE0_VALN_TAG_CFG_6 0x5452138
+
+#define NIC0_TXE0_VALN_TAG_CFG_7 0x545213C
+
+#define NIC0_TXE0_VALN_TAG_CFG_8 0x5452140
+
+#define NIC0_TXE0_VALN_TAG_CFG_9 0x5452144
+
+#define NIC0_TXE0_VALN_TAG_CFG_10 0x5452148
+
+#define NIC0_TXE0_VALN_TAG_CFG_11 0x545214C
+
+#define NIC0_TXE0_VALN_TAG_CFG_12 0x5452150
+
+#define NIC0_TXE0_VALN_TAG_CFG_13 0x5452154
+
+#define NIC0_TXE0_VALN_TAG_CFG_14 0x5452158
+
+#define NIC0_TXE0_VALN_TAG_CFG_15 0x545215C
+
+#define NIC0_TXE0_DBG_TRIG 0x5452160
+
+#define NIC0_TXE0_WQE_PREFETCH_CFG 0x5452164
+
+#define NIC0_TXE0_WQE_PREFETCH_INVALIDATE 0x5452168
+
+#define NIC0_TXE0_SWAP_MEMORY_ENDIANNESS 0x545216C
+
+#define NIC0_TXE0_WQE_FETCH_SLICE_47_32 0x5452170
+
+#define NIC0_TXE0_WQE_FETCH_SLICE_31_0 0x5452174
+
+#define NIC0_TXE0_WQE_EXE_SLICE_47_32 0x5452178
+
+#define NIC0_TXE0_WQE_EXE_SLICE_31_0 0x545217C
+
+#define NIC0_TXE0_DBG_COUNT_SELECT0 0x5452180
+
+#define NIC0_TXE0_DBG_COUNT_SELECT1 0x5452184
+
+#define NIC0_TXE0_DBG_COUNT_SELECT2 0x5452188
+
+#define NIC0_TXE0_DBG_COUNT_SELECT3 0x545218C
+
+#define NIC0_TXE0_DBG_COUNT_SELECT4 0x5452190
+
+#define NIC0_TXE0_DBG_COUNT_SELECT5 0x5452194
+
+#define NIC0_TXE0_DBG_COUNT_SELECT6 0x5452198
+
+#define NIC0_TXE0_DBG_COUNT_SELECT7 0x545219C
+
+#define NIC0_TXE0_DBG_COUNT_SELECT8 0x54521A0
+
+#define NIC0_TXE0_DBG_COUNT_SELECT9 0x54521A4
+
+#define NIC0_TXE0_DBG_COUNT_SELECT10 0x54521A8
+
+#define NIC0_TXE0_DBG_COUNT_SELECT11 0x54521AC
+
+#define NIC0_TXE0_BTH_MKEY 0x54521B0
+
+#define NIC0_TXE0_WQE_BUFF_FLUSH_SLICE_47_3 0x54521B4
+
+#define NIC0_TXE0_WQE_BUFF_FLUSH_SLICE_31_0 0x54521B8
+
+#define NIC0_TXE0_INTERRUPT_INDEX_MASK_RING_0 0x54521BC
+
+#define NIC0_TXE0_INTERRUPT_INDEX_MASK_RING_1 0x54521C0
+
+#define NIC0_TXE0_INTERRUPT_INDEX_MASK_RING_2 0x54521C4
+
+#define NIC0_TXE0_INTERRUPT_INDEX_MASK_RING_3 0x54521C8
+
+#define NIC0_TXE0_INTERRUPT_INDEX_MASK_RING_4 0x54521CC
+
+#define NIC0_TXE0_QPN_RING_0 0x54521D0
+
+#define NIC0_TXE0_QPN_RING_1 0x54521D4
+
+#define NIC0_TXE0_QPN_RING_2 0x54521D8
+
+#define NIC0_TXE0_QPN_RING_3 0x54521DC
+
+#define NIC0_TXE0_INTERRUPT_EACH_PACKET 0x54521F0
+
+#define NIC0_TXE0_EXECUTIN_INDEX_RING_0 0x54521F4
+
+#define NIC0_TXE0_EXECUTIN_INDEX_RING_1 0x54521F8
+
+#define NIC0_TXE0_EXECUTIN_INDEX_RING_2 0x54521FC
+
+#define NIC0_TXE0_EXECUTIN_INDEX_RING_3 0x5452200
+
+#define NIC0_TXE0_WQE_FETCH_AXI_USER_LO 0x5452208
+
+#define NIC0_TXE0_WQE_FETCH_AXI_USER_HI 0x545220C
+
+#define NIC0_TXE0_DATA_FETCH_AXI_USER_LO 0x5452210
+
+#define NIC0_TXE0_DATA_FETCH_AXI_USER_HI 0x5452214
+
+#define NIC0_TXE0_CHICKEN_BITS 0x5452218
+
+#define NIC0_TXE0_CHICKEN_BITS2 0x545221C
+
+#define NIC0_TXE0_WQE_CHECK_EN 0x5452220
+
+#define NIC0_TXE0_WQE_CHECK_EN2 0x5452224
+
+#define NIC0_TXE0_WQE_CHECK_CFG1 0x5452228
+
+#define NIC0_TXE0_WQE_CHECK_CFG2 0x545222C
+
+#define NIC0_TXE0_WQE_CHECK_CFG3 0x5452230
+
+#define NIC0_TXE0_WQE_CHECK_CONST1 0x5452234
+
+#define NIC0_TXE0_WQE_CHECK_CONST2 0x5452238
+
+#define NIC0_TXE0_WQE_CHECK_CONST3 0x545223C
+
+#define NIC0_TXE0_WQE_CHECK_CONST4 0x5452240
+
+#define NIC0_TXE0_WQE_CHECK_CONST5 0x5452244
+
+#define NIC0_TXE0_WQE_CHECK_CONST6 0x5452248
+
+#define NIC0_TXE0_WQE_CHECK_CONST7 0x545224C
+
+#define NIC0_TXE0_SOURCE_IP_PORT0_0 0x5452250
+
+#define NIC0_TXE0_SOURCE_IP_PORT0_1 0x5452254
+
+#define NIC0_TXE0_SOURCE_IP_PORT0_2 0x5452258
+
+#define NIC0_TXE0_SOURCE_IP_PORT0_3 0x545225C
+
+#define NIC0_TXE0_SOURCE_IP_PORT0_4 0x5452260
+
+#define NIC0_TXE0_SOURCE_IP_PORT0_5 0x5452264
+
+#define NIC0_TXE0_SOURCE_IP_PORT0_6 0x5452268
+
+#define NIC0_TXE0_SOURCE_IP_PORT0_7 0x545226C
+
+#define NIC0_TXE0_SOURCE_IP_PORT1_0 0x5452270
+
+#define NIC0_TXE0_SOURCE_IP_PORT1_1 0x5452274
+
+#define NIC0_TXE0_SOURCE_IP_PORT1_2 0x5452278
+
+#define NIC0_TXE0_SOURCE_IP_PORT1_3 0x545227C
+
+#define NIC0_TXE0_SOURCE_IP_PORT1_4 0x5452280
+
+#define NIC0_TXE0_SOURCE_IP_PORT1_5 0x5452284
+
+#define NIC0_TXE0_SOURCE_IP_PORT1_6 0x5452288
+
+#define NIC0_TXE0_SOURCE_IP_PORT1_7 0x545228C
+
+#define NIC0_TXE0_BTH_RSVD 0x5452290
+
+#define NIC0_TXE0_MULTI_PKT_WQE 0x5452294
+
+#define NIC0_TXE0_TXWQC 0x54522A0
+
+#define NIC0_TXE0_TXWQC_STATUS 0x54522A4
+
+#define NIC0_TXE0_TXWQC_INVALIDATE 0x54522A8
+
+#define NIC0_TXE0_STATS_CFG0 0x54522B0
+
+#define NIC0_TXE0_STATS_CFG1 0x54522B4
+
+#define NIC0_TXE0_STATS_CFG2 0x54522B8
+
+#define NIC0_TXE0_STATS_TOT_BYTES_LSB 0x54522C0
+
+#define NIC0_TXE0_STATS_TOT_BYTES_MSB 0x54522C4
+
+#define NIC0_TXE0_STATS_TOT_PKTS_LSB 0x54522C8
+
+#define NIC0_TXE0_STATS_TOT_PKTS_MSB 0x54522CC
+
+#define NIC0_TXE0_STATS_MEAS_WIN_BYTES_LSB 0x54522D0
+
+#define NIC0_TXE0_STATS_MEAS_WIN_BYTES_MSB 0x54522D4
+
+#define NIC0_TXE0_STATS_MEAS_WIN_PKTS 0x54522D8
+
+#define NIC0_TXE0_STATS_MEAS_LATENCY 0x54522DC
+
+#define NIC0_TXE0_HW_EVENT_CFG 0x54522E0
+
+#define NIC0_TXE0_ENCAP_CFG_0 0x5452300
+
+#define NIC0_TXE0_ENCAP_CFG_1 0x5452304
+
+#define NIC0_TXE0_ENCAP_CFG_2 0x5452308
+
+#define NIC0_TXE0_ENCAP_CFG_3 0x545230C
+
+#define NIC0_TXE0_ENCAP_CFG_4 0x5452310
+
+#define NIC0_TXE0_ENCAP_CFG_5 0x5452314
+
+#define NIC0_TXE0_ENCAP_CFG_6 0x5452318
+
+#define NIC0_TXE0_ENCAP_CFG_7 0x545231C
+
+#define NIC0_TXE0_ENCAP_DATA_31_0_0 0x5452320
+
+#define NIC0_TXE0_ENCAP_DATA_31_0_1 0x5452324
+
+#define NIC0_TXE0_ENCAP_DATA_31_0_2 0x5452328
+
+#define NIC0_TXE0_ENCAP_DATA_31_0_3 0x545232C
+
+#define NIC0_TXE0_ENCAP_DATA_31_0_4 0x5452330
+
+#define NIC0_TXE0_ENCAP_DATA_31_0_5 0x5452334
+
+#define NIC0_TXE0_ENCAP_DATA_31_0_6 0x5452338
+
+#define NIC0_TXE0_ENCAP_DATA_31_0_7 0x545233C
+
+#define NIC0_TXE0_ENCAP_DATA_63_32_0 0x5452340
+
+#define NIC0_TXE0_ENCAP_DATA_63_32_1 0x5452344
+
+#define NIC0_TXE0_ENCAP_DATA_63_32_2 0x5452348
+
+#define NIC0_TXE0_ENCAP_DATA_63_32_3 0x545234C
+
+#define NIC0_TXE0_ENCAP_DATA_63_32_4 0x5452350
+
+#define NIC0_TXE0_ENCAP_DATA_63_32_5 0x5452354
+
+#define NIC0_TXE0_ENCAP_DATA_63_32_6 0x5452358
+
+#define NIC0_TXE0_ENCAP_DATA_63_32_7 0x545235C
+
+#define NIC0_TXE0_ENCAP_DATA_95_64_0 0x5452360
+
+#define NIC0_TXE0_ENCAP_DATA_95_64_1 0x5452364
+
+#define NIC0_TXE0_ENCAP_DATA_95_64_2 0x5452368
+
+#define NIC0_TXE0_ENCAP_DATA_95_64_3 0x545236C
+
+#define NIC0_TXE0_ENCAP_DATA_95_64_4 0x5452370
+
+#define NIC0_TXE0_ENCAP_DATA_95_64_5 0x5452374
+
+#define NIC0_TXE0_ENCAP_DATA_95_64_6 0x5452378
+
+#define NIC0_TXE0_ENCAP_DATA_95_64_7 0x545237C
+
+#define NIC0_TXE0_ENCAP_DATA_127_96_0 0x5452380
+
+#define NIC0_TXE0_ENCAP_DATA_127_96_1 0x5452384
+
+#define NIC0_TXE0_ENCAP_DATA_127_96_2 0x5452388
+
+#define NIC0_TXE0_ENCAP_DATA_127_96_3 0x545238C
+
+#define NIC0_TXE0_ENCAP_DATA_127_96_4 0x5452390
+
+#define NIC0_TXE0_ENCAP_DATA_127_96_5 0x5452394
+
+#define NIC0_TXE0_ENCAP_DATA_127_96_6 0x5452398
+
+#define NIC0_TXE0_ENCAP_DATA_127_96_7 0x545239C
+
+#define NIC0_TXE0_ENCAP_DATA_159_128_0 0x54523A0
+
+#define NIC0_TXE0_ENCAP_DATA_159_128_1 0x54523A4
+
+#define NIC0_TXE0_ENCAP_DATA_159_128_2 0x54523A8
+
+#define NIC0_TXE0_ENCAP_DATA_159_128_3 0x54523AC
+
+#define NIC0_TXE0_ENCAP_DATA_159_128_4 0x54523B0
+
+#define NIC0_TXE0_ENCAP_DATA_159_128_5 0x54523B4
+
+#define NIC0_TXE0_ENCAP_DATA_159_128_6 0x54523B8
+
+#define NIC0_TXE0_ENCAP_DATA_159_128_7 0x54523BC
+
+#define NIC0_TXE0_ENCAP_DATA_191_160_0 0x54523C0
+
+#define NIC0_TXE0_ENCAP_DATA_191_160_1 0x54523C4
+
+#define NIC0_TXE0_ENCAP_DATA_191_160_2 0x54523C8
+
+#define NIC0_TXE0_ENCAP_DATA_191_160_3 0x54523CC
+
+#define NIC0_TXE0_ENCAP_DATA_191_160_4 0x54523D0
+
+#define NIC0_TXE0_ENCAP_DATA_191_160_5 0x54523D4
+
+#define NIC0_TXE0_ENCAP_DATA_191_160_6 0x54523D8
+
+#define NIC0_TXE0_ENCAP_DATA_191_160_7 0x54523DC
+
+#define NIC0_TXE0_ENCAP_DATA_223_192_0 0x54523E0
+
+#define NIC0_TXE0_ENCAP_DATA_223_192_1 0x54523E4
+
+#define NIC0_TXE0_ENCAP_DATA_223_192_2 0x54523E8
+
+#define NIC0_TXE0_ENCAP_DATA_223_192_3 0x54523EC
+
+#define NIC0_TXE0_ENCAP_DATA_223_192_4 0x54523F0
+
+#define NIC0_TXE0_ENCAP_DATA_223_192_5 0x54523F4
+
+#define NIC0_TXE0_ENCAP_DATA_223_192_6 0x54523F8
+
+#define NIC0_TXE0_ENCAP_DATA_223_192_7 0x54523FC
+
+#define NIC0_TXE0_ENCAP_DATA_255_224_0 0x5452400
+
+#define NIC0_TXE0_ENCAP_DATA_255_224_1 0x5452404
+
+#define NIC0_TXE0_ENCAP_DATA_255_224_2 0x5452408
+
+#define NIC0_TXE0_ENCAP_DATA_255_224_3 0x545240C
+
+#define NIC0_TXE0_ENCAP_DATA_255_224_4 0x5452410
+
+#define NIC0_TXE0_ENCAP_DATA_255_224_5 0x5452414
+
+#define NIC0_TXE0_ENCAP_DATA_255_224_6 0x5452418
+
+#define NIC0_TXE0_ENCAP_DATA_255_224_7 0x545241C
+
+#define NIC0_TXE0_ENCAP_CFG2 0x5452420
+
+#define NIC0_TXE0_MTD_DUAL_STRIDE3 0x5452430
+
+#define NIC0_TXE0_MTD_DUAL_STRIDE4 0x5452434
+
+#define NIC0_TXE0_MTD_DUAL_NUM_OF_STRIDES 0x5452438
+
+#define NIC0_TXE0_CLK_GATE_CFG 0x5452440
+
+#define NIC0_TXE0_WQE_CHECK_NOTIFY_EN 0x5452450
+
+#define NIC0_TXE0_WQE_CHECK_NOTIFY_EN2 0x5452454
+
+#define NIC0_TXE0_WQE_CHECK_CFG4 0x5452458
+
+#define NIC0_TXE0_WQE_CHECK_CFG5 0x545245C
+
+#define NIC0_TXE0_WQE_CHECK_CFG6 0x5452460
+
+#define NIC0_TXE0_DATA_READ_RL_CFG 0x5452470
+
+#endif /* ASIC_REG_NIC0_TXE0_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txs0_masks.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txs0_masks.h
new file mode 100644
index 000000000000..e3d95dd6c928
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txs0_masks.h
@@ -0,0 +1,555 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_TXS0_MASKS_H_
+#define ASIC_REG_NIC0_TXS0_MASKS_H_
+
+/*****************************************
+ * NIC0_TXS0
+ * (Prototype: NIC_TXS)
+ *****************************************
+ */
+
+/* NIC0_TXS0_TMR_SCAN_EN */
+#define NIC0_TXS0_TMR_SCAN_EN_R_SHIFT 0
+#define NIC0_TXS0_TMR_SCAN_EN_R_MASK 0x1
+
+/* NIC0_TXS0_TICK_WRAP */
+#define NIC0_TXS0_TICK_WRAP_R_SHIFT 0
+#define NIC0_TXS0_TICK_WRAP_R_MASK 0xFFFF
+
+/* NIC0_TXS0_SCAN_TIME_COMPARE_0 */
+#define NIC0_TXS0_SCAN_TIME_COMPARE_0_R_SHIFT 0
+#define NIC0_TXS0_SCAN_TIME_COMPARE_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_SCAN_TIME_COMPARE_1 */
+#define NIC0_TXS0_SCAN_TIME_COMPARE_1_R_SHIFT 0
+#define NIC0_TXS0_SCAN_TIME_COMPARE_1_R_MASK 0xFFFF
+
+/* NIC0_TXS0_SLICE_CREDIT */
+#define NIC0_TXS0_SLICE_CREDIT_R_SHIFT 0
+#define NIC0_TXS0_SLICE_CREDIT_R_MASK 0x3F
+
+/* NIC0_TXS0_SLICE_FORCE_FULL */
+#define NIC0_TXS0_SLICE_FORCE_FULL_R_SHIFT 0
+#define NIC0_TXS0_SLICE_FORCE_FULL_R_MASK 0x1
+
+/* NIC0_TXS0_FIRST_SCHEDQ_ID */
+#define NIC0_TXS0_FIRST_SCHEDQ_ID_R0_SHIFT 0
+#define NIC0_TXS0_FIRST_SCHEDQ_ID_R0_MASK 0x3F
+#define NIC0_TXS0_FIRST_SCHEDQ_ID_R1_SHIFT 8
+#define NIC0_TXS0_FIRST_SCHEDQ_ID_R1_MASK 0x3F00
+#define NIC0_TXS0_FIRST_SCHEDQ_ID_R2_SHIFT 16
+#define NIC0_TXS0_FIRST_SCHEDQ_ID_R2_MASK 0x3F0000
+#define NIC0_TXS0_FIRST_SCHEDQ_ID_R3_SHIFT 24
+#define NIC0_TXS0_FIRST_SCHEDQ_ID_R3_MASK 0x3F000000
+
+/* NIC0_TXS0_LAST_SCHEDQ_ID */
+#define NIC0_TXS0_LAST_SCHEDQ_ID_R0_SHIFT 0
+#define NIC0_TXS0_LAST_SCHEDQ_ID_R0_MASK 0x3F
+#define NIC0_TXS0_LAST_SCHEDQ_ID_R1_SHIFT 8
+#define NIC0_TXS0_LAST_SCHEDQ_ID_R1_MASK 0x3F00
+#define NIC0_TXS0_LAST_SCHEDQ_ID_R2_SHIFT 16
+#define NIC0_TXS0_LAST_SCHEDQ_ID_R2_MASK 0x3F0000
+#define NIC0_TXS0_LAST_SCHEDQ_ID_R3_SHIFT 24
+#define NIC0_TXS0_LAST_SCHEDQ_ID_R3_MASK 0x3F000000
+
+/* NIC0_TXS0_PUSH_MASK */
+#define NIC0_TXS0_PUSH_MASK_R_SHIFT 0
+#define NIC0_TXS0_PUSH_MASK_R_MASK 0x1
+
+/* NIC0_TXS0_POP_MASK */
+#define NIC0_TXS0_POP_MASK_R_SHIFT 0
+#define NIC0_TXS0_POP_MASK_R_MASK 0x1
+
+/* NIC0_TXS0_PUSH_RELEASE_INVALIDATE */
+#define NIC0_TXS0_PUSH_RELEASE_INVALIDATE_R_SHIFT 0
+#define NIC0_TXS0_PUSH_RELEASE_INVALIDATE_R_MASK 0x1
+
+/* NIC0_TXS0_POP_RELEASE_INVALIDATE */
+#define NIC0_TXS0_POP_RELEASE_INVALIDATE_R_SHIFT 0
+#define NIC0_TXS0_POP_RELEASE_INVALIDATE_R_MASK 0x1
+
+/* NIC0_TXS0_LIST_MEM_READ_MASK */
+#define NIC0_TXS0_LIST_MEM_READ_MASK_R_SHIFT 0
+#define NIC0_TXS0_LIST_MEM_READ_MASK_R_MASK 0x1
+
+/* NIC0_TXS0_FIFO_MEM_READ_MASK */
+#define NIC0_TXS0_FIFO_MEM_READ_MASK_R_SHIFT 0
+#define NIC0_TXS0_FIFO_MEM_READ_MASK_R_MASK 0x1
+
+/* NIC0_TXS0_LIST_MEM_WRITE_MASK */
+#define NIC0_TXS0_LIST_MEM_WRITE_MASK_R_SHIFT 0
+#define NIC0_TXS0_LIST_MEM_WRITE_MASK_R_MASK 0x1
+
+/* NIC0_TXS0_FIFO_MEM_WRITE_MASK */
+#define NIC0_TXS0_FIFO_MEM_WRITE_MASK_R_SHIFT 0
+#define NIC0_TXS0_FIFO_MEM_WRITE_MASK_R_MASK 0x1
+
+/* NIC0_TXS0_BASE_ADDRESS_63_32 */
+#define NIC0_TXS0_BASE_ADDRESS_63_32_R_SHIFT 0
+#define NIC0_TXS0_BASE_ADDRESS_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_BASE_ADDRESS_31_7 */
+#define NIC0_TXS0_BASE_ADDRESS_31_7_R_SHIFT 0
+#define NIC0_TXS0_BASE_ADDRESS_31_7_R_MASK 0x1FFFFFF
+
+/* NIC0_TXS0_AXI_PROT */
+#define NIC0_TXS0_AXI_PROT_R_SHIFT 0
+#define NIC0_TXS0_AXI_PROT_R_MASK 0x7
+
+/* NIC0_TXS0_RATE_LIMIT */
+#define NIC0_TXS0_RATE_LIMIT_ALWAYS_EN_SHIFT 0
+#define NIC0_TXS0_RATE_LIMIT_ALWAYS_EN_MASK 0x1
+#define NIC0_TXS0_RATE_LIMIT_IMMEDIATE_SET_SHIFT 1
+#define NIC0_TXS0_RATE_LIMIT_IMMEDIATE_SET_MASK 0x2
+
+/* NIC0_TXS0_CACHE_CFG */
+#define NIC0_TXS0_CACHE_CFG_LIST_PLRU_EVICTION_SHIFT 0
+#define NIC0_TXS0_CACHE_CFG_LIST_PLRU_EVICTION_MASK 0x1
+#define NIC0_TXS0_CACHE_CFG_LIST_CACHE_STOP_SHIFT 1
+#define NIC0_TXS0_CACHE_CFG_LIST_CACHE_STOP_MASK 0x2
+#define NIC0_TXS0_CACHE_CFG_LIST_INV_WRITEBACK_SHIFT 2
+#define NIC0_TXS0_CACHE_CFG_LIST_INV_WRITEBACK_MASK 0x4
+#define NIC0_TXS0_CACHE_CFG_FREE_LIST_PLRU_EVICTION_SHIFT 3
+#define NIC0_TXS0_CACHE_CFG_FREE_LIST_PLRU_EVICTION_MASK 0x8
+#define NIC0_TXS0_CACHE_CFG_FREE_LIST_CACHE_STOP_SHIFT 4
+#define NIC0_TXS0_CACHE_CFG_FREE_LIST_CACHE_STOP_MASK 0x10
+#define NIC0_TXS0_CACHE_CFG_FREE_LIST_INV_WRITEBACK_SHIFT 5
+#define NIC0_TXS0_CACHE_CFG_FREE_LIST_INV_WRITEBACK_MASK 0x20
+
+/* NIC0_TXS0_SCHEDQ_MEM_INIT */
+#define NIC0_TXS0_SCHEDQ_MEM_INIT_SCHED_MEM_INIT_SC_SHIFT 0
+#define NIC0_TXS0_SCHEDQ_MEM_INIT_SCHED_MEM_INIT_SC_MASK 0x7
+#define NIC0_TXS0_SCHEDQ_MEM_INIT_TMR_MEM_INIT_SC_SHIFT 4
+#define NIC0_TXS0_SCHEDQ_MEM_INIT_TMR_MEM_INIT_SC_MASK 0xF0
+#define NIC0_TXS0_SCHEDQ_MEM_INIT_SCHED_MEM_INIT_BUSY_SHIFT 8
+#define NIC0_TXS0_SCHEDQ_MEM_INIT_SCHED_MEM_INIT_BUSY_MASK 0x700
+#define NIC0_TXS0_SCHEDQ_MEM_INIT_TMR_MEM_INIT_BUSY_SHIFT 12
+#define NIC0_TXS0_SCHEDQ_MEM_INIT_TMR_MEM_INIT_BUSY_MASK 0xF000
+
+/* NIC0_TXS0_SCHEDQ_UPDATE_EN */
+#define NIC0_TXS0_SCHEDQ_UPDATE_EN_R_SHIFT 0
+#define NIC0_TXS0_SCHEDQ_UPDATE_EN_R_MASK 0x1
+
+/* NIC0_TXS0_SCHEDQ_UPDATE_FIFO */
+#define NIC0_TXS0_SCHEDQ_UPDATE_FIFO_R_SHIFT 0
+#define NIC0_TXS0_SCHEDQ_UPDATE_FIFO_R_MASK 0xFF
+
+/* NIC0_TXS0_SCHEDQ_UPDATE_DESC_31_0 */
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_31_0_R_SHIFT 0
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_SCHEDQ_UPDATE_DESC_63_32 */
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_63_32_R_SHIFT 0
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_SCHEDQ_UPDATE_DESC_95_64 */
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_95_64_R_SHIFT 0
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_95_64_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_SCHEDQ_UPDATE_DESC_127_96 */
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_127_96_R_SHIFT 0
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_127_96_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_SCHEDQ_UPDATE_DESC_159_128 */
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_159_128_R_SHIFT 0
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_159_128_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_SCHEDQ_UPDATE_DESC_191_160 */
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_191_160_R_SHIFT 0
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_191_160_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_SCHEDQ_UPDATE_DESC_217_192 */
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_217_192_R_SHIFT 0
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_217_192_R_MASK 0x1FFFFFF
+
+/* NIC0_TXS0_FORCE_HIT_EN */
+#define NIC0_TXS0_FORCE_HIT_EN_R_SHIFT 0
+#define NIC0_TXS0_FORCE_HIT_EN_R_MASK 0x1
+
+/* NIC0_TXS0_INVALIDATE_LIST */
+
+/* NIC0_TXS0_INVALIDATE_LIST_STATUS */
+#define NIC0_TXS0_INVALIDATE_LIST_STATUS_INVALIDATE_DONE_SHIFT 0
+#define NIC0_TXS0_INVALIDATE_LIST_STATUS_INVALIDATE_DONE_MASK 0x1
+#define NIC0_TXS0_INVALIDATE_LIST_STATUS_CACHE_IDLE_SHIFT 1
+#define NIC0_TXS0_INVALIDATE_LIST_STATUS_CACHE_IDLE_MASK 0x2
+
+/* NIC0_TXS0_INVALIDATE_FREE_LIST */
+
+/* NIC0_TXS0_INVALIDATE_FREE_LIST_STAT */
+#define NIC0_TXS0_INVALIDATE_FREE_LIST_STAT_INVALIDATE_DONE_SHIFT 0
+#define NIC0_TXS0_INVALIDATE_FREE_LIST_STAT_INVALIDATE_DONE_MASK 0x1
+#define NIC0_TXS0_INVALIDATE_FREE_LIST_STAT_CACHE_IDLE_SHIFT 1
+#define NIC0_TXS0_INVALIDATE_FREE_LIST_STAT_CACHE_IDLE_MASK 0x2
+
+/* NIC0_TXS0_PUSH_PREFETCH_EN */
+#define NIC0_TXS0_PUSH_PREFETCH_EN_R_SHIFT 0
+#define NIC0_TXS0_PUSH_PREFETCH_EN_R_MASK 0x1
+
+/* NIC0_TXS0_PUSH_RELEASE_EN */
+#define NIC0_TXS0_PUSH_RELEASE_EN_R_SHIFT 0
+#define NIC0_TXS0_PUSH_RELEASE_EN_R_MASK 0x1
+
+/* NIC0_TXS0_PUSH_LOCK_EN */
+#define NIC0_TXS0_PUSH_LOCK_EN_R_SHIFT 0
+#define NIC0_TXS0_PUSH_LOCK_EN_R_MASK 0x1
+
+/* NIC0_TXS0_PUSH_PREFETCH_NEXT_EN */
+#define NIC0_TXS0_PUSH_PREFETCH_NEXT_EN_R_SHIFT 0
+#define NIC0_TXS0_PUSH_PREFETCH_NEXT_EN_R_MASK 0x1
+
+/* NIC0_TXS0_POP_PREFETCH_EN */
+#define NIC0_TXS0_POP_PREFETCH_EN_R_SHIFT 0
+#define NIC0_TXS0_POP_PREFETCH_EN_R_MASK 0x1
+
+/* NIC0_TXS0_POP_RELEASE_EN */
+#define NIC0_TXS0_POP_RELEASE_EN_R_SHIFT 0
+#define NIC0_TXS0_POP_RELEASE_EN_R_MASK 0x1
+
+/* NIC0_TXS0_POP_LOCK_EN */
+#define NIC0_TXS0_POP_LOCK_EN_R_SHIFT 0
+#define NIC0_TXS0_POP_LOCK_EN_R_MASK 0x1
+
+/* NIC0_TXS0_POP_PREFETCH_NEXT_EN */
+#define NIC0_TXS0_POP_PREFETCH_NEXT_EN_R_SHIFT 0
+#define NIC0_TXS0_POP_PREFETCH_NEXT_EN_R_MASK 0x1
+
+/* NIC0_TXS0_LIST_MASK */
+#define NIC0_TXS0_LIST_MASK_R_SHIFT 0
+#define NIC0_TXS0_LIST_MASK_R_MASK 0x7FFFFFF
+
+/* NIC0_TXS0_RELEASE_INCALIDATE */
+#define NIC0_TXS0_RELEASE_INCALIDATE_R_SHIFT 0
+#define NIC0_TXS0_RELEASE_INCALIDATE_R_MASK 0x1
+
+/* NIC0_TXS0_BASE_ADDRESS_FREE_LIST_63_32 */
+#define NIC0_TXS0_BASE_ADDRESS_FREE_LIST_63_32_R_SHIFT 0
+#define NIC0_TXS0_BASE_ADDRESS_FREE_LIST_63_32_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_BASE_ADDRESS_FREE_LIST_31_0 */
+#define NIC0_TXS0_BASE_ADDRESS_FREE_LIST_31_0_R_SHIFT 0
+#define NIC0_TXS0_BASE_ADDRESS_FREE_LIST_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_FREE_LIST_EN */
+#define NIC0_TXS0_FREE_LIST_EN_R_SHIFT 0
+#define NIC0_TXS0_FREE_LIST_EN_R_MASK 0x1
+
+/* NIC0_TXS0_PUSH_FORCE_HIT_EN */
+#define NIC0_TXS0_PUSH_FORCE_HIT_EN_R_SHIFT 0
+#define NIC0_TXS0_PUSH_FORCE_HIT_EN_R_MASK 0x1
+
+/* NIC0_TXS0_PRODUCER_UPDATE_EN */
+#define NIC0_TXS0_PRODUCER_UPDATE_EN_R_SHIFT 0
+#define NIC0_TXS0_PRODUCER_UPDATE_EN_R_MASK 0x1
+
+/* NIC0_TXS0_PRODUCER_UPDATE */
+#define NIC0_TXS0_PRODUCER_UPDATE_R_SHIFT 0
+#define NIC0_TXS0_PRODUCER_UPDATE_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_PRIOQ_CREDIT_FORCE */
+#define NIC0_TXS0_PRIOQ_CREDIT_FORCE_FORCE_FULL_SHIFT 0
+#define NIC0_TXS0_PRIOQ_CREDIT_FORCE_FORCE_FULL_MASK 0xFF
+
+/* NIC0_TXS0_PRIOQ_CREDIT */
+#define NIC0_TXS0_PRIOQ_CREDIT_R_SHIFT 0
+#define NIC0_TXS0_PRIOQ_CREDIT_R_MASK 0x3F
+
+/* NIC0_TXS0_DBG_COUNT_SELECT0 */
+#define NIC0_TXS0_DBG_COUNT_SELECT0_R_SHIFT 0
+#define NIC0_TXS0_DBG_COUNT_SELECT0_R_MASK 0x3F
+
+/* NIC0_TXS0_DBG_COUNT_SELECT1 */
+#define NIC0_TXS0_DBG_COUNT_SELECT1_R_SHIFT 0
+#define NIC0_TXS0_DBG_COUNT_SELECT1_R_MASK 0x3F
+
+/* NIC0_TXS0_DBG_COUNT_SELECT2 */
+#define NIC0_TXS0_DBG_COUNT_SELECT2_R_SHIFT 0
+#define NIC0_TXS0_DBG_COUNT_SELECT2_R_MASK 0x3F
+
+/* NIC0_TXS0_DBG_COUNT_SELECT3 */
+#define NIC0_TXS0_DBG_COUNT_SELECT3_R_SHIFT 0
+#define NIC0_TXS0_DBG_COUNT_SELECT3_R_MASK 0x3F
+
+/* NIC0_TXS0_DBG_COUNT_SELECT4 */
+#define NIC0_TXS0_DBG_COUNT_SELECT4_R_SHIFT 0
+#define NIC0_TXS0_DBG_COUNT_SELECT4_R_MASK 0x3F
+
+/* NIC0_TXS0_DBG_COUNT_SELECT5 */
+#define NIC0_TXS0_DBG_COUNT_SELECT5_R_SHIFT 0
+#define NIC0_TXS0_DBG_COUNT_SELECT5_R_MASK 0x3F
+
+/* NIC0_TXS0_DBG_COUNT_SELECT6 */
+#define NIC0_TXS0_DBG_COUNT_SELECT6_R_SHIFT 0
+#define NIC0_TXS0_DBG_COUNT_SELECT6_R_MASK 0x3F
+
+/* NIC0_TXS0_DBG_COUNT_SELECT7 */
+#define NIC0_TXS0_DBG_COUNT_SELECT7_R_SHIFT 0
+#define NIC0_TXS0_DBG_COUNT_SELECT7_R_MASK 0x3F
+
+/* NIC0_TXS0_DBG_COUNT_SELECT8 */
+#define NIC0_TXS0_DBG_COUNT_SELECT8_R_SHIFT 0
+#define NIC0_TXS0_DBG_COUNT_SELECT8_R_MASK 0x3F
+
+/* NIC0_TXS0_DBG_COUNT_SELECT9 */
+#define NIC0_TXS0_DBG_COUNT_SELECT9_R_SHIFT 0
+#define NIC0_TXS0_DBG_COUNT_SELECT9_R_MASK 0x3F
+
+/* NIC0_TXS0_DBG_COUNT_SELECT10 */
+#define NIC0_TXS0_DBG_COUNT_SELECT10_R_SHIFT 0
+#define NIC0_TXS0_DBG_COUNT_SELECT10_R_MASK 0x3F
+
+/* NIC0_TXS0_DBG_COUNT_SELECT11 */
+#define NIC0_TXS0_DBG_COUNT_SELECT11_R_SHIFT 0
+#define NIC0_TXS0_DBG_COUNT_SELECT11_R_MASK 0x3F
+
+/* NIC0_TXS0_IGNORE_BURST_EN */
+#define NIC0_TXS0_IGNORE_BURST_EN_R_SHIFT 0
+#define NIC0_TXS0_IGNORE_BURST_EN_R_MASK 0x1
+
+/* NIC0_TXS0_IGNORE_BURST_THRESHOLD */
+#define NIC0_TXS0_IGNORE_BURST_THRESHOLD_R_SHIFT 0
+#define NIC0_TXS0_IGNORE_BURST_THRESHOLD_R_MASK 0x1FFFFFF
+
+/* NIC0_TXS0_RANDOM_PSUH_CFG */
+#define NIC0_TXS0_RANDOM_PSUH_CFG_BYPASS_SHIFT 0
+#define NIC0_TXS0_RANDOM_PSUH_CFG_BYPASS_MASK 0x1
+#define NIC0_TXS0_RANDOM_PSUH_CFG_RATE_LIMIT_EN_SHIFT 1
+#define NIC0_TXS0_RANDOM_PSUH_CFG_RATE_LIMIT_EN_MASK 0x2
+#define NIC0_TXS0_RANDOM_PSUH_CFG_SATURATION_SHIFT 2
+#define NIC0_TXS0_RANDOM_PSUH_CFG_SATURATION_MASK 0x3C
+#define NIC0_TXS0_RANDOM_PSUH_CFG_RST_TOKEN_SHIFT 6
+#define NIC0_TXS0_RANDOM_PSUH_CFG_RST_TOKEN_MASK 0x7FFC0
+#define NIC0_TXS0_RANDOM_PSUH_CFG_TIMEOUT_SHIFT 19
+#define NIC0_TXS0_RANDOM_PSUH_CFG_TIMEOUT_MASK 0xFFF80000
+
+/* NIC0_TXS0_DBG_HW_EVENT_TRIGER */
+#define NIC0_TXS0_DBG_HW_EVENT_TRIGER_R_SHIFT 0
+#define NIC0_TXS0_DBG_HW_EVENT_TRIGER_R_MASK 0x1F
+
+/* NIC0_TXS0_INTERRUPT_CAUSE */
+#define NIC0_TXS0_INTERRUPT_CAUSE_R_SHIFT 0
+#define NIC0_TXS0_INTERRUPT_CAUSE_R_MASK 0xF
+
+/* NIC0_TXS0_INTERRUPT_MASK */
+#define NIC0_TXS0_INTERRUPT_MASK_R_SHIFT 0
+#define NIC0_TXS0_INTERRUPT_MASK_R_MASK 0xF
+
+/* NIC0_TXS0_INTERRUPT_CLR */
+
+/* NIC0_TXS0_LOAD_SLICE_HIT_EN */
+#define NIC0_TXS0_LOAD_SLICE_HIT_EN_R_SHIFT 0
+#define NIC0_TXS0_LOAD_SLICE_HIT_EN_R_MASK 0x1
+
+/* NIC0_TXS0_SLICE_ACTIVE_47_32 */
+#define NIC0_TXS0_SLICE_ACTIVE_47_32_R_SHIFT 0
+#define NIC0_TXS0_SLICE_ACTIVE_47_32_R_MASK 0xFFFF
+
+/* NIC0_TXS0_SLICE_ACTIVE_31_0 */
+#define NIC0_TXS0_SLICE_ACTIVE_31_0_R_SHIFT 0
+#define NIC0_TXS0_SLICE_ACTIVE_31_0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_AXI_CACHE */
+#define NIC0_TXS0_AXI_CACHE_R_SHIFT 0
+#define NIC0_TXS0_AXI_CACHE_R_MASK 0xF
+
+/* NIC0_TXS0_SLICE_GW_ADDR */
+#define NIC0_TXS0_SLICE_GW_ADDR_R_SHIFT 0
+#define NIC0_TXS0_SLICE_GW_ADDR_R_MASK 0x3F
+
+/* NIC0_TXS0_SLICE_GW_DATA */
+#define NIC0_TXS0_SLICE_GW_DATA_R_SHIFT 0
+#define NIC0_TXS0_SLICE_GW_DATA_R_MASK 0x1FFFFFF
+
+/* NIC0_TXS0_SCANNER_CREDIT_EN */
+#define NIC0_TXS0_SCANNER_CREDIT_EN_R_SHIFT 0
+#define NIC0_TXS0_SCANNER_CREDIT_EN_R_MASK 0x3
+
+/* NIC0_TXS0_FREE_LIST_PUSH_MASK_EN */
+#define NIC0_TXS0_FREE_LIST_PUSH_MASK_EN_R_SHIFT 0
+#define NIC0_TXS0_FREE_LIST_PUSH_MASK_EN_R_MASK 0x1
+
+/* NIC0_TXS0_FREE_AEMPTY_THRESHOLD */
+#define NIC0_TXS0_FREE_AEMPTY_THRESHOLD_R_SHIFT 0
+#define NIC0_TXS0_FREE_AEMPTY_THRESHOLD_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_AXI_USER_LO */
+#define NIC0_TXS0_AXI_USER_LO_R_SHIFT 0
+#define NIC0_TXS0_AXI_USER_LO_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_AXI_USER_HI */
+#define NIC0_TXS0_AXI_USER_HI_R_SHIFT 0
+#define NIC0_TXS0_AXI_USER_HI_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_NCH_SYNCED */
+#define NIC0_TXS0_NCH_SYNCED_FORCE_BP_SHIFT 0
+#define NIC0_TXS0_NCH_SYNCED_FORCE_BP_MASK 0x1
+#define NIC0_TXS0_NCH_SYNCED_GRCFL_CLEAR_SHIFT 1
+#define NIC0_TXS0_NCH_SYNCED_GRCFL_CLEAR_MASK 0x2
+#define NIC0_TXS0_NCH_SYNCED_RESERVED_SHIFT 2
+#define NIC0_TXS0_NCH_SYNCED_RESERVED_MASK 0xFFFFFFFC
+
+/* NIC0_TXS0_NCH_ASYNCED */
+#define NIC0_TXS0_NCH_ASYNCED_ARB_WEIGHT_SHIFT 0
+#define NIC0_TXS0_NCH_ASYNCED_ARB_WEIGHT_MASK 0xFF
+#define NIC0_TXS0_NCH_ASYNCED_Y_X_MASK_SHIFT 8
+#define NIC0_TXS0_NCH_ASYNCED_Y_X_MASK_MASK 0x3FFFF00
+#define NIC0_TXS0_NCH_ASYNCED_MC_EN_SHIFT 28
+#define NIC0_TXS0_NCH_ASYNCED_MC_EN_MASK 0x30000000
+
+/* NIC0_TXS0_NCH_ASYNCED_RES */
+#define NIC0_TXS0_NCH_ASYNCED_RES_RESERVED_SHIFT 0
+#define NIC0_TXS0_NCH_ASYNCED_RES_RESERVED_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_STATS_CFG */
+#define NIC0_TXS0_STATS_CFG_MEAS_WIN_SIZE_SHIFT 0
+#define NIC0_TXS0_STATS_CFG_MEAS_WIN_SIZE_MASK 0x7FFFFFFF
+#define NIC0_TXS0_STATS_CFG_CLEAR_SC_SHIFT 31
+#define NIC0_TXS0_STATS_CFG_CLEAR_SC_MASK 0x80000000
+
+/* NIC0_TXS0_STATS_TOT_PUSH_REQ */
+#define NIC0_TXS0_STATS_TOT_PUSH_REQ_R_SHIFT 0
+#define NIC0_TXS0_STATS_TOT_PUSH_REQ_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_STATS_TOT_PUSH_RES */
+#define NIC0_TXS0_STATS_TOT_PUSH_RES_R_SHIFT 0
+#define NIC0_TXS0_STATS_TOT_PUSH_RES_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_STATS_TOT_SCHED_QP_REQ */
+#define NIC0_TXS0_STATS_TOT_SCHED_QP_REQ_R_SHIFT 0
+#define NIC0_TXS0_STATS_TOT_SCHED_QP_REQ_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_STATS_TOT_SCHED_QP_RES */
+#define NIC0_TXS0_STATS_TOT_SCHED_QP_RES_R_SHIFT 0
+#define NIC0_TXS0_STATS_TOT_SCHED_QP_RES_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_STATS_TOT_RETURN_SLICE */
+#define NIC0_TXS0_STATS_TOT_RETURN_SLICE_R_SHIFT 0
+#define NIC0_TXS0_STATS_TOT_RETURN_SLICE_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_STATS_WIN_PUSH_REQ */
+#define NIC0_TXS0_STATS_WIN_PUSH_REQ_R_SHIFT 0
+#define NIC0_TXS0_STATS_WIN_PUSH_REQ_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_STATS_WIN_PUSH_RES */
+#define NIC0_TXS0_STATS_WIN_PUSH_RES_R_SHIFT 0
+#define NIC0_TXS0_STATS_WIN_PUSH_RES_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_STATS_WIN_SCHED_QP_REQ */
+#define NIC0_TXS0_STATS_WIN_SCHED_QP_REQ_R_SHIFT 0
+#define NIC0_TXS0_STATS_WIN_SCHED_QP_REQ_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_STATS_WIN_SCHED_QP_RES */
+#define NIC0_TXS0_STATS_WIN_SCHED_QP_RES_R_SHIFT 0
+#define NIC0_TXS0_STATS_WIN_SCHED_QP_RES_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_STATS_WIN_RETURN_SLICE */
+#define NIC0_TXS0_STATS_WIN_RETURN_SLICE_R_SHIFT 0
+#define NIC0_TXS0_STATS_WIN_RETURN_SLICE_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_ASYNC_NICL_APB_ADDR_MASK */
+#define NIC0_TXS0_ASYNC_NICL_APB_ADDR_MASK_R_SHIFT 0
+#define NIC0_TXS0_ASYNC_NICL_APB_ADDR_MASK_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR0 */
+#define NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR0_R_SHIFT 0
+#define NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR1 */
+#define NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR1_R_SHIFT 0
+#define NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR1_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR2 */
+#define NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR2_R_SHIFT 0
+#define NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR2_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR3 */
+#define NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR3_R_SHIFT 0
+#define NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR3_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_ASYNC_NICD_APB_ADDR_MASK */
+#define NIC0_TXS0_ASYNC_NICD_APB_ADDR_MASK_R_SHIFT 0
+#define NIC0_TXS0_ASYNC_NICD_APB_ADDR_MASK_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR0 */
+#define NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR0_R_SHIFT 0
+#define NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR1 */
+#define NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR1_R_SHIFT 0
+#define NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR1_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR2 */
+#define NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR2_R_SHIFT 0
+#define NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR2_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR3 */
+#define NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR3_R_SHIFT 0
+#define NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR3_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_TX_APB_ADDR_MASK */
+#define NIC0_TXS0_TX_APB_ADDR_MASK_R_SHIFT 0
+#define NIC0_TXS0_TX_APB_ADDR_MASK_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_TX_APB_SPLIT_ADDR0 */
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR0_R_SHIFT 0
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR0_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_TX_APB_SPLIT_ADDR1 */
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR1_R_SHIFT 0
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR1_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_TX_APB_SPLIT_ADDR2 */
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR2_R_SHIFT 0
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR2_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_TX_APB_SPLIT_ADDR3 */
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR3_R_SHIFT 0
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR3_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_TX_APB_SPLIT_ADDR4 */
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR4_R_SHIFT 0
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR4_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_TX_APB_SPLIT_ADDR5 */
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR5_R_SHIFT 0
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR5_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_TX_APB_SPLIT_ADDR6 */
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR6_R_SHIFT 0
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR6_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_HW_EVENT_CFG */
+#define NIC0_TXS0_HW_EVENT_CFG_EVENT_ID_SHIFT 0
+#define NIC0_TXS0_HW_EVENT_CFG_EVENT_ID_MASK 0xFFFF
+#define NIC0_TXS0_HW_EVENT_CFG_DBG_SELECT0_SHIFT 16
+#define NIC0_TXS0_HW_EVENT_CFG_DBG_SELECT0_MASK 0xF0000
+#define NIC0_TXS0_HW_EVENT_CFG_DBG_SELECT1_SHIFT 20
+#define NIC0_TXS0_HW_EVENT_CFG_DBG_SELECT1_MASK 0xF00000
+#define NIC0_TXS0_HW_EVENT_CFG_DBG_SELECT2_SHIFT 24
+#define NIC0_TXS0_HW_EVENT_CFG_DBG_SELECT2_MASK 0xF000000
+
+/* NIC0_TXS0_CHICKEN_BITS */
+#define NIC0_TXS0_CHICKEN_BITS_R_SHIFT 0
+#define NIC0_TXS0_CHICKEN_BITS_R_MASK 0xFFFFFFFF
+
+/* NIC0_TXS0_CLK_GATE_CFG */
+#define NIC0_TXS0_CLK_GATE_CFG_CLOSE_DELAY_SHIFT 0
+#define NIC0_TXS0_CLK_GATE_CFG_CLOSE_DELAY_MASK 0xFFFF
+#define NIC0_TXS0_CLK_GATE_CFG_CGM_DIS_SHIFT 30
+#define NIC0_TXS0_CLK_GATE_CFG_CGM_DIS_MASK 0x40000000
+#define NIC0_TXS0_CLK_GATE_CFG_FORCE_OPEN_SHIFT 31
+#define NIC0_TXS0_CLK_GATE_CFG_FORCE_OPEN_MASK 0x80000000
+
+#endif /* ASIC_REG_NIC0_TXS0_MASKS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txs0_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txs0_regs.h
new file mode 100644
index 000000000000..833a9fcd41ba
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txs0_regs.h
@@ -0,0 +1,289 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_TXS0_REGS_H_
+#define ASIC_REG_NIC0_TXS0_REGS_H_
+
+/*****************************************
+ * NIC0_TXS0
+ * (Prototype: NIC_TXS)
+ *****************************************
+ */
+
+#define NIC0_TXS0_TMR_SCAN_EN 0x5450000
+
+#define NIC0_TXS0_TICK_WRAP 0x5450004
+
+#define NIC0_TXS0_SCAN_TIME_COMPARE_0 0x5450008
+
+#define NIC0_TXS0_SCAN_TIME_COMPARE_1 0x545000C
+
+#define NIC0_TXS0_SLICE_CREDIT 0x5450010
+
+#define NIC0_TXS0_SLICE_FORCE_FULL 0x5450014
+
+#define NIC0_TXS0_FIRST_SCHEDQ_ID 0x5450018
+
+#define NIC0_TXS0_LAST_SCHEDQ_ID 0x545001C
+
+#define NIC0_TXS0_PUSH_MASK 0x5450020
+
+#define NIC0_TXS0_POP_MASK 0x5450024
+
+#define NIC0_TXS0_PUSH_RELEASE_INVALIDATE 0x5450028
+
+#define NIC0_TXS0_POP_RELEASE_INVALIDATE 0x545002C
+
+#define NIC0_TXS0_LIST_MEM_READ_MASK 0x5450030
+
+#define NIC0_TXS0_FIFO_MEM_READ_MASK 0x5450034
+
+#define NIC0_TXS0_LIST_MEM_WRITE_MASK 0x5450038
+
+#define NIC0_TXS0_FIFO_MEM_WRITE_MASK 0x545003C
+
+#define NIC0_TXS0_BASE_ADDRESS_63_32 0x5450040
+
+#define NIC0_TXS0_BASE_ADDRESS_31_7 0x5450044
+
+#define NIC0_TXS0_AXI_PROT 0x545004C
+
+#define NIC0_TXS0_RATE_LIMIT 0x5450050
+
+#define NIC0_TXS0_CACHE_CFG 0x5450054
+
+#define NIC0_TXS0_SCHEDQ_MEM_INIT 0x5450058
+
+#define NIC0_TXS0_SCHEDQ_UPDATE_EN 0x545005C
+
+#define NIC0_TXS0_SCHEDQ_UPDATE_FIFO 0x5450060
+
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_31_0 0x5450064
+
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_63_32 0x5450068
+
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_95_64 0x545006C
+
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_127_96 0x5450070
+
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_159_128 0x5450074
+
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_191_160 0x5450078
+
+#define NIC0_TXS0_SCHEDQ_UPDATE_DESC_217_192 0x545007C
+
+#define NIC0_TXS0_FORCE_HIT_EN 0x5450080
+
+#define NIC0_TXS0_INVALIDATE_LIST 0x5450084
+
+#define NIC0_TXS0_INVALIDATE_LIST_STATUS 0x5450088
+
+#define NIC0_TXS0_INVALIDATE_FREE_LIST 0x545008C
+
+#define NIC0_TXS0_INVALIDATE_FREE_LIST_STAT 0x5450090
+
+#define NIC0_TXS0_PUSH_PREFETCH_EN 0x5450094
+
+#define NIC0_TXS0_PUSH_RELEASE_EN 0x5450098
+
+#define NIC0_TXS0_PUSH_LOCK_EN 0x545009C
+
+#define NIC0_TXS0_PUSH_PREFETCH_NEXT_EN 0x54500A0
+
+#define NIC0_TXS0_POP_PREFETCH_EN 0x54500A4
+
+#define NIC0_TXS0_POP_RELEASE_EN 0x54500A8
+
+#define NIC0_TXS0_POP_LOCK_EN 0x54500AC
+
+#define NIC0_TXS0_POP_PREFETCH_NEXT_EN 0x54500B0
+
+#define NIC0_TXS0_LIST_MASK 0x54500B4
+
+#define NIC0_TXS0_RELEASE_INCALIDATE 0x54500B8
+
+#define NIC0_TXS0_BASE_ADDRESS_FREE_LIST_63_32 0x54500BC
+
+#define NIC0_TXS0_BASE_ADDRESS_FREE_LIST_31_0 0x54500C0
+
+#define NIC0_TXS0_FREE_LIST_EN 0x54500C4
+
+#define NIC0_TXS0_PUSH_FORCE_HIT_EN 0x54500C8
+
+#define NIC0_TXS0_PRODUCER_UPDATE_EN 0x54500CC
+
+#define NIC0_TXS0_PRODUCER_UPDATE 0x54500D0
+
+#define NIC0_TXS0_PRIOQ_CREDIT_FORCE 0x54500D4
+
+#define NIC0_TXS0_PRIOQ_CREDIT_0 0x54500D8
+
+#define NIC0_TXS0_PRIOQ_CREDIT_1 0x54500DC
+
+#define NIC0_TXS0_PRIOQ_CREDIT_2 0x54500E0
+
+#define NIC0_TXS0_PRIOQ_CREDIT_3 0x54500E4
+
+#define NIC0_TXS0_PRIOQ_CREDIT_4 0x54500E8
+
+#define NIC0_TXS0_PRIOQ_CREDIT_5 0x54500EC
+
+#define NIC0_TXS0_PRIOQ_CREDIT_6 0x54500F0
+
+#define NIC0_TXS0_PRIOQ_CREDIT_7 0x54500F4
+
+#define NIC0_TXS0_DBG_COUNT_SELECT0 0x54500F8
+
+#define NIC0_TXS0_DBG_COUNT_SELECT1 0x54500FC
+
+#define NIC0_TXS0_DBG_COUNT_SELECT2 0x5450100
+
+#define NIC0_TXS0_DBG_COUNT_SELECT3 0x5450104
+
+#define NIC0_TXS0_DBG_COUNT_SELECT4 0x5450108
+
+#define NIC0_TXS0_DBG_COUNT_SELECT5 0x545010C
+
+#define NIC0_TXS0_DBG_COUNT_SELECT6 0x5450110
+
+#define NIC0_TXS0_DBG_COUNT_SELECT7 0x5450114
+
+#define NIC0_TXS0_DBG_COUNT_SELECT8 0x5450118
+
+#define NIC0_TXS0_DBG_COUNT_SELECT9 0x545011C
+
+#define NIC0_TXS0_DBG_COUNT_SELECT10 0x5450120
+
+#define NIC0_TXS0_DBG_COUNT_SELECT11 0x5450124
+
+#define NIC0_TXS0_IGNORE_BURST_EN 0x5450140
+
+#define NIC0_TXS0_IGNORE_BURST_THRESHOLD_0 0x5450144
+
+#define NIC0_TXS0_IGNORE_BURST_THRESHOLD_1 0x5450148
+
+#define NIC0_TXS0_IGNORE_BURST_THRESHOLD_2 0x545014C
+
+#define NIC0_TXS0_IGNORE_BURST_THRESHOLD_3 0x5450150
+
+#define NIC0_TXS0_IGNORE_BURST_THRESHOLD_4 0x5450154
+
+#define NIC0_TXS0_IGNORE_BURST_THRESHOLD_5 0x5450158
+
+#define NIC0_TXS0_IGNORE_BURST_THRESHOLD_6 0x545015C
+
+#define NIC0_TXS0_IGNORE_BURST_THRESHOLD_7 0x5450160
+
+#define NIC0_TXS0_RANDOM_PSUH_CFG 0x5450164
+
+#define NIC0_TXS0_DBG_HW_EVENT_TRIGER 0x5450168
+
+#define NIC0_TXS0_INTERRUPT_CAUSE 0x545016C
+
+#define NIC0_TXS0_INTERRUPT_MASK 0x5450170
+
+#define NIC0_TXS0_INTERRUPT_CLR 0x5450174
+
+#define NIC0_TXS0_LOAD_SLICE_HIT_EN 0x5450178
+
+#define NIC0_TXS0_SLICE_ACTIVE_47_32 0x545017C
+
+#define NIC0_TXS0_SLICE_ACTIVE_31_0 0x5450180
+
+#define NIC0_TXS0_AXI_CACHE 0x5450184
+
+#define NIC0_TXS0_SLICE_GW_ADDR 0x5450188
+
+#define NIC0_TXS0_SLICE_GW_DATA 0x545018C
+
+#define NIC0_TXS0_SCANNER_CREDIT_EN 0x5450190
+
+#define NIC0_TXS0_FREE_LIST_PUSH_MASK_EN 0x5450194
+
+#define NIC0_TXS0_FREE_AEMPTY_THRESHOLD 0x5450198
+
+#define NIC0_TXS0_AXI_USER_LO 0x5450200
+
+#define NIC0_TXS0_AXI_USER_HI 0x5450204
+
+#define NIC0_TXS0_NCH_SYNCED 0x5450210
+
+#define NIC0_TXS0_NCH_ASYNCED 0x5450214
+
+#define NIC0_TXS0_NCH_ASYNCED_RES 0x5450218
+
+#define NIC0_TXS0_STATS_CFG 0x5450220
+
+#define NIC0_TXS0_STATS_TOT_PUSH_REQ 0x5450230
+
+#define NIC0_TXS0_STATS_TOT_PUSH_RES 0x5450234
+
+#define NIC0_TXS0_STATS_TOT_SCHED_QP_REQ 0x5450238
+
+#define NIC0_TXS0_STATS_TOT_SCHED_QP_RES 0x545023C
+
+#define NIC0_TXS0_STATS_TOT_RETURN_SLICE 0x5450240
+
+#define NIC0_TXS0_STATS_WIN_PUSH_REQ 0x5450250
+
+#define NIC0_TXS0_STATS_WIN_PUSH_RES 0x5450254
+
+#define NIC0_TXS0_STATS_WIN_SCHED_QP_REQ 0x5450258
+
+#define NIC0_TXS0_STATS_WIN_SCHED_QP_RES 0x545025C
+
+#define NIC0_TXS0_STATS_WIN_RETURN_SLICE 0x5450260
+
+#define NIC0_TXS0_ASYNC_NICL_APB_ADDR_MASK 0x5450270
+
+#define NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR0 0x5450274
+
+#define NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR1 0x5450278
+
+#define NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR2 0x545027C
+
+#define NIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR3 0x5450280
+
+#define NIC0_TXS0_ASYNC_NICD_APB_ADDR_MASK 0x5450290
+
+#define NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR0 0x5450294
+
+#define NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR1 0x5450298
+
+#define NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR2 0x545029C
+
+#define NIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR3 0x54502A0
+
+#define NIC0_TXS0_TX_APB_ADDR_MASK 0x54502B0
+
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR0 0x54502B4
+
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR1 0x54502B8
+
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR2 0x54502BC
+
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR3 0x54502C0
+
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR4 0x54502C4
+
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR5 0x54502C8
+
+#define NIC0_TXS0_TX_APB_SPLIT_ADDR6 0x54502CC
+
+#define NIC0_TXS0_HW_EVENT_CFG 0x54502E0
+
+#define NIC0_TXS0_CHICKEN_BITS 0x54502E8
+
+#define NIC0_TXS0_CLK_GATE_CFG 0x54502F0
+
+#endif /* ASIC_REG_NIC0_TXS0_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h
new file mode 100644
index 000000000000..67aec43375d3
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_REGS_H_
+#define ASIC_REG_NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_REGS_H_
+
+/*****************************************
+ * NIC0_UMR0_0_COMPLETION_QUEUE_CI_1
+ * (Prototype: COMPLETION_QUEUE_CI)
+ *****************************************
+ */
+
+#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_NUMBER 0x5400180
+
+#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX 0x5400184
+
+#endif /* ASIC_REG_NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h
new file mode 100644
index 000000000000..090fa21d9600
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL0_REGS_H_
+#define ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL0_REGS_H_
+
+/*****************************************
+ * NIC0_UMR0_0_UNSECURE_DOORBELL0
+ * (Prototype: NIC_UNSEC_DBELL)
+ *****************************************
+ */
+
+#define NIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 0x5400000
+
+#define NIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_SECOND32 0x5400004
+
+#define NIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_THIRD32 0x5400008
+
+#define NIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FOURTH32 0x540000C
+
+#endif /* ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL0_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell1_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell1_regs.h
new file mode 100644
index 000000000000..54a9a9ae5d47
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell1_regs.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL1_REGS_H_
+#define ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL1_REGS_H_
+
+/*****************************************
+ * NIC0_UMR0_0_UNSECURE_DOORBELL1
+ * (Prototype: NIC_UNSEC_DBELL)
+ *****************************************
+ */
+
+#define NIC0_UMR0_0_UNSECURE_DOORBELL1_UNSECURE_DB_FIRST32 0x5400080
+
+#define NIC0_UMR0_0_UNSECURE_DOORBELL1_UNSECURE_DB_SECOND32 0x5400084
+
+#define NIC0_UMR0_0_UNSECURE_DOORBELL1_UNSECURE_DB_THIRD32 0x5400088
+
+#define NIC0_UMR0_0_UNSECURE_DOORBELL1_UNSECURE_DB_FOURTH32 0x540008C
+
+#endif /* ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL1_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/prt0_mac_core_masks.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/prt0_mac_core_masks.h
new file mode 100644
index 000000000000..6a1999c28272
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/prt0_mac_core_masks.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_PRT0_MAC_CORE_MASKS_H_
+#define ASIC_REG_PRT0_MAC_CORE_MASKS_H_
+
+/*****************************************
+ * PRT0_MAC_CORE
+ * (Prototype: PRT_MAC_CORE)
+ *****************************************
+ */
+
+/* PRT0_MAC_CORE_MAC_SD_CFG */
+#define PRT0_MAC_CORE_MAC_SD_CFG_SD_N2_SHIFT 0
+#define PRT0_MAC_CORE_MAC_SD_CFG_SD_N2_MASK 0xF
+#define PRT0_MAC_CORE_MAC_SD_CFG_SD_8X_SHIFT 4
+#define PRT0_MAC_CORE_MAC_SD_CFG_SD_8X_MASK 0xF0
+#define PRT0_MAC_CORE_MAC_SD_CFG_SD_SW_SIGNAL_DET_OR_SHIFT 16
+#define PRT0_MAC_CORE_MAC_SD_CFG_SD_SW_SIGNAL_DET_OR_MASK 0xF0000
+#define PRT0_MAC_CORE_MAC_SD_CFG_SD_SW_SIGNAL_DET_AND_SHIFT 20
+#define PRT0_MAC_CORE_MAC_SD_CFG_SD_SW_SIGNAL_DET_AND_MASK 0xF00000
+#define PRT0_MAC_CORE_MAC_SD_CFG_SD_SW_SIGNAL_DET_OVERRIDE_SHIFT 24
+#define PRT0_MAC_CORE_MAC_SD_CFG_SD_SW_SIGNAL_DET_OVERRIDE_MASK 0xF000000
+
+/* PRT0_MAC_CORE_MAC_SD_STS */
+#define PRT0_MAC_CORE_MAC_SD_STS_SD_SIG_DET_SHIFT 0
+#define PRT0_MAC_CORE_MAC_SD_STS_SD_SIG_DET_MASK 0xF
+
+/* PRT0_MAC_CORE_MAC_REC_STS0 */
+#define PRT0_MAC_CORE_MAC_REC_STS0_REC_ALIGN_DONE_SHIFT 0
+#define PRT0_MAC_CORE_MAC_REC_STS0_REC_ALIGN_DONE_MASK 0x3
+#define PRT0_MAC_CORE_MAC_REC_STS0_REC_HIGH_BER_SHIFT 2
+#define PRT0_MAC_CORE_MAC_REC_STS0_REC_HIGH_BER_MASK 0x3C
+#define PRT0_MAC_CORE_MAC_REC_STS0_REC_LINK_STS_SHIFT 6
+#define PRT0_MAC_CORE_MAC_REC_STS0_REC_LINK_STS_MASK 0x3C0
+#define PRT0_MAC_CORE_MAC_REC_STS0_REC_AMPS_LOCK_SHIFT 10
+#define PRT0_MAC_CORE_MAC_REC_STS0_REC_AMPS_LOCK_MASK 0x3FC00
+#define PRT0_MAC_CORE_MAC_REC_STS0_REC_RSFEC_ALIGNED_SHIFT 18
+#define PRT0_MAC_CORE_MAC_REC_STS0_REC_RSFEC_ALIGNED_MASK 0x3C0000
+
+/* PRT0_MAC_CORE_MAC_REC_STS1 */
+#define PRT0_MAC_CORE_MAC_REC_STS1_REC_BLOCK_LOCK_SHIFT 0
+#define PRT0_MAC_CORE_MAC_REC_STS1_REC_BLOCK_LOCK_MASK 0xFFFFF
+
+/* PRT0_MAC_CORE_MAC_FC_FEC_CFG */
+#define PRT0_MAC_CORE_MAC_FC_FEC_CFG_FEC_ENA_SHIFT 0
+#define PRT0_MAC_CORE_MAC_FC_FEC_CFG_FEC_ENA_MASK 0xF
+#define PRT0_MAC_CORE_MAC_FC_FEC_CFG_FEC_ERR_ENA_SHIFT 4
+#define PRT0_MAC_CORE_MAC_FC_FEC_CFG_FEC_ERR_ENA_MASK 0xF0
+
+/* PRT0_MAC_CORE_MAC_FC_FEC_STS */
+#define PRT0_MAC_CORE_MAC_FC_FEC_STS_FEC_LOCKED_SHIFT 0
+#define PRT0_MAC_CORE_MAC_FC_FEC_STS_FEC_LOCKED_MASK 0xFF
+#define PRT0_MAC_CORE_MAC_FC_FEC_STS_FEC_CERR_SHIFT 8
+#define PRT0_MAC_CORE_MAC_FC_FEC_STS_FEC_CERR_MASK 0xFF00
+#define PRT0_MAC_CORE_MAC_FC_FEC_STS_FEC_NCERR_SHIFT 16
+#define PRT0_MAC_CORE_MAC_FC_FEC_STS_FEC_NCERR_MASK 0xFF0000
+
+/* PRT0_MAC_CORE_MAC_FEC91_CFG */
+#define PRT0_MAC_CORE_MAC_FEC91_CFG_FEC91_ENA_IN_SHIFT 0
+#define PRT0_MAC_CORE_MAC_FEC91_CFG_FEC91_ENA_IN_MASK 0xF
+#define PRT0_MAC_CORE_MAC_FEC91_CFG_FEC91_KP_MODE_IN_SHIFT 4
+#define PRT0_MAC_CORE_MAC_FEC91_CFG_FEC91_KP_MODE_IN_MASK 0xF0
+#define PRT0_MAC_CORE_MAC_FEC91_CFG_FEC91_1LANE_IN0_SHIFT 9
+#define PRT0_MAC_CORE_MAC_FEC91_CFG_FEC91_1LANE_IN0_MASK 0x200
+#define PRT0_MAC_CORE_MAC_FEC91_CFG_FEC91_1LANE_IN2_SHIFT 10
+#define PRT0_MAC_CORE_MAC_FEC91_CFG_FEC91_1LANE_IN2_MASK 0x400
+
+/* PRT0_MAC_CORE_MAC_PCS_CFG */
+#define PRT0_MAC_CORE_MAC_PCS_CFG_PCS_FAST_LLANE_MODE_SHIFT 0
+#define PRT0_MAC_CORE_MAC_PCS_CFG_PCS_FAST_LLANE_MODE_MASK 0xF
+#define PRT0_MAC_CORE_MAC_PCS_CFG_PCS_RXLAUI_ENA_IN0_SHIFT 4
+#define PRT0_MAC_CORE_MAC_PCS_CFG_PCS_RXLAUI_ENA_IN0_MASK 0x10
+#define PRT0_MAC_CORE_MAC_PCS_CFG_PCS_RXLAUI_ENA_IN2_SHIFT 5
+#define PRT0_MAC_CORE_MAC_PCS_CFG_PCS_RXLAUI_ENA_IN2_MASK 0x20
+#define PRT0_MAC_CORE_MAC_PCS_CFG_PCS_PCS100_ENA_IN0_SHIFT 6
+#define PRT0_MAC_CORE_MAC_PCS_CFG_PCS_PCS100_ENA_IN0_MASK 0x40
+#define PRT0_MAC_CORE_MAC_PCS_CFG_PCS_PCS100_ENA_IN2_SHIFT 7
+#define PRT0_MAC_CORE_MAC_PCS_CFG_PCS_PCS100_ENA_IN2_MASK 0x80
+#define PRT0_MAC_CORE_MAC_PCS_CFG_PCS_MODE40_ENA_IN_SHIFT 8
+#define PRT0_MAC_CORE_MAC_PCS_CFG_PCS_MODE40_ENA_IN_MASK 0x100
+
+/* PRT0_MAC_CORE_MAC_GNRL_STS */
+#define PRT0_MAC_CORE_MAC_GNRL_STS_TX_OVR_ERR_SHIFT 0
+#define PRT0_MAC_CORE_MAC_GNRL_STS_TX_OVR_ERR_MASK 0x1
+#define PRT0_MAC_CORE_MAC_GNRL_STS_TX_UNDERFLOW_SHIFT 1
+#define PRT0_MAC_CORE_MAC_GNRL_STS_TX_UNDERFLOW_MASK 0x2
+#define PRT0_MAC_CORE_MAC_GNRL_STS_LOC_FAULT_SHIFT 2
+#define PRT0_MAC_CORE_MAC_GNRL_STS_LOC_FAULT_MASK 0x4
+#define PRT0_MAC_CORE_MAC_GNRL_STS_REM_FAULT_SHIFT 3
+#define PRT0_MAC_CORE_MAC_GNRL_STS_REM_FAULT_MASK 0x8
+#define PRT0_MAC_CORE_MAC_GNRL_STS_LI_FAULT_SHIFT 4
+#define PRT0_MAC_CORE_MAC_GNRL_STS_LI_FAULT_MASK 0x10
+
+/* PRT0_MAC_CORE_MAC_XOFF_CFG */
+#define PRT0_MAC_CORE_MAC_XOFF_CFG_MAC_SW_XOFF_GEN_OR_SHIFT 0
+#define PRT0_MAC_CORE_MAC_XOFF_CFG_MAC_SW_XOFF_GEN_OR_MASK 0xFF
+#define PRT0_MAC_CORE_MAC_XOFF_CFG_MAC_SW_XOFF_GEN_AND_SHIFT 8
+#define PRT0_MAC_CORE_MAC_XOFF_CFG_MAC_SW_XOFF_GEN_AND_MASK 0xFF00
+#define PRT0_MAC_CORE_MAC_XOFF_CFG_MAC_SW_XOFF_GEN_OVERRIDE_SHIFT 16
+#define PRT0_MAC_CORE_MAC_XOFF_CFG_MAC_SW_XOFF_GEN_OVERRIDE_MASK 0xFF0000
+
+/* PRT0_MAC_CORE_MAC_PAUSE_CFG */
+#define PRT0_MAC_CORE_MAC_PAUSE_CFG_MAC_SW_PAUSE_ON_OR_SHIFT 0
+#define PRT0_MAC_CORE_MAC_PAUSE_CFG_MAC_SW_PAUSE_ON_OR_MASK 0xFF
+#define PRT0_MAC_CORE_MAC_PAUSE_CFG_MAC_SW_PAUSE_ON_AND_SHIFT 8
+#define PRT0_MAC_CORE_MAC_PAUSE_CFG_MAC_SW_PAUSE_ON_AND_MASK 0xFF00
+#define PRT0_MAC_CORE_MAC_PAUSE_CFG_MAC_SW_PAUSE_ON_OVERRIDE_SHIFT 16
+#define PRT0_MAC_CORE_MAC_PAUSE_CFG_MAC_SW_PAUSE_ON_OVERRIDE_MASK 0xFF0000
+
+/* PRT0_MAC_CORE_MAC_RST_CFG */
+#define PRT0_MAC_CORE_MAC_RST_CFG_SD_RX_SW_RST_N_SHIFT 0
+#define PRT0_MAC_CORE_MAC_RST_CFG_SD_RX_SW_RST_N_MASK 0xF
+#define PRT0_MAC_CORE_MAC_RST_CFG_SD_TX_SW_RST_N_SHIFT 4
+#define PRT0_MAC_CORE_MAC_RST_CFG_SD_TX_SW_RST_N_MASK 0xF0
+#define PRT0_MAC_CORE_MAC_RST_CFG_MAC_PRT_SW_RST_N_SHIFT 8
+#define PRT0_MAC_CORE_MAC_RST_CFG_MAC_PRT_SW_RST_N_MASK 0x100
+#define PRT0_MAC_CORE_MAC_RST_CFG_MAC_REF_SW_RST_N_SHIFT 9
+#define PRT0_MAC_CORE_MAC_RST_CFG_MAC_REF_SW_RST_N_MASK 0x200
+#define PRT0_MAC_CORE_MAC_RST_CFG_MAC_REG_SW_RST_N_SHIFT 10
+#define PRT0_MAC_CORE_MAC_RST_CFG_MAC_REG_SW_RST_N_MASK 0x400
+
+/* PRT0_MAC_CORE_MAC_TS */
+#define PRT0_MAC_CORE_MAC_TS_PRESCALE_SHIFT 0
+#define PRT0_MAC_CORE_MAC_TS_PRESCALE_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_PRT0_MAC_CORE_MASKS_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/prt0_mac_core_regs.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/prt0_mac_core_regs.h
new file mode 100644
index 000000000000..997ff9c5c08c
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/prt0_mac_core_regs.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_PRT0_MAC_CORE_REGS_H_
+#define ASIC_REG_PRT0_MAC_CORE_REGS_H_
+
+/*****************************************
+ * PRT0_MAC_CORE
+ * (Prototype: PRT_MAC_CORE)
+ *****************************************
+ */
+
+#define PRT0_MAC_CORE_MAC_SD_CFG 0x5469000
+
+#define PRT0_MAC_CORE_MAC_SD_STS 0x5469004
+
+#define PRT0_MAC_CORE_MAC_REC_STS0 0x5469008
+
+#define PRT0_MAC_CORE_MAC_REC_STS1 0x546900C
+
+#define PRT0_MAC_CORE_MAC_FC_FEC_CFG 0x5469010
+
+#define PRT0_MAC_CORE_MAC_FC_FEC_STS 0x5469014
+
+#define PRT0_MAC_CORE_MAC_FEC91_CFG 0x5469018
+
+#define PRT0_MAC_CORE_MAC_PCS_CFG 0x546901C
+
+#define PRT0_MAC_CORE_MAC_GNRL_STS_0 0x5469020
+
+#define PRT0_MAC_CORE_MAC_GNRL_STS_1 0x5469024
+
+#define PRT0_MAC_CORE_MAC_GNRL_STS_2 0x5469028
+
+#define PRT0_MAC_CORE_MAC_GNRL_STS_3 0x546902C
+
+#define PRT0_MAC_CORE_MAC_XOFF_CFG_0 0x5469030
+
+#define PRT0_MAC_CORE_MAC_XOFF_CFG_1 0x5469034
+
+#define PRT0_MAC_CORE_MAC_XOFF_CFG_2 0x5469038
+
+#define PRT0_MAC_CORE_MAC_XOFF_CFG_3 0x546903C
+
+#define PRT0_MAC_CORE_MAC_PAUSE_CFG_0 0x5469040
+
+#define PRT0_MAC_CORE_MAC_PAUSE_CFG_1 0x5469044
+
+#define PRT0_MAC_CORE_MAC_PAUSE_CFG_2 0x5469048
+
+#define PRT0_MAC_CORE_MAC_PAUSE_CFG_3 0x546904C
+
+#define PRT0_MAC_CORE_MAC_RST_CFG 0x5469050
+
+#define PRT0_MAC_CORE_MAC_TS 0x5469054
+
+#endif /* ASIC_REG_PRT0_MAC_CORE_REGS_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* [PATCH 08/15] net: hbl_cn: gaudi2: ASIC specific support
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
` (6 preceding siblings ...)
2024-06-13 8:22 ` [PATCH 07/15] net: hbl_cn: gaudi2: ASIC register header files Omer Shpigelman
@ 2024-06-13 8:22 ` Omer Shpigelman
2024-06-13 8:22 ` [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver Omer Shpigelman
` (8 subsequent siblings)
16 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:22 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
Add GAUDI2 ASIC support which includes HW specific configurations and
operations.
It is initialized on top of the common device layer and has dedicated data
structures which are passed via auxiliary bus.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
MAINTAINERS | 1 +
drivers/net/ethernet/intel/hbl_cn/Makefile | 3 +
.../net/ethernet/intel/hbl_cn/common/hbl_cn.c | 2 +
.../net/ethernet/intel/hbl_cn/common/hbl_cn.h | 2 +
.../net/ethernet/intel/hbl_cn/gaudi2/Makefile | 3 +
.../ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.c | 5689 +++++++++++++++++
.../ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.h | 427 ++
.../intel/hbl_cn/gaudi2/gaudi2_cn_debugfs.c | 319 +
.../intel/hbl_cn/gaudi2/gaudi2_cn_eq.c | 732 +++
.../intel/hbl_cn/gaudi2/gaudi2_cn_phy.c | 2743 ++++++++
include/linux/net/intel/gaudi2.h | 432 ++
include/linux/net/intel/gaudi2_aux.h | 94 +
12 files changed, 10447 insertions(+)
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/Makefile
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.c
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.h
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_debugfs.c
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_eq.c
create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_phy.c
create mode 100644 include/linux/net/intel/gaudi2.h
create mode 100644 include/linux/net/intel/gaudi2_aux.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 906224204aba..096439a62129 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9615,6 +9615,7 @@ F: Documentation/networking/device_drivers/ethernet/intel/hbl.rst
F: drivers/net/ethernet/intel/hbl_cn/
F: include/linux/habanalabs/
F: include/linux/net/intel/cn*
+F: include/linux/net/intel/gaudi2*
HACKRF MEDIA DRIVER
L: linux-media@vger.kernel.org
diff --git a/drivers/net/ethernet/intel/hbl_cn/Makefile b/drivers/net/ethernet/intel/hbl_cn/Makefile
index c2c4142f18a0..836b7f7824b4 100644
--- a/drivers/net/ethernet/intel/hbl_cn/Makefile
+++ b/drivers/net/ethernet/intel/hbl_cn/Makefile
@@ -8,4 +8,7 @@ obj-$(CONFIG_HABANA_CN) := habanalabs_cn.o
include $(src)/common/Makefile
habanalabs_cn-y += $(HBL_CN_COMMON_FILES)
+include $(src)/gaudi2/Makefile
+habanalabs_cn-y += $(HBL_CN_GAUDI2_FILES)
+
habanalabs_cn-$(CONFIG_DEBUG_FS) += common/hbl_cn_debugfs.o
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
index fc7bd6474404..b493b681a3b2 100644
--- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
@@ -1747,6 +1747,8 @@ static int hbl_cn_set_asic_funcs(struct hbl_cn_device *hdev)
{
switch (hdev->asic_type) {
case HBL_ASIC_GAUDI2:
+ gaudi2_cn_set_asic_funcs(hdev);
+ break;
default:
dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type);
return -EINVAL;
diff --git a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.h b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.h
index 0b96cd3db719..0627a2aa6f0c 100644
--- a/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.h
+++ b/drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.h
@@ -1644,6 +1644,8 @@ void hbl_cn_fw_status_work(struct work_struct *work);
int hbl_cn_get_src_ip(struct hbl_cn_port *cn_port, u32 *src_ip);
void hbl_cn_ctx_resources_destroy(struct hbl_cn_device *hdev, struct hbl_cn_ctx *ctx);
+void gaudi2_cn_set_asic_funcs(struct hbl_cn_device *hdev);
+
int __hbl_cn_ports_reopen(struct hbl_cn_device *hdev);
void __hbl_cn_hard_reset_prepare(struct hbl_cn_device *hdev, bool fw_reset, bool in_teardown);
void __hbl_cn_stop(struct hbl_cn_device *hdev);
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/Makefile b/drivers/net/ethernet/intel/hbl_cn/gaudi2/Makefile
new file mode 100644
index 000000000000..889776350452
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+HBL_CN_GAUDI2_FILES := gaudi2/gaudi2_cn.o gaudi2/gaudi2_cn_phy.o \
+ gaudi2/gaudi2_cn_eq.o gaudi2/gaudi2_cn_debugfs.o
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.c b/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.c
new file mode 100644
index 000000000000..a1b01c729c31
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.c
@@ -0,0 +1,5689 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "gaudi2_cn.h"
+
+#include <linux/circ_buf.h>
+#include <linux/units.h>
+
+#define CFG_BAR_ID 0
+
+#define GAUDI2_NIC_WTD_BP_UPPER_TH_DIFF 24
+#define GAUDI2_NIC_WTD_BP_LOWER_TH_DIFF 26
+#define GAUDI2_NIC_MIN_WQ_SIZE_BP_ENABLED 32
+#define GAUDI2_NIC_MTU_DEFAULT SZ_8K /* 8KB */
+#define QPC_SANITY_CHECK_INTERVAL_MS 1 /* 1 msec */
+#define NIC_TMR_TIMEOUT_PLDM_US 1000 /* 1 msec */
+#define NIC_TMR_TIMEOUT_PLDM_GRAN 7 /* 512 us */
+
+#define PERF_BW_WINDOW_MSEC 100
+#define PERF_BW_WINDOW_USEC (PERF_BW_WINDOW_MSEC * USEC_PER_MSEC)
+/* Convert bytes per window into gigabytes per second */
+#define PERF_BW_WINDOW_DIV ((GIGA * PERF_BW_WINDOW_MSEC) / MSEC_PER_SEC)
+
+#define IPV4_PROTOCOL_UDP 17
+#define DUMMY_UDP_PORT 8224
+#define GAUDI2_USER_ENCAP_ID 0
+
+#define GAUDI2_PFC_PRIO_DRIVER 0
+#define GAUDI2_PFC_PRIO_USER_BASE 1
+
+#define GAUDI2_NIC_MAX_CONG_WND BIT(23)
+#define GAUDI2_NIC_MAX_SPEED SPEED_100000
+
+#define RETRY_COUNT_QPC_SANITY 10
+#define GAUDI2_NIC_MAX_TIMEOUT_RETRIES 0xFE
+#define GAUDI2_NIC_MAX_SEQ_ERR_RETRIES 0xFE
+
+/* Actual mask used by HW is smaller than the one declared in
+ * NIC0_QPC0_WQ_BP_2ARC_ADDR_VAL_MASK and NIC0_QPC0_WQ_BP_2QMAN_ADDR_VAL_MASK
+ */
+#define WQ_BP_ADDR_VAL_MASK 0x7FFFFFF
+
+/* User encapsulation 32 bit register offset. */
+#define encap_offset(id) ((id) * 4)
+
+/* We have fixed mapping between SW and HW IDs. */
+#define db_fifo_hw_id(id) ((id) - 1)
+
+/* User doorbell fifo 32 bit register offset. */
+#define db_fifo_offset(id) (db_fifo_hw_id(id) * 4)
+
+/* User doorbell fifo 64 bit register offset. */
+#define db_fifo_offset64(id) (db_fifo_hw_id(id) * 8)
+
+static int gaudi2_cn_ctx_init(struct hbl_cn_ctx *ctx);
+static void gaudi2_cn_ctx_fini(struct hbl_cn_ctx *ctx);
+static void gaudi2_qp_sanity_fini(struct gaudi2_cn_port *gaudi2_port);
+static int gaudi2_qp_sanity_init(struct gaudi2_cn_port *gaudi2_port);
+static void gaudi2_get_default_encap_id(struct hbl_cn_port *cn_port, u32 *id);
+static int gaudi2_encap_set(struct hbl_cn_port *cn_port, u32 encap_id,
+ struct hbl_cn_encap_xarray_pdata *xa_pdata);
+static void gaudi2_user_cq_set_overrun(struct hbl_cn_user_cq *user_cq, bool set_overrun);
+static int gaudi2_cn_poll_reg(struct hbl_cn_device *hdev, u32 reg, u64 timeout_us,
+ hbl_cn_poll_cond_func func, void *arg);
+
+enum gaudi2_cn_user_bp_offs {
+ HBL_CNI_USER_BP_OFFS_FW,
+ HBL_CNI_USER_BP_OFFS_QMAN
+};
+
+struct gaudi2_cn_stat {
+ char str[ETH_GSTRING_LEN];
+};
+
+static struct gaudi2_cn_stat gaudi2_cn_err_stats[] = {
+ {"Congestion Q err"},
+ {"Eth DB fifo overrun"}
+};
+
+/* Gaudi2 FEC (Fwd Error Correction) Stats */
+static struct gaudi2_cn_stat gaudi2_cn_mac_fec_stats[] = {
+ {"cw_corrected_accum"},
+ {"cw_uncorrect_accum"},
+ {"cw_corrected"},
+ {"cw_uncorrect"},
+ {"symbol_err_corrected_lane_0"},
+ {"symbol_err_corrected_lane_1"},
+ {"symbol_err_corrected_lane_2"},
+ {"symbol_err_corrected_lane_3"},
+ {"pre_FEC_SER_int"},
+ {"pre_FEC_SER_exp (negative)"},
+ {"post_FEC_SER_int"},
+ {"post_FEC_SER_exp (negative)"},
+};
+
+/* Gaudi2 performance Stats */
+static struct gaudi2_cn_stat gaudi2_cn_perf_stats[] = {
+ {"bandwidth_gbps_int"},
+ {"bandwidth_gbps_frac"},
+ {"last_data_latency_usec_int"},
+ {"last_data_latency_usec_frac"},
+};
+
+static size_t gaudi2_cn_err_stats_len = ARRAY_SIZE(gaudi2_cn_err_stats);
+static size_t gaudi2_cn_mac_fec_stats_len = ARRAY_SIZE(gaudi2_cn_mac_fec_stats);
+static size_t gaudi2_cn_perf_stats_len = ARRAY_SIZE(gaudi2_cn_perf_stats);
+
+#define GAUDI2_SYNDROME_TYPE(syndrome) (((syndrome) >> 6) & 0x3)
+#define GAUDI2_MAX_SYNDROME_STRING_LEN 256
+#define GAUDI2_MAX_SYNDROME_TYPE 3
+
+#define GAUDI2_NUM_OF_NIC_RXB_CORE_SEI_CAUSE 2
+#define GAUDI2_NUM_OF_NIC_RXB_CORE_SPI_CAUSE 6
+#define GAUDI2_NUM_OF_NIC_RXE_SEI_CAUSE 4
+#define GAUDI2_NUM_OF_NIC_RXE_SPI_CAUSE 24
+#define GAUDI2_NUM_OF_NIC_QPC_RESP_ERR_CAUSE 7
+
+static const char * const
+gaudi2_cn_rxb_core_sei_interrupts_cause[GAUDI2_NUM_OF_NIC_RXB_CORE_SEI_CAUSE] = {
+ "HBW RRESP error",
+ "LBW RRESP error"
+};
+
+static const char * const
+gaudi2_cn_rxb_core_spi_interrupts_cause[GAUDI2_NUM_OF_NIC_RXB_CORE_SPI_CAUSE] = {
+ "Packet dropped due to no available buffers",
+ "Control pointers count illegal port 0",
+ "Control pointers count illegal port 1",
+ "Control pointers count illegal port 2",
+ "Control pointers count illegal port 3",
+ "Scatter pointers count illegal"
+};
+
+static const char * const
+gaudi2_cn_qpc_resp_err_interrupts_cause[GAUDI2_NUM_OF_NIC_QPC_RESP_ERR_CAUSE] = {
+ "ARC SEI error",
+ "QPC LBW AXI write slv decode err",
+ "QPC LBW AXI write slv err",
+ "QPC HBW AXI write slv decode err",
+ "QPC HBW AXI write slv err",
+ "QPC HBW AXI read slv decode err",
+ "QPC HBW AXI read slv err"
+};
+
+static const char * const gaudi2_cn_rxe_sei_interrupts_cause[GAUDI2_NUM_OF_NIC_RXE_SEI_CAUSE] = {
+ "HBW RRESP error WQE",
+ "HBW RRESP error FNA",
+ "LBW BRESP error",
+ "HBW BRESP error"
+};
+
+static const char * const gaudi2_cn_rxe_spi_interrupts_cause[GAUDI2_NUM_OF_NIC_RXE_SPI_CAUSE] = {
+ "QP invalid",
+ "TS mismatch",
+ "Request CS invalid",
+ "Response CS invalid",
+ "Request PSN invalid",
+ "Request PSN unsent",
+ "Response RKEY invalid",
+ "Response RESYNC invalid",
+ "Packet bad format",
+ "Invalid opcode",
+ "Invalid syndrome",
+ "Invalid min packet size RC",
+ "Invalid max packet size RC",
+ "Invalid min packet size raw",
+ "Invalid max packet size raw",
+ "Tunnel invalid",
+ "WQE index mismatch",
+ "WQ WR opcode invalid",
+ "WQ RDV opcode invalid",
+ "WQ RD opcode invalid",
+ "WQE WR zero",
+ "WQE multi zero",
+ "WQE WE send big",
+ "WQE multi big"
+};
+
+static char qp_syndromes[NIC_MAX_QP_ERR_SYNDROMES][GAUDI2_MAX_SYNDROME_STRING_LEN] = {
+ /* Rx packet errors*/
+ [0x1] = "[RX] pkt err, pkt bad format",
+ [0x2] = "[RX] pkt err, pkt tunnel invalid",
+ [0x3] = "[RX] pkt err, BTH opcode invalid",
+ [0x4] = "[RX] pkt err, syndrome invalid",
+ [0x5] = "[RX] pkt err, Reliable QP max size invalid",
+ [0x6] = "[RX] pkt err, Reliable QP min size invalid",
+ [0x7] = "[RX] pkt err, Raw min size invalid",
+ [0x8] = "[RX] pkt err, Raw max size invalid",
+ [0x9] = "[RX] pkt err, QP invalid",
+ [0xa] = "[RX] pkt err, Transport Service mismatch",
+ [0xb] = "[RX] pkt err, QPC Requester QP state invalid",
+ [0xc] = "[RX] pkt err, QPC Responder QP state invalid",
+ [0xd] = "[RX] pkt err, QPC Responder resync invalid",
+ [0xe] = "[RX] pkt err, QPC Requester PSN invalid",
+ [0xf] = "[RX] pkt err, QPC Requester PSN unset",
+ [0x10] = "[RX] pkt err, QPC Responder RKEY invalid",
+ [0x11] = "[RX] pkt err, WQE index mismatch",
+ [0x12] = "[RX] pkt err, WQE write opcode invalid",
+ [0x13] = "[RX] pkt err, WQE Rendezvous opcode invalid",
+ [0x14] = "[RX] pkt err, WQE Read opcode invalid",
+ [0x15] = "[RX] pkt err, WQE Write Zero",
+ [0x16] = "[RX] pkt err, WQE multi zero",
+ [0x17] = "[RX] pkt err, WQE Write send big",
+ [0x18] = "[RX] pkt err, WQE multi big",
+
+ /* QPC errors */
+ [0x40] = "[qpc] [TMR] max-retry-cnt exceeded",
+ [0x41] = "[qpc] [req DB] QP not valid",
+ [0x42] = "[qpc] [req DB] security check",
+ [0x43] = "[qpc] [req DB] PI > last-index",
+ [0x44] = "[qpc] [req DB] wq-type is READ",
+ [0x45] = "[qpc] [req TX] QP not valid",
+ [0x46] = "[qpc] [req TX] Rendezvous WQE but wq-type is not WRITE",
+ [0x47] = "[qpc] [req RX] QP not valid",
+ [0x48] = "[qpc] [req RX] max-retry-cnt exceeded",
+ [0x49] = "[qpc] [req RDV] QP not valid",
+ [0x4a] = "[qpc] [req RDV] wrong wq-type",
+ [0x4b] = "[qpc] [req RDV] PI > last-index",
+ [0x4c] = "[qpc] [res TX] QP not valid",
+ [0x4d] = "[qpc] [res RX] QP not valid",
+
+ /* tx packet error */
+ [0x80] = "[TX] pkt error, QPC.wq_type is write does not support WQE.opcode",
+ [0x81] = "[TX] pkt error, QPC.wq_type is rendezvous does not support WQE.opcode",
+ [0x82] = "[TX] pkt error, QPC.wq_type is read does not support WQE.opcode",
+ [0x83] = "[TX] pkt error, QPC.gaudi1 is set does not support WQE.opcode",
+ [0x84] = "[TX] pkt error, WQE.opcode is write but WQE.size is 0",
+ [0x85] =
+ "[TX] pkt error, WQE.opcode is multi-stride|local-stride|multi-dual but WQE.size is 0",
+ [0x86] = "[TX] pkt error, WQE.opcode is send but WQE.size is 0",
+ [0x87] = "[TX] pkt error, WQE.opcode is rendezvous-write|rendezvous-read but WQE.size is 0",
+ [0x88] = "[TX] pkt error, WQE.opcode is write but size > configured max-write-send-size",
+ [0x89] =
+ "[TX] pkt error, WQE.opcode is multi-stride|local-stride|multi-dual but size > configured max-stride-size",
+ [0x8a] =
+ "[TX] pkt error, WQE.opcode is rendezvous-write|rendezvous-read but QPC.remote_wq_log_size <= configured min-remote-log-size",
+ [0x8b] =
+ "[TX] pkt error, WQE.opcode is rendezvous-write but WQE.size != configured rdv-wqe-size (per granularity)",
+ [0x8c] =
+ "[TX] pkt error, WQE.opcode is rendezvous-read but WQE.size != configured rdv-wqe-size (per granularity)",
+ [0x8d] =
+ "[TX] pkt error, WQE.inline is set but WQE.size != configured inline-wqe-size (per granularity)",
+ [0x8e] = "[TX] pkt error, QPC.gaudi1 is set but WQE.inline is set",
+ [0x8f] =
+ "[TX] pkt error, WQE.opcode is multi-stride|local-stride|multi-dual but QPC.swq_granularity is 0",
+ [0x90] = "[TX] pkt error, WQE.opcode != NOP but WQE.reserved0 != 0",
+ [0x91] = "[TX] pkt error, WQE.opcode != NOP but WQE.wqe_index != execution-index [7.0]",
+ [0x92] =
+ "[TX] pkt error, WQE.opcode is multi-stride|local-stride|multi-dual but WQE.size < stride-size",
+ [0x93] =
+ "[TX] pkt error, WQE.reduction_opcode is upscale but WQE.remote_address LSB is not 0",
+ [0x94] = "[TX] pkt error, WQE.reduction_opcode is upscale but does not support WQE.opcode",
+ [0x95] = "[TX] pkt error, RAW packet but WQE.size not supported",
+ [0xB0] = "WQE.opcode is QoS but WQE.inline is set",
+ [0xB1] = "WQE.opcode above 15",
+ [0xB2] = "RAW above MIN",
+ [0xB3] = "RAW below MAX",
+ [0xB4] = "WQE.reduction is disable but reduction-opcode is not 0",
+ [0xB5] = "WQE.opcode is READ-RDV but WQE.inline is set",
+ [0xB6] = "WQE fetch WR size not 4",
+ [0xB7] = "WQE fetch WR addr not mod4",
+ [0xB8] = "RDV last-index",
+ [0xB9] = "Gaudi1 multi-dual",
+ [0xBA] = "WQE bad opcode",
+ [0xBB] = "WQE bad size",
+ [0xBC] = "WQE SE not RAW",
+ [0xBD] = "Gaudi1 tunnal",
+ [0xBE] = "Tunnel 0-size",
+ [0xBF] = "Tunnel max size",
+};
+
+char *gaudi2_cn_qp_err_syndrome_to_str(u32 syndrome)
+{
+ int syndrome_type;
+ char *str;
+
+ /* syndrome comprised from 8 bits
+ * [2:type, 6:syndrome]
+ * 6 bits for syndrome
+ * 2 bits for type
+ * 0 - rx packet error
+ * 1 - qp error
+ * 2 - tx packet error
+ */
+
+ if (syndrome >= NIC_MAX_QP_ERR_SYNDROMES)
+ return "syndrome unknown";
+
+ syndrome_type = GAUDI2_SYNDROME_TYPE(syndrome);
+
+ str = qp_syndromes[syndrome];
+ if (strlen(str))
+ return str;
+
+ switch (syndrome_type) {
+ case 0:
+ str = "RX packet syndrome unknown";
+ break;
+ case 1:
+ str = "QPC syndrome unknown";
+ break;
+ case 2:
+ str = "TX packet syndrome unknown";
+ break;
+ default:
+ str = "syndrome unknown";
+ break;
+ }
+
+ return str;
+}
+
+static void db_fifo_toggle_err_evt(struct hbl_cn_port *cn_port, bool enable)
+{
+ u32 mask = NIC0_QPC0_REQ_STATIC_CONFIG_QM_PUSH_TO_ERR_FIFO_NON_V_MASK |
+ NIC0_QPC0_REQ_STATIC_CONFIG_QM_PUSH_ERR_PI_EX_LAST_MASK;
+ u32 val = enable ? (mask >> __ffs(mask)) : 0;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+
+ NIC_RMWREG32_SHIFTED(NIC0_QPC0_REQ_STATIC_CONFIG, val, mask);
+}
+
+static void __gaudi2_cn_get_db_fifo_umr(struct hbl_cn_port *cn_port, u32 block_id, u32 offset_id,
+ u64 *umr_block_addr, u32 *umr_db_offset)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port, odd_db_offset;
+ struct gaudi2_cn_device *gaudi2;
+
+ gaudi2 = hdev->asic_specific;
+ odd_db_offset = NIC0_UMR0_0_UNSECURE_DOORBELL1_UNSECURE_DB_FIRST32 -
+ NIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32;
+
+ /* UMR base address we map to userspace */
+ *umr_block_addr = gaudi2->cfg_base +
+ NIC_CFG_BASE(port, NIC0_UMR0_0_UNSECURE_DOORBELL0_BASE) +
+ NIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + (block_id * NIC_UMR_OFFSET);
+
+ /* Each UMR block hosts 2 doorbell fifos. Get byte offset. */
+ *umr_db_offset = (offset_id & 1) ? odd_db_offset : 0;
+}
+
+static void gaudi2_cn_get_db_fifo_umr(struct hbl_cn_port *cn_port, u32 id, u64 *umr_block_addr,
+ u32 *umr_db_offset)
+{
+ __gaudi2_cn_get_db_fifo_umr(cn_port, db_fifo_hw_id(id) / 2, db_fifo_hw_id(id),
+ umr_block_addr, umr_db_offset);
+}
+
+static void db_fifo_push_dummy(struct hbl_cn_port *cn_port, u32 id, int n_dummy, bool is_eth)
+{
+ u32 port, umr_db_offset, offset_0_31, offset_32_64, db_dummy[2];
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct gaudi2_cn_device *gaudi2;
+ u64 umr_block_addr;
+ int i;
+
+ gaudi2 = hdev->asic_specific;
+ port = cn_port->port;
+
+ /* 8 bytes dummy doorbell packet with unused QP ID. */
+ db_dummy[0] = 0;
+ db_dummy[1] = NIC_MAX_QP_NUM;
+
+ /* Get DB fifo offset in register configuration space. */
+ gaudi2_cn_get_db_fifo_umr(cn_port, id, &umr_block_addr, &umr_db_offset);
+ offset_0_31 = umr_block_addr - gaudi2->cfg_base + umr_db_offset;
+ offset_32_64 = offset_0_31 + (NIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_SECOND32 -
+ NIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32);
+
+ /* Split user doorbell fifo packets to fit 32 bit registers. */
+ for (i = 0; i < n_dummy; i++)
+ if (is_eth) {
+ NIC_WREG32(NIC0_QPC0_SECURED_DB_FIRST32, db_dummy[0]);
+ NIC_WREG32(NIC0_QPC0_SECURED_DB_SECOND32, db_dummy[1]);
+ } else {
+ WREG32(offset_0_31, db_dummy[0]);
+ WREG32(offset_32_64, db_dummy[1]);
+ }
+
+ if (gaudi2->flush_db_fifo) {
+ if (is_eth)
+ NIC_RREG32(NIC0_QPC0_SECURED_DB_FIRST32);
+ else
+ RREG32(offset_0_31);
+ }
+}
+
+static bool db_fifo_reset_cond_func1(u32 val, void *arg)
+{
+ return val;
+}
+
+static bool db_fifo_reset_cond_func2(u32 val, void *arg)
+{
+ return val == (NIC_FIFO_DB_SIZE - 1);
+}
+
+/* Doorbell fifo H/W bug. There is no provision for S/W to reset H/W CI.
+ * Hence, we implement workaround. Push dummy doorbells to db fifos till
+ * CI wraps.
+ */
+static void __db_fifo_reset(struct hbl_cn_port *cn_port, u32 *ci_cpu_addr, u32 id, bool is_eth)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct gaudi2_cn_aux_ops *gaudi2_aux_ops;
+ struct hbl_cn_aux_ops *aux_ops;
+ u32 ci = *ci_cpu_addr, port;
+ struct hbl_aux_dev *aux_dev;
+ int rc;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ gaudi2_aux_ops = aux_ops->asic_ops;
+
+ /* no need to push dummy doorbells, as the hard will reset itself. However, reset the memory
+ * where the last CI is stored at.
+ */
+ if (!hdev->operational) {
+ *ci_cpu_addr = 0;
+ return;
+ }
+
+ port = cn_port->port;
+
+ /* Stop HW from throwing below error events.
+ * 1. Requester DB, invalid QP
+ * 2. Requester DB, PI > last WQ index
+ *
+ * Dummy doorbell piggybacks on the idea that HW updates CI
+ * even for invalid doorbells. However, EQ error events are
+ * generated and fifo is pushed to error state.
+ */
+ db_fifo_toggle_err_evt(cn_port, false);
+
+ /* 1. Another User doorbell fifo HW bug. CI updated by HW is one
+ * less than number of doorbells pushed.
+ * 2. We cannot assert if user has pushed any doorbells. i.e
+ * CI buffer is default 0 or HW updated zero.
+ *
+ * To handle above scenario we push 2 dummy doorbells if CI is zero.
+ * This forces HW to update CI buffer. Hence, ensuring we are not
+ * dealing with default zero memory.
+ * Note, driver ensures CI buffer is zeroed out before passing it on to HW.
+ */
+ if (!ci) {
+ db_fifo_push_dummy(cn_port, id, 2, is_eth);
+
+ rc = gaudi2_aux_ops->poll_mem(aux_dev, ci_cpu_addr, &ci, db_fifo_reset_cond_func1);
+ if (rc && !ci)
+ dev_err(hdev->dev, "Doorbell fifo reset timed out\n");
+ }
+
+ /* Push dummy doorbells such that HW CI points to fifo base. */
+ db_fifo_push_dummy(cn_port, id, NIC_FIFO_DB_SIZE - ci - 1, is_eth);
+
+ /* Wait for HW to absorb dummy doorbells and update CI. */
+ rc = gaudi2_aux_ops->poll_mem(aux_dev, ci_cpu_addr, &ci, db_fifo_reset_cond_func2);
+ if (rc && (ci != (NIC_FIFO_DB_SIZE - 1)))
+ dev_err(hdev->dev, "Doorbell fifo reset timed out, ci: %d\n", ci);
+
+ db_fifo_toggle_err_evt(cn_port, true);
+
+ /* Zero out HW CI buffer address register for added safety. */
+ if (is_eth) {
+ NIC_WREG32(NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_DBFIFO_CI_UPD_ADDR_31_7, 0);
+ NIC_WREG32(NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_DBFIFO_CI_UPD_ADDR_63_32, 0);
+ } else {
+ NIC_WREG32(NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_DBFIFO_CI_UPD_ADDR_31_7 +
+ db_fifo_offset64(id), 0);
+ NIC_WREG32(NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_DBFIFO_CI_UPD_ADDR_63_32 +
+ db_fifo_offset64(id), 0);
+ }
+}
+
+static void gaudi2_cn_db_fifo_reset(struct hbl_aux_dev *aux_dev, u32 port)
+{
+ struct hbl_cn_device *hdev = container_of(aux_dev, struct hbl_cn_device, en_aux_dev);
+ struct hbl_cn_port *cn_port = &hdev->cn_ports[port];
+ struct gaudi2_cn_port *gaudi2_port;
+ u32 *ci_cpu_addr;
+
+ gaudi2_port = cn_port->cn_specific;
+ ci_cpu_addr = (u32 *)RING_BUF_ADDRESS(&gaudi2_port->fifo_ring);
+
+ gaudi2_port->db_fifo_pi = 0;
+
+ __db_fifo_reset(cn_port, ci_cpu_addr, 0, true);
+}
+
+static int gaudi2_cn_config_wqe_asid(struct hbl_cn_port *cn_port, u32 asid, bool set_asid)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+ int rc;
+
+ rc = hbl_cn_send_cpucp_packet(hdev, port, set_asid ? CPUCP_PACKET_NIC_WQE_ASID_SET :
+ CPUCP_PACKET_NIC_WQE_ASID_UNSET, asid);
+ if (rc)
+ dev_err(hdev->dev, "Failed to %s WQE ASID, port %d, rc %d\n",
+ set_asid ? "set" : "unset", port, rc);
+
+ return rc;
+}
+
+static int gaudi2_cn_disable_wqe_index_checker(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+ int rc;
+
+ rc = hbl_cn_send_cpucp_packet(hdev, port, CPUCP_PACKET_NIC_SET_CHECKERS,
+ RX_WQE_IDX_MISMATCH);
+
+ if (rc) {
+ dev_err(hdev->dev,
+ "Failed to disable Rx WQE idx mismatch checker, port %d, rc %d\n", port,
+ rc);
+ return rc;
+ }
+
+ rc = hbl_cn_send_cpucp_packet(hdev, port, CPUCP_PACKET_NIC_SET_CHECKERS,
+ TX_WQE_IDX_MISMATCH);
+ if (rc) {
+ dev_err(hdev->dev,
+ "Failed to disable Tx WQE idx mismatch checker, port %d, rc %d\n", port,
+ rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static void *gaudi2_cn_dma_alloc_coherent(struct hbl_cn_device *hdev, size_t size,
+ dma_addr_t *dma_handle, gfp_t flag)
+{
+ const struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ struct hbl_aux_dev *aux_dev = hdev->cn_aux_dev;
+
+ return gaudi2->cn_aux_ops->dma_alloc_coherent(aux_dev, size, dma_handle, flag);
+}
+
+static void gaudi2_cn_dma_free_coherent(struct hbl_cn_device *hdev, size_t size, void *cpu_addr,
+ dma_addr_t dma_handle)
+{
+ const struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ struct hbl_aux_dev *aux_dev = hdev->cn_aux_dev;
+
+ gaudi2->cn_aux_ops->dma_free_coherent(aux_dev, size, cpu_addr, dma_handle);
+}
+
+static void *gaudi2_cn_dma_pool_zalloc(struct hbl_cn_device *hdev, size_t size, gfp_t mem_flags,
+ dma_addr_t *dma_handle)
+{
+ const struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ struct hbl_aux_dev *aux_dev = hdev->cn_aux_dev;
+
+ return gaudi2->cn_aux_ops->dma_pool_zalloc(aux_dev, size, mem_flags, dma_handle);
+}
+
+static void gaudi2_cn_dma_pool_free(struct hbl_cn_device *hdev, void *vaddr, dma_addr_t dma_addr)
+{
+ const struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ struct hbl_aux_dev *aux_dev = hdev->cn_aux_dev;
+
+ gaudi2->cn_aux_ops->dma_pool_free(aux_dev, vaddr, dma_addr);
+}
+
+static int gaudi2_cn_send_cpu_message(struct hbl_cn_device *hdev, u32 *msg, u16 len, u32 timeout,
+ u64 *result)
+{
+ struct gaudi2_cn_aux_ops *gaudi2_aux_ops;
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ gaudi2_aux_ops = aux_ops->asic_ops;
+
+ return gaudi2_aux_ops->send_cpu_message(aux_dev, msg, len, timeout, result);
+}
+
+static int gaudi2_cn_poll_reg(struct hbl_cn_device *hdev, u32 reg, u64 timeout_us,
+ hbl_cn_poll_cond_func func, void *arg)
+{
+ struct gaudi2_cn_aux_ops *gaudi2_aux_ops;
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ gaudi2_aux_ops = aux_ops->asic_ops;
+
+ return gaudi2_aux_ops->poll_reg(aux_dev, reg, timeout_us, func, arg);
+}
+
+static int gaudi2_cn_alloc_cq_rings(struct gaudi2_cn_port *gaudi2_port)
+{
+ u32 elem_size, queue_size, total_queues_size, count;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ struct hbl_cn_ring *ring;
+ dma_addr_t dma_addr;
+ void *cpu_addr;
+ int rc, i;
+
+ elem_size = sizeof(struct gaudi2_cqe);
+ count = NIC_CQ_MAX_ENTRIES;
+ queue_size = elem_size * count;
+ total_queues_size = queue_size * GAUDI2_NIC_MAX_CQS_NUM;
+
+ /* The HW expects that all CQs will be located in a physically consecutive memory one after
+ * the other. Hence we allocate all of them in one chunk.
+ */
+ cpu_addr = hbl_cn_dma_alloc_coherent(hdev, total_queues_size, &dma_addr, GFP_KERNEL);
+ if (!cpu_addr)
+ return -ENOMEM;
+
+ for (i = 0; i < NIC_CQS_NUM; i++) {
+ ring = &gaudi2_port->cq_rings[i];
+ RING_BUF_ADDRESS(ring) = cpu_addr + i * queue_size;
+ RING_BUF_DMA_ADDRESS(ring) = dma_addr + i * queue_size;
+ /* prevent freeing memory fragments by individual Qs */
+ RING_BUF_SIZE(ring) = i ? 0 : total_queues_size;
+ ring->count = count;
+ ring->elem_size = elem_size;
+ ring->asid = hdev->kernel_asid;
+ }
+
+ for (i = 0; i < NIC_CQS_NUM; i++) {
+ ring = &gaudi2_port->cq_rings[i];
+ RING_PI_SIZE(ring) = sizeof(u64);
+ RING_PI_ADDRESS(ring) = hbl_cn_dma_pool_zalloc(hdev, RING_PI_SIZE(ring),
+ GFP_KERNEL | __GFP_ZERO,
+ &RING_PI_DMA_ADDRESS(ring));
+ if (!RING_PI_ADDRESS(ring)) {
+ rc = -ENOMEM;
+ goto err;
+ }
+ }
+
+ return 0;
+
+err:
+ /* free the allocated rings indices */
+ for (--i; i >= 0; i--) {
+ ring = &gaudi2_port->cq_rings[i];
+ hbl_cn_dma_pool_free(hdev, RING_PI_ADDRESS(ring), RING_PI_DMA_ADDRESS(ring));
+ }
+
+ /* free rings memory */
+ hbl_cn_dma_free_coherent(hdev, total_queues_size, cpu_addr, dma_addr);
+
+ return rc;
+}
+
+static void gaudi2_cn_free_cq_rings(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ struct hbl_cn_ring *ring;
+ int i;
+
+ for (i = 0; i < NIC_CQS_NUM; i++) {
+ ring = &gaudi2_port->cq_rings[i];
+ hbl_cn_dma_pool_free(hdev, RING_PI_ADDRESS(ring), RING_PI_DMA_ADDRESS(ring));
+ }
+
+ /* the entire CQs memory is allocated as one chunk and stored at index 0 */
+ ring = &gaudi2_port->cq_rings[0];
+ hbl_cn_dma_free_coherent(hdev, RING_BUF_SIZE(ring), RING_BUF_ADDRESS(ring),
+ RING_BUF_DMA_ADDRESS(ring));
+}
+
+static int gaudi2_cn_alloc_rings_resources(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ int rc;
+
+ rc = hbl_cn_alloc_ring(hdev, &gaudi2_port->fifo_ring,
+ ALIGN(sizeof(u32), DEVICE_CACHE_LINE_SIZE), 1);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to allocate fifo ring\n");
+ return rc;
+ }
+
+ rc = hbl_cn_alloc_ring(hdev, &gaudi2_port->rx_ring, NIC_RAW_ELEM_SIZE,
+ NIC_RX_RING_PKT_NUM);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to allocate RX ring\n");
+ goto err_rx_ring;
+ }
+
+ rc = hbl_cn_alloc_ring(hdev, &gaudi2_port->wq_ring, sizeof(struct gaudi2_sq_wqe),
+ QP_WQE_NUM_REC);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to allocate WQ ring\n");
+ goto err_wq_ring;
+ }
+
+ rc = hbl_cn_alloc_ring(hdev, &gaudi2_port->eq_ring, sizeof(struct hbl_cn_eqe),
+ NIC_EQ_RING_NUM_REC);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to allocate EQ ring\n");
+ goto err_eq_ring;
+ }
+
+ rc = gaudi2_cn_alloc_cq_rings(gaudi2_port);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to allocate CQ rings\n");
+ goto err_cq_rings;
+ }
+
+ return 0;
+
+err_cq_rings:
+ hbl_cn_free_ring(hdev, &gaudi2_port->eq_ring);
+err_eq_ring:
+ hbl_cn_free_ring(hdev, &gaudi2_port->wq_ring);
+err_wq_ring:
+ hbl_cn_free_ring(hdev, &gaudi2_port->rx_ring);
+err_rx_ring:
+ hbl_cn_free_ring(hdev, &gaudi2_port->fifo_ring);
+
+ return rc;
+}
+
+static void gaudi2_cn_free_rings_resources(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+
+ gaudi2_cn_free_cq_rings(gaudi2_port);
+ hbl_cn_free_ring(hdev, &gaudi2_port->eq_ring);
+ hbl_cn_free_ring(hdev, &gaudi2_port->wq_ring);
+ hbl_cn_free_ring(hdev, &gaudi2_port->rx_ring);
+ hbl_cn_free_ring(hdev, &gaudi2_port->fifo_ring);
+}
+
+static void gaudi2_cn_reset_rings(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_ring *cq_ring;
+
+ /* Reset CQ ring HW PI and shadow PI/CI */
+ cq_ring = &gaudi2_port->cq_rings[NIC_CQ_RDMA_IDX];
+ *((u32 *)RING_PI_ADDRESS(cq_ring)) = 0;
+ cq_ring->pi_shadow = 0;
+ cq_ring->ci_shadow = 0;
+}
+
+static void gaudi2_cn_port_sw_fini(struct hbl_cn_port *cn_port)
+{
+ struct gaudi2_cn_port *gaudi2_port = cn_port->cn_specific;
+
+ mutex_destroy(&gaudi2_port->qp_destroy_lock);
+ mutex_destroy(&gaudi2_port->cfg_lock);
+
+ hbl_cn_eq_dispatcher_fini(cn_port);
+ gaudi2_cn_free_rings_resources(gaudi2_port);
+}
+
+static void link_eqe_init(struct hbl_cn_port *cn_port)
+{
+ /* Init only header. Data field(i.e. link status) would be updated
+ * when event is ready to be sent to user.
+ */
+ cn_port->link_eqe.data[0] = EQE_HEADER(true, EQE_LINK_STATUS);
+}
+
+static int gaudi2_cn_port_sw_init(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct gaudi2_cn_port *gaudi2_port;
+ struct gaudi2_cn_device *gaudi2;
+ u32 port = cn_port->port;
+ int rc;
+
+ gaudi2 = hdev->asic_specific;
+ gaudi2_port = &gaudi2->cn_ports[port];
+ gaudi2_port->hdev = hdev;
+ gaudi2_port->cn_port = cn_port;
+ cn_port->cn_specific = gaudi2_port;
+
+ cn_port->cn_macro = &hdev->cn_macros[port >> 1];
+
+ INIT_DELAYED_WORK(&cn_port->fw_status_work, hbl_cn_fw_status_work);
+
+ rc = gaudi2_cn_alloc_rings_resources(gaudi2_port);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to alloc rings, port: %d, %d\n", port, rc);
+ return rc;
+ }
+
+ hbl_cn_eq_dispatcher_init(gaudi2_port->cn_port);
+
+ mutex_init(&gaudi2_port->cfg_lock);
+ mutex_init(&gaudi2_port->qp_destroy_lock);
+
+ /* Userspace might not be notified immediately of link event from HW.
+ * e.g. if serdes is not yet configured or link is not stable, SW might
+ * defer sending link event to userspace.
+ * Hence we cache HW link EQE and updated with real link status just
+ * before sending to userspace.
+ */
+ link_eqe_init(cn_port);
+
+ return 0;
+}
+
+static int gaudi2_cn_macro_sw_init(struct hbl_cn_macro *cn_macro)
+{
+ return 0;
+}
+
+static void gaudi2_cn_macro_sw_fini(struct hbl_cn_macro *cn_macro)
+{
+}
+
+static int gaudi2_cn_set_pfc(struct hbl_cn_port *cn_port)
+{
+ struct gaudi2_cn_port *gaudi2_port = cn_port->cn_specific;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 port = cn_port->port, val = 0;
+ int i, start_lane;
+
+ val |= NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_TX_ENA_MASK |
+ NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_RX_ENA_MASK |
+ NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PROMIS_EN_MASK |
+ NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_TX_PAD_EN_MASK;
+
+ if (cn_port->pfc_enable) {
+ val |= NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PFC_MODE_MASK;
+ } else {
+ val |= NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_PAUSE_IGNORE_MASK |
+ NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG_CNTL_FRAME_ENA_MASK;
+ }
+
+ /* Write the value for each lane under this port */
+ start_lane = (port & 1) ? (NIC_MAC_NUM_OF_LANES / 2) : NIC_MAC_LANES_START;
+
+ for (i = start_lane; i < start_lane + (NIC_MAC_NUM_OF_LANES / 2); i++)
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG + MAC_CH_OFFSET(i), val);
+
+ return 0;
+}
+
+static int gaudi2_cn_config_port_hw_txs(struct gaudi2_cn_port *gaudi2_port)
+{
+ u32 txs_schedq, txs_fence_idx, txs_pi, txs_ci, txs_tail, txs_head, txs_timeout_31_0,
+ timeout_47_32, prio, txs_port, rl_en_log_time;
+ struct hbl_cn_port *cn_port = gaudi2_port->cn_port;
+ struct cpucp_cn_init_hw_mem_packet pkt;
+ struct hbl_cn_properties *cn_prop;
+ struct hbl_cn_device *hdev;
+ u32 port = cn_port->port;
+ bool use_cpucp;
+ u64 txs_addr;
+ int i, rc;
+
+ hdev = gaudi2_port->hdev;
+ cn_prop = &hdev->cn_props;
+
+ txs_addr = cn_prop->txs_base_addr + port * cn_prop->txs_base_size;
+
+ use_cpucp = !!(hdev->fw_app_cpu_boot_dev_sts0 & CPU_BOOT_DEV_STS0_NIC_MEM_CLEAR_EN);
+ if (use_cpucp) {
+ memset(&pkt, 0, sizeof(pkt));
+ pkt.cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_NIC_INIT_TXS_MEM <<
+ CPUCP_PKT_CTL_OPCODE_SHIFT);
+ pkt.cpucp_pkt.port_index = cpu_to_le32(port);
+ pkt.mem_base_addr = cpu_to_le64(txs_addr + TXS_FREE_OFFS);
+ pkt.num_entries = cpu_to_le16(TXS_FREE_NUM_ENTRIES);
+ pkt.entry_size = cpu_to_le16(TXS_ENT_SIZE);
+ pkt.granularity = cpu_to_le16(TXS_GRANULARITY);
+
+ rc = gaudi2_cn_send_cpu_message(hdev, (u32 *)&pkt, sizeof(pkt), 0, NULL);
+
+ if (rc) {
+ dev_err(hdev->dev,
+ "Failed to handle CPU-CP pkt %u, error %d\n",
+ CPUCP_PACKET_NIC_INIT_TXS_MEM, rc);
+ return rc;
+ }
+ } else {
+ /* TX sched-Qs list */
+ for (i = 0; i < TXS_FREE_NUM_ENTRIES; i++)
+ hbl_cn_dram_writel(hdev, TXS_GRANULARITY + i,
+ txs_addr + TXS_FREE_OFFS + i * TXS_ENT_SIZE);
+
+ /* Perform read to flush the writes */
+ hbl_cn_dram_readl(hdev, txs_addr);
+ }
+
+ WARN_ON_CACHE_UNALIGNED(txs_addr + TXS_FIFO_OFFS);
+
+ /* set TX sched queues address */
+ NIC_WREG32(NIC0_TXS0_BASE_ADDRESS_63_32, upper_32_bits(txs_addr + TXS_FIFO_OFFS));
+ NIC_WREG32(NIC0_TXS0_BASE_ADDRESS_31_7, lower_32_bits(txs_addr + TXS_FIFO_OFFS) >> 7);
+
+ /* Set access to bypass the MMU (old style configuration) */
+ NIC_WREG32(NIC0_TXS0_AXI_USER_LO, 0x400);
+
+ NIC_WREG32(NIC0_TXS0_FREE_LIST_PUSH_MASK_EN, 1);
+
+ txs_fence_idx = 0;
+ txs_pi = 0;
+ txs_ci = 0;
+ txs_tail = 0;
+ txs_head = 0;
+ txs_timeout_31_0 = 0;
+ timeout_47_32 = 0;
+ prio = 0;
+ txs_port = 0;
+ rl_en_log_time = 0;
+
+ /* Gaudi2 TXS implements 256 schedule-Qs.
+ * These queues are hard-divided to 4x64 priority groups of Qs.
+ * (The first and last Q group-relative numbers of each group (0-63) can be configured
+ * via NIC0_TXS0_FIRST_SCHEDQ_ID and NIC0_TXS0_LAST_SCHEDQ_ID, We will use its
+ * default values of 0 and 63 respectively).
+ * From the above pools we need to allocate and configure:
+ * 256 Qs (0-255) are evenly divided between the 4 possible ports so each port is
+ * assigned with 64 Qs.
+ * The 64 Qs are divided between the 4 possible priorities generating 16
+ * priority-granularity groups of which:
+ * - The Last group is dedicated for Ethernet (RAW_SCHED_Q).
+ * - The last-1 group is dedicated for the RDMA responder (RES_SCHED_Q)
+ * - The Last-2 group is dedicated for the RDMA Req (REQ_SCHED_Q)
+ * - The remaining Qs will be used by the BBR when supported.
+ */
+ for (i = 0; i < TXS_SCHEDQ; i++) {
+ /* main sched Qs */
+ txs_port = i / TXS_PORT_NUM_SCHEDQS;
+
+ prio = i % HBL_EN_PFC_PRIO_NUM;
+ txs_schedq = (timeout_47_32 & 0xFFFF) | ((prio & 0x3) << 16) |
+ ((txs_port & 1) << 18) | ((rl_en_log_time & 0x3F) << 19);
+ txs_tail = i;
+ txs_head = i;
+ NIC_WREG32(NIC0_TXS0_SCHEDQ_UPDATE_DESC_31_0, txs_fence_idx);
+ NIC_WREG32(NIC0_TXS0_SCHEDQ_UPDATE_DESC_63_32, txs_pi);
+ NIC_WREG32(NIC0_TXS0_SCHEDQ_UPDATE_DESC_95_64, txs_ci);
+ NIC_WREG32(NIC0_TXS0_SCHEDQ_UPDATE_DESC_127_96, txs_tail);
+ NIC_WREG32(NIC0_TXS0_SCHEDQ_UPDATE_DESC_159_128, txs_head);
+ NIC_WREG32(NIC0_TXS0_SCHEDQ_UPDATE_DESC_191_160, txs_timeout_31_0);
+ NIC_WREG32(NIC0_TXS0_SCHEDQ_UPDATE_DESC_217_192, txs_schedq);
+ NIC_WREG32(NIC0_TXS0_SCHEDQ_UPDATE_FIFO, i);
+ NIC_WREG32(NIC0_TXS0_SCHEDQ_UPDATE_EN, 1);
+ }
+
+ NIC_WREG32(NIC0_TXS0_TICK_WRAP, 100);
+
+ NIC_WREG32(NIC0_TXS0_SCAN_TIME_COMPARE_0, 4);
+ NIC_WREG32(NIC0_TXS0_SCAN_TIME_COMPARE_1, 0);
+ NIC_WREG32(NIC0_TXS0_TMR_SCAN_EN, 1);
+
+ NIC_WREG32(NIC0_TXS0_BASE_ADDRESS_FREE_LIST_63_32,
+ upper_32_bits(txs_addr + TXS_FREE_OFFS));
+
+ NIC_WREG32(NIC0_TXS0_BASE_ADDRESS_FREE_LIST_31_0,
+ lower_32_bits(txs_addr + TXS_FREE_OFFS));
+
+ NIC_WREG32(NIC0_TXS0_LIST_MASK,
+ ~(0xFFFFFFFF << (ilog2(TXS_FREE_NUM_ENTRIES) - 5)));
+ NIC_WREG32(NIC0_TXS0_PRODUCER_UPDATE, TXS_FREE_NUM_ENTRIES);
+ NIC_WREG32(NIC0_TXS0_PRODUCER_UPDATE_EN, 1);
+ NIC_WREG32(NIC0_TXS0_PRODUCER_UPDATE_EN, 0);
+ NIC_WREG32(NIC0_TXS0_LIST_MEM_READ_MASK, 0);
+ NIC_WREG32(NIC0_TXS0_PUSH_LOCK_EN, 1);
+
+ /* disable burst size optimization */
+ NIC_WREG32(NIC0_TXS0_IGNORE_BURST_EN, 0);
+
+ return 0;
+}
+
+static void gaudi2_cn_config_port_hw_txe(struct gaudi2_cn_port *gaudi2_port, u64 mac_addr)
+{
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ struct hbl_cn_properties *cn_prop;
+ u32 port;
+
+ cn_prop = &hdev->cn_props;
+ port = gaudi2_port->cn_port->port;
+
+ /* set the base address of the raw wq */
+ NIC_WREG32(NIC0_TXE0_SQ_BASE_ADDRESS_63_32_0,
+ upper_32_bits(RING_BUF_DMA_ADDRESS(&gaudi2_port->wq_ring)));
+
+ NIC_WREG32(NIC0_TXE0_SQ_BASE_ADDRESS_31_0_0,
+ lower_32_bits(RING_BUF_DMA_ADDRESS(&gaudi2_port->wq_ring)));
+
+ NIC_WREG32(NIC0_TXE0_LOG_MAX_WQ_SIZE_0, WQ_BUFFER_LOG_SIZE - 2);
+
+ /* map: prio#0-dscp#0, prio#1-dscp#0, prio#2-dscp#16, prio#3-dscp#24 */
+ NIC_WREG32(NIC0_TXE0_PRIO_TO_DSCP_0, 0x18100000);
+
+ NIC_WREG32(NIC0_TXE0_PORT0_MAC_CFG_47_32, (mac_addr >> 32) & 0xFFFF);
+ NIC_WREG32(NIC0_TXE0_PORT0_MAC_CFG_31_0, mac_addr & 0xFFFFFFFF);
+ NIC_WREG32(NIC0_TXE0_PORT1_MAC_CFG_47_32, (mac_addr >> 32) & 0xFFFF);
+ NIC_WREG32(NIC0_TXE0_PORT1_MAC_CFG_31_0, mac_addr & 0xFFFFFFFF);
+
+ /* set MMU bypass for kernel WQ */
+ NIC_WREG32(NIC0_TXE0_WQE_USER_CFG, 0x1);
+
+ NIC_WREG32(NIC0_TXE0_WQE_PREFETCH_CFG, 0x3);
+
+ NIC_WREG32(NIC0_TXE0_BTH_MKEY, 0xffff);
+
+ /* 100ms BW window size */
+ NIC_WREG32(NIC0_TXE0_STATS_CFG0, cn_prop->clk * PERF_BW_WINDOW_USEC);
+ NIC_RMWREG32(NIC0_TXE0_STATS_CFG1, 1, NIC0_TXE0_STATS_CFG1_LATENCY_ENABLE_MASK);
+ NIC_RMWREG32(NIC0_TXE0_STATS_CFG1, 0, NIC0_TXE0_STATS_CFG1_WIN_TYPE_MASK);
+ NIC_RMWREG32(NIC0_TXE0_STATS_CFG1, 0, NIC0_TXE0_STATS_CFG1_WIN_SAMP_LATENCY_MASK);
+ NIC_RMWREG32(NIC0_TXE0_STATS_CFG1, 3, NIC0_TXE0_STATS_CFG1_TOT_TYPE_MASK);
+ NIC_RMWREG32(NIC0_TXE0_STATS_CFG1, 1, NIC0_TXE0_STATS_CFG1_ENABLE_MASK);
+ NIC_RMWREG32(NIC0_TXE0_STATS_CFG2, 0, NIC0_TXE0_STATS_CFG2_LATENCY_WRAP_EN_MASK);
+ /* 2us latency window size */
+ NIC_RMWREG32(NIC0_TXE0_STATS_CFG2, 2 * cn_prop->clk,
+ NIC0_TXE0_STATS_CFG2_LATENCY_MAX_VAL_MASK);
+}
+
+static void gaudi2_cn_config_port_hw_qpc(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_port *cn_port = gaudi2_port->cn_port;
+ u64 req_qpc_base_addr, res_qpc_base_addr;
+ struct hbl_cn_properties *cn_prop;
+ struct hbl_cn_device *hdev;
+ u32 port = cn_port->port;
+
+ hdev = gaudi2_port->hdev;
+ cn_prop = &hdev->cn_props;
+
+ req_qpc_base_addr = cn_prop->req_qpc_base_addr + port * cn_prop->req_qpc_base_size;
+ res_qpc_base_addr = cn_prop->res_qpc_base_addr + port * cn_prop->res_qpc_base_size;
+
+ WARN_ON_CACHE_UNALIGNED(req_qpc_base_addr);
+ WARN_ON_CACHE_UNALIGNED(res_qpc_base_addr);
+
+ NIC_WREG32(NIC0_QPC0_REQ_BASE_ADDRESS_63_32, upper_32_bits(req_qpc_base_addr));
+ NIC_WREG32(NIC0_QPC0_REQ_BASE_ADDRESS_31_7, lower_32_bits(req_qpc_base_addr) >> 7);
+
+ NIC_WREG32(NIC0_QPC0_RES_BASE_ADDRESS_63_32, upper_32_bits(res_qpc_base_addr));
+ NIC_WREG32(NIC0_QPC0_RES_BASE_ADDRESS_31_7, lower_32_bits(res_qpc_base_addr) >> 7);
+
+ NIC_WREG32(NIC0_QPC0_RES_QPC_CACHE_INVALIDATE, 1);
+ NIC_WREG32(NIC0_QPC0_REQ_QPC_CACHE_INVALIDATE, 1);
+ NIC_WREG32(NIC0_QPC0_RES_QPC_CACHE_INVALIDATE, 0);
+ NIC_WREG32(NIC0_QPC0_REQ_QPC_CACHE_INVALIDATE, 0);
+
+ NIC_WREG32(NIC0_QPC0_INTERRUPT_CAUSE, 0);
+
+ /* Configure MMU-BP override for DB-FIFOs */
+ NIC_WREG32(NIC0_QPC0_AXUSER_DB_FIFO_HB_WR_OVRD_LO, 0xFFFFFBFF);
+ NIC_WREG32(NIC0_QPC0_AXUSER_DB_FIFO_HB_RD_OVRD_LO, 0xFFFFFBFF);
+
+ WARN_ON_CACHE_UNALIGNED(RING_BUF_DMA_ADDRESS(&gaudi2_port->fifo_ring));
+
+ /* Configure doorbell */
+ NIC_WREG32(NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_DBFIFO_CI_UPD_ADDR_63_32,
+ upper_32_bits(RING_BUF_DMA_ADDRESS(&gaudi2_port->fifo_ring)));
+ NIC_WREG32(NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_DBFIFO_CI_UPD_ADDR_31_7,
+ lower_32_bits(RING_BUF_DMA_ADDRESS(&gaudi2_port->fifo_ring)) >> 7);
+
+ gaudi2_cn_eq_dispatcher_register_db(gaudi2_port, hdev->kernel_asid,
+ GAUDI2_DB_FIFO_SECURE_HW_ID);
+
+ /* Configure MMU-BP override for error-FIFO */
+ NIC_WREG32(NIC0_QPC0_AXUSER_ERR_FIFO_HB_WR_OVRD_LO, 0xFFFFFBFF);
+ NIC_WREG32(NIC0_QPC0_AXUSER_ERR_FIFO_HB_RD_OVRD_LO, 0xFFFFFBFF);
+
+ NIC_WREG32(NIC0_QPC0_RETRY_COUNT_MAX,
+ (GAUDI2_NIC_MAX_TIMEOUT_RETRIES << NIC0_QPC0_RETRY_COUNT_MAX_TIMEOUT_SHIFT) |
+ (GAUDI2_NIC_MAX_SEQ_ERR_RETRIES <<
+ NIC0_QPC0_RETRY_COUNT_MAX_SEQUENCE_ERROR_SHIFT));
+
+ /* Configure MMU-BP override for QPCs */
+ NIC_WREG32(NIC0_QPC0_AXUSER_QPC_REQ_HB_WR_OVRD_LO, 0xFFFFFBFF);
+ NIC_WREG32(NIC0_QPC0_AXUSER_QPC_REQ_HB_RD_OVRD_LO, 0xFFFFFBFF);
+ NIC_WREG32(NIC0_QPC0_AXUSER_QPC_RESP_HB_WR_OVRD_LO, 0xFFFFFBFF);
+ NIC_WREG32(NIC0_QPC0_AXUSER_QPC_RESP_HB_RD_OVRD_LO, 0xFFFFFBFF);
+
+ /* Configure MMU-BP override for Congestion-Queue */
+ NIC_WREG32(NIC0_QPC0_AXUSER_CONG_QUE_HB_WR_OVRD_LO, 0xFFFFFBFF);
+ NIC_WREG32(NIC0_QPC0_AXUSER_CONG_QUE_HB_RD_OVRD_LO, 0xFFFFFBFF);
+
+ NIC_RMWREG32(NIC0_QPC0_REQ_STATIC_CONFIG, 1,
+ NIC0_QPC0_REQ_STATIC_CONFIG_QM_MOVEQP2ERR_SECUR_ERR_MASK);
+ NIC_RMWREG32(NIC0_QPC0_REQ_STATIC_CONFIG, 0,
+ NIC0_QPC0_REQ_STATIC_CONFIG_QM_PUSH_TO_ERROR_ASID_MASK);
+ NIC_RMWREG32(NIC0_QPC0_REQ_STATIC_CONFIG, 1,
+ NIC0_QPC0_REQ_STATIC_CONFIG_QM_UPD_IGNORE_ASID_ERR_MASK);
+ NIC_RMWREG32(NIC0_QPC0_REQ_STATIC_CONFIG, 0,
+ NIC0_QPC0_REQ_STATIC_CONFIG_QM_MOVEQP2ERR_ASID_ERR_MASK);
+ NIC_RMWREG32(NIC0_QPC0_REQ_STATIC_CONFIG, 1,
+ NIC0_QPC0_REQ_STATIC_CONFIG_QM_PUSH_TO_ERROR_SECURITY_MASK);
+
+ /* Disable the WTD back-pressure mechanism to ARC and QMAN - it will be
+ * enabled later on by the user.
+ */
+ NIC_RMWREG32_SHIFTED(NIC0_QPC0_WTD_CONFIG, 0, NIC0_QPC0_WTD_CONFIG_WQ_BP_2ARC_EN_MASK |
+ NIC0_QPC0_WTD_CONFIG_WQ_BP_2QMAN_EN_MASK);
+}
+
+static void gaudi2_cn_config_port_hw_rxe(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_ring *cq_ring = &gaudi2_port->cq_rings[NIC_CQ_RAW_IDX];
+ struct hbl_cn_properties *cn_prop = &gaudi2_port->hdev->cn_props;
+ struct hbl_cn_ring *rx_ring = &gaudi2_port->rx_ring;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 port = gaudi2_port->cn_port->port;
+ u32 rx_mem_addr_lo, rx_mem_addr_hi;
+ int i;
+
+ rx_mem_addr_lo = lower_32_bits(RING_BUF_DMA_ADDRESS(rx_ring));
+ rx_mem_addr_hi = upper_32_bits(RING_BUF_DMA_ADDRESS(rx_ring));
+
+ NIC_WREG32(NIC0_RXE0_RAW_QPN_P0_0, RAW_QPN);
+ NIC_WREG32(NIC0_RXE0_RAW_QPN_P0_1, RAW_QPN);
+ NIC_WREG32(NIC0_RXE0_RAW_QPN_P1_0, RAW_QPN);
+ NIC_WREG32(NIC0_RXE0_RAW_QPN_P1_1, RAW_QPN);
+ NIC_WREG32(NIC0_RXE0_RAW_QPN_P2_0, RAW_QPN);
+ NIC_WREG32(NIC0_RXE0_RAW_QPN_P2_1, RAW_QPN);
+ NIC_WREG32(NIC0_RXE0_RAW_QPN_P3_0, RAW_QPN);
+ NIC_WREG32(NIC0_RXE0_RAW_QPN_P3_1, RAW_QPN);
+
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_LO_P0_0, rx_mem_addr_lo);
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_LO_P0_1, rx_mem_addr_lo);
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_HI_P0_0, rx_mem_addr_hi);
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_HI_P0_1, rx_mem_addr_hi);
+
+ /* #define NIC5_RXE1_RAW_MISC_P2_LOG_RAW_ENTRY_SIZE_P2_SHIFT 0 */
+ /* #define NIC5_RXE1_RAW_MISC_P2_LOG_RAW_ENTRY_SIZE_P2_MASK 0xF */
+
+ /* #define NIC5_RXE1_RAW_MISC_P2_LOG_BUFFER_SIZE_MASK_P2_SHIFT 15 */
+ /* #define NIC5_RXE1_RAW_MISC_P2_LOG_BUFFER_SIZE_MASK_P2_MASK */
+ /* 0xF8000 */
+
+ NIC_WREG32(NIC0_RXE0_RAW_MISC_P0_0,
+ (ilog2(rx_ring->elem_size) & NIC0_RXE0_RAW_MISC_P2_LOG_RAW_ENTRY_SIZE_P2_MASK) |
+ ((ilog2(rx_ring->count) & 0x1F) << 15));
+
+ NIC_WREG32(NIC0_RXE0_RAW_MISC_P0_1,
+ (ilog2(rx_ring->elem_size) & NIC0_RXE0_RAW_MISC_P2_LOG_RAW_ENTRY_SIZE_P2_MASK) |
+ ((ilog2(rx_ring->count) & 0x1F) << 15));
+
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_LO_P1_0, rx_mem_addr_lo);
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_LO_P1_1, rx_mem_addr_lo);
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_HI_P1_0, rx_mem_addr_hi);
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_HI_P1_1, rx_mem_addr_hi);
+
+ NIC_WREG32(NIC0_RXE0_RAW_MISC_P1_0,
+ (ilog2(rx_ring->elem_size) & NIC0_RXE0_RAW_MISC_P2_LOG_RAW_ENTRY_SIZE_P2_MASK) |
+ ((ilog2(rx_ring->count) & 0x1F) << 15));
+
+ NIC_WREG32(NIC0_RXE0_RAW_MISC_P1_1,
+ (ilog2(rx_ring->elem_size) & NIC0_RXE0_RAW_MISC_P2_LOG_RAW_ENTRY_SIZE_P2_MASK) |
+ ((ilog2(rx_ring->count) & 0x1F) << 15));
+
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_LO_P2_0, rx_mem_addr_lo);
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_LO_P2_1, rx_mem_addr_lo);
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_HI_P2_0, rx_mem_addr_hi);
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_HI_P2_1, rx_mem_addr_hi);
+
+ NIC_WREG32(NIC0_RXE0_RAW_MISC_P2_0,
+ (ilog2(rx_ring->elem_size) & NIC0_RXE0_RAW_MISC_P2_LOG_RAW_ENTRY_SIZE_P2_MASK) |
+ ((ilog2(rx_ring->count) & 0x1F) << 15));
+
+ NIC_WREG32(NIC0_RXE0_RAW_MISC_P2_1,
+ (ilog2(rx_ring->elem_size) & NIC0_RXE0_RAW_MISC_P2_LOG_RAW_ENTRY_SIZE_P2_MASK) |
+ ((ilog2(rx_ring->count) & 0x1F) << 15));
+
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_LO_P3_0, rx_mem_addr_lo);
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_LO_P3_1, rx_mem_addr_lo);
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_HI_P3_0, rx_mem_addr_hi);
+ NIC_WREG32(NIC0_RXE0_RAW_BASE_HI_P3_1, rx_mem_addr_hi);
+
+ NIC_WREG32(NIC0_RXE0_RAW_MISC_P3_0,
+ (ilog2(rx_ring->elem_size) & NIC0_RXE0_RAW_MISC_P2_LOG_RAW_ENTRY_SIZE_P2_MASK) |
+ ((ilog2(rx_ring->count) & 0x1F) << 15));
+
+ NIC_WREG32(NIC0_RXE0_RAW_MISC_P3_1,
+ (ilog2(rx_ring->elem_size) & NIC0_RXE0_RAW_MISC_P2_LOG_RAW_ENTRY_SIZE_P2_MASK) |
+ ((ilog2(rx_ring->count) & 0x1F) << 15));
+
+ NIC_WREG32(NIC0_RXE0_CQ_BASE_ADDR_63_32, upper_32_bits(RING_BUF_DMA_ADDRESS(cq_ring)));
+ NIC_WREG32(NIC0_RXE0_CQ_BASE_ADDR_31_7,
+ lower_32_bits(RING_BUF_DMA_ADDRESS(cq_ring)) & 0xFFFFFF80);
+
+ NIC_WREG32(NIC0_RXE0_CQ_PI_ADDR_HI_0,
+ upper_32_bits(RING_PI_DMA_ADDRESS(cq_ring)));
+ NIC_WREG32(NIC0_RXE0_CQ_PI_ADDR_LO_0,
+ lower_32_bits(RING_PI_DMA_ADDRESS(cq_ring)) & 0xFFFFFF80);
+
+ /* Set the max CQ size */
+ NIC_WREG32(NIC0_RXE0_CQ_LOG_MAX_SIZE, ilog2(NIC_CQ_MAX_ENTRIES));
+
+ /* Set the actual single CQ size log2(number of entries in cq)*/
+ NIC_WREG32(NIC0_RXE0_CQ_LOG_SIZE_0, ilog2(cq_ring->count));
+
+ /* Initialize MMU-BP for all CQs */
+ for (i = 0; i < cn_prop->max_cqs; i++)
+ NIC_WREG32(NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_WR_OVRD_LO +
+ (i * NIC_RXE_AXUSER_AXUSER_CQ_OFFSET), 0xFFFFFBFF);
+
+ NIC_WREG32(NIC0_RXE0_CQ_WRITE_INDEX_0, 0);
+ NIC_WREG32(NIC0_RXE0_CQ_PRODUCER_INDEX_0, 0);
+ NIC_WREG32(NIC0_RXE0_CQ_CONSUMER_INDEX_0, 0);
+
+ /* enable, pi-update and completion-events */
+ NIC_WREG32(NIC0_RXE0_CQ_CFG_0, 1 << NIC0_RXE0_CQ_CFG_WRITE_PI_EN_SHIFT |
+ 1 << NIC0_RXE0_CQ_CFG_ENABLE_SHIFT);
+
+ /* disable all RDMA CQs */
+ for (i = 1; i < cn_prop->max_cqs; i++)
+ NIC_WREG32(NIC0_RXE0_CQ_CFG_0 + i * 4, 0);
+
+ /* set MMU bypass for kernel WQ */
+ NIC_WREG32(NIC0_RXE0_ARUSER_MMU_BP, 0x1);
+
+ /* set SPMU RXE counters of Group 1 */
+ NIC_WREG32(NIC0_RXE0_DBG_SPMU_SELECT, 0x1);
+}
+
+static void gaudi2_cn_config_hw_mac_filter(struct gaudi2_cn_port *gaudi2_port, u64 mac_addr)
+{
+ struct hbl_cn_port *cn_port = gaudi2_port->cn_port;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 port = cn_port->port;
+
+ if (cn_port->eth_enable) {
+ if (port & 1) {
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RC_MAC_31_0_2,
+ mac_addr & 0xFFFFFFFF);
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RC_MAC_47_32_2,
+ (mac_addr >> 32) & 0xFFFF);
+
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RC_MAC_31_0_MASK_2, 0);
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RC_MAC_47_32_MASK_2, 0);
+
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RAW0_MAC_31_0_2,
+ mac_addr & 0xFFFFFFFF);
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RAW0_MAC_47_32_2,
+ (mac_addr >> 32) & 0xFFFF);
+
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RAW0_MAC_31_0_MASK_2, 0);
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RAW0_MAC_47_32_MASK_2, 0);
+ } else {
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RC_MAC_31_0_0,
+ mac_addr & 0xFFFFFFFF);
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RC_MAC_47_32_0,
+ (mac_addr >> 32) & 0xFFFF);
+
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RC_MAC_31_0_MASK_0, 0);
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RC_MAC_47_32_MASK_0, 0);
+
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RAW0_MAC_31_0_0,
+ mac_addr & 0xFFFFFFFF);
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RAW0_MAC_47_32_0,
+ (mac_addr >> 32) & 0xFFFF);
+
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RAW0_MAC_31_0_MASK_0, 0);
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RAW0_MAC_47_32_MASK_0, 0);
+ }
+ } else {
+ if (port & 1) {
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RC_MAC_31_0_MASK_2, 0xFFFFFFFF);
+
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RC_MAC_47_32_MASK_2, 0xFFFF);
+ } else {
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RC_MAC_31_0_MASK_0, 0xFFFFFFFF);
+
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TS_RC_MAC_47_32_MASK_0, 0xFFFF);
+ }
+ }
+}
+
+static int gaudi2_cn_hw_mac_ch_reset(struct gaudi2_cn_port *gaudi2_port, int lane)
+{
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 port = gaudi2_port->cn_port->port;
+ ktime_t timeout;
+ u32 read_reg;
+
+ if (hdev->skip_mac_reset)
+ return 0;
+
+ timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * 1000ull);
+
+ do {
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_CONTROL1 + MAC_CH_OFFSET(lane),
+ BIT(NIC0_MAC_CH0_MAC_PCS_CONTROL1_FLD_RESET_SHIFT));
+ usleep_range(50, 200);
+
+ read_reg = NIC_MACRO_RREG32(NIC0_MAC_CH0_MAC_PCS_CONTROL1 + MAC_CH_OFFSET(lane));
+ } while ((read_reg & NIC0_MAC_CH0_MAC_PCS_CONTROL1_FLD_RESET_MASK) &&
+ ktime_compare(ktime_get(), timeout) < 0);
+
+ if (read_reg & NIC0_MAC_CH0_MAC_PCS_CONTROL1_FLD_RESET_MASK) {
+ dev_err(hdev->dev, "Timeout while MAC channel %d reset\n", lane);
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+static void gaudi2_cn_hw_mac_port_config_lane_speed(struct gaudi2_cn_port *gaudi2_port, int i)
+{
+ struct hbl_cn_port *cn_port = gaudi2_port->cn_port;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 port = cn_port->port;
+
+ switch (cn_port->speed) {
+ case SPEED_25000:
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL_INTVL + MAC_CH_OFFSET(i),
+ REGMASK(0x4FFF,
+ NIC0_MAC_CH0_MAC_PCS_VENDOR_VL_INTVL_MARKER_COUNTER));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE + MAC_CH_OFFSET(i),
+ REGMASK(1, NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE_ENA_CLAUSE49) |
+ REGMASK(1, NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE_HI_BER25));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0 + MAC_CH_OFFSET(i),
+ REGMASK(0xC1, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0_M0) |
+ REGMASK(0x68, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0_M1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x21, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_1_M2));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0 + MAC_CH_OFFSET(i),
+ REGMASK(0xF0, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0_M0) |
+ REGMASK(0xC4, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0_M1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_1 + MAC_CH_OFFSET(i),
+ REGMASK(0xE6, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_1_M2));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0 + MAC_CH_OFFSET(i),
+ REGMASK(0xC5, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0_M0) |
+ REGMASK(0x65, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0_M1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x9B, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_1_M2));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0 + MAC_CH_OFFSET(i),
+ REGMASK(0xA2, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0_M0) |
+ REGMASK(0x79, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0_M1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x3D, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_1_M2));
+ break;
+ case SPEED_50000:
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL_INTVL + MAC_CH_OFFSET(i),
+ REGMASK(0x4FFF,
+ NIC0_MAC_CH0_MAC_PCS_VENDOR_VL_INTVL_MARKER_COUNTER));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE + MAC_CH_OFFSET(i), 0x0);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0 + MAC_CH_OFFSET(i),
+ REGMASK(0x90, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0_M0) |
+ REGMASK(0x76, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0_M1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x47, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_1_M2));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0 + MAC_CH_OFFSET(i),
+ REGMASK(0xF0, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0_M0) |
+ REGMASK(0xC4, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0_M1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_1 + MAC_CH_OFFSET(i),
+ REGMASK(0xE6, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_1_M2));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0 + MAC_CH_OFFSET(i),
+ REGMASK(0xC5, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0_M0) |
+ REGMASK(0x65, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0_M1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x9B, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_1_M2));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0 + MAC_CH_OFFSET(i),
+ REGMASK(0xA2, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0_M0) |
+ REGMASK(0x79, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0_M1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x3D, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_1_M2));
+ break;
+ case SPEED_100000:
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL_INTVL + MAC_CH_OFFSET(i),
+ REGMASK(0x3FFF,
+ NIC0_MAC_CH0_MAC_PCS_VENDOR_VL_INTVL_MARKER_COUNTER));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_PCS_MODE + MAC_CH_OFFSET(i), 0x0);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0 + MAC_CH_OFFSET(i),
+ REGMASK(0xC1, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0_M0) |
+ REGMASK(0x68, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_0_M1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x21, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL0_1_M2));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0 + MAC_CH_OFFSET(i),
+ REGMASK(0x9D, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0_M0) |
+ REGMASK(0x71, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_0_M1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x8E, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL1_1_M2));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0 + MAC_CH_OFFSET(i),
+ REGMASK(0x59, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0_M0) |
+ REGMASK(0x4B, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_0_M1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_1 + MAC_CH_OFFSET(i),
+ REGMASK(0xE8, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL2_1_M2));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0 + MAC_CH_OFFSET(i),
+ REGMASK(0x4D, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0_M0) |
+ REGMASK(0x95, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_0_M1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x7B, NIC0_MAC_CH0_MAC_PCS_VENDOR_VL3_1_M2));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL4_0 + MAC_CH_OFFSET(i),
+ REGMASK(0x7F5, NIC0_MAC_CH0_MAC_PCS_VL4_0_VL4_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL4_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x9, NIC0_MAC_CH0_MAC_PCS_VL4_1_VL4_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL5_0 + MAC_CH_OFFSET(i),
+ REGMASK(0x14DD, NIC0_MAC_CH0_MAC_PCS_VL5_0_VL5_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL5_1 + MAC_CH_OFFSET(i),
+ REGMASK(0xC2, NIC0_MAC_CH0_MAC_PCS_VL5_1_VL5_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL6_0 + MAC_CH_OFFSET(i),
+ REGMASK(0x4A9A, NIC0_MAC_CH0_MAC_PCS_VL6_0_VL6_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL6_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x26, NIC0_MAC_CH0_MAC_PCS_VL6_1_VL6_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL7_0 + MAC_CH_OFFSET(i),
+ REGMASK(0x457B, NIC0_MAC_CH0_MAC_PCS_VL7_0_VL7_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL7_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x66, NIC0_MAC_CH0_MAC_PCS_VL7_1_VL7_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL8_0 + MAC_CH_OFFSET(i),
+ REGMASK(0x24A0, NIC0_MAC_CH0_MAC_PCS_VL8_0_VL8_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL8_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x76, NIC0_MAC_CH0_MAC_PCS_VL8_1_VL8_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL9_0 + MAC_CH_OFFSET(i),
+ REGMASK(0xC968, NIC0_MAC_CH0_MAC_PCS_VL9_0_VL9_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL9_1 + MAC_CH_OFFSET(i),
+ REGMASK(0xFB, NIC0_MAC_CH0_MAC_PCS_VL9_1_VL9_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL10_0 + MAC_CH_OFFSET(i),
+ REGMASK(0x6CFD, NIC0_MAC_CH0_MAC_PCS_VL10_0_VL10_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL10_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x99, NIC0_MAC_CH0_MAC_PCS_VL10_1_VL10_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL11_0 + MAC_CH_OFFSET(i),
+ REGMASK(0x91B9, NIC0_MAC_CH0_MAC_PCS_VL11_0_VL11_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL11_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x55, NIC0_MAC_CH0_MAC_PCS_VL11_1_VL11_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL12_0 + MAC_CH_OFFSET(i),
+ REGMASK(0xB95C, NIC0_MAC_CH0_MAC_PCS_VL12_0_VL12_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL12_1 + MAC_CH_OFFSET(i),
+ REGMASK(0xB2, NIC0_MAC_CH0_MAC_PCS_VL12_1_VL12_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL13_0 + MAC_CH_OFFSET(i),
+ REGMASK(0xF81A, NIC0_MAC_CH0_MAC_PCS_VL13_0_VL13_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL13_1 + MAC_CH_OFFSET(i),
+ REGMASK(0xBD, NIC0_MAC_CH0_MAC_PCS_VL13_1_VL13_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL14_0 + MAC_CH_OFFSET(i),
+ REGMASK(0xC783, NIC0_MAC_CH0_MAC_PCS_VL14_0_VL14_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL14_1 + MAC_CH_OFFSET(i),
+ REGMASK(0xCA, NIC0_MAC_CH0_MAC_PCS_VL14_1_VL14_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL15_0 + MAC_CH_OFFSET(i),
+ REGMASK(0x3635, NIC0_MAC_CH0_MAC_PCS_VL15_0_VL15_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL15_1 + MAC_CH_OFFSET(i),
+ REGMASK(0xCD, NIC0_MAC_CH0_MAC_PCS_VL15_1_VL15_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL16_0 + MAC_CH_OFFSET(i),
+ REGMASK(0x31C4, NIC0_MAC_CH0_MAC_PCS_VL16_0_VL16_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL16_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x4C, NIC0_MAC_CH0_MAC_PCS_VL16_1_VL16_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL17_0 + MAC_CH_OFFSET(i),
+ REGMASK(0xD6AD, NIC0_MAC_CH0_MAC_PCS_VL17_0_VL17_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL17_1 + MAC_CH_OFFSET(i),
+ REGMASK(0xB7, NIC0_MAC_CH0_MAC_PCS_VL17_1_VL17_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL18_0 + MAC_CH_OFFSET(i),
+ REGMASK(0x665F, NIC0_MAC_CH0_MAC_PCS_VL18_0_VL18_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL18_1 + MAC_CH_OFFSET(i),
+ REGMASK(0x2A, NIC0_MAC_CH0_MAC_PCS_VL18_1_VL18_1));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL19_0 + MAC_CH_OFFSET(i),
+ REGMASK(0xF0C0, NIC0_MAC_CH0_MAC_PCS_VL19_0_VL19_0));
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_PCS_VL19_1 + MAC_CH_OFFSET(i),
+ REGMASK(0xE5, NIC0_MAC_CH0_MAC_PCS_VL19_1_VL19_1));
+ break;
+ default:
+ dev_err(hdev->dev, "unknown port %d speed %dMb/s, cannot set MAC XPCS\n", port,
+ cn_port->speed);
+ return;
+ }
+}
+
+static void gaudi2_cn_hw_mac_port_config(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_port *cn_port = gaudi2_port->cn_port;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 port = cn_port->port;
+ int i, start_lane;
+
+ start_lane = (port & 1) ? (NIC_MAC_NUM_OF_LANES / 2) : NIC_MAC_LANES_START;
+
+ for (i = start_lane; i < start_lane + (NIC_MAC_NUM_OF_LANES / 2); i++) {
+ gaudi2_cn_hw_mac_ch_reset(gaudi2_port, i);
+
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_FRM_LENGTH + MAC_CH_OFFSET(i),
+ NIC_MAC_MAX_FRM_LEN);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_COMMAND_CONFIG + MAC_CH_OFFSET(i), 0x2913);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_TX_FIFO_SECTIONS + MAC_CH_OFFSET(i), 0x4);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_RX_FIFO_SECTIONS + MAC_CH_OFFSET(i), 0x4);
+
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL01_PAUSE_QUANTA + MAC_CH_OFFSET(i),
+ 0xFFFFFFFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL01_QUANTA_THRESH + MAC_CH_OFFSET(i),
+ 0x7FFF7FFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL23_PAUSE_QUANTA + MAC_CH_OFFSET(i),
+ 0xFFFFFFFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL23_QUANTA_THRESH + MAC_CH_OFFSET(i),
+ 0x7FFF7FFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL45_PAUSE_QUANTA + MAC_CH_OFFSET(i),
+ 0xFFFFFFFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL45_QUANTA_THRESH + MAC_CH_OFFSET(i),
+ 0x7FFF7FFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL67_PAUSE_QUANTA + MAC_CH_OFFSET(i),
+ 0xFFFFFFFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL67_QUANTA_THRESH + MAC_CH_OFFSET(i),
+ 0x7FFF7FFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL89_PAUSE_QUANTA + MAC_CH_OFFSET(i),
+ 0xFFFFFFFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL89_QUANTA_THRESH + MAC_CH_OFFSET(i),
+ 0x7FFF7FFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL1011_PAUSE_QUANTA + MAC_CH_OFFSET(i),
+ 0xFFFFFFFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL1011_QUANTA_THRESH + MAC_CH_OFFSET(i),
+ 0x7FFF7FFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL1213_PAUSE_QUANTA + MAC_CH_OFFSET(i),
+ 0xFFFFFFFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL1213_QUANTA_THRESH + MAC_CH_OFFSET(i),
+ 0x7FFF7FFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL1415_PAUSE_QUANTA + MAC_CH_OFFSET(i),
+ 0xFFFFFFFF);
+ NIC_MACRO_WREG32(NIC0_MAC_CH0_MAC_128_CL1415_QUANTA_THRESH + MAC_CH_OFFSET(i),
+ 0x7FFF7FFF);
+
+ gaudi2_cn_hw_mac_port_config_lane_speed(gaudi2_port, i);
+ }
+}
+
+static void gaudi2_cn_enable_port_interrupts(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+
+ /* enable RXE block interrupts. RXE SPI interrupts should stay masked out,
+ * they generate a lot of events which are not fatal errors
+ */
+ NIC_WREG32(NIC0_RXE0_SEI_INTR_MASK, 0x0);
+
+ /* enable TXS block interrupts */
+ NIC_WREG32(NIC0_TXS0_INTERRUPT_MASK, 0x0);
+
+ /* enable TXE block interrupts */
+ NIC_WREG32(NIC0_TXE0_INTERRUPT_MASK, 0x0);
+
+ /* enable QPC response error interrupts */
+ NIC_WREG32(NIC0_QPC0_INTERRUPT_RESP_ERR_MASK, 0x0);
+}
+
+static void gaudi2_cn_disable_port_interrupts(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+
+ /* disable RXE block interrupts */
+ NIC_WREG32(NIC0_RXE0_SEI_INTR_MASK, 0xF);
+
+ /* disable TXS block interrupts */
+ NIC_WREG32(NIC0_TXS0_INTERRUPT_MASK, 0xF);
+
+ /* disable TXE block interrupts */
+ NIC_WREG32(NIC0_TXE0_INTERRUPT_MASK, 0x7F);
+
+ /* disable QPC response error interrupts */
+ NIC_WREG32(NIC0_QPC0_INTERRUPT_RESP_ERR_MASK, 0x7F);
+}
+
+static int gaudi2_cn_hw_port_config(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_port *cn_port = gaudi2_port->cn_port;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 port = cn_port->port;
+ u64 mac_addr = 0;
+ int i, rc = 0;
+
+ for (i = 0; i < ETH_ALEN; i++) {
+ mac_addr <<= 8;
+ mac_addr |= hdev->cpucp_info->mac_addrs[port].mac_addr[i];
+ }
+
+ /* TXS Configuration */
+ rc = gaudi2_cn_config_port_hw_txs(gaudi2_port);
+ if (rc)
+ return rc;
+
+ /* TXE Configuration */
+ gaudi2_cn_config_port_hw_txe(gaudi2_port, mac_addr);
+
+ /* QPC Configuration */
+ gaudi2_cn_config_port_hw_qpc(gaudi2_port);
+
+ /* RXE Configuration */
+ gaudi2_cn_config_port_hw_rxe(gaudi2_port);
+
+ /* MAC filtering */
+ gaudi2_cn_config_hw_mac_filter(gaudi2_port, mac_addr);
+
+ /* Lanes Configuration */
+ gaudi2_cn_hw_mac_port_config(gaudi2_port);
+
+ /* PFC Configuration */
+ gaudi2_cn_set_pfc(cn_port);
+
+ /* Enable port GIC interrupts - required only if running on PLDM */
+ if (hdev->pldm)
+ gaudi2_cn_enable_port_interrupts(cn_port);
+
+ return rc;
+}
+
+void gaudi2_cn_hw_mac_loopback_cfg(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_port *cn_port;
+ struct hbl_cn_device *hdev;
+ u32 port, val;
+
+ cn_port = gaudi2_port->cn_port;
+ hdev = cn_port->hdev;
+ port = cn_port->port;
+ val = !!cn_port->mac_loopback;
+
+ if (port & 1) {
+ /* odd ports use lanes 2,3 */
+ NIC_MACRO_RMWREG32(NIC0_MAC_CH2_MAC_PCS_CONTROL1, val,
+ NIC0_MAC_CH0_MAC_PCS_CONTROL1_LOOPBACK_MASK);
+ NIC_MACRO_RMWREG32(NIC0_MAC_CH3_MAC_PCS_CONTROL1, val,
+ NIC0_MAC_CH0_MAC_PCS_CONTROL1_LOOPBACK_MASK);
+ } else {
+ /* even ports use lanes 0,1 */
+ NIC_MACRO_RMWREG32(NIC0_MAC_CH0_MAC_PCS_CONTROL1, val,
+ NIC0_MAC_CH0_MAC_PCS_CONTROL1_LOOPBACK_MASK);
+ NIC_MACRO_RMWREG32(NIC0_MAC_CH1_MAC_PCS_CONTROL1, val,
+ NIC0_MAC_CH0_MAC_PCS_CONTROL1_LOOPBACK_MASK);
+ }
+
+ /* flush cfg */
+ NIC_MACRO_RREG32(NIC0_MAC_CH0_MAC_PCS_CONTROL1);
+}
+
+bool gaudi2_cn_is_cq_in_overrun(struct hbl_cn_port *cn_port, u8 cq_id)
+{
+ struct hbl_cn_user_cq *user_cq;
+ bool is_cq_in_overrun = false;
+
+ user_cq = hbl_cn_user_cq_get(cn_port, cq_id);
+ if (user_cq) {
+ is_cq_in_overrun = user_cq->qp_set_overrun_cnt > 0;
+ hbl_cn_user_cq_put(user_cq);
+ }
+
+ return is_cq_in_overrun;
+}
+
+static void gaudi2_cn_qp_pre_destroy(struct hbl_cn_qp *qp)
+{
+ struct hbl_cn_port *cn_port = qp->cn_port;
+ struct gaudi2_cn_port *gaudi2_port;
+
+ gaudi2_port = cn_port->cn_specific;
+
+ mutex_lock(&gaudi2_port->qp_destroy_lock);
+
+ /* only the first QP should enable MAC loopback */
+ if (++gaudi2_port->qp_destroy_cnt == 1 && !cn_port->mac_loopback && !cn_port->pcs_link) {
+ cn_port->mac_loopback = true;
+ gaudi2_cn_hw_mac_loopback_cfg(gaudi2_port);
+ gaudi2_port->qp_destroy_mac_lpbk = true;
+ }
+
+ mutex_unlock(&gaudi2_port->qp_destroy_lock);
+}
+
+static void gaudi2_cn_qp_post_destroy(struct hbl_cn_qp *qp)
+{
+ struct hbl_cn_port *cn_port = qp->cn_port;
+ struct gaudi2_cn_port *gaudi2_port;
+
+ gaudi2_port = cn_port->cn_specific;
+
+ mutex_lock(&gaudi2_port->qp_destroy_lock);
+
+ /* only the last QP should disable MAC loopback */
+ if (!--gaudi2_port->qp_destroy_cnt && gaudi2_port->qp_destroy_mac_lpbk) {
+ cn_port->mac_loopback = false;
+ gaudi2_cn_hw_mac_loopback_cfg(gaudi2_port);
+ gaudi2_port->qp_destroy_mac_lpbk = false;
+ }
+
+ mutex_unlock(&gaudi2_port->qp_destroy_lock);
+}
+
+static int gaudi2_cn_hw_config(struct gaudi2_cn_port *gaudi2_port)
+{
+ int rc = 0;
+
+ rc = gaudi2_cn_hw_port_config(gaudi2_port);
+ if (rc)
+ return rc;
+
+ gaudi2_cn_hw_mac_loopback_cfg(gaudi2_port);
+
+ return rc;
+}
+
+static int gaudi2_cn_port_hw_init(struct hbl_cn_port *cn_port)
+{
+ struct gaudi2_cn_port *gaudi2_port = cn_port->cn_specific;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 port = cn_port->port;
+ int rc;
+
+ gaudi2_cn_reset_rings(gaudi2_port);
+
+ /* register the Eth CQ with the event dispatcher */
+ rc = hbl_cn_eq_dispatcher_register_cq(cn_port, gaudi2_port->cq_rings[NIC_CQ_RAW_IDX].asid,
+ NIC_CQ_RAW_IDX);
+ if (rc) {
+ dev_err(hdev->dev, "failed to register port %d CQ %d with cn_eq_sw\n", port,
+ NIC_CQ_RAW_IDX);
+ goto cq_register_fail;
+ }
+
+ rc = gaudi2_cn_hw_config(gaudi2_port);
+ if (rc)
+ goto cq_init_fail;
+
+ cn_port->eq_handler_enable = true;
+
+ rc = gaudi2_qp_sanity_init(gaudi2_port);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init QP sanity, port: %d, %d\n", port, rc);
+ goto cq_init_fail;
+ }
+
+ return 0;
+
+cq_init_fail:
+ cn_port->eq_handler_enable = false;
+ hbl_cn_eq_dispatcher_unregister_cq(cn_port, NIC_CQ_RAW_IDX);
+cq_register_fail:
+
+ return rc;
+}
+
+static void gaudi2_cn_port_hw_fini(struct hbl_cn_port *cn_port)
+{
+ struct gaudi2_cn_port *gaudi2_port = cn_port->cn_specific;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+
+ /* Disable port GIC interrupts - required only if running on PLDM */
+ if (hdev->pldm)
+ gaudi2_cn_disable_port_interrupts(cn_port);
+
+ gaudi2_qp_sanity_fini(gaudi2_port);
+
+ cn_port->eq_handler_enable = false;
+
+ hbl_cn_eq_dispatcher_unregister_cq(cn_port, NIC_CQ_RAW_IDX);
+ hbl_cn_eq_dispatcher_unregister_db(cn_port, GAUDI2_DB_FIFO_SECURE_HW_ID);
+
+ hbl_cn_eq_dispatcher_reset(cn_port);
+}
+
+static bool qpc_op_cond_func(u32 val, void *arg)
+{
+ return !val;
+}
+
+/* must be called under mutex_lock(&cn_port->qpc_lock) */
+static int gaudi2_cn_qpc_op(struct hbl_cn_port *cn_port, u64 ctrl, bool wait_for_completion)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+ int rc = 0;
+
+ NIC_WREG32(NIC0_QPC0_GW_CTRL, ctrl);
+
+ NIC_WREG32(NIC0_QPC0_GW_BUSY, 1);
+
+ /* do not poll on registers when reset was initiated by FW */
+ if (wait_for_completion && !hdev->fw_reset) {
+ u32 addr = NIC0_QPC0_GW_BUSY + NIC_CFG_BASE(port, NIC0_QPC0_GW_BUSY);
+
+ rc = gaudi2_cn_poll_reg(hdev, addr, hdev->qpc_cache_inv_timeout, qpc_op_cond_func,
+ NULL);
+ }
+
+ return rc;
+}
+
+static int gaudi2_cn_qpc_write_masked(struct hbl_cn_port *cn_port, const void *qpc_data,
+ const struct qpc_mask *qpc_mask, u32 qpn, bool is_req,
+ bool force_doorbell)
+{
+ struct hbl_cn_device *hdev;
+ u32 port, data_size, ctrl;
+ const u32 *mask, *data;
+ int i, rc;
+
+ hdev = cn_port->hdev;
+ port = cn_port->port;
+ data_size = is_req ? sizeof(struct gaudi2_qpc_requester) :
+ sizeof(struct gaudi2_qpc_responder);
+ mask = (const u32 *)qpc_mask;
+ data = qpc_data;
+
+ /* Don't write to the Gw if its busy with prev operation */
+ if (NIC_RREG32(NIC0_QPC0_GW_BUSY)) {
+ if (hbl_cn_comp_device_operational(hdev))
+ dev_err(hdev->dev, "Cannot write to port %d QP %d %s QPC, GW is busy\n",
+ port, qpn, is_req ? "requester" : "responder");
+
+ return (hdev->in_teardown && hdev->hw_invalid_while_teardown) ? 0 : -EBUSY;
+ }
+
+ /* Copy the mask and data to the gateway regs.
+ * Only the data bits with their corresponding mask-bits set will be written
+ * to the HW.
+ */
+ for (i = 0; i < (sizeof(struct qpc_mask) / sizeof(u32)); i++)
+ NIC_WREG32(NIC0_QPC0_GW_MASK_0 + i * sizeof(u32), mask[i]);
+
+ for (i = 0; i < (data_size / sizeof(u32)); i++)
+ NIC_WREG32(NIC0_QPC0_GW_DATA_0 + i * sizeof(u32), data[i]);
+
+ ctrl = (is_req << NIC0_QPC0_GW_CTRL_REQUESTER_SHIFT) | qpn |
+ (!!force_doorbell << NIC0_QPC0_GW_CTRL_DOORBELL_FORCE_SHIFT);
+
+ rc = gaudi2_cn_qpc_op(cn_port, ctrl, true);
+ if (rc && hbl_cn_comp_device_operational(hdev))
+ /* Device might not respond during reset if the reset was due to error */
+ dev_err(hdev->dev, "%s QPC GW write timeout, port: %d, qpn: %u\n",
+ is_req ? "requester" : "responder", port, qpn);
+
+ return rc;
+}
+
+bool gaudi2_handle_qp_error_retry(struct hbl_cn_port *cn_port, u32 qpn)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct gaudi2_qpc_requester req_qpc = {};
+ struct qpc_mask mask = {};
+ int port = cn_port->port;
+ u8 max_retry_timeout;
+ struct hbl_cn_qp *qp;
+ int rc, retry = 5;
+ u8 timeout_max;
+ u64 wq_delay;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+ port_funcs->cfg_lock(cn_port);
+ qp = xa_load(&cn_port->qp_ids, qpn);
+
+ if (!qp) {
+ port_funcs->cfg_unlock(cn_port);
+ dev_err(hdev->dev, "adaptive retry, port %d, QP: %d is null\n",
+ port, qpn);
+
+ return false;
+ }
+
+ cancel_delayed_work(&qp->adaptive_tmr_reset);
+
+ timeout_max = qp->timeout_granularity + NIC_ADAPTIVE_TIMEOUT_RANGE / 2;
+ if (qp->timeout_curr < timeout_max) {
+ qp->timeout_curr++;
+ /* clear QP error */
+ REQ_QPC_SET_ERR(mask, 1);
+ REQ_QPC_SET_ERR(req_qpc, 0);
+ REQ_QPC_SET_TIMEOUT_RETRY_COUNT(mask, 0xff);
+ REQ_QPC_SET_TIMEOUT_RETRY_COUNT(req_qpc, 0);
+ REQ_QPC_SET_TM_GRANULARITY(mask, 0x7f);
+ REQ_QPC_SET_TM_GRANULARITY(req_qpc, qp->timeout_curr);
+
+ do {
+ rc = gaudi2_cn_qpc_write_masked(cn_port, &req_qpc, &mask, qp->qp_id,
+ true, true);
+ if (rc)
+ dev_err(hdev->dev, "failed to write QPC port %d, %d, err %d\n",
+ port, qpn, rc);
+
+ rc = gaudi2_cn_qpc_read(cn_port, &req_qpc, qp->qp_id, true);
+ if (rc)
+ dev_err(hdev->dev, "failed to read QPC port %d, %d, err %d\n",
+ port, qpn, rc);
+ if (!REQ_QPC_GET_ERROR(req_qpc))
+ break;
+ retry--;
+ } while (retry);
+
+ if (!retry) {
+ port_funcs->cfg_unlock(cn_port);
+ dev_err(hdev->dev, "failed to clear QPC error port %d, %d\n", port, qpn);
+
+ return false;
+ }
+
+ dev_dbg_ratelimited(hdev->dev, "dropping Port-%d QP error on qp %d\n",
+ port, qp->qp_id);
+
+ max_retry_timeout = GAUDI2_NIC_MAX_TIMEOUT_RETRIES / NIC_ADAPTIVE_TIMEOUT_RANGE;
+ wq_delay = NIC_GRAN_TO_USEC(qp->timeout_curr) * max_retry_timeout *
+ NIC_TMR_RESET_FACTOR;
+ queue_delayed_work(cn_port->qp_wq, &qp->adaptive_tmr_reset,
+ msecs_to_jiffies(wq_delay / 1000));
+
+ port_funcs->cfg_unlock(cn_port);
+
+ return true;
+ }
+
+ qp->timeout_curr = qp->timeout_granularity - (NIC_ADAPTIVE_TIMEOUT_RANGE >> 1);
+
+ port_funcs->cfg_unlock(cn_port);
+
+ return false;
+}
+
+static int gaudi2_cn_qpc_write(struct hbl_cn_port *cn_port, void *qpc, struct qpc_mask *qpc_mask,
+ u32 qpn, bool is_req)
+{
+ u32 data_size = is_req ? sizeof(struct gaudi2_qpc_requester) :
+ sizeof(struct gaudi2_qpc_responder);
+ struct qpc_mask mask = {};
+
+ if (!qpc_mask) {
+ /* NULL mask flags full QPC write */
+ memset(&mask, 0xFF, data_size);
+ qpc_mask = &mask;
+ }
+
+ return gaudi2_cn_qpc_write_masked(cn_port, qpc, qpc_mask, qpn, is_req, false);
+}
+
+static int gaudi2_cn_qpc_invalidate(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp, bool is_req)
+{
+ struct gaudi2_qpc_requester req_qpc = {};
+ struct gaudi2_qpc_responder res_qpc = {};
+ struct qpc_mask mask = {};
+ void *qpc;
+ int rc;
+
+ if (is_req) {
+ /* use Congestion window mode with RTT state disabled &
+ * window size 0 to force REQ Tx stop, while Rx remains
+ * active.
+ */
+ REQ_QPC_SET_CONGESTION_MODE(mask, 3);
+ REQ_QPC_SET_RTT_STATE(mask, 3);
+ REQ_QPC_SET_CONGESTION_WIN(mask, GENMASK(23, 0));
+
+ REQ_QPC_SET_CONGESTION_MODE(req_qpc, 2);
+ REQ_QPC_SET_RTT_STATE(req_qpc, 0);
+ REQ_QPC_SET_CONGESTION_WIN(req_qpc, 0);
+ qpc = &req_qpc;
+ } else {
+ RES_QPC_SET_VALID(mask, 1);
+ RES_QPC_SET_VALID(res_qpc, 0);
+ qpc = &res_qpc;
+ }
+
+ rc = gaudi2_cn_qpc_write_masked(cn_port, qpc, &mask, qp->qp_id, is_req, false);
+
+ if (is_req) {
+ /* Allow CQ overrun to make sure QP drain is successful. In case PFC is sent due to
+ * CQ overflow, no Tx can be sent until CQ releases the back-pressure. If in the
+ * meanwhile a QP needs to be invalidated, no tx will be sent in the QP drain stage.
+ * This will cause Tx slices to be stuck after the QP drain stage has finished.
+ * Next when the CQ will be destroyed, it will release the back-pressure, causing
+ * the stuck Tx slices to be sent (as there's no more back-pressure). Since no QP
+ * is allocated anymore, AXI errors and QP invalid errors will be received.
+ * As a workaround to the issue above, allow overrun to the associated CQ of the
+ * invalidated QP. This will release the back-pressure before the drain stage, and
+ * will allow all needed tx packets to be drained successfully. Once the drain stage
+ * is done, and the QP is cleared, disable CQ overrun.
+ */
+ if (!qp->force_cq_overrun && qp->req_user_cq) {
+ qp->force_cq_overrun = true;
+ gaudi2_user_cq_set_overrun(qp->req_user_cq, true);
+ }
+
+ /* H/W bug H6-3379: the TXE WQ cache is disabled, thus no need to invalidate it */
+ }
+
+ return rc;
+}
+
+static int gaudi2_cn_qpc_clear(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp, bool is_req)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct gaudi2_qpc_requester req_qpc = {};
+ struct gaudi2_qpc_responder res_qpc = {};
+ u32 port = cn_port->port;
+ struct qpc_mask mask;
+ void *qpc;
+ int rc;
+
+ qpc = is_req ? (void *)&req_qpc : (void *)&res_qpc;
+
+ if (qp->force_cq_overrun && is_req) {
+ qp->force_cq_overrun = false;
+ if (qp->req_user_cq)
+ gaudi2_user_cq_set_overrun(qp->req_user_cq, false);
+ }
+
+ memset(&mask, 0xFF, sizeof(mask));
+
+ rc = gaudi2_cn_qpc_write_masked(cn_port, qpc, &mask, qp->qp_id, is_req, false);
+ if (rc)
+ return rc;
+
+ if (is_req) {
+ /* Invalidate RXE WQE cache */
+ NIC_RMWREG32(NIC0_RXE0_CACHE_CFG, 1, NIC0_RXE0_CACHE_CFG_INVALIDATION_MASK);
+ NIC_RREG32(NIC0_RXE0_CACHE_CFG);
+
+ NIC_RMWREG32(NIC0_RXE0_CACHE_CFG, 0, NIC0_RXE0_CACHE_CFG_INVALIDATION_MASK);
+ NIC_RREG32(NIC0_RXE0_CACHE_CFG);
+ }
+
+ return 0;
+}
+
+int gaudi2_cn_qpc_read(struct hbl_cn_port *cn_port, void *qpc, u32 qpn, bool is_req)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ bool force_doorbell = false;
+ u32 *data, port, size;
+ int i, rc;
+ u64 ctrl;
+
+ port = cn_port->port;
+ data = qpc;
+ size = is_req ? sizeof(struct gaudi2_qpc_requester) : sizeof(struct gaudi2_qpc_responder);
+
+ /* Don't write to the Gw if its busy with prev operation */
+ if (NIC_RREG32(NIC0_QPC0_GW_BUSY)) {
+ if (hbl_cn_comp_device_operational(hdev))
+ dev_err(hdev->dev, "Cannot read from port %d QP %d %s QPC, GW is busy\n",
+ port, qpn, is_req ? "requester" : "responder");
+
+ return (hdev->in_teardown && hdev->hw_invalid_while_teardown) ? 0 : -EBUSY;
+ }
+
+ /* Clear the mask gateway regs which will cause the operation to be a read */
+ for (i = 0; i < QPC_GW_MASK_REG_NUM; i++)
+ NIC_WREG32(NIC0_QPC0_GW_MASK_0 + i * sizeof(u32), 0);
+
+ ctrl = (is_req << NIC0_QPC0_GW_CTRL_REQUESTER_SHIFT) | qpn |
+ (!!force_doorbell << NIC0_QPC0_GW_CTRL_DOORBELL_FORCE_SHIFT);
+ rc = gaudi2_cn_qpc_op(cn_port, ctrl, true);
+ if (rc)
+ return rc;
+
+ for (i = 0; i < size / sizeof(u32); i++)
+ data[i] = NIC_RREG32(NIC0_QPC0_GW_DATA_0 + i * sizeof(u32));
+
+ return 0;
+}
+
+static int gaudi2_cn_qpc_query(struct hbl_cn_port *cn_port, u32 qpn, bool is_req,
+ struct hbl_cn_qpc_attr *attr)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct gaudi2_qpc_requester req_qpc;
+ struct gaudi2_qpc_responder res_qpc;
+ u32 port = cn_port->port;
+ int rc;
+
+ if (is_req) {
+ rc = gaudi2_cn_qpc_read(cn_port, (void *)&req_qpc, qpn, is_req);
+ if (rc)
+ goto out_err;
+
+ attr->valid = REQ_QPC_GET_VALID(req_qpc);
+ attr->in_work = REQ_QPC_GET_IN_WORK(req_qpc);
+ attr->error = REQ_QPC_GET_ERROR(req_qpc);
+ } else {
+ rc = gaudi2_cn_qpc_read(cn_port, (void *)&res_qpc, qpn, is_req);
+ if (rc)
+ goto out_err;
+
+ attr->valid = RES_QPC_GET_VALID(res_qpc);
+ attr->in_work = RES_QPC_GET_IN_WORK(res_qpc);
+ attr->conn_state = RES_QPC_GET_CONN_STATE(res_qpc);
+ }
+
+ return 0;
+
+out_err:
+ dev_err(hdev->dev, "%s QPC GW read timeout, port: %d, qpn: %u\n",
+ is_req ? "requester" : "responder", port, qpn);
+ return rc;
+}
+
+int gaudi2_cn_wqe_read(struct hbl_cn_port *cn_port, void *wqe, u32 qpn, u32 wqe_idx, bool is_tx)
+{
+ u64 wq_base_addr_upper, wq_base_addr_lower, wq_size_cline_log, ctrl,
+ req_qpc_base_addr_upper, req_qpc_base_addr_lower, wqe_offset;
+ u32 *data, port, wqe_cline_idx, num_of_wqe_in_cline;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ int i, rc;
+
+ port = cn_port->port;
+ data = wqe;
+
+ if (is_tx) {
+ wq_base_addr_upper = NIC_RREG32(NIC0_TXE0_SQ_BASE_ADDRESS_63_32_1);
+ wq_base_addr_lower = NIC_RREG32(NIC0_TXE0_SQ_BASE_ADDRESS_31_0_1);
+ wq_size_cline_log = NIC_RREG32(NIC0_TXE0_LOG_MAX_WQ_SIZE_1);
+ num_of_wqe_in_cline = TX_WQE_NUM_IN_CLINE;
+ } else {
+ wq_base_addr_upper = NIC_RREG32(NIC0_RXE0_WIN1_WQ_BASE_HI);
+ wq_base_addr_lower = NIC_RREG32(NIC0_RXE0_WIN1_WQ_BASE_LO);
+ wq_size_cline_log = NIC_RREG32(NIC0_RXE0_WIN1_WQ_MISC);
+ num_of_wqe_in_cline = RX_WQE_NUM_IN_CLINE;
+ }
+ wqe_cline_idx = wqe_idx / num_of_wqe_in_cline;
+
+ req_qpc_base_addr_upper = NIC_RREG32(NIC0_TXE0_SQ_BASE_ADDRESS_63_32_1);
+ req_qpc_base_addr_lower = NIC_RREG32(NIC0_QPC0_REQ_BASE_ADDRESS_31_7);
+
+ /* Don't write to the Gw if its busy with prev operation */
+ if (NIC_RREG32(NIC0_QPC0_GW_BUSY)) {
+ if (hbl_cn_comp_device_operational(hdev))
+ dev_err(hdev->dev,
+ "Cannot read wqe from port %d QP %d, GW is busy\n", port, qpn);
+
+ return -EBUSY;
+ }
+
+ WARN_ON_CACHE_UNALIGNED(wq_base_addr_lower);
+
+ /* Hacking the QPC base address to read WQ */
+ NIC_WREG32(NIC0_QPC0_REQ_BASE_ADDRESS_63_32, wq_base_addr_upper);
+ NIC_WREG32(NIC0_QPC0_REQ_BASE_ADDRESS_31_7, wq_base_addr_lower >> 7);
+
+ /* Clear the mask gateway regs which will cause the operation to be a read */
+ for (i = 0; i < QPC_GW_MASK_REG_NUM; i++)
+ NIC_WREG32(NIC0_QPC0_GW_MASK_0 + i * sizeof(u32), 0);
+
+ /* Calculate the WQE offset in cache line units */
+ wqe_offset = (1ULL << wq_size_cline_log) * qpn + wqe_cline_idx;
+ ctrl = NIC0_QPC0_GW_CTRL_REQUESTER_MASK + wqe_offset;
+ rc = gaudi2_cn_qpc_op(cn_port, ctrl, true);
+ if (rc)
+ goto exit;
+
+ /* H/W reads in cache line size */
+ for (i = 0; i < 32; i++)
+ data[i] = NIC_RREG32(NIC0_QPC0_GW_DATA_0 + i * sizeof(u32));
+
+exit:
+ /* Restore the configuration */
+ NIC_WREG32(NIC0_QPC0_REQ_BASE_ADDRESS_63_32, req_qpc_base_addr_upper);
+ NIC_WREG32(NIC0_QPC0_REQ_BASE_ADDRESS_31_7, req_qpc_base_addr_lower);
+
+ return rc;
+}
+
+static bool is_valid_mtu(u16 mtu)
+{
+ return (mtu == SZ_1K) || (mtu == SZ_2K) || (mtu == SZ_4K) || (mtu == SZ_8K);
+}
+
+static int normalize_priority(struct hbl_cn_device *hdev, u32 priority, enum hbl_ts_type type,
+ bool is_req, u32 *norm_priority)
+{
+ /* Ethernet and Responder get the highest priority */
+ if (!is_req || type == TS_RAW) {
+ *norm_priority = GAUDI2_PFC_PRIO_DRIVER;
+ return 0;
+ }
+
+ /* Req priority can vary from 1 to 3 */
+ if (priority < GAUDI2_PFC_PRIO_USER_BASE || priority >= HBL_EN_PFC_PRIO_NUM)
+ return -EINVAL;
+
+ *norm_priority = priority;
+ return 0;
+}
+
+static u32 gaudi2_cn_txs_get_schedq_num(u32 priority, bool is_req)
+{
+ u32 prio_q_group;
+
+ /* prio-group numbering start from 1 - normalize it to Zero */
+ prio_q_group = (is_req ? TXS_PORT_REQ_SCHED_Q : TXS_PORT_RES_SCHED_Q);
+
+ return prio_q_group * HBL_EN_PFC_PRIO_NUM + priority;
+}
+
+static void gaudi2_default_encap_set(struct hbl_cn_port *cn_port, u32 *encap_id, u32 src_ip)
+{
+ struct hbl_cn_encap_xarray_pdata encap_data;
+ u8 dummy_hdr[NIC_MAX_TNL_HDR_SIZE] = {};
+
+ gaudi2_get_default_encap_id(cn_port, encap_id);
+
+ if (!src_ip && hbl_cn_get_src_ip(cn_port, &src_ip)) {
+ dev_dbg(cn_port->hdev->dev, "failed to get interface IP, using 0\n");
+ src_ip = 0;
+ }
+
+ memset(dummy_hdr, 0xa5, sizeof(dummy_hdr));
+
+ encap_data.port = cn_port->port;
+ encap_data.id = *encap_id;
+ encap_data.src_ip = src_ip;
+ encap_data.encap_type = HBL_CNI_ENCAP_OVER_UDP;
+ encap_data.encap_type_data = DUMMY_UDP_PORT;
+ encap_data.encap_header = dummy_hdr;
+ encap_data.encap_header_size = sizeof(dummy_hdr);
+
+ gaudi2_encap_set(cn_port, *encap_id, &encap_data);
+}
+
+static int gaudi2_cn_validate_timeout(u8 gran)
+{
+ u64 tmr_timeout_us;
+ int ret = 0;
+
+ tmr_timeout_us = NIC_GRAN_TO_USEC(gran);
+
+ /* This check guarantees that we can't overflow the PSN window within a timer period,
+ * meaning that it needs to ensure that the time it takes to transmit the total amount
+ * of bits ofall packets is greater than the timeout value. note that we take the
+ * "worst case" values, i.e. min MTU and max speed.
+ *
+ * MAX_CONG_WND * MIN_MTU [bits]
+ * ----------------------------- > TIMEOUT [s]
+ * SPEED [bits/s]
+ *
+ * ==>
+ *
+ * GAUDI2_NIC_MAX_CONG_WND * (NIC_RAW_MIN_MTU [bytes] * BITS_PER_BYTE)
+ * ------------------------------------------------------------------- >
+ * GAUDI2_NIC_MAX_SPEED [Mbits/sec] * 1M
+ *
+ * NIC_TMR_TIMEOUT_US [usec]
+ * -------------------------
+ * 1M
+ * ==>
+ *
+ * GAUDI2_NIC_MAX_CONG_WND * (NIC_RAW_MIN_MTU * BITS_PER_BYTE) >
+ * NIC_TMR_TIMEOUT_US * GAUDI2_NIC_MAX_SPEED
+ */
+ if ((((u64)GAUDI2_NIC_MAX_CONG_WND) * ((u64)(NIC_RAW_MIN_MTU * BITS_PER_BYTE))) <=
+ (tmr_timeout_us * ((u64)GAUDI2_NIC_MAX_SPEED)))
+ ret = -EINVAL;
+
+ return ret;
+}
+
+static int gaudi2_set_req_qp_ctx(struct hbl_cn_device *hdev, struct hbl_cni_req_conn_ctx_in *in,
+ struct hbl_cn_qp *qp)
+{
+ u8 mac[ETH_ALEN], cqn, encap_en, timer_granularity;
+ struct gaudi2_qpc_requester req_qpc;
+ struct gaudi2_cn_port *gaudi2_port;
+ struct hbl_cn_user_cq *user_cq;
+ struct hbl_en_aux_ops *aux_ops;
+ u32 port, priority, encap_id;
+ struct hbl_cn_port *cn_port;
+ struct hbl_aux_dev *aux_dev;
+ int rc;
+
+ port = in->port;
+ cn_port = &hdev->cn_ports[port];
+ gaudi2_port = cn_port->cn_specific;
+ aux_dev = &hdev->en_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ /* In case user didn't set encap, unset for internal ports. */
+ encap_id = 0;
+ encap_en = 0;
+
+ /* Enforce sender (remote) WQ to be at least 4 times bigger than receiver WQ to avoid H/W
+ * bug - RDV roll-back may stuck the QP.
+ */
+ if (in->wq_type == QPC_REQ_WQ_TYPE_WRITE && in->wq_remote_log_size &&
+ (in->wq_size * 4 > BIT(in->wq_remote_log_size))) {
+ dev_dbg(hdev->dev, "Invalid RDV WQ size. local %d, remote %lu, port %d\n",
+ in->wq_size, BIT(in->wq_remote_log_size), port);
+ return -EINVAL;
+ }
+
+ if (in->mtu && !is_valid_mtu(in->mtu)) {
+ dev_dbg(hdev->dev, "MTU of %u is not supported, port %d\n", in->mtu, port);
+ return -EINVAL;
+ }
+
+ if (normalize_priority(hdev, in->priority, TS_RC, true, &priority)) {
+ dev_dbg(hdev->dev, "Unsupported priority value %u, port %d\n", in->priority, port);
+ return -EINVAL;
+ }
+
+ /* H6-3399: Below configuration isn't valid due to H/W bug, i.e.: using encap_id for src IP
+ * settings w/o encapsulation isn't allowed.
+ */
+ if (!in->encap_en && in->encap_id) {
+ dev_dbg(hdev->dev,
+ "Encapsulation ID %d can't be set when encapsulation disable, port %d\n",
+ in->encap_id, port);
+ return -EINVAL;
+ }
+
+ /* Due to H/W bug H6-3280, it was decided to allow congestion control for external ports
+ * only - the user shouldn't enable it for internal ports.
+ */
+ if (!cn_port->eth_enable && in->congestion_en) {
+ dev_err(hdev->dev,
+ "congestion control should be disabled for internal ports, port %d mode %u\n",
+ port, in->congestion_en);
+ return -EINVAL;
+ }
+
+ if (cn_port->bp_enable && in->wq_size < GAUDI2_NIC_MIN_WQ_SIZE_BP_ENABLED) {
+ dev_err(hdev->dev,
+ "WQ size (%d) can't be smaller than %d when back pressure is enabled, port %d\n",
+ in->wq_size, GAUDI2_NIC_MIN_WQ_SIZE_BP_ENABLED, port);
+ return -EINVAL;
+ }
+
+ timer_granularity = hdev->pldm ? NIC_TMR_TIMEOUT_PLDM_GRAN : in->timer_granularity;
+
+ /* gran 0 is a special case for the highest timeout supported by hw */
+ if (timer_granularity && gaudi2_cn_validate_timeout(timer_granularity)) {
+ dev_err(hdev->dev,
+ "timer granularity %d is not supported\n", timer_granularity);
+ return -EINVAL;
+ }
+
+ if (gaudi2_port->adaptive_timeout_en) {
+ qp->timeout_granularity = timer_granularity;
+ qp->timeout_curr = timer_granularity - (NIC_ADAPTIVE_TIMEOUT_RANGE >> 1);
+ timer_granularity = qp->timeout_curr;
+ }
+
+ if (in->cq_number) {
+ /* User CQ. */
+ cqn = in->cq_number;
+
+ user_cq = hbl_cn_user_cq_get(cn_port, cqn);
+ if (!user_cq) {
+ dev_dbg(hdev->dev, "CQ %d is invalid, port %d\n", cqn, port);
+ return -EINVAL;
+ }
+
+ qp->req_user_cq = user_cq;
+ } else {
+ /* No CQ. */
+ cqn = NIC_CQ_RDMA_IDX;
+ }
+
+ if (cn_port->eth_enable)
+ memcpy(mac, in->dst_mac_addr, ETH_ALEN);
+ else
+ /* in this case the MAC is irrelevant so use broadcast */
+ eth_broadcast_addr(mac);
+
+ memset(&req_qpc, 0, sizeof(req_qpc));
+
+ REQ_QPC_SET_DST_QP(req_qpc, in->dst_conn_id);
+ REQ_QPC_SET_PORT(req_qpc, 0); /* Always select lane 0 */
+ REQ_QPC_SET_PRIORITY(req_qpc, 3);
+ REQ_QPC_SET_RKEY(req_qpc, qp->remote_key);
+ REQ_QPC_SET_DST_IP(req_qpc, in->dst_ip_addr);
+ REQ_QPC_SET_DST_MAC_LSB(req_qpc, *(u32 *)mac);
+ REQ_QPC_SET_DST_MAC_MSB(req_qpc, *(u16 *)(mac + 4));
+
+ REQ_QPC_SET_SCHD_Q_NUM(req_qpc, gaudi2_cn_txs_get_schedq_num(priority, true));
+ REQ_QPC_SET_TM_GRANULARITY(req_qpc, timer_granularity);
+
+ REQ_QPC_SET_TRANSPORT_SERVICE(req_qpc, TS_RC);
+ REQ_QPC_SET_BURST_SIZE(req_qpc, QPC_REQ_BURST_SIZE);
+ REQ_QPC_SET_LAST_IDX(req_qpc, in->wq_size - 1);
+
+ REQ_QPC_SET_WQ_BASE_ADDR(req_qpc, 1);
+
+ /* In case the user didn't specify MTU, set the one from netdev.
+ * If there is no netdev, use the default value.
+ */
+ if (in->mtu) {
+ qp->mtu = in->mtu;
+ qp->mtu_type = MTU_FROM_USER;
+ } else if (cn_port->eth_enable) {
+ if (aux_ops->get_mtu)
+ qp->mtu = aux_ops->get_mtu(aux_dev, port) + HBL_EN_MAX_HEADERS_SZ;
+ else
+ qp->mtu = GAUDI2_NIC_MTU_DEFAULT;
+
+ qp->mtu_type = MTU_FROM_NETDEV;
+ } else {
+ qp->mtu = GAUDI2_NIC_MTU_DEFAULT;
+ qp->mtu_type = MTU_DEFAULT;
+ }
+
+ REQ_QPC_SET_MTU(req_qpc, ilog2(roundup_pow_of_two(qp->mtu)) - 10);
+
+ /* GAUDI1 mode is not used and hence set to 0 */
+ REQ_QPC_SET_MOD_GAUDI1(req_qpc, 0);
+ REQ_QPC_SET_SWQ_GRANULARITY(req_qpc, in->swq_granularity);
+ REQ_QPC_SET_CQ_NUM(req_qpc, cqn);
+
+ /* Protect the HW from zero value */
+ REQ_QPC_SET_REMOTE_WQ_LOG_SZ(req_qpc, in->wq_remote_log_size ? in->wq_remote_log_size : 2);
+
+ /* config MMU-BP */
+ REQ_QPC_SET_DATA_MMU_BYPASS(req_qpc, 0);
+
+ /* ASID is also used as protection-domain, so always configure it */
+ REQ_QPC_SET_ASID(req_qpc, qp->ctx->user_asid);
+
+ REQ_QPC_SET_ACKREQ_FREQ(req_qpc, 8);
+ REQ_QPC_SET_WQ_TYPE(req_qpc, in->wq_type);
+
+ /* user QP - unsecured trust level */
+ REQ_QPC_SET_TRUST_LEVEL(req_qpc, UNSECURED);
+
+ /* Congestion control configurations are done for external ports only - for internal ports
+ * congestion control will be disabled.
+ */
+ if (cn_port->eth_enable) {
+ u32 congestion_wnd;
+
+ if (in->congestion_wnd > GAUDI2_NIC_MAX_CONG_WND) {
+ dev_dbg(hdev->dev,
+ "Congestion window size(%u) can't be > max allowed size(%lu), port %d\n",
+ in->congestion_wnd, GAUDI2_NIC_MAX_CONG_WND, port);
+ return -EINVAL;
+ }
+
+ /* congestion_mode:
+ * 0: no congestion
+ * 1: congestion control (BBR/SWIFT)
+ * 2: congestion window
+ *
+ * REQ_QPC_SET_CONGESTION_MODE set those modes.
+ * REQ_QPC_SET_RTT_STATE enable the CC-CQ mechanism (relevant for BBR/SWIFT only).
+ * when user does not set congestion_en we set congestion to mode 2
+ * so we still have cc via the CONGESTION_WIN.
+ */
+ REQ_QPC_SET_CONGESTION_MODE(req_qpc, (in->congestion_en) ? 1 : 2);
+
+ REQ_QPC_SET_RTT_STATE(req_qpc, in->congestion_en);
+
+ congestion_wnd = in->congestion_wnd ? in->congestion_wnd : GAUDI2_NIC_MAX_CONG_WND;
+ REQ_QPC_SET_CONGESTION_WIN(req_qpc, congestion_wnd);
+ }
+
+ if (in->encap_en) {
+ encap_id = in->encap_id;
+ encap_en = in->encap_en;
+ } else if (cn_port->eth_enable) {
+ gaudi2_get_default_encap_id(cn_port, &encap_id);
+ encap_en = 1;
+ }
+
+ REQ_QPC_SET_ENCAP_ENABLE(req_qpc, encap_en);
+ REQ_QPC_SET_ENCAP_TYPE(req_qpc, encap_id);
+
+ REQ_QPC_SET_VALID(req_qpc, 1);
+
+ rc = gaudi2_cn_qpc_write(cn_port, &req_qpc, NULL, in->conn_id, true);
+ if (rc)
+ goto qpc_write_fail;
+
+ if (gaudi2_port->advanced && cn_port->bp_enable &&
+ in->wq_size < gaudi2_port->min_qp_size) {
+ gaudi2_port->min_qp_size = in->wq_size;
+
+ /* The back-pressure thresholds values describe the occupancy of the QP,
+ * thus should be configured to be the size of the smallest QP minus some
+ * defined numbers (currently 24/26 for the upper/lower thresholds
+ * respectively).
+ */
+ NIC_WREG32(NIC0_QPC0_WQ_UPPER_THRESHOLD,
+ gaudi2_port->min_qp_size - GAUDI2_NIC_WTD_BP_UPPER_TH_DIFF);
+ NIC_WREG32(NIC0_QPC0_WQ_LOWER_THRESHOLD,
+ gaudi2_port->min_qp_size - GAUDI2_NIC_WTD_BP_LOWER_TH_DIFF);
+ }
+
+ return 0;
+
+qpc_write_fail:
+ if (qp->req_user_cq) {
+ hbl_cn_user_cq_put(qp->req_user_cq);
+ qp->req_user_cq = NULL;
+ }
+
+ return rc;
+}
+
+static int gaudi2_set_res_qp_ctx(struct hbl_cn_device *hdev, struct hbl_cni_res_conn_ctx_in *in,
+ struct hbl_cn_qp *qp)
+{
+ u8 mac[ETH_ALEN], cqn, encap_en, wq_mmu_bypass;
+ u32 port = in->port, priority, encap_id;
+ struct gaudi2_qpc_responder res_qpc;
+ struct hbl_cn_user_cq *user_cq;
+ struct hbl_cn_port *cn_port;
+ int rc;
+
+ cn_port = &hdev->cn_ports[port];
+
+ /* In case user didn't set encap, unset for internal ports. */
+ encap_id = 0;
+ encap_en = 0;
+
+ /* H6-3399: Below configuration isn't valid due to H/W bug, i.e.: using encap_id for src IP
+ * settings w/o encapsulation isn't allowed.
+ */
+ if (!in->encap_en && in->encap_id) {
+ dev_dbg(hdev->dev,
+ "Encapsulation ID %d can't be set when encapsulation disable, port %d\n",
+ in->encap_id, port);
+ return -EINVAL;
+ }
+
+ if (cn_port->eth_enable)
+ memcpy(mac, in->dst_mac_addr, ETH_ALEN);
+ else
+ /* in this case the MAC is irrelevant so use broadcast */
+ eth_broadcast_addr(mac);
+
+ if (normalize_priority(hdev, in->priority, TS_RC, false, &priority)) {
+ dev_dbg(hdev->dev, "Unsupported priority value %u, port %d\n", in->priority, port);
+ return -EINVAL;
+ }
+
+ if (in->cq_number) {
+ /* User CQ. */
+ cqn = in->cq_number;
+
+ user_cq = hbl_cn_user_cq_get(cn_port, cqn);
+ if (!user_cq) {
+ dev_dbg(hdev->dev, "CQ %d is invalid, port %d\n", cqn, port);
+ return -EINVAL;
+ }
+
+ qp->res_user_cq = user_cq;
+ } else {
+ /* No CQ. */
+ cqn = NIC_CQ_RDMA_IDX;
+ }
+
+ memset(&res_qpc, 0, sizeof(res_qpc));
+
+ RES_QPC_SET_DST_QP(res_qpc, in->dst_conn_id);
+ RES_QPC_SET_PORT(res_qpc, 0); /* Always select lane 0 */
+ RES_QPC_SET_PRIORITY(res_qpc, 2);
+ RES_QPC_SET_LKEY(res_qpc, qp->local_key);
+ RES_QPC_SET_DST_IP(res_qpc, in->dst_ip_addr);
+ RES_QPC_SET_DST_MAC_LSB(res_qpc, *(u32 *)mac);
+ RES_QPC_SET_DST_MAC_MSB(res_qpc, *(u16 *)(mac + 4));
+
+ RES_QPC_SET_TRANSPORT_SERVICE(res_qpc, TS_RC);
+
+ /* config MMU-BP
+ * In RDV QPs, the responded side is not used for 'real' user data but
+ * rather to pass WQEs as data, therefore the QPC MMU-BP attribute shall
+ * be taken according to the configuration of the WQ array.
+ */
+ wq_mmu_bypass = cn_port->wq_arr_props[HBL_CNI_USER_WQ_SEND].wq_mmu_bypass;
+
+ if (!(in->rdv && wq_mmu_bypass))
+ RES_QPC_SET_DATA_MMU_BYPASS(res_qpc, 0);
+ else
+ RES_QPC_SET_DATA_MMU_BYPASS(res_qpc, 1);
+
+ /* ASID is also used as protection-domain, so always configure it */
+ RES_QPC_SET_ASID(res_qpc, qp->ctx->user_asid);
+
+ RES_QPC_SET_PEER_QP(res_qpc, in->conn_peer);
+ RES_QPC_SET_SCHD_Q_NUM(res_qpc, gaudi2_cn_txs_get_schedq_num(priority, false));
+
+ /* for rdv QPs RXE responder takes its security-level from QPC */
+ if (in->rdv)
+ RES_QPC_SET_TRUST_LEVEL(res_qpc, SECURED);
+ else
+ RES_QPC_SET_TRUST_LEVEL(res_qpc, UNSECURED);
+
+ /* GAUDI1 mode is not used and hence set to 0 */
+ RES_QPC_SET_MOD_GAUDI1(res_qpc, 0);
+
+ RES_QPC_SET_CQ_NUM(res_qpc, cqn);
+ RES_QPC_SET_PEER_WQ_GRAN(res_qpc, in->wq_peer_granularity);
+
+ if (in->encap_en) {
+ encap_id = in->encap_id;
+ encap_en = in->encap_en;
+ } else if (cn_port->eth_enable) {
+ gaudi2_get_default_encap_id(cn_port, &encap_id);
+ encap_en = 1;
+ }
+
+ RES_QPC_SET_ENCAP_ENABLE(res_qpc, encap_en);
+ RES_QPC_SET_ENCAP_TYPE(res_qpc, encap_id);
+
+ RES_QPC_SET_VALID(res_qpc, 1);
+
+ rc = gaudi2_cn_qpc_write(cn_port, &res_qpc, NULL, in->conn_id, false);
+ if (rc)
+ goto qpc_write_fail;
+
+ return 0;
+
+qpc_write_fail:
+ if (qp->res_user_cq) {
+ hbl_cn_user_cq_put(qp->res_user_cq);
+ qp->res_user_cq = NULL;
+ }
+
+ return rc;
+}
+
+static int gaudi2_cn_update_qp_mtu(struct hbl_cn_port *cn_port, struct hbl_cn_qp *qp, u32 mtu)
+{
+ struct gaudi2_qpc_requester req_qpc = {};
+ struct qpc_mask mask = {};
+
+ /* MTU field is 2 bits wide */
+ REQ_QPC_SET_MTU(mask, 0x3);
+ REQ_QPC_SET_MTU(req_qpc, ilog2(roundup_pow_of_two(mtu)) - 10);
+
+ return gaudi2_cn_qpc_write_masked(cn_port, &req_qpc, &mask, qp->qp_id, true, false);
+}
+
+static int gaudi2_user_wq_arr_set(struct hbl_cn_device *hdev, struct hbl_cni_user_wq_arr_set_in *in,
+ struct hbl_cni_user_wq_arr_set_out *out, struct hbl_cn_ctx *ctx)
+{
+ u64 wq_base_addr, wq_size_cline_log, wq_size, wq_arr_size, num_of_wqs, num_of_wq_entries;
+ u32 wqe_size, rw_asid, type, port, wqe_asid, alignment_size;
+ struct hbl_cn_wq_array_properties *wq_arr_props;
+ struct hbl_cn_mem_data mem_data = {};
+ struct gaudi2_cn_port *gaudi2_port;
+ struct hbl_cn_port *cn_port;
+ bool phys_addr = true;
+ int rc;
+
+ type = in->type;
+ port = in->port;
+ cn_port = &hdev->cn_ports[port];
+ gaudi2_port = cn_port->cn_specific;
+
+ wq_arr_props = &cn_port->wq_arr_props[type];
+ num_of_wqs = in->num_of_wqs;
+
+ if (wq_arr_props->is_send) {
+ wqe_size = (in->swq_granularity == HBL_CNI_SWQE_GRAN_64B) ?
+ NIC_SEND_WQE_SIZE_MULTI_STRIDE : NIC_SEND_WQE_SIZE;
+ cn_port->swqe_size = wqe_size;
+ } else {
+ wqe_size = NIC_RECV_WQE_SIZE;
+ }
+
+ if (in->mem_id == HBL_CNI_MEM_HOST) {
+ alignment_size = PAGE_SIZE / min(NIC_SEND_WQE_SIZE, NIC_RECV_WQE_SIZE);
+ num_of_wq_entries = ALIGN(in->num_of_wq_entries, alignment_size);
+ wq_size = num_of_wq_entries * wqe_size;
+ wqe_asid = ctx->asid;
+ wq_arr_props->wq_size = wq_size;
+ wq_size_cline_log = ilog2(wq_size / DEVICE_CACHE_LINE_SIZE);
+ mem_data.mem_id = HBL_CN_DRV_MEM_HOST_DMA_COHERENT;
+ } else {
+ num_of_wq_entries = in->num_of_wq_entries;
+ wq_size = ALIGN(num_of_wq_entries * wqe_size, DEVICE_CACHE_LINE_SIZE);
+ mem_data.mem_id = HBL_CN_DRV_MEM_DEVICE;
+ mem_data.in.device_mem_data.port = port;
+ mem_data.in.device_mem_data.type = type;
+ wqe_asid = hdev->kernel_asid;
+ /* device wants the size in units of cache-line */
+ wq_size_cline_log = ilog2((num_of_wq_entries * wqe_size) / DEVICE_CACHE_LINE_SIZE);
+ }
+
+ wq_arr_size = num_of_wqs * wq_size;
+
+ /* We use the MMU whenever the WQ allocation is more than the 4MB DMA coherent memory
+ * constraint. We need not allocate memory if we are using MMU. We reserve the VA in the
+ * PMMU and allocate the actual memory inside set_req_qp_ctx and map to this virtual address
+ * space.
+ */
+ if (wq_arr_size > DMA_COHERENT_MAX_SIZE && in->mem_id == HBL_CNI_MEM_HOST) {
+ if (!hdev->mmu_enable) {
+ dev_dbg(hdev->dev,
+ "MMU not enabled. For allocations greater than %llx, MMU needs to be enabled, wq_arr_size : 0x%llx, port: %d\n",
+ (u64)DMA_COHERENT_MAX_SIZE, wq_arr_size, port);
+ return -EINVAL;
+ }
+ phys_addr = false;
+
+ rc = hbl_cn_reserve_wq_dva(ctx, cn_port, wq_arr_size, type, &wq_base_addr);
+ if (rc)
+ return rc;
+ } else {
+ mem_data.size = wq_arr_size;
+
+ rc = hbl_cn_mem_alloc(ctx, &mem_data);
+ if (rc) {
+ dev_dbg(hdev->dev, "Failed to allocate WQ: %d\n", rc);
+ return rc;
+ }
+
+ wq_base_addr = mem_data.addr;
+ wq_arr_props->handle = mem_data.handle;
+ }
+
+ wq_arr_props->on_device_mem = in->mem_id == HBL_CNI_MEM_DEVICE;
+
+ dev_dbg(hdev->dev,
+ "port %d: WQ-> type:%u addr=0x%llx log_size:%llu wqe_asid:%u mmu_bp:%u\n", port,
+ type, wq_base_addr, wq_size_cline_log, wqe_asid, phys_addr ? 1 : 0);
+
+ if (wq_arr_props->is_send) {
+ NIC_WREG32(NIC0_TXE0_SQ_BASE_ADDRESS_63_32_1, upper_32_bits(wq_base_addr));
+ NIC_WREG32(NIC0_TXE0_SQ_BASE_ADDRESS_31_0_1, lower_32_bits(wq_base_addr));
+
+ NIC_WREG32(NIC0_TXE0_LOG_MAX_WQ_SIZE_1, wq_size_cline_log);
+
+ /* configure WQ MMU
+ * currently user app has the index of 1
+ */
+ if (phys_addr)
+ NIC_WREG32(NIC0_TXE0_WQE_USER_CFG,
+ NIC_RREG32(NIC0_TXE0_WQE_USER_CFG) | (1 << 1));
+ else
+ NIC_WREG32(NIC0_TXE0_WQE_USER_CFG,
+ NIC_RREG32(NIC0_TXE0_WQE_USER_CFG) & ~(1 << 1));
+
+ /* Set secured ASID config. The security is enabled for WQs on HBM such that it can
+ * be accessed only with process whose ASID is wqe_asid. Here we program ASID '0' so
+ * that only the CN HW can access the WQs on HBM.
+ * There is a provision to unset the previous ASID settings, so we set the
+ * ASID only in case of WQ on HBM and unset it in the wq_arr_unset.
+ */
+ if (wqe_asid != ctx->asid) {
+ rc = gaudi2_cn_config_wqe_asid(cn_port, wqe_asid, true);
+ if (rc)
+ goto set_asid_fail;
+ }
+
+ rw_asid = (ctx->asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT) |
+ (ctx->asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT);
+
+ NIC_WREG32(NIC0_QM0_AXUSER_NONSECURED_HB_ASID, rw_asid);
+ NIC_WREG32(NIC0_QM0_AXUSER_NONSECURED_HB_MMU_BP, phys_addr ? 0x1 : 0);
+
+ if (gaudi2_port->advanced) {
+ /* enable override of asid */
+ NIC_WREG32(NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_WR_OVRD_LO, 0xfffff800);
+ NIC_WREG32(NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_RD_OVRD_LO, 0xfffff800);
+ NIC_WREG32(NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_ASID, wqe_asid);
+ /* Configure MMU-BP override for TX-WQs */
+ NIC_WREG32(NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_HB_MMU_BP,
+ phys_addr ? 0x1 : 0);
+
+ /* configure the QPC with the Tx WQ parameters */
+ NIC_WREG32(NIC0_QPC0_TX_WQ_BASE_ADDR_63_32_1,
+ upper_32_bits(wq_base_addr));
+ NIC_WREG32(NIC0_QPC0_TX_WQ_BASE_ADDR_31_0_1, lower_32_bits(wq_base_addr));
+ NIC_WREG32(NIC0_QPC0_LOG_MAX_TX_WQ_SIZE_1, wq_size_cline_log);
+ NIC_WREG32(NIC0_QPC0_MMU_BYPASS_TX_WQ_1, phys_addr ? 0x1 : 0);
+
+ /* rendezvous configuration for send work queue */
+ NIC_WREG32(NIC0_RXE0_RDV_SEND_WQ_BASE_ADDR_HI,
+ upper_32_bits(wq_base_addr));
+ NIC_WREG32(NIC0_RXE0_RDV_SEND_WQ_BASE_ADDR_LO,
+ lower_32_bits(wq_base_addr));
+ NIC_WREG32(NIC0_RXE0_RDV_LOG_MAX_WQ_SIZE, wq_size_cline_log);
+
+ if (num_of_wq_entries < gaudi2_port->min_qp_size) {
+ gaudi2_port->min_qp_size = (u32)num_of_wq_entries;
+
+ /* The back-pressure thresholds values describe the occupancy of
+ * the QP, thus should be configured to be the size of the smallest
+ * QP minus some defined numbers (currently 4/8 for the
+ * upper/lower thresholds respectively).
+ */
+ NIC_WREG32(NIC0_QPC0_WQ_UPPER_THRESHOLD,
+ gaudi2_port->min_qp_size -
+ GAUDI2_NIC_WTD_BP_UPPER_TH_DIFF);
+ NIC_WREG32(NIC0_QPC0_WQ_LOWER_THRESHOLD,
+ gaudi2_port->min_qp_size -
+ GAUDI2_NIC_WTD_BP_LOWER_TH_DIFF);
+ }
+ }
+ } else {
+ NIC_WREG32(NIC0_RXE0_WIN1_WQ_BASE_HI, upper_32_bits(wq_base_addr));
+ NIC_WREG32(NIC0_RXE0_WIN1_WQ_BASE_LO, lower_32_bits(wq_base_addr));
+
+ NIC_WREG32(NIC0_RXE0_WIN1_WQ_MISC, wq_size_cline_log);
+
+ /* configure WQ MMU for RXE */
+ if (phys_addr)
+ NIC_WREG32(NIC0_RXE0_ARUSER_MMU_BP,
+ NIC_RREG32(NIC0_RXE0_ARUSER_MMU_BP) | (1 << 1));
+ else
+ NIC_WREG32(NIC0_RXE0_ARUSER_MMU_BP,
+ NIC_RREG32(NIC0_RXE0_ARUSER_MMU_BP) & ~(1 << 1));
+
+ if (wqe_asid != ctx->asid) {
+ /* enable override of asid bit before changing asid */
+ NIC_WREG32(NIC0_RXE0_WQE_ARUSER_HB_RD_OVRD_LO, 0xFFFFFc00);
+ /* change asid to secured asid */
+ NIC_WREG32(NIC0_RXE0_WQE_ARUSER_HB_ASID, wqe_asid);
+ } else {
+ NIC_WREG32(NIC0_RXE0_WQE_ARUSER_HB_RD_OVRD_LO, 0xFFFFFFFF);
+ }
+
+ if (gaudi2_port->advanced) {
+ /* enable override of asid */
+ NIC_WREG32(NIC0_QPC0_AXUSER_RXWQE_HB_WR_OVRD_LO, 0xFFFFF800);
+ NIC_WREG32(NIC0_QPC0_AXUSER_RXWQE_HB_RD_OVRD_LO, 0xFFFFF800);
+ NIC_WREG32(NIC0_QPC0_AXUSER_RXWQE_HB_ASID, wqe_asid);
+ /* Configure MMU-BP override for RX-WQs */
+ NIC_WREG32(NIC0_QPC0_AXUSER_RXWQE_HB_MMU_BP, phys_addr ? 0x1 : 0);
+
+ /* configure the QPC with the Rx WQ parameters */
+ NIC_WREG32(NIC0_QPC0_RX_WQ_BASE_ADDR_63_32_1,
+ upper_32_bits(wq_base_addr));
+ NIC_WREG32(NIC0_QPC0_RX_WQ_BASE_ADDR_31_0_1,
+ lower_32_bits(wq_base_addr));
+ NIC_WREG32(NIC0_QPC0_LOG_MAX_RX_WQ_SIZE_1, wq_size_cline_log);
+ NIC_WREG32(NIC0_QPC0_MMU_BYPASS_RX_WQ_1, phys_addr ? 0x1 : 0);
+
+ /* rendezvous configuration for receive work queue */
+ NIC_WREG32(NIC0_RXE0_WIN0_WQ_BASE_HI, (upper_32_bits(wq_base_addr)));
+ NIC_WREG32(NIC0_RXE0_WIN0_WQ_BASE_LO, lower_32_bits(wq_base_addr));
+ NIC_WREG32(NIC0_RXE0_WIN0_WQ_MISC, wq_size_cline_log);
+ }
+ }
+
+ /* We are using a separate flag for wq mmu bypass as the hdev->mmu_bypass is being used by
+ * other CN data structures.
+ */
+ wq_arr_props->wq_mmu_bypass = phys_addr;
+
+ return 0;
+
+set_asid_fail:
+ if (phys_addr)
+ hbl_cn_mem_destroy(hdev, mem_data.handle);
+ else
+ hbl_cn_unreserve_dva_block(ctx, wq_arr_props->dva_base, wq_arr_props->dva_size);
+
+ return rc;
+}
+
+static int gaudi2_user_wq_arr_unset(struct hbl_cn_ctx *ctx, struct hbl_cn_port *cn_port, u32 type)
+{
+ struct hbl_cn_wq_array_properties *wq_arr_props = &cn_port->wq_arr_props[type];
+ struct hbl_cn_device *hdev = ctx->hdev;
+ u32 port = cn_port->port;
+ int rc = 0;
+
+ if (wq_arr_props->is_send) {
+ NIC_WREG32(NIC0_QPC0_TX_WQ_BASE_ADDR_63_32_1, 0);
+ NIC_WREG32(NIC0_QPC0_TX_WQ_BASE_ADDR_31_0_1, 0);
+ NIC_WREG32(NIC0_QPC0_LOG_MAX_TX_WQ_SIZE_1, 0);
+
+ NIC_WREG32(NIC0_TXE0_SQ_BASE_ADDRESS_63_32_1, 0);
+ NIC_WREG32(NIC0_TXE0_SQ_BASE_ADDRESS_31_0_1, 0);
+ NIC_WREG32(NIC0_TXE0_LOG_MAX_WQ_SIZE_1, 0);
+
+ if (wq_arr_props->on_device_mem)
+ gaudi2_cn_config_wqe_asid(cn_port, 0, false);
+ } else {
+ NIC_WREG32(NIC0_QPC0_RX_WQ_BASE_ADDR_63_32_1, 0);
+ NIC_WREG32(NIC0_QPC0_RX_WQ_BASE_ADDR_31_0_1, 0);
+ NIC_WREG32(NIC0_QPC0_LOG_MAX_RX_WQ_SIZE_1, 0);
+
+ NIC_WREG32(NIC0_RXE0_WIN1_WQ_BASE_LO, 0);
+ NIC_WREG32(NIC0_RXE0_WIN1_WQ_BASE_HI, 0);
+ NIC_WREG32(NIC0_RXE0_WIN1_WQ_MISC, 0);
+ }
+
+ if (wq_arr_props->dva_base) {
+ hbl_cn_unreserve_wq_dva(ctx, cn_port, type);
+ } else {
+ rc = hbl_cn_mem_destroy(hdev, wq_arr_props->handle);
+ if (!rc)
+ wq_arr_props->handle = 0;
+ }
+
+ return rc;
+}
+
+static void gaudi2_get_cq_id_range(struct hbl_cn_port *cn_port, u32 *min_id, u32 *max_id)
+{
+ *min_id = NIC_MIN_CQ_ID;
+ *max_id = NIC_MAX_CQ_ID;
+}
+
+static int gaudi2_user_cq_set(struct hbl_cn_user_cq *user_cq,
+ struct hbl_cni_user_cq_set_in_params *in,
+ struct hbl_cni_user_cq_set_out_params *out)
+{
+ u64 mem_handle, pi_handle, regs_handle, pi_device_addr, umr_block_addr;
+ u32 port, id = user_cq->id, offset = id * 4, regs_offset;
+ struct hbl_cn_port *cn_port = user_cq->cn_port;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_ctx *ctx = user_cq->ctx;
+ struct gaudi2_cn_port *gaudi2_port;
+ struct gaudi2_cn_device *gaudi2;
+ struct hbl_cn_mem_data mem_data;
+ int rc;
+
+ gaudi2 = hdev->asic_specific;
+ port = cn_port->port;
+
+ if (!hdev->mmu_bypass) {
+ dev_dbg(hdev->dev,
+ "Allocation of non physical CQ %d dma-mem is not supported, port %d\n", id,
+ port);
+ return -EOPNOTSUPP;
+ }
+
+ gaudi2_port = &gaudi2->cn_ports[port];
+
+ memset(&mem_data, 0, sizeof(mem_data));
+ mem_data.mem_id = HBL_CN_DRV_MEM_HOST_MAP_ONLY;
+ mem_data.in.host_map_data.bus_address = RING_BUF_DMA_ADDRESS(&gaudi2_port->cq_rings[0]) +
+ (id * NIC_TOTAL_CQ_MEM_SIZE);
+ mem_data.in.host_map_data.kernel_address = RING_BUF_ADDRESS(&gaudi2_port->cq_rings[0]) +
+ (id * NIC_TOTAL_CQ_MEM_SIZE);
+ mem_data.size = in->num_of_cqes * CQE_SIZE;
+ rc = hbl_cn_mem_alloc(ctx, &mem_data);
+ if (rc) {
+ dev_dbg(hdev->dev, "user CQ %d buffer allocation failed, rc %d, port %d\n", id, rc,
+ port);
+ return rc;
+ }
+
+ mem_handle = mem_data.handle;
+
+ /* Allocate a producer-index (PI) buffer in host kernel.
+ * HW updates PI when it pushes an entry to a CQ.
+ * User mmaps PI buffer and may poll to read current PI.
+ *
+ * Allocate page size, else we risk exposing kernel data to userspace inadvertently.
+ */
+ memset(&mem_data, 0, sizeof(mem_data));
+ mem_data.mem_id = HBL_CN_DRV_MEM_HOST_DMA_COHERENT;
+ mem_data.size = PAGE_SIZE;
+ rc = hbl_cn_mem_alloc(ctx, &mem_data);
+ if (rc) {
+ dev_dbg(hdev->dev, "user CQ %d PI buffer allocation failed, rc %d, port %d\n", id,
+ rc, port);
+ goto pi_alloc_fail;
+ }
+
+ pi_handle = mem_data.handle;
+ pi_device_addr = mem_data.addr;
+
+ NIC_WREG32(NIC0_RXE0_CQ_LOG_SIZE_0 + offset, ilog2(in->num_of_cqes));
+ NIC_WREG32(NIC0_RXE0_CQ_PI_ADDR_HI_0 + offset, upper_32_bits(pi_device_addr));
+ NIC_WREG32(NIC0_RXE0_CQ_PI_ADDR_LO_0 + offset, lower_32_bits(pi_device_addr));
+
+ /* reset the PI+CI for this CQ */
+ NIC_WREG32(NIC0_RXE0_CQ_WRITE_INDEX_0 + offset, 0);
+ NIC_WREG32(NIC0_RXE0_CQ_PRODUCER_INDEX_0 + offset, 0);
+ NIC_WREG32(NIC0_RXE0_CQ_CONSUMER_INDEX_0 + offset, 0);
+ NIC_WREG32(NIC0_RXE0_CQ_CFG_0 + offset, NIC0_RXE0_CQ_CFG_WRITE_PI_EN_MASK |
+ NIC0_RXE0_CQ_CFG_ENABLE_MASK);
+
+ /* CQs 0 and 1 are secured and hence reserved so skip them for block addr calculation */
+ __gaudi2_cn_get_db_fifo_umr(cn_port, (id >> 1) - 1, id, &umr_block_addr, ®s_offset);
+
+ /* add CQ offset */
+ regs_offset += NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_NUMBER -
+ NIC0_UMR0_0_UNSECURE_DOORBELL1_UNSECURE_DB_FIRST32;
+
+ /* get mmap handle for UMR block */
+ rc = hbl_cn_get_hw_block_handle(hdev, umr_block_addr, ®s_handle);
+ if (rc) {
+ dev_dbg(hdev->dev, "Failed to get user CQ %d UMR block, rc %d, port %d\n", id, rc,
+ port);
+ goto umr_get_fail;
+ }
+
+ rc = hbl_cn_eq_dispatcher_register_cq(cn_port, ctx->asid, id);
+ if (rc) {
+ dev_err(hdev->dev, "failed to register CQ %d, rc %d, port %d\n", id, rc, port);
+ goto eq_register_fail;
+ }
+
+ out->mem_handle = mem_handle;
+ out->regs_handle = regs_handle;
+ out->regs_offset = regs_offset;
+ out->pi_handle = pi_handle;
+
+ user_cq->mem_handle = mem_handle;
+ user_cq->pi_handle = pi_handle;
+
+ return 0;
+
+eq_register_fail:
+umr_get_fail:
+ hbl_cn_mem_destroy(hdev, pi_handle);
+pi_alloc_fail:
+ hbl_cn_mem_destroy(hdev, mem_handle);
+
+ return rc;
+}
+
+static int gaudi2_user_cq_unset(struct hbl_cn_user_cq *user_cq)
+{
+ struct hbl_cn_port *cn_port = user_cq->cn_port;
+ u32 port, id = user_cq->id, offset = id * 4;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+
+ port = cn_port->port;
+
+ hbl_cn_eq_dispatcher_unregister_cq(cn_port, id);
+
+ NIC_RMWREG32(NIC0_RXE0_CQ_CFG_0 + offset, 0, NIC0_RXE0_CQ_CFG_WRITE_PI_EN_MASK);
+ /* flush the new cfg */
+ NIC_RREG32(NIC0_RXE0_CQ_CFG_0 + offset);
+
+ NIC_WREG32(NIC0_RXE0_CQ_PI_ADDR_HI_0 + offset, 0);
+ NIC_WREG32(NIC0_RXE0_CQ_PI_ADDR_LO_0 + offset, 0);
+
+ /* only unmaps as the HW might still access this memory */
+ hbl_cn_mem_destroy(hdev, user_cq->mem_handle);
+ /* unmaps and frees as we disabled the PI flag and the HW won't access this memory */
+ hbl_cn_mem_destroy(hdev, user_cq->pi_handle);
+
+ return 0;
+}
+
+static void gaudi2_user_cq_set_overrun(struct hbl_cn_user_cq *user_cq, bool set_overrun)
+{
+ struct hbl_cn_port *cn_port = user_cq->cn_port;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port, offset = user_cq->id * 4;
+ bool update_cq_cfg = false;
+
+ port = cn_port->port;
+
+ mutex_lock(&user_cq->overrun_lock);
+
+ /* only the first QP should enable CQ overrun, and the last QP should disable overrun */
+ if (set_overrun && user_cq->qp_set_overrun_cnt == 0) {
+ user_cq->qp_set_overrun_cnt++;
+ update_cq_cfg = true;
+ } else if (!set_overrun && user_cq->qp_set_overrun_cnt == 1) {
+ user_cq->qp_set_overrun_cnt--;
+ update_cq_cfg = true;
+ }
+
+ if (update_cq_cfg)
+ NIC_RMWREG32(NIC0_RXE0_CQ_CFG_0 + offset, set_overrun,
+ NIC0_RXE0_CQ_CFG_OVERRUN_EN_MASK);
+
+ mutex_unlock(&user_cq->overrun_lock);
+}
+
+static void gaudi2_user_cq_destroy(struct hbl_cn_user_cq *user_cq)
+{
+ struct hbl_cn_port *cn_port = user_cq->cn_port;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port, offset = user_cq->id * 4;
+
+ port = cn_port->port;
+
+ NIC_WREG32(NIC0_RXE0_CQ_CFG_0 + offset, 0);
+ NIC_WREG32(NIC0_RXE0_CQ_LOG_SIZE_0 + offset, 0);
+}
+
+static void gaudi2_set_advanced_op_mask(struct hbl_cn_device *hdev, bool advanced)
+{
+ u64 advanced_op_mask = BIT(HBL_CNI_OP_USER_CCQ_SET) | BIT(HBL_CNI_OP_USER_CCQ_UNSET);
+
+ if (advanced)
+ hdev->ctrl_op_mask |= advanced_op_mask;
+ else
+ hdev->ctrl_op_mask &= ~advanced_op_mask;
+}
+
+static int gaudi2_user_set_app_params(struct hbl_cn_device *hdev,
+ struct hbl_cni_set_user_app_params_in *in,
+ bool *modify_wqe_checkers, struct hbl_cn_ctx *ctx)
+{
+ u32 port = in->port, bp_offs_fw, bp_offs_qman, encap_id, wtd_config;
+ struct gaudi2_cn_port *gaudi2_port;
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+
+ if (cn_port->set_app_params) {
+ dev_dbg(hdev->dev, "App params were already set, port %d\n", port);
+ return -EPERM;
+ }
+
+ gaudi2_port = cn_port->cn_specific;
+ gaudi2_port->advanced = in->advanced;
+ gaudi2_port->adaptive_timeout_en = in->adaptive_timeout_en;
+
+ /* Enable\disable advanced operations */
+ gaudi2_set_advanced_op_mask(hdev, (bool)gaudi2_port->advanced);
+
+ bp_offs_fw = in->bp_offs[HBL_CNI_USER_BP_OFFS_FW];
+ bp_offs_qman = in->bp_offs[HBL_CNI_USER_BP_OFFS_QMAN];
+
+ /* Validate the parameters before performing any register changes */
+ if ((bp_offs_fw) || (bp_offs_qman)) {
+ if (!gaudi2_port->advanced) {
+ dev_dbg(hdev->dev,
+ "Port %u: advanced flag is disabled - can't set back-pressue\n",
+ port);
+ return -EINVAL;
+ }
+
+ if ((bp_offs_fw) && (bp_offs_fw & ~WQ_BP_ADDR_VAL_MASK)) {
+ dev_dbg(hdev->dev, "Port %u: invalid ARC BP offset 0x%x\n", port,
+ bp_offs_fw);
+ return -EINVAL;
+ }
+
+ if ((bp_offs_qman) && (bp_offs_qman & ~WQ_BP_ADDR_VAL_MASK)) {
+ dev_dbg(hdev->dev, "Port %u: invalid QMAN BP offset 0x%x\n", port,
+ bp_offs_qman);
+ return -EINVAL;
+ }
+
+ gaudi2_port->min_qp_size = U32_MAX;
+
+ /* Enable BP for DB */
+ wtd_config = NIC_RREG32(NIC0_QPC0_WTD_CONFIG) |
+ NIC0_QPC0_WTD_CONFIG_WQ_BP_DB_ACCOUNTED_MASK;
+
+ if (bp_offs_fw) {
+ /* Enable WTD BP to ARC */
+ wtd_config |= NIC0_QPC0_WTD_CONFIG_WQ_BP_2ARC_EN_MASK;
+
+ /* Set the offset in the ARC memory to signal the BP*/
+ NIC_WREG32(NIC0_QPC0_WQ_BP_2ARC_ADDR, bp_offs_fw);
+ }
+
+ if (bp_offs_qman) {
+ /* Enable WTD BP to QMAN */
+ wtd_config |= NIC0_QPC0_WTD_CONFIG_WQ_BP_2QMAN_EN_MASK;
+
+ /* Set the offset in the QMAN memory to signal the BP*/
+ NIC_WREG32(NIC0_QPC0_WQ_BP_2QMAN_ADDR, bp_offs_qman);
+ }
+
+ NIC_WREG32(NIC0_QPC0_WTD_CONFIG, wtd_config);
+
+ *modify_wqe_checkers = true;
+ cn_port->bp_enable = true;
+ } else {
+ cn_port->bp_enable = false;
+ *modify_wqe_checkers = false;
+ }
+
+ if (gaudi2_port->adaptive_timeout_en) {
+ u8 max_retry_timeout = GAUDI2_NIC_MAX_TIMEOUT_RETRIES / NIC_ADAPTIVE_TIMEOUT_RANGE;
+
+ NIC_WREG32(NIC0_QPC0_RETRY_COUNT_MAX,
+ (max_retry_timeout << NIC0_QPC0_RETRY_COUNT_MAX_TIMEOUT_SHIFT) |
+ (max_retry_timeout << NIC0_QPC0_RETRY_COUNT_MAX_SEQUENCE_ERROR_SHIFT));
+ }
+
+ /* configure port's encapsulation for source ip-address automatically */
+ if (cn_port->eth_enable)
+ gaudi2_default_encap_set(cn_port, &encap_id, 0);
+
+ return 0;
+}
+
+static void gaudi2_user_get_app_params(struct hbl_cn_device *hdev,
+ struct hbl_cni_get_user_app_params_in *in,
+ struct hbl_cni_get_user_app_params_out *out)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ struct hbl_cn_port *cn_port;
+
+ cn_port = gaudi2->cn_ports[in->port].cn_port;
+ out->max_num_of_qps = NIC_MAX_QP_NUM;
+ /* always include the Ethernet QP */
+ out->num_allocated_qps = 1 + atomic_read(&cn_port->num_of_allocated_qps);
+ out->max_allocated_qp_idx = hbl_cn_get_max_qp_id(cn_port);
+ out->max_cq_size = CQE_SIZE * NIC_CQ_MAX_ENTRIES;
+
+ /* Two CQs are reserved - one for the Ethernet and one for the driver CQ. We could use the
+ * driver CQ as a user CQ but in each UMR there are 2 CQs and since CQ idx 0 is reserved for
+ * Ethernet, also CQ idx 1 is unavailable.
+ */
+ out->max_num_of_cqs = GAUDI2_NIC_MAX_CQS_NUM - NIC_CQS_NUM;
+ out->max_num_of_db_fifos = GAUDI2_MAX_DB_FIFO_ID - GAUDI2_MIN_DB_FIFO_ID + 1;
+ out->max_num_of_encaps = GAUDI2_MAX_ENCAP_ID - GAUDI2_MIN_ENCAP_ID + 1;
+}
+
+static void gaudi2_cn_stop_traffic_macro(struct hbl_cn_macro *cn_macro)
+{
+ struct hbl_cn_device *hdev = cn_macro->hdev;
+ u32 port = cn_macro->idx << 1; /* the index of the first port in the macro */
+ int i;
+
+ for (i = 0; i < 8; i++)
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_DROP_THRESHOLD_0 + i * 4, 0);
+
+ usleep_range(1000, 2000);
+
+ NIC_MACRO_RMWREG32(NIC0_TMR_TMR_CACHES_CFG, 1,
+ NIC0_TMR_TMR_CACHES_CFG_LIST_CACHE_STOP_MASK);
+ NIC_MACRO_RMWREG32(NIC0_TMR_TMR_CACHES_CFG, 1,
+ NIC0_TMR_TMR_CACHES_CFG_FREE_LIST_CACHE_STOP_MASK);
+ NIC_MACRO_RMWREG32(NIC0_TMR_TMR_CACHES_CFG, 1,
+ NIC0_TMR_TMR_CACHES_CFG_STATE_CACHE_STOP_MASK);
+
+ usleep_range(1000, 2000);
+
+ /* Flush all the writes */
+ NIC_MACRO_RREG32(NIC0_TMR_TMR_CACHES_CFG);
+}
+
+static void gaudi2_cn_stop_traffic_port(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+
+ NIC_RMWREG32(NIC0_QPC0_REQ_STATIC_CONFIG, 1,
+ NIC0_QPC0_REQ_STATIC_CONFIG_CACHE_STOP_MASK);
+ NIC_RMWREG32(NIC0_QPC0_RES_STATIC_CONFIG, 1,
+ NIC0_QPC0_RES_STATIC_CONFIG_CACHE_STOP_MASK);
+ NIC_RMWREG32(NIC0_TXS0_CACHE_CFG, 1,
+ NIC0_TXS0_CACHE_CFG_LIST_CACHE_STOP_MASK);
+ NIC_RMWREG32(NIC0_TXS0_CACHE_CFG, 1,
+ NIC0_TXS0_CACHE_CFG_FREE_LIST_CACHE_STOP_MASK);
+
+ /* Flush all the writes */
+ NIC_MACRO_RREG32(NIC0_TXS0_CACHE_CFG);
+}
+
+static bool gaudi2_cn_is_macro_enabled(struct hbl_cn_macro *cn_macro)
+{
+ struct hbl_cn_device *hdev = cn_macro->hdev;
+ u32 port1, port2;
+
+ port1 = cn_macro->idx << 1; /* the index of the first port in the macro */
+ port2 = port1 + 1;
+
+ return (hdev->ports_mask & BIT(port1)) || (hdev->ports_mask & BIT(port2));
+}
+
+/* FW must be aligned with any changes done to this function */
+static void gaudi2_cn_stop_traffic(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_macro *cn_macro;
+ int i;
+
+ for (i = 0; i < hdev->cn_props.num_of_macros; i++) {
+ cn_macro = &hdev->cn_macros[i];
+
+ if (!gaudi2_cn_is_macro_enabled(cn_macro))
+ continue;
+
+ gaudi2_cn_stop_traffic_macro(cn_macro);
+ }
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ gaudi2_cn_stop_traffic_port(&hdev->cn_ports[i]);
+ }
+}
+
+static void gaudi2_cn_set_speed(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_port *cn_port;
+ int i;
+
+ for (i = 0; i < NIC_NUMBER_OF_PORTS; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+ cn_port->speed = hdev->phy_set_nrz ? SPEED_25000 : SPEED_100000;
+ }
+}
+
+static void gaudi2_cn_config_hw_mac(struct hbl_cn_macro *cn_macro)
+{
+ struct hbl_cn_device *hdev = cn_macro->hdev;
+ struct gaudi2_cn_device *gaudi2;
+ u32 port, speed;
+
+ gaudi2 = hdev->asic_specific;
+ /* the index of the first port in the macro */
+ port = cn_macro->idx << 1;
+ speed = hdev->cn_ports[port].speed;
+
+ switch (speed) {
+ case SPEED_25000:
+ /* AC_SD_CFG: sd_n2 = 0, sd_8x = 0 */
+ NIC_MACRO_WREG32(PRT0_MAC_CORE_MAC_SD_CFG, 0xF0FF00);
+
+ /* KP_MODE = 0, FEC91_EN = 1, FEC91_1LANE = 1 */
+ NIC_MACRO_WREG32(PRT0_MAC_CORE_MAC_FEC91_CFG, 0x60F);
+ NIC_MACRO_WREG32(PRT0_MAC_CORE_MAC_PCS_CFG, 0x0);
+ NIC_MACRO_WREG32(PRT0_MAC_CORE_MAC_FC_FEC_CFG, 0x0);
+ break;
+ case SPEED_50000:
+ NIC_MACRO_WREG32(PRT0_MAC_CORE_MAC_SD_CFG, 0xF0FFF0);
+ NIC_MACRO_WREG32(PRT0_MAC_CORE_MAC_FEC91_CFG, 0xFF);
+ NIC_MACRO_WREG32(PRT0_MAC_CORE_MAC_PCS_CFG, 0x0);
+
+ if (gaudi2->mac_rs_fec_ctrl_support) {
+ NIC_MACRO_WREG32(NIC0_MAC_RS_FEC_RSFEC_CONTROL, 0x400);
+ NIC_MACRO_WREG32(NIC0_MAC_RS_FEC_RSFEC1_CONTROL, 0x400);
+ NIC_MACRO_WREG32(NIC0_MAC_RS_FEC_RSFEC2_CONTROL, 0x400);
+ NIC_MACRO_WREG32(NIC0_MAC_RS_FEC_RSFEC3_CONTROL, 0x400);
+ }
+ break;
+ case SPEED_100000:
+ NIC_MACRO_WREG32(PRT0_MAC_CORE_MAC_FEC91_CFG, 0xFF);
+ break;
+ default:
+ dev_err(hdev->dev, "unknown speed %dMb/s, cannot set MAC\n", speed);
+ }
+}
+
+static void gaudi2_cn_config_hw_rxb(struct hbl_cn_macro *cn_macro)
+{
+ u32 dynamic_credits, static_credits, drop_th, small_pkt_drop_th, xoff_th, xon_th, val;
+ struct hbl_cn_device *hdev = cn_macro->hdev;
+ u32 port = cn_macro->idx << 1; /* the index of the first port in the macro */
+ int i;
+
+ /* Set iCRC calculation & verification with reversed bytes */
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_ICRC_CFG, 0x2);
+
+ /* Assuming 1 effective priority per port divided between 2 physical ports. */
+ static_credits = RXB_NUM_STATIC_CREDITS;
+ dynamic_credits = 0;
+ drop_th = static_credits - RXB_DROP_TH_DEPTH;
+ xoff_th = static_credits - RXB_XOFF_TH_DEPTH;
+ xon_th = xoff_th - RXB_XON_TH_DEPTH;
+ small_pkt_drop_th = static_credits - RXB_DROP_SMALL_TH_DEPTH;
+
+ /* Dynamic credits (global) */
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_MAX_DYNAMIC, dynamic_credits);
+
+ val = static_credits | (static_credits << 13);
+ for (i = 0; i < 8; i++)
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_MAX_STATIC_CREDITS_0 + i * 4, val);
+
+ /* Drop threshold (per port/prio) */
+ val = drop_th | (drop_th << 13);
+ for (i = 0; i < 8; i++)
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_DROP_THRESHOLD_0 + i * 4, val);
+
+ /* Drop threshold for small packets (per port/prio) */
+ val = small_pkt_drop_th | (small_pkt_drop_th << 13);
+ for (i = 0; i < 8; i++)
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_DROP_SMALL_THRESHOLD_0 + i * 4, val);
+
+ /* XOFF threshold (per port/prio) */
+ val = xoff_th | (xoff_th << 13);
+ for (i = 0; i < 8; i++)
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_XOFF_THRESHOLD_0 + i * 4, val);
+
+ /* XON threshold (per port/prio) */
+ val = xon_th | (xon_th << 13);
+ for (i = 0; i < 8; i++)
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_XON_THRESHOLD_0 + i * 4, val);
+
+ /* All DSCP values should be mapped to PRIO 0 */
+ for (i = 0; i < 8; i++)
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_DSCP2PRIO_0 + i * 4, 0);
+
+ /* set priority 0 as default priority to all ports and set the RXB to take the priority
+ * according to the incoming port.
+ */
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_PORT_DEFAULT_PRIO, 0x0);
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_PORT_TRUST_LEVEL, 0);
+
+ /* spread PAUSE on all prios (i.e. global pause) */
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_MAC_PFC_MODE, 0x2);
+}
+
+static void gaudi2_cn_config_hw_txb(struct hbl_cn_macro *cn_macro)
+{
+ struct hbl_cn_device *hdev = cn_macro->hdev;
+ u32 port = cn_macro->idx << 1; /* the index of the first port in the macro */
+ u32 speed;
+
+ speed = hdev->cn_ports[port].speed;
+
+ /* Set iCRC calculation & generation with reversed bytes */
+ NIC_MACRO_WREG32(NIC0_TXB_ICRC_CFG, 0x2);
+
+ NIC_MACRO_WREG32(NIC0_TXB_GLOBAL_PAUSE, 0x0);
+
+ switch (speed) {
+ case SPEED_25000:
+ fallthrough;
+ case SPEED_50000:
+ NIC_MACRO_WREG32(NIC0_TXB_TDM_PORT_ARB_MASK, 0x7BDE);
+ break;
+ case SPEED_100000:
+ NIC_MACRO_WREG32(NIC0_TXB_TDM_PORT_ARB_MASK, 0xBBEE);
+ break;
+ default:
+ dev_err(hdev->dev, "unknown port %d speed %dMb/s, cannot set TDM mask\n", port,
+ speed);
+ }
+}
+
+static int gaudi2_cn_config_hw_tmr(struct hbl_cn_macro *cn_macro)
+{
+ struct cpucp_cn_init_hw_mem_packet pkt;
+ struct hbl_cn_properties *cn_prop;
+ u64 tmr_addr, nic_tmr_timeout_us;
+ struct hbl_cn_device *hdev;
+ bool use_cpucp;
+ int i, rc;
+ u32 port;
+
+ port = cn_macro->idx << 1; /* the index of the first port in the macro */
+ hdev = cn_macro->hdev;
+ cn_prop = &hdev->cn_props;
+
+ tmr_addr = cn_prop->tmr_base_addr + cn_macro->idx * cn_prop->tmr_base_size;
+
+ use_cpucp = !!(hdev->fw_app_cpu_boot_dev_sts0 & CPU_BOOT_DEV_STS0_NIC_MEM_CLEAR_EN);
+ if (use_cpucp) {
+ memset(&pkt, 0, sizeof(pkt));
+ pkt.cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_NIC_INIT_TMR_MEM <<
+ CPUCP_PKT_CTL_OPCODE_SHIFT);
+ pkt.cpucp_pkt.macro_index = cpu_to_le32(cn_macro->idx);
+ pkt.mem_base_addr = cpu_to_le64(tmr_addr + TMR_FREE_OFFS);
+ pkt.num_entries = cpu_to_le16(TMR_FREE_NUM_ENTRIES);
+ pkt.entry_size = cpu_to_le16(TMR_ENT_SIZE);
+ pkt.granularity = cpu_to_le16(TMR_GRANULARITY);
+
+ rc = gaudi2_cn_send_cpu_message(hdev, (u32 *)&pkt, sizeof(pkt), 0, NULL);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to handle CPU-CP pkt %u, error %d\n",
+ CPUCP_PACKET_NIC_INIT_TMR_MEM, rc);
+ return rc;
+ }
+ } else {
+ /* Timer free list */
+ for (i = 0; i < TMR_FREE_NUM_ENTRIES; i++) {
+ hbl_cn_dram_writel(hdev, TMR_GRANULARITY + i,
+ tmr_addr + TMR_FREE_OFFS + i * TMR_ENT_SIZE);
+
+ if ((i % NIC_MAX_COMBINED_WRITES) == 0)
+ hbl_cn_dram_readl(hdev,
+ tmr_addr + TMR_FREE_OFFS + i * TMR_ENT_SIZE);
+ }
+
+ /* Perform read to flush the writes */
+ hbl_cn_dram_readl(hdev, tmr_addr);
+ }
+
+ WARN_ON_CACHE_UNALIGNED(tmr_addr + TMR_FIFO_OFFS);
+ WARN_ON_CACHE_UNALIGNED(tmr_addr + TMR_FSM0_OFFS);
+
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_BASE_ADDRESS_63_32,
+ upper_32_bits(tmr_addr + TMR_FIFO_OFFS));
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_BASE_ADDRESS_31_7,
+ lower_32_bits(tmr_addr + TMR_FIFO_OFFS) >> 7);
+
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_BASE_ADDRESS_FREE_LIST_63_32,
+ upper_32_bits(tmr_addr + TMR_FREE_OFFS));
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_BASE_ADDRESS_FREE_LIST_31_0,
+ lower_32_bits(tmr_addr + TMR_FREE_OFFS));
+
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_CACHE_BASE_ADDR_63_32,
+ upper_32_bits(tmr_addr + TMR_FSM0_OFFS));
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_CACHE_BASE_ADDR_31_7,
+ lower_32_bits(tmr_addr + TMR_FSM0_OFFS) >> 7);
+
+ /* configure MMU-BP for TIMERS */
+ NIC_MACRO_WREG32(NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_WR_OVRD_LO, 0xFFFFFBFF);
+ NIC_MACRO_WREG32(NIC0_TMR_AXUSER_TMR_FREE_LIST_HB_RD_OVRD_LO, 0xFFFFFBFF);
+
+ NIC_MACRO_WREG32(NIC0_TMR_AXUSER_TMR_FIFO_HB_WR_OVRD_LO, 0xFFFFFBFF);
+ NIC_MACRO_WREG32(NIC0_TMR_AXUSER_TMR_FIFO_HB_RD_OVRD_LO, 0xFFFFFBFF);
+
+ NIC_MACRO_WREG32(NIC0_TMR_AXUSER_TMR_FSM_HB_WR_OVRD_LO, 0xFFFFFBFF);
+ NIC_MACRO_WREG32(NIC0_TMR_AXUSER_TMR_FSM_HB_RD_OVRD_LO, 0xFFFFFBFF);
+ /* Perform read to flush the writes */
+ NIC_MACRO_RREG32(NIC0_TMR_AXUSER_TMR_FSM_HB_RD_OVRD_LO);
+
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_31_0, 0);
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_63_32, 0);
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_95_64, 0);
+
+ for (i = 0; i < TMR_GRANULARITY; i++) {
+ /* Set the amount of ticks for timeout. */
+ nic_tmr_timeout_us = ((i == 0) || (i >= 32)) ?
+ GENMASK_ULL(46, 0) :
+ (u64)(hdev->pldm ? NIC_TMR_TIMEOUT_PLDM_US :
+ (1ULL << (i + 2)));
+
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_191_160,
+ lower_32_bits(nic_tmr_timeout_us));
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_216_192,
+ upper_32_bits(nic_tmr_timeout_us));
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_127_96, i);
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_SCHEDQ_UPDATE_DESC_159_128, i);
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_SCHEDQ_UPDATE_FIFO, i);
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_SCHEDQ_UPDATE_EN, 1);
+ }
+
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_SCAN_TIMER_COMP_31_0, 10);
+
+ /* Set the number of clock's cycles for a single tick in order to have 1 usec per tick.
+ * i.e.: 1/frequency_in_MHz * num_of_clk_cycles = 1 usec
+ */
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_TICK_WRAP, cn_prop->clk);
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_LIST_MASK,
+ ~(0xFFFFFFFF << (ilog2(TMR_FREE_NUM_ENTRIES) - 5)));
+
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_PRODUCER_UPDATE, TMR_FREE_NUM_ENTRIES);
+ /* Latch the TMR value */
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_PRODUCER_UPDATE_EN, 1);
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_PRODUCER_UPDATE_EN, 0);
+
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_LIST_MEM_READ_MASK, 0);
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_PUSH_LOCK_EN, 1);
+ NIC_MACRO_WREG32(NIC0_TMR_TMR_TIMER_EN, 1);
+ NIC_MACRO_WREG32(NIC0_TMR_FREE_LIST_PUSH_MASK_EN, 0);
+
+ /* Perform read from the device to flush all configurations */
+ NIC_MACRO_RREG32(NIC0_TMR_TMR_TIMER_EN);
+
+ return 0;
+}
+
+static void gaudi2_cn_enable_gic_macro_interrupts(struct hbl_cn_macro *cn_macro)
+{
+ struct hbl_cn_device *hdev;
+ u32 port;
+
+ port = cn_macro->idx << 1; /* the index of the first port in the macro */
+ hdev = cn_macro->hdev;
+
+ /* enable TMR block interrupts */
+ NIC_MACRO_WREG32(NIC0_TMR_INTERRUPT_MASK, 0x0);
+
+ /* enable RXB_CORE block interrupts */
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_SEI_INTR_MASK, 0x0);
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_SPI_INTR_MASK, 0x0);
+}
+
+static void gaudi2_cn_disable_gic_macro_interrupts(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_macro *cn_macro;
+ u32 port;
+ int i;
+
+ for (i = 0; i < NIC_NUMBER_OF_MACROS; i++) {
+ cn_macro = &hdev->cn_macros[i];
+ port = cn_macro->idx << 1; /* the index of the first port in the macro */
+
+ /* It's not allowed to configure a macro that both of its ports are not enabled */
+ if (!gaudi2_cn_is_macro_enabled(cn_macro))
+ continue;
+
+ /* disable TMR block interrupts */
+ NIC_MACRO_WREG32(NIC0_TMR_INTERRUPT_MASK, 0xF);
+
+ /* disable RXB_CORE block interrupts */
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_SEI_INTR_MASK, 0x3);
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_SPI_INTR_MASK, 0x3F);
+ }
+}
+
+static int gaudi2_cn_hw_macro_config(struct hbl_cn_macro *cn_macro)
+{
+ int rc;
+
+ /* the following registers are shared between each pair of ports */
+
+ /* MAC Configuration */
+ gaudi2_cn_config_hw_mac(cn_macro);
+
+ /* RXB Configuration */
+ gaudi2_cn_config_hw_rxb(cn_macro);
+
+ /* TXB Configuration */
+ gaudi2_cn_config_hw_txb(cn_macro);
+
+ /* TMR Configuration */
+ rc = gaudi2_cn_config_hw_tmr(cn_macro);
+ if (rc)
+ return rc;
+
+ /* Enable GIC macro interrupts - required only if running on PLDM */
+ if (cn_macro->hdev->pldm)
+ gaudi2_cn_enable_gic_macro_interrupts(cn_macro);
+
+ return rc;
+}
+
+static int gaudi2_cn_macros_hw_config(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_macro *cn_macro;
+ int i, rc = 0;
+
+ for (i = 0; i < NIC_NUMBER_OF_MACROS; i++) {
+ cn_macro = &hdev->cn_macros[i];
+
+ if (!gaudi2_cn_is_macro_enabled(cn_macro))
+ continue;
+
+ rc = gaudi2_cn_hw_macro_config(cn_macro);
+ if (rc)
+ return rc;
+ }
+
+ return rc;
+}
+
+static int gaudi2_cn_core_init(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_properties *cn_prop = &hdev->cn_props;
+ u64 nic_dram_alloc_size;
+ int rc;
+
+ nic_dram_alloc_size = cn_prop->nic_drv_end_addr - cn_prop->nic_drv_base_addr;
+ if (nic_dram_alloc_size > cn_prop->nic_drv_size) {
+ dev_err(hdev->dev, "DRAM allocation for CN (%lluMB) shouldn't exceed %lluMB\n",
+ div_u64(nic_dram_alloc_size, SZ_1M),
+ div_u64(cn_prop->nic_drv_size, SZ_1M));
+ return -ENOMEM;
+ }
+
+ rc = gaudi2_cn_phy_init(hdev);
+ if (rc)
+ return rc;
+
+ /* This function must be called before configuring the macros */
+ gaudi2_cn_set_speed(hdev);
+
+ rc = gaudi2_cn_macros_hw_config(hdev);
+ if (rc)
+ return rc;
+
+ return gaudi2_cn_eq_init(hdev);
+}
+
+static void gaudi2_cn_core_fini(struct hbl_cn_device *hdev)
+{
+ gaudi2_cn_eq_fini(hdev);
+
+ /* Disable GIC macro interrupts - required only if running on PLDM */
+ if (hdev->pldm)
+ gaudi2_cn_disable_gic_macro_interrupts(hdev);
+
+ gaudi2_cn_stop_traffic(hdev);
+}
+
+static int gaudi2_cn_ctx_dispatcher_init(struct hbl_cn_device *hdev, u32 asid)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_cn_port *gaudi2_port;
+ struct hbl_cn_port *cn_port;
+ int i, j, rc = 0;
+ u32 port;
+
+ for (i = 0; i < NIC_NUMBER_OF_PORTS; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ gaudi2_port = &gaudi2->cn_ports[i];
+ cn_port = gaudi2_port->cn_port;
+ port = cn_port->port;
+
+ rc = hbl_cn_eq_dispatcher_associate_dq(gaudi2_port->cn_port, asid);
+ if (rc) {
+ dev_err(hdev->dev,
+ "failed to associate ASID %d with port %d event dispatcher (err %d)\n",
+ asid, port, rc);
+ goto associate_error;
+ }
+ }
+
+ return 0;
+
+associate_error:
+ /* dissociate the associated dqs */
+ for (j = 0; j < i; j++) {
+ gaudi2_port = &gaudi2->cn_ports[j];
+ hbl_cn_eq_dispatcher_dissociate_dq(gaudi2_port->cn_port, asid);
+ }
+
+ return rc;
+}
+
+static void gaudi2_cn_ctx_dispatcher_fini(struct hbl_cn_device *hdev, u32 asid)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_cn_port *gaudi2_port;
+ int i;
+
+ for (i = 0; i < NIC_NUMBER_OF_PORTS; i++)
+ if (hdev->ports_mask & BIT(i)) {
+ gaudi2_port = &gaudi2->cn_ports[i];
+ hbl_cn_eq_dispatcher_dissociate_dq(gaudi2_port->cn_port, asid);
+ }
+}
+
+static int gaudi2_cn_kernel_ctx_init(struct hbl_cn_device *hdev, u32 asid)
+{
+ return gaudi2_cn_ctx_dispatcher_init(hdev, asid);
+}
+
+static void gaudi2_cn_kernel_ctx_fini(struct hbl_cn_device *hdev, u32 asid)
+{
+ gaudi2_cn_ctx_dispatcher_fini(hdev, asid);
+}
+
+static int gaudi2_cn_ctx_init(struct hbl_cn_ctx *ctx)
+{
+ return gaudi2_cn_ctx_dispatcher_init(ctx->hdev, ctx->asid);
+}
+
+static void gaudi2_cn_ctx_fini(struct hbl_cn_ctx *ctx)
+{
+ gaudi2_cn_ctx_dispatcher_fini(ctx->hdev, ctx->asid);
+}
+
+static void gaudi2_cn_configure_cq(struct hbl_aux_dev *aux_dev, u32 port, u16 coalesce_usec,
+ bool enable)
+{
+ struct hbl_cn_device *hdev = container_of(aux_dev, struct hbl_cn_device, en_aux_dev);
+ struct hbl_cn_properties *cn_prop = &hdev->cn_props;
+ u32 arm_timeout;
+
+ /* Calc timeout in ticks.
+ * result/value of 0 is interpreted as ASAP but since a value of Zero is an invalid value
+ * we modify it to 1.
+ */
+ arm_timeout = coalesce_usec ? cn_prop->clk * coalesce_usec : 1;
+
+ /* disable the current timer before configuring the new time */
+ NIC_RMWREG32(NIC0_RXE0_CQ_ARM_TIMEOUT_EN, 0, BIT(NIC_CQ_RAW_IDX));
+ NIC_RREG32(NIC0_RXE0_CQ_ARM_TIMEOUT_EN);
+
+ /* if enable - configure the new timer and enable it */
+ if (enable) {
+ NIC_WREG32(NIC0_RXE0_CQ_ARM_TIMEOUT, arm_timeout);
+ NIC_RMWREG32(NIC0_RXE0_CQ_ARM_TIMEOUT_EN, 1, BIT(NIC_CQ_RAW_IDX));
+ }
+}
+
+static void gaudi2_cn_arm_cq(struct hbl_aux_dev *aux_dev, u32 port, u32 index)
+{
+ struct hbl_cn_device *hdev = container_of(aux_dev, struct hbl_cn_device, en_aux_dev);
+
+ NIC_WREG32(NIC0_QPC0_ARM_CQ_NUM, NIC_CQ_RAW_IDX);
+ NIC_WREG32(NIC0_QPC0_ARM_CQ_INDEX, index);
+}
+
+static void gaudi2_cn_write_rx_ci(struct hbl_aux_dev *aux_dev, u32 port, u32 ci)
+{
+ struct hbl_cn_device *hdev = container_of(aux_dev, struct hbl_cn_device, en_aux_dev);
+
+ NIC_WREG32(NIC0_QPC0_SECURED_CQ_NUMBER, NIC_CQ_RAW_IDX);
+ NIC_WREG32(NIC0_QPC0_SECURED_CQ_CONSUMER_INDEX, ci);
+}
+
+static void gaudi2_cn_get_pfc_cnts(struct hbl_aux_dev *aux_dev, u32 port, int pfc_prio,
+ u64 *indications, u64 *requests)
+{
+ struct hbl_cn_device *hdev = container_of(aux_dev, struct hbl_cn_device, en_aux_dev);
+ u64 reg_addr, lo_part, hi_part;
+
+ reg_addr = (port & 1) ? NIC0_MAC_GLOB_STAT_RX2_ACBFCPAUSEFRAMESRECEIVED0_2 :
+ NIC0_MAC_GLOB_STAT_RX0_ACBFCPAUSEFRAMESRECEIVED0;
+
+ reg_addr += (4 * pfc_prio);
+
+ lo_part = NIC_MACRO_RREG32(reg_addr);
+ hi_part = NIC_MACRO_RREG32(NIC0_MAC_GLOB_STAT_CONTROL_REG_DATA_HI);
+ *indications = lo_part | (hi_part << 32);
+
+ reg_addr = (port & 1) ? NIC0_MAC_GLOB_STAT_TX2_ACBFCPAUSEFRAMESTRANSMITTED0_2 :
+ NIC0_MAC_GLOB_STAT_TX0_ACBFCPAUSEFRAMESTRANSMITTED0;
+
+ reg_addr += (4 * pfc_prio);
+
+ lo_part = NIC_MACRO_RREG32(reg_addr);
+ hi_part = NIC_MACRO_RREG32(NIC0_MAC_GLOB_STAT_CONTROL_REG_DATA_HI);
+ *requests = lo_part | (hi_part << 32);
+}
+
+static int gaudi2_cn_ring_tx_doorbell(struct hbl_aux_dev *aux_dev, u32 port, u32 pi,
+ bool *full_after_tx)
+{
+ struct hbl_cn_device *hdev = container_of(aux_dev, struct hbl_cn_device, en_aux_dev);
+ u32 db_fifo_ci = 0, db_fifo_pi = 0, space_left_in_db_fifo = 0;
+ struct gaudi2_cn_port *gaudi2_port;
+ struct hbl_cn_port *cn_port;
+
+ cn_port = &hdev->cn_ports[port];
+ gaudi2_port = cn_port->cn_specific;
+
+ db_fifo_ci = *((u32 *)RING_CI_ADDRESS(&gaudi2_port->fifo_ring));
+ db_fifo_pi = gaudi2_port->db_fifo_pi;
+
+ space_left_in_db_fifo = CIRC_SPACE(db_fifo_pi, db_fifo_ci, NIC_FIFO_DB_SIZE);
+
+ if (!space_left_in_db_fifo) {
+ dev_dbg_ratelimited(hdev->dev, "port %d DB fifo full. PI %d, CI %d\n", port,
+ db_fifo_pi, db_fifo_ci);
+ return -EBUSY;
+ }
+
+ NIC_WREG32(NIC0_QPC0_SECURED_DB_FIRST32, pi);
+ NIC_WREG32(NIC0_QPC0_SECURED_DB_SECOND32, RAW_QPN);
+
+ /* Incrementing local PI and wrap around at the size of NIC_FIFO_DB_SIZE */
+ gaudi2_port->db_fifo_pi = (gaudi2_port->db_fifo_pi + 1) & (NIC_FIFO_DB_SIZE - 1);
+
+ *full_after_tx = !(CIRC_SPACE(gaudi2_port->db_fifo_pi, db_fifo_ci, NIC_FIFO_DB_SIZE));
+
+ return 0;
+}
+
+static void gaudi2_cn_compute_reset_prepare(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_cn_device *hdev = aux_dev->priv;
+ struct gaudi2_cn_device *gaudi2;
+
+ gaudi2 = hdev->asic_specific;
+ gaudi2->in_compute_reset = true;
+
+ gaudi2_cn_eq_enter_temporal_polling_mode(hdev);
+ gaudi2_cn_phy_flush_link_status_work(hdev);
+}
+
+static void gaudi2_cn_compute_reset_late_init(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_cn_device *hdev = aux_dev->priv;
+ struct gaudi2_cn_device *gaudi2;
+
+ gaudi2_cn_eq_exit_temporal_polling_mode(hdev);
+
+ gaudi2 = hdev->asic_specific;
+ gaudi2->in_compute_reset = false;
+}
+
+static void gaudi2_handle_cn_port_reset_locked(struct hbl_cn_port *cn_port)
+{
+ struct gaudi2_en_aux_ops *gaudi2_en_aux_ops;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct gaudi2_cn_device *gaudi2;
+
+ gaudi2 = hdev->asic_specific;
+ gaudi2_en_aux_ops = &gaudi2->en_aux_ops;
+
+ if (hdev->ext_ports_mask & BIT(cn_port->port)) {
+ dev_err_ratelimited(hdev->dev, "port %d, going to reset\n", cn_port->port);
+ if (gaudi2_en_aux_ops->port_reset_locked)
+ gaudi2_en_aux_ops->port_reset_locked(&hdev->en_aux_dev, cn_port->port);
+ } else {
+ hbl_cn_internal_port_fini_locked(cn_port);
+ hbl_cn_internal_port_init_locked(cn_port);
+ }
+}
+
+static void gaudi2_cn_print_event(struct hbl_cn_device *hdev, u16 event_type, bool ratelimited,
+ const char *fmt, ...)
+{
+ struct gaudi2_cn_aux_ops *gaudi2_aux_ops;
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ struct va_format vaf;
+ va_list args;
+ char *name;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ gaudi2_aux_ops = aux_ops->asic_ops;
+
+ name = gaudi2_aux_ops->get_event_name(aux_dev, event_type);
+
+ va_start(args, fmt);
+ vaf.fmt = fmt;
+ vaf.va = &args;
+
+ if (ratelimited)
+ dev_err_ratelimited(hdev->dev, "%s: %pV\n", name, &vaf);
+ else
+ dev_err(hdev->dev, "%s: %pV\n", name, &vaf);
+
+ va_end(args);
+}
+
+static int gaudi2_handle_error(struct hbl_cn_device *hdev, u16 event_type, u8 macro_index,
+ struct hbl_cn_eq_intr_cause *intr_cause)
+{
+ u32 intr_cause_data, port, first_port, last_port, num_of_ports_in_macro, intr_type,
+ error_count = 0;
+ int idx, i;
+
+ num_of_ports_in_macro = NIC_NUMBER_OF_ENGINES / NIC_NUMBER_OF_MACROS;
+ first_port = macro_index * num_of_ports_in_macro;
+ last_port = (macro_index + 1) * num_of_ports_in_macro - 1;
+ intr_type = intr_cause->intr_type;
+
+ if (!intr_type || intr_type > HBL_CN_CPUCP_INTR_TXE) {
+ gaudi2_cn_print_event(hdev, event_type, true, "port %u: invalid interrupt type %u",
+ macro_index, intr_type);
+ return 1;
+ }
+
+ intr_cause_data = (u32)intr_cause->intr_cause[0].intr_cause_data;
+
+ switch (intr_type) {
+ case HBL_CN_CPUCP_INTR_TMR:
+ gaudi2_cn_print_event(hdev, event_type, true,
+ "TMR error on macro %d cause 0x%x", macro_index,
+ intr_cause_data);
+ return 1;
+ case HBL_CN_CPUCP_INTR_RXB_CORE_SPI:
+ for (i = 0; i < GAUDI2_NUM_OF_NIC_RXB_CORE_SPI_CAUSE; i++) {
+ if (!(intr_cause_data & BIT(i)))
+ continue;
+
+ gaudi2_cn_print_event(hdev, event_type, true,
+ "RXB CORE SPI error on macro %d cause: %s. cause bit %d",
+ macro_index,
+ gaudi2_cn_rxb_core_spi_interrupts_cause[i], i);
+ error_count++;
+ }
+
+ return error_count;
+ case HBL_CN_CPUCP_INTR_RXB_CORE_SEI:
+ for (i = 0; i < GAUDI2_NUM_OF_NIC_RXB_CORE_SEI_CAUSE; i++) {
+ if (!(intr_cause_data & BIT(i)))
+ continue;
+
+ gaudi2_cn_print_event(hdev, event_type, true,
+ "RXB CORE SEI error on macro %d cause: %s. cause bit %d",
+ macro_index,
+ gaudi2_cn_rxb_core_sei_interrupts_cause[i], i);
+ error_count++;
+ }
+
+ return error_count;
+ }
+
+ for (port = first_port, idx = 0; port <= last_port; port++, idx++) {
+ /* check that port is indeed enabled in the macro */
+ if (!(hdev->ports_mask & BIT(port)))
+ continue;
+
+ intr_cause_data = (u32)intr_cause->intr_cause[idx].intr_cause_data;
+ if (!intr_cause_data)
+ continue;
+
+ switch (intr_type) {
+ case HBL_CN_CPUCP_INTR_QPC_RESP_ERR:
+ for (i = 0; i < GAUDI2_NUM_OF_NIC_QPC_RESP_ERR_CAUSE; i++) {
+ if (!(intr_cause_data & BIT(i)))
+ continue;
+
+ gaudi2_cn_print_event(hdev, event_type, true,
+ "QPC response error on port %d cause: %s. cause bit %d",
+ port,
+ gaudi2_cn_qpc_resp_err_interrupts_cause[i],
+ i);
+ error_count++;
+ }
+
+ break;
+ case HBL_CN_CPUCP_INTR_RXE_SPI:
+ for (i = 0; i < GAUDI2_NUM_OF_NIC_RXE_SPI_CAUSE; i++) {
+ if (!(intr_cause_data & BIT(i)))
+ continue;
+
+ dev_dbg_ratelimited(hdev->dev,
+ "RXE SPI error on port %d cause: %s. cause bit %d\n",
+ port, gaudi2_cn_rxe_spi_interrupts_cause[i],
+ i);
+ error_count++;
+ }
+
+ break;
+ case HBL_CN_CPUCP_INTR_RXE_SEI:
+ for (i = 0; i < GAUDI2_NUM_OF_NIC_RXE_SEI_CAUSE; i++) {
+ if (!(intr_cause_data & BIT(i)))
+ continue;
+
+ gaudi2_cn_print_event(hdev, event_type, true,
+ "RXE SEI error on port %d cause: %s. cause bit %d",
+ port,
+ gaudi2_cn_rxe_sei_interrupts_cause[i], i);
+ error_count++;
+ }
+
+ break;
+ case HBL_CN_CPUCP_INTR_TXS:
+ gaudi2_cn_print_event(hdev, event_type, true,
+ "TXS error on port %d cause 0x%x", port,
+ intr_cause_data);
+ error_count++;
+ break;
+ case HBL_CN_CPUCP_INTR_TXE:
+ gaudi2_cn_print_event(hdev, event_type, true,
+ "TXE error on port %d cause 0x%x", port,
+ intr_cause_data);
+ error_count++;
+ break;
+ default:
+ gaudi2_cn_print_event(hdev, event_type, true,
+ "Invalid interrupt type port %d", port);
+ }
+ }
+
+ return error_count;
+}
+
+static void gaudi2_cn_convert_intr_cause(struct hbl_cn_eq_intr_cause *to,
+ struct hl_eq_nic_intr_cause *from)
+{
+ int i;
+
+ to->intr_type = le32_to_cpu(from->intr_type);
+
+ for (i = 0; i < MAX_PORTS_PER_NIC; i++)
+ to->intr_cause[i].intr_cause_data =
+ le64_to_cpu(from->intr_cause[i].intr_cause_data);
+}
+
+static int gaudi2_cn_sw_err_event(struct hbl_aux_dev *aux_dev, u16 event_type, u8 macro_index,
+ struct hl_eq_nic_intr_cause *intr_cause_cpucp)
+{
+ u32 qpc_intr_cause, port, first_port, last_port, num_of_ports_in_macro, error_count = 0;
+ struct hbl_cn_device *hdev = aux_dev->priv;
+ struct hbl_cn_eq_intr_cause intr_cause;
+ struct hbl_cn_port *cn_port;
+
+ gaudi2_cn_convert_intr_cause(&intr_cause, intr_cause_cpucp);
+
+ num_of_ports_in_macro = NIC_NUMBER_OF_ENGINES / NIC_NUMBER_OF_MACROS;
+ first_port = macro_index * num_of_ports_in_macro;
+ last_port = (macro_index + 1) * num_of_ports_in_macro - 1;
+
+ for (port = first_port; port <= last_port; port++) {
+ /* check that port is indeed enabled in the macro */
+ if (!(hdev->ports_mask & BIT(port)))
+ continue;
+
+ qpc_intr_cause = NIC_RREG32(NIC0_QPC0_INTERRUPT_CAUSE);
+
+ /* eqe interrupts are mapped to MSI except interrupt on error event queue
+ * which is handled here, in such case port reset is required.
+ */
+ if (!(qpc_intr_cause & 0x400))
+ continue;
+
+ gaudi2_cn_print_event(hdev, event_type, true, "QPC EQ error on port %d", port);
+ NIC_WREG32(NIC0_QPC0_INTERRUPT_CLR, 0x400);
+ error_count++;
+
+ cn_port = &hdev->cn_ports[port];
+ mutex_lock(&cn_port->control_lock);
+ hbl_cn_track_port_reset(cn_port, NIC_EQ_ERR_SYNDROME);
+ gaudi2_handle_cn_port_reset_locked(cn_port);
+ mutex_unlock(&cn_port->control_lock);
+ }
+
+ error_count += gaudi2_handle_error(hdev, event_type, macro_index, &intr_cause);
+
+ return error_count;
+}
+
+static int gaudi2_cn_axi_error_response_event(struct hbl_aux_dev *aux_dev, u16 event_type,
+ u8 macro_index,
+ struct hl_eq_nic_intr_cause *intr_cause_cpucp)
+{
+ struct hbl_cn_device *hdev = aux_dev->priv;
+ struct hbl_cn_eq_intr_cause intr_cause;
+
+ gaudi2_cn_convert_intr_cause(&intr_cause, intr_cause_cpucp);
+
+ return gaudi2_handle_error(hdev, event_type, macro_index, &intr_cause);
+}
+
+static void gaudi2_cn_pre_sw_init(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_properties *cn_prop = &hdev->cn_props;
+
+ cn_prop->phy_base_addr = NIC0_PHY_BASE;
+ cn_prop->max_hw_qps_num = NIC_HW_MAX_QP_NUM;
+ cn_prop->max_qps_num = NIC_MAX_QP_NUM;
+ cn_prop->max_hw_user_wqs_num = USER_WQES_MAX_NUM;
+ cn_prop->min_hw_user_wqs_num = USER_WQES_MIN_NUM;
+ cn_prop->rwqe_size = NIC_RECV_WQE_SIZE;
+ cn_prop->force_cq = false;
+ cn_prop->max_num_of_lanes = NIC_MAX_NUM_OF_LANES;
+ cn_prop->num_of_macros = NIC_NUMBER_OF_MACROS;
+ cn_prop->max_cqs = GAUDI2_NIC_MAX_CQS_NUM;
+ cn_prop->max_ccqs = NIC_MAX_CCQS_NUM;
+ cn_prop->max_db_fifos = GAUDI2_NIC_NUM_DB_FIFOS;
+ cn_prop->user_cq_min_entries = NIC_CQ_USER_MIN_ENTRIES;
+ cn_prop->user_cq_max_entries = NIC_CQ_USER_MAX_ENTRIES;
+ cn_prop->cqe_size = CQE_SIZE;
+ cn_prop->max_frm_len = NIC_MAX_FRM_LEN;
+ cn_prop->raw_elem_size = NIC_RAW_ELEM_SIZE;
+ cn_prop->max_raw_mtu = NIC_RAW_MAX_MTU;
+ cn_prop->min_raw_mtu = NIC_RAW_MIN_MTU;
+ cn_prop->max_wq_arr_type = HBL_CNI_USER_WQ_RECV;
+ cn_prop->is_phy_fw_binary = true;
+}
+
+static int gaudi2_cn_sw_init(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_ring **rx_rings, **cq_rings, **wq_rings;
+ struct gaudi2_cn_aux_data *gaudi2_cn_aux_data;
+ struct gaudi2_en_aux_data *gaudi2_en_aux_data;
+ struct gaudi2_en_aux_ops *gaudi2_en_aux_ops;
+ struct hbl_cn_aux_data *cn_aux_data;
+ struct hbl_en_aux_data *en_aux_data;
+ struct hbl_cn_aux_ops *cn_aux_ops;
+ struct hbl_en_aux_ops *en_aux_ops;
+ struct gaudi2_cn_device *gaudi2;
+ struct hbl_aux_dev *cn_aux_dev;
+ struct hbl_aux_dev *en_aux_dev;
+ int rc;
+
+ BUILD_BUG_ON_NOT_POWER_OF_2(NIC_RAW_ELEM_SIZE);
+ BUILD_BUG_ON_NOT_POWER_OF_2(NIC_RX_RING_PKT_NUM);
+ BUILD_BUG_ON_NOT_POWER_OF_2(NIC_CQ_MAX_ENTRIES);
+ BUILD_BUG_ON_NOT_POWER_OF_2(NIC_EQ_RING_NUM_REC);
+
+ gaudi2 = kzalloc(sizeof(*gaudi2), GFP_KERNEL);
+ if (!gaudi2)
+ return -ENOMEM;
+
+ rx_rings = kcalloc(NIC_NUMBER_OF_PORTS, sizeof(*rx_rings), GFP_KERNEL);
+ if (!rx_rings) {
+ rc = -ENOMEM;
+ goto rx_rings_fail;
+ }
+
+ cq_rings = kcalloc(NIC_NUMBER_OF_PORTS, sizeof(*cq_rings), GFP_KERNEL);
+ if (!cq_rings) {
+ rc = -ENOMEM;
+ goto cq_rings_fail;
+ }
+
+ wq_rings = kcalloc(NIC_NUMBER_OF_PORTS, sizeof(*wq_rings), GFP_KERNEL);
+ if (!wq_rings) {
+ rc = -ENOMEM;
+ goto qp_rings_fail;
+ }
+
+ hdev->asic_specific = gaudi2;
+
+ cn_aux_dev = hdev->cn_aux_dev;
+ cn_aux_data = cn_aux_dev->aux_data;
+ cn_aux_ops = cn_aux_dev->aux_ops;
+ gaudi2_cn_aux_data = cn_aux_data->asic_specific;
+ gaudi2->cn_aux_ops = cn_aux_ops->asic_ops;
+
+ gaudi2->temporal_polling = !hdev->poll_enable;
+ gaudi2->fw_security_enabled = gaudi2_cn_aux_data->fw_security_enabled;
+ gaudi2->msix_enabled = gaudi2_cn_aux_data->msix_enabled;
+ gaudi2->cfg_base = gaudi2_cn_aux_data->cfg_base;
+ gaudi2->irq_num_port_base = gaudi2_cn_aux_data->irq_num_port_base;
+ gaudi2->sob_id_base = gaudi2_cn_aux_data->sob_id_base;
+ gaudi2->sob_inc_cfg_val = gaudi2_cn_aux_data->sob_inc_cfg_val;
+ gaudi2->setup_type = gaudi2_cn_aux_data->setup_type;
+
+ gaudi2_en_aux_data = &gaudi2->en_aux_data;
+ gaudi2_en_aux_ops = &gaudi2->en_aux_ops;
+
+ en_aux_dev = &hdev->en_aux_dev;
+ en_aux_data = en_aux_dev->aux_data;
+ en_aux_ops = en_aux_dev->aux_ops;
+ en_aux_data->asic_specific = gaudi2_en_aux_data;
+ en_aux_ops->asic_ops = gaudi2_en_aux_ops;
+
+ gaudi2_en_aux_data->rx_rings = rx_rings;
+ gaudi2_en_aux_data->cq_rings = cq_rings;
+ gaudi2_en_aux_data->wq_rings = wq_rings;
+ gaudi2_en_aux_data->kernel_asid = hdev->kernel_asid;
+ gaudi2_en_aux_data->raw_qpn = RAW_QPN;
+ gaudi2_en_aux_data->tx_ring_len = NIC_TX_BUF_SIZE;
+ gaudi2_en_aux_data->schedq_num = TXS_PORT_RAW_SCHED_Q * HBL_EN_PFC_PRIO_NUM +
+ GAUDI2_PFC_PRIO_DRIVER;
+
+ /* As a W/A for H/W bug H6-3399, we increase our Tx packets by padding them with bigger
+ * value than the default. This should keep the MAC in the other side busier on each packet
+ * processing, hence decrease the rate that it pushes the packet towards the Rx.
+ */
+ gaudi2_en_aux_data->pad_size = NIC_SKB_PAD_SIZE;
+
+ /* en2cn */
+ gaudi2_en_aux_ops->configure_cq = gaudi2_cn_configure_cq;
+ gaudi2_en_aux_ops->arm_cq = gaudi2_cn_arm_cq;
+ gaudi2_en_aux_ops->write_rx_ci = gaudi2_cn_write_rx_ci;
+ gaudi2_en_aux_ops->get_pfc_cnts = gaudi2_cn_get_pfc_cnts;
+ gaudi2_en_aux_ops->ring_tx_doorbell = gaudi2_cn_ring_tx_doorbell;
+ gaudi2_en_aux_ops->qp_err_syndrome_to_str = gaudi2_cn_qp_err_syndrome_to_str;
+ gaudi2_en_aux_ops->db_fifo_reset = gaudi2_cn_db_fifo_reset;
+
+ hdev->ctrl_op_mask = BIT(HBL_CNI_OP_ALLOC_CONN) |
+ BIT(HBL_CNI_OP_SET_REQ_CONN_CTX) |
+ BIT(HBL_CNI_OP_SET_RES_CONN_CTX) |
+ BIT(HBL_CNI_OP_DESTROY_CONN) |
+ BIT(HBL_CNI_OP_USER_WQ_SET) |
+ BIT(HBL_CNI_OP_USER_WQ_UNSET) |
+ BIT(HBL_CNI_OP_SET_USER_APP_PARAMS) |
+ BIT(HBL_CNI_OP_GET_USER_APP_PARAMS) |
+ BIT(HBL_CNI_OP_ALLOC_USER_DB_FIFO) |
+ BIT(HBL_CNI_OP_USER_DB_FIFO_SET) |
+ BIT(HBL_CNI_OP_USER_DB_FIFO_UNSET) |
+ BIT(HBL_CNI_OP_EQ_POLL) |
+ BIT(HBL_CNI_OP_USER_ENCAP_ALLOC) |
+ BIT(HBL_CNI_OP_USER_ENCAP_SET) |
+ BIT(HBL_CNI_OP_USER_ENCAP_UNSET) |
+ BIT(HBL_CNI_OP_ALLOC_USER_CQ_ID) |
+ BIT(HBL_CNI_OP_USER_CQ_ID_SET) |
+ BIT(HBL_CNI_OP_USER_CQ_ID_UNSET) |
+ BIT(HBL_CNI_OP_DUMP_QP);
+
+ hdev->debugfs_supp_mask = BIT(NIC_MAC_LOOPBACK) |
+ BIT(NIC_PAM4_TX_TAPS) |
+ BIT(NIC_NRZ_TX_TAPS) |
+ BIT(NIC_POLARITY) |
+ BIT(NIC_QP) |
+ BIT(NIC_WQE) |
+ BIT(NIC_RESET_CNT) |
+ BIT(NIC_MAC_LANE_REMAP) |
+ BIT(NIC_RAND_STATUS) |
+ BIT(NIC_MMU_BYPASS) |
+ BIT(NIC_ETH_LOOPBACK) |
+ BIT(NIC_PHY_REGS_PRINT) |
+ BIT(NIC_SHOW_INTERNAL_PORTS_STATUS) |
+ BIT(NIC_PRINT_FEC_STATS) |
+ BIT(NIC_DISABLE_DECAP) |
+ BIT(NIC_PHY_SET_NRZ) |
+ BIT(NIC_PHY_DUMP_SERDES_PARAMS) |
+ BIT(NIC_PHY_CALC_BER) |
+ BIT(NIC_PHY_CALC_BER_WAIT_SEC) |
+ BIT(NIC_OVERRIDE_PORT_STATUS) |
+ BIT(NIC_ACCUMULATE_FEC_DURATION) |
+ BIT(NIC_PHY_FORCE_FIRST_TX_TAPS_CFG);
+
+ hdev->ib_support = true;
+ hdev->qpc_cache_inv_timeout = hdev->pldm ? NIC_PLDM_QPC_INV_USEC :
+ NIC_QPC_INV_USEC;
+ hdev->qp_wait_for_idle = true;
+ hdev->qp_reset_mode = CN_QP_RESET_MODE_HARD;
+ hdev->hw_invalid_while_teardown = false;
+ hdev->has_eq = true;
+ hdev->umr_support = true;
+ hdev->cc_support = true;
+
+ gaudi2->mac_rs_fec_ctrl_support = true;
+ gaudi2->flush_db_fifo = false;
+
+ hdev->cn_props.max_qp_error_syndromes = NIC_MAX_QP_ERR_SYNDROMES;
+ hdev->cn_props.status_packet_size = sizeof(struct cpucp_nic_status);
+
+ hdev->wq_arrays_pool_enable = true;
+ hdev->mmap_type_flag = HBL_CN_MMAP_TYPE_CN_MEM;
+
+ return 0;
+
+qp_rings_fail:
+ kfree(cq_rings);
+cq_rings_fail:
+ kfree(rx_rings);
+rx_rings_fail:
+ kfree(gaudi2);
+
+ return rc;
+}
+
+static void gaudi2_cn_sw_fini(struct hbl_cn_device *hdev)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_en_aux_data *en_aux_data;
+
+ en_aux_data = &gaudi2->en_aux_data;
+
+ kfree(en_aux_data->wq_rings);
+ kfree(en_aux_data->cq_rings);
+ kfree(en_aux_data->rx_rings);
+ kfree(gaudi2);
+}
+
+static void gaudi2_cn_set_en_data(struct hbl_cn_device *hdev)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_en_aux_data *gaudi2_aux_data;
+ struct gaudi2_cn_port *gaudi2_port;
+ struct hbl_en_aux_data *aux_data;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_cn_port *cn_port;
+ struct hbl_aux_dev *aux_dev;
+ int i;
+
+ aux_dev = &hdev->en_aux_dev;
+ aux_data = aux_dev->aux_data;
+ gaudi2_aux_data = &gaudi2->en_aux_data;
+ aux_data->asic_specific = gaudi2_aux_data;
+ aux_ops = aux_dev->aux_ops;
+ aux_ops->asic_ops = &gaudi2->en_aux_ops;
+
+ for (i = 0; i < NIC_NUMBER_OF_PORTS; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+ gaudi2_port = cn_port->cn_specific;
+
+ if (cn_port->eth_enable) {
+ gaudi2_aux_data->rx_rings[i] = &gaudi2_port->rx_ring;
+ gaudi2_aux_data->cq_rings[i] = &gaudi2_port->cq_rings[NIC_CQ_RAW_IDX];
+ gaudi2_aux_data->wq_rings[i] = &gaudi2_port->wq_ring;
+ }
+ }
+}
+
+static int gaudi2_register_qp(struct hbl_cn_port *cn_port, u32 qp_id, u32 asid)
+{
+ return hbl_cn_eq_dispatcher_register_qp(cn_port, asid, qp_id);
+}
+
+static void gaudi2_unregister_qp(struct hbl_cn_port *cn_port, u32 qp_id)
+{
+ hbl_cn_eq_dispatcher_unregister_qp(cn_port, qp_id);
+}
+
+static void gaudi2_get_qp_id_range(struct hbl_cn_port *cn_port, u32 *min_id, u32 *max_id)
+{
+ *min_id = NIC_MIN_CONN_ID;
+ *max_id = NIC_MAX_CONN_ID;
+}
+
+static u8 gaudi2_qp_event_is_req_event(struct hbl_cn_eqe *eqe)
+{
+ char synd_str_to_lower[GAUDI2_MAX_SYNDROME_STRING_LEN] = {};
+ u32 synd = EQE_QP_EVENT_ERR_SYND(eqe);
+ char *synd_str;
+
+ synd_str = gaudi2_cn_qp_err_syndrome_to_str(synd);
+
+ if (strlen(synd_str)) {
+ strscpy(synd_str_to_lower, synd_str, sizeof(synd_str_to_lower));
+ hbl_cn_strtolower(synd_str_to_lower);
+
+ if (strnstr(synd_str_to_lower, "req", strlen(synd_str_to_lower)))
+ return 1;
+ }
+
+ return 0;
+}
+
+static int gaudi2_eq_poll(struct hbl_cn_port *cn_port, u32 asid, struct hbl_cni_eq_poll_out *event)
+{
+ u32 ev_type, ev_valid, port = cn_port->port;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_eqe eqe;
+ int rc;
+
+ rc = hbl_cn_eq_dispatcher_dequeue(cn_port, asid, &eqe, false);
+ if (rc)
+ return rc;
+
+ ev_valid = EQE_IS_VALID(&eqe);
+ if (!ev_valid) {
+ dev_dbg_ratelimited(hdev->dev,
+ "got EQE invalid entry while expecting a valid one\n");
+ return -ENODATA;
+ }
+
+ ev_type = EQE_TYPE(&eqe);
+ switch (ev_type) {
+ case EQE_COMP_ERR:
+ event->ev_type = HBL_CNI_EQ_EVENT_TYPE_CQ_ERR;
+ event->idx = EQE_CQ_EVENT_CQ_NUM(&eqe);
+ break;
+ case EQE_QP_ERR:
+ event->ev_type = HBL_CNI_EQ_EVENT_TYPE_QP_ERR;
+ event->idx = EQE_RAW_TX_EVENT_QPN(&eqe);
+ event->rest_occurred = EQE_QP_EVENT_RESET(&eqe);
+ event->is_req = gaudi2_qp_event_is_req_event(&eqe);
+ break;
+ case EQE_DB_FIFO_OVERRUN:
+ event->ev_type = HBL_CNI_EQ_EVENT_TYPE_DB_FIFO_ERR;
+ event->idx = EQE_DB_EVENT_DB_NUM(&eqe);
+ break;
+ case EQE_CONG:
+ /* completion ready in cc comp queue */
+ event->ev_type = HBL_CNI_EQ_EVENT_TYPE_CCQ;
+ event->idx = EQE_CQ_EVENT_CQ_NUM(&eqe);
+ break;
+ case EQE_LINK_STATUS:
+ event->ev_type = HBL_CNI_EQ_EVENT_TYPE_LINK_STATUS;
+ break;
+ case EQE_QP_ALIGN_COUNTERS:
+ event->ev_type = HBL_CNI_EQ_EVENT_TYPE_QP_ALIGN_COUNTERS;
+ event->idx = EQE_SW_EVENT_QPN(&eqe);
+ break;
+ default:
+ /* if the event should not be reported to the user then return
+ * as if no event was found
+ */
+ dev_dbg_ratelimited(hdev->dev, "dropping Port-%d event %d report to user\n", port,
+ ev_type);
+ return -ENODATA;
+ }
+
+ /* fill the vevent-specific data */
+ event->ev_data = eqe.data[2];
+
+ return 0;
+}
+
+static void gaudi2_get_db_fifo_id_range(struct hbl_cn_port *cn_port, u32 *min_id, u32 *max_id)
+{
+ *min_id = GAUDI2_MIN_DB_FIFO_ID;
+ *max_id = GAUDI2_MAX_DB_FIFO_ID;
+}
+
+static void gaudi2_get_db_fifo_hw_id_range(struct hbl_cn_port *cn_port, u32 *min_id, u32 *max_id)
+{
+ *min_id = db_fifo_hw_id(GAUDI2_MIN_DB_FIFO_ID);
+ *max_id = GAUDI2_DB_FIFO_SECURE_HW_ID;
+}
+
+static void gaudi2_get_db_fifo_modes_mask(struct hbl_cn_port *cn_port, u32 *mode_mask)
+{
+ *mode_mask = BIT(HBL_CNI_DB_FIFO_TYPE_DB) | BIT(HBL_CNI_DB_FIFO_TYPE_CC);
+}
+
+static int gaudi2_db_fifo_allocate(struct hbl_cn_port *cn_port,
+ struct hbl_cn_db_fifo_xarray_pdata *xa_pdata)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 fifo_size;
+
+ switch (xa_pdata->fifo_mode) {
+ case HBL_CNI_DB_FIFO_TYPE_DB:
+ case HBL_CNI_DB_FIFO_TYPE_CC:
+ fifo_size = DB_FIFO_SIZE;
+ break;
+ default:
+ dev_dbg(hdev->dev, "Port %d, invalid DB fifo mode: %d. Allocation failed\n",
+ cn_port->port, xa_pdata->fifo_mode);
+ return -EINVAL;
+ }
+
+ xa_pdata->fifo_size = fifo_size;
+
+ return 0;
+}
+
+static void gaudi2_db_fifo_free(struct hbl_cn_port *cn_port, u32 db_pool_offset, u32 fifo_size)
+{
+}
+
+static int gaudi2_db_fifo_set(struct hbl_cn_port *cn_port, struct hbl_cn_ctx *ctx, u32 id,
+ u64 ci_device_handle, struct hbl_cn_db_fifo_xarray_pdata *xa_pdata)
+{
+ struct gaudi2_cn_port *gaudi2_port = cn_port->cn_specific;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+ u32 mmu_bypass;
+ u8 is_cc;
+ u32 val;
+ int rc;
+
+ rc = gaudi2_cn_eq_dispatcher_register_db(gaudi2_port, ctx->asid, db_fifo_hw_id(id));
+ if (rc)
+ return rc;
+
+ WARN_ON_CACHE_UNALIGNED(ci_device_handle);
+
+ /* Config HW to use memory buffer for updating
+ * consumer-index(CI) when it pops fifo.
+ */
+ NIC_WREG32(NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_DBFIFO_CI_UPD_ADDR_31_7 + db_fifo_offset64(id),
+ lower_32_bits(ci_device_handle) >> 7);
+ NIC_WREG32(NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_DBFIFO_CI_UPD_ADDR_63_32 + db_fifo_offset64(id),
+ upper_32_bits(ci_device_handle));
+
+ is_cc = (xa_pdata->fifo_mode == HBL_CNI_DB_FIFO_TYPE_CC);
+ /* We use generic H/W FIFOs. Configured as a userspace doorbell or congestion control FIFO.
+ */
+ NIC_WREG32(NIC0_QPC0_DB_FIFO_CFG_0 + db_fifo_offset(id), is_cc);
+
+ mmu_bypass = !!(hdev->mmu_bypass);
+ val = ctx->asid;
+ val |= mmu_bypass << NIC0_QPC0_DB_FIFO_USER_OVRD_MMU_BYPASS_SHIFT;
+ NIC_WREG32(NIC0_QPC0_DB_FIFO_USER_OVRD_0 + db_fifo_offset(id), val);
+
+ return 0;
+}
+
+static void db_fifo_reset(struct hbl_cn_port *cn_port, u32 id, u64 mmap_handle)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_mem_buf *buf;
+ u32 *ci_cpu_addr;
+
+ buf = hbl_cn_mem_buf_get(hdev, mmap_handle);
+ if (!buf) {
+ dev_err(hdev->dev, "Failed to retrieve port %d db fifo CI memory\n",
+ cn_port->port);
+ return;
+ }
+
+ /* Read latest HW updated CI */
+ ci_cpu_addr = (u32 *)buf->kernel_address;
+
+ __db_fifo_reset(cn_port, ci_cpu_addr, id, false);
+
+ hbl_cn_mem_buf_put(buf);
+}
+
+static void gaudi2_db_fifo_unset(struct hbl_cn_port *cn_port, u32 id,
+ struct hbl_cn_db_fifo_xarray_pdata *xa_pdata)
+{
+ db_fifo_reset(cn_port, id, xa_pdata->ci_mmap_handle);
+
+ hbl_cn_eq_dispatcher_unregister_db(cn_port, db_fifo_hw_id(id));
+}
+
+static void gaudi2_get_encap_id_range(struct hbl_cn_port *cn_port, u32 *min_id, u32 *max_id)
+{
+ if (cn_port->port & 0x1) {
+ *min_id = GAUDI2_USER_ENCAP_ID + 2;
+ *max_id = GAUDI2_USER_ENCAP_ID + 2;
+ } else {
+ *min_id = GAUDI2_USER_ENCAP_ID;
+ *max_id = GAUDI2_USER_ENCAP_ID;
+ }
+}
+
+static void gaudi2_get_default_encap_id(struct hbl_cn_port *cn_port, u32 *id)
+{
+ u32 min, max;
+
+ gaudi2_get_encap_id_range(cn_port, &min, &max);
+ *id = max + 1;
+}
+
+static int gaudi2_encap_set(struct hbl_cn_port *cn_port, u32 encap_id,
+ struct hbl_cn_encap_xarray_pdata *xa_pdata)
+{
+ u32 encap_hdr_offset = NIC0_TXE0_ENCAP_DATA_63_32_0 - NIC0_TXE0_ENCAP_DATA_31_0_0;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 *encap_header = xa_pdata->encap_header;
+ u32 encap_cfg = 0, decap_cfg = 0;
+ u32 port = cn_port->port;
+ u32 hdr_size;
+ int i;
+
+ NIC_WREG32(NIC0_TXE0_SOURCE_IP_PORT0_0 + encap_offset(encap_id), xa_pdata->src_ip);
+
+ encap_cfg |= xa_pdata->encap_type_data & NIC0_TXE0_ENCAP_CFG_IPV4_PROTOCOL_UDP_DEST_MASK;
+
+ if (xa_pdata->encap_type == HBL_CNI_ENCAP_NONE) {
+ NIC_WREG32(NIC0_TXE0_ENCAP_CFG_0 + encap_offset(encap_id), encap_cfg);
+ return 0;
+ }
+
+ if (!IS_ALIGNED(xa_pdata->encap_header_size, sizeof(u32))) {
+ dev_err(hdev->dev, "Encap header size(%d) must be a multiple of %ld\n",
+ xa_pdata->encap_header_size, sizeof(u32));
+ return -EINVAL;
+ }
+
+ hdr_size = xa_pdata->encap_header_size / sizeof(u32);
+ encap_cfg |= (hdr_size << NIC0_TXE0_ENCAP_CFG_ENCAP_SIZE_SHIFT) &
+ NIC0_TXE0_ENCAP_CFG_ENCAP_SIZE_MASK;
+
+ if (xa_pdata->encap_type == HBL_CNI_ENCAP_OVER_UDP) {
+ encap_cfg |= BIT(NIC0_TXE0_ENCAP_CFG_HDR_FORMAT_SHIFT);
+ if (!hdev->is_decap_disabled) {
+ decap_cfg |= NIC0_RXB_CORE_TNL_DECAP_UDP_VALID_MASK;
+ decap_cfg |= (xa_pdata->encap_type_data <<
+ NIC0_RXB_CORE_TNL_DECAP_UDP_UDP_DEST_PORT_SHIFT) &
+ NIC0_RXB_CORE_TNL_DECAP_UDP_UDP_DEST_PORT_MASK;
+ decap_cfg |= (hdr_size << NIC0_RXB_CORE_TNL_DECAP_UDP_TNL_SIZE_SHIFT) &
+ NIC0_RXB_CORE_TNL_DECAP_UDP_TNL_SIZE_MASK;
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TNL_DECAP_UDP_0 + encap_offset(encap_id),
+ decap_cfg);
+ }
+ } else if (xa_pdata->encap_type == HBL_CNI_ENCAP_OVER_IPV4) {
+ if (!hdev->is_decap_disabled) {
+ decap_cfg |= NIC0_RXB_CORE_TNL_DECAP_IPV4_VALID_MASK;
+ decap_cfg |= (xa_pdata->encap_type_data <<
+ NIC0_RXB_CORE_TNL_DECAP_IPV4_IPV4_PROTOCOL_SHIFT) &
+ NIC0_RXB_CORE_TNL_DECAP_IPV4_IPV4_PROTOCOL_MASK;
+ decap_cfg |= (hdr_size << NIC0_RXB_CORE_TNL_DECAP_IPV4_TNL_SIZE_SHIFT) &
+ NIC0_RXB_CORE_TNL_DECAP_IPV4_TNL_SIZE_MASK;
+
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TNL_DECAP_IPV4_0 + encap_offset(encap_id),
+ decap_cfg);
+ }
+ }
+
+ NIC_WREG32(NIC0_TXE0_ENCAP_CFG_0 + encap_offset(encap_id), encap_cfg);
+
+ /* Encapsulation header is already aligned to 32 bits. Hence, it's
+ * safe to access it in chunks of 4 bytes.
+ */
+ for (i = 0; i * sizeof(u32) < xa_pdata->encap_header_size; i++)
+ NIC_WREG32(NIC0_TXE0_ENCAP_DATA_31_0_0 + encap_hdr_offset * i +
+ encap_offset(encap_id), encap_header[i]);
+
+ return 0;
+}
+
+static void gaudi2_encap_unset(struct hbl_cn_port *cn_port, u32 encap_id,
+ struct hbl_cn_encap_xarray_pdata *xa_pdata)
+{
+ u32 encap_hdr_offset = NIC0_TXE0_ENCAP_DATA_63_32_0 - NIC0_TXE0_ENCAP_DATA_31_0_0;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+ int i;
+
+ NIC_WREG32(NIC0_TXE0_SOURCE_IP_PORT0_0 + encap_offset(encap_id), 0);
+ NIC_WREG32(NIC0_TXE0_ENCAP_CFG_0 + encap_offset(encap_id), 0);
+
+ if (xa_pdata->encap_type == HBL_CNI_ENCAP_OVER_UDP)
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TNL_DECAP_UDP_0 + encap_offset(encap_id), 0);
+ else if (xa_pdata->encap_type == HBL_CNI_ENCAP_OVER_IPV4)
+ NIC_MACRO_WREG32(NIC0_RXB_CORE_TNL_DECAP_IPV4_0 + encap_offset(encap_id), 0);
+
+ for (i = 0; i * sizeof(u32) < xa_pdata->encap_header_size; i++)
+ NIC_WREG32(NIC0_TXE0_ENCAP_DATA_31_0_0 + encap_hdr_offset * i +
+ encap_offset(encap_id), 0);
+}
+
+static u32 gaudi2_cn_get_default_port_speed(struct hbl_cn_device *hdev)
+{
+ return SPEED_100000;
+}
+
+static void gaudi2_cn_get_cnts_names(struct hbl_cn_port *cn_port, u8 *data, bool ext)
+{
+ char str[HBL_IB_CNT_NAME_LEN], *rx_fmt, *tx_fmt;
+ struct hbl_cn_stat *spmu_stats;
+ u32 n_spmu_stats;
+ int i, len;
+
+ if (ext) {
+ len = HBL_IB_CNT_NAME_LEN;
+ rx_fmt = "rx_%s";
+ tx_fmt = "tx_%s";
+ } else {
+ len = ETH_GSTRING_LEN;
+ rx_fmt = "%s";
+ tx_fmt = "%s";
+ }
+
+ hbl_cn_spmu_get_stats_info(cn_port, &spmu_stats, &n_spmu_stats);
+
+ for (i = 0; i < n_spmu_stats; i++)
+ memcpy(data + i * len, spmu_stats[i].str, ETH_GSTRING_LEN);
+ data += i * len;
+
+ if (!cn_port->hdev->skip_mac_cnts) {
+ for (i = 0; i < hbl_cn_mac_stats_rx_len; i++) {
+ memset(str, 0, len);
+ snprintf(str, len, rx_fmt, hbl_cn_mac_stats_rx[i].str);
+ memcpy(data + i * len, str, len);
+ }
+ data += i * len;
+
+ for (i = 0; i < gaudi2_cn_mac_fec_stats_len; i++)
+ memcpy(data + i * len, gaudi2_cn_mac_fec_stats[i].str, ETH_GSTRING_LEN);
+ data += i * len;
+
+ for (i = 0; i < hbl_cn_mac_stats_tx_len; i++) {
+ memset(str, 0, len);
+ snprintf(str, len, tx_fmt, hbl_cn_mac_stats_tx[i].str);
+ memcpy(data + i * len, str, len);
+ }
+ data += i * len;
+ }
+
+ for (i = 0; i < gaudi2_cn_err_stats_len; i++)
+ memcpy(data + i * len, gaudi2_cn_err_stats[i].str, ETH_GSTRING_LEN);
+ data += i * len;
+
+ for (i = 0; i < gaudi2_cn_perf_stats_len; i++)
+ memcpy(data + i * len, gaudi2_cn_perf_stats[i].str, ETH_GSTRING_LEN);
+}
+
+static int gaudi2_cn_get_cnts_num(struct hbl_cn_port *cn_port)
+{
+ int n_spmu_stats, mac_counters;
+ struct hbl_cn_stat *ignore;
+
+ hbl_cn_spmu_get_stats_info(cn_port, &ignore, &n_spmu_stats);
+
+ mac_counters = !cn_port->hdev->skip_mac_cnts ? hbl_cn_mac_stats_rx_len +
+ hbl_cn_mac_stats_tx_len + gaudi2_cn_mac_fec_stats_len : 0;
+
+ return n_spmu_stats + mac_counters + gaudi2_cn_err_stats_len + gaudi2_cn_perf_stats_len;
+}
+
+static int gaudi2_cn_get_mac_tx_stats(struct hbl_cn_port *cn_port, u64 *data)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u64 start_reg, lo_part, hi_part;
+ u32 port = cn_port->port;
+ int i;
+
+ start_reg = (port & 1) ? NIC0_MAC_GLOB_STAT_TX2_ETHERSTATSOCTETS_6 :
+ NIC0_MAC_GLOB_STAT_TX0_ETHERSTATSOCTETS_4;
+
+ for (i = 0; i < hbl_cn_mac_stats_tx_len; i++) {
+ lo_part = NIC_MACRO_RREG32(start_reg + hbl_cn_mac_stats_tx[i].lo_offset);
+ /* Upper part must be read after lower part, since the upper part register
+ * gets its value only after the lower part was read.
+ */
+ hi_part = NIC_MACRO_RREG32(NIC0_MAC_GLOB_STAT_CONTROL_REG_DATA_HI);
+
+ data[i] = lo_part | (hi_part << 32);
+ }
+
+ return i;
+}
+
+static int gaudi2_cn_get_mac_rx_stats(struct hbl_cn_port *cn_port, u64 *data)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u64 start_reg, lo_part, hi_part;
+ u32 port = cn_port->port;
+ int i;
+
+ start_reg = (port & 1) ? NIC0_MAC_GLOB_STAT_RX2_ETHERSTATSOCTETS_2 :
+ NIC0_MAC_GLOB_STAT_RX0_ETHERSTATSOCTETS;
+
+ for (i = 0; i < hbl_cn_mac_stats_rx_len; i++) {
+ lo_part = NIC_MACRO_RREG32(start_reg + hbl_cn_mac_stats_rx[i].lo_offset);
+ /* Upper part must be read after lower part, since the upper part register
+ * gets its value only after the lower part was read.
+ */
+ hi_part = NIC_MACRO_RREG32(NIC0_MAC_GLOB_STAT_CONTROL_REG_DATA_HI);
+
+ data[i] = lo_part | (hi_part << 32);
+ }
+
+ return i;
+}
+
+static int __gaudi2_cn_get_mac_fec_stats(struct hbl_cn_port *cn_port, u64 *data)
+{
+ u64 start_jiffies, diff_ms, numerator, denominator, integer, exp;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+ int i;
+
+ if (!data)
+ return 0;
+
+ /* Read the relevant registers in order to clear them */
+ if (port & 1) {
+ cn_port->correctable_errors_cnt +=
+ NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC2_CCW_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC2_CCW_HI) << 16);
+ cn_port->uncorrectable_errors_cnt +=
+ NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC2_NCCW_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC2_NCCW_HI) << 16);
+
+ for (i = 0; i < 8; i++)
+ NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR4_LO + 4 * i);
+ } else {
+ cn_port->correctable_errors_cnt +=
+ NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_CCW_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_CCW_HI) << 16);
+ cn_port->uncorrectable_errors_cnt +=
+ NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_NCCW_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_NCCW_HI) << 16);
+
+ for (i = 0; i < 8; i++)
+ NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR0_LO + 4 * i);
+ }
+
+ start_jiffies = jiffies;
+
+ /* sleep some time to accumulate stats */
+ msleep(hdev->accumulate_fec_duration);
+
+ diff_ms = jiffies_to_msecs(jiffies - start_jiffies);
+
+ if (port & 1) {
+ data[FEC_CW_CORRECTED] = NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC2_CCW_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC2_CCW_HI) << 16);
+ data[FEC_CW_UNCORRECTED] = NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC2_NCCW_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC2_NCCW_HI) <<
+ 16);
+ data[FEC_SYMBOL_ERR_CORRECTED_LANE_0] =
+ NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR4_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR4_HI) <<
+ 16);
+ data[FEC_SYMBOL_ERR_CORRECTED_LANE_1] =
+ NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR5_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR5_HI) <<
+ 16);
+ data[FEC_SYMBOL_ERR_CORRECTED_LANE_2] =
+ NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR6_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR6_HI) <<
+ 16);
+ data[FEC_SYMBOL_ERR_CORRECTED_LANE_3] =
+ NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR7_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR7_HI) <<
+ 16);
+ } else {
+ data[FEC_CW_CORRECTED] = NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_CCW_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_CCW_HI) << 16);
+ data[FEC_CW_UNCORRECTED] = NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_NCCW_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_NCCW_HI) <<
+ 16);
+ data[FEC_SYMBOL_ERR_CORRECTED_LANE_0] =
+ NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR0_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR0_HI) <<
+ 16);
+ data[FEC_SYMBOL_ERR_CORRECTED_LANE_1] =
+ NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR1_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR1_HI) <<
+ 16);
+ data[FEC_SYMBOL_ERR_CORRECTED_LANE_2] =
+ NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR2_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR2_HI) <<
+ 16);
+ data[FEC_SYMBOL_ERR_CORRECTED_LANE_3] =
+ NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR3_LO) |
+ (NIC_MACRO_RREG32(NIC0_MAC_RS_FEC_RSFEC_SYMBLERR3_HI) <<
+ 16);
+ }
+
+ cn_port->correctable_errors_cnt += data[FEC_CW_CORRECTED];
+ cn_port->uncorrectable_errors_cnt += data[FEC_CW_UNCORRECTED];
+
+ data[FEC_CW_CORRECTED_ACCUM] = cn_port->correctable_errors_cnt;
+ data[FEC_CW_UNCORRECTED_ACCUM] = cn_port->uncorrectable_errors_cnt;
+
+ /* The denominator is the total number of symbols in the measured time T ms
+ * (100G bits/sec = 10G sym/sec = 10G * T/1000 sym = 1G * T / 100 sym)
+ */
+ denominator = div_u64((u64)BIT(30) * diff_ms, 100);
+
+ /* Pre FEC: the numerator is the sum of uncorrected symbols (~= uncorrected_cw * 16) and
+ * corrected symbols.
+ */
+ numerator = data[FEC_CW_UNCORRECTED] << 4;
+ for (i = 0; i < 4; i++)
+ numerator += data[FEC_SYMBOL_ERR_CORRECTED_LANE_0 + i];
+
+ hbl_cn_get_frac_info(numerator, denominator, &integer, &exp);
+
+ data[FEC_PRE_FEC_SER_INT] = integer;
+ data[FEC_PRE_FEC_SER_EXP] = exp;
+
+ /* Post FEC: the numerator is the uncorrected symbols (~= uncorrected_cw * 16) */
+ numerator = data[FEC_CW_UNCORRECTED] << 4;
+
+ hbl_cn_get_frac_info(numerator, denominator, &integer, &exp);
+
+ data[FEC_POST_FEC_SER_INT] = integer;
+ data[FEC_POST_FEC_SER_EXP] = exp;
+
+ return (int)gaudi2_cn_mac_fec_stats_len;
+}
+
+static int gaudi2_cn_get_mac_stats(struct hbl_cn_port *cn_port, u64 *data)
+{
+ int cnt = 0;
+
+ if (cn_port->hdev->skip_mac_cnts)
+ return 0;
+
+ cnt += gaudi2_cn_get_mac_rx_stats(cn_port, &data[cnt]);
+ cnt += __gaudi2_cn_get_mac_fec_stats(cn_port, &data[cnt]);
+ cnt += gaudi2_cn_get_mac_tx_stats(cn_port, &data[cnt]);
+
+ return cnt;
+}
+
+static int gaudi2_cn_get_err_stats(struct hbl_cn_port *cn_port, u64 *data)
+{
+ struct gaudi2_en_aux_ops *gaudi2_en_aux_ops;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct gaudi2_cn_device *gaudi2;
+ struct hbl_aux_dev *aux_dev;
+ int i = 0;
+
+ gaudi2 = hdev->asic_specific;
+ aux_dev = &hdev->en_aux_dev;
+ gaudi2_en_aux_ops = &gaudi2->en_aux_ops;
+
+ data[i++] = cn_port->cong_q_err_cnt;
+
+ if (cn_port->eth_enable && gaudi2_en_aux_ops->get_overrun_cnt)
+ data[i++] = gaudi2_en_aux_ops->get_overrun_cnt(aux_dev, cn_port->port);
+ else
+ data[i++] = 0;
+
+ return i;
+}
+
+static int gaudi2_cn_get_perf_stats(struct hbl_cn_port *cn_port, u64 *data)
+{
+ u64 lat_dividend, lat_divisor, lat_int, lat_frac;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct hbl_cn_properties *cn_prop;
+ u64 bw_dividend, bw_int, bw_frac;
+ u32 port = cn_port->port;
+
+ cn_prop = &hdev->cn_props;
+
+ /* Bandwidth calculation */
+ bw_dividend = (((u64)NIC_RREG32(NIC0_TXE0_STATS_MEAS_WIN_BYTES_MSB)) << 32) |
+ NIC_RREG32(NIC0_TXE0_STATS_MEAS_WIN_BYTES_LSB);
+
+ /* bytes to bits */
+ bw_dividend *= BITS_PER_BYTE;
+
+ bw_int = div_u64(bw_dividend, PERF_BW_WINDOW_DIV);
+ bw_frac = ((bw_dividend - PERF_BW_WINDOW_DIV * bw_int) * 10) / PERF_BW_WINDOW_DIV;
+
+ /* In case there is no traffic (BW=0), the latency will show the last measured value (when
+ * there was traffic). Therefore, we need to clear it.
+ */
+ if (bw_int == 0 && bw_frac == 0) {
+ lat_int = 0;
+ lat_frac = 0;
+ } else {
+ /* Latency calculation */
+ lat_dividend = (((u64)NIC_RREG32(NIC0_TXE0_STATS_TOT_BYTES_MSB)) << 32) |
+ NIC_RREG32(NIC0_TXE0_STATS_TOT_BYTES_LSB);
+ lat_divisor = cn_prop->clk;
+
+ lat_int = div_u64(lat_dividend, lat_divisor);
+ lat_frac = ((lat_dividend - lat_divisor * lat_int) * 10) / lat_divisor;
+ }
+
+ data[PERF_BANDWIDTH_INT] = bw_int;
+ data[PERF_BANDWIDTH_FRAC] = bw_frac;
+ data[PERF_LATENCY_INT] = lat_int;
+ data[PERF_LATENCY_FRAC] = lat_frac;
+
+ return (int)gaudi2_cn_perf_stats_len;
+}
+
+static void gaudi2_cn_get_cnts_values(struct hbl_cn_port *cn_port, u64 *data)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 cnt = 0;
+ int rc;
+
+ rc = hbl_cn_read_spmu_counters(cn_port, &data[cnt], &cnt);
+ if (rc)
+ dev_err(hdev->dev, "Failed to get SPMU counters, port %d\n", cn_port->port);
+
+ cnt += gaudi2_cn_get_mac_stats(cn_port, &data[cnt]);
+ cnt += gaudi2_cn_get_err_stats(cn_port, &data[cnt]);
+ cnt += gaudi2_cn_get_perf_stats(cn_port, &data[cnt]);
+}
+
+static void gaudi2_cn_reset_mac_stats(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+
+ NIC_MACRO_WREG32(NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONFIG,
+ BIT(NIC0_MAC_GLOB_STAT_CONTROL_REG_STATN_CONFIG_F_RESET_SHIFT));
+}
+
+void gaudi2_cn_get_mac_fec_stats(struct hbl_cn_port *cn_port, u64 *data)
+{
+ __gaudi2_cn_get_mac_fec_stats(cn_port, data);
+}
+
+/* HW bug: QP stuck in limited state in case there is a race between timeout and receive ACK.
+ * Description: When timeout occurs QPC resets NTS to ONA. If an ACK arives to the RX, the RX reads
+ * the QPC and timeout occurs after the read response to the RX and before the RX update indication,
+ * the NTS will rollback to the ONA.
+ * After the RX handles the ACK, it will do an update, and may advance the ONA ahead of the NTS.
+ * In this case the QP will go into limited state forever: NTS - ONA > congestion window
+ */
+static void __qpc_sanity_check(struct gaudi2_cn_port *gaudi2_port, u32 qpn)
+{
+ u32 ona_psn, nts_psn, in_work, bcs_psn, bcc_psn, ona_rem_pi, consumer_idx, execution_idx,
+ is_valid, port, wq_type;
+ int rc, retry_cnt_in_work = 0, retry_cnt_qpc_timeout = 0;
+ struct gaudi2_qpc_requester req_qpc = {};
+ struct qpc_mask qpc_mask = {};
+ struct hbl_cn_port *cn_port;
+ struct hbl_cn_device *hdev;
+
+ cn_port = gaudi2_port->cn_port;
+ hdev = cn_port->hdev;
+ port = cn_port->port;
+
+retry:
+ rc = gaudi2_cn_qpc_read(cn_port, (void *)&req_qpc, qpn, true);
+ if (rc) {
+ dev_err_ratelimited(hdev->dev, "Requester port %d QPC %d read failed\n", port, qpn);
+ return;
+ }
+
+ is_valid = REQ_QPC_GET_VALID(req_qpc);
+ if (!is_valid)
+ return;
+
+ /* When the timeout retry counter is non zero, an ack could potentially arrive and increase
+ * ONA, after QPC was read.
+ */
+ if (REQ_QPC_GET_TIMEOUT_RETRY_COUNT(req_qpc)) {
+ if (retry_cnt_qpc_timeout < RETRY_COUNT_QPC_SANITY) {
+ dev_dbg(hdev->dev, "QPC timeout retry count > 0, trying again #%d\n",
+ retry_cnt_qpc_timeout);
+ usleep_range(1000, 1500);
+ retry_cnt_qpc_timeout++;
+ goto retry;
+ } else {
+ dev_dbg(hdev->dev,
+ "Can't apply fix. QPC timeout retry count > 0, after %d QPC reads",
+ retry_cnt_qpc_timeout);
+ return;
+ }
+ }
+
+ in_work = REQ_QPC_GET_IN_WORK(req_qpc);
+
+ ona_psn = REQ_QPC_GET_ONA_PSN(req_qpc);
+ nts_psn = REQ_QPC_GET_NTS_PSN(req_qpc);
+
+ bcs_psn = REQ_QPC_GET_BCS_PSN(req_qpc);
+ bcc_psn = REQ_QPC_GET_BCC_PSN(req_qpc);
+
+ consumer_idx = REQ_QPC_GET_CONSUMER_IDX(req_qpc);
+ execution_idx = REQ_QPC_GET_EXECUTION_IDX(req_qpc);
+
+ ona_rem_pi = REQ_QPC_GET_OLDEST_UNACKED_REMOTE_PRODUCER_IDX(req_qpc);
+
+ wq_type = REQ_QPC_GET_WQ_TYPE(req_qpc);
+
+ /* We hit the HW bug. Unacknowledged PSN can never be greater than next
+ * PSN to be sent out.
+ */
+ if (NIC_IS_PSN_CYCLIC_BIG(ona_psn, nts_psn)) {
+ struct hbl_cn_eqe eqe;
+
+ dev_dbg(hdev->dev,
+ "ona_psn(%d) nts_psn(%d), bcc_psn(%d) bcs_psn(%d), consumer_idx(%d) execution_idx(%d). Retry_cnt %d\n",
+ ona_psn, nts_psn, bcc_psn, bcs_psn, consumer_idx, execution_idx,
+ retry_cnt_in_work);
+
+ /* Wait till HW stops working on QPC. */
+ if (in_work && retry_cnt_in_work < RETRY_COUNT_QPC_SANITY) {
+ usleep_range(1000, 1500);
+ retry_cnt_in_work++;
+ goto retry;
+ }
+
+ dev_dbg(hdev->dev, "Port %d QP %d in limited state. Applying fix.\n", port, qpn);
+
+ /* Force update QPC fields. */
+
+ REQ_QPC_SET_NTS_PSN(qpc_mask, 0xffffff);
+ REQ_QPC_SET_BCS_PSN(qpc_mask, 0xffffff);
+ REQ_QPC_SET_EXECUTION_IDX(qpc_mask, 0x3fffff);
+ if (wq_type == QPC_REQ_WQ_TYPE_WRITE)
+ REQ_QPC_SET_REMOTE_PRODUCER_IDX(qpc_mask, 0x3fffff);
+
+ REQ_QPC_SET_NTS_PSN(req_qpc, ona_psn);
+ REQ_QPC_SET_BCS_PSN(req_qpc, bcc_psn);
+ REQ_QPC_SET_EXECUTION_IDX(req_qpc, consumer_idx);
+ if (wq_type == QPC_REQ_WQ_TYPE_WRITE)
+ REQ_QPC_SET_REMOTE_PRODUCER_IDX(req_qpc, ona_rem_pi);
+
+ rc = gaudi2_cn_qpc_write_masked(cn_port, (void *)&req_qpc, &qpc_mask, qpn, true,
+ true);
+ if (rc)
+ dev_err(hdev->dev, "Requester port %d QPC %d write failed\n", port, qpn);
+
+ eqe.data[0] = EQE_HEADER(true, EQE_QP_ALIGN_COUNTERS);
+ eqe.data[1] = qpn;
+
+ rc = hbl_cn_eq_dispatcher_enqueue(cn_port, &eqe);
+ if (rc)
+ dev_err(hdev->dev, "port %d QPC %d failed dispatching EQ event %d\n", port,
+ qpn, EQE_QP_ALIGN_COUNTERS);
+ }
+}
+
+/* We sanitize one QP at a time since it's high latency operation,
+ * too heavy to do it in one shot. We mitigate this via interleaving
+ * with thread scheduling.
+ */
+static void gaudi2_qp_sanity_work(struct work_struct *work)
+{
+ struct gaudi2_cn_port *gaudi2_port = container_of(work, struct gaudi2_cn_port,
+ qp_sanity_work.work);
+ struct hbl_cn_port *cn_port = gaudi2_port->cn_port;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ unsigned long qp_id = 0;
+ u32 timeout_cnt, port;
+ struct hbl_cn_qp *qp;
+
+ port = cn_port->port;
+ timeout_cnt = NIC_RREG32(NIC0_QPC0_NUM_TIMEOUTS);
+
+ if (gaudi2_port->qp_timeout_cnt == timeout_cnt)
+ goto done;
+
+ gaudi2_port->qp_timeout_cnt = timeout_cnt;
+
+ mutex_lock(&gaudi2_port->cfg_lock);
+ xa_for_each(&cn_port->qp_ids, qp_id, qp)
+ if (qp && qp->is_req)
+ __qpc_sanity_check(gaudi2_port, qp_id);
+ mutex_unlock(&gaudi2_port->cfg_lock);
+
+done:
+ queue_delayed_work(gaudi2_port->qp_sanity_wq, &gaudi2_port->qp_sanity_work,
+ msecs_to_jiffies(QPC_SANITY_CHECK_INTERVAL_MS));
+}
+
+static int gaudi2_qp_sanity_init(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_port *cn_port = gaudi2_port->cn_port;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 port = cn_port->port;
+ char wq_name[30] = {0};
+
+ /* The qp sanity work is relevant only for external ports */
+ if (!cn_port->eth_enable)
+ return 0;
+
+ snprintf(wq_name, sizeof(wq_name) - 1, "hbl%u-cn%d-qp-sanity", hdev->id, port);
+
+ gaudi2_port->qp_sanity_wq = alloc_ordered_workqueue(wq_name, 0);
+ if (!gaudi2_port->qp_sanity_wq) {
+ dev_err(hdev->dev, "Failed to create QP sanity WQ, port: %d\n", port);
+ return -ENOMEM;
+ }
+
+ INIT_DELAYED_WORK(&gaudi2_port->qp_sanity_work, gaudi2_qp_sanity_work);
+ queue_delayed_work(gaudi2_port->qp_sanity_wq, &gaudi2_port->qp_sanity_work,
+ msecs_to_jiffies(QPC_SANITY_CHECK_INTERVAL_MS));
+
+ return 0;
+}
+
+static void gaudi2_qp_sanity_fini(struct gaudi2_cn_port *gaudi2_port)
+{
+ if (!gaudi2_port->qp_sanity_wq)
+ return;
+
+ cancel_delayed_work_sync(&gaudi2_port->qp_sanity_work);
+ destroy_workqueue(gaudi2_port->qp_sanity_wq);
+}
+
+static void gaudi2_cn_user_ccq_set(struct hbl_cn_port *cn_port, u64 ccq_device_addr,
+ u64 pi_device_addr, u32 num_of_entries, u32 *ccqn)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+
+ WARN_ON_CACHE_UNALIGNED(ccq_device_addr);
+ WARN_ON_CACHE_UNALIGNED(pi_device_addr);
+
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_BASE_ADDR_63_32, upper_32_bits(ccq_device_addr));
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_BASE_ADDR_31_7, ((ccq_device_addr >> 7) & 0x1FFFFFF));
+
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_PI_ADDR_63_32, upper_32_bits(pi_device_addr));
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_PI_ADDR_31_7, ((pi_device_addr >> 7) & 0x1FFFFFF));
+
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_WRITE_INDEX, 0);
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_PRODUCER_INDEX, 0);
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_CONSUMER_INDEX, 0);
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CB, 0);
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_LOG_SIZE, ilog2(num_of_entries));
+
+ /* set enable + update-pi
+ * set overrun-en to allow overrun of ci since a HW bug exist
+ * in Gaudi2 which prevents updating ci.
+ */
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_CFG, NIC0_QPC0_CONG_QUE_CFG_ENABLE_MASK |
+ NIC0_QPC0_CONG_QUE_CFG_OVERRUN_EN_MASK |
+ NIC0_QPC0_CONG_QUE_CFG_WRITE_PI_EN_MASK);
+
+ /* gaudi2 has only 1 CCQ. Therefore, set 0 as ccqn. */
+ *ccqn = 0;
+}
+
+static void gaudi2_cn_user_ccq_unset(struct hbl_cn_port *cn_port, u32 *ccqn)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_CFG, 0);
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_PI_ADDR_63_32, 0);
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_PI_ADDR_31_7, 0);
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_BASE_ADDR_63_32, 0);
+ NIC_WREG32(NIC0_QPC0_CONG_QUE_BASE_ADDR_31_7, 0);
+
+ /* gaudi2 has only 1 CCQ. Therefore, set 0 as ccqn. */
+ *ccqn = 0;
+}
+
+static void gaudi2_cn_get_spmu_data(struct hbl_cn_port *cn_port, struct hbl_cn_cpucp_status *status)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u64 spmu_data[NIC_SPMU_STATS_LEN_MAX];
+ u32 port = cn_port->port, ignore;
+ int rc;
+
+ memset(spmu_data, 0, sizeof(spmu_data));
+
+ rc = hbl_cn_read_spmu_counters(cn_port, spmu_data, &ignore);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to get SPMU counters, port %d, %d\n", port, rc);
+ return;
+ }
+
+ status->bad_format_cnt = 0;
+ status->responder_out_of_sequence_psn_cnt = spmu_data[3];
+}
+
+static void gaudi2_cn_get_fec_status(struct hbl_cn_port *cn_port,
+ struct hbl_cn_cpucp_status *status)
+{
+ u64 fec_data[FEC_STAT_LAST];
+
+ memset(fec_data, 0, sizeof(fec_data));
+
+ gaudi2_cn_get_mac_fec_stats(cn_port, fec_data);
+
+ status->correctable_err_cnt = fec_data[FEC_CW_CORRECTED_ACCUM];
+ status->uncorrectable_err_cnt = fec_data[FEC_CW_UNCORRECTED_ACCUM];
+ status->pre_fec_ser.integer = fec_data[FEC_PRE_FEC_SER_INT];
+ status->pre_fec_ser.exp = fec_data[FEC_PRE_FEC_SER_EXP];
+ status->post_fec_ser.integer = fec_data[FEC_POST_FEC_SER_INT];
+ status->post_fec_ser.exp = fec_data[FEC_POST_FEC_SER_EXP];
+}
+
+static void gaudi2_cn_get_perf_status(struct hbl_cn_port *cn_port,
+ struct hbl_cn_cpucp_status *status)
+{
+ u64 perf_data[PERF_STAT_LAST];
+
+ memset(perf_data, 0, sizeof(perf_data));
+
+ gaudi2_cn_get_perf_stats(cn_port, perf_data);
+
+ status->bandwidth.integer = perf_data[PERF_BANDWIDTH_INT];
+ status->bandwidth.frac = perf_data[PERF_BANDWIDTH_FRAC];
+ status->lat.integer = perf_data[PERF_LATENCY_INT];
+ status->lat.frac = perf_data[PERF_LATENCY_FRAC];
+}
+
+static u32 gaudi2_cn_get_timeout_retransmission_cnt(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+
+ return NIC_RREG32(NIC0_QPC0_NUM_TIMEOUTS);
+}
+
+static u32 gaudi2_cn_get_high_ber_cnt(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+
+ if (port & 1)
+ return NIC_RREG32(NIC0_MAC_CH2_MAC_PCS_BER_HIGH_ORDER_CNT);
+ else
+ return NIC_RREG32(NIC0_MAC_CH0_MAC_PCS_BER_HIGH_ORDER_CNT);
+}
+
+static void gaudi2_cn_get_status(struct hbl_cn_port *cn_port, struct hbl_cn_cpucp_status *status)
+{
+ u32 timeout_retransmission_cnt, high_ber_cnt;
+
+ gaudi2_cn_get_spmu_data(cn_port, status);
+ gaudi2_cn_get_fec_status(cn_port, status);
+ gaudi2_cn_get_perf_status(cn_port, status);
+
+ timeout_retransmission_cnt = gaudi2_cn_get_timeout_retransmission_cnt(cn_port);
+ high_ber_cnt = gaudi2_cn_get_high_ber_cnt(cn_port);
+
+ status->timeout_retransmission_cnt = timeout_retransmission_cnt;
+ status->high_ber_cnt = high_ber_cnt;
+}
+
+static void gaudi2_cn_cfg_lock(struct hbl_cn_port *cn_port)
+ __acquires(&gaudi2_port->cfg_lock)
+{
+ struct gaudi2_cn_port *gaudi2_port = cn_port->cn_specific;
+
+ mutex_lock(&gaudi2_port->cfg_lock);
+}
+
+static void gaudi2_cn_cfg_unlock(struct hbl_cn_port *cn_port)
+ __releases(&gaudi2_port->cfg_lock)
+{
+ struct gaudi2_cn_port *gaudi2_port = cn_port->cn_specific;
+
+ mutex_unlock(&gaudi2_port->cfg_lock);
+}
+
+static bool gaudi2_cn_cfg_is_locked(struct hbl_cn_port *cn_port)
+{
+ struct gaudi2_cn_port *gaudi2_port = cn_port->cn_specific;
+
+ return mutex_is_locked(&gaudi2_port->cfg_lock);
+}
+
+static u32 gaudi2_cn_get_max_msg_sz(struct hbl_cn_device *hdev)
+{
+ return SZ_1G;
+}
+
+static void gaudi2_cn_app_params_clear(struct hbl_cn_device *hdev)
+{
+}
+
+static void gaudi2_cn_set_port_status(struct hbl_cn_port *cn_port, bool up)
+{
+ cn_port->link_eqe.data[2] = !!up;
+}
+
+static void gaudi2_cn_adaptive_tmr_reset(struct hbl_cn_qp *qp)
+{
+ struct hbl_cn_port *cn_port = qp->cn_port;
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct gaudi2_qpc_requester req_qpc;
+ struct hbl_cn_device *hdev;
+ u64 retry_count;
+ u8 user_gran;
+ u32 rc;
+
+ hdev = cn_port->hdev;
+ user_gran = qp->timeout_granularity - NIC_ADAPTIVE_TIMEOUT_RANGE / 2;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ port_funcs->cfg_lock(cn_port);
+ rc = gaudi2_cn_qpc_read(cn_port, &req_qpc, qp->qp_id, true);
+
+ if (rc)
+ goto out;
+
+ retry_count = REQ_QPC_GET_TIMEOUT_RETRY_COUNT(req_qpc);
+
+ if (!retry_count) {
+ if (qp->timeout_curr != user_gran)
+ qp->timeout_curr = user_gran;
+ } else if (qp->timeout_curr == user_gran) {
+ dev_err(hdev->dev, "Retry count is %lld, but current gran is already reset\n",
+ retry_count);
+ } else if (!REQ_QPC_GET_ERROR(req_qpc)) {
+ queue_delayed_work(cn_port->qp_wq, &qp->adaptive_tmr_reset,
+ msecs_to_jiffies(5));
+ }
+
+out:
+ port_funcs->cfg_unlock(cn_port);
+}
+
+static int gaudi2_cn_send_cpucp_packet(struct hbl_cn_port *cn_port, enum cpucp_packet_id packet_id,
+ int val)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct cpucp_packet pkt;
+ u32 port;
+ int rc;
+
+ port = cn_port->port;
+
+ memset(&pkt, 0, sizeof(pkt));
+ pkt.ctl = cpu_to_le32(packet_id << CPUCP_PKT_CTL_OPCODE_SHIFT);
+ pkt.value = cpu_to_le64(val);
+ pkt.macro_index = cpu_to_le32(port);
+
+ rc = gaudi2_cn_send_cpu_message(hdev, (u32 *)&pkt, sizeof(pkt), 0, NULL);
+ if (rc)
+ dev_err(hdev->dev,
+ "Failed to send cpucp packet, port %d packet id %d, val %d, error %d\n",
+ port, packet_id, val, rc);
+
+ return rc;
+}
+
+static void gaudi2_cn_spmu_get_stats_info(struct hbl_cn_port *cn_port, struct hbl_cn_stat **stats,
+ u32 *n_stats)
+{
+ struct gaudi2_cn_aux_ops *gaudi2_aux_ops;
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = cn_port->hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ gaudi2_aux_ops = aux_ops->asic_ops;
+
+ gaudi2_aux_ops->spmu_get_stats_info(aux_dev, cn_port->port, stats, n_stats);
+}
+
+static int gaudi2_cn_spmu_config(struct hbl_cn_port *cn_port, u32 num_event_types,
+ u32 event_types[], bool enable)
+{
+ struct gaudi2_cn_aux_ops *gaudi2_aux_ops;
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = cn_port->hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ gaudi2_aux_ops = aux_ops->asic_ops;
+
+ return gaudi2_aux_ops->spmu_config(aux_dev, cn_port->port, num_event_types, event_types,
+ enable);
+}
+
+static int gaudi2_cn_spmu_sample(struct hbl_cn_port *cn_port, u32 num_out_data, u64 out_data[])
+{
+ struct gaudi2_cn_aux_ops *gaudi2_aux_ops;
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = cn_port->hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ gaudi2_aux_ops = aux_ops->asic_ops;
+
+ return gaudi2_aux_ops->spmu_sample(aux_dev, cn_port->port, num_out_data, out_data);
+}
+
+static void gaudi2_cn_post_send_status(struct hbl_cn_port *cn_port)
+{
+ struct gaudi2_cn_aux_ops *gaudi2_aux_ops;
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = cn_port->hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ gaudi2_aux_ops = aux_ops->asic_ops;
+
+ gaudi2_aux_ops->post_send_status(aux_dev, cn_port->port);
+}
+
+static int gaudi2_cn_inject_rx_err(struct hbl_cn_device *hdev, u8 drop_percent)
+{
+ /* NoOps */
+ return 0;
+}
+
+static bool gaudi2_cn_is_encap_supported(struct hbl_cn_device *hdev,
+ struct hbl_cni_user_encap_set_in *in)
+{
+ if (in->encap_type != HBL_CNI_ENCAP_OVER_UDP) {
+ dev_dbg(hdev->dev, "Encap type %u is not supported\n", in->encap_type);
+ return false;
+ }
+
+ if (in->tnl_hdr_size != NIC_MAX_TNL_HDR_SIZE) {
+ dev_dbg(hdev->dev, "Encap hdr-size must be %d\n", NIC_MAX_TNL_HDR_SIZE);
+ return false;
+ }
+
+ return true;
+}
+
+static int gaudi2_cn_set_static_properties(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_properties *cn_prop = &hdev->cn_props;
+ struct hbl_cn_aux_data *cn_aux_data;
+ struct hbl_aux_dev *cn_aux_dev;
+
+ cn_aux_dev = hdev->cn_aux_dev;
+ cn_aux_data = cn_aux_dev->aux_data;
+
+ cn_prop->max_num_of_ports = NIC_NUMBER_OF_PORTS;
+ cn_prop->macro_cfg_size = cn_aux_data->macro_cfg_size;
+ cn_prop->txs_base_size = TXS_TOTAL_PORT_SIZE;
+ cn_prop->tmr_base_size = TMR_TOTAL_MACRO_SIZE;
+ cn_prop->req_qpc_base_size = REQ_QPC_TOTAL_PORT_SIZE;
+ cn_prop->res_qpc_base_size = RES_QPC_TOTAL_PORT_SIZE;
+ cn_prop->clk = cn_aux_data->clk;
+
+ return 0;
+}
+
+static int gaudi2_cn_set_dram_properties(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_properties *cn_prop = &hdev->cn_props;
+ struct hbl_cn_aux_data *cn_aux_data;
+ struct hbl_aux_dev *cn_aux_dev;
+ u64 nic_drv_addr, nic_drv_size;
+
+ cn_aux_dev = hdev->cn_aux_dev;
+ cn_aux_data = cn_aux_dev->aux_data;
+ nic_drv_addr = cn_aux_data->nic_drv_addr;
+ nic_drv_size = cn_aux_data->nic_drv_size;
+
+ cn_prop->nic_drv_addr = nic_drv_addr;
+ cn_prop->nic_drv_base_addr = NIC_DRV_BASE_ADDR(nic_drv_addr);
+ cn_prop->nic_drv_end_addr = NIC_DRV_END_ADDR(nic_drv_addr, nic_drv_size);
+ cn_prop->wq_base_addr = WQ_BASE_ADDR(nic_drv_addr);
+ cn_prop->txs_base_addr = TXS_BASE_ADDR(nic_drv_addr);
+ cn_prop->tmr_base_addr = TMR_BASE_ADDR(nic_drv_addr);
+ cn_prop->req_qpc_base_addr = REQ_QPC_BASE_ADDR(nic_drv_addr);
+ cn_prop->res_qpc_base_addr = RES_QPC_BASE_ADDR(nic_drv_addr);
+ cn_prop->nic_drv_size = nic_drv_size;
+ cn_prop->wq_base_size = WQ_BASE_SIZE(nic_drv_addr, nic_drv_size);
+
+ return 0;
+}
+
+static void gaudi2_cn_late_init(struct hbl_cn_device *hdev)
+{
+ struct gaudi2_cn_aux_ops *gaudi2_cn_aux_ops;
+ struct hbl_cn_aux_ops *cn_aux_ops;
+
+ cn_aux_ops = hdev->cn_aux_dev->aux_ops;
+ gaudi2_cn_aux_ops = cn_aux_ops->asic_ops;
+
+ /* compute2cn */
+ gaudi2_cn_aux_ops->reset_prepare = gaudi2_cn_compute_reset_prepare;
+ gaudi2_cn_aux_ops->reset_late_init = gaudi2_cn_compute_reset_late_init;
+ gaudi2_cn_aux_ops->sw_err_event_handler = gaudi2_cn_sw_err_event;
+ gaudi2_cn_aux_ops->axi_error_response_event_handler = gaudi2_cn_axi_error_response_event;
+ gaudi2_cn_aux_ops->ports_stop_prepare = hbl_cn_hard_reset_prepare;
+ gaudi2_cn_aux_ops->send_port_cpucp_status = hbl_cn_send_port_cpucp_status;
+}
+
+static void gaudi2_cn_late_fini(struct hbl_cn_device *hdev)
+{
+ struct gaudi2_cn_aux_ops *gaudi2_cn_aux_ops;
+ struct hbl_cn_aux_ops *cn_aux_ops;
+
+ cn_aux_ops = hdev->cn_aux_dev->aux_ops;
+ gaudi2_cn_aux_ops = cn_aux_ops->asic_ops;
+
+ /* compute2cn */
+ gaudi2_cn_aux_ops->reset_prepare = NULL;
+ gaudi2_cn_aux_ops->reset_late_init = NULL;
+ gaudi2_cn_aux_ops->sw_err_event_handler = NULL;
+ gaudi2_cn_aux_ops->axi_error_response_event_handler = NULL;
+ gaudi2_cn_aux_ops->ports_stop_prepare = NULL;
+ gaudi2_cn_aux_ops->send_port_cpucp_status = NULL;
+}
+
+static int gaudi2_cn_get_hw_block_handle(struct hbl_cn_device *hdev, u64 address, u64 *handle)
+{
+ hbl_cn_get_self_hw_block_handle(hdev, address, handle);
+
+ return 0;
+}
+
+static int gaudi2_cn_get_hw_block_addr(struct hbl_cn_device *hdev, u64 handle, u64 *addr, u64 *size)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ u32 reg;
+ int rc;
+
+ *size = HBL_CN_BLOCK_SIZE;
+ reg = hbl_cn_hw_block_handle_to_addr32(hdev, handle) - lower_32_bits(gaudi2->cfg_base);
+
+ rc = hbl_cn_get_reg_pcie_addr(hdev, CFG_BAR_ID, reg, addr);
+ if (rc)
+ dev_err(hdev->dev, "Failed to get hw block address for register 0x%x", reg);
+
+ return rc;
+}
+
+static struct hbl_cn_asic_port_funcs gaudi2_cn_port_funcs = {
+ .port_hw_init = gaudi2_cn_port_hw_init,
+ .port_hw_fini = gaudi2_cn_port_hw_fini,
+ .phy_port_init = gaudi2_cn_phy_port_init,
+ .phy_port_start_stop = gaudi2_cn_phy_port_start_stop,
+ .phy_port_power_up = gaudi2_cn_phy_port_power_up,
+ .phy_port_reconfig = gaudi2_cn_phy_port_reconfig,
+ .phy_port_fini = gaudi2_cn_phy_port_fini,
+ .phy_link_status_work = gaudi2_cn_phy_link_status_work,
+ .update_qp_mtu = gaudi2_cn_update_qp_mtu,
+ .user_wq_arr_unset = gaudi2_user_wq_arr_unset,
+ .get_cq_id_range = gaudi2_get_cq_id_range,
+ .user_cq_set = gaudi2_user_cq_set,
+ .user_cq_unset = gaudi2_user_cq_unset,
+ .user_cq_destroy = gaudi2_user_cq_destroy,
+ .get_cnts_num = gaudi2_cn_get_cnts_num,
+ .get_cnts_names = gaudi2_cn_get_cnts_names,
+ .get_cnts_values = gaudi2_cn_get_cnts_values,
+ .port_sw_init = gaudi2_cn_port_sw_init,
+ .port_sw_fini = gaudi2_cn_port_sw_fini,
+ .register_qp = gaudi2_register_qp,
+ .unregister_qp = gaudi2_unregister_qp,
+ .get_qp_id_range = gaudi2_get_qp_id_range,
+ .eq_poll = gaudi2_eq_poll,
+ .eq_dispatcher_select_dq = gaudi2_cn_eq_dispatcher_select_dq,
+ .get_db_fifo_id_range = gaudi2_get_db_fifo_id_range,
+ .get_db_fifo_hw_id_range = gaudi2_get_db_fifo_hw_id_range,
+ .db_fifo_set = gaudi2_db_fifo_set,
+ .db_fifo_unset = gaudi2_db_fifo_unset,
+ .get_db_fifo_umr = gaudi2_cn_get_db_fifo_umr,
+ .get_db_fifo_modes_mask = gaudi2_get_db_fifo_modes_mask,
+ .db_fifo_allocate = gaudi2_db_fifo_allocate,
+ .db_fifo_free = gaudi2_db_fifo_free,
+ .set_pfc = gaudi2_cn_set_pfc,
+ .get_encap_id_range = gaudi2_get_encap_id_range,
+ .encap_set = gaudi2_encap_set,
+ .encap_unset = gaudi2_encap_unset,
+ .set_ip_addr_encap = gaudi2_default_encap_set,
+ .qpc_write = gaudi2_cn_qpc_write,
+ .qpc_invalidate = gaudi2_cn_qpc_invalidate,
+ .qpc_query = gaudi2_cn_qpc_query,
+ .qpc_clear = gaudi2_cn_qpc_clear,
+ .user_ccq_set = gaudi2_cn_user_ccq_set,
+ .user_ccq_unset = gaudi2_cn_user_ccq_unset,
+ .reset_mac_stats = gaudi2_cn_reset_mac_stats,
+ .collect_fec_stats = gaudi2_cn_debugfs_collect_fec_stats,
+ .disable_wqe_index_checker = gaudi2_cn_disable_wqe_index_checker,
+ .get_status = gaudi2_cn_get_status,
+ .cfg_lock = gaudi2_cn_cfg_lock,
+ .cfg_unlock = gaudi2_cn_cfg_unlock,
+ .cfg_is_locked = gaudi2_cn_cfg_is_locked,
+ .qp_pre_destroy = gaudi2_cn_qp_pre_destroy,
+ .qp_post_destroy = gaudi2_cn_qp_post_destroy,
+ .set_port_status = gaudi2_cn_set_port_status,
+ .send_cpucp_packet = gaudi2_cn_send_cpucp_packet,
+ .adaptive_tmr_reset = gaudi2_cn_adaptive_tmr_reset,
+ .spmu_get_stats_info = gaudi2_cn_spmu_get_stats_info,
+ .spmu_config = gaudi2_cn_spmu_config,
+ .spmu_sample = gaudi2_cn_spmu_sample,
+ .post_send_status = gaudi2_cn_post_send_status,
+};
+
+static struct hbl_cn_asic_funcs gaudi2_cn_funcs = {
+ .core_init = gaudi2_cn_core_init,
+ .core_fini = gaudi2_cn_core_fini,
+ .set_req_qp_ctx = gaudi2_set_req_qp_ctx,
+ .set_res_qp_ctx = gaudi2_set_res_qp_ctx,
+ .user_wq_arr_set = gaudi2_user_wq_arr_set,
+ .user_set_app_params = gaudi2_user_set_app_params,
+ .user_get_app_params = gaudi2_user_get_app_params,
+ .phy_reset_macro = gaudi2_cn_phy_reset_macro,
+ .phy_get_crc = gaudi2_cn_phy_get_crc,
+ .get_phy_fw_name = gaudi2_cn_phy_get_fw_name,
+ .phy_fw_load_all = gaudi2_cn_phy_fw_load_all,
+ .get_default_port_speed = gaudi2_cn_get_default_port_speed,
+ .pre_sw_init = gaudi2_cn_pre_sw_init,
+ .sw_init = gaudi2_cn_sw_init,
+ .sw_fini = gaudi2_cn_sw_fini,
+ .macro_sw_init = gaudi2_cn_macro_sw_init,
+ .macro_sw_fini = gaudi2_cn_macro_sw_fini,
+ .kernel_ctx_init = gaudi2_cn_kernel_ctx_init,
+ .kernel_ctx_fini = gaudi2_cn_kernel_ctx_fini,
+ .ctx_init = gaudi2_cn_ctx_init,
+ .ctx_fini = gaudi2_cn_ctx_fini,
+ .qp_read = gaudi2_cn_debugfs_qp_read,
+ .wqe_read = gaudi2_cn_debugfs_wqe_read,
+ .set_en_data = gaudi2_cn_set_en_data,
+ .request_irqs = gaudi2_cn_eq_request_irqs,
+ .synchronize_irqs = gaudi2_cn_eq_sync_irqs,
+ .free_irqs = gaudi2_cn_eq_free_irqs,
+ .phy_dump_serdes_params = gaudi2_cn_phy_dump_serdes_params,
+ .get_max_msg_sz = gaudi2_cn_get_max_msg_sz,
+ .qp_syndrome_to_str = gaudi2_cn_qp_err_syndrome_to_str,
+ .app_params_clear = gaudi2_cn_app_params_clear,
+ .inject_rx_err = gaudi2_cn_inject_rx_err,
+ .is_encap_supported = gaudi2_cn_is_encap_supported,
+ .set_static_properties = gaudi2_cn_set_static_properties,
+ .set_dram_properties = gaudi2_cn_set_dram_properties,
+ .late_init = gaudi2_cn_late_init,
+ .late_fini = gaudi2_cn_late_fini,
+ .get_hw_block_handle = gaudi2_cn_get_hw_block_handle,
+ .get_hw_block_addr = gaudi2_cn_get_hw_block_addr,
+ .dma_alloc_coherent = gaudi2_cn_dma_alloc_coherent,
+ .dma_free_coherent = gaudi2_cn_dma_free_coherent,
+ .dma_pool_zalloc = gaudi2_cn_dma_pool_zalloc,
+ .dma_pool_free = gaudi2_cn_dma_pool_free,
+ .send_cpu_message = gaudi2_cn_send_cpu_message,
+ .ports_cancel_status_work = hbl_cn_ports_cancel_status_work,
+ .port_funcs = &gaudi2_cn_port_funcs,
+};
+
+void gaudi2_cn_set_asic_funcs(struct hbl_cn_device *hdev)
+{
+ hdev->asic_funcs = &gaudi2_cn_funcs;
+}
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.h b/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.h
new file mode 100644
index 000000000000..58a0d4e86d47
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.h
@@ -0,0 +1,427 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#ifndef GAUDI2_CN_H_
+#define GAUDI2_CN_H_
+
+#include <linux/net/intel/gaudi2.h>
+
+#include "../common/hbl_cn.h"
+#include "asic_reg/gaudi2_regs.h"
+
+#define NIC_NUMBER_OF_MACROS 12
+#define NIC_NUMBER_OF_ENGINES (NIC_NUMBER_OF_MACROS * 2)
+#define NIC_MAX_NUMBER_OF_PORTS (NIC_NUMBER_OF_ENGINES * 2)
+#define NIC_MAX_FIFO_RINGS 32
+#define NIC_MAC_NUM_OF_LANES 4
+#define NIC_MAC_LANES_START 0
+#define NIC_NUMBER_OF_EQS 1
+#define DEVICE_CACHE_LINE_SIZE 128
+#define NIC_SEND_WQE_SIZE 32
+#define NIC_SEND_WQE_SIZE_MULTI_STRIDE 64
+#define NIC_RECV_WQE_SIZE 16
+#define DB_FIFO_ELEMENT_SIZE 8
+/* 4 entries of 32 bit each i.e. 16 bytes */
+#define NIC_RAW_EQE_SIZE 16
+#define NIC_MAX_CCQS_NUM 1
+#define NIC_HW_MAX_QP_NUM BIT(24) /* 16M (per port) */
+
+#define NIC_NUMBER_OF_PORTS NIC_NUMBER_OF_ENGINES
+#define NIC_MAX_NUM_OF_LANES (NIC_NUMBER_OF_MACROS * NIC_MAC_LANES)
+#define NIC_CQS_NUM 2 /* For Raw and RDMA */
+#define NIC_EQ_ERR_SYNDROME 0
+#define NIC_QP_ERR_RETRY_SYNDROME 0x40
+#define NIC_MAX_QP_ERR_SYNDROMES 0x100
+#define GAUDI2_NIC_MAX_CQS_NUM 16
+
+/* make sure generic max CCQs number is always larger than h/w specific max CCQs number */
+static_assert(NIC_MAX_CCQS_NUM <= NIC_DRV_MAX_CCQS_NUM);
+
+#define GAUDI2_NIC_NUM_DB_FIFOS 32
+
+/* writing to the device memory-mapped dram using the writel or writeb commands (for example) is
+ * subject to the write-combined rules, meaning that writes temporarily stored in a buffer and are
+ * released together later in burst mode towards the device.
+ * Due to the high latencies in the PLDM such writes take a lot of time which may lead to system
+ * hangs. The burst issue gets more severe if ports are opened in parallel as each port accesses
+ * this memory, therefore we limit the amount of pending writes by inserting reads every several
+ * writes which causes the pending writes to be flushed to the device.
+ */
+#define NIC_MAX_COMBINED_WRITES 0x2000
+
+#define NIC_MAX_RC_MTU SZ_8K
+
+#define UDP_HDR_SIZE 8
+
+/* This is the max frame length the H/W supports (Tx/Rx) */
+#define NIC_MAX_RDMA_HDRS 128
+#define NIC_MAX_TNL_HDR_SIZE 32 /* Bytes */
+#define NIC_MAX_TNL_HDRS (NIC_MAX_TNL_HDR_SIZE + UDP_HDR_SIZE)
+#define NIC_MAX_FRM_LEN (NIC_MAX_RC_MTU + NIC_MAX_RDMA_HDRS)
+#define NIC_MAC_MAX_FRM_LEN (NIC_MAX_FRM_LEN + HBL_EN_MAX_HEADERS_SZ + NIC_MAX_TNL_HDRS)
+#define NIC_RAW_MIN_MTU (SZ_1K - HBL_EN_MAX_HEADERS_SZ)
+#define NIC_RAW_MAX_MTU (NIC_MAX_RC_MTU - HBL_EN_MAX_HEADERS_SZ)
+
+/* This is the size of an element size in the RAW buffer - note that it is different than
+ * NIC_MAX_FRM_LEN, because it has to be power of 2.
+ */
+#define NIC_RAW_ELEM_SIZE (2 * NIC_MAX_RC_MTU)
+
+#define NIC_RX_RING_PKT_NUM BIT(8)
+
+#define NIC_MIN_CONN_ID 1
+#define NIC_MAX_CONN_ID (BIT(13) - 1) /* 8K QPs */
+
+#define NIC_MAX_QP_NUM (NIC_MAX_CONN_ID + 1)
+
+/* Number of available QPs must not exceed NIC_HW_MAX_QP_NUM */
+static_assert(NIC_MAX_QP_NUM <= NIC_HW_MAX_QP_NUM);
+
+/* Allocate an extra QP to be used as dummy QP. */
+#define REQ_QPC_TOTAL_PORT_SIZE ((NIC_MAX_QP_NUM + 1) * sizeof(struct gaudi2_qpc_requester))
+#define RES_QPC_TOTAL_PORT_SIZE ALIGN((NIC_MAX_QP_NUM + 1) * \
+ sizeof(struct gaudi2_qpc_responder), \
+ DEVICE_CACHE_LINE_SIZE)
+
+#define TMR_ENT_SIZE 4
+#define TMR_GRANULARITY 256
+#define TMR_FSM_SIZE ALIGN(NIC_MAX_QP_NUM, DEVICE_CACHE_LINE_SIZE)
+/* each timer serves two NICs, hence multiply by 2 */
+#define TMR_FIFO_SIZE ALIGN((NIC_MAX_QP_NUM * 2 * TMR_ENT_SIZE) + \
+ DEVICE_CACHE_LINE_SIZE * TMR_GRANULARITY, \
+ DEVICE_CACHE_LINE_SIZE)
+#define TMR_FREE_NUM_ENTRIES (TMR_FIFO_SIZE / DEVICE_CACHE_LINE_SIZE)
+#define TMR_FREE_SIZE ALIGN(TMR_FREE_NUM_ENTRIES * TMR_ENT_SIZE, \
+ DEVICE_CACHE_LINE_SIZE)
+#define TMR_TOTAL_MACRO_SIZE (TMR_FSM_SIZE * 2 + TMR_FREE_SIZE + TMR_FIFO_SIZE)
+
+#define TMR_FSM0_OFFS 0
+#define TMR_FREE_OFFS (TMR_FSM0_OFFS + 2 * TMR_FSM_SIZE)
+#define TMR_FIFO_OFFS (TMR_FREE_OFFS + TMR_FREE_SIZE)
+
+#define TXS_ENT_SIZE 4
+#define TXS_GRANULARITY 256
+#define TXS_FIFO_SIZE ALIGN((NIC_MAX_QP_NUM * 2 * TXS_ENT_SIZE) + \
+ DEVICE_CACHE_LINE_SIZE * TXS_GRANULARITY, \
+ DEVICE_CACHE_LINE_SIZE)
+#define TXS_FREE_NUM_ENTRIES (TXS_FIFO_SIZE / DEVICE_CACHE_LINE_SIZE)
+#define TXS_FREE_SIZE ALIGN(TXS_FREE_NUM_ENTRIES * TXS_ENT_SIZE, \
+ DEVICE_CACHE_LINE_SIZE)
+#define TXS_TOTAL_PORT_SIZE (TXS_FREE_SIZE + TXS_FIFO_SIZE)
+
+#define TXS_FREE_OFFS 0
+#define TXS_FIFO_OFFS (TXS_FREE_OFFS + TXS_FREE_SIZE)
+
+#define TXS_NUM_PORTS NIC_MAC_LANES
+#define TXS_SCHEDQ TXS_GRANULARITY
+#define TXS_NUM_SCHEDQS TXS_SCHEDQ
+
+#define TXS_PORT_NUM_SCHEDQS (TXS_NUM_SCHEDQS / TXS_NUM_PORTS)
+#define TXS_PORT_NUM_SCHED_GRANS (TXS_PORT_NUM_SCHEDQS / HBL_EN_PFC_PRIO_NUM)
+#define TXS_PORT_RAW_SCHED_Q (TXS_PORT_NUM_SCHED_GRANS - QPC_RAW_SCHED_Q)
+#define TXS_PORT_RES_SCHED_Q (TXS_PORT_NUM_SCHED_GRANS - QPC_RES_SCHED_Q)
+#define TXS_PORT_REQ_SCHED_Q (TXS_PORT_NUM_SCHED_GRANS - QPC_REQ_SCHED_Q)
+
+#define RXB_NUM_BUFFS 2880
+#define RXB_BUFF_SIZE 128 /* size in bytes */
+#define RXB_NUM_MTU_BUFFS ((NIC_MAX_FRM_LEN / RXB_BUFF_SIZE) + 1)
+#define RXB_DROP_SMALL_TH_DEPTH 3
+#define RXB_DROP_TH_DEPTH (1 * RXB_NUM_MTU_BUFFS)
+#define RXB_XOFF_TH_DEPTH (11 * RXB_NUM_MTU_BUFFS)
+#define RXB_XON_TH_DEPTH (1 * RXB_NUM_MTU_BUFFS)
+#define RXB_NUM_STATIC_CREDITS (RXB_NUM_BUFFS / 2)
+
+#define SECTION_ALIGN_SIZE 0x100000ull
+#define NIC_DRV_BASE_ADDR(nic_drv_addr) ALIGN(nic_drv_addr, SECTION_ALIGN_SIZE)
+
+#define NIC_DRV_END_ADDR(nic_drv_addr, nic_drv_size) \
+ ALIGN(((nic_drv_addr) + (nic_drv_size)), \
+ SECTION_ALIGN_SIZE)
+
+#define REQ_QPC_BASE_ADDR NIC_DRV_BASE_ADDR
+
+#define RES_QPC_BASE_ADDR(nic_drv_addr) (REQ_QPC_BASE_ADDR(nic_drv_addr) + \
+ ALIGN(NIC_NUMBER_OF_ENGINES * REQ_QPC_TOTAL_PORT_SIZE, \
+ SECTION_ALIGN_SIZE))
+
+#define TMR_BASE_ADDR(nic_drv_addr) (RES_QPC_BASE_ADDR(nic_drv_addr) + \
+ ALIGN(NIC_NUMBER_OF_ENGINES * RES_QPC_TOTAL_PORT_SIZE, \
+ SECTION_ALIGN_SIZE))
+
+#define TXS_BASE_ADDR(nic_drv_addr) (TMR_BASE_ADDR(nic_drv_addr) + \
+ ALIGN(NIC_NUMBER_OF_MACROS * TMR_TOTAL_MACRO_SIZE, \
+ SECTION_ALIGN_SIZE))
+
+#define WQ_BASE_ADDR(nic_drv_addr) (TXS_BASE_ADDR(nic_drv_addr) + \
+ ALIGN(NIC_NUMBER_OF_ENGINES * TXS_TOTAL_PORT_SIZE, \
+ SECTION_ALIGN_SIZE))
+
+/* Unlike the other port related sizes, this size is shared between all the engines */
+#define WQ_BASE_SIZE(nic_drv_addr, nic_drv_size) \
+ ({ \
+ u64 __nic_drv_addr = (nic_drv_addr); \
+ NIC_DRV_END_ADDR(__nic_drv_addr, (nic_drv_size)) - WQ_BASE_ADDR(__nic_drv_addr); \
+ })
+
+#define WQ_BUFFER_LOG_SIZE 8
+#define WQ_BUFFER_SIZE (1 << (WQ_BUFFER_LOG_SIZE))
+#define CQE_SIZE sizeof(struct gaudi2_cqe)
+#define NIC_CQ_RAW_IDX 0
+#define NIC_CQ_RDMA_IDX 1
+#define QP_WQE_NUM_REC 128
+#define TX_WQE_NUM_IN_CLINE (DEVICE_CACHE_LINE_SIZE / NIC_SEND_WQE_SIZE_MULTI_STRIDE)
+#define RX_WQE_NUM_IN_CLINE (DEVICE_CACHE_LINE_SIZE / NIC_RECV_WQE_SIZE)
+#define RAW_QPN 0
+
+#define NIC_FIFO_DB_SIZE 64
+#define NIC_TX_BUF_SIZE QP_WQE_NUM_REC
+#define NIC_CQ_MAX_ENTRIES BIT(13)
+#define NIC_EQ_RING_NUM_REC BIT(18)
+
+/* if not equal, the size of the WQ must be considered when checking data bounds in en_tx_done */
+static_assert(NIC_TX_BUF_SIZE == QP_WQE_NUM_REC);
+
+#define NIC_TOTAL_CQ_MEM_SIZE (NIC_CQ_MAX_ENTRIES * CQE_SIZE)
+
+#define NIC_CQ_USER_MIN_ENTRIES 4
+#define NIC_CQ_USER_MAX_ENTRIES NIC_CQ_MAX_ENTRIES
+
+#define NIC_MIN_CQ_ID NIC_CQS_NUM
+#define NIC_MAX_CQ_ID (GAUDI2_NIC_MAX_CQS_NUM - 1)
+
+static_assert(NIC_CQ_RDMA_IDX < GAUDI2_NIC_MAX_CQS_NUM);
+static_assert(NIC_CQ_RAW_IDX < GAUDI2_NIC_MAX_CQS_NUM);
+
+#define USER_WQES_MIN_NUM 16
+#define USER_WQES_MAX_NUM BIT(15) /* 32K */
+
+#define NIC_RXE_AXUSER_AXUSER_CQ_OFFSET (NIC0_RXE0_AXUSER_AXUSER_CQ1_HB_ASID - \
+ NIC0_RXE0_AXUSER_AXUSER_CQ0_HB_ASID)
+
+/* Unsecure userspace doorbell fifo IDs as reported to the user, HW IDs are 0-29 */
+#define GAUDI2_MIN_DB_FIFO_ID 1
+#define GAUDI2_MAX_DB_FIFO_ID 30
+
+#define GAUDI2_DB_FIFO_SECURE_HW_ID 30
+#define GAUDI2_DB_FIFO_PRIVILEGE_HW_ID 31
+
+/* The size of the DB FIFO in bytes is constant */
+#define DB_FIFO_ENTRY_SIZE 8
+#define DB_FIFO_NUM_OF_ENTRIES 64
+#define DB_FIFO_SIZE (DB_FIFO_NUM_OF_ENTRIES * DB_FIFO_ENTRY_SIZE)
+
+/* User encapsulation IDs. There are 8 encaps and 4 decap resources available per macro.
+ * So for now let's allow the max of 2 encaps per port.
+ */
+#define GAUDI2_MIN_ENCAP_ID 0
+#define GAUDI2_MAX_ENCAP_ID 1
+
+#define QPC_GW_MASK_REG_NUM (((NIC0_QPC0_GW_MASK_31 - NIC0_QPC0_GW_MASK_0) >> 2) + 1)
+
+#define NIC_CFG_LO_SIZE (NIC0_QPC1_REQ_STATIC_CONFIG - NIC0_QPC0_REQ_STATIC_CONFIG)
+
+#define NIC_CFG_HI_SIZE (NIC0_RXE1_CONTROL - NIC0_RXE0_CONTROL)
+
+#define NIC_CFG_BASE(port, reg) \
+ ({ \
+ u32 __port = (port); \
+ u32 __reg = (reg); \
+ (u64)(NIC_MACRO_CFG_BASE(__port) + ((__reg < NIC0_RXE0_CONTROL) ? \
+ (NIC_CFG_LO_SIZE * (u64)(__port & 1)) : (NIC_CFG_HI_SIZE * (u64)(__port & 1)))); \
+ })
+
+#define NIC_RREG32(reg) \
+ ({ \
+ u32 _reg = (reg); \
+ RREG32(NIC_CFG_BASE(port, _reg) + _reg); \
+ })
+
+#define NIC_WREG32(reg, val) \
+ ({ \
+ u32 _reg = (reg); \
+ WREG32(NIC_CFG_BASE(port, _reg) + _reg, (val)); \
+ })
+
+#define NIC_RMWREG32(reg, val, mask) \
+ ({ \
+ u32 _reg = (reg); \
+ RMWREG32(NIC_CFG_BASE(port, _reg) + _reg, (val), (mask)); \
+ })
+
+#define NIC_RMWREG32_SHIFTED(reg, val, mask) \
+ ({ \
+ u32 _reg = (reg); \
+ RMWREG32_SHIFTED(NIC_CFG_BASE(port, _reg) + _reg, (val), (mask)); \
+ })
+
+#define MAC_CH_OFFSET(lane) ((NIC0_MAC_CH1_MAC_PCS_BASE - NIC0_MAC_CH0_MAC_PCS_BASE) * (lane))
+
+#define WARN_ON_CACHE_UNALIGNED(addr) WARN_ON_ONCE(!IS_ALIGNED(addr, DEVICE_CACHE_LINE_SIZE))
+
+enum gaudi2_cn_mac_fec_stats_type {
+ FEC_CW_CORRECTED_ACCUM,
+ FEC_CW_UNCORRECTED_ACCUM,
+ FEC_CW_CORRECTED,
+ FEC_CW_UNCORRECTED,
+ FEC_SYMBOL_ERR_CORRECTED_LANE_0,
+ FEC_SYMBOL_ERR_CORRECTED_LANE_1,
+ FEC_SYMBOL_ERR_CORRECTED_LANE_2,
+ FEC_SYMBOL_ERR_CORRECTED_LANE_3,
+ FEC_PRE_FEC_SER_INT,
+ FEC_PRE_FEC_SER_EXP,
+ FEC_POST_FEC_SER_INT,
+ FEC_POST_FEC_SER_EXP,
+ FEC_STAT_LAST
+};
+
+enum gaudi2_cn_perf_stats_type {
+ PERF_BANDWIDTH_INT,
+ PERF_BANDWIDTH_FRAC,
+ PERF_LATENCY_INT,
+ PERF_LATENCY_FRAC,
+ PERF_STAT_LAST
+};
+
+enum gaudi2_cn_pcs_link_state {
+ PCS_LINK_STATE_SETTLING,
+ PCS_LINK_STATE_STRESS,
+ PCS_LINK_STATE_STEADY
+};
+
+struct gaudi2_cn_port;
+
+/**
+ * struct gaudi2_cn_port - manage specific port.
+ * @hdev: habanalabs device structure.
+ * @cn_port: pointer to a common device structure.
+ * @fifo_ring: rings array for doorbell H/W interface.
+ * @wq_ring: raw work queue ring.
+ * @rx_ring: raw skb ring.
+ * @cq_ring: ring array for the completion queue of raw/rdma packets.
+ * @eq_ring: ring for the event queue.
+ * @eq_work: EQ work for processing events (e.g Tx completion).
+ * @qp_sanity_work: QPC sanity check worker.
+ * @qp_sanity_wq: QPC sanity worker thread.
+ * @cfg_lock: Serializes the port configuration.
+ * @qp_destroy_lock: protects the MAC loopback switching for QP destroy flow.
+ * @pcs_link_stady_state_ts: the timestamp to move to the pcs link steady state.
+ * @pcs_link_state: the current pcs link state.
+ * @qp_destroy_cnt: number of QPs currently under destruction.
+ * @min_qp_size: the size of the smallest QP.
+ * @db_fifo_pi: DB fifo ring producer index.
+ * @qp_timeout_cnt: count of timeouts occurred on a port operating a QP.
+ * @pcs_link_samples_per_sec: the number of times we check the pcs link in a second.
+ * @advanced: true if advanced features are supported.
+ * @adaptive_timeout_en: enable adaptive timeout feature.
+ * @qp_destroy_mac_lpbk: port in is MAC loopback due to QP destroy flow.
+ * @initial_tx_taps_cfg: first tx taps config since the last PHY power-up.
+ * @tx_taps_cfg: current tx taps config.
+ * @tx_taps_modified: flag to indicate if tx_taps were modified due to remote faults.
+ */
+struct gaudi2_cn_port {
+ struct hbl_cn_device *hdev;
+ struct hbl_cn_port *cn_port;
+ struct hbl_cn_ring fifo_ring;
+ struct hbl_cn_ring wq_ring;
+ struct hbl_cn_ring rx_ring;
+ struct hbl_cn_ring cq_rings[NIC_CQS_NUM];
+ struct hbl_cn_ring eq_ring;
+ struct delayed_work eq_work;
+ struct delayed_work qp_sanity_work;
+ struct workqueue_struct *qp_sanity_wq;
+ /* Serializes the port configuration */
+ struct mutex cfg_lock;
+ /* protects the MAC loopback switching for QP destroy flow */
+ struct mutex qp_destroy_lock;
+ ktime_t pcs_link_stady_state_ts;
+ enum gaudi2_cn_pcs_link_state pcs_link_state;
+ u32 qp_destroy_cnt;
+ u32 min_qp_size;
+ u32 db_fifo_pi;
+ u32 qp_timeout_cnt;
+ u32 pcs_link_samples_per_sec;
+ u8 advanced;
+ u8 adaptive_timeout_en;
+ u8 qp_destroy_mac_lpbk;
+ u8 initial_tx_taps_cfg;
+ u8 tx_taps_cfg;
+ u8 tx_taps_modified;
+};
+
+/**
+ * struct gaudi2_cn_device - ASIC specific manage structure.
+ * @cn_ports: array that holds all ports manage structures.
+ * @cn_macros: array that holds all macro manage structures.
+ * @en_aux_data: data to be used by the Ethernet driver.
+ * @en_aux_ops: functions for Ethernet <-> CN drivers communication.
+ * @cn_aux_ops: functions for CN <-> compute drivers communication.
+ * @setup_type: type of setup connectivity.
+ * @cfg_base: configuration space base address.
+ * @irq_num_port_base: base IRQ number for port EQ.
+ * @sob_id_base: first reserved SOB ID.
+ * @sob_inc_cfg_val: configuration value for incrementing SOB by one.
+ * @fw_security_enabled: FW security enabled.
+ * @msix_enabled: MSI-X enabled.
+ * @temporal_polling: EQ polling activity is temporal and is used only in specific cases.
+ * @flush_db_fifo: force flush DB FIFO after a write.
+ * @in_compute_reset: device is under compute reset.
+ * @mac_rs_fec_ctrl_support: Is MAC_RS_FEC_CONTROL block supported.
+ */
+struct gaudi2_cn_device {
+ struct gaudi2_cn_port cn_ports[NIC_NUMBER_OF_PORTS];
+ struct gaudi2_en_aux_data en_aux_data;
+ struct gaudi2_en_aux_ops en_aux_ops;
+ struct gaudi2_cn_aux_ops *cn_aux_ops;
+ enum gaudi2_setup_type setup_type;
+ u64 cfg_base;
+ u32 irq_num_port_base;
+ u32 sob_id_base;
+ u32 sob_inc_cfg_val;
+ u8 fw_security_enabled;
+ u8 msix_enabled;
+ u8 temporal_polling;
+ u8 flush_db_fifo;
+ u8 in_compute_reset;
+ u8 mac_rs_fec_ctrl_support;
+};
+
+int gaudi2_cn_eq_init(struct hbl_cn_device *hdev);
+void gaudi2_cn_eq_fini(struct hbl_cn_device *hdev);
+int gaudi2_cn_debugfs_qp_read(struct hbl_cn_device *hdev, struct hbl_cn_qp_info *qp_info, char *buf,
+ size_t bsize);
+int gaudi2_cn_debugfs_wqe_read(struct hbl_cn_device *hdev, char *buf, size_t bsize);
+void gaudi2_cn_debugfs_collect_fec_stats(struct hbl_cn_port *cn_port, char *buf, size_t size);
+int gaudi2_cn_eq_dispatcher_register_db(struct gaudi2_cn_port *gaudi2_cn, u32 asid, u32 dbn);
+int gaudi2_cn_eq_request_irqs(struct hbl_cn_device *hdev);
+void gaudi2_cn_eq_sync_irqs(struct hbl_cn_device *hdev);
+void gaudi2_cn_eq_free_irqs(struct hbl_cn_device *hdev);
+struct hbl_cn_ev_dq *gaudi2_cn_eq_dispatcher_select_dq(struct hbl_cn_port *cn_port,
+ const struct hbl_cn_eqe *eqe);
+char *gaudi2_cn_qp_err_syndrome_to_str(u32 syndrome);
+int gaudi2_cn_qpc_read(struct hbl_cn_port *cn_port, void *qpc, u32 qpn, bool is_req);
+int gaudi2_cn_wqe_read(struct hbl_cn_port *cn_port, void *wqe, u32 qpn, u32 wqe_idx, bool is_tx);
+void gaudi2_cn_hw_mac_loopback_cfg(struct gaudi2_cn_port *gaudi2_cn);
+int gaudi2_cn_set_info(struct hbl_cn_device *hdev, bool get_from_fw);
+int gaudi2_cn_phy_reset_macro(struct hbl_cn_macro *cn_macro);
+int gaudi2_cn_phy_init(struct hbl_cn_device *hdev);
+void gaudi2_cn_eq_enter_temporal_polling_mode(struct hbl_cn_device *hdev);
+void gaudi2_cn_eq_exit_temporal_polling_mode(struct hbl_cn_device *hdev);
+void gaudi2_cn_phy_flush_link_status_work(struct hbl_cn_device *hdev);
+int gaudi2_cn_phy_port_init(struct hbl_cn_port *cn_port);
+void gaudi2_cn_phy_port_start_stop(struct hbl_cn_port *cn_port, bool is_start);
+const char *gaudi2_cn_phy_get_fw_name(void);
+int gaudi2_cn_phy_fw_load_all(struct hbl_cn_device *hdev);
+u16 gaudi2_cn_phy_get_crc(struct hbl_cn_device *hdev);
+int gaudi2_cn_phy_port_power_up(struct hbl_cn_port *cn_port);
+void gaudi2_cn_phy_port_reconfig(struct hbl_cn_port *cn_port);
+void gaudi2_cn_phy_port_fini(struct hbl_cn_port *cn_port);
+void gaudi2_cn_phy_link_status_work(struct work_struct *work);
+void gaudi2_cn_phy_dump_serdes_params(struct hbl_cn_device *hdev, char *buf, size_t size);
+void gaudi2_cn_get_mac_fec_stats(struct hbl_cn_port *cn_port, u64 *data);
+bool gaudi2_cn_is_cq_in_overrun(struct hbl_cn_port *cn_port, u8 cq_id);
+bool gaudi2_handle_qp_error_retry(struct hbl_cn_port *cn_port, u32 qpn);
+
+#endif /* GAUDI2_CN_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_debugfs.c b/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_debugfs.c
new file mode 100644
index 000000000000..3acd8b8b0f4a
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_debugfs.c
@@ -0,0 +1,319 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "gaudi2_cn.h"
+
+#define _fsnprintf(buf, size, fmt, ...) \
+ do { \
+ if (full_print) \
+ __snprintf(buf, size, fmt, ##__VA_ARGS__); \
+ \
+ } while (0)
+
+static int gaudi2_cn_debugfs_qpc_req_parse(struct hbl_cn_device *hdev,
+ struct hbl_cn_qp_info *qp_info,
+ struct gaudi2_qpc_requester *req, char *buf,
+ size_t bsize)
+{
+ bool full_print, force_read;
+
+ force_read = qp_info->force_read;
+ full_print = qp_info->full_print;
+
+ __snprintf(buf, bsize, "Valid: %lld\n", REQ_QPC_GET_VALID(*req));
+ if (strlen(buf) >= bsize)
+ return -EFBIG;
+
+ if (!force_read && !REQ_QPC_GET_VALID(*req))
+ return 0;
+
+ __snprintf(buf, bsize, "Error: %lld\n", REQ_QPC_GET_ERROR(*req));
+ if (strlen(buf) >= bsize)
+ return -EFBIG;
+
+ if (!force_read && REQ_QPC_GET_ERROR(*req))
+ return 0;
+
+ _fsnprintf(buf, bsize, "in_work: 0x%llx\n", REQ_QPC_GET_IN_WORK(*req));
+ _fsnprintf(buf, bsize, "trusted: 0x%llx\n", REQ_QPC_GET_TRUST_LEVEL(*req));
+ _fsnprintf(buf, bsize, "WQ addr: 0x%llx\n", REQ_QPC_GET_WQ_BASE_ADDR(*req));
+ _fsnprintf(buf, bsize, "MTU: 0x%llx\n", REQ_QPC_GET_MTU(*req));
+ _fsnprintf(buf, bsize, "cong mode: 0x%llx\n", REQ_QPC_GET_CONGESTION_MODE(*req));
+ _fsnprintf(buf, bsize, "priority: 0x%llx\n", REQ_QPC_GET_PRIORITY(*req));
+ _fsnprintf(buf, bsize, "transport service: 0x%llx\n", REQ_QPC_GET_TRANSPORT_SERVICE(*req));
+ _fsnprintf(buf, bsize, "SWQ gran: 0x%llx\n", REQ_QPC_GET_SWQ_GRANULARITY(*req));
+ __snprintf(buf, bsize, "WQ type: 0x%llx\n", REQ_QPC_GET_WQ_TYPE(*req));
+ _fsnprintf(buf, bsize, "port/lane: 0x%llx\n", REQ_QPC_GET_PORT(*req));
+ _fsnprintf(buf, bsize, "Gaudi1 mode: 0x%llx\n", REQ_QPC_GET_MOD_GAUDI1(*req));
+ __snprintf(buf, bsize, "data MMU BP: 0x%llx\n", REQ_QPC_GET_DATA_MMU_BYPASS(*req));
+ _fsnprintf(buf, bsize, "PSN delivered: 0x%llx\n", REQ_QPC_GET_PSN_DELIVERED(*req));
+ _fsnprintf(buf, bsize, "pacing time: 0x%llx\n", REQ_QPC_GET_PACING_TIME(*req));
+ _fsnprintf(buf, bsize, "Ackreq freq: 0x%llx\n", REQ_QPC_GET_ACKREQ_FREQ(*req));
+ _fsnprintf(buf, bsize, "PSN since ackreq: 0x%llx\n", REQ_QPC_GET_PSN_SINCE_ACKREQ(*req));
+ __snprintf(buf, bsize, "oldest unacked remote PI: 0x%llx\n",
+ REQ_QPC_GET_OLDEST_UNACKED_REMOTE_PRODUCER_IDX(*req));
+ __snprintf(buf, bsize, "remote CI: 0x%llx\n", REQ_QPC_GET_REMOTE_CONSUMER_IDX(*req));
+ __snprintf(buf, bsize, "remote PI: 0x%llx\n", REQ_QPC_GET_REMOTE_PRODUCER_IDX(*req));
+ __snprintf(buf, bsize, "local PI: 0x%llx\n", REQ_QPC_GET_LOCAL_PRODUCER_IDX(*req));
+ __snprintf(buf, bsize, "local CI: 0x%llx\n", REQ_QPC_GET_CONSUMER_IDX(*req));
+ __snprintf(buf, bsize, "local EI: 0x%llx\n", REQ_QPC_GET_EXECUTION_IDX(*req));
+ __snprintf(buf, bsize, "last index: 0x%llx\n", REQ_QPC_GET_LAST_IDX(*req));
+ __snprintf(buf, bsize, "ASID: 0x%llx\n", REQ_QPC_GET_ASID(*req));
+ _fsnprintf(buf, bsize, "burst size: 0x%llx\n", REQ_QPC_GET_BURST_SIZE(*req));
+ _fsnprintf(buf, bsize, "CC RTT PSN: 0x%llx\n", REQ_QPC_GET_RTT_MARKED_PSN(*req));
+ _fsnprintf(buf, bsize, "CC RTT timestamp: 0x%llx\n", REQ_QPC_GET_RTT_TIMESTAMP(*req));
+ _fsnprintf(buf, bsize, "congestion window: 0x%llx\n", REQ_QPC_GET_CONGESTION_WIN(*req));
+ _fsnprintf(buf, bsize, "encap en: 0x%llx\n", REQ_QPC_GET_ENCAP_ENABLE(*req));
+ _fsnprintf(buf, bsize, "RTT state: 0x%llx\n", REQ_QPC_GET_RTT_STATE(*req));
+ _fsnprintf(buf, bsize, "CQ num: 0x%llx\n", REQ_QPC_GET_CQ_NUM(*req));
+ _fsnprintf(buf, bsize, "congestion window NMA: 0x%llx\n",
+ REQ_QPC_GET_CONGESTION_NON_MARKED_ACK(*req));
+ _fsnprintf(buf, bsize, "encap type: 0x%llx\n", REQ_QPC_GET_ENCAP_TYPE(*req));
+ __snprintf(buf, bsize, "remote WQ log bsize: 0x%llx\n", REQ_QPC_GET_REMOTE_WQ_LOG_SZ(*req));
+ _fsnprintf(buf, bsize, "congestion window MA: 0x%llx\n",
+ REQ_QPC_GET_CONGESTION_MARKED_ACK(*req));
+ _fsnprintf(buf, bsize, "WQ back-press: 0x%llx\n", REQ_QPC_GET_WQ_BACK_PRESSURE(*req));
+ _fsnprintf(buf, bsize, "timeout gran: 0x%llx\n", REQ_QPC_GET_TM_GRANULARITY(*req));
+ __snprintf(buf, bsize, "BCC PSN: 0x%llx\n", REQ_QPC_GET_BCC_PSN(*req));
+ __snprintf(buf, bsize, "ONA PSN: 0x%llx\n", REQ_QPC_GET_ONA_PSN(*req));
+ _fsnprintf(buf, bsize, "sched Q: 0x%llx\n", REQ_QPC_GET_SCHD_Q_NUM(*req));
+ __snprintf(buf, bsize, "BCS PSN: 0x%llx\n", REQ_QPC_GET_BCS_PSN(*req));
+ __snprintf(buf, bsize, "NTS PSN: 0x%llx\n", REQ_QPC_GET_NTS_PSN(*req));
+ _fsnprintf(buf, bsize, "timeout retry cnt: 0x%llx\n",
+ REQ_QPC_GET_TIMEOUT_RETRY_COUNT(*req));
+ _fsnprintf(buf, bsize, "seq ERR retry cnt: 0x%llx\n",
+ REQ_QPC_GET_SEQUENCE_ERROR_RETRY_COUNT(*req));
+ __snprintf(buf, bsize, "dst MAC: %04llx%08llx\n", REQ_QPC_GET_DST_MAC_MSB(*req),
+ REQ_QPC_GET_DST_MAC_LSB(*req));
+ _fsnprintf(buf, bsize, "dst ipv4: 0x%llx\n", REQ_QPC_GET_DST_IP(*req));
+ _fsnprintf(buf, bsize, "remote key: 0x%llx\n", REQ_QPC_GET_RKEY(*req));
+ _fsnprintf(buf, bsize, "multi-stride state: 0x%016llx%08llx\n",
+ REQ_QPC_GET_MULTI_STRIDE_STATE_MSB(*req),
+ REQ_QPC_GET_MULTI_STRIDE_STATE_LSB(*req));
+ _fsnprintf(buf, bsize, "dest QP: 0x%llx\n", REQ_QPC_GET_DST_QP(*req));
+
+ /* make sure the caller is aware that the buffer it is using is not long enough */
+ if (strlen(buf) >= bsize)
+ return -EFBIG;
+
+ return 0;
+}
+
+static int gaudi2_cn_debugfs_qpc_res_parse(struct hbl_cn_device *hdev,
+ struct hbl_cn_qp_info *qp_info,
+ struct gaudi2_qpc_responder *res, char *buf,
+ size_t bsize)
+{
+ bool full_print, force_read;
+
+ force_read = qp_info->force_read;
+ full_print = qp_info->full_print;
+
+ __snprintf(buf, bsize, "Valid: %lld\n", RES_QPC_GET_VALID(*res));
+ if (strlen(buf) >= bsize)
+ return -EFBIG;
+
+ if (!force_read && !RES_QPC_GET_VALID(*res))
+ return 0;
+
+ _fsnprintf(buf, bsize, "in work: 0x%llx\n", RES_QPC_GET_IN_WORK(*res));
+ _fsnprintf(buf, bsize, "peer WQ gran: 0x%llx\n", RES_QPC_GET_PEER_WQ_GRAN(*res));
+ _fsnprintf(buf, bsize, "CQ num: 0x%llx\n", RES_QPC_GET_CQ_NUM(*res));
+ __snprintf(buf, bsize, "cyc_idx: 0x%llx\n", RES_QPC_GET_CYCLIC_IDX(*res));
+ _fsnprintf(buf, bsize, "encap EN: 0x%llx\n", RES_QPC_GET_ENCAP_ENABLE(*res));
+ _fsnprintf(buf, bsize, "encap type: 0x%llx\n", RES_QPC_GET_ENCAP_TYPE(*res));
+ __snprintf(buf, bsize, "data MMU BP: 0x%llx\n", RES_QPC_GET_DATA_MMU_BYPASS(*res));
+ _fsnprintf(buf, bsize, "Gaudi1 mode: 0x%llx\n", RES_QPC_GET_MOD_GAUDI1(*res));
+ _fsnprintf(buf, bsize, "trust level: 0x%llx\n", RES_QPC_GET_TRUST_LEVEL(*res));
+ __snprintf(buf, bsize, "expected PSN: 0x%llx\n", RES_QPC_GET_EXPECTED_PSN(*res));
+ _fsnprintf(buf, bsize, "sched Q: 0x%llx\n", RES_QPC_GET_SCHD_Q_NUM(*res));
+ _fsnprintf(buf, bsize, "peer QP: 0x%llx\n", RES_QPC_GET_PEER_QP(*res));
+ __snprintf(buf, bsize, "ASID: 0x%llx\n", RES_QPC_GET_ASID(*res));
+ _fsnprintf(buf, bsize, "transport service: 0x%llx\n", RES_QPC_GET_TRANSPORT_SERVICE(*res));
+ _fsnprintf(buf, bsize, "ECN count: 0x%llx\n", RES_QPC_GET_ECN_COUNT(*res));
+ __snprintf(buf, bsize, "dst MAC: %04llx%08llx\n", RES_QPC_GET_DST_MAC_MSB(*res),
+ RES_QPC_GET_DST_MAC_LSB(*res));
+ __snprintf(buf, bsize, "dst ipv4: 0x%llx\n", RES_QPC_GET_DST_IP(*res));
+ _fsnprintf(buf, bsize, "local key: 0x%llx\n", RES_QPC_GET_LKEY(*res));
+ _fsnprintf(buf, bsize, "NACK syndrome: 0x%llx\n", RES_QPC_GET_NACK_SYNDROME(*res));
+ __snprintf(buf, bsize, "conn state: 0x%llx\n", RES_QPC_GET_CONN_STATE(*res));
+ _fsnprintf(buf, bsize, "priority: 0x%llx\n", RES_QPC_GET_PRIORITY(*res));
+ _fsnprintf(buf, bsize, "port/lane: 0x%llx\n", RES_QPC_GET_PORT(*res));
+ _fsnprintf(buf, bsize, "dest QP: 0x%llx\n", RES_QPC_GET_DESTINATION_QP(*res));
+
+ /* make sure the caller is aware that the buffer it is using is not long enough */
+ if (strlen(buf) >= bsize)
+ return -EFBIG;
+
+ return 0;
+}
+
+int gaudi2_cn_debugfs_qp_read(struct hbl_cn_device *hdev, struct hbl_cn_qp_info *qp_info, char *buf,
+ size_t bsize)
+{
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct gaudi2_qpc_requester qpc_req = {};
+ struct gaudi2_qpc_responder qpc_res = {};
+ struct hbl_cn_port *cn_port;
+ u32 port, qpn;
+ void *qpc;
+ bool req;
+ int rc;
+
+ req = qp_info->req;
+ port = qp_info->port;
+ qpn = qp_info->qpn;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+ cn_port = &hdev->cn_ports[port];
+ qpc = req ? (void *)&qpc_req : (void *)&qpc_res;
+
+ if (!hbl_cn_is_port_open(cn_port)) {
+ dev_err(hdev->dev,
+ "Cannot read port %d QP %d, port is not initialized\n", port, qpn);
+ return -EPERM;
+ }
+
+ port_funcs->cfg_lock(cn_port);
+ rc = gaudi2_cn_qpc_read(cn_port, qpc, qpn, req);
+ port_funcs->cfg_unlock(cn_port);
+ if (rc)
+ return rc;
+
+ __snprintf(buf, bsize, "port %d, qpn %d, req %d:\n", port, qpn, req);
+ if (strlen(buf) >= bsize)
+ return -EFBIG;
+
+ if (req)
+ rc = gaudi2_cn_debugfs_qpc_req_parse(hdev, qp_info, &qpc_req, buf, bsize);
+ else
+ rc = gaudi2_cn_debugfs_qpc_res_parse(hdev, qp_info, &qpc_res, buf, bsize);
+
+ return rc;
+}
+
+static int gaudi2_cn_debugfs_wqe_parse(struct hbl_cn_device *hdev, struct hbl_cn_wqe_info *wqe_info,
+ void *wqe, char *buf, size_t bsize)
+{
+ struct gaudi2_sq_wqe *sq_wqe;
+ struct gaudi2_rq_wqe *rq_wqe;
+ u8 i;
+
+ if (wqe_info->tx) {
+ i = wqe_info->wqe_idx % TX_WQE_NUM_IN_CLINE;
+ sq_wqe = &(((struct gaudi2_sq_wqe *)wqe)[i]);
+ __snprintf(buf, bsize, "opcode: 0x%llx\n", TX_WQE_GET_OPCODE(*sq_wqe));
+ __snprintf(buf, bsize, "trace event data: 0x%llx\n",
+ TX_WQE_GET_TRACE_EVENT_DATA(*sq_wqe));
+ __snprintf(buf, bsize, "trace event: 0x%llx\n", TX_WQE_GET_TRACE_EVENT(*sq_wqe));
+ __snprintf(buf, bsize, "WQE index: 0x%llx\n", TX_WQE_GET_WQE_INDEX(*sq_wqe));
+ __snprintf(buf, bsize, "reduction opcode: 0x%llx\n",
+ TX_WQE_GET_REDUCTION_OPCODE(*sq_wqe));
+ __snprintf(buf, bsize, "SE: 0x%llx\n", TX_WQE_GET_SE(*sq_wqe));
+ __snprintf(buf, bsize, "inline: 0x%llx\n", TX_WQE_GET_INLINE(*sq_wqe));
+ __snprintf(buf, bsize, "ackreq: 0x%llx\n", TX_WQE_GET_ACKREQ(*sq_wqe));
+ __snprintf(buf, bsize, "size: 0x%llx\n", TX_WQE_GET_SIZE(*sq_wqe));
+ __snprintf(buf, bsize, "local address LSB: 0x%llx\n",
+ TX_WQE_GET_LOCAL_ADDR_LSB(*sq_wqe));
+ __snprintf(buf, bsize, "local address MSB: 0x%llx\n",
+ TX_WQE_GET_LOCAL_ADDR_MSB(*sq_wqe));
+ __snprintf(buf, bsize, "remote address LSB: 0x%llx\n",
+ TX_WQE_GET_REMOTE_ADDR_LSB(*sq_wqe));
+ __snprintf(buf, bsize, "remote address MSB: 0x%llx\n",
+ TX_WQE_GET_REMOTE_ADDR_MSB(*sq_wqe));
+ __snprintf(buf, bsize, "tag: 0x%llx\n", TX_WQE_GET_TAG(*sq_wqe));
+ __snprintf(buf, bsize, "remote SOB: 0x%llx\n", TX_WQE_GET_REMOTE_SOB(*sq_wqe));
+ __snprintf(buf, bsize, "remote SOB data: 0x%llx\n",
+ TX_WQE_GET_REMOTE_SOB_DATA(*sq_wqe));
+ __snprintf(buf, bsize, "SOB command: 0x%llx\n", TX_WQE_GET_SOB_CMD(*sq_wqe));
+ __snprintf(buf, bsize, "completion type: 0x%llx\n",
+ TX_WQE_GET_COMPLETION_TYPE(*sq_wqe));
+ } else {
+ i = wqe_info->wqe_idx % RX_WQE_NUM_IN_CLINE;
+ rq_wqe = &(((struct gaudi2_rq_wqe *)wqe)[i]);
+ __snprintf(buf, bsize, "opcode: 0x%llx\n", RX_WQE_GET_OPCODE(*rq_wqe));
+ __snprintf(buf, bsize, "WQE index: 0x%llx\n", RX_WQE_GET_WQE_INDEX(*rq_wqe));
+ __snprintf(buf, bsize, "SOB command: 0x%llx\n", RX_WQE_GET_SOB_CMD(*rq_wqe));
+ __snprintf(buf, bsize, "local SOB: 0x%llx\n", RX_WQE_GET_LOCAL_SOB(*rq_wqe));
+ __snprintf(buf, bsize, "local SOB data: 0x%llx\n",
+ RX_WQE_GET_LOCAL_SOB_DATA(*rq_wqe));
+ __snprintf(buf, bsize, "completion type: 0x%llx\n",
+ RX_WQE_GET_COMPLETION_TYPE(*rq_wqe));
+ __snprintf(buf, bsize, "size: 0x%llx\n", RX_WQE_GET_SIZE(*rq_wqe));
+ __snprintf(buf, bsize, "tag: 0x%llx\n", RX_WQE_GET_TAG(*rq_wqe));
+ }
+
+ /* Make sure the caller is aware that the buffer used isn't big enough */
+ if (strlen(buf) >= bsize)
+ return -EFBIG;
+
+ return 0;
+}
+
+int gaudi2_cn_debugfs_wqe_read(struct hbl_cn_device *hdev, char *buf, size_t bsize)
+{
+ struct gaudi2_sq_wqe sq_wqe[TX_WQE_NUM_IN_CLINE] = {};
+ struct gaudi2_rq_wqe rq_wqe[RX_WQE_NUM_IN_CLINE] = {};
+ struct hbl_cn_asic_port_funcs *port_funcs;
+ struct hbl_cn_wqe_info *wqe_info;
+ struct hbl_cn_port *cn_port;
+ u32 port, qpn, wqe_idx;
+ void *wqe;
+ bool tx;
+ int rc;
+
+ port_funcs = hdev->asic_funcs->port_funcs;
+
+ /* Get the details of the WQE to read as written by the user via debugfs */
+ wqe_info = &hdev->wqe_info;
+ tx = wqe_info->tx;
+ port = wqe_info->port;
+ qpn = wqe_info->qpn;
+ wqe_idx = wqe_info->wqe_idx;
+
+ cn_port = &hdev->cn_ports[port];
+ wqe = tx ? (void *)&sq_wqe : (void *)&rq_wqe;
+
+ if (!hbl_cn_is_port_open(cn_port)) {
+ dev_err(hdev->dev,
+ "Cannot read port %d QP %d, port is not initialized\n", port, qpn);
+ return -EPERM;
+ }
+
+ port_funcs->cfg_lock(cn_port);
+ rc = gaudi2_cn_wqe_read(cn_port, wqe, qpn, wqe_idx, tx);
+ port_funcs->cfg_unlock(cn_port);
+ if (rc)
+ goto exit;
+
+ __snprintf(buf, bsize, "port %d, qpn %d, wqe_idx %d, tx %d:\n", port, qpn, wqe_idx, tx);
+
+ rc = gaudi2_cn_debugfs_wqe_parse(hdev, wqe_info, wqe, buf, bsize);
+
+exit:
+ return rc;
+}
+
+void gaudi2_cn_debugfs_collect_fec_stats(struct hbl_cn_port *cn_port, char *buf, size_t size)
+{
+ u32 port = cn_port->port;
+ u64 data[FEC_STAT_LAST];
+ ssize_t len;
+
+ gaudi2_cn_get_mac_fec_stats(cn_port, data);
+
+ len = strlen(buf);
+ if ((size - len) <= 1)
+ return;
+
+ if (cn_port->pcs_link)
+ snprintf(buf + len, size - len,
+ "Port %u: pre_fec_SER: %llue-%llu post_fec_SER: %llue-%llu\n", port,
+ data[FEC_PRE_FEC_SER_INT], data[FEC_PRE_FEC_SER_EXP],
+ data[FEC_POST_FEC_SER_INT], data[FEC_POST_FEC_SER_EXP]);
+ else
+ snprintf(buf + len, size - len, "Port %u: Link is down\n", port);
+}
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_eq.c b/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_eq.c
new file mode 100644
index 000000000000..68f6367f3798
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_eq.c
@@ -0,0 +1,732 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include <linux/pci.h>
+
+#include "gaudi2_cn.h"
+
+#define GAUDI2_NIC_MAX_STRING_LEN 64
+
+static const char
+gaudi2_cn_eq_irq_name[NIC_NUMBER_OF_ENGINES][GAUDI2_NIC_MAX_STRING_LEN] = {
+ "gaudi2 cn0 qpc0 EQ",
+ "gaudi2 cn0 qpc1 EQ",
+ "gaudi2 cn1 qpc0 EQ",
+ "gaudi2 cn1 qpc1 EQ",
+ "gaudi2 cn2 qpc0 EQ",
+ "gaudi2 cn2 qpc1 EQ",
+ "gaudi2 cn3 qpc0 EQ",
+ "gaudi2 cn3 qpc1 EQ",
+ "gaudi2 cn4 qpc0 EQ",
+ "gaudi2 cn4 qpc1 EQ",
+ "gaudi2 cn5 qpc0 EQ",
+ "gaudi2 cn5 qpc1 EQ",
+ "gaudi2 cn6 qpc0 EQ",
+ "gaudi2 cn6 qpc1 EQ",
+ "gaudi2 cn7 qpc0 EQ",
+ "gaudi2 cn7 qpc1 EQ",
+ "gaudi2 cn8 qpc0 EQ",
+ "gaudi2 cn8 qpc1 EQ",
+ "gaudi2 cn9 qpc0 EQ",
+ "gaudi2 cn9 qpc1 EQ",
+ "gaudi2 cn10 qpc0 EQ",
+ "gaudi2 cn10 qpc1 EQ",
+ "gaudi2 cn11 qpc0 EQ",
+ "gaudi2 cn11 qpc1 EQ",
+};
+
+/* Event queues for all the ports are initialized ahead of port-specific initialization regardless
+ * of being enabled or not. We do the same for their IRQs.
+ */
+static irqreturn_t gaudi2_cn_eq_threaded_isr(int irq, void *arg);
+
+int gaudi2_cn_eq_request_irqs(struct hbl_cn_device *hdev)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_cn_port *gaudi2_port;
+ int i, rc, irq;
+
+ if (!gaudi2->msix_enabled)
+ return 0;
+
+ /* IRQs should be allocated if polling activity is only temporal */
+ if (hdev->poll_enable && !gaudi2->temporal_polling)
+ return 0;
+
+ for (i = 0; i < NIC_NUMBER_OF_PORTS; i++) {
+ gaudi2_port = &gaudi2->cn_ports[i];
+ irq = pci_irq_vector(hdev->pdev, gaudi2->irq_num_port_base + i);
+ rc = request_threaded_irq(irq, NULL, gaudi2_cn_eq_threaded_isr, IRQF_ONESHOT,
+ gaudi2_cn_eq_irq_name[i], gaudi2_port);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to request IRQ %d for port %d\n", irq, i);
+ goto irq_fail;
+ }
+ }
+
+ return 0;
+
+irq_fail:
+ for (i--; i >= 0; i--) {
+ gaudi2_port = &gaudi2->cn_ports[i];
+ irq = pci_irq_vector(hdev->pdev, gaudi2->irq_num_port_base + i);
+ free_irq(irq, gaudi2_port);
+ }
+ return rc;
+}
+
+void gaudi2_cn_eq_sync_irqs(struct hbl_cn_device *hdev)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ int i, irq;
+
+ if (!gaudi2->msix_enabled)
+ return;
+
+ /* IRQs are allocated if polling is temporal so return only if polling mode is constant */
+ if (hdev->poll_enable && !gaudi2->temporal_polling)
+ return;
+
+ for (i = 0; i < NIC_NUMBER_OF_PORTS; i++) {
+ irq = pci_irq_vector(hdev->pdev, gaudi2->irq_num_port_base + i);
+ synchronize_irq(irq);
+ }
+}
+
+void gaudi2_cn_eq_free_irqs(struct hbl_cn_device *hdev)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_cn_port *gaudi2_port;
+ int i, irq;
+
+ if (!gaudi2->msix_enabled)
+ return;
+
+ /* IRQs are allocated if polling is temporal so return only if polling mode is constant */
+ if (hdev->poll_enable && !gaudi2->temporal_polling)
+ return;
+
+ for (i = 0; i < NIC_NUMBER_OF_PORTS; i++) {
+ gaudi2_port = &gaudi2->cn_ports[i];
+ irq = pci_irq_vector(hdev->pdev, gaudi2->irq_num_port_base + i);
+ free_irq(irq, gaudi2_port);
+ }
+}
+
+/* HW per port link/lane status mask */
+static u32 gaudi2_cn_get_link_status_mask(struct gaudi2_cn_port *gaudi2_port)
+{
+ switch (gaudi2_port->cn_port->speed) {
+ case SPEED_50000:
+ /* In 50GbE mode, HW supports up to 2 SERDES
+ * links per port.
+ * Note: SW uses fixed link 0 per port for
+ * transmission. Link 1 is unused.
+ */
+ return 0x3;
+ case SPEED_25000:
+ fallthrough;
+ case SPEED_100000:
+ /* In 100GbE mode, HW supports only one
+ * SERDES link per port.
+ */
+ return 0x1;
+ default:
+ dev_err(gaudi2_port->hdev->dev, "Unsupported speed %d\n",
+ gaudi2_port->cn_port->speed);
+ }
+
+ return 0;
+}
+
+static void gaudi2_cn_link_event_handler(struct gaudi2_cn_port *gaudi2_port)
+{
+ u32 curr_link_sts, link_sts_change, link_status_mask, port;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ struct gaudi2_cn_port *gaudi2_port_curr;
+ u8 l, cn_m, port_offset, port_shift;
+ struct hbl_cn_port *cn_port_curr;
+ struct gaudi2_cn_device *gaudi2;
+ struct hbl_cn_macro *cn_macro;
+ bool link_up, prev_link_up;
+
+ gaudi2 = hdev->asic_specific;
+ port = gaudi2_port->cn_port->port;
+ cn_macro = gaudi2_port->cn_port->cn_macro;
+
+ curr_link_sts = (NIC_MACRO_RREG32(PRT0_MAC_CORE_MAC_REC_STS0) &
+ PRT0_MAC_CORE_MAC_REC_STS0_REC_LINK_STS_MASK) >>
+ PRT0_MAC_CORE_MAC_REC_STS0_REC_LINK_STS_SHIFT;
+
+ /* get the change on the serdes by XOR with previous val */
+ link_sts_change = curr_link_sts ^ cn_macro->rec_link_sts;
+
+ /* store current value as previous (for next round) */
+ cn_macro->rec_link_sts = curr_link_sts;
+
+ /* calc the MACRO its link-change we need to handle */
+ cn_m = port >> 1;
+
+ /* Iterate all SERDES links and check which one was changed */
+ for (l = 0; l < NIC_MAC_LANES; l++) {
+ if (!(link_sts_change & BIT(l)))
+ continue;
+
+ /* calc port offset from current link
+ * (2 ports per macro and 2 links per port)
+ */
+ port_offset = l >> 1;
+ port_shift = port_offset ? 2 : 0;
+
+ /* get the port struct to handle its link according to the
+ * current SERDES link index
+ */
+ gaudi2_port_curr = &gaudi2->cn_ports[cn_m * 2 + port_offset];
+ cn_port_curr = gaudi2_port_curr->cn_port;
+
+ mutex_lock(&cn_port_curr->control_lock);
+
+ /* Skip in case the port is closed because the port_close method took care of
+ * disabling the carrier and stopping the queue.
+ */
+ if (!hbl_cn_is_port_open(cn_port_curr)) {
+ mutex_unlock(&cn_port_curr->control_lock);
+ continue;
+ }
+
+ link_status_mask = gaudi2_cn_get_link_status_mask(gaudi2_port_curr);
+ link_up = (curr_link_sts >> port_shift) & link_status_mask;
+ prev_link_up = cn_port_curr->pcs_link;
+
+ if (prev_link_up != link_up && !link_up) {
+ mutex_lock(&gaudi2_port_curr->qp_destroy_lock);
+
+ if (gaudi2_port_curr->qp_destroy_cnt && !cn_port_curr->mac_loopback) {
+ cn_port_curr->mac_loopback = true;
+ gaudi2_cn_hw_mac_loopback_cfg(gaudi2_port_curr);
+ gaudi2_port_curr->qp_destroy_mac_lpbk = true;
+ }
+
+ mutex_unlock(&gaudi2_port_curr->qp_destroy_lock);
+ }
+
+ /* Record the current link status that we got.
+ * In case it is UP, and PHY is not ready, we don't want to actually set it and
+ * reflect it to the user - this will be done later once the PHY will be ready.
+ */
+ cn_port_curr->eq_pcs_link = link_up;
+
+ /* In case of link DOWN, set the actual link and reflect it to the user */
+ if (!link_up)
+ cn_port_curr->pcs_link = false;
+
+ /* Set the actual link status that is reflected to the user and print it in case
+ * either we don't have PHY or we have PHY and it's ready.
+ */
+ if (!hdev->phy_config_fw || cn_port_curr->phy_fw_tuned) {
+ cn_port_curr->pcs_link = link_up;
+ hbl_cn_phy_set_port_status(cn_port_curr, link_up);
+ }
+
+ mutex_unlock(&cn_port_curr->control_lock);
+ }
+}
+
+static void gaudi2_cn_eq_dispatcher_default_handler(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_port *cn_port = gaudi2_port->cn_port;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 event_type, port, synd;
+ struct hbl_cn_eqe eqe;
+
+ port = cn_port->port;
+
+ mutex_lock(&cn_port->control_lock);
+
+ while (!hbl_cn_eq_dispatcher_dequeue(cn_port, hdev->kernel_asid, &eqe, true)) {
+ if (!EQE_IS_VALID(&eqe)) {
+ dev_warn_ratelimited(hdev->dev,
+ "Port-%d got invalid EQE on default queue!\n", port);
+ continue;
+ }
+
+ event_type = EQE_TYPE(&eqe);
+
+ switch (event_type) {
+ case EQE_COMP:
+ dev_warn_ratelimited(hdev->dev, "Port-%d comp event for invalid CQ:%d\n",
+ port, EQE_CQ_EVENT_CQ_NUM(&eqe));
+ break;
+ case EQE_RAW_TX_COMP:
+ dev_warn_ratelimited(hdev->dev,
+ "Port-%d raw-tx-comp event for invalid QP:%d\n",
+ port, EQE_RAW_TX_EVENT_QPN(&eqe));
+ break;
+ case EQE_QP_ERR:
+ synd = EQE_QP_EVENT_ERR_SYND(&eqe);
+ dev_warn_ratelimited(hdev->dev,
+ "Port-%d qp-err event: %d ,%s, for invalid QP:%d\n",
+ port, synd, gaudi2_cn_qp_err_syndrome_to_str(synd),
+ EQE_QP_EVENT_QPN(&eqe));
+ break;
+ case EQE_COMP_ERR:
+ dev_warn_ratelimited(hdev->dev, "Port-%d cq-err event for invalid CQ:%d\n",
+ port, EQE_CQ_EVENT_CQ_NUM(&eqe));
+ break;
+ case EQE_DB_FIFO_OVERRUN:
+ dev_warn_ratelimited(hdev->dev,
+ "Port-%d db-fifo overrun event for invalid DB:%d\n",
+ port, EQE_DB_EVENT_DB_NUM(&eqe));
+ break;
+ case EQE_CONG:
+ dev_warn_ratelimited(hdev->dev,
+ "Port-%d congestion event for invalid CCQ:%d\n",
+ port, EQE_CQ_EVENT_CCQ_NUM(&eqe));
+ break;
+ case EQE_CONG_ERR:
+ /* congestion error due to cc cq hw bug is known */
+ cn_port->cong_q_err_cnt++;
+ dev_dbg_ratelimited(hdev->dev, "Port-%d congestion error event\n", port);
+ break;
+ case EQE_QP_ALIGN_COUNTERS:
+ dev_warn_ratelimited(hdev->dev,
+ "Port-%d QP align counters event, for invalid QP:%d\n",
+ port, EQE_SW_EVENT_QPN(&eqe));
+ break;
+ default:
+ dev_warn_ratelimited(hdev->dev, "Port-%d unsupported event type: %d",
+ port, event_type);
+ }
+ }
+
+ mutex_unlock(&cn_port->control_lock);
+}
+
+static void cn_eq_handler(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_port *cn_port = gaudi2_port->cn_port;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 event_type, port, synd, qpn;
+ bool qp_retry_handled = false;
+ struct hbl_cn_ring *eq_ring;
+ struct hbl_cn_eqe *eqe_p;
+ int rc;
+
+ eq_ring = &gaudi2_port->eq_ring;
+ port = cn_port->port;
+
+ /* read the producer index from HW once. New event, received
+ * after the "read once", will be handled in the next callback.
+ */
+ eq_ring->pi_shadow = *((u32 *)RING_PI_ADDRESS(eq_ring));
+
+ while (eq_ring->ci_shadow != eq_ring->pi_shadow) {
+ eqe_p = (struct hbl_cn_eqe *)RING_BUF_ADDRESS(eq_ring) +
+ (eq_ring->ci_shadow & (eq_ring->count - 1));
+ if (!EQE_IS_VALID(eqe_p)) {
+ dev_warn_ratelimited(hdev->dev,
+ "Port-%d got invalid EQE on EQ (eq.data[0] 0x%x, ci 0x%x, pi 0x%x)\n",
+ port, eqe_p->data[0], eq_ring->ci_shadow,
+ eq_ring->pi_shadow);
+ } else {
+ event_type = EQE_TYPE(eqe_p);
+
+ if (event_type == EQE_QP_ERR) {
+ synd = EQE_QP_EVENT_ERR_SYND(eqe_p);
+ if (gaudi2_port->adaptive_timeout_en && synd ==
+ NIC_QP_ERR_RETRY_SYNDROME) {
+ qpn = EQE_RAW_TX_EVENT_QPN(eqe_p);
+ if (qpn != RAW_QPN)
+ qp_retry_handled =
+ gaudi2_handle_qp_error_retry(cn_port, qpn);
+ }
+ }
+
+ /* In case this is link event, we handle it now and the dispatcher won't be
+ * involved.
+ */
+ if (event_type == EQE_LINK_STATUS) {
+ gaudi2_cn_link_event_handler(gaudi2_port);
+ /* ignore CQ errors when CQ is in overrun, as CQ overflow errors are
+ * expected.
+ */
+ } else if (!qp_retry_handled && ((event_type != EQE_COMP_ERR) ||
+ !gaudi2_cn_is_cq_in_overrun(cn_port, EQE_CQ_EVENT_CQ_NUM(eqe_p)))) {
+ rc = hbl_cn_eq_dispatcher_enqueue(cn_port, eqe_p);
+ if (rc)
+ dev_warn_ratelimited(hdev->dev,
+ "failed to dispatch event %d, err %d\n",
+ event_type, rc);
+ }
+
+ /* Mark the EQ-entry is not valid */
+ EQE_SET_INVALID(eqe_p);
+ }
+
+ eq_ring->rep_idx++;
+ eq_ring->ci_shadow = (eq_ring->ci_shadow + 1) & EQ_IDX_MASK;
+
+ /* Update the HW consumer index, every quarter ring, with an
+ * absolute value (ci_shadow is a wrap-around value).
+ * Use the read producer index value for that.
+ */
+ if (eq_ring->rep_idx > (eq_ring->count / 4) - 1) {
+ eq_ring->rep_idx = 0;
+ NIC_WREG32(NIC0_QPC0_EVENT_QUE_CONSUMER_INDEX, eq_ring->ci_shadow);
+ }
+ }
+
+ if (!qp_retry_handled) {
+ hbl_cn_eq_handler(cn_port);
+
+ /* Handle unknown resources and events */
+ gaudi2_cn_eq_dispatcher_default_handler(gaudi2_port);
+ }
+}
+
+static inline void gaudi2_cn_eq_clr_interrupts(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 port = gaudi2_port->cn_port->port;
+
+ /* Release the HW to allow more EQ interrupts.
+ * No need for interrupt masking. As long as the SW hasn't set the clear reg,
+ * new interrupts won't be raised
+ */
+ NIC_WREG32(NIC0_QPC0_INTERRUPT_CLR, 0x200);
+
+ /* flush write so the interrupt will be cleared as soon as possible */
+ NIC_RREG32(NIC0_QPC0_INTERRUPT_CLR);
+}
+
+static void gaudi2_cn_eq_work(struct work_struct *work)
+{
+ struct gaudi2_cn_port *gaudi2_port = container_of(work, struct gaudi2_cn_port,
+ eq_work.work);
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+
+ cn_eq_handler(gaudi2_port);
+
+ if (hdev->poll_enable)
+ schedule_delayed_work(&gaudi2_port->eq_work, msecs_to_jiffies(1));
+ else
+ gaudi2_cn_eq_clr_interrupts(gaudi2_port);
+}
+
+/* Use this routine when working with real HW */
+static irqreturn_t gaudi2_cn_eq_threaded_isr(int irq, void *arg)
+{
+ struct gaudi2_cn_port *gaudi2_port = arg;
+
+ gaudi2_cn_eq_clr_interrupts(gaudi2_port);
+ cn_eq_handler(gaudi2_port);
+
+ return IRQ_HANDLED;
+}
+
+static void gaudi2_cn_eq_hw_config(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_ring *ring = &gaudi2_port->eq_ring;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 port = gaudi2_port->cn_port->port;
+
+ WARN_ON_CACHE_UNALIGNED(RING_PI_DMA_ADDRESS(ring));
+ WARN_ON_CACHE_UNALIGNED(RING_BUF_DMA_ADDRESS(ring));
+
+ /* set base address for event queue */
+ NIC_WREG32(NIC0_QPC0_EVENT_QUE_PI_ADDR_63_32, upper_32_bits(RING_PI_DMA_ADDRESS(ring)));
+
+ NIC_WREG32(NIC0_QPC0_EVENT_QUE_PI_ADDR_31_7,
+ lower_32_bits(RING_PI_DMA_ADDRESS(ring)) >> 7);
+
+ NIC_WREG32(NIC0_QPC0_EVENT_QUE_BASE_ADDR_63_32,
+ upper_32_bits(RING_BUF_DMA_ADDRESS(ring)));
+
+ NIC_WREG32(NIC0_QPC0_EVENT_QUE_BASE_ADDR_31_7,
+ lower_32_bits(RING_BUF_DMA_ADDRESS(ring)) >> 7);
+
+ NIC_WREG32(NIC0_QPC0_EVENT_QUE_LOG_SIZE, ilog2(ring->count));
+
+ NIC_WREG32(NIC0_QPC0_EVENT_QUE_WRITE_INDEX, 0);
+ NIC_WREG32(NIC0_QPC0_EVENT_QUE_PRODUCER_INDEX, 0);
+ NIC_WREG32(NIC0_QPC0_EVENT_QUE_CONSUMER_INDEX, 0);
+ NIC_WREG32(NIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CB, 0);
+
+ NIC_WREG32(NIC0_QPC0_EVENT_QUE_CFG, NIC0_QPC0_EVENT_QUE_CFG_INTERRUPT_PER_EQE_MASK |
+ NIC0_QPC0_EVENT_QUE_CFG_WRITE_PI_EN_MASK | NIC0_QPC0_EVENT_QUE_CFG_ENABLE_MASK);
+
+ NIC_WREG32(NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_WR_OVRD_LO, 0xFFFFFBFF);
+ NIC_WREG32(NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_HB_RD_OVRD_LO, 0xFFFFFBFF);
+
+ /* reset SW indices */
+ *((u32 *)RING_PI_ADDRESS(ring)) = 0;
+ ring->pi_shadow = 0;
+ ring->ci_shadow = 0;
+ ring->rep_idx = 0;
+}
+
+static void gaudi2_cn_eq_interrupts_enable_conditionally(struct gaudi2_cn_port *gaudi2_port,
+ bool poll_enable)
+{
+ struct hbl_cn_port *cn_port = gaudi2_port->cn_port;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 port = cn_port->port, sob_id;
+ struct gaudi2_cn_device *gaudi2;
+
+ gaudi2 = hdev->asic_specific;
+
+ if (poll_enable) {
+ /* Masking all QPC Interrupts except EQ wire int */
+ NIC_WREG32(NIC0_QPC0_INTERRUPT_MASK, 0x3FF);
+ NIC_WREG32(NIC0_QPC0_INTERRUPT_EN,
+ NIC0_QPC0_INTERRUPT_EN_INTERRUPT10_WIRE_EN_MASK);
+ } else {
+ sob_id = gaudi2->sob_id_base + port;
+ NIC_WREG32(NIC0_QPC0_INTERRUPT_BASE_9,
+ DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_id * sizeof(u32));
+ NIC_WREG32(NIC0_QPC0_INTERRUPT_DATA_9, gaudi2->sob_inc_cfg_val);
+
+ /* Masking all QPC Interrupts except EQ int and error event queue int */
+ NIC_WREG32(NIC0_QPC0_INTERRUPT_MASK, 0x1FF);
+
+ NIC_WREG32(NIC0_QPC0_INTERRUPT_EN,
+ NIC0_QPC0_INTERRUPT_EN_INTERRUPT9_MSI_EN_MASK |
+ NIC0_QPC0_INTERRUPT_EN_INTERRUPT10_WIRE_EN_MASK);
+ }
+
+ /* flush */
+ NIC_RREG32(NIC0_QPC0_INTERRUPT_EN);
+}
+
+static void gaudi2_cn_eq_interrupts_disable(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_port *cn_port = gaudi2_port->cn_port;
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+ u32 port = cn_port->port;
+
+ /* disabling and masking all QPC Interrupts */
+ NIC_WREG32(NIC0_QPC0_INTERRUPT_EN, 0);
+ NIC_WREG32(NIC0_QPC0_INTERRUPT_MASK, 0x7FF);
+
+ /* flush */
+ NIC_RREG32(NIC0_QPC0_INTERRUPT_EN);
+}
+
+void gaudi2_cn_eq_enter_temporal_polling_mode(struct hbl_cn_device *hdev)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_cn_port *gaudi2_port;
+ int i;
+
+ if (hdev->poll_enable)
+ return;
+
+ for (i = 0; i < NIC_NUMBER_OF_PORTS; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ gaudi2_port = &gaudi2->cn_ports[i];
+ gaudi2_cn_eq_interrupts_enable_conditionally(gaudi2_port, true);
+ }
+
+ hdev->poll_enable = true;
+
+ /* wait for ISRs to complete before scheduling the polling work */
+ gaudi2_cn_eq_sync_irqs(hdev);
+
+ for (i = 0; i < NIC_NUMBER_OF_PORTS; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ gaudi2_port = &gaudi2->cn_ports[i];
+ schedule_delayed_work(&gaudi2_port->eq_work, msecs_to_jiffies(1));
+ }
+}
+
+void gaudi2_cn_eq_exit_temporal_polling_mode(struct hbl_cn_device *hdev)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_cn_port *gaudi2_port;
+ int i;
+
+ if (!hdev->poll_enable)
+ return;
+
+ if (!gaudi2->temporal_polling)
+ return;
+
+ for (i = 0; i < NIC_NUMBER_OF_PORTS; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ gaudi2_port = &gaudi2->cn_ports[i];
+ cancel_delayed_work_sync(&gaudi2_port->eq_work);
+ }
+
+ hdev->poll_enable = false;
+
+ for (i = 0; i < NIC_NUMBER_OF_PORTS; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ gaudi2_port = &gaudi2->cn_ports[i];
+ gaudi2_cn_eq_interrupts_enable_conditionally(gaudi2_port, false);
+ /* Schedule the work as interrupts may be pending but not acked thus preventing
+ * interrupts from triggering.
+ * Double scheduling avoidance of the work (from the ISR and from here)
+ * is done by the WQ scheduler itself.
+ */
+ schedule_delayed_work(&gaudi2_port->eq_work, 0);
+ }
+}
+
+static int gaudi2_cn_eq_port_init(struct gaudi2_cn_port *gaudi2_port)
+{
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+
+ gaudi2_cn_eq_hw_config(gaudi2_port);
+
+ /* we disable eq handler here in order to prevent a crash if a race occurs
+ * between the work-queue calling the handler routine and the eth driver
+ * unregistering it.
+ */
+ gaudi2_port->cn_port->eq_handler_enable = false;
+
+ INIT_DELAYED_WORK(&gaudi2_port->eq_work, gaudi2_cn_eq_work);
+
+ gaudi2_cn_eq_interrupts_enable_conditionally(gaudi2_port, hdev->poll_enable);
+
+ if (hdev->poll_enable)
+ schedule_delayed_work(&gaudi2_port->eq_work, msecs_to_jiffies(1));
+
+ return 0;
+}
+
+static void gaudi2_cn_eq_port_fini(struct gaudi2_cn_port *gaudi2_port)
+{
+ gaudi2_cn_eq_interrupts_disable(gaudi2_port);
+ cancel_delayed_work_sync(&gaudi2_port->eq_work);
+ gaudi2_port->cn_port->eq_handler_enable = false;
+}
+
+int gaudi2_cn_eq_init(struct hbl_cn_device *hdev)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_cn_port *gaudi2_port;
+ int rc, i, port_cnt = 0;
+ u32 port;
+
+ /* Need to reset the value of 'poll_enable' for a case that we entered temporal polling mode
+ * but didn't exit it (e.g. during a failing soft-reset).
+ * The original value is actually the inverse of 'temporal_polling' which is set once in
+ * sw_init and is constant.
+ */
+ hdev->poll_enable = !gaudi2->temporal_polling;
+
+ /* Due to H/W bug on gaudi2, link events for both even and odd ports arrive only on the odd
+ * port in the macro. Therefore, need to initialize all EQs of all ports regardless of their
+ * enablement.
+ */
+ for (i = 0; i < NIC_NUMBER_OF_PORTS; i++, port_cnt++) {
+ gaudi2_port = &gaudi2->cn_ports[i];
+ port = gaudi2_port->cn_port->port;
+
+ rc = gaudi2_cn_eq_port_init(gaudi2_port);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init the hardware EQ, port: %d, %d\n", port,
+ rc);
+ goto err;
+ }
+ }
+
+ return 0;
+
+err:
+ for (i = 0; i < port_cnt; i++)
+ gaudi2_cn_eq_port_fini(&gaudi2->cn_ports[i]);
+
+ return rc;
+}
+
+void gaudi2_cn_eq_fini(struct hbl_cn_device *hdev)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ int i;
+
+ for (i = 0; i < NIC_NUMBER_OF_PORTS; i++)
+ gaudi2_cn_eq_port_fini(&gaudi2->cn_ports[i]);
+}
+
+/* event dispatcher
+ *
+ * In gaudi2 each port has a single EQ. The HW writes all the related events
+ * to this EQ. Since multiple applications can use the port at the same time we
+ * need to have a way to dispatch the app-related events to the correct
+ * application, these events will be read later on by the IB API.
+ */
+
+struct hbl_cn_ev_dq *gaudi2_cn_eq_dispatcher_select_dq(struct hbl_cn_port *cn_port,
+ const struct hbl_cn_eqe *eqe)
+{
+ struct gaudi2_cn_port *gaudi2_port = (struct gaudi2_cn_port *)cn_port->cn_specific;
+ struct hbl_cn_ev_dqs *ev_dqs = &cn_port->ev_dqs;
+ struct hbl_cn_ev_dq *dq = NULL;
+ u32 event_type = EQE_TYPE(eqe);
+ u32 cqn, qpn, dbn, ccqn;
+
+ switch (event_type) {
+ case EQE_COMP:
+ fallthrough;
+ case EQE_COMP_ERR:
+ cqn = EQE_CQ_EVENT_CQ_NUM(eqe);
+ dq = hbl_cn_cqn_to_dq(ev_dqs, cqn, gaudi2_port->hdev);
+ break;
+ case EQE_QP_ERR:
+ qpn = EQE_QP_EVENT_QPN(eqe);
+ dq = hbl_cn_qpn_to_dq(ev_dqs, qpn);
+ break;
+ case EQE_RAW_TX_COMP:
+ qpn = EQE_RAW_TX_EVENT_QPN(eqe);
+ dq = hbl_cn_qpn_to_dq(ev_dqs, qpn);
+ break;
+ case EQE_DB_FIFO_OVERRUN:
+ dbn = EQE_DB_EVENT_DB_NUM(eqe);
+ dq = hbl_cn_dbn_to_dq(ev_dqs, dbn, gaudi2_port->hdev);
+ break;
+ case EQE_CONG:
+ ccqn = EQE_CQ_EVENT_CCQ_NUM(eqe);
+ dq = hbl_cn_ccqn_to_dq(ev_dqs, ccqn, gaudi2_port->hdev);
+ break;
+ case EQE_QP_ALIGN_COUNTERS:
+ qpn = EQE_SW_EVENT_QPN(eqe);
+ dq = hbl_cn_qpn_to_dq(ev_dqs, qpn);
+ break;
+ case EQE_CONG_ERR:
+ fallthrough;
+ case EQE_RESERVED:
+ fallthrough;
+ default:
+ dq = &ev_dqs->default_edq;
+ }
+
+ /* Unknown resources and events should be handled by default events
+ * dispatch queue.
+ */
+ return IS_ERR_OR_NULL(dq) ? &ev_dqs->default_edq : dq;
+}
+
+int gaudi2_cn_eq_dispatcher_register_db(struct gaudi2_cn_port *gaudi2_port, u32 asid, u32 dbn)
+{
+ struct hbl_cn_device *hdev = gaudi2_port->hdev;
+
+ if (dbn == GAUDI2_DB_FIFO_PRIVILEGE_HW_ID)
+ return -EINVAL;
+
+ if (asid != hdev->kernel_asid && dbn == GAUDI2_DB_FIFO_SECURE_HW_ID)
+ return -EINVAL;
+
+ return hbl_cn_eq_dispatcher_register_db(gaudi2_port->cn_port, asid, dbn);
+}
diff --git a/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_phy.c b/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_phy.c
new file mode 100644
index 000000000000..2837fc11c43a
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_phy.c
@@ -0,0 +1,2743 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/firmware.h>
+
+#include "gaudi2_cn.h"
+
+#define NIC_PHY_CFG_SIZE (NIC0_SERDES1_LANE0_REGISTER_0P00 - NIC0_SERDES0_LANE0_REGISTER_0P00)
+
+#define NIC_PHY_CFG_BASE(port) \
+ ({ \
+ u32 __port = (port); \
+ ((u64)(NIC_MACRO_CFG_BASE(__port) + \
+ NIC_PHY_CFG_SIZE * (u64)((__port) & 1))); \
+ })
+
+#define LANE_LO_OFF (NIC0_SERDES0_LANE1_REGISTER_0P00 - NIC0_SERDES0_LANE0_REGISTER_0P00)
+
+#define LANE_HI_OFF (NIC0_SERDES0_LANE1_REGISTER_AI00 - NIC0_SERDES0_LANE0_REGISTER_AI00)
+
+#define LANE_OFF(reg, lane) \
+ ({ \
+ u32 __lane = lane; \
+ ((reg) < NIC0_SERDES0_LANE0_REGISTER_AI00) ? \
+ ((__lane) * LANE_LO_OFF) : ((__lane) * LANE_HI_OFF); \
+ })
+
+#define PHY_PRINT(port, lane, op, val, reg) \
+ ({ \
+ if (hdev->phy_regs_print) { \
+ u32 __port = (port); \
+ dev_info(hdev->dev, "[%s],Nic,%u,Port,%u,Lane,%d,%s,0x%08x,0x%08llx\n", \
+ __func__, __port >> 1, __port & 0x1, (lane), (op), (val), (reg)); \
+ usleep_range(1000, 2000); \
+ } \
+ })
+
+#define NIC_PHY_RREG32(reg) \
+ ({ \
+ u32 _port = port; \
+ u64 _reg = NIC_PHY_CFG_BASE(_port) + (reg); \
+ u32 _val = RREG32(_reg); \
+ PHY_PRINT(_port, -1, "read", _val, _reg); \
+ _val; \
+ })
+
+#define NIC_PHY_WREG32(reg, val) \
+ do { \
+ u32 _port = port; \
+ u64 _reg = NIC_PHY_CFG_BASE(_port) + (reg); \
+ u32 _val = (val); \
+ WREG32(_reg, _val); \
+ PHY_PRINT(_port, -1, "write", _val, _reg); \
+ } while (0)
+
+#define NIC_PHY_RMWREG32(reg, val, mask) \
+ do { \
+ u32 _port = port; \
+ u64 _reg = NIC_PHY_CFG_BASE(_port) + (reg); \
+ u32 _val = (val); \
+ u32 _mask = (mask); \
+ u32 _tmp = RREG32(_reg); \
+ PHY_PRINT(_port, -1, "read(rmw)", _tmp, _reg); \
+ _tmp &= ~_mask; \
+ _tmp |= (_val << __ffs(_mask)); \
+ WREG32(_reg, _tmp); \
+ PHY_PRINT(_port, -1, "write(rmw)", _tmp, _reg); \
+ } while (0)
+
+#define NIC_PHY_RREG32_LANE(reg) \
+ ({ \
+ u32 _port = port; \
+ u32 _lane = lane; \
+ u64 _reg = (reg); \
+ u64 __reg = NIC_PHY_CFG_BASE(_port) + _reg + LANE_OFF(_reg, _lane); \
+ u32 _val = RREG32(__reg); \
+ PHY_PRINT(_port, _lane, "read", _val, __reg); \
+ _val; \
+ })
+
+#define NIC_PHY_WREG32_LANE(reg, val) \
+ do { \
+ u32 _port = port; \
+ u32 _lane = lane; \
+ u64 _reg = (reg); \
+ u64 __reg = NIC_PHY_CFG_BASE(_port) + _reg + LANE_OFF(_reg, _lane); \
+ u32 _val = (val); \
+ WREG32(__reg, _val); \
+ PHY_PRINT(_port, _lane, "write", _val, __reg); \
+ } while (0)
+
+#define NIC_PHY_RMWREG32_LANE(reg, val, mask) \
+ do { \
+ u32 _port = port; \
+ u32 _lane = lane; \
+ u64 _reg = (reg); \
+ u64 __reg = NIC_PHY_CFG_BASE(_port) + _reg + LANE_OFF(_reg, _lane); \
+ u32 _val = (val); \
+ u32 _mask = (mask); \
+ u32 _tmp = RREG32(__reg); \
+ PHY_PRINT(_port, _lane, "read(rmw)", _tmp, __reg); \
+ _tmp &= ~_mask; \
+ _tmp |= (_val << __ffs(_mask)); \
+ WREG32(__reg, _tmp); \
+ PHY_PRINT(_port, _lane, "write(rmw)", _tmp, __reg); \
+ } while (0)
+
+#define NIC_PHY_READ_COUNTS_PER_MS 100000
+#define NIC_PHY_FW_TIME_CONSTANT_RATIO 64
+#define NIC_PHY_FW_TUNING_INTERVAL_MS 100
+#define NIC_PHY_FW_TUNING_TIMEOUT_MS (30 * MSEC_PER_SEC) /* 30 seconds */
+#define NIC_PHY_PAM4_BER_FACTOR 53125000
+#define NIC_PHY_NRZ_BER_FACTOR 25781250
+
+#define NIC_PHY_TX_POL_MASK_HL225 0xF00000000430
+#define NIC_PHY_RX_POL_MASK_HL225 0x0FFFFFFFFBCF
+#define NIC_PHY_TX_POL_MASK_HLS2 0x0
+#define NIC_PHY_RX_POL_MASK_HLS2 0x0
+
+#define NIC_PHY_PCS_LINK_DOWN_TH_S 5
+#define NIC_PHY_MAC_REMOTE_FAULT_TH_S 10
+
+#define NIC_PHY_PCS_SETTLING_WAIT_MS (5 * MSEC_PER_SEC)
+#define NIC_PHY_PCS_STRESS_INT_MS 10
+#define NIC_PHY_PCS_STEADY_STATE_INT_MS (1 * MSEC_PER_SEC)
+
+#define NIC_PHY_PCS_TESTING_WINDOW_S 20
+#define NIC_PHY_PCS_TESTING_WINDOW_MS (NIC_PHY_PCS_TESTING_WINDOW_S * MSEC_PER_SEC)
+#define NIC_PHY_PCS_STRESS_WINDOW_MS \
+ (NIC_PHY_PCS_TESTING_WINDOW_MS - NIC_PHY_PCS_SETTLING_WAIT_MS)
+
+#define NIC_PHY_PCS_MAX_LINK_TOGGLES 5
+
+enum tx_taps_sets {
+ NIC_PHY_TX_TAPS_SET_1 = 0,
+ NIC_PHY_TX_TAPS_SET_2,
+ NIC_PHY_TX_TAPS_SET_3,
+ NIC_PHY_TX_TAPS_SET_4,
+
+ NIC_PHY_TX_TAPS_NUM_SETS
+};
+
+#define NIC_PHY_DEFAULT_TX_TAPS_DEFAULT NIC_PHY_TX_TAPS_SET_1
+
+struct hbl_cn_tx_taps tx_taps_set_array[NIC_PHY_TX_TAPS_NUM_SETS] = {
+ {.pam4_taps = {2, -10, 23, 0, 0}, .nrz_taps = {0, -10, 26, 0, 0}},
+ {.pam4_taps = {0, -6, 22, 0, 0}, .nrz_taps = {0, -10, 26, 0, 0}},
+ {.pam4_taps = {3, -12, 21, 0, 0}, .nrz_taps = {0, -10, 26, 0, 0}},
+ {.pam4_taps = {1, -7, 18, 0, 0}, .nrz_taps = {0, -10, 26, 0, 0}},
+};
+
+static enum tx_taps_sets tx_taps_cfg_array[][2] = {
+ {NIC_PHY_TX_TAPS_SET_1, NIC_PHY_TX_TAPS_SET_1},
+ {NIC_PHY_TX_TAPS_SET_1, NIC_PHY_TX_TAPS_SET_2},
+ {NIC_PHY_TX_TAPS_SET_2, NIC_PHY_TX_TAPS_SET_1},
+ {NIC_PHY_TX_TAPS_SET_2, NIC_PHY_TX_TAPS_SET_2},
+ {NIC_PHY_TX_TAPS_SET_1, NIC_PHY_TX_TAPS_SET_3},
+ {NIC_PHY_TX_TAPS_SET_3, NIC_PHY_TX_TAPS_SET_1},
+ {NIC_PHY_TX_TAPS_SET_3, NIC_PHY_TX_TAPS_SET_3},
+ {NIC_PHY_TX_TAPS_SET_1, NIC_PHY_TX_TAPS_SET_4},
+ {NIC_PHY_TX_TAPS_SET_4, NIC_PHY_TX_TAPS_SET_1},
+ {NIC_PHY_TX_TAPS_SET_4, NIC_PHY_TX_TAPS_SET_4}
+};
+
+static size_t tx_taps_num_cfgs = ARRAY_SIZE(tx_taps_cfg_array);
+
+#define NIC_MAC_LANE_MAP(lane_0, lane_1, lane_2, lane_3) \
+ (((lane_0) & \
+ NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES0_TX0_SWAP_ID_MASK) | \
+ (((lane_1) & \
+ NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES0_TX0_SWAP_ID_MASK) << \
+ NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES0_TX1_SWAP_ID_SHIFT) | \
+ (((lane_2) & \
+ NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES0_TX0_SWAP_ID_MASK) << \
+ NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES1_TX0_SWAP_ID_SHIFT) | \
+ (((lane_3) & \
+ NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES0_TX0_SWAP_ID_MASK) << \
+ NIC0_PHY_PHY_ASYNC_LANE_SWAP_SERDES1_TX1_SWAP_ID_SHIFT))
+
+/* Lane map for HL-225 */
+static u32 default_cn_mac_lane_remap[] = {
+ /* MACRO 0 */
+ NIC_MAC_LANE_MAP(NIC_MAC_LANE_3, NIC_MAC_LANE_1, NIC_MAC_LANE_0, NIC_MAC_LANE_2),
+ /* MACRO 1-10. Use default HW power on reset mapping. */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* MACRO 11 */
+ NIC_MAC_LANE_MAP(NIC_MAC_LANE_1, NIC_MAC_LANE_0, NIC_MAC_LANE_3, NIC_MAC_LANE_2),
+};
+
+/* Firmware lane mapping per macro are nibbles.
+ * e.g. 0x3210 maps to lane 3/2/1/0
+ */
+#define FW_PARSE_LANE_MAP(macro, lane) \
+ ({ \
+ u32 _lane = (lane); \
+ ((macro) & (0xf << (_lane * 4))) >> (_lane * 4); \
+ })
+
+enum lane_state {
+ READY,
+ NOT_READY,
+ FAILURE
+};
+
+#define GAUDI2_PHY_FW_FILE "habanalabs/gaudi2/gaudi2_cn_fw.bin"
+
+MODULE_FIRMWARE(GAUDI2_PHY_FW_FILE);
+
+const char *gaudi2_cn_phy_get_fw_name(void)
+{
+ return GAUDI2_PHY_FW_FILE;
+}
+
+static int get_tx_lane_in_macro(struct hbl_cn_device *hdev, u32 port, int lane)
+{
+ u32 lane_in_macro, lane_swap_val;
+ int tx_lane;
+
+ lane_in_macro = (port & 0x1) * 2 + lane;
+ lane_swap_val = hdev->mac_lane_remap[port >> 1];
+
+ if (!lane_swap_val)
+ return lane_in_macro;
+
+ for (tx_lane = 0; tx_lane < NIC_MAC_NUM_OF_LANES; tx_lane++) {
+ if (((lane_swap_val >> (tx_lane * 2)) & 0x3) == lane_in_macro)
+ break;
+ }
+
+ return tx_lane;
+}
+
+static void get_tx_port_and_lane(struct hbl_cn_device *hdev, u32 port, int lane, u32 *tx_port,
+ int *tx_lane)
+{
+ struct hbl_cn_port *cn_port = &hdev->cn_ports[port];
+ u32 tx_lane_in_macro, abs_tx_lane_idx;
+
+ if (!cn_port->auto_neg_enable) {
+ *tx_port = port;
+ *tx_lane = lane;
+ return;
+ }
+
+ tx_lane_in_macro = get_tx_lane_in_macro(hdev, port, lane);
+ abs_tx_lane_idx = (port >> 1) * NIC_MAC_NUM_OF_LANES + tx_lane_in_macro;
+
+ *tx_port = abs_tx_lane_idx >> 1;
+ *tx_lane = abs_tx_lane_idx & 0x1;
+}
+
+static bool is_lane_swapping(struct hbl_cn_device *hdev, u32 port, int lane)
+{
+ u32 tx_port;
+ int tx_lane;
+
+ get_tx_port_and_lane(hdev, port, lane, &tx_port, &tx_lane);
+
+ return (tx_port != port) || (tx_lane != lane);
+}
+
+static void set_fw_lane_mapping(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_cpucp_info *cpucp_info = hdev->cpucp_info;
+ u16 cpu_macro_tx_swap_map;
+ int i;
+
+ for (i = 0; i < NIC_NUMBER_OF_MACROS; i++) {
+ cpu_macro_tx_swap_map = cpucp_info->tx_swap_map[i];
+ hdev->mac_lane_remap[i] = NIC_MAC_LANE_MAP(FW_PARSE_LANE_MAP(cpu_macro_tx_swap_map,
+ 0), /* lane 0 */
+ FW_PARSE_LANE_MAP(cpu_macro_tx_swap_map,
+ 1), /* lane 1 */
+ FW_PARSE_LANE_MAP(cpu_macro_tx_swap_map,
+ 2), /* lane 2 */
+ FW_PARSE_LANE_MAP(cpu_macro_tx_swap_map,
+ 3)); /* lane 3 */
+ }
+}
+
+static void mac_lane_remap(struct hbl_cn_device *hdev, u32 port)
+{
+ if (hdev->mac_lane_remap[port >> 1])
+ NIC_MACRO_WREG32(NIC0_PHY_PHY_ASYNC_LANE_SWAP, hdev->mac_lane_remap[port >> 1]);
+}
+
+static void soft_reset(struct hbl_cn_device *hdev, u32 port)
+{
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_980D, 0x888,
+ NIC0_SERDES0_REGISTER_980D_DOMAIN_RESET_MASK);
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_980D, 0x0,
+ NIC0_SERDES0_REGISTER_980D_DOMAIN_RESET_MASK);
+}
+
+static void logic_reset(struct hbl_cn_device *hdev, u32 port)
+{
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_980D, 0x777,
+ NIC0_SERDES0_REGISTER_980D_DOMAIN_RESET_MASK);
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_980D, 0x0,
+ NIC0_SERDES0_REGISTER_980D_DOMAIN_RESET_MASK);
+}
+
+static void cpu_reset(struct hbl_cn_device *hdev, u32 port)
+{
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_980D, 0xAAA,
+ NIC0_SERDES0_REGISTER_980D_DOMAIN_RESET_MASK);
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_980D, 0x0,
+ NIC0_SERDES0_REGISTER_980D_DOMAIN_RESET_MASK);
+}
+
+static int fw_cmd(struct hbl_cn_device *hdev, u32 port, u32 cmd, u32 *detail, u32 expected_res,
+ u32 *res_ptr)
+{
+ u32 res, val, checks = 0;
+
+ if (detail)
+ NIC_PHY_WREG32(NIC0_SERDES0_REGISTER_9816, *detail);
+
+ NIC_PHY_WREG32(NIC0_SERDES0_REGISTER_9815, cmd);
+
+ do {
+ usleep_range(1000, 2000);
+ res = NIC_PHY_RREG32(NIC0_SERDES0_REGISTER_9815);
+ if (checks++ > NIC_PHY_READ_COUNTS_PER_MS) {
+ dev_dbg(hdev->dev, "timeout for PHY cmd 0x%x port %u\n", cmd, port);
+ return -ETIMEDOUT;
+ }
+ } while (res == cmd);
+
+ val = (res >> 8) & 0xF;
+
+ if (val != expected_res) {
+ dev_dbg(hdev->dev, "cmd 0x%x returned error 0x%x port %u\n", cmd, val, port);
+ return -EFAULT;
+ }
+
+ *res_ptr = res;
+
+ return 0;
+}
+
+static void clock_init(struct hbl_cn_device *hdev, u32 port, int lane)
+{
+ u32 first_val, second_val;
+
+ if (port & 0x1) { /* raven 1 */
+ if (lane == 0) {
+ first_val = 0xA9E0;
+ second_val = 0x9B9E;
+ } else { /* lane 1 */
+ first_val = 0xA9E0;
+ second_val = 0x9B9E;
+ }
+ } else { /* raven 0 */
+ if (lane == 0) {
+ first_val = 0x59E0;
+ second_val = 0x9B5E;
+ } else { /* lane 1 */
+ first_val = 0xA9E0;
+ second_val = 0x9B9E;
+ }
+ }
+
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PCC, first_val);
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0NF3, second_val);
+}
+
+static u32 int_to_twos(s32 val, u8 bitwidth)
+{
+ return val < 0 ? (1 << bitwidth) + val : val;
+}
+
+static int twos_to_int(unsigned int val, u8 bitwidth)
+{
+ u32 mask = 1 << (bitwidth - 1);
+
+ return -(val & mask) + (val & ~mask);
+}
+
+static void set_tx_taps(struct hbl_cn_device *hdev, u32 port, int lane, s32 tx_pre2, s32 tx_pre1,
+ s32 tx_main, s32 tx_post1, s32 tx_post2, bool pam4)
+{
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA5, int_to_twos(tx_pre2, 8),
+ NIC0_SERDES0_LANE0_REGISTER_0PA5_TX_PRE_2_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA7, int_to_twos(tx_pre1, 8),
+ NIC0_SERDES0_LANE0_REGISTER_0PA7_TX_PRE_1_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA9, int_to_twos(tx_main, 8),
+ NIC0_SERDES0_LANE0_REGISTER_0PA9_TX_MAIN_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PAB, int_to_twos(tx_post1, 8),
+ NIC0_SERDES0_LANE0_REGISTER_0PAB_TX_POST_1_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PAD, int_to_twos(tx_post2, 8),
+ NIC0_SERDES0_LANE0_REGISTER_0PAD_TX_POST_2_MASK);
+
+ dev_dbg(hdev->dev, "Card %u Port %u lane %d: set %s tx taps [%d,%d,%d,%d,%d]\n",
+ hdev->card_location, port, lane, pam4 ? "PAM4" : "NRZ", tx_pre2, tx_pre1, tx_main,
+ tx_post1, tx_post2);
+}
+
+static void set_tx_taps_cfg(struct hbl_cn_device *hdev, u32 port, int lane, u8 cfg, bool pam4,
+ bool reset_taps)
+{
+ enum tx_taps_sets set_id;
+ u32 abs_lane_idx;
+ s32 *taps;
+
+ set_id = tx_taps_cfg_array[cfg][lane];
+ abs_lane_idx = (port << 1) + lane;
+
+ if (pam4) {
+ taps = hdev->phy_tx_taps[abs_lane_idx].pam4_taps;
+ memcpy(taps, tx_taps_set_array[set_id].pam4_taps,
+ sizeof(hdev->phy_tx_taps[abs_lane_idx].pam4_taps));
+ } else {
+ taps = hdev->phy_tx_taps[abs_lane_idx].nrz_taps;
+ memcpy(taps, tx_taps_set_array[set_id].nrz_taps,
+ sizeof(hdev->phy_tx_taps[abs_lane_idx].nrz_taps));
+ }
+
+ if (reset_taps) {
+ /* Here we first reset the Tx taps (setting all to zero) in order to force link
+ * down on the remote port, so it will have a "fresh start" when setting the next
+ * Tx taps set.
+ */
+ set_tx_taps(hdev, port, lane, 0, 0, 0, 0, 0, pam4);
+ msleep(100);
+ }
+
+ set_tx_taps(hdev, port, lane, taps[0], taps[1], taps[2], taps[3], taps[4], pam4);
+}
+
+static u8 get_curr_tx_taps_cfg(struct hbl_cn_device *hdev, u32 port)
+{
+ struct gaudi2_cn_port *gaudi2_port = hdev->cn_ports[port].cn_specific;
+
+ return gaudi2_port->tx_taps_cfg;
+}
+
+static void init_pam4_tx(struct hbl_cn_device *hdev, u32 port, int lane)
+{
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA1, 0x0);
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA2, 0x0);
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA3, 0x0);
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA4, 0x0);
+ /* data quite */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, 0x6320);
+ /* auto symmetric, scale */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PAF, 0xFAC9);
+ /* data, prbs */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PB0, 0x4000);
+ /* cursor -2 */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA5, 0x100);
+ /* cursor -1 */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA7, 0xF900);
+ /* cursor -main */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA9, 0x1700);
+ /* cursor +1 */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PAB, 0x0);
+ /* cursor +2 */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PAD, 0x0);
+}
+
+static void init_pam4_rx(struct hbl_cn_device *hdev, u32 port, int lane)
+{
+ /* ac-couple always */
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PF8, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_0PF8_AC_COUPLE_EN_MASK);
+}
+
+static void set_lane_mode_tx(struct hbl_cn_device *hdev, u32 port, int lane, bool pam4)
+{
+ if (pam4) {
+ /* Disable NRZ mode */
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PB0, 0x0,
+ NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_MODE_MASK);
+ /* Disable NRZ PRBS Generator */
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PB0, 0x0,
+ NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_PRBS_GEN_EN_MASK);
+ /* Enable PAM4 PRBS Generator */
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_CLK_EN_MASK);
+ } else {
+ /* Disable PAM4 PRBS Generator */
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, 0x0,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_CLK_EN_MASK);
+ /* Enable NRZ mode */
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PB0, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_MODE_MASK);
+ /* Enable NRZ PRBS Generator */
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PB0, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_PRBS_GEN_EN_MASK);
+ }
+}
+
+static void set_lane_mode_rx(struct hbl_cn_device *hdev, u32 port, int lane, bool pam4)
+{
+ if (pam4)
+ /* Enable PAM4 mode */
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P41, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_0P41_PAM4_EN_MASK);
+ else
+ /* Disable PAM4 mode */
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P41, 0x0,
+ NIC0_SERDES0_LANE0_REGISTER_0P41_PAM4_EN_MASK);
+}
+
+static void prbs_mode_select_tx(struct hbl_cn_device *hdev, u32 port, int lane, bool pam4,
+ char *mode)
+{
+ u32 val;
+
+ if (!mode || strncmp(mode, "PRBS", strlen("PRBS")))
+ return;
+
+ if (pam4) {
+ if (!strncmp(mode, "PRBS9", strlen("PRBS9")))
+ val = 0;
+ else if (!strncmp(mode, "PRBS13", strlen("PRBS13")))
+ val = 1;
+ else if (!strncmp(mode, "PRBS15", strlen("PRBS15")))
+ val = 2;
+ else /* PRBS31 */
+ val = 3;
+
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, val,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_MODE_MASK);
+ } else {
+ if (!strncmp(mode, "PRBS9", strlen("PRBS9")))
+ val = 0;
+ else if (!strncmp(mode, "PRBS15", strlen("PRBS15")))
+ val = 1;
+ else if (!strncmp(mode, "PRBS23", strlen("PRBS23")))
+ val = 2;
+ else /* PRBS31 */
+ val = 3;
+
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, val,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_MODE_MASK);
+ }
+
+ val = pam4 ? 0 : 1;
+
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PB0, val,
+ NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_PRBS_CLK_EN_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PB0, val,
+ NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_PRBS_GEN_EN_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PB0, val,
+ NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_NRZ_MODE_MASK);
+
+ if (pam4)
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PB0, 0x0,
+ NIC0_SERDES0_LANE0_REGISTER_0PB0_TX_HALF_RATE_EN_MASK);
+
+ val = pam4 ? 1 : 0;
+
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_TEST_DATA_SRC_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, val,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_CLK_EN_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PAM4_TEST_EN_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, val,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_GEN_EN_MASK);
+}
+
+static void prbs_mode_select_rx(struct hbl_cn_device *hdev, u32 port, int lane, bool pam4,
+ char *mode)
+{
+ u32 val;
+
+ if (!mode || strncmp(mode, "PRBS", strlen("PRBS")))
+ return;
+
+ if (pam4) {
+ if (!strncmp(mode, "PRBS9", strlen("PRBS9")))
+ val = 0;
+ else if (!strncmp(mode, "PRBS13", strlen("PRBS13")))
+ val = 1;
+ else if (!strncmp(mode, "PRBS15", strlen("PRBS15")))
+ val = 2;
+ else /* PRBS31 */
+ val = 3;
+
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P43, val,
+ NIC0_SERDES0_LANE0_REGISTER_0P43_PRBS_MODE_SEL_MASK);
+ } else {
+ if (!strncmp(mode, "PRBS9", strlen("PRBS9")))
+ val = 0;
+ else if (!strncmp(mode, "PRBS15", strlen("PRBS15")))
+ val = 1;
+ else if (!strncmp(mode, "PRBS23", strlen("PRBS23")))
+ val = 2;
+ else /* PRBS31 */
+ val = 3;
+
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0N61, val,
+ NIC0_SERDES0_LANE0_REGISTER_0N61_NRZ_PRBS_MODE_SEL_MASK);
+ }
+
+ if (pam4) {
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P43, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_0P43_PU_PRBS_CHKR_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P43, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_0P43_PU_PRBS_SYNC_CHKR_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P43, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_0P43_RX_PRBS_AUTO_SYNC_EN_MASK);
+ } else {
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0N61, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_0N61_PRBS_CHKR_EN_MASK);
+ }
+}
+
+static void set_default_polarity_values(struct hbl_cn_device *hdev)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ enum gaudi2_setup_type setup_type;
+ u64 pol_tx, pol_rx;
+
+ setup_type = gaudi2->setup_type;
+
+ if (hdev->skip_phy_pol_cfg)
+ return;
+
+ switch (setup_type) {
+ case GAUDI2_SETUP_TYPE_HLS2:
+ pol_tx = NIC_PHY_TX_POL_MASK_HL225 ^ NIC_PHY_TX_POL_MASK_HLS2;
+ pol_rx = NIC_PHY_RX_POL_MASK_HL225 ^ NIC_PHY_RX_POL_MASK_HLS2;
+ break;
+ default:
+ dev_err(hdev->dev, "Wrong setup type %d\n", setup_type);
+ return;
+ }
+
+ hdev->pol_tx_mask = pol_tx;
+ hdev->pol_rx_mask = pol_rx;
+}
+
+static void set_default_mac_lane_remap(struct hbl_cn_device *hdev)
+{
+ memcpy(hdev->mac_lane_remap, default_cn_mac_lane_remap,
+ sizeof(default_cn_mac_lane_remap));
+}
+
+static s32 get_pam4_tap_pre2(struct hbl_cn_device *hdev, u32 card_location, u32 abs_lane_idx)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ enum gaudi2_setup_type setup_type;
+
+ setup_type = gaudi2->setup_type;
+
+ switch (setup_type) {
+ case GAUDI2_SETUP_TYPE_HLS2:
+ return tx_taps_set_array[NIC_PHY_DEFAULT_TX_TAPS_DEFAULT].pam4_taps[0];
+ default:
+ dev_err(hdev->dev, "Wrong setup type %d\n", setup_type);
+ }
+
+ return 2;
+}
+
+static s32 get_pam4_tap_pre1(struct hbl_cn_device *hdev, u32 card_location, u32 abs_lane_idx)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ enum gaudi2_setup_type setup_type;
+
+ setup_type = gaudi2->setup_type;
+
+ switch (setup_type) {
+ case GAUDI2_SETUP_TYPE_HLS2:
+ return tx_taps_set_array[NIC_PHY_DEFAULT_TX_TAPS_DEFAULT].pam4_taps[1];
+ default:
+ dev_err(hdev->dev, "Wrong setup type %d\n", setup_type);
+ }
+
+ return -12;
+}
+
+static s32 get_pam4_tap_main(struct hbl_cn_device *hdev, u32 card_location, u32 abs_lane_idx)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ enum gaudi2_setup_type setup_type;
+
+ setup_type = gaudi2->setup_type;
+
+ switch (setup_type) {
+ case GAUDI2_SETUP_TYPE_HLS2:
+ return tx_taps_set_array[NIC_PHY_DEFAULT_TX_TAPS_DEFAULT].pam4_taps[2];
+ default:
+ dev_err(hdev->dev, "Wrong setup type %d\n", setup_type);
+ }
+
+ return 22;
+}
+
+static s32 get_pam4_tap_post1(struct hbl_cn_device *hdev, u32 card_location, u32 abs_lane_idx)
+{
+ return tx_taps_set_array[NIC_PHY_DEFAULT_TX_TAPS_DEFAULT].pam4_taps[3];
+}
+
+static s32 get_pam4_tap_post2(struct hbl_cn_device *hdev, u32 card_location, u32 abs_lane_idx)
+{
+ return tx_taps_set_array[NIC_PHY_DEFAULT_TX_TAPS_DEFAULT].pam4_taps[4];
+}
+
+static void set_default_tx_taps_values(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_properties *cn_props = &hdev->cn_props;
+ u32 card_location;
+ int abs_lane_idx;
+ s32 *taps;
+
+ card_location = hdev->card_location;
+
+ for (abs_lane_idx = 0; abs_lane_idx < cn_props->max_num_of_lanes; abs_lane_idx++) {
+ /* PAM4 */
+ taps = hdev->phy_tx_taps[abs_lane_idx].pam4_taps;
+ taps[0] = get_pam4_tap_pre2(hdev, card_location, abs_lane_idx);
+ taps[1] = get_pam4_tap_pre1(hdev, card_location, abs_lane_idx);
+ taps[2] = get_pam4_tap_main(hdev, card_location, abs_lane_idx);
+ taps[3] = get_pam4_tap_post1(hdev, card_location, abs_lane_idx);
+ taps[4] = get_pam4_tap_post2(hdev, card_location, abs_lane_idx);
+
+ /* NRZ */
+ taps = hdev->phy_tx_taps[abs_lane_idx].nrz_taps;
+ taps[0] = tx_taps_set_array[NIC_PHY_DEFAULT_TX_TAPS_DEFAULT].nrz_taps[0];
+ taps[1] = tx_taps_set_array[NIC_PHY_DEFAULT_TX_TAPS_DEFAULT].nrz_taps[1];
+ taps[2] = tx_taps_set_array[NIC_PHY_DEFAULT_TX_TAPS_DEFAULT].nrz_taps[2];
+ taps[3] = tx_taps_set_array[NIC_PHY_DEFAULT_TX_TAPS_DEFAULT].nrz_taps[3];
+ taps[4] = tx_taps_set_array[NIC_PHY_DEFAULT_TX_TAPS_DEFAULT].nrz_taps[4];
+ }
+}
+
+static void set_pol_tx(struct hbl_cn_device *hdev, u32 port, int lane, u32 tx_pol)
+{
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, tx_pol,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_ANA_OUT_FLIP_MASK);
+}
+
+static void set_pol_rx(struct hbl_cn_device *hdev, u32 port, int lane, u32 rx_pol)
+{
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P43, rx_pol,
+ NIC0_SERDES0_LANE0_REGISTER_0P43_RX_DATA_FLIP_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0N61, rx_pol,
+ NIC0_SERDES0_LANE0_REGISTER_0N61_PRBS_CHECK_FLIP_MASK);
+}
+
+static void set_gc_tx(struct hbl_cn_device *hdev, u32 port, int lane, u32 tx_gc)
+{
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PAF, tx_gc,
+ NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_GRAYCODE_EN_MASK);
+}
+
+static void set_gc_rx(struct hbl_cn_device *hdev, u32 port, int lane, u32 rx_gc)
+{
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P42, rx_gc,
+ NIC0_SERDES0_LANE0_REGISTER_0P42_RX_GRAYCODE_EN_MASK);
+}
+
+static void set_pc_tx(struct hbl_cn_device *hdev, u32 port, int lane, u32 tx_pc)
+{
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PAF, tx_pc,
+ NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_PRECODE_EN_MASK);
+}
+
+static void set_pc_rx(struct hbl_cn_device *hdev, u32 port, int lane, u32 rx_pc)
+{
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P42, rx_pc,
+ NIC0_SERDES0_LANE0_REGISTER_0P42_RX_PRECODE_EN_MASK);
+}
+
+static void set_msblsb_tx(struct hbl_cn_device *hdev, u32 port, int lane, u32 tx_msblsb)
+{
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PAF, tx_msblsb,
+ NIC0_SERDES0_LANE0_REGISTER_0PAF_TX_SWAP_MSB_LSB_MASK);
+}
+
+static void set_msblsb_rx(struct hbl_cn_device *hdev, u32 port, int lane, u32 rx_msblsb)
+{
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P43, rx_msblsb,
+ NIC0_SERDES0_LANE0_REGISTER_0P43_RX_SWAP_MSB_LSB_MASK);
+}
+
+static void init_lane_for_fw_tx(struct hbl_cn_device *hdev, u32 port, int lane, bool pam4,
+ bool do_lt)
+{
+ u32 abs_lane_idx, tx_pol, tx_gc, tx_msblsb;
+
+ abs_lane_idx = (port << 1) + lane;
+ tx_pol = (hdev->pol_tx_mask >> abs_lane_idx) & 1;
+
+ tx_gc = (pam4 && !do_lt) ? 1 : 0;
+ tx_msblsb = do_lt ? 1 : 0;
+
+ set_lane_mode_tx(hdev, port, lane, pam4);
+ set_gc_tx(hdev, port, lane, tx_gc);
+ set_pc_tx(hdev, port, lane, 0);
+ set_msblsb_tx(hdev, port, lane, tx_msblsb);
+ set_pol_tx(hdev, port, lane, tx_pol);
+}
+
+static void init_lane_for_fw_rx(struct hbl_cn_device *hdev, u32 port, int lane, bool pam4,
+ bool do_lt)
+{
+ u32 abs_lane_idx, rx_pol, rx_gc, rx_msblsb;
+
+ abs_lane_idx = (port << 1) + lane;
+ rx_pol = (hdev->pol_rx_mask >> abs_lane_idx) & 1;
+
+ rx_gc = (pam4 && !do_lt) ? 1 : 0;
+ rx_msblsb = do_lt ? 1 : 0;
+
+ set_lane_mode_rx(hdev, port, lane, pam4);
+ set_gc_rx(hdev, port, lane, rx_gc);
+ set_pc_rx(hdev, port, lane, 0);
+ set_msblsb_rx(hdev, port, lane, rx_msblsb);
+ set_pol_rx(hdev, port, lane, rx_pol);
+}
+
+static void set_functional_mode_lane(struct hbl_cn_device *hdev, u32 port, int lane, bool do_lt)
+{
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, 0,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_CLK_EN_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, 0,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PAM4_TEST_EN_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, 0,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PRBS_GEN_EN_MASK);
+
+ if (do_lt)
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_AN10, 0x5);
+ else
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_AN10, 0);
+}
+
+static void set_functional_mode(struct hbl_cn_device *hdev, u32 port)
+{
+ struct hbl_cn_port *cn_port = &hdev->cn_ports[port];
+ int lane, tx_lane;
+ u32 tx_port;
+ bool do_lt;
+
+ do_lt = cn_port->auto_neg_enable;
+
+ for (lane = 0; lane < 2; lane++) {
+ get_tx_port_and_lane(hdev, port, lane, &tx_port, &tx_lane);
+ set_functional_mode_lane(hdev, tx_port, tx_lane, do_lt);
+ }
+
+ cn_port->phy_func_mode_en = true;
+}
+
+static u32 get_fw_reg(struct hbl_cn_device *hdev, u32 port, u32 fw_addr)
+{
+ u32 ignore;
+
+ fw_cmd(hdev, port, 0xE010, &fw_addr, 0xE, &ignore);
+
+ return NIC_PHY_RREG32(NIC0_SERDES0_REGISTER_9812);
+}
+
+static int set_fw_reg(struct hbl_cn_device *hdev, u32 port, u32 fw_addr, u32 val)
+{
+ u32 ignore;
+
+ NIC_PHY_WREG32(NIC0_SERDES0_REGISTER_9812, val);
+
+ return fw_cmd(hdev, port, 0xE020, &fw_addr, 0xE, &ignore);
+}
+
+static void enable_lane_swapping(struct hbl_cn_device *hdev, u32 port, int lane, bool do_an,
+ bool do_lt)
+{
+ if (do_an || do_lt)
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_AJ40, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_AJ40_ANLT_LANE_SWAPPING_EN_MASK);
+
+ if (do_an)
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_AJ40, 0x0, 0x40);
+}
+
+static void disable_lane_swapping(struct hbl_cn_device *hdev, u32 port, int lane, bool do_an,
+ bool do_lt)
+{
+ if (do_an)
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_AJ40, 0x0,
+ NIC0_SERDES0_LANE0_REGISTER_AJ40_ANLT_LANE_SWAPPING_EN_MASK);
+}
+
+static void lane_swapping_config(struct hbl_cn_device *hdev, u32 port, int lane, bool do_an,
+ bool do_lt)
+{
+ u32 tx_port, lt_option;
+ int tx_lane;
+
+ get_tx_port_and_lane(hdev, port, lane, &tx_port, &tx_lane);
+
+ lt_option = get_fw_reg(hdev, port, 366);
+
+ if (is_lane_swapping(hdev, port, lane)) {
+ enable_lane_swapping(hdev, tx_port, tx_lane, do_an, do_lt);
+ enable_lane_swapping(hdev, port, lane, do_an, do_lt);
+
+ lt_option |= (1 << (3 + 8 * (1 - lane)));
+ } else {
+ disable_lane_swapping(hdev, tx_port, tx_lane, do_an, do_lt);
+ disable_lane_swapping(hdev, port, lane, do_an, do_lt);
+
+ lt_option &= ~(1 << (3 + 8 * (1 - lane)));
+ }
+
+ set_fw_reg(hdev, port, 366, lt_option);
+}
+
+static int fw_start(struct hbl_cn_device *hdev, u32 port, int lane, bool pam4, bool do_lt)
+{
+ u32 cmd, speed, ignore;
+
+ cmd = pam4 ? (0x80D0 | lane) : (0x80C0 | lane);
+ speed = pam4 ? 0x9 : 0x3;
+
+ if (do_lt)
+ speed |= 0x100;
+
+ return fw_cmd(hdev, port, cmd, &speed, 0x8, &ignore);
+}
+
+static int fw_start_tx(struct hbl_cn_device *hdev, u32 port, int lane, bool pam4, bool do_lt)
+{
+ u32 speed, cmd, ignore;
+ int rc;
+
+ speed = pam4 ? 0x9 : 0x3;
+
+ if (pam4)
+ cmd = do_lt ? (0x7030 | lane) : (0x7010 | lane);
+ else
+ cmd = do_lt ? (0x7020 | lane) : (0x7000 | lane);
+
+ rc = fw_cmd(hdev, port, cmd, &speed, 0x7, &ignore);
+ if (rc)
+ return rc;
+
+ if (do_lt)
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_RSVD_0PA0_04_MASK);
+
+ return 0;
+}
+
+static int fw_config_vcocap(struct hbl_cn_device *hdev, u32 port, int lane, u32 mode,
+ u32 counter_value)
+{
+ u32 ignore;
+
+ return fw_cmd(hdev, port, 0x6000 | (mode << 4) | lane, &counter_value, 14, &ignore);
+}
+
+static int set_pll_tx(struct hbl_cn_device *hdev, u32 port, int lane, u32 data_rate)
+{
+ u32 card_location, msbc, lsbc;
+ int rc;
+
+ card_location = hdev->card_location;
+
+ if (lane == 0)
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_9825, 0x0,
+ NIC0_SERDES0_REGISTER_9825_PLL_0_LOCK_32T_CLK_SEL_MASK);
+ else
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_982E, 0x0,
+ NIC0_SERDES0_REGISTER_982E_PLL_1_LOCK_32T_CLK_SEL_MASK);
+
+ switch (data_rate) {
+ case NIC_DR_50:
+ /* toggle FRACN LSB for better phase noise */
+ NIC_PHY_RMWREG32_LANE(0x54587D4, 0x0, 0x1);
+ msbc = 0x5;
+ lsbc = 0x4FFA;
+ break;
+ case NIC_DR_26:
+ /* toggle FRACN LSB for better phase noise */
+ NIC_PHY_RMWREG32_LANE(0x54587D4, 0x0, 0x1);
+ NIC_PHY_RMWREG32_LANE(0x5458320, 0x0, 0x1);
+ msbc = 0x5;
+ lsbc = 0x4FFA;
+ break;
+ case NIC_DR_25:
+ msbc = 0x5;
+ lsbc = 0x27FA;
+ break;
+ case NIC_DR_10:
+ msbc = 0x2;
+ lsbc = 0xFFD;
+ break;
+ default:
+ dev_err(hdev->dev, "Card %u Port %u lane %d: unsupported data rate\n",
+ card_location, port, lane);
+ return -EFAULT;
+ }
+
+ rc = fw_config_vcocap(hdev, port, lane, 1, msbc);
+ if (rc)
+ return rc;
+
+ rc = fw_config_vcocap(hdev, port, lane, 2, lsbc);
+ if (rc)
+ return rc;
+
+ rc = fw_config_vcocap(hdev, port, lane, 3, 0x40);
+ if (rc)
+ return rc;
+
+ rc = fw_config_vcocap(hdev, port, lane, 4, 0x0);
+ if (rc)
+ return rc;
+
+ usleep_range(500, 1000);
+
+ if (lane == 0) {
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_9825, 0x1,
+ NIC0_SERDES0_REGISTER_9825_PLL_LOCK_SRC_SEL_MASK);
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_9825, 0x0,
+ NIC0_SERDES0_REGISTER_9825_PLL_0_LOCK_EN_MASK);
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_9825, 0x1,
+ NIC0_SERDES0_REGISTER_9825_PLL_0_LOCK_EN_MASK);
+ } else {
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_9825, 0x2,
+ NIC0_SERDES0_REGISTER_9825_PLL_LOCK_SRC_SEL_MASK);
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_982E, 0x0,
+ NIC0_SERDES0_REGISTER_982E_PLL_1_LOCK_EN_MASK);
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_982E, 0x1,
+ NIC0_SERDES0_REGISTER_982E_PLL_1_LOCK_EN_MASK);
+ }
+
+ usleep_range(500, 1000);
+
+ return 0;
+}
+
+static int set_pll_rx(struct hbl_cn_device *hdev, u32 port, int lane, u32 data_rate)
+{
+ u32 card_location, msbc, lsbc, third_val;
+ int rc;
+
+ card_location = hdev->card_location;
+
+ if (lane == 0)
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_9825, 0x1,
+ NIC0_SERDES0_REGISTER_9825_PLL_0_LOCK_32T_CLK_SEL_MASK);
+ else
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_982E, 0x1,
+ NIC0_SERDES0_REGISTER_982E_PLL_1_LOCK_32T_CLK_SEL_MASK);
+
+ switch (data_rate) {
+ case NIC_DR_50:
+ case NIC_DR_26:
+ msbc = 0x5;
+ lsbc = 0x4FFA;
+ third_val = 0x30;
+ break;
+ case NIC_DR_25:
+ msbc = 0x5;
+ lsbc = 0x27FA;
+ third_val = 0x30;
+ break;
+ case NIC_DR_10:
+ msbc = 0x2;
+ lsbc = 0xFFD;
+ third_val = 0x40;
+ break;
+ default:
+ dev_err(hdev->dev, "Card %u Port %u lane %d: unsupported data rate\n",
+ card_location, port, lane);
+ return -EFAULT;
+ }
+
+ rc = fw_config_vcocap(hdev, port, lane, 1, msbc);
+ if (rc)
+ return rc;
+
+ rc = fw_config_vcocap(hdev, port, lane, 2, lsbc);
+ if (rc)
+ return rc;
+
+ rc = fw_config_vcocap(hdev, port, lane, 3, third_val);
+ if (rc)
+ return rc;
+
+ rc = fw_config_vcocap(hdev, port, lane, 4, 0x1);
+ if (rc)
+ return rc;
+
+ usleep_range(500, 1000);
+
+ if (lane == 0) {
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_9825, 0x1,
+ NIC0_SERDES0_REGISTER_9825_PLL_LOCK_SRC_SEL_MASK);
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_9825, 0x0,
+ NIC0_SERDES0_REGISTER_9825_PLL_0_LOCK_EN_MASK);
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_9825, 0x1,
+ NIC0_SERDES0_REGISTER_9825_PLL_0_LOCK_EN_MASK);
+ } else {
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_9825, 0x2,
+ NIC0_SERDES0_REGISTER_9825_PLL_LOCK_SRC_SEL_MASK);
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_982E, 0x0,
+ NIC0_SERDES0_REGISTER_982E_PLL_1_LOCK_EN_MASK);
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_982E, 0x1,
+ NIC0_SERDES0_REGISTER_982E_PLL_1_LOCK_EN_MASK);
+ }
+
+ usleep_range(500, 1000);
+
+ return 0;
+}
+
+static int set_pll(struct hbl_cn_device *hdev, u32 port, int lane, u32 data_rate)
+{
+ u32 card_location, tx_port;
+ int tx_lane, rc;
+
+ card_location = hdev->card_location;
+
+ get_tx_port_and_lane(hdev, port, lane, &tx_port, &tx_lane);
+
+ rc = set_pll_tx(hdev, tx_port, tx_lane, data_rate);
+ if (rc) {
+ dev_err(hdev->dev, "Card %u Port %u lane %d: set Tx PLL failed, rc %d\n",
+ card_location, tx_port, tx_lane, rc);
+ return rc;
+ }
+
+ rc = set_pll_rx(hdev, port, lane, data_rate);
+ if (rc) {
+ dev_err(hdev->dev, "Card %u Port %u lane %d: set Rx PLL failed, rc %d\n",
+ card_location, port, lane, rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static void set_tx_taps_scale(struct hbl_cn_device *hdev, u32 port, int lane)
+{
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PAF, 0x4, 0x3E);
+}
+
+static int fw_config_speed_pam4(struct hbl_cn_device *hdev, u32 port, int lane, bool do_lt)
+{
+ u32 tx_port, card_location, val;
+ u8 curr_tx_taps_cfg;
+ int tx_lane, rc;
+
+ card_location = hdev->card_location;
+
+ get_tx_port_and_lane(hdev, port, lane, &tx_port, &tx_lane);
+
+ init_pam4_tx(hdev, tx_port, tx_lane);
+ init_pam4_rx(hdev, port, lane);
+
+ /* Disable AN/LT lane swapping */
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_AJ40, 0x0,
+ NIC0_SERDES0_LANE0_REGISTER_AJ40_ANLT_LANE_SWAPPING_EN_MASK);
+
+ lane_swapping_config(hdev, port, lane, false, do_lt);
+
+ init_lane_for_fw_tx(hdev, tx_port, tx_lane, true, do_lt);
+ init_lane_for_fw_rx(hdev, port, lane, true, do_lt);
+
+ prbs_mode_select_tx(hdev, tx_port, tx_lane, true, "PRBS31");
+ prbs_mode_select_rx(hdev, port, lane, true, "PRBS31");
+
+ rc = fw_start(hdev, port, lane, true, do_lt);
+ if (rc) {
+ dev_err(hdev->dev,
+ "Card %u Port %u lane %d: F/W config speed PAM4 failed (LT %s), rc %d\n",
+ card_location, port, lane, do_lt ? "enabled" : "disable", rc);
+ return rc;
+ }
+
+ if (is_lane_swapping(hdev, port, lane)) {
+ rc = fw_start_tx(hdev, tx_port, tx_lane, true, do_lt);
+ if (rc) {
+ dev_err(hdev->dev,
+ "Card %u Port %u lane %d: F/W config speed PAM4 failed (LT %s), rc %d\n",
+ card_location, tx_port, tx_lane, do_lt ? "enabled" : "disable",
+ rc);
+ return rc;
+ }
+
+ if (do_lt)
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_RSVD_0PA0_04_MASK);
+ }
+
+ if (do_lt) {
+ if (!hdev->phy_calc_ber) {
+ /* tell the F/W to do LT with PCS data instead of PRBS */
+ val = get_fw_reg(hdev, port, 366);
+ val &= 0xFEFE;
+ set_fw_reg(hdev, port, 366, val);
+ }
+
+ set_tx_taps_scale(hdev, tx_port, tx_lane);
+ set_gc_tx(hdev, tx_port, tx_lane, 0);
+ set_pc_tx(hdev, tx_port, tx_lane, 0);
+ set_gc_rx(hdev, port, lane, 0);
+ set_pc_rx(hdev, port, lane, 0);
+ } else {
+ curr_tx_taps_cfg = get_curr_tx_taps_cfg(hdev, port);
+ set_tx_taps_cfg(hdev, tx_port, tx_lane, curr_tx_taps_cfg, true, false);
+ }
+
+ return 0;
+}
+
+static void init_nrz_tx(struct hbl_cn_device *hdev, u32 port, int lane)
+{
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA1, 0x0);
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA2, 0x0);
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA3, 0x0);
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA4, 0x0);
+ /* data quiet */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, 0x6320);
+ /* auto symmetric, scale */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PAF, 0xF8C9);
+ /* data, prbs */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PB0, 0x4820);
+ /* cursor -2 */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA5, 0x0);
+ /* cursor -1 */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA7, 0xFC00);
+ /* cursor -main */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA9, 0x1800);
+ /* cursor +1 */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PAB, 0x0);
+ /* cursor +2 */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PAD, 0x0);
+}
+
+static void init_nrz_rx(struct hbl_cn_device *hdev, u32 port, int lane)
+{
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PF8, 0xEC06);
+}
+
+static int fw_config_speed_nrz(struct hbl_cn_device *hdev, u32 port, int lane)
+{
+ u32 tx_port, card_location;
+ u8 curr_tx_taps_cfg;
+ int tx_lane, rc;
+
+ card_location = hdev->card_location;
+
+ get_tx_port_and_lane(hdev, port, lane, &tx_port, &tx_lane);
+
+ lane_swapping_config(hdev, port, lane, false, false);
+
+ init_nrz_tx(hdev, tx_port, tx_lane);
+ init_nrz_rx(hdev, port, lane);
+
+ init_lane_for_fw_tx(hdev, tx_port, tx_lane, false, false);
+ init_lane_for_fw_rx(hdev, port, lane, false, false);
+
+ prbs_mode_select_tx(hdev, tx_port, tx_lane, false, "PRBS31");
+ prbs_mode_select_rx(hdev, port, lane, false, "PRBS31");
+
+ rc = fw_start(hdev, port, lane, false, false);
+ if (rc) {
+ dev_err(hdev->dev,
+ "Card %u Port %u lane %d: F/W config speed NRZ failed, rc %d\n",
+ card_location, port, lane, rc);
+ return rc;
+ }
+
+ if (is_lane_swapping(hdev, port, lane)) {
+ rc = fw_start_tx(hdev, tx_port, tx_lane, false, false);
+ if (rc) {
+ dev_err(hdev->dev,
+ "Card %u Port %u lane %d: F/W config speed NRZ failed, rc %d\n",
+ card_location, tx_port, tx_lane, rc);
+ return rc;
+ }
+ }
+
+ curr_tx_taps_cfg = get_curr_tx_taps_cfg(hdev, port);
+ set_tx_taps_cfg(hdev, tx_port, tx_lane, curr_tx_taps_cfg, false, false);
+
+ return 0;
+}
+
+static void reset_mac_tx(struct hbl_cn_device *hdev, u32 port)
+{
+ struct gaudi2_cn_device *gaudi2 = hdev->asic_specific;
+ u32 tx_ch_mask;
+
+ /* For F/W version 37.1.0 and above, the reset will be done by the F/W */
+ if ((hdev->fw_major_version == 37 && hdev->fw_minor_version > 1) ||
+ hdev->fw_major_version > 37) {
+ struct gaudi2_cn_aux_ops *gaudi2_aux_ops;
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ struct cpucp_packet pkt;
+ int rc;
+
+ aux_dev = hdev->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ gaudi2_aux_ops = aux_ops->asic_ops;
+
+ memset(&pkt, 0, sizeof(pkt));
+ pkt.ctl = cpu_to_le32(CPUCP_PACKET_NIC_MAC_TX_RESET << CPUCP_PKT_CTL_OPCODE_SHIFT);
+ pkt.port_index = cpu_to_le32(port);
+
+ rc = gaudi2_aux_ops->send_cpu_message(aux_dev, (u32 *)&pkt, sizeof(pkt), 0, NULL);
+ if (rc)
+ dev_warn(hdev->dev, "Card %u Port %u: Failed to reset MAC Tx, rc %d\n",
+ hdev->card_location, port, rc);
+
+ return;
+ }
+
+ if (gaudi2->fw_security_enabled) {
+ dev_warn(hdev->dev, "Card %u Port %u: Failed to reset MAC Tx, security is enabled.\n",
+ hdev->card_location, port);
+ return;
+ }
+
+ tx_ch_mask = 1 << PRT0_MAC_CORE_MAC_RST_CFG_SD_TX_SW_RST_N_SHIFT;
+ tx_ch_mask <<= (port & 0x1) ? 2 : 0;
+
+ NIC_MACRO_RMWREG32(PRT0_MAC_CORE_MAC_RST_CFG, 0, tx_ch_mask);
+ msleep(100);
+ NIC_MACRO_RMWREG32(PRT0_MAC_CORE_MAC_RST_CFG, 1, tx_ch_mask);
+}
+
+static int fw_config(struct hbl_cn_device *hdev, u32 port, u32 data_rate, bool do_lt)
+{
+ u32 card_location;
+ int lane, rc;
+ bool pam4;
+
+ card_location = hdev->card_location;
+ pam4 = (data_rate == NIC_DR_50);
+
+ /* clear go bit */
+ if (pam4) {
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_980F, 0x1, 0x800);
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_980F, 0x1, 0x100);
+ }
+
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_980F, 0x0, 0x8000);
+
+ for (lane = 0; lane < 2; lane++) {
+ if (pam4) {
+ rc = fw_config_speed_pam4(hdev, port, lane, do_lt);
+ if (rc) {
+ dev_err(hdev->dev,
+ "Card %u Port %u lane %d: F/W PAM4 config failed, rc %d\n",
+ card_location, port, lane, rc);
+ return rc;
+ }
+
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PEA, 0x60,
+ NIC0_SERDES0_LANE0_REGISTER_0PEA_VDACCLKPHASE0_MASK);
+ } else {
+ rc = fw_config_speed_nrz(hdev, port, lane);
+ if (rc) {
+ dev_err(hdev->dev,
+ "Card %u Port %u lane %d: F/W NRZ config failed, rc %d\n",
+ card_location, port, lane, rc);
+ return rc;
+ }
+ }
+ }
+
+ for (lane = 0; lane < 2; lane++) {
+ rc = set_pll(hdev, port, lane, data_rate);
+ if (rc)
+ return rc;
+ }
+
+ msleep(100);
+
+ reset_mac_tx(hdev, port);
+
+ if (!hdev->phy_calc_ber)
+ set_functional_mode(hdev, port);
+
+ /* set go bit */
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_980F, 0x1, 0x8000);
+
+ return 0;
+}
+
+static void phy_port_reset(struct hbl_cn_device *hdev, u32 port)
+{
+ int lane;
+
+ soft_reset(hdev, port);
+ usleep_range(500, 1000);
+
+ for (lane = 0; lane < 2; lane++)
+ clock_init(hdev, port, lane);
+
+ cpu_reset(hdev, port);
+ logic_reset(hdev, port);
+
+ usleep_range(500, 1000);
+}
+
+static void prbs_reset(struct hbl_cn_port *cn_port, int lane, bool pam4)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P43, 1,
+ NIC0_SERDES0_LANE0_REGISTER_0P43_RX_PRBS_AUTO_SYNC_EN_MASK);
+
+ if (pam4) {
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P43, 1,
+ NIC0_SERDES0_LANE0_REGISTER_0P43_PRBS_SYNC_CNTR_RESET_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P43, 0,
+ NIC0_SERDES0_LANE0_REGISTER_0P43_PRBS_SYNC_CNTR_RESET_MASK);
+ } else {
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0N61, 1,
+ NIC0_SERDES0_LANE0_REGISTER_0N61_PRBS_CNTR_RESET_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0N61, 0,
+ NIC0_SERDES0_LANE0_REGISTER_0N61_PRBS_CNTR_RESET_MASK);
+ }
+
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P43, 0,
+ NIC0_SERDES0_LANE0_REGISTER_0P43_RX_PRBS_AUTO_SYNC_EN_MASK);
+}
+
+static u64 _get_prbs_cnt(struct hbl_cn_port *cn_port, int lane, bool pam4)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+ u64 cnt;
+
+ if (pam4)
+ cnt = (((u64)NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P50)) << 16) +
+ NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P51);
+ else
+ cnt = (((u64)NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0N66)) << 16) +
+ NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0N67);
+
+ return cnt;
+}
+
+static enum lane_state get_prbs_cnt(struct hbl_cn_port *cn_port, int lane, bool pam4,
+ u64 prbs_prev_cnt, u64 *prbs_new_cnt)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port, phy_ready;
+ u64 cnt;
+
+ if (pam4) {
+ phy_ready = (NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P6A) &
+ NIC0_SERDES0_LANE0_REGISTER_0P6A_RX_READ_PHY_READY_MASK) >>
+ NIC0_SERDES0_LANE0_REGISTER_0P6A_RX_READ_PHY_READY_SHIFT;
+ } else {
+ phy_ready = (NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0N2E) &
+ NIC0_SERDES0_LANE0_REGISTER_0N2E_NRZ_READ_PHY_READY_MASK) >>
+ NIC0_SERDES0_LANE0_REGISTER_0N2E_NRZ_READ_PHY_READY_SHIFT;
+ }
+
+ if (!phy_ready)
+ return NOT_READY;
+
+ cnt = _get_prbs_cnt(cn_port, lane, pam4);
+
+ /* check PRBS counter wrapped around */
+ if (cnt < prbs_prev_cnt) {
+ if ((prbs_prev_cnt - cnt) < 0x10000)
+ return FAILURE;
+
+ cnt = _get_prbs_cnt(cn_port, lane, pam4);
+ }
+
+ *prbs_new_cnt = cnt;
+
+ return READY;
+}
+
+static void _calc_ber_lane(struct hbl_cn_port *cn_port, int lane, u64 total_cnt, u64 error_cnt,
+ struct hbl_cn_ber_info *ber_info)
+{
+ u64 total_high_digits, error_high_digits, integer, frac;
+ u8 total_num_digits, error_num_digits, exp;
+ int i;
+
+ total_num_digits = hbl_cn_get_num_of_digits(total_cnt);
+ error_num_digits = hbl_cn_get_num_of_digits(error_cnt);
+
+ if (total_num_digits > 2) {
+ total_high_digits = total_cnt;
+
+ for (i = 0; i < total_num_digits - 2; i++)
+ total_high_digits = total_high_digits / 10;
+ } else {
+ total_high_digits = total_cnt;
+ }
+
+ if (!total_high_digits)
+ return;
+
+ if (error_num_digits > 2) {
+ error_high_digits = error_cnt;
+
+ for (i = 0; i < error_num_digits - 2; i++)
+ error_high_digits = error_high_digits / 10;
+ } else {
+ error_high_digits = error_cnt;
+ }
+
+ exp = total_num_digits - error_num_digits;
+
+ if (error_high_digits < total_high_digits) {
+ error_high_digits *= 10;
+ exp++;
+ }
+
+ integer = div_u64(error_high_digits, total_high_digits);
+ frac = div_u64(((error_high_digits - (integer * total_high_digits)) * 10),
+ total_high_digits);
+
+ ber_info->integer = integer;
+ ber_info->frac = frac;
+ ber_info->exp = exp;
+ ber_info->valid = true;
+}
+
+static void calc_ber_lane(struct hbl_cn_port *cn_port, int lane, bool pam4)
+{
+ u64 prbs_err_cnt_pre, prbs_prev_cnt, prbs_err_cnt_post, prbs_err_cnt,
+ prbs_reset_time_jiffies, prbs_accum_time_jiffies, prbs_accum_time_ms,
+ factor, error_cnt, total_cnt;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 card_location, port, abs_lane_idx;
+ struct hbl_cn_ber_info *ber_info;
+ enum lane_state state;
+
+ card_location = hdev->card_location;
+ port = cn_port->port;
+ abs_lane_idx = (port << 1) + lane;
+
+ ber_info = &hdev->phy_ber_info[abs_lane_idx];
+ memset(ber_info, 0, sizeof(*ber_info));
+
+ prbs_reset(cn_port, lane, pam4);
+ prbs_reset_time_jiffies = jiffies;
+ prbs_err_cnt_pre = _get_prbs_cnt(cn_port, lane, pam4);
+ prbs_err_cnt_post = 0;
+
+ prbs_prev_cnt = prbs_err_cnt_pre;
+
+ while (true) {
+ msleep(500);
+
+ state = get_prbs_cnt(cn_port, lane, pam4, prbs_prev_cnt, &prbs_err_cnt_post);
+ prbs_accum_time_jiffies = jiffies - prbs_reset_time_jiffies;
+ prbs_accum_time_ms = jiffies_to_msecs(prbs_accum_time_jiffies);
+ prbs_err_cnt = prbs_err_cnt_post - prbs_err_cnt_pre;
+
+ if (state != READY) {
+ dev_dbg(hdev->dev, "Card %u Port %u lane %d: No BER (state = %s)\n",
+ card_location, port, lane,
+ (state == NOT_READY) ? "NOT_READY" : "FAILURE");
+ return;
+ }
+
+ if (prbs_accum_time_ms >= 5000 || prbs_err_cnt >= 10000000)
+ break;
+
+ prbs_prev_cnt = prbs_err_cnt_post;
+ }
+
+ factor = pam4 ? NIC_PHY_PAM4_BER_FACTOR : NIC_PHY_NRZ_BER_FACTOR;
+
+ error_cnt = prbs_err_cnt;
+ total_cnt = prbs_accum_time_ms * factor;
+
+ _calc_ber_lane(cn_port, lane, total_cnt, error_cnt, ber_info);
+
+ dev_dbg(hdev->dev,
+ "Card %u Port %u lane %d: total_cnt %llu error_cnt %llu (%llu ms) - BER %llu.%llue-%u\n",
+ card_location, port, lane, total_cnt, error_cnt, prbs_accum_time_ms,
+ ber_info->integer, ber_info->frac, ber_info->exp);
+}
+
+static void calc_ber(struct hbl_cn_port *cn_port)
+{
+ int lane;
+
+ for (lane = 0; lane < 2; lane++)
+ calc_ber_lane(cn_port, lane, cn_port->data_rate == NIC_DR_50);
+}
+
+static void get_tx_port_lane(u32 port, int lane, u32 *_port, int *_lane)
+{
+ if (port != 0 && port != 1) {
+ *_port = port;
+ *_lane = lane;
+ return;
+ }
+
+ if (port == 0 && lane == 0) {
+ *_port = 1;
+ *_lane = 1;
+ } else if (port == 0 && lane == 1) {
+ *_port = 0;
+ *_lane = 1;
+ } else if (port == 1 && lane == 0) {
+ *_port = 0;
+ *_lane = 0;
+ } else if (port == 1 && lane == 1) {
+ *_port = 1;
+ *_lane = 0;
+ }
+}
+
+static void modify_tx_taps(struct hbl_cn_port *cn_port)
+{
+ struct gaudi2_cn_port *gaudi2_port = cn_port->cn_specific;
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u8 curr_cfg, next_cfg;
+ u32 port, _port;
+ int lane, _lane;
+ bool pam4;
+
+ port = cn_port->port;
+ curr_cfg = get_curr_tx_taps_cfg(hdev, port);
+ next_cfg = (curr_cfg + 1) % tx_taps_num_cfgs;
+ pam4 = cn_port->data_rate == NIC_DR_50;
+ _port = 0;
+ _lane = 0;
+
+ gaudi2_port->tx_taps_cfg = next_cfg;
+
+ /* If the next cfg equals the initial cfg, it means that we went through all the taps cfgs.
+ * In that case, PHY reconfigure should be triggered.
+ */
+ if (next_cfg == gaudi2_port->initial_tx_taps_cfg) {
+ dev_dbg(hdev->dev,
+ "Card %u Port %u: all tx taps cfgs were failed - reconfiguring PHY\n",
+ hdev->card_location, port);
+
+ return hbl_cn_phy_port_reconfig(cn_port);
+ }
+
+ dev_dbg(hdev->dev, "Card %u Port %u: modify %s tx taps (%u,%u)->(%u,%u)\n",
+ hdev->card_location, port, pam4 ? "PAM4" : "NRZ",
+ tx_taps_cfg_array[curr_cfg][0] + 1, tx_taps_cfg_array[curr_cfg][1] + 1,
+ tx_taps_cfg_array[next_cfg][0] + 1, tx_taps_cfg_array[next_cfg][1] + 1);
+
+ for (lane = 0; lane < 2; lane++) {
+ get_tx_port_lane(port, lane, &_port, &_lane);
+ set_tx_taps_cfg(hdev, _port, _lane, next_cfg, pam4, true);
+ }
+
+ gaudi2_port->tx_taps_modified = true;
+}
+
+static void print_final_tx_taps(struct hbl_cn_port *cn_port)
+{
+ char tx_taps_str0[25] = {0}, tx_taps_str1[25] = {0};
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port, abs_lane0_idx, abs_lane1_idx;
+ s32 *taps;
+ bool pam4;
+
+ pam4 = cn_port->data_rate == NIC_DR_50;
+ port = cn_port->port;
+ abs_lane0_idx = port << 1;
+ abs_lane1_idx = abs_lane0_idx + 1;
+
+ taps = pam4 ? hdev->phy_tx_taps[abs_lane0_idx].pam4_taps :
+ hdev->phy_tx_taps[abs_lane0_idx].nrz_taps;
+ sprintf(tx_taps_str0, "%d,%d,%d,%d,%d", taps[0], taps[1], taps[2], taps[3], taps[4]);
+
+ taps = pam4 ? hdev->phy_tx_taps[abs_lane1_idx].pam4_taps :
+ hdev->phy_tx_taps[abs_lane1_idx].nrz_taps;
+ sprintf(tx_taps_str1, "%d,%d,%d,%d,%d", taps[0], taps[1], taps[2], taps[3], taps[4]);
+
+ dev_dbg(hdev->dev, "Card %u Port %u: Final Tx taps - lane0: [%s], lane1: [%s]\n",
+ hdev->card_location, port, tx_taps_str0, tx_taps_str1);
+}
+
+static void change_pcs_link_state(struct gaudi2_cn_port *gaudi2_port,
+ enum gaudi2_cn_pcs_link_state pcs_link_state)
+{
+ struct hbl_cn_port *cn_port = gaudi2_port->cn_port;
+
+ gaudi2_port->pcs_link_state = pcs_link_state;
+
+ /* The retry count is being incremented in a different frequency in every state.
+ * Therefore, in order to have a logical value in each state, it needs to be reset when
+ * moving to a new state.
+ */
+ cn_port->retry_cnt = 0;
+}
+
+static void check_pcs_link(struct hbl_cn_port *cn_port)
+{
+ u32 card_location, port, mac_gnrl_sts, pcs_link_samples_per_sec, link_down_cnt_th,
+ remote_fault_cnt_th, link_toggles;
+ enum gaudi2_cn_pcs_link_state pcs_link_state;
+ struct gaudi2_cn_port *gaudi2_port;
+ struct hbl_cn_device *hdev;
+
+ hdev = cn_port->hdev;
+ gaudi2_port = cn_port->cn_specific;
+ card_location = hdev->card_location;
+ port = cn_port->port;
+ pcs_link_state = gaudi2_port->pcs_link_state;
+
+ if (pcs_link_state == PCS_LINK_STATE_SETTLING) {
+ if (cn_port->eth_enable) {
+ change_pcs_link_state(gaudi2_port, PCS_LINK_STATE_STEADY);
+ } else {
+ change_pcs_link_state(gaudi2_port, PCS_LINK_STATE_STRESS);
+ gaudi2_port->pcs_link_stady_state_ts =
+ ktime_add_ms(ktime_get(), NIC_PHY_PCS_STRESS_WINDOW_MS);
+ }
+
+ return;
+ }
+
+ mac_gnrl_sts = (port & 0x1) ? NIC_MACRO_RREG32(PRT0_MAC_CORE_MAC_GNRL_STS_2) :
+ NIC_MACRO_RREG32(PRT0_MAC_CORE_MAC_GNRL_STS_0);
+
+ if (FIELD_GET(PRT0_MAC_CORE_MAC_GNRL_STS_LOC_FAULT_MASK, mac_gnrl_sts))
+ cn_port->pcs_local_fault_cnt++;
+
+ if (FIELD_GET(PRT0_MAC_CORE_MAC_GNRL_STS_REM_FAULT_MASK, mac_gnrl_sts)) {
+ cn_port->pcs_remote_fault_cnt++;
+ cn_port->pcs_remote_fault_seq_cnt++;
+ } else {
+ cn_port->pcs_remote_fault_seq_cnt = 0;
+ }
+
+ pcs_link_samples_per_sec = gaudi2_port->pcs_link_samples_per_sec;
+ remote_fault_cnt_th = NIC_PHY_MAC_REMOTE_FAULT_TH_S * pcs_link_samples_per_sec;
+
+ if (pcs_link_state == PCS_LINK_STATE_STRESS) {
+ if (ktime_after(ktime_get(), gaudi2_port->pcs_link_stady_state_ts)) {
+ change_pcs_link_state(gaudi2_port, PCS_LINK_STATE_STEADY);
+ goto check_link;
+ }
+
+ if (cn_port->pcs_remote_fault_seq_cnt) {
+ dev_dbg(hdev->dev, "Card %u Port %u: got MAC remote fault during stress window\n",
+ card_location, port);
+
+ modify_tx_taps(cn_port);
+ change_pcs_link_state(gaudi2_port, PCS_LINK_STATE_SETTLING);
+ cn_port->pcs_remote_fault_seq_cnt = 0;
+ }
+ } else { /* PCS_LINK_STATE_STEADY */
+ if (gaudi2_port->tx_taps_modified) {
+ print_final_tx_taps(cn_port);
+ gaudi2_port->tx_taps_modified = false;
+ }
+
+ if (cn_port->pcs_remote_fault_seq_cnt == remote_fault_cnt_th) {
+ dev_dbg(hdev->dev,
+ "Card %u Port %u: %u sequential seconds of MAC remote faults\n",
+ card_location, port, NIC_PHY_MAC_REMOTE_FAULT_TH_S);
+
+ /* Modify tx taps - external ports are excluded */
+ if (!cn_port->eth_enable) {
+ modify_tx_taps(cn_port);
+ change_pcs_link_state(gaudi2_port, PCS_LINK_STATE_SETTLING);
+ }
+
+ cn_port->pcs_remote_fault_seq_cnt = 0;
+ }
+ }
+
+check_link:
+ link_toggles = cn_port->port_toggle_cnt - cn_port->port_toggle_cnt_prev;
+ cn_port->port_toggle_cnt_prev = cn_port->port_toggle_cnt;
+
+ /* The condition to reset the retry_cnt is that the link is UP, and if in steady state,
+ * only if the link toggling threshold is not exceeded.
+ */
+ if (cn_port->pcs_link && !(pcs_link_state == PCS_LINK_STATE_STEADY &&
+ link_toggles > NIC_PHY_PCS_MAX_LINK_TOGGLES)) {
+ cn_port->retry_cnt = 0;
+ return;
+ }
+
+ cn_port->retry_cnt++;
+ link_down_cnt_th = NIC_PHY_PCS_LINK_DOWN_TH_S * pcs_link_samples_per_sec;
+
+ if (cn_port->retry_cnt == link_down_cnt_th) {
+ dev_dbg(hdev->dev,
+ "Card %u Port %u: %u sequential seconds of PCS link down - reconfiguring PHY\n",
+ card_location, port, NIC_PHY_PCS_LINK_DOWN_TH_S);
+
+ hbl_cn_phy_port_reconfig(cn_port);
+ }
+}
+
+static u32 rv_debug(struct hbl_cn_device *hdev, u32 port, int lane, u32 mode, u32 index)
+{
+ u32 cmd, res;
+
+ cmd = 0xB000 + ((mode & 0xF) << 4) + lane;
+
+ fw_cmd(hdev, port, cmd, &index, 0xB, &res);
+
+ return NIC_PHY_RREG32(NIC0_SERDES0_REGISTER_9816);
+}
+
+static int fw_tuning(struct hbl_cn_device *hdev, u32 port, int lane, bool pam4)
+{
+ u32 state, mode;
+
+ mode = pam4 ? 2 : 1;
+ state = rv_debug(hdev, port, lane, mode, 0);
+
+ if (pam4) {
+ if (((u16)state) != 0x8F00 && ((u16)state) != 0x8F80)
+ return -EAGAIN;
+ } else {
+ if (((u16)state) != 0x9A00)
+ return -EAGAIN;
+ }
+
+ return 0;
+}
+
+static void do_fw_tuning(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 card_location, port;
+ int lane, rc;
+ bool pam4;
+
+ card_location = hdev->card_location;
+ port = cn_port->port;
+ pam4 = (cn_port->data_rate == NIC_DR_50);
+
+ for (lane = 0; lane < 2; lane++) {
+ rc = fw_tuning(hdev, port, lane, pam4);
+ if (rc) {
+ if (ktime_after(ktime_get(), cn_port->fw_tuning_limit_ts)) {
+ dev_dbg(hdev->dev,
+ "Card %u Port %u lane %d: F/W tuning limit - reconfiguring PHY\n",
+ card_location, port, lane);
+
+ hbl_cn_phy_port_reconfig(cn_port);
+ return;
+ }
+
+ break;
+ }
+ }
+
+ if (!rc) {
+ /* The control lock needs to be taken here in order to protect against a parallel
+ * status set from the link event handler.
+ * This lock also protects port close flow that destroys this thread synchronically,
+ * so a potential deadlock could happen here.
+ * In order to avoid this deadlock, we need to check if this lock was taken.
+ * If it was taken and the port is marked as closed (i.e., we are now during port
+ * close flow), we can return immediately.
+ * Otherwise, we need to keep trying to take this lock before we enter the critial
+ * section.
+ */
+ while (!mutex_trylock(&cn_port->control_lock))
+ if (!hbl_cn_is_port_open(cn_port))
+ return;
+
+ cn_port->phy_fw_tuned = true;
+
+ /* If we got link up event, set it now when PHY is ready */
+ if (cn_port->eq_pcs_link) {
+ cn_port->pcs_link = true;
+ hbl_cn_phy_set_port_status(cn_port, true);
+ }
+
+ mutex_unlock(&cn_port->control_lock);
+
+ cn_port->retry_cnt = 0;
+ }
+}
+
+static int fw_tuning_an(struct hbl_cn_device *hdev, u32 port, int lane)
+{
+ u32 state = rv_debug(hdev, port, lane, 1, 0);
+
+ if (((u16)state) != 0xA01F && ((u16)state) != 0xA020 && ((u16)state) != 0xAF00) {
+ u32 error_status = rv_debug(hdev, port, lane, 0, 3);
+
+ dev_dbg_ratelimited(hdev->dev,
+ "Card %u Port %u lane %d: auto neg fw is not ready, state 0x%x error 0x%x\n",
+ hdev->card_location, port, lane, state, error_status);
+ return -EAGAIN;
+ }
+
+ return 0;
+}
+
+static void tx_quite(struct hbl_cn_device *hdev, u32 port, int lane)
+{
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA1, 0x0);
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA2, 0x0);
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA3, 0x0);
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA4, 0x0);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, 0x0,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_TEST_DATA_SRC_MASK);
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, 0x0,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PAM4_TEST_EN_MASK);
+}
+
+static int do_anlt(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port, tx_port;
+ int tx_lane, rc;
+
+ /* fw_tuning_an needs to be done only on lane 0 */
+ rc = fw_tuning_an(hdev, port, 0);
+ if (rc)
+ return rc;
+
+ get_tx_port_and_lane(hdev, port, 0, &tx_port, &tx_lane);
+ tx_quite(hdev, tx_port, tx_lane);
+
+ rc = fw_config(hdev, port, NIC_DR_50, true);
+ if (rc) {
+ dev_dbg(hdev->dev,
+ "Card %u Port %u: PHY link training failed, rc %d - reconfiguring PHY\n",
+ hdev->card_location, port, rc);
+
+ hbl_cn_phy_port_reconfig(cn_port);
+
+ return rc;
+ }
+
+ cn_port->auto_neg_resolved = true;
+
+ return 0;
+}
+
+static void do_fw_tuning_auto_neg(struct hbl_cn_port *cn_port)
+{
+ u32 fw_tuning_timeout_ms;
+
+ if (cn_port->auto_neg_enable) {
+ if (do_anlt(cn_port))
+ return;
+ } else {
+ cn_port->auto_neg_skipped = true;
+ }
+
+ if (cn_port->eth_enable)
+ fw_tuning_timeout_ms = NIC_PHY_FW_TUNING_TIMEOUT_MS;
+ else
+ fw_tuning_timeout_ms = tx_taps_num_cfgs * NIC_PHY_PCS_SETTLING_WAIT_MS;
+
+ cn_port->fw_tuning_limit_ts = ktime_add_ms(ktime_get(), fw_tuning_timeout_ms);
+ do_fw_tuning(cn_port);
+}
+
+static u32 get_timeout_ms(struct hbl_cn_port *cn_port)
+{
+ u32 card_location, port, timeout_ms;
+ struct gaudi2_cn_port *gaudi2_port;
+ struct hbl_cn_device *hdev;
+
+ hdev = cn_port->hdev;
+ gaudi2_port = cn_port->cn_specific;
+ card_location = hdev->card_location;
+ port = cn_port->port;
+ timeout_ms = MSEC_PER_SEC;
+
+ if (!cn_port->phy_fw_tuned) {
+ timeout_ms = NIC_PHY_FW_TUNING_INTERVAL_MS;
+ } else if (!cn_port->phy_func_mode_en) {
+ u16 timeout_sec = hdev->phy_calc_ber_wait_sec;
+
+ dev_info(hdev->dev, "Card %u Port %u: Waiting %u seconds before calculating BER\n",
+ card_location, port, timeout_sec);
+ timeout_ms = timeout_sec * MSEC_PER_SEC;
+ } else {
+ enum gaudi2_cn_pcs_link_state pcs_link_state = gaudi2_port->pcs_link_state;
+
+ switch (pcs_link_state) {
+ case PCS_LINK_STATE_SETTLING:
+ timeout_ms = NIC_PHY_PCS_SETTLING_WAIT_MS;
+ dev_dbg(hdev->dev, "Card %u Port %u: waiting %lu seconds for settling\n",
+ card_location, port, timeout_ms / MSEC_PER_SEC);
+ break;
+ case PCS_LINK_STATE_STRESS:
+ timeout_ms = NIC_PHY_PCS_STRESS_INT_MS;
+ gaudi2_port->pcs_link_samples_per_sec = MSEC_PER_SEC / timeout_ms;
+ break;
+ case PCS_LINK_STATE_STEADY:
+ timeout_ms = NIC_PHY_PCS_STEADY_STATE_INT_MS;
+ gaudi2_port->pcs_link_samples_per_sec = MSEC_PER_SEC / timeout_ms;
+ break;
+ default:
+ dev_err(hdev->dev, "Card %u Port %u: invalid pcs_link_state %u\n",
+ card_location, port, pcs_link_state);
+ }
+ }
+
+ return timeout_ms;
+}
+
+void gaudi2_cn_phy_link_status_work(struct work_struct *work)
+{
+ u32 card_location, port, timeout_ms;
+ struct gaudi2_cn_device *gaudi2;
+ struct hbl_cn_port *cn_port;
+ struct hbl_cn_device *hdev;
+
+ cn_port = container_of(work, struct hbl_cn_port, link_status_work.work);
+ hdev = cn_port->hdev;
+ gaudi2 = hdev->asic_specific;
+ card_location = hdev->card_location;
+ port = cn_port->port;
+
+ /* Reschedule this work if the device is under compute reset */
+ if (gaudi2->in_compute_reset) {
+ timeout_ms = MSEC_PER_SEC;
+ goto reschedule;
+ }
+
+ if (cn_port->phy_fw_tuned) {
+ if (!cn_port->phy_func_mode_en) {
+ calc_ber(cn_port);
+ dev_info(hdev->dev, "Card %u Port %u: BER calculation is done\n",
+ card_location, port);
+ return;
+ }
+
+ check_pcs_link(cn_port);
+ } else {
+ if (cn_port->auto_neg_resolved || cn_port->auto_neg_skipped)
+ do_fw_tuning(cn_port);
+ else
+ do_fw_tuning_auto_neg(cn_port);
+ }
+
+ timeout_ms = get_timeout_ms(cn_port);
+
+reschedule:
+ queue_delayed_work(cn_port->wq, &cn_port->link_status_work, msecs_to_jiffies(timeout_ms));
+}
+
+static void set_tx(struct hbl_cn_device *hdev, u32 port, int lane, bool enable)
+{
+ u32 val = enable ? 0x1 : 0x0;
+
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0NF8, val,
+ NIC0_SERDES0_LANE0_REGISTER_0NF8_PU_VDRV_MASK);
+}
+
+void gaudi2_cn_phy_port_start_stop(struct hbl_cn_port *cn_port, bool is_start)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port, tx_port;
+ int lane, tx_lane;
+
+ for (lane = 0; lane < 2; lane++) {
+ get_tx_port_and_lane(hdev, port, lane, &tx_port, &tx_lane);
+
+ if (is_start) {
+ /* Enable TX driver in SerDes */
+ set_tx(hdev, tx_port, tx_lane, true);
+ /* Enable F/W Rx tuning is done during power up flow */
+ } else {
+ /* Disable TX driver in SerDes */
+ set_tx(hdev, tx_port, tx_lane, false);
+ /* Silence F/W Rx tuning */
+ NIC_PHY_WREG32(NIC0_SERDES0_REGISTER_9815, 0x9000 | lane);
+ }
+ }
+}
+
+static int fw_start_an(struct hbl_cn_device *hdev, u32 port, int lane)
+{
+ u32 detail = 0, ignore;
+
+ return fw_cmd(hdev, port, 0x80A0 | lane, &detail, 0x8, &ignore);
+}
+
+static int fw_start_an_tx(struct hbl_cn_device *hdev, u32 port, int lane)
+{
+ u32 detail = 0, ignore;
+ int rc;
+
+ rc = fw_cmd(hdev, port, 0x7040 | lane, &detail, 0x7, &ignore);
+ if (rc)
+ return rc;
+
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0, 0x0,
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_PAM4_TEST_EN_MASK);
+
+ return 0;
+}
+
+static int fw_config_auto_neg(struct hbl_cn_device *hdev, u32 port, int lane)
+{
+ struct hbl_cn_port *cn_port = &hdev->cn_ports[port];
+ u64 basepage = 0x800000001ull;
+ u32 tx_port, pflags;
+ u32 card_location;
+ int tx_lane, rc;
+
+ card_location = hdev->card_location;
+ pflags = hbl_cn_get_pflags(cn_port);
+
+ get_tx_port_and_lane(hdev, port, lane, &tx_port, &tx_lane);
+
+ /* clear go bit */
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_980F, 0x0, 0x8000);
+
+ init_nrz_tx(hdev, tx_port, tx_lane);
+ init_nrz_rx(hdev, port, lane);
+
+ init_lane_for_fw_tx(hdev, tx_port, tx_lane, false, true);
+ init_lane_for_fw_rx(hdev, port, lane, false, true);
+
+ prbs_mode_select_tx(hdev, tx_port, tx_lane, false, "PRBS31");
+ prbs_mode_select_rx(hdev, port, lane, false, "PRBS31");
+
+ lane_swapping_config(hdev, port, lane, true, true);
+
+ /* set FW to start AN */
+
+ rc = fw_start_an(hdev, port, lane);
+ if (rc) {
+ dev_err(hdev->dev, "Card %u Port %u lane %d: start auto neg failed, rc %d\n",
+ card_location, tx_port, tx_lane, rc);
+ return rc;
+ }
+
+ if (is_lane_swapping(hdev, port, lane)) {
+ rc = fw_start_an_tx(hdev, tx_port, tx_lane);
+ if (rc) {
+ dev_err(hdev->dev,
+ "Card %u Port %u lane %d: start auto neg failed, rc %d\n",
+ card_location, tx_port, tx_lane, rc);
+ return rc;
+ }
+ }
+
+ /* AN reset */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_AK00, 0xE000);
+
+ /* AN mode */
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_AI10, basepage & 0xFFFF);
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_AI11, (basepage >> 16) & 0xFFFF);
+ NIC_PHY_WREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_AI12, (basepage >> 32) & 0xFFFF);
+
+ /* IEEE */
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_AK00, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_ANEG_IEEE_MODE_S_MASK);
+
+ if (pflags & PFLAGS_PHY_AUTO_NEG_LPBK)
+ NIC_PHY_RMWREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_AK00, 0x1,
+ NIC0_SERDES0_LANE0_REGISTER_AK00_ARG_DIS_NONCE_MATCH_S_MASK);
+
+ rc = set_pll(hdev, port, lane, NIC_DR_25);
+ if (rc)
+ return rc;
+
+ /* set go bit */
+ NIC_PHY_RMWREG32(NIC0_SERDES0_REGISTER_980F, 0x1, 0x8000);
+
+ return 0;
+}
+
+static int port_9_reinit(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_port *cn_port_9 = &hdev->cn_ports[9];
+
+ if (!hbl_cn_is_port_open(cn_port_9))
+ return 0;
+
+ dev_dbg(hdev->dev,
+ "Card %u Port 9: Performing port 9 PHY reinit following port 8 PHY init\n",
+ hdev->card_location);
+
+ hbl_cn_phy_fini(cn_port_9);
+
+ return hbl_cn_phy_init(cn_port_9);
+}
+
+int gaudi2_cn_phy_port_power_up(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ struct gaudi2_cn_port *gaudi2_port;
+ u32 data_rate = cn_port->data_rate;
+ u32 card_location, port;
+ int rc;
+
+ gaudi2_port = cn_port->cn_specific;
+ card_location = hdev->card_location;
+ port = cn_port->port;
+
+ phy_port_reset(hdev, port);
+
+ if (hdev->phy_force_first_tx_taps_cfg)
+ gaudi2_port->tx_taps_cfg = 0;
+
+ cn_port->phy_func_mode_en = false;
+ gaudi2_port->pcs_link_state = PCS_LINK_STATE_SETTLING;
+ gaudi2_port->initial_tx_taps_cfg = gaudi2_port->tx_taps_cfg;
+
+ if (cn_port->auto_neg_enable) {
+ /* AN config should be done only on lane 0 */
+ rc = fw_config_auto_neg(hdev, port, 0);
+ if (rc) {
+ dev_err(hdev->dev, "Card %u Port %u: F/W config auto_neg failed, rc %d\n",
+ card_location, port, rc);
+ return rc;
+ }
+ } else {
+ rc = fw_config(hdev, port, data_rate, false);
+ if (rc) {
+ dev_err(hdev->dev, "Card %u Port %u: F/W config failed, rc %d\n",
+ card_location, port, rc);
+ return rc;
+ }
+ }
+
+ /* Port 8 is an external port which will usually be brought UP after all the internal ports
+ * are UP. Due to macro clock nest dependency, when PHY reset is called for port 8,
+ * port 9 (which is internal) is being toggled and might lost stabilization.
+ * A W/A to overcome this issue is to reinit port 9 right after.
+ */
+ if (port == 8)
+ port_9_reinit(hdev);
+
+ return 0;
+}
+
+void gaudi2_cn_phy_port_reconfig(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 card_location, port;
+ int rc;
+
+ if (!hdev->phy_config_fw)
+ return;
+
+ card_location = hdev->card_location;
+ port = cn_port->port;
+
+ rc = gaudi2_cn_phy_port_power_up(cn_port);
+ if (rc)
+ dev_err(hdev->dev, "Card %u Port %u: PHY reconfig failed\n", card_location, port);
+}
+
+int gaudi2_cn_phy_port_init(struct hbl_cn_port *cn_port)
+{
+ struct hbl_cn_device *hdev = cn_port->hdev;
+ u32 port = cn_port->port;
+ int rc;
+
+ mac_lane_remap(hdev, port);
+
+ rc = hbl_cn_phy_init(cn_port);
+ if (rc)
+ dev_err(hdev->dev, "Port %u: failed to init PHY, rc %d\n", port, rc);
+
+ return rc;
+}
+
+void gaudi2_cn_phy_port_fini(struct hbl_cn_port *cn_port)
+{
+ hbl_cn_phy_fini(cn_port);
+}
+
+int gaudi2_cn_phy_reset_macro(struct hbl_cn_macro *cn_macro)
+{
+ struct hbl_cn_device *hdev = cn_macro->hdev;
+ u32 port;
+
+ /* Reset the two ports under the given cn_macro */
+ port = cn_macro->idx << 1;
+
+ /* Enable PHY refclk */
+ NIC_MACRO_WREG32(NIC0_PHY_PHY_IDDQ_0, 0);
+ NIC_MACRO_WREG32(NIC0_PHY_PHY_IDDQ_1, 0);
+
+ phy_port_reset(hdev, port);
+ phy_port_reset(hdev, port + 1);
+
+ return 0;
+}
+
+void gaudi2_cn_phy_flush_link_status_work(struct hbl_cn_device *hdev)
+{
+ struct hbl_cn_port *cn_port;
+ int i;
+
+ for (i = 0; i < hdev->cn_props.max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ cn_port = &hdev->cn_ports[i];
+
+ flush_delayed_work(&cn_port->link_status_work);
+ }
+}
+
+static int find_first_enabled_port(struct hbl_cn_device *hdev, u32 *port)
+{
+ int i;
+
+ for (i = 0; i < NIC_NUMBER_OF_PORTS; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ *port = i;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static void fw_write_all(struct hbl_cn_device *hdev, u32 addr, u32 data)
+{
+ int port;
+
+ for (port = 0; port < NIC_NUMBER_OF_PORTS; port++) {
+ if (!(hdev->ports_mask & BIT(port)))
+ continue;
+
+ NIC_PHY_WREG32(addr, data);
+ }
+}
+
+static void fw_write_all_lanes(struct hbl_cn_device *hdev, u32 addr, u32 data)
+{
+ int port, lane;
+
+ for (port = 0; port < NIC_NUMBER_OF_PORTS; port++) {
+ if (!(hdev->ports_mask & BIT(port)))
+ continue;
+
+ for (lane = 0; lane < 2; lane++)
+ NIC_PHY_WREG32_LANE(addr, data);
+ }
+}
+
+static void fw_unload_all(struct hbl_cn_device *hdev)
+{
+ u32 port;
+
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_9814, 0xFFF0);
+
+ for (port = 0; port < NIC_NUMBER_OF_PORTS; port++) {
+ if (!(hdev->ports_mask & BIT(port)))
+ continue;
+
+ cpu_reset(hdev, port);
+ }
+
+ msleep(100);
+
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_9814, 0x0);
+
+ /* PAM4 */
+ fw_write_all_lanes(hdev, NIC0_SERDES0_LANE0_REGISTER_0P11, 0);
+ usleep_range(1000, 2000);
+ fw_write_all_lanes(hdev, NIC0_SERDES0_LANE0_REGISTER_0P11, 0x2000);
+
+ /* NRZ */
+ fw_write_all_lanes(hdev, NIC0_SERDES0_LANE0_REGISTER_0N0B, 0);
+ fw_write_all_lanes(hdev, NIC0_SERDES0_LANE0_REGISTER_0N0C, 0);
+ usleep_range(1000, 2000);
+ fw_write_all_lanes(hdev, NIC0_SERDES0_LANE0_REGISTER_0N0C, 0x8000);
+}
+
+static u32 fw_crc(struct hbl_cn_device *hdev, u32 port)
+{
+ u32 checksum_code, ignore;
+
+ fw_cmd(hdev, port, 0xF001, NULL, 0xF, &ignore);
+ checksum_code = NIC_PHY_RREG32(NIC0_SERDES0_REGISTER_9816);
+
+ return checksum_code;
+}
+
+static u32 fw_hash(struct hbl_cn_device *hdev, u32 port)
+{
+ u32 low_word, hash_code, res;
+
+ fw_cmd(hdev, port, 0xF000, NULL, 0xF, &res);
+ low_word = NIC_PHY_RREG32(NIC0_SERDES0_REGISTER_9816);
+ hash_code = ((res & 0xFF) << 16) | low_word;
+
+ return hash_code;
+}
+
+static int mcu_cal_enable_all(struct hbl_cn_device *hdev)
+{
+ u32 port;
+ int rc;
+
+ for (port = 0; port < NIC_NUMBER_OF_PORTS; port++) {
+ if (!(hdev->ports_mask & BIT(port)))
+ continue;
+
+ rc = set_fw_reg(hdev, port, 357, NIC_PHY_FW_TIME_CONSTANT_RATIO);
+ if (rc) {
+ dev_dbg(hdev->dev, "Port %u: MCU calibration failed\n", port);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+int gaudi2_cn_phy_fw_load_all(struct hbl_cn_device *hdev)
+{
+ u32 entry_point, length, ram_addr, sections, status, checks, checksum;
+ int rc, i, j, data_ptr = 0;
+ const struct firmware *fw;
+ const void *fw_data;
+ const char *fw_name;
+ u16 mdio_data;
+ u32 port; /* For regs read */
+
+ rc = find_first_enabled_port(hdev, &port);
+ if (rc)
+ return rc;
+
+ fw_name = gaudi2_cn_phy_get_fw_name();
+
+ fw_unload_all(hdev);
+
+ rc = request_firmware(&fw, fw_name, hdev->dev);
+ if (rc) {
+ dev_err(hdev->dev, "Firmware file %s is not found\n", fw_name);
+ return rc;
+ }
+
+ fw_data = (const void *)fw->data;
+ fw_data += 0x1000;
+
+ /* skip hash, crc and date */
+ entry_point = get_unaligned_be32(fw_data + 8);
+ length = get_unaligned_be32(fw_data + 12);
+ ram_addr = get_unaligned_be32(fw_data + 16);
+
+ dev_dbg(hdev->dev, "entry_point: 0x%x\n", entry_point);
+ dev_dbg(hdev->dev, "length: 0x%x\n", length);
+
+ fw_data += 20;
+
+ sections = DIV_ROUND_UP(length, 24);
+
+ dev_dbg(hdev->dev, "sections: %d\n", sections);
+
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_9814, 0xFFF0); /* FW2 */
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_980D, 0x0AAA); /* FW1 */
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_980D, 0x0); /* FW1 */
+
+ checks = 0;
+
+ do {
+ usleep_range(10000, 20000);
+ status = NIC_PHY_RREG32(NIC0_SERDES0_REGISTER_9814); /* FW2 */
+ dev_dbg(hdev->dev, "port %d, status: 0x%x\n", port, status);
+ if (checks++ > NIC_PHY_READ_COUNTS_PER_MS) {
+ dev_err(hdev->dev, "failed to load F/W, fw2 timeout 0x%x\n", status);
+ rc = -ETIMEDOUT;
+ goto release_fw;
+ }
+ } while (status);
+
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_9814, 0x0);
+
+ for (i = 0; i <= sections; i++) {
+ checksum = 0x800C;
+
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_9F0C, ram_addr >> 16); /* FW0 + 12 */
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_9F0D, ram_addr & 0xFFFF); /* FW0 + 13 */
+ checksum += (ram_addr >> 16) + (ram_addr & 0xFFFF);
+
+ for (j = 0; j < 12; j++) {
+ if (data_ptr >= length)
+ mdio_data = 0;
+ else
+ mdio_data = get_unaligned_be16(fw_data + data_ptr);
+
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_9F00 + 4 * j, mdio_data);
+
+ checksum += mdio_data;
+ data_ptr += 2;
+ ram_addr += 2;
+ }
+
+ /* FW0 + 14 */
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_9F0E, (~checksum + 1) & 0xFFFF);
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_9F0F, 0x800C); /* FW0 + 15 */
+
+ checks = 0;
+
+ do {
+ usleep_range(1000, 2000);
+ status = NIC_PHY_RREG32(NIC0_SERDES0_REGISTER_9F0F); /* FW0 + 15 */
+ if (checks++ > NIC_PHY_READ_COUNTS_PER_MS) {
+ dev_err(hdev->dev, "failed to load F/W, fw0 timeout 0x%x\n",
+ status);
+ rc = -ETIMEDOUT;
+ goto release_fw;
+ }
+ } while (status == 0x800C);
+ }
+
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_9F0C, entry_point >> 16); /* FW0 + 12 */
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_9F0D, entry_point & 0xFFFF); /* FW0 + 13 */
+ checksum = (entry_point >> 16) + (entry_point & 0xFFFF) + 0x4000;
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_9F0E, (~checksum + 1) & 0xFFFF); /* FW0 + 14 */
+ fw_write_all(hdev, NIC0_SERDES0_REGISTER_9F0F, 0x4000); /* FW0 + 15 */
+
+ msleep(500);
+
+ dev_dbg(hdev->dev, "F/W CRC = 0x%x\n", fw_crc(hdev, port));
+ dev_dbg(hdev->dev, "F/W hash = 0x%x\n", fw_hash(hdev, port));
+
+ rc = mcu_cal_enable_all(hdev);
+
+release_fw:
+ release_firmware(fw);
+ return rc;
+}
+
+u16 gaudi2_cn_phy_get_crc(struct hbl_cn_device *hdev)
+{
+ u32 port;
+ int rc;
+
+ rc = find_first_enabled_port(hdev, &port);
+ if (rc)
+ return rc;
+
+ return fw_crc(hdev, port);
+}
+
+static bool is_old_phy_fw_loaded(struct hbl_cn_device *hdev)
+{
+ return gaudi2_cn_phy_get_crc(hdev) == 0x1723;
+}
+
+static bool is_phy_fw_with_anlt_support(struct hbl_cn_device *hdev)
+{
+ return gaudi2_cn_phy_get_crc(hdev) == 0x185E;
+}
+
+int gaudi2_cn_phy_init(struct hbl_cn_device *hdev)
+{
+ if (!hdev->phy_config_fw)
+ return 0;
+
+ /* Fail the initialization in case of an old PHY F/W, as the current PHY init flow won't
+ * work with it.
+ */
+ if (is_old_phy_fw_loaded(hdev)) {
+ dev_err(hdev->dev, "PHY F/W is very old - failing the initialization\n");
+ return -EINVAL;
+ }
+
+ /* In case LKD override the existing PHY F/W with an unofficial one and this F/W has ANLT
+ * support, ANLT will be enabled according to the mask.
+ * Otherwise, ANLT will be disabled on all ports.
+ */
+ if (hdev->load_phy_fw && is_phy_fw_with_anlt_support(hdev))
+ hdev->auto_neg_mask = hdev->phys_auto_neg_mask;
+ else
+ hdev->auto_neg_mask = 0;
+
+ /* In case we didn't get serdes info from FW, set to default values */
+ if (hdev->use_fw_serdes_info) {
+ set_fw_lane_mapping(hdev);
+ hbl_cn_phy_set_fw_polarity(hdev);
+ } else {
+ set_default_mac_lane_remap(hdev);
+ set_default_polarity_values(hdev);
+ }
+
+ /* Set the tx taps to their default values only once */
+ if (!hdev->skip_phy_default_tx_taps_cfg) {
+ set_default_tx_taps_values(hdev);
+ hdev->skip_phy_default_tx_taps_cfg = true;
+ }
+
+ return 0;
+}
+
+static int fw_read_s16(struct hbl_cn_device *hdev, u32 port, u32 offset)
+{
+ u32 t = NIC_PHY_RREG32(NIC0_SERDES0_REGISTER_9F00 + 4 * offset);
+
+ return (t & 0x8000) ? t - 0x10000 : t;
+}
+
+static void get_channel_estimation_params(struct hbl_cn_device *hdev, u32 port, int lane, u32 *of,
+ u32 *hf)
+{
+ struct hbl_cn_port *cn_port = &hdev->cn_ports[port];
+
+ if (cn_port->auto_neg_enable) {
+ *of = rv_debug(hdev, port, lane, 5, 22);
+ *hf = rv_debug(hdev, port, lane, 5, 23);
+ } else {
+ *of = rv_debug(hdev, port, lane, 2, 4);
+ *hf = rv_debug(hdev, port, lane, 2, 5);
+ }
+}
+
+static void get_tx_taps(struct hbl_cn_device *hdev, u32 port, int lane, int *tx_taps)
+{
+ u32 tx_pre2, tx_pre1, tx_main, tx_post1, tx_post2;
+
+ tx_pre2 = (NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA5) &
+ NIC0_SERDES0_LANE0_REGISTER_0PA5_TX_PRE_2_MASK) >>
+ NIC0_SERDES0_LANE0_REGISTER_0PA5_TX_PRE_2_SHIFT;
+ tx_pre1 = (NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA7) &
+ NIC0_SERDES0_LANE0_REGISTER_0PA7_TX_PRE_1_MASK) >>
+ NIC0_SERDES0_LANE0_REGISTER_0PA7_TX_PRE_1_SHIFT;
+ tx_main = (NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA9) &
+ NIC0_SERDES0_LANE0_REGISTER_0PA9_TX_MAIN_MASK) >>
+ NIC0_SERDES0_LANE0_REGISTER_0PA9_TX_MAIN_SHIFT;
+ tx_post1 = (NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PAB) &
+ NIC0_SERDES0_LANE0_REGISTER_0PAB_TX_POST_1_MASK) >>
+ NIC0_SERDES0_LANE0_REGISTER_0PAB_TX_POST_1_SHIFT;
+ tx_post2 = (NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PAD) &
+ NIC0_SERDES0_LANE0_REGISTER_0PAD_TX_POST_2_MASK) >>
+ NIC0_SERDES0_LANE0_REGISTER_0PAD_TX_POST_2_SHIFT;
+
+ tx_taps[0] = twos_to_int(tx_pre2, 8);
+ tx_taps[1] = twos_to_int(tx_pre1, 8);
+ tx_taps[2] = twos_to_int(tx_main, 8);
+ tx_taps[3] = twos_to_int(tx_post1, 8);
+ tx_taps[4] = twos_to_int(tx_post2, 8);
+}
+
+static void copy_info(char *buf, char *name, int *data, u8 count, ssize_t size)
+{
+ int i;
+
+ __snprintf(buf, size, "%s:", name);
+
+ for (i = 0; i < count; i++)
+ __snprintf(buf, size, " %d", data[i]);
+
+ __snprintf(buf, size, "\n");
+}
+
+static void dump_ber_info(struct hbl_cn_device *hdev, u32 port, int lane, char *buf, ssize_t size)
+{
+ struct hbl_cn_ber_info *ber_info;
+ u32 abs_lane_idx;
+
+ abs_lane_idx = (port << 1) + lane;
+ ber_info = &hdev->phy_ber_info[abs_lane_idx];
+
+ if (ber_info->valid)
+ __snprintf(buf, size, "BER: %llu.%llue-%u\n",
+ ber_info->integer, ber_info->frac, ber_info->exp);
+ else
+ __snprintf(buf, size, "No BER information\n");
+}
+
+void gaudi2_cn_phy_dump_serdes_params(struct hbl_cn_device *hdev, char *buf, size_t size)
+{
+ u32 port, card_location, sd, phy_ready, ch_est_of, ch_est_hf, ppm_twos, adapt_state;
+ int lane, i, ppm, eye[3], isi[18], tx_taps[5];
+ u8 tx_pol, rx_pol;
+ bool pam4;
+
+ port = hdev->phy_port_to_dump;
+ card_location = hdev->card_location;
+ pam4 = hdev->cn_ports[port].data_rate == NIC_DR_50;
+
+ __snprintf(buf, size, "\nmode: %s\n\n", pam4 ? "PAM4" : "NRZ");
+
+ for (lane = 0; lane < 2; lane++) {
+ sd = (NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P6A) &
+ NIC0_SERDES0_LANE0_REGISTER_0P6A_READ_SIG_DET_MASK) >>
+ NIC0_SERDES0_LANE0_REGISTER_0P6A_READ_SIG_DET_SHIFT;
+
+ phy_ready = (NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P6A) &
+ NIC0_SERDES0_LANE0_REGISTER_0P6A_RX_READ_PHY_READY_MASK) >>
+ NIC0_SERDES0_LANE0_REGISTER_0P6A_RX_READ_PHY_READY_SHIFT;
+ ppm_twos = (NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P73) &
+ NIC0_SERDES0_LANE0_REGISTER_0P73_READ_FREQ_ACC_MASK) >>
+ NIC0_SERDES0_LANE0_REGISTER_0P73_READ_FREQ_ACC_SHIFT;
+ ppm = twos_to_int(ppm_twos, 11);
+ adapt_state = rv_debug(hdev, port, lane, 2, 0);
+
+ tx_pol = (NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0PA0) &
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_ANA_OUT_FLIP_MASK) >>
+ NIC0_SERDES0_LANE0_REGISTER_0PA0_TX_ANA_OUT_FLIP_SHIFT;
+
+ rx_pol = pam4 ? (NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0P43) &
+ NIC0_SERDES0_LANE0_REGISTER_0P43_RX_DATA_FLIP_MASK) >>
+ NIC0_SERDES0_LANE0_REGISTER_0P43_RX_DATA_FLIP_SHIFT :
+ (NIC_PHY_RREG32_LANE(NIC0_SERDES0_LANE0_REGISTER_0N61) &
+ NIC0_SERDES0_LANE0_REGISTER_0N61_PRBS_CHECK_FLIP_MASK) >>
+ NIC0_SERDES0_LANE0_REGISTER_0N61_PRBS_CHECK_FLIP_SHIFT;
+
+ get_channel_estimation_params(hdev, port, lane, &ch_est_of, &ch_est_hf);
+
+ rv_debug(hdev, port, lane, 0xA, 5);
+ for (i = 0; i < 3; i++)
+ eye[i] = fw_read_s16(hdev, port, i);
+
+ rv_debug(hdev, port, lane, 0xA, 0);
+ for (i = 0; i < 16; i++)
+ isi[i] = fw_read_s16(hdev, port, i);
+
+ rv_debug(hdev, port, lane, 0xA, 8);
+ for (i = 0; i < 2; i++)
+ isi[16 + i] = fw_read_s16(hdev, port, i);
+
+ get_tx_taps(hdev, port, lane, tx_taps);
+
+ __snprintf(buf, size, "Card %u Port %u lane %d:\n", card_location, port, lane);
+ __snprintf(buf, size,
+ "sd: %u\nphy_ready: %u\nppm: %d\nch_est_of: %u\nch_est_hf: %u\n"
+ "adaptation state: 0x%x\ntx_pol: %u\nrx_pol: %u\n", sd, phy_ready, ppm,
+ ch_est_of, ch_est_hf, adapt_state, tx_pol, rx_pol);
+ copy_info(buf, "eyes", eye, 3, size);
+ copy_info(buf, "isi", isi, 18, size);
+ copy_info(buf, "tx_taps", tx_taps, 5, size);
+
+ dump_ber_info(hdev, port, lane, buf, size);
+
+ __snprintf(buf, size, "\n");
+ }
+}
diff --git a/include/linux/net/intel/gaudi2.h b/include/linux/net/intel/gaudi2.h
new file mode 100644
index 000000000000..49dd1b6b7c86
--- /dev/null
+++ b/include/linux/net/intel/gaudi2.h
@@ -0,0 +1,432 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#ifndef HBL_GAUDI2_H_
+#define HBL_GAUDI2_H_
+
+#include <linux/net/intel/cn.h>
+#include <linux/net/intel/gaudi2_aux.h>
+
+#define NIC_PSN_NBITS 24
+#define NIC_PSN_MSB_MASK (BIT(NIC_PSN_NBITS - 1))
+#define NIC_PSN_LOWER_MASK ((NIC_PSN_MSB_MASK) - 1)
+
+#define NIC_IS_PSN_CYCLIC_BIG(psn_a, psn_b) \
+ ({ \
+ u32 _psn_a = (psn_a); \
+ u32 _psn_b = (psn_b); \
+ ((_psn_a & NIC_PSN_MSB_MASK) == (_psn_b & NIC_PSN_MSB_MASK) ? \
+ (_psn_a & NIC_PSN_LOWER_MASK) > (_psn_b & NIC_PSN_LOWER_MASK) : \
+ (_psn_a & NIC_PSN_LOWER_MASK) < (_psn_b & NIC_PSN_LOWER_MASK)); \
+ })
+
+enum gaudi2_wqe_opcode {
+ WQE_NOP = 0,
+ WQE_SEND = 1,
+ WQE_LINEAR = 2,
+ WQE_STRIDE = 3,
+ WQE_MULTI_STRIDE = 4,
+ WQE_RENDEZVOUS_WR = 5,
+ WQE_RENDEZVOUS_RD = 6,
+ WQE_QOS_UPDATE = 7
+};
+
+#define NIC_SKB_PAD_SIZE 187
+
+/**
+ * enum gaudi2_eqe_type - Event queue element types for the NIC.
+ * @EQE_COMP: Completion queue event. May occur upon Ethernet or RDMA Rx completion.
+ * @EQE_COMP_ERR: Completion queue error event. May occur upon CQ overrun or other errors. Overrun
+ * may occur in case the S/W doesn't consume the CQ entries fast enough so there is
+ * no room for new H/W's entries.
+ * @EQE_QP_ERR: QP moved to error state event. May occur by varies QP errors, e.g.: QP not valid,
+ * QP state invalid etc.
+ * @EQE_LINK_STATUS: PCS link status changed event. May occur upon link up/down events.
+ * @EQE_RAW_TX_COMP: Ethernet Tx completion event. May occur once H/W complete to send Ethernet
+ * packet.
+ * @EQE_DB_FIFO_OVERRUN: DB FIFO overrun event. May occur upon FIFO overrun in case S/W overwrite
+ * un-consumed FIFO entry.
+ * @EQE_CONG: Congestion control completion queue event. May occur upon any packet completion in
+ * case CC is enabled.
+ * @EQE_CONG_ERR: Congestion control completion queue error event. May occur upon CCQ overrun or
+ * other errors. Overrun may occur in case the S/W doesn't consume the CCQ entries
+ * fast enough so there is no room for new H/W's entries.
+ * @EQE_RESERVED: Reserved event value.
+ *
+ * ******************* SW events *******************
+ * @EQE_QP_ALIGN_COUNTERS: QPC sanity failed and QPC counters were reset to last valid values.
+ */
+enum gaudi2_eqe_type {
+ EQE_COMP = 0x0,
+ EQE_COMP_ERR = 0x1,
+ EQE_QP_ERR = 0x2,
+ EQE_LINK_STATUS = 0x3,
+ EQE_RAW_TX_COMP = 0x4,
+ EQE_DB_FIFO_OVERRUN = 0x5,
+ EQE_CONG = 0x6,
+ EQE_CONG_ERR = 0x7,
+ EQE_RESERVED = 0x8,
+
+ /* events triggered by SW */
+ EQE_QP_ALIGN_COUNTERS = 0xa,
+};
+
+/* BIT() macro is overflowing on full 64 bit mask, use the safer BITMLL() instead */
+#define BITMLL(nr) (U64_MAX >> (64 - (nr)))
+
+/* Use multiple underscores to avoid hiding collisions. Using len and _len like in NIC_SET_BITS()
+ * causes len to be 0 here in NIC_SET().
+ */
+#define NIC_SET(desc, idx, shift, val, __len) \
+ ({ \
+ u64 *_data = &(desc).data[(idx)]; \
+ u32 _shift = (shift); \
+ u32 ___len = (__len); \
+ *_data &= ~((u64)(BITMLL(___len)) << _shift); \
+ *_data |= (u64)((val) & BITMLL(___len)) << _shift; \
+ })
+
+#define NIC_SET_BITS(desc, lsb, val, len) \
+ do { \
+ u32 _lsb = (lsb); \
+ u32 _len = (len); \
+ BUILD_BUG_ON((_lsb / 64) != ((_lsb + _len - 1) / 64)); \
+ NIC_SET((desc), _lsb / 64, _lsb % 64, (val), _len); \
+ } while (0)
+
+#define NIC_GET(desc, idx, shift, len) \
+ ((((desc).data[idx]) >> (shift)) & BITMLL(len))
+
+#define NIC_GET_BITS(desc, lsb, len) \
+ ({ \
+ u32 _lsb = (lsb); \
+ u32 _len = (len); \
+ BUILD_BUG_ON((_lsb / 64) != ((_lsb + _len - 1) / 64)); \
+ NIC_GET(desc, _lsb / 64, _lsb % 64, _len); \
+ })
+
+struct gaudi2_qpc_requester {
+ u64 data[16];
+};
+
+struct qpc_mask {
+ u64 data[sizeof(struct gaudi2_qpc_requester) >> 3];
+};
+
+#define REQ_QPC_SET_DST_QP(req, val) NIC_SET_BITS(req, 0, val, 24)
+#define REQ_QPC_SET_RKEY(req, val) NIC_SET_BITS(req, 128, val, 32)
+#define REQ_QPC_SET_DST_IP(req, val) NIC_SET_BITS(req, 160, val, 32)
+#define REQ_QPC_SET_DST_MAC_LSB(req, val) NIC_SET_BITS(req, 192, val, 32)
+#define REQ_QPC_SET_DST_MAC_MSB(req, val) NIC_SET_BITS(req, 224, val, 16)
+#define REQ_QPC_SET_TIMEOUT_RETRY_COUNT(req, val) \
+ NIC_SET_BITS(req, 248, val, 8)
+#define REQ_QPC_SET_NTS_PSN(req, val) NIC_SET_BITS(req, 256, val, 24)
+#define REQ_QPC_SET_BCS_PSN(req, val) NIC_SET_BITS(req, 288, val, 24)
+#define REQ_QPC_SET_SCHD_Q_NUM(req, val) NIC_SET_BITS(req, 312, val, 8)
+#define REQ_QPC_SET_ONA_PSN(req, val) NIC_SET_BITS(req, 320, val, 24)
+
+#define REQ_QPC_SET_TM_GRANULARITY(req, val) NIC_SET_BITS(req, 376, val, 7)
+#define REQ_QPC_SET_WQ_BACK_PRESSURE(req, val) NIC_SET_BITS(req, 383, val, 1)
+#define REQ_QPC_SET_REMOTE_WQ_LOG_SZ(req, val) NIC_SET_BITS(req, 408, val, 5)
+#define REQ_QPC_SET_ENCAP_TYPE(req, val) NIC_SET_BITS(req, 413, val, 3)
+#define REQ_QPC_SET_CQ_NUM(req, val) NIC_SET_BITS(req, 440, val, 5)
+#define REQ_QPC_SET_RTT_STATE(req, val) NIC_SET_BITS(req, 445, val, 2)
+#define REQ_QPC_SET_ENCAP_ENABLE(req, val) NIC_SET_BITS(req, 447, val, 1)
+#define REQ_QPC_SET_CONGESTION_WIN(req, val) NIC_SET_BITS(req, 448, val, 24)
+#define REQ_QPC_SET_BURST_SIZE(req, val) NIC_SET_BITS(req, 544, val, 22)
+#define REQ_QPC_SET_ASID(req, val) NIC_SET_BITS(req, 566, val, 8)
+
+#define REQ_QPC_SET_LAST_IDX(req, val) NIC_SET_BITS(req, 576, val, 22)
+#define REQ_QPC_SET_EXECUTION_IDX(req, val) NIC_SET_BITS(req, 608, val, 22)
+#define REQ_QPC_SET_CONSUMER_IDX(req, val) NIC_SET_BITS(req, 640, val, 22)
+#define REQ_QPC_SET_LOCAL_PRODUCER_IDX(req, val) NIC_SET_BITS(req, 672, val, 22)
+#define REQ_QPC_SET_REMOTE_PRODUCER_IDX(req, val) NIC_SET_BITS(req, 704, val, 22)
+#define REQ_QPC_SET_REMOTE_CONSUMER_IDX(req, val) NIC_SET_BITS(req, 736, val, 22)
+#define REQ_QPC_SET_OLDEST_UNACKED_REMOTE_PRODUCER_IDX(req, val) NIC_SET_BITS(req, 768, \
+ val, 22)
+#define REQ_QPC_SET_PSN_SINCE_ACKREQ(req, val) NIC_SET_BITS(req, 800, val, 8)
+#define REQ_QPC_SET_ACKREQ_FREQ(req, val) NIC_SET_BITS(req, 808, val, 8)
+#define REQ_QPC_SET_PACING_TIME(req, val) NIC_SET_BITS(req, 832, val, 16)
+
+#define REQ_QPC_SET_DATA_MMU_BYPASS(req, val) NIC_SET_BITS(req, 1003, val, 1)
+#define REQ_QPC_SET_MOD_GAUDI1(req, val) NIC_SET_BITS(req, 1004, val, 1)
+#define REQ_QPC_SET_PORT(req, val) NIC_SET_BITS(req, 1005, val, 2)
+#define REQ_QPC_SET_WQ_TYPE(req, val) NIC_SET_BITS(req, 1007, val, 2)
+
+#define REQ_QPC_SET_SWQ_GRANULARITY(req, val) NIC_SET_BITS(req, 1009, val, 1)
+#define REQ_QPC_SET_TRANSPORT_SERVICE(req, val) NIC_SET_BITS(req, 1010, val, 1)
+#define REQ_QPC_SET_PRIORITY(req, val) NIC_SET_BITS(req, 1011, val, 2)
+#define REQ_QPC_SET_CONGESTION_MODE(req, val) NIC_SET_BITS(req, 1013, val, 2)
+#define REQ_QPC_SET_MTU(req, val) NIC_SET_BITS(req, 1015, val, 2)
+
+#define REQ_QPC_SET_WQ_BASE_ADDR(req, val) NIC_SET_BITS(req, 1017, val, 2)
+#define REQ_QPC_SET_TRUST_LEVEL(req, val) NIC_SET_BITS(req, 1019, val, 2)
+#define REQ_QPC_SET_ERR(req, val) NIC_SET_BITS(req, 1022, val, 1)
+#define REQ_QPC_SET_VALID(req, val) NIC_SET_BITS(req, 1023, val, 1)
+
+/* REQ QPC Get */
+#define REQ_QPC_GET_DST_QP(req) NIC_GET_BITS(req, 0, 24)
+#define REQ_QPC_GET_MULTI_STRIDE_STATE_LSB(req) NIC_GET_BITS(req, 32, 32)
+#define REQ_QPC_GET_MULTI_STRIDE_STATE_MSB(req) NIC_GET_BITS(req, 64, 64)
+#define REQ_QPC_GET_RKEY(req) NIC_GET_BITS(req, 128, 32)
+#define REQ_QPC_GET_DST_IP(req) NIC_GET_BITS(req, 160, 32)
+#define REQ_QPC_GET_DST_MAC_LSB(req) NIC_GET_BITS(req, 192, 32)
+#define REQ_QPC_GET_DST_MAC_MSB(req) NIC_GET_BITS(req, 224, 16)
+#define REQ_QPC_GET_SEQUENCE_ERROR_RETRY_COUNT(req) NIC_GET_BITS(req, 240, 8)
+#define REQ_QPC_GET_TIMEOUT_RETRY_COUNT(req) NIC_GET_BITS(req, 248, 8)
+#define REQ_QPC_GET_NTS_PSN(req) NIC_GET_BITS(req, 256, 24)
+#define REQ_QPC_GET_BCS_PSN(req) NIC_GET_BITS(req, 288, 24)
+#define REQ_QPC_GET_SCHD_Q_NUM(req) NIC_GET_BITS(req, 312, 8)
+#define REQ_QPC_GET_ONA_PSN(req) NIC_GET_BITS(req, 320, 24)
+#define REQ_QPC_GET_BCC_PSN(req) NIC_GET_BITS(req, 352, 24)
+#define REQ_QPC_GET_TM_GRANULARITY(req) NIC_GET_BITS(req, 376, 7)
+#define REQ_QPC_GET_WQ_BACK_PRESSURE(req) NIC_GET_BITS(req, 383, 1)
+#define REQ_QPC_GET_CONGESTION_MARKED_ACK(req) NIC_GET_BITS(req, 384, 24)
+#define REQ_QPC_GET_REMOTE_WQ_LOG_SZ(req) NIC_GET_BITS(req, 408, 5)
+#define REQ_QPC_GET_ENCAP_TYPE(req) NIC_GET_BITS(req, 413, 3)
+#define REQ_QPC_GET_CONGESTION_NON_MARKED_ACK(req) NIC_GET_BITS(req, 416, 24)
+#define REQ_QPC_GET_CQ_NUM(req) NIC_GET_BITS(req, 440, 5)
+#define REQ_QPC_GET_RTT_STATE(req) NIC_GET_BITS(req, 445, 2)
+#define REQ_QPC_GET_ENCAP_ENABLE(req) NIC_GET_BITS(req, 447, 1)
+#define REQ_QPC_GET_CONGESTION_WIN(req) NIC_GET_BITS(req, 448, 24)
+#define REQ_QPC_GET_RTT_TIMESTAMP(req) NIC_GET_BITS(req, 480, 25)
+#define REQ_QPC_GET_RTT_MARKED_PSN(req) NIC_GET_BITS(req, 512, 24)
+#define REQ_QPC_GET_BURST_SIZE(req) NIC_GET_BITS(req, 544, 22)
+#define REQ_QPC_GET_ASID(req) NIC_GET_BITS(req, 566, 10)
+#define REQ_QPC_GET_LAST_IDX(req) NIC_GET_BITS(req, 576, 22)
+#define REQ_QPC_GET_EXECUTION_IDX(req) NIC_GET_BITS(req, 608, 22)
+#define REQ_QPC_GET_CONSUMER_IDX(req) NIC_GET_BITS(req, 640, 22)
+#define REQ_QPC_GET_LOCAL_PRODUCER_IDX(req) NIC_GET_BITS(req, 672, 22)
+#define REQ_QPC_GET_REMOTE_PRODUCER_IDX(req) NIC_GET_BITS(req, 704, 22)
+#define REQ_QPC_GET_REMOTE_CONSUMER_IDX(req) NIC_GET_BITS(req, 736, 22)
+#define REQ_QPC_GET_OLDEST_UNACKED_REMOTE_PRODUCER_IDX(req) NIC_GET_BITS(req, 768, 22)
+#define REQ_QPC_GET_PSN_SINCE_ACKREQ(req) NIC_GET_BITS(req, 800, 8)
+#define REQ_QPC_GET_ACKREQ_FREQ(req) NIC_GET_BITS(req, 808, 8)
+#define REQ_QPC_GET_PACING_TIME(req) NIC_GET_BITS(req, 832, 16)
+#define REQ_QPC_GET_PSN_DELIVERED(req) NIC_GET_BITS(req, 864, 24)
+#define REQ_QPC_GET_DATA_MMU_BYPASS(req) NIC_GET_BITS(req, 1003, 1)
+#define REQ_QPC_GET_MOD_GAUDI1(req) NIC_GET_BITS(req, 1004, 1)
+#define REQ_QPC_GET_PORT(req) NIC_GET_BITS(req, 1005, 2)
+#define REQ_QPC_GET_WQ_TYPE(req) NIC_GET_BITS(req, 1007, 2)
+#define REQ_QPC_GET_SWQ_GRANULARITY(req) NIC_GET_BITS(req, 1009, 1)
+#define REQ_QPC_GET_TRANSPORT_SERVICE(req) NIC_GET_BITS(req, 1010, 1)
+#define REQ_QPC_GET_PRIORITY(req) NIC_GET_BITS(req, 1011, 2)
+#define REQ_QPC_GET_CONGESTION_MODE(req) NIC_GET_BITS(req, 1013, 2)
+#define REQ_QPC_GET_MTU(req) NIC_GET_BITS(req, 1015, 2)
+#define REQ_QPC_GET_WQ_BASE_ADDR(req) NIC_GET_BITS(req, 1017, 2)
+#define REQ_QPC_GET_TRUST_LEVEL(req) NIC_GET_BITS(req, 1019, 2)
+#define REQ_QPC_GET_IN_WORK(req) NIC_GET_BITS(req, 1021, 1)
+#define REQ_QPC_GET_ERROR(req) NIC_GET_BITS(req, 1022, 1)
+#define REQ_QPC_GET_VALID(req) NIC_GET_BITS(req, 1023, 1)
+
+/* Resp QPC */
+struct gaudi2_qpc_responder {
+ u64 data[4];
+};
+
+#define RES_QPC_SET_DST_QP(res, val) NIC_SET_BITS(res, 0, val, 24)
+#define RES_QPC_SET_PORT(res, val) NIC_SET_BITS(res, 24, val, 2)
+#define RES_QPC_SET_PRIORITY(res, val) NIC_SET_BITS(res, 26, val, 2)
+#define RES_QPC_SET_LKEY(res, val) NIC_SET_BITS(res, 32, val, 32)
+
+#define RES_QPC_SET_DST_IP(res, val) NIC_SET_BITS(res, 64, val, 32)
+#define RES_QPC_SET_DST_MAC_LSB(res, val) NIC_SET_BITS(res, 96, val, 32)
+#define RES_QPC_SET_DST_MAC_MSB(res, val) NIC_SET_BITS(res, 128, val, 16)
+#define RES_QPC_SET_TRANSPORT_SERVICE(res, val) NIC_SET_BITS(res, 149, val, 1)
+
+#define RES_QPC_SET_ASID(res, val) NIC_SET_BITS(res, 150, val, 10)
+#define RES_QPC_SET_PEER_QP(res, val) NIC_SET_BITS(res, 160, val, 24)
+#define RES_QPC_SET_SCHD_Q_NUM(res, val) NIC_SET_BITS(res, 184, val, 8)
+
+#define RES_QPC_SET_TRUST_LEVEL(res, val) NIC_SET_BITS(res, 216, val, 2)
+#define RES_QPC_SET_MOD_GAUDI1(res, val) NIC_SET_BITS(res, 218, val, 1)
+#define RES_QPC_SET_DATA_MMU_BYPASS(res, val) NIC_SET_BITS(res, 219, val, 1)
+#define RES_QPC_SET_ENCAP_TYPE(res, val) NIC_SET_BITS(res, 220, val, 3)
+#define RES_QPC_SET_ENCAP_ENABLE(res, val) NIC_SET_BITS(res, 223, val, 1)
+#define RES_QPC_SET_CQ_NUM(res, val) NIC_SET_BITS(res, 248, val, 5)
+
+#define RES_QPC_SET_PEER_WQ_GRAN(res, val) NIC_SET_BITS(res, 253, val, 1)
+#define RES_QPC_SET_VALID(res, val) NIC_SET_BITS(res, 255, val, 1)
+
+/* Resp QPC Get */
+#define RES_QPC_GET_DESTINATION_QP(res) NIC_GET_BITS(res, 0, 24)
+#define RES_QPC_GET_PORT(res) NIC_GET_BITS(res, 24, 2)
+#define RES_QPC_GET_PRIORITY(res) NIC_GET_BITS(res, 26, 2)
+#define RES_QPC_GET_CONN_STATE(res) NIC_GET_BITS(res, 28, 2)
+#define RES_QPC_GET_NACK_SYNDROME(res) NIC_GET_BITS(res, 30, 2)
+#define RES_QPC_GET_LKEY(res) NIC_GET_BITS(res, 32, 32)
+#define RES_QPC_GET_DST_IP(res) NIC_GET_BITS(res, 64, 32)
+#define RES_QPC_GET_DST_MAC_LSB(res) NIC_GET_BITS(res, 96, 32)
+#define RES_QPC_GET_DST_MAC_MSB(res) NIC_GET_BITS(res, 128, 16)
+#define RES_QPC_GET_ECN_COUNT(res) NIC_GET_BITS(res, 144, 5)
+#define RES_QPC_GET_TRANSPORT_SERVICE(res) NIC_GET_BITS(res, 149, 1)
+#define RES_QPC_GET_ASID(res) NIC_GET_BITS(res, 150, 10)
+#define RES_QPC_GET_PEER_QP(res) NIC_GET_BITS(res, 160, 24)
+#define RES_QPC_GET_SCHD_Q_NUM(res) NIC_GET_BITS(res, 184, 8)
+#define RES_QPC_GET_EXPECTED_PSN(res) NIC_GET_BITS(res, 192, 24)
+#define RES_QPC_GET_TRUST_LEVEL(res) NIC_GET_BITS(res, 216, 2)
+#define RES_QPC_GET_MOD_GAUDI1(res) NIC_GET_BITS(res, 218, 1)
+#define RES_QPC_GET_DATA_MMU_BYPASS(res) NIC_GET_BITS(res, 219, 1)
+#define RES_QPC_GET_ENCAP_TYPE(res) NIC_GET_BITS(res, 220, 3)
+#define RES_QPC_GET_ENCAP_ENABLE(res) NIC_GET_BITS(res, 223, 1)
+#define RES_QPC_GET_CYCLIC_IDX(res) NIC_GET_BITS(res, 224, 24)
+#define RES_QPC_GET_CQ_NUM(res) NIC_GET_BITS(res, 248, 5)
+#define RES_QPC_GET_PEER_WQ_GRAN(res) NIC_GET_BITS(res, 253, 1)
+#define RES_QPC_GET_IN_WORK(res) NIC_GET_BITS(res, 254, 1)
+#define RES_QPC_GET_VALID(res) NIC_GET_BITS(res, 255, 1)
+
+struct gaudi2_sq_wqe {
+ u64 data[4];
+};
+
+/* TX WQE Get */
+#define TX_WQE_GET_OPCODE(wqe) NIC_GET_BITS(wqe, 0, 5)
+#define TX_WQE_GET_TRACE_EVENT_DATA(wqe) NIC_GET_BITS(wqe, 5, 1)
+#define TX_WQE_GET_TRACE_EVENT(wqe) NIC_GET_BITS(wqe, 6, 1)
+#define TX_WQE_GET_WQE_INDEX(wqe) NIC_GET_BITS(wqe, 8, 8)
+#define TX_WQE_GET_REDUCTION_OPCODE(wqe) NIC_GET_BITS(wqe, 16, 13)
+#define TX_WQE_GET_SE(wqe) NIC_GET_BITS(wqe, 29, 1)
+#define TX_WQE_GET_INLINE(wqe) NIC_GET_BITS(wqe, 30, 1)
+#define TX_WQE_GET_ACKREQ(wqe) NIC_GET_BITS(wqe, 31, 1)
+#define TX_WQE_GET_SIZE(wqe) NIC_GET_BITS(wqe, 32, 32)
+#define TX_WQE_GET_LOCAL_ADDR_LSB(wqe) NIC_GET_BITS(wqe, 64, 32)
+#define TX_WQE_GET_LOCAL_ADDR_MSB(wqe) NIC_GET_BITS(wqe, 96, 32)
+#define TX_WQE_GET_REMOTE_ADDR_LSB(wqe) NIC_GET_BITS(wqe, 128, 32)
+#define TX_WQE_GET_REMOTE_ADDR_MSB(wqe) NIC_GET_BITS(wqe, 160, 32)
+#define TX_WQE_GET_TAG(wqe) NIC_GET_BITS(wqe, 192, 32)
+#define TX_WQE_GET_REMOTE_SOB(wqe) NIC_GET_BITS(wqe, 224, 27)
+#define TX_WQE_GET_REMOTE_SOB_DATA(wqe) NIC_GET_BITS(wqe, 251, 2)
+#define TX_WQE_GET_SOB_CMD(wqe) NIC_GET_BITS(wqe, 253, 1)
+#define TX_WQE_GET_COMPLETION_TYPE(wqe) NIC_GET_BITS(wqe, 254, 2)
+
+/* TX WQE Set */
+#define CFG_SQ_WQE_RESET(swq) memset((swq)->data, 0, sizeof(u64) * 4)
+
+#define CFG_SQ_WQE_OPCODE(swq, val) \
+ ((swq)->data[0] |= (val))
+#define CFG_SQ_WQE_INDEX(swq, val) \
+ ((swq)->data[0] |= (val) << 8)
+#define CFG_SQ_WQE_SOL_EVENT(swq, val) \
+ ((swq)->data[0] |= (val) << 29)
+#define CFG_SQ_WQE_INLINE(swq, val) \
+ ((swq)->data[0] |= (val) << 30)
+#define CFG_SQ_WQE_SIZE(swq, val) \
+ ((swq)->data[0] |= (val) << 32)
+#define CFG_SQ_WQE_LOCAL_ADDRESS(swq, val) \
+ ((swq)->data[1] = (val))
+struct gaudi2_rq_wqe {
+ u64 data[2];
+};
+
+/* RX WQE Get */
+#define RX_WQE_GET_OPCODE(wqe) NIC_GET_BITS(wqe, 0, 5)
+#define RX_WQE_GET_WQE_INDEX(wqe) NIC_GET_BITS(wqe, 8, 8)
+#define RX_WQE_GET_SOB_CMD(wqe) NIC_GET_BITS(wqe, 31, 1)
+#define RX_WQE_GET_LOCAL_SOB(wqe) NIC_GET_BITS(wqe, 32, 27)
+#define RX_WQE_GET_LOCAL_SOB_DATA(wqe) NIC_GET_BITS(wqe, 59, 3)
+#define RX_WQE_GET_COMPLETION_TYPE(wqe) NIC_GET_BITS(wqe, 62, 2)
+#define RX_WQE_GET_SIZE(wqe) NIC_GET_BITS(wqe, 64, 32)
+#define RX_WQE_GET_TAG(wqe) NIC_GET_BITS(wqe, 96, 32)
+
+struct gaudi2_cqe {
+ u32 data[4];
+};
+
+#define CQE_IS_VALID(cqe) (((cqe)->data[0] >> 31) & 1)
+#define CQE_IS_REQ(cqe) (((cqe)->data[0] >> 24) & 1)
+#define CQE_QPN(cqe) ((cqe)->data[0] & 0xFFFFFF)
+#define CQE_SET_INVALID(cqe) ((cqe)->data[0] &= ~(1ull << 31))
+#define CQE_WQE_IDX(cqe) ((cqe)->data[1])
+#define CQE_TAG(cqe) ((cqe)->data[2])
+#define CQE_RAW_PKT_SIZE(cqe) ((cqe)->data[3])
+
+#define EQE_HEADER(valid, type) ((!!(valid) << 31) | (type))
+#define EQE_TYPE(eqe) ((eqe)->data[0] & 0xf)
+#define EQE_IS_VALID(eqe) (((eqe)->data[0] >> 31) & 0x1)
+#define EQE_SET_INVALID(eqe) ((eqe)->data[0] &= ~(1ull << 31))
+#define EQE_CQ_EVENT_CQ_NUM(eqe) ((eqe)->data[1] & 0xffff)
+#define EQE_CQ_EVENT_PI(eqe) ((eqe)->data[2])
+#define EQE_CQ_EVENT_CCQ_NUM(eqe) ((eqe)->data[1] & 0xffff)
+
+#define EQE_QP_EVENT_QPN(eqe) ((eqe)->data[1] & 0xffffff)
+#define EQE_QP_EVENT_RESET(eqe) (((eqe)->data[1] >> 31) & 0x1)
+#define EQE_QP_EVENT_ERR_SYND(eqe) ((eqe)->data[2])
+
+#define EQE_RAW_TX_EVENT_QPN(eqe) ((eqe)->data[1] & 0xffffff)
+#define EQE_RAW_TX_EVENT_IDX(eqe) ((eqe)->data[2] & 0xffffffff)
+
+#define EQE_LINK_STATUS_TIME_STAMP(eqe) ((eqe)->data[1])
+#define EQE_LINK_STATUS(eqe) ((eqe)->data[2] & 0xf)
+
+#define EQE_DB_EVENT_DB_NUM(eqe) ((eqe)->data[1] & 0xffff)
+
+#define EQE_SW_EVENT_QPN(eqe) ((eqe)->data[1] & 0xffffff)
+
+#define EQ_IDX_MASK GENMASK(23, 0)
+
+/**
+ * struct gaudi2_en_tx_buf - indicates a tx buffer
+ * @skb: the transmitted skb
+ * @dma_addr: the skb's mapped dma address
+ * @len: buffer size
+ */
+struct gaudi2_en_tx_buf {
+ struct sk_buff *skb;
+ dma_addr_t dma_addr;
+ int len;
+};
+
+/**
+ * struct gaudi2_en_aux_data - Gaudi2 Ethernet driver data.
+ * @rx_rings: array of the Rx rings of all ports.
+ * @cq_rings: array of the CQ rings of all ports.
+ * @wq_rings: array of the WQ rings of all ports.
+ * @kernel_asid: kernel ASID.
+ * @raw_qpn: raw data (Ethernet) QP number.
+ * @tx_ring_len: number of elements in the Tx ring.
+ * @schedq_num: sched-Q number used for the Eth driver of the port.
+ * @pad_size: the pad size in bytes for the skb to transmit.
+ */
+struct gaudi2_en_aux_data {
+ struct hbl_cn_ring **rx_rings;
+ struct hbl_cn_ring **cq_rings;
+ struct hbl_cn_ring **wq_rings;
+ u32 kernel_asid;
+ u32 raw_qpn;
+ u32 tx_ring_len;
+ u32 schedq_num;
+ u16 pad_size;
+};
+
+/**
+ * struct gaudi2_en_aux_ops - ASIC specific functions for cn <-> en drivers communication.
+ * @configure_cq: configure a CQ.
+ * @arm_cq: arm a CQ to issue an interrupt after reaching certain index or timeout.
+ * @write_rx_ci: write the Rx CI to the HW.
+ * @get_pfc_cnts: retrieve PFC counters.
+ * @ring_tx_doorbell: ring the Tx door bell so the HW will send it.
+ * @qp_err_syndrome_to_str: Convert error syndrome id to string.
+ * @db_fifo_reset: Reset Ethernet doorbell fifo.
+ * @port_reset_locked: reset the port assuming we are under lock.
+ * @get_overrun_cnt: get db fifo overrun counter.
+ */
+struct gaudi2_en_aux_ops {
+ /* en2cn */
+ void (*configure_cq)(struct hbl_aux_dev *aux_dev, u32 port, u16 coalesce_usec, bool enable);
+ void (*arm_cq)(struct hbl_aux_dev *aux_dev, u32 port, u32 index);
+ void (*write_rx_ci)(struct hbl_aux_dev *aux_dev, u32 port, u32 ci);
+ void (*get_pfc_cnts)(struct hbl_aux_dev *aux_dev, u32 port, int pfc_prio,
+ u64 *indications, u64 *requests);
+ int (*ring_tx_doorbell)(struct hbl_aux_dev *aux_dev, u32 port, u32 pi, bool *full_after_tx);
+ char* (*qp_err_syndrome_to_str)(u32 syndrome);
+ void (*db_fifo_reset)(struct hbl_aux_dev *aux_dev, u32 port);
+
+ /* cn2en */
+ int (*port_reset_locked)(struct hbl_aux_dev *aux_dev, u32 port);
+ u32 (*get_overrun_cnt)(struct hbl_aux_dev *aux_dev, u32 port_idx);
+};
+
+#endif /* HBL_GAUDI2_H_ */
diff --git a/include/linux/net/intel/gaudi2_aux.h b/include/linux/net/intel/gaudi2_aux.h
new file mode 100644
index 000000000000..6b2025ff5713
--- /dev/null
+++ b/include/linux/net/intel/gaudi2_aux.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#ifndef HBL_GAUDI2_AUX_H_
+#define HBL_GAUDI2_AUX_H_
+
+#include <linux/types.h>
+#include <linux/net/intel/cn_aux.h>
+
+enum gaudi2_setup_type {
+ GAUDI2_SETUP_TYPE_HLS2,
+};
+
+/**
+ * struct gaudi2_cn_aux_data - Gaudi2 CN driver data.
+ * @setup_type: type of setup connectivity.
+ * @cfg_base: configuration space base address.
+ * @irq_num_port_base: base IRQ number for port EQ.
+ * @sob_id_base: first reserved SOB ID.
+ * @sob_inc_cfg_val: configuration value for incrementing SOB by one.
+ * @fw_security_enabled: FW security enabled.
+ * @msix_enabled: MSI-X enabled.
+ */
+struct gaudi2_cn_aux_data {
+ enum gaudi2_setup_type setup_type;
+ u64 cfg_base;
+ u32 irq_num_port_base;
+ u32 sob_id_base;
+ u32 sob_inc_cfg_val;
+ u8 fw_security_enabled;
+ u8 msix_enabled;
+};
+
+/**
+ * struct gaudi2_cn_aux_ops - ASIC specific functions for cn <-> compute drivers communication.
+ * @get_event_name: Translate event type to name.
+ * @poll_mem: Poll on a memory address until a given condition is fulfilled or timeout.
+ * @dma_alloc_coherent: Allocate coherent DMA memory.
+ * @dma_free_coherent: Free coherent DMA memory.
+ * @dma_pool_zalloc: Allocate small size DMA memory from the pool.
+ * @dma_pool_free: Free small size DMA memory from the pool.
+ * @spmu_get_stats_info: get SPMU statistics information.
+ * @spmu_config: config the SPMU.
+ * @spmu_sample: read SPMU counters.
+ * @poll_reg: Poll on a register until a given condition is fulfilled or timeout.
+ * @send_cpu_message: send message to F/W. If the message is timedout, the driver will eventually
+ * reset the device. The timeout is passed as an argument. If it is 0 the
+ * timeout set is the default timeout for the specific ASIC.
+ * @post_send_status: handler for post sending status packet to FW.
+ * @reset_prepare: Prepare to reset.
+ * @reset_late_init: Notify that compute device finished reset.
+ * @sw_err_event_handler: Handle SW error event.
+ * @axi_error_response_event_handler: Handle AXI error.
+ * @ports_stop_prepare: prepare the ports for a stop.
+ * @send_port_cpucp_status: Send port status to FW.
+ */
+struct gaudi2_cn_aux_ops {
+ /* cn2compute */
+ char *(*get_event_name)(struct hbl_aux_dev *aux_dev, u16 event_type);
+ int (*poll_mem)(struct hbl_aux_dev *aux_dev, u32 *addr, u32 *val,
+ hbl_cn_poll_cond_func func);
+ void *(*dma_alloc_coherent)(struct hbl_aux_dev *aux_dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t flag);
+ void (*dma_free_coherent)(struct hbl_aux_dev *aux_dev, size_t size, void *cpu_addr,
+ dma_addr_t dma_handle);
+ void *(*dma_pool_zalloc)(struct hbl_aux_dev *aux_dev, size_t size, gfp_t mem_flags,
+ dma_addr_t *dma_handle);
+ void (*dma_pool_free)(struct hbl_aux_dev *aux_dev, void *vaddr, dma_addr_t dma_addr);
+ void (*spmu_get_stats_info)(struct hbl_aux_dev *aux_dev, u32 port,
+ struct hbl_cn_stat **stats, u32 *n_stats);
+ int (*spmu_config)(struct hbl_aux_dev *aux_dev, u32 port, u32 num_event_types,
+ u32 event_types[], bool enable);
+ int (*spmu_sample)(struct hbl_aux_dev *aux_dev, u32 port, u32 num_out_data, u64 out_data[]);
+ int (*poll_reg)(struct hbl_aux_dev *aux_dev, u32 reg, u64 timeout_us,
+ hbl_cn_poll_cond_func func, void *arg);
+ int (*send_cpu_message)(struct hbl_aux_dev *aux_dev, u32 *msg, u16 len, u32 timeout,
+ u64 *result);
+ void (*post_send_status)(struct hbl_aux_dev *aux_dev, u32 port);
+ /* compute2cn */
+ void (*reset_prepare)(struct hbl_aux_dev *aux_dev);
+ void (*reset_late_init)(struct hbl_aux_dev *aux_dev);
+ int (*sw_err_event_handler)(struct hbl_aux_dev *aux_dev, u16 event_type, u8 macro_index,
+ struct hl_eq_nic_intr_cause *intr_cause_cpucp);
+ int (*axi_error_response_event_handler)(struct hbl_aux_dev *aux_dev, u16 event_type,
+ u8 macro_index,
+ struct hl_eq_nic_intr_cause *intr_cause_cpucp);
+ void (*ports_stop_prepare)(struct hbl_aux_dev *aux_dev, bool fw_reset, bool in_teardown);
+ int (*send_port_cpucp_status)(struct hbl_aux_dev *aux_dev, u32 port, u8 cmd, u8 period);
+};
+
+#endif /* HBL_GAUDI2_AUX_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
` (7 preceding siblings ...)
2024-06-13 8:22 ` [PATCH 08/15] net: hbl_cn: gaudi2: ASIC specific support Omer Shpigelman
@ 2024-06-13 8:22 ` Omer Shpigelman
2024-06-13 21:49 ` Andrew Lunn
` (5 more replies)
2024-06-13 8:22 ` [PATCH 10/15] net: hbl_en: gaudi2: ASIC specific support Omer Shpigelman
` (7 subsequent siblings)
16 siblings, 6 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:22 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
This ethernet driver is initialized via auxiliary bus by the hbl_cn
driver.
It serves mainly for control operations that are needed for AI scaling.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
MAINTAINERS | 9 +
drivers/net/ethernet/intel/Kconfig | 18 +
drivers/net/ethernet/intel/Makefile | 1 +
drivers/net/ethernet/intel/hbl_en/Makefile | 9 +
.../net/ethernet/intel/hbl_en/common/Makefile | 3 +
.../net/ethernet/intel/hbl_en/common/hbl_en.c | 1168 +++++++++++++++++
.../net/ethernet/intel/hbl_en/common/hbl_en.h | 206 +++
.../intel/hbl_en/common/hbl_en_dcbnl.c | 101 ++
.../ethernet/intel/hbl_en/common/hbl_en_drv.c | 211 +++
.../intel/hbl_en/common/hbl_en_ethtool.c | 452 +++++++
10 files changed, 2178 insertions(+)
create mode 100644 drivers/net/ethernet/intel/hbl_en/Makefile
create mode 100644 drivers/net/ethernet/intel/hbl_en/common/Makefile
create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c
create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c
create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 096439a62129..7301f38e9cfb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9617,6 +9617,15 @@ F: include/linux/habanalabs/
F: include/linux/net/intel/cn*
F: include/linux/net/intel/gaudi2*
+HABANALABS ETHERNET DRIVER
+M: Omer Shpigelman <oshpigelman@habana.ai>
+L: netdev@vger.kernel.org
+S: Supported
+W: https://www.habana.ai
+F: Documentation/networking/device_drivers/ethernet/intel/hbl.rst
+F: drivers/net/ethernet/intel/hbl_en/
+F: include/linux/net/intel/cn*
+
HACKRF MEDIA DRIVER
L: linux-media@vger.kernel.org
S: Orphan
diff --git a/drivers/net/ethernet/intel/Kconfig b/drivers/net/ethernet/intel/Kconfig
index 0d1b8a2bae99..5d07349348a0 100644
--- a/drivers/net/ethernet/intel/Kconfig
+++ b/drivers/net/ethernet/intel/Kconfig
@@ -417,4 +417,22 @@ config HABANA_CN
To compile this driver as a module, choose M here. The module
will be called habanalabs_cn.
+config HABANA_EN
+ tristate "HabanaLabs (an Intel Company) Ethernet driver"
+ depends on NETDEVICES && ETHERNET && INET
+ select HABANA_CN
+ help
+ This driver enables Ethernet functionality for the network interfaces
+ that are part of the GAUDI ASIC family of AI Accelerators.
+ For more information on how to identify your adapter, go to the
+ Adapter & Driver ID Guide that can be located at:
+
+ <http://support.intel.com>
+
+ More specific information on configuring the driver is in
+ <file:Documentation/networking/device_drivers/ethernet/intel/hbl.rst>.
+
+ To compile this driver as a module, choose M here. The module
+ will be called habanalabs_en.
+
endif # NET_VENDOR_INTEL
diff --git a/drivers/net/ethernet/intel/Makefile b/drivers/net/ethernet/intel/Makefile
index 10049a28e336..ec62a0227897 100644
--- a/drivers/net/ethernet/intel/Makefile
+++ b/drivers/net/ethernet/intel/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_FM10K) += fm10k/
obj-$(CONFIG_ICE) += ice/
obj-$(CONFIG_IDPF) += idpf/
obj-$(CONFIG_HABANA_CN) += hbl_cn/
+obj-$(CONFIG_HABANA_EN) += hbl_en/
diff --git a/drivers/net/ethernet/intel/hbl_en/Makefile b/drivers/net/ethernet/intel/hbl_en/Makefile
new file mode 100644
index 000000000000..695497ab93b6
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_en/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Makefile for HabanaLabs (an Intel Company) Ethernet network driver
+#
+
+obj-$(CONFIG_HABANA_EN) := habanalabs_en.o
+
+include $(src)/common/Makefile
+habanalabs_en-y += $(HBL_EN_COMMON_FILES)
diff --git a/drivers/net/ethernet/intel/hbl_en/common/Makefile b/drivers/net/ethernet/intel/hbl_en/common/Makefile
new file mode 100644
index 000000000000..a3ccb5dbf4a6
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_en/common/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+HBL_EN_COMMON_FILES := common/hbl_en_drv.o common/hbl_en.o \
+ common/hbl_en_ethtool.o common/hbl_en_dcbnl.o
diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
new file mode 100644
index 000000000000..066be5ac2d84
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
@@ -0,0 +1,1168 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "hbl_en.h"
+#include <linux/inetdevice.h>
+
+#define TX_TIMEOUT (5 * HZ)
+#define PORT_RESET_TIMEOUT_MSEC (60 * 1000ull) /* 60s */
+
+/**
+ * struct hbl_en_tx_pkt_work - used to schedule a work of a Tx packet.
+ * @tx_work: workqueue object to run when packet needs to be sent.
+ * @port: pointer to current port structure.
+ * @skb: copy of the packet to send.
+ */
+struct hbl_en_tx_pkt_work {
+ struct work_struct tx_work;
+ struct hbl_en_port *port;
+ struct sk_buff *skb;
+};
+
+static int hbl_en_napi_poll(struct napi_struct *napi, int budget);
+static int hbl_en_port_open(struct hbl_en_port *port);
+
+static int hbl_en_ports_reopen(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_en_device *hdev = aux_dev->priv;
+ struct hbl_en_port *port;
+ int rc = 0, i;
+
+ for (i = 0; i < hdev->max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ port = &hdev->ports[i];
+
+ /* It could be that the port was shutdown by 'ip link set down' and there is no need
+ * in reopening it.
+ * Since we mark the ports as in reset even if they are disabled, we clear the flag
+ * here anyway.
+ * See hbl_en_ports_stop_prepare() for more info.
+ */
+ if (!netif_running(port->ndev)) {
+ atomic_set(&port->in_reset, 0);
+ continue;
+ }
+
+ rc = hbl_en_port_open(port);
+
+ atomic_set(&port->in_reset, 0);
+
+ if (rc)
+ break;
+ }
+
+ hdev->in_reset = false;
+
+ return rc;
+}
+
+static void hbl_en_port_fini(struct hbl_en_port *port)
+{
+ if (port->rx_wq)
+ destroy_workqueue(port->rx_wq);
+}
+
+static int hbl_en_port_init(struct hbl_en_port *port)
+{
+ struct hbl_en_device *hdev = port->hdev;
+ u32 port_idx = port->idx;
+ char wq_name[32];
+ int rc;
+
+ if (hdev->poll_enable) {
+ memset(wq_name, 0, sizeof(wq_name));
+ snprintf(wq_name, sizeof(wq_name) - 1, "hbl%u-port%d-rx-wq", hdev->core_dev_id,
+ port_idx);
+ port->rx_wq = alloc_ordered_workqueue(wq_name, 0);
+ if (!port->rx_wq) {
+ dev_err(hdev->dev, "Failed to allocate Rx WQ\n");
+ rc = -ENOMEM;
+ goto fail;
+ }
+ }
+
+ hbl_en_ethtool_init_coalesce(port);
+
+ return 0;
+
+fail:
+ hbl_en_port_fini(port);
+
+ return rc;
+}
+
+static void _hbl_en_set_port_status(struct hbl_en_port *port, bool up)
+{
+ struct net_device *ndev = port->ndev;
+ u32 port_idx = port->idx;
+
+ if (up) {
+ netif_carrier_on(ndev);
+ netif_wake_queue(ndev);
+ } else {
+ netif_carrier_off(ndev);
+ netif_stop_queue(ndev);
+ }
+
+ /* Unless link events are getting through the EQ, no need to print about link down events
+ * during port reset
+ */
+ if (port->hdev->has_eq || up || !atomic_read(&port->in_reset))
+ netdev_info(port->ndev, "link %s, port %d\n", up ? "up" : "down", port_idx);
+}
+
+static void hbl_en_set_port_status(struct hbl_aux_dev *aux_dev, u32 port_idx, bool up)
+{
+ struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
+
+ _hbl_en_set_port_status(port, up);
+}
+
+static bool hbl_en_is_port_open(struct hbl_aux_dev *aux_dev, u32 port_idx)
+{
+ struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
+
+ return port->is_initialized;
+}
+
+/* get the src IP as it is done in devinet_ioctl() */
+static int hbl_en_get_src_ip(struct hbl_aux_dev *aux_dev, u32 port_idx, u32 *src_ip)
+{
+ struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
+ struct net_device *ndev = port->ndev;
+ struct in_device *in_dev;
+ struct in_ifaddr *ifa;
+ int rc = 0;
+
+ /* for the case where no src IP is configured */
+ *src_ip = 0;
+
+ /* rtnl lock should be acquired in relevant flows before taking configuration lock */
+ if (!rtnl_is_locked()) {
+ netdev_err(port->ndev, "Rtnl lock is not acquired, can't proceed\n");
+ rc = -EFAULT;
+ goto out;
+ }
+
+ in_dev = __in_dev_get_rtnl(ndev);
+ if (!in_dev) {
+ netdev_err(port->ndev, "Failed to get IPv4 struct\n");
+ rc = -EFAULT;
+ goto out;
+ }
+
+ ifa = rtnl_dereference(in_dev->ifa_list);
+
+ while (ifa) {
+ if (!strcmp(ndev->name, ifa->ifa_label)) {
+ /* convert the BE to native and later on it will be
+ * written to the HW as LE in QPC_SET
+ */
+ *src_ip = be32_to_cpu(ifa->ifa_local);
+ break;
+ }
+ ifa = rtnl_dereference(ifa->ifa_next);
+ }
+out:
+ return rc;
+}
+
+static void hbl_en_reset_stats(struct hbl_aux_dev *aux_dev, u32 port_idx)
+{
+ struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
+
+ port->net_stats.rx_packets = 0;
+ port->net_stats.tx_packets = 0;
+ port->net_stats.rx_bytes = 0;
+ port->net_stats.tx_bytes = 0;
+ port->net_stats.tx_errors = 0;
+ atomic64_set(&port->net_stats.rx_dropped, 0);
+ atomic64_set(&port->net_stats.tx_dropped, 0);
+}
+
+static u32 hbl_en_get_mtu(struct hbl_aux_dev *aux_dev, u32 port_idx)
+{
+ struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
+ struct net_device *ndev = port->ndev;
+ u32 mtu;
+
+ if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
+ netdev_err(ndev, "port is in reset, can't get MTU\n");
+ return 0;
+ }
+
+ mtu = ndev->mtu;
+
+ atomic_set(&port->in_reset, 0);
+
+ return mtu;
+}
+
+static u32 hbl_en_get_pflags(struct hbl_aux_dev *aux_dev, u32 port_idx)
+{
+ struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
+
+ return port->pflags;
+}
+
+static void hbl_en_set_dev_lpbk(struct hbl_aux_dev *aux_dev, u32 port_idx, bool enable)
+{
+ struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
+ struct net_device *ndev = port->ndev;
+
+ if (enable)
+ ndev->features |= NETIF_F_LOOPBACK;
+ else
+ ndev->features &= ~NETIF_F_LOOPBACK;
+}
+
+/* This function should be called after ctrl_lock was taken */
+static int hbl_en_port_open_locked(struct hbl_en_port *port)
+{
+ struct hbl_en_device *hdev = port->hdev;
+ struct net_device *ndev = port->ndev;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+ int rc;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ if (port->is_initialized)
+ return 0;
+
+ if (!hdev->poll_enable)
+ netif_napi_add(ndev, &port->napi, hbl_en_napi_poll);
+
+ rc = aux_ops->port_hw_init(aux_dev, port_idx);
+ if (rc) {
+ netdev_err(ndev, "Failed to configure the HW, rc %d\n", rc);
+ goto hw_init_fail;
+ }
+
+ if (!hdev->poll_enable)
+ napi_enable(&port->napi);
+
+ rc = hdev->asic_funcs.eth_port_open(port);
+ if (rc) {
+ netdev_err(ndev, "Failed to init H/W, rc %d\n", rc);
+ goto port_open_fail;
+ }
+
+ rc = aux_ops->update_mtu(aux_dev, port_idx, ndev->mtu);
+ if (rc) {
+ netdev_err(ndev, "MTU update failed, rc %d\n", rc);
+ goto update_mtu_fail;
+ }
+
+ rc = aux_ops->phy_init(aux_dev, port_idx);
+ if (rc) {
+ netdev_err(ndev, "PHY init failed, rc %d\n", rc);
+ goto phy_init_fail;
+ }
+
+ netif_start_queue(ndev);
+
+ port->is_initialized = true;
+
+ return 0;
+
+phy_init_fail:
+ /* no need to revert the MTU change, it will be updated on next port open */
+update_mtu_fail:
+ hdev->asic_funcs.eth_port_close(port);
+port_open_fail:
+ if (!hdev->poll_enable)
+ napi_disable(&port->napi);
+
+ aux_ops->port_hw_fini(aux_dev, port_idx);
+hw_init_fail:
+ if (!hdev->poll_enable)
+ netif_napi_del(&port->napi);
+
+ return rc;
+}
+
+static int hbl_en_port_open(struct hbl_en_port *port)
+{
+ struct hbl_en_device *hdev = port->hdev;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+ int rc;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ aux_ops->ctrl_lock(aux_dev, port_idx);
+ rc = hbl_en_port_open_locked(port);
+ aux_ops->ctrl_unlock(aux_dev, port_idx);
+
+ return rc;
+}
+
+static int hbl_en_open(struct net_device *netdev)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(netdev);
+ int rc;
+
+ if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
+ netdev_err(netdev, "port is in reset, can't open it\n");
+ return -EBUSY;
+ }
+
+ rc = hbl_en_port_open(port);
+
+ atomic_set(&port->in_reset, 0);
+
+ return rc;
+}
+
+/* This function should be called after ctrl_lock was taken */
+static void hbl_en_port_close_locked(struct hbl_en_port *port)
+{
+ struct hbl_en_device *hdev = port->hdev;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ if (!port->is_initialized)
+ return;
+
+ port->is_initialized = false;
+
+ /* verify that the port is marked as closed before continuing */
+ mb();
+
+ /* Print if not in hard reset flow e.g. from ip cmd */
+ if (!hdev->in_reset && netif_carrier_ok(port->ndev))
+ netdev_info(port->ndev, "port was closed\n");
+
+ /* disable the PHY here so no link changes will occur from this point forward */
+ aux_ops->phy_fini(aux_dev, port_idx);
+
+ /* disable Tx SW flow */
+ netif_carrier_off(port->ndev);
+ netif_tx_disable(port->ndev);
+
+ /* stop Tx/Rx HW */
+ aux_ops->port_hw_fini(aux_dev, port_idx);
+
+ /* disable Tx/Rx QPs */
+ hdev->asic_funcs.eth_port_close(port);
+
+ /* stop Rx SW flow */
+ if (hdev->poll_enable) {
+ hbl_en_rx_poll_stop(port);
+ } else {
+ napi_disable(&port->napi);
+ netif_napi_del(&port->napi);
+ }
+
+ /* Explicitly count the port close operations as we don't get a link event for this.
+ * Upon port open we receive a link event, hence no additional action required.
+ */
+ aux_ops->port_toggle_count(aux_dev, port_idx);
+}
+
+static void hbl_en_port_close(struct hbl_en_port *port)
+{
+ struct hbl_en_device *hdev = port->hdev;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ aux_ops->ctrl_lock(aux_dev, port_idx);
+ hbl_en_port_close_locked(port);
+ aux_ops->ctrl_unlock(aux_dev, port_idx);
+}
+
+/* This function should be called after ctrl_lock was taken */
+static int __hbl_en_port_reset_locked(struct hbl_en_port *port)
+{
+ hbl_en_port_close_locked(port);
+
+ return hbl_en_port_open_locked(port);
+}
+
+/* This function should be called after ctrl_lock was taken */
+int hbl_en_port_reset_locked(struct hbl_aux_dev *aux_dev, u32 port_idx)
+{
+ struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
+
+ return __hbl_en_port_reset_locked(port);
+}
+
+int hbl_en_port_reset(struct hbl_en_port *port)
+{
+ hbl_en_port_close(port);
+
+ /* Sleep in order to let obsolete events to be dropped before re-opening the port */
+ msleep(20);
+
+ return hbl_en_port_open(port);
+}
+
+static int hbl_en_close(struct net_device *netdev)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(netdev);
+ struct hbl_en_device *hdev = port->hdev;
+ ktime_t timeout;
+
+ /* Looks like the return value of this function is not checked, so we can't just return
+ * EBUSY if the port is under reset. We need to wait until the reset is finished and then
+ * close the port. Otherwise the netdev will set the port as closed although port_close()
+ * wasn't called. Only if we waited long enough and the reset hasn't finished, we can return
+ * an error without actually closing the port as it is a fatal flow anyway.
+ */
+ timeout = ktime_add_ms(ktime_get(), PORT_RESET_TIMEOUT_MSEC);
+ while (atomic_cmpxchg(&port->in_reset, 0, 1)) {
+ /* If this is called from unregister_netdev() then the port was already closed and
+ * hence we can safely return.
+ * We could have just check the port_open boolean, but that might hide some future
+ * bugs. Hence it is better to use a dedicated flag for that.
+ */
+ if (READ_ONCE(hdev->in_teardown))
+ return 0;
+
+ usleep_range(50, 200);
+ if (ktime_compare(ktime_get(), timeout) > 0) {
+ netdev_crit(netdev,
+ "Timeout while waiting for port to finish reset, can't close it\n"
+ );
+ return -EBUSY;
+ }
+ }
+
+ hbl_en_port_close(port);
+
+ atomic_set(&port->in_reset, 0);
+
+ return 0;
+}
+
+/**
+ * hbl_en_ports_stop_prepare() - stop the Rx and Tx and synchronize with other reset flows.
+ * @aux_dev: habanalabs auxiliary device structure.
+ *
+ * This function makes sure that during the reset no packets will be processed and that
+ * ndo_open/ndo_close do not open/close the ports.
+ * A hard reset might occur right after the driver was loaded, which means before the ports
+ * initialization was finished. Therefore, even if the ports are not yet open, we mark it as in
+ * reset in order to avoid races. We clear the in reset flag later on when reopening the ports.
+ */
+static void hbl_en_ports_stop_prepare(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_en_device *hdev = aux_dev->priv;
+ struct hbl_en_port *port;
+ ktime_t timeout;
+ int i;
+
+ /* Check if the ports where initialized. If not, we shouldn't mark them as in reset because
+ * they will fail to get opened.
+ */
+ if (!hdev->is_initialized || hdev->in_reset)
+ return;
+
+ for (i = 0; i < hdev->max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ port = &hdev->ports[i];
+
+ /* This function is competing with reset from ethtool/ip, so try to take the
+ * in_reset atomic and if we are already in a middle of reset, wait until reset
+ * function is finished.
+ * Reset function is designed to always finish (could take up to a few seconds in
+ * worst case).
+ * We mark also closed ports as in reset so they won't be able to get opened while
+ * the device in under reset.
+ */
+
+ timeout = ktime_add_ms(ktime_get(), PORT_RESET_TIMEOUT_MSEC);
+ while (atomic_cmpxchg(&port->in_reset, 0, 1)) {
+ usleep_range(50, 200);
+ if (ktime_compare(ktime_get(), timeout) > 0) {
+ netdev_crit(port->ndev,
+ "Timeout while waiting for port %d to finish reset\n",
+ port->idx);
+ break;
+ }
+ }
+ }
+
+ hdev->in_reset = true;
+}
+
+static void hbl_en_ports_stop(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_en_device *hdev = aux_dev->priv;
+ struct hbl_en_port *port;
+ int i;
+
+ for (i = 0; i < hdev->max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ port = &hdev->ports[i];
+
+ if (netif_running(port->ndev))
+ hbl_en_port_close(port);
+ }
+}
+
+static int hbl_en_change_mtu(struct net_device *netdev, int new_mtu)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(netdev);
+ int rc = 0;
+
+ if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
+ netdev_err(netdev, "port is in reset, can't change MTU\n");
+ return -EBUSY;
+ }
+
+ if (netif_running(port->ndev)) {
+ hbl_en_port_close(port);
+
+ /* Sleep in order to let obsolete events to be dropped before re-opening the port */
+ msleep(20);
+
+ netdev->mtu = new_mtu;
+
+ rc = hbl_en_port_open(port);
+ if (rc)
+ netdev_err(netdev, "Failed to reinit port for MTU change, rc %d\n", rc);
+ } else {
+ netdev->mtu = new_mtu;
+ }
+
+ atomic_set(&port->in_reset, 0);
+
+ return rc;
+}
+
+/* Swap source and destination MAC addresses */
+static inline void swap_l2(char *buf)
+{
+ u16 *eth_hdr, tmp;
+
+ eth_hdr = (u16 *)buf;
+ tmp = eth_hdr[0];
+ eth_hdr[0] = eth_hdr[3];
+ eth_hdr[3] = tmp;
+ tmp = eth_hdr[1];
+ eth_hdr[1] = eth_hdr[4];
+ eth_hdr[4] = tmp;
+ tmp = eth_hdr[2];
+ eth_hdr[2] = eth_hdr[5];
+ eth_hdr[5] = tmp;
+}
+
+/* Swap source and destination IP addresses
+ */
+static inline void swap_l3(char *buf)
+{
+ u32 tmp;
+
+ /* skip the Ethernet header and the IP header till source IP address */
+ buf += ETH_HLEN + 12;
+ tmp = ((u32 *)buf)[0];
+ ((u32 *)buf)[0] = ((u32 *)buf)[1];
+ ((u32 *)buf)[1] = tmp;
+}
+
+static void do_tx_swap(struct hbl_en_port *port, struct sk_buff *skb)
+{
+ struct hbl_en_device *hdev = port->hdev;
+ u16 *tmp_buff = (u16 *)skb->data;
+ u32 port_idx = port->idx;
+
+ /* First, let's print the SKB we got */
+ dev_dbg_ratelimited(hdev->dev,
+ "Send [P%d]: dst-mac:%04x%04x%04x, src-mac:%04x%04x%04x, eth-type:%04x, len:%u\n",
+ port_idx, swab16(tmp_buff[0]), swab16(tmp_buff[1]), swab16(tmp_buff[2]),
+ swab16(tmp_buff[3]), swab16(tmp_buff[4]), swab16(tmp_buff[5]),
+ swab16(tmp_buff[6]), skb->len);
+
+ /* Before submit it to HW, in case this is ipv4 pkt, swap eth/ip addresses.
+ * that way, we may send ECMP (ping) to ourselves in LB cases.
+ */
+ swap_l2(skb->data);
+ if (swab16(tmp_buff[6]) == ETH_P_IP)
+ swap_l3(skb->data);
+}
+
+static bool is_pkt_swap_enabled(struct hbl_en_device *hdev)
+{
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ return aux_ops->is_eth_lpbk(aux_dev);
+}
+
+static bool is_tx_disabled(struct hbl_en_port *port)
+{
+ struct hbl_en_device *hdev = port->hdev;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ return aux_ops->get_mac_lpbk(aux_dev, port_idx) && !is_pkt_swap_enabled(hdev);
+}
+
+static netdev_tx_t hbl_en_handle_tx(struct hbl_en_port *port, struct sk_buff *skb)
+{
+ struct hbl_en_device *hdev = port->hdev;
+ netdev_tx_t ret;
+
+ if (skb->len <= 0 || is_tx_disabled(port))
+ goto free_skb;
+
+ if (skb->len > hdev->max_frm_len) {
+ netdev_err(port->ndev, "Tx pkt size %uB exceeds maximum of %uB\n", skb->len,
+ hdev->max_frm_len);
+ goto free_skb;
+ }
+
+ if (is_pkt_swap_enabled(hdev))
+ do_tx_swap(port, skb);
+
+ /* Pad the ethernet packets to the minimum frame size as the NIC hw doesn't do it.
+ * eth_skb_pad() frees the packet on failure, so just increment the dropped counter and
+ * return as success to avoid a retry.
+ */
+ if (skb_put_padto(skb, hdev->pad_size)) {
+ dev_err_ratelimited(hdev->dev, "Padding failed, the skb is dropped\n");
+ atomic64_inc(&port->net_stats.tx_dropped);
+ return NETDEV_TX_OK;
+ }
+
+ ret = hdev->asic_funcs.write_pkt_to_hw(port, skb);
+ if (ret == NETDEV_TX_OK) {
+ port->net_stats.tx_packets++;
+ port->net_stats.tx_bytes += skb->len;
+ }
+
+ return ret;
+
+free_skb:
+ dev_kfree_skb_any(skb);
+ return NETDEV_TX_OK;
+}
+
+static netdev_tx_t hbl_en_start_xmit(struct sk_buff *skb, struct net_device *netdev)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(netdev);
+ struct hbl_en_device *hdev;
+
+ hdev = port->hdev;
+
+ return hbl_en_handle_tx(port, skb);
+}
+
+static int hbl_en_set_port_mac_loopback(struct hbl_en_port *port, bool enable)
+{
+ struct hbl_en_device *hdev = port->hdev;
+ struct net_device *ndev = port->ndev;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+ int rc;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ rc = aux_ops->set_mac_lpbk(aux_dev, port_idx, enable);
+ if (rc)
+ return rc;
+
+ netdev_info(ndev, "port %u: mac loopback is %s\n", port_idx,
+ enable ? "enabled" : "disabled");
+
+ if (netif_running(ndev)) {
+ rc = hbl_en_port_reset(port);
+ if (rc) {
+ netdev_err(ndev, "Failed to reset port %u, rc %d\n", port_idx, rc);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+static int hbl_en_set_features(struct net_device *netdev, netdev_features_t features)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(netdev);
+ netdev_features_t changed;
+ int rc = 0;
+
+ if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
+ netdev_err(netdev, "port %d is in reset, can't update settings", port->idx);
+ return -EBUSY;
+ }
+
+ changed = netdev->features ^ features;
+
+ if (changed & NETIF_F_LOOPBACK)
+ rc = hbl_en_set_port_mac_loopback(port, !!(features & NETIF_F_LOOPBACK));
+
+ atomic_set(&port->in_reset, 0);
+
+ return rc;
+}
+
+static void hbl_en_handle_tx_timeout(struct net_device *netdev, unsigned int txqueue)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(netdev);
+
+ port->net_stats.tx_errors++;
+ atomic64_inc(&port->net_stats.tx_dropped);
+}
+
+static void hbl_en_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(dev);
+
+ stats->rx_bytes = port->net_stats.rx_bytes;
+ stats->tx_bytes = port->net_stats.tx_bytes;
+ stats->rx_packets = port->net_stats.rx_packets;
+ stats->tx_packets = port->net_stats.tx_packets;
+ stats->tx_errors = port->net_stats.tx_errors;
+ stats->tx_dropped = (u64)atomic64_read(&port->net_stats.tx_dropped);
+ stats->rx_dropped = (u64)atomic64_read(&port->net_stats.rx_dropped);
+}
+
+static const struct net_device_ops hbl_en_netdev_ops = {
+ .ndo_open = hbl_en_open,
+ .ndo_stop = hbl_en_close,
+ .ndo_start_xmit = hbl_en_start_xmit,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_change_mtu = hbl_en_change_mtu,
+ .ndo_set_features = hbl_en_set_features,
+ .ndo_get_stats64 = hbl_en_get_stats64,
+ .ndo_tx_timeout = hbl_en_handle_tx_timeout,
+};
+
+static void hbl_en_set_ops(struct net_device *ndev)
+{
+ ndev->netdev_ops = &hbl_en_netdev_ops;
+ ndev->ethtool_ops = hbl_en_ethtool_get_ops(ndev);
+#ifdef CONFIG_DCB
+ ndev->dcbnl_ops = &hbl_en_dcbnl_ops;
+#endif
+}
+
+static int hbl_en_port_register(struct hbl_en_port *port)
+{
+ struct hbl_en_device *hdev = port->hdev;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+ struct hbl_en_port **ptr;
+ struct net_device *ndev;
+ int rc;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ ndev = alloc_etherdev(sizeof(struct hbl_en_port *));
+ if (!ndev) {
+ dev_err(hdev->dev, "netdevice %d alloc failed\n", port_idx);
+ return -ENOMEM;
+ }
+
+ port->ndev = ndev;
+ SET_NETDEV_DEV(ndev, &hdev->pdev->dev);
+ ptr = netdev_priv(ndev);
+ *ptr = port;
+
+ /* necessary for creating multiple interfaces */
+ ndev->dev_port = port_idx;
+
+ hbl_en_set_ops(ndev);
+
+ ndev->watchdog_timeo = TX_TIMEOUT;
+ ndev->min_mtu = hdev->min_raw_mtu;
+ ndev->max_mtu = hdev->max_raw_mtu;
+
+ /* Add loopback capability to the device. */
+ ndev->hw_features |= NETIF_F_LOOPBACK;
+
+ /* If this port was set to loopback, set it also to the ndev features */
+ if (aux_ops->get_mac_lpbk(aux_dev, port_idx))
+ ndev->features |= NETIF_F_LOOPBACK;
+
+ eth_hw_addr_set(ndev, port->mac_addr);
+
+ /* It's more an intelligent poll wherein, we enable the Rx completion EQE event and then
+ * start the poll from there.
+ * Inside the polling thread, we read packets from hardware and then reschedule the poll
+ * only if there are more packets to be processed. Else we re-enable the CQ Arm interrupt
+ * and exit the poll.
+ */
+ if (hdev->poll_enable)
+ hbl_en_rx_poll_trigger_init(port);
+
+ netif_carrier_off(ndev);
+
+ rc = register_netdev(ndev);
+ if (rc) {
+ dev_err(hdev->dev, "Could not register netdevice %d\n", port_idx);
+ goto err;
+ }
+
+ return 0;
+
+err:
+ if (ndev) {
+ free_netdev(ndev);
+ port->ndev = NULL;
+ }
+
+ return rc;
+}
+
+static void dump_swap_pkt(struct hbl_en_port *port, struct sk_buff *skb)
+{
+ struct hbl_en_device *hdev = port->hdev;
+ u16 *tmp_buff = (u16 *)skb->data;
+ u32 port_idx = port->idx;
+
+ /* The SKB is ready now (before stripping-out the L2), print its content */
+ dev_dbg_ratelimited(hdev->dev,
+ "Recv [P%d]: dst-mac:%04x%04x%04x, src-mac:%04x%04x%04x, eth-type:%04x, len:%u\n",
+ port_idx, swab16(tmp_buff[0]), swab16(tmp_buff[1]), swab16(tmp_buff[2]),
+ swab16(tmp_buff[3]), swab16(tmp_buff[4]), swab16(tmp_buff[5]),
+ swab16(tmp_buff[6]), skb->len);
+}
+
+int hbl_en_handle_rx(struct hbl_en_port *port, int budget)
+{
+ struct hbl_en_device *hdev = port->hdev;
+ enum hbl_en_eth_pkt_status pkt_status;
+ struct net_device *ndev = port->ndev;
+ int rc, pkt_count = 0;
+ struct sk_buff *skb;
+ void *pkt_addr;
+ u32 pkt_size;
+
+ if (!netif_carrier_ok(ndev))
+ return 0;
+
+ while (pkt_count < budget) {
+ pkt_status = hdev->asic_funcs.read_pkt_from_hw(port, &pkt_addr, &pkt_size);
+
+ if (pkt_status == ETH_PKT_NONE)
+ break;
+
+ pkt_count++;
+
+ if (pkt_status == ETH_PKT_DROP) {
+ atomic64_inc(&port->net_stats.rx_dropped);
+ continue;
+ }
+
+ if (hdev->poll_enable)
+ skb = __netdev_alloc_skb_ip_align(ndev, pkt_size, GFP_KERNEL);
+ else
+ skb = napi_alloc_skb(&port->napi, pkt_size);
+
+ if (!skb) {
+ atomic64_inc(&port->net_stats.rx_dropped);
+ break;
+ }
+
+ skb_copy_to_linear_data(skb, pkt_addr, pkt_size);
+ skb_put(skb, pkt_size);
+
+ if (is_pkt_swap_enabled(hdev))
+ dump_swap_pkt(port, skb);
+
+ skb->protocol = eth_type_trans(skb, ndev);
+
+ /* Zero the packet buffer memory to avoid leak in case of wrong
+ * size is used when next packet populates the same memory
+ */
+ memset(pkt_addr, 0, pkt_size);
+
+ /* polling is done in thread context and hence BH should be disabled */
+ if (hdev->poll_enable)
+ local_bh_disable();
+
+ rc = netif_receive_skb(skb);
+
+ if (hdev->poll_enable)
+ local_bh_enable();
+
+ if (rc == NET_RX_SUCCESS) {
+ port->net_stats.rx_packets++;
+ port->net_stats.rx_bytes += pkt_size;
+ } else {
+ atomic64_inc(&port->net_stats.rx_dropped);
+ }
+ }
+
+ return pkt_count;
+}
+
+static bool __hbl_en_rx_poll_schedule(struct hbl_en_port *port, unsigned long delay)
+{
+ return queue_delayed_work(port->rx_wq, &port->rx_poll_work, delay);
+}
+
+static void hbl_en_rx_poll_work(struct work_struct *work)
+{
+ struct hbl_en_port *port = container_of(work, struct hbl_en_port, rx_poll_work.work);
+ struct hbl_en_device *hdev = port->hdev;
+ int pkt_count;
+
+ pkt_count = hbl_en_handle_rx(port, NAPI_POLL_WEIGHT);
+
+ /* Reschedule the poll if we have consumed budget which means we still have packets to
+ * process. Else re-enable the Rx IRQs and exit the work.
+ */
+ if (pkt_count < NAPI_POLL_WEIGHT)
+ hdev->asic_funcs.reenable_rx_irq(port);
+ else
+ __hbl_en_rx_poll_schedule(port, 0);
+}
+
+/* Rx poll init and trigger routines are used in event-driven setups where
+ * Rx polling is initialized once during init or open and started/triggered by the event handler.
+ */
+void hbl_en_rx_poll_trigger_init(struct hbl_en_port *port)
+{
+ INIT_DELAYED_WORK(&port->rx_poll_work, hbl_en_rx_poll_work);
+}
+
+bool hbl_en_rx_poll_start(struct hbl_en_port *port)
+{
+ return __hbl_en_rx_poll_schedule(port, msecs_to_jiffies(1));
+}
+
+void hbl_en_rx_poll_stop(struct hbl_en_port *port)
+{
+ cancel_delayed_work_sync(&port->rx_poll_work);
+}
+
+static int hbl_en_napi_poll(struct napi_struct *napi, int budget)
+{
+ struct hbl_en_port *port = container_of(napi, struct hbl_en_port, napi);
+ struct hbl_en_device *hdev = port->hdev;
+ int pkt_count;
+
+ /* exit if we are called by netpoll as we free the Tx ring via EQ (if enabled) */
+ if (!budget)
+ return 0;
+
+ pkt_count = hbl_en_handle_rx(port, budget);
+
+ /* If budget not fully consumed, exit the polling mode */
+ if (pkt_count < budget) {
+ napi_complete_done(napi, pkt_count);
+ hdev->asic_funcs.reenable_rx_irq(port);
+ }
+
+ return pkt_count;
+}
+
+static void hbl_en_port_unregister(struct hbl_en_port *port)
+{
+ struct net_device *ndev = port->ndev;
+
+ unregister_netdev(ndev);
+ free_netdev(ndev);
+ port->ndev = NULL;
+}
+
+static int hbl_en_set_asic_funcs(struct hbl_en_device *hdev)
+{
+ switch (hdev->asic_type) {
+ case HBL_ASIC_GAUDI2:
+ default:
+ dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void hbl_en_handle_eqe(struct hbl_aux_dev *aux_dev, u32 port, struct hbl_cn_eqe *eqe)
+{
+ struct hbl_en_device *hdev = aux_dev->priv;
+
+ hdev->asic_funcs.handle_eqe(aux_dev, port, eqe);
+}
+
+static void hbl_en_set_aux_ops(struct hbl_en_device *hdev, bool enable)
+{
+ struct hbl_en_aux_ops *aux_ops = hdev->aux_dev->aux_ops;
+
+ if (enable) {
+ aux_ops->ports_reopen = hbl_en_ports_reopen;
+ aux_ops->ports_stop_prepare = hbl_en_ports_stop_prepare;
+ aux_ops->ports_stop = hbl_en_ports_stop;
+ aux_ops->set_port_status = hbl_en_set_port_status;
+ aux_ops->is_port_open = hbl_en_is_port_open;
+ aux_ops->get_src_ip = hbl_en_get_src_ip;
+ aux_ops->reset_stats = hbl_en_reset_stats;
+ aux_ops->get_mtu = hbl_en_get_mtu;
+ aux_ops->get_pflags = hbl_en_get_pflags;
+ aux_ops->set_dev_lpbk = hbl_en_set_dev_lpbk;
+ aux_ops->handle_eqe = hbl_en_handle_eqe;
+ } else {
+ aux_ops->ports_reopen = NULL;
+ aux_ops->ports_stop_prepare = NULL;
+ aux_ops->ports_stop = NULL;
+ aux_ops->set_port_status = NULL;
+ aux_ops->is_port_open = NULL;
+ aux_ops->get_src_ip = NULL;
+ aux_ops->reset_stats = NULL;
+ aux_ops->get_mtu = NULL;
+ aux_ops->get_pflags = NULL;
+ aux_ops->set_dev_lpbk = NULL;
+ aux_ops->handle_eqe = NULL;
+ }
+}
+
+int hbl_en_dev_init(struct hbl_en_device *hdev)
+{
+ struct hbl_en_asic_funcs *asic_funcs = &hdev->asic_funcs;
+ struct hbl_en_port *port;
+ int rc, i, port_cnt = 0;
+
+ /* must be called before the call to dev_init() */
+ rc = hbl_en_set_asic_funcs(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "failed to set aux ops\n");
+ return rc;
+ }
+
+ rc = asic_funcs->dev_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "device init failed\n");
+ return rc;
+ }
+
+ /* init the function pointers here before calling hbl_en_port_register which sets up
+ * net_device_ops, and its ops might start getting called.
+ * If any failure is encountered, these will be made NULL and the core driver won't call
+ * them.
+ */
+ hbl_en_set_aux_ops(hdev, true);
+
+ /* Port register depends on the above initialization so it must be called here and not
+ * before that.
+ */
+ for (i = 0; i < hdev->max_num_of_ports; i++, port_cnt++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ port = &hdev->ports[i];
+
+ rc = hbl_en_port_init(port);
+ if (rc) {
+ dev_err(hdev->dev, "port init failed\n");
+ goto unregister_ports;
+ }
+
+ rc = hbl_en_port_register(port);
+ if (rc) {
+ dev_err(hdev->dev, "port register failed\n");
+
+ hbl_en_port_fini(port);
+ goto unregister_ports;
+ }
+ }
+
+ hdev->is_initialized = true;
+
+ return 0;
+
+unregister_ports:
+ for (i = 0; i < port_cnt; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ port = &hdev->ports[i];
+
+ hbl_en_port_unregister(port);
+ hbl_en_port_fini(port);
+ }
+
+ hbl_en_set_aux_ops(hdev, false);
+
+ asic_funcs->dev_fini(hdev);
+
+ return rc;
+}
+
+void hbl_en_dev_fini(struct hbl_en_device *hdev)
+{
+ struct hbl_en_asic_funcs *asic_funcs = &hdev->asic_funcs;
+ struct hbl_en_port *port;
+ int i;
+
+ hdev->in_teardown = true;
+
+ if (!hdev->is_initialized)
+ return;
+
+ hdev->is_initialized = false;
+
+ for (i = 0; i < hdev->max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ port = &hdev->ports[i];
+
+ /* It could be this cleanup flow is called after a failed init flow.
+ * Hence we need to check that we indeed have a netdev to unregister.
+ */
+ if (!port->ndev)
+ continue;
+
+ hbl_en_port_unregister(port);
+ hbl_en_port_fini(port);
+ }
+
+ hbl_en_set_aux_ops(hdev, false);
+
+ asic_funcs->dev_fini(hdev);
+}
+
+dma_addr_t hbl_en_dma_map(struct hbl_en_device *hdev, void *addr, int len)
+{
+ dma_addr_t dma_addr;
+
+ if (hdev->dma_map_support)
+ dma_addr = dma_map_single(&hdev->pdev->dev, addr, len, DMA_TO_DEVICE);
+ else
+ dma_addr = virt_to_phys(addr);
+
+ return dma_addr;
+}
+
+void hbl_en_dma_unmap(struct hbl_en_device *hdev, dma_addr_t dma_addr, int len)
+{
+ if (hdev->dma_map_support)
+ dma_unmap_single(&hdev->pdev->dev, dma_addr, len, DMA_TO_DEVICE);
+}
diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
new file mode 100644
index 000000000000..15504c1f3cfb
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#ifndef HABANALABS_EN_H_
+#define HABANALABS_EN_H_
+
+#include <linux/net/intel/cn.h>
+
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+
+#define HBL_EN_NAME "habanalabs_en"
+
+#define HBL_EN_PORT(aux_dev, idx) (&(((struct hbl_en_device *)(aux_dev)->priv)->ports[(idx)]))
+
+#define hbl_netdev_priv(ndev) \
+({ \
+ typecheck(struct net_device *, ndev); \
+ *(struct hbl_en_port **)netdev_priv(ndev); \
+})
+
+/**
+ * enum hbl_en_eth_pkt_status - status of Rx Ethernet packet.
+ * ETH_PKT_OK: packet was received successfully.
+ * ETH_PKT_DROP: packet should be dropped.
+ * ETH_PKT_NONE: no available packet.
+ */
+enum hbl_en_eth_pkt_status {
+ ETH_PKT_OK,
+ ETH_PKT_DROP,
+ ETH_PKT_NONE
+};
+
+/**
+ * struct hbl_en_net_stats - stats of Ethernet interface.
+ * rx_packets: number of packets received.
+ * tx_packets: number of packets sent.
+ * rx_bytes: total bytes of data received.
+ * tx_bytes: total bytes of data sent.
+ * tx_errors: number of errors in the TX.
+ * rx_dropped: number of packets dropped by the RX.
+ * tx_dropped: number of packets dropped by the TX.
+ */
+struct hbl_en_net_stats {
+ u64 rx_packets;
+ u64 tx_packets;
+ u64 rx_bytes;
+ u64 tx_bytes;
+ u64 tx_errors;
+ atomic64_t rx_dropped;
+ atomic64_t tx_dropped;
+};
+
+/**
+ * struct hbl_en_port - manage port common structure.
+ * @hdev: habanalabs Ethernet device structure.
+ * @ndev: network device.
+ * @rx_wq: WQ for Rx poll when we cannot schedule NAPI poll.
+ * @mac_addr: HW MAC addresses.
+ * @asic_specific: ASIC specific port structure.
+ * @napi: New API structure.
+ * @rx_poll_work: Rx work for polling mode.
+ * @net_stats: statistics of the ethernet interface.
+ * @in_reset: true if the NIC was marked as in reset, false otherwise. Used to avoid an additional
+ * stopping of the NIC if a hard reset was re-initiated.
+ * @pflags: ethtool private flags bit mask.
+ * @idx: index of this specific port.
+ * @rx_max_coalesced_frames: Maximum number of packets to receive before an RX interrupt.
+ * @tx_max_coalesced_frames: Maximum number of packets to be sent before a TX interrupt.
+ * @rx_coalesce_usecs: How many usecs to delay an RX interrupt after a packet arrives.
+ * @is_initialized: true if the port H/W is initialized, false otherwise.
+ * @pfc_enable: true if this port supports Priority Flow Control, false otherwise.
+ * @auto_neg_enable: is autoneg enabled.
+ * @auto_neg_resolved: was autoneg phase finished successfully.
+ */
+struct hbl_en_port {
+ struct hbl_en_device *hdev;
+ struct net_device *ndev;
+ struct workqueue_struct *rx_wq;
+ char *mac_addr;
+ void *asic_specific;
+ struct napi_struct napi;
+ struct delayed_work rx_poll_work;
+ struct hbl_en_net_stats net_stats;
+ atomic_t in_reset;
+ u32 pflags;
+ u32 idx;
+ u32 rx_max_coalesced_frames;
+ u32 tx_max_coalesced_frames;
+ u16 rx_coalesce_usecs;
+ u8 is_initialized;
+ u8 pfc_enable;
+ u8 auto_neg_enable;
+ u8 auto_neg_resolved;
+};
+
+/**
+ * struct hbl_en_asic_funcs - ASIC specific Ethernet functions.
+ * @dev_init: device init.
+ * @dev_fini: device cleanup.
+ * @reenable_rx_irq: re-enable Rx interrupts.
+ * @eth_port_open: initialize and open the Ethernet port.
+ * @eth_port_close: close the Ethernet port.
+ * @write_pkt_to_hw: write skb to HW.
+ * @read_pkt_from_hw: read pkt from HW.
+ * @get_pfc_cnts: get PFC counters.
+ * @set_coalesce: set Tx/Rx coalesce config in HW.
+ * @get_rx_ring size: get max number of elements the Rx ring can contain.
+ * @handle_eqe: Handle a received event.
+ */
+struct hbl_en_asic_funcs {
+ int (*dev_init)(struct hbl_en_device *hdev);
+ void (*dev_fini)(struct hbl_en_device *hdev);
+ void (*reenable_rx_irq)(struct hbl_en_port *port);
+ int (*eth_port_open)(struct hbl_en_port *port);
+ void (*eth_port_close)(struct hbl_en_port *port);
+ netdev_tx_t (*write_pkt_to_hw)(struct hbl_en_port *port, struct sk_buff *skb);
+ int (*read_pkt_from_hw)(struct hbl_en_port *port, void **pkt_addr, u32 *pkt_size);
+ void (*get_pfc_cnts)(struct hbl_en_port *port, void *ptr);
+ int (*set_coalesce)(struct hbl_en_port *port);
+ int (*get_rx_ring_size)(struct hbl_en_port *port);
+ void (*handle_eqe)(struct hbl_aux_dev *aux_dev, u32 port_idx, struct hbl_cn_eqe *eqe);
+};
+
+/**
+ * struct hbl_en_device - habanalabs Ethernet device structure.
+ * @pdev: pointer to PCI device.
+ * @dev: related kernel basic device structure.
+ * @ports: array of all ports manage common structures.
+ * @aux_dev: pointer to auxiliary device.
+ * @asic_specific: ASIC specific device structure.
+ * @fw_ver: FW version.
+ * @qsfp_eeprom: QSFPD EEPROM info.
+ * @mac_addr: array of all MAC addresses.
+ * @asic_funcs: ASIC specific Ethernet functions.
+ * @asic_type: ASIC specific type.
+ * @ports_mask: mask of available ports.
+ * @auto_neg_mask: mask of port with Autonegotiation enabled.
+ * @port_reset_timeout: max time in seconds for a port reset flow to finish.
+ * @pending_reset_long_timeout: long timeout for pending hard reset to finish in seconds.
+ * @max_frm_len: maximum allowed frame length.
+ * @raw_elem_size: size of element in raw buffers.
+ * @max_raw_mtu: maximum MTU size for raw packets.
+ * @min_raw_mtu: minimum MTU size for raw packets.
+ * @pad_size: the pad size in bytes for the skb to transmit.
+ * @core_dev_id: core device ID.
+ * @max_num_of_ports: max number of available ports;
+ * @in_reset: is the entire NIC currently under reset.
+ * @poll_enable: Enable Rx polling rather than IRQ + NAPI.
+ * @in_teardown: true if the NIC is in teardown (during device remove).
+ * @is_initialized: was the device initialized successfully.
+ * @has_eq: true if event queue is supported.
+ * @dma_map_support: HW supports DMA mapping.
+ */
+struct hbl_en_device {
+ struct pci_dev *pdev;
+ struct device *dev;
+ struct hbl_en_port *ports;
+ struct hbl_aux_dev *aux_dev;
+ void *asic_specific;
+ char *fw_ver;
+ char *qsfp_eeprom;
+ char *mac_addr;
+ struct hbl_en_asic_funcs asic_funcs;
+ enum hbl_cn_asic_type asic_type;
+ u64 ports_mask;
+ u64 auto_neg_mask;
+ u32 port_reset_timeout;
+ u32 pending_reset_long_timeout;
+ u32 max_frm_len;
+ u32 raw_elem_size;
+ u16 max_raw_mtu;
+ u16 min_raw_mtu;
+ u16 pad_size;
+ u16 core_dev_id;
+ u8 max_num_of_ports;
+ u8 in_reset;
+ u8 poll_enable;
+ u8 in_teardown;
+ u8 is_initialized;
+ u8 has_eq;
+ u8 dma_map_support;
+};
+
+int hbl_en_dev_init(struct hbl_en_device *hdev);
+void hbl_en_dev_fini(struct hbl_en_device *hdev);
+
+const struct ethtool_ops *hbl_en_ethtool_get_ops(struct net_device *ndev);
+void hbl_en_ethtool_init_coalesce(struct hbl_en_port *port);
+
+extern const struct dcbnl_rtnl_ops hbl_en_dcbnl_ops;
+
+bool hbl_en_rx_poll_start(struct hbl_en_port *port);
+void hbl_en_rx_poll_stop(struct hbl_en_port *port);
+void hbl_en_rx_poll_trigger_init(struct hbl_en_port *port);
+int hbl_en_port_reset(struct hbl_en_port *port);
+int hbl_en_port_reset_locked(struct hbl_aux_dev *aux_dev, u32 port_idx);
+int hbl_en_handle_rx(struct hbl_en_port *port, int budget);
+dma_addr_t hbl_en_dma_map(struct hbl_en_device *hdev, void *addr, int len);
+void hbl_en_dma_unmap(struct hbl_en_device *hdev, dma_addr_t dma_addr, int len);
+
+#endif /* HABANALABS_EN_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c
new file mode 100644
index 000000000000..5d718579a2b6
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "hbl_en.h"
+
+#define PFC_PRIO_MASK_ALL GENMASK(HBL_EN_PFC_PRIO_NUM - 1, 0)
+#define PFC_PRIO_MASK_NONE 0
+
+#ifdef CONFIG_DCB
+static int hbl_en_dcbnl_ieee_getpfc(struct net_device *netdev, struct ieee_pfc *pfc)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(netdev);
+ struct hbl_en_device *hdev;
+ u32 port_idx;
+
+ hdev = port->hdev;
+ port_idx = port->idx;
+
+ if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
+ dev_dbg_ratelimited(hdev->dev, "port %d is in reset, can't get PFC", port_idx);
+ return -EBUSY;
+ }
+
+ pfc->pfc_en = port->pfc_enable ? PFC_PRIO_MASK_ALL : PFC_PRIO_MASK_NONE;
+ pfc->pfc_cap = HBL_EN_PFC_PRIO_NUM;
+
+ hdev->asic_funcs.get_pfc_cnts(port, pfc);
+
+ atomic_set(&port->in_reset, 0);
+
+ return 0;
+}
+
+static int hbl_en_dcbnl_ieee_setpfc(struct net_device *netdev, struct ieee_pfc *pfc)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(netdev);
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_en_device *hdev;
+ u8 curr_pfc_en;
+ u32 port_idx;
+ int rc = 0;
+
+ hdev = port->hdev;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ port_idx = port->idx;
+
+ if (pfc->pfc_en & ~PFC_PRIO_MASK_ALL) {
+ dev_dbg_ratelimited(hdev->dev, "PFC supports %d priorities only, port %d\n",
+ HBL_EN_PFC_PRIO_NUM, port_idx);
+ return -EINVAL;
+ }
+
+ if (pfc->pfc_en != PFC_PRIO_MASK_NONE && pfc->pfc_en != PFC_PRIO_MASK_ALL) {
+ dev_dbg_ratelimited(hdev->dev,
+ "PFC should be enabled/disabled on all priorities, port %d\n",
+ port_idx);
+ return -EINVAL;
+ }
+
+ if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
+ dev_dbg_ratelimited(hdev->dev, "port %d is in reset, can't set PFC", port_idx);
+ return -EBUSY;
+ }
+
+ curr_pfc_en = port->pfc_enable ? PFC_PRIO_MASK_ALL : PFC_PRIO_MASK_NONE;
+
+ if (pfc->pfc_en == curr_pfc_en)
+ goto out;
+
+ port->pfc_enable = !port->pfc_enable;
+
+ rc = aux_ops->set_pfc(aux_dev, port_idx, port->pfc_enable);
+
+out:
+ atomic_set(&port->in_reset, 0);
+
+ return rc;
+}
+
+static u8 hbl_en_dcbnl_getdcbx(struct net_device *netdev)
+{
+ return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
+}
+
+static u8 hbl_en_dcbnl_setdcbx(struct net_device *netdev, u8 mode)
+{
+ return !(mode == (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE));
+}
+
+const struct dcbnl_rtnl_ops hbl_en_dcbnl_ops = {
+ .ieee_getpfc = hbl_en_dcbnl_ieee_getpfc,
+ .ieee_setpfc = hbl_en_dcbnl_ieee_setpfc,
+ .getdcbx = hbl_en_dcbnl_getdcbx,
+ .setdcbx = hbl_en_dcbnl_setdcbx
+};
+#endif
diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c
new file mode 100644
index 000000000000..23a87d36ded5
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#define pr_fmt(fmt) "habanalabs_en: " fmt
+
+#include "hbl_en.h"
+
+#include <linux/module.h>
+#include <linux/auxiliary_bus.h>
+
+#define HBL_DRIVER_AUTHOR "HabanaLabs Kernel Driver Team"
+
+#define HBL_DRIVER_DESC "HabanaLabs AI accelerators Ethernet driver"
+
+MODULE_AUTHOR(HBL_DRIVER_AUTHOR);
+MODULE_DESCRIPTION(HBL_DRIVER_DESC);
+MODULE_LICENSE("GPL");
+
+static bool poll_enable;
+
+module_param(poll_enable, bool, 0444);
+MODULE_PARM_DESC(poll_enable,
+ "Enable Rx polling rather than IRQ + NAPI (0 = no, 1 = yes, default: no)");
+
+static int hdev_init(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_en_aux_data *aux_data = aux_dev->aux_data;
+ struct hbl_en_port *ports, *port;
+ struct hbl_en_device *hdev;
+ int rc, i;
+
+ hdev = kzalloc(sizeof(*hdev), GFP_KERNEL);
+ if (!hdev)
+ return -ENOMEM;
+
+ ports = kcalloc(aux_data->max_num_of_ports, sizeof(*ports), GFP_KERNEL);
+ if (!ports) {
+ rc = -ENOMEM;
+ goto ports_alloc_fail;
+ }
+
+ aux_dev->priv = hdev;
+ hdev->aux_dev = aux_dev;
+ hdev->ports = ports;
+ hdev->pdev = aux_data->pdev;
+ hdev->dev = aux_data->dev;
+ hdev->ports_mask = aux_data->ports_mask;
+ hdev->auto_neg_mask = aux_data->auto_neg_mask;
+ hdev->max_num_of_ports = aux_data->max_num_of_ports;
+ hdev->core_dev_id = aux_data->id;
+ hdev->fw_ver = aux_data->fw_ver;
+ hdev->qsfp_eeprom = aux_data->qsfp_eeprom;
+ hdev->asic_type = aux_data->asic_type;
+ hdev->pending_reset_long_timeout = aux_data->pending_reset_long_timeout;
+ hdev->max_frm_len = aux_data->max_frm_len;
+ hdev->raw_elem_size = aux_data->raw_elem_size;
+ hdev->max_raw_mtu = aux_data->max_raw_mtu;
+ hdev->min_raw_mtu = aux_data->min_raw_mtu;
+ hdev->pad_size = ETH_ZLEN;
+ hdev->has_eq = aux_data->has_eq;
+ hdev->dma_map_support = true;
+ hdev->poll_enable = poll_enable;
+
+ for (i = 0; i < hdev->max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ port = &hdev->ports[i];
+ port->hdev = hdev;
+ port->idx = i;
+ port->pfc_enable = true;
+ port->pflags = PFLAGS_PCS_LINK_CHECK | PFLAGS_PHY_AUTO_NEG_LPBK;
+ port->mac_addr = aux_data->mac_addr[i];
+ port->auto_neg_enable = !!(aux_data->auto_neg_mask & BIT(i));
+ }
+
+ return 0;
+
+ports_alloc_fail:
+ kfree(hdev);
+
+ return rc;
+}
+
+static void hdev_fini(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_en_device *hdev = aux_dev->priv;
+
+ kfree(hdev->ports);
+ kfree(hdev);
+ aux_dev->priv = NULL;
+}
+
+static const struct auxiliary_device_id hbl_en_id_table[] = {
+ { .name = "habanalabs_cn.en", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(auxiliary, hbl_en_id_table);
+
+static int hbl_en_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
+{
+ struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
+ struct hbl_en_aux_ops *aux_ops = aux_dev->aux_ops;
+ struct hbl_en_device *hdev;
+ ktime_t timeout;
+ int rc;
+
+ rc = hdev_init(aux_dev);
+ if (rc) {
+ dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
+ return -EIO;
+ }
+
+ hdev = aux_dev->priv;
+
+ /* don't allow module unloading while it is attached */
+ if (!try_module_get(THIS_MODULE)) {
+ dev_err(hdev->dev, "Failed to increment %s module refcount\n", HBL_EN_NAME);
+ rc = -EIO;
+ goto module_get_err;
+ }
+
+ timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
+ while (1) {
+ aux_ops->hw_access_lock(aux_dev);
+
+ /* if the device is operational, proceed to actual init while holding the lock in
+ * order to prevent concurrent hard reset
+ */
+ if (aux_ops->device_operational(aux_dev))
+ break;
+
+ aux_ops->hw_access_unlock(aux_dev);
+
+ if (ktime_compare(ktime_get(), timeout) > 0) {
+ dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
+ rc = -EBUSY;
+ goto timeout_err;
+ }
+
+ dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing en\n");
+
+ msleep_interruptible(MSEC_PER_SEC);
+ }
+
+ rc = hbl_en_dev_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init en device\n");
+ goto dev_init_err;
+ }
+
+ aux_ops->hw_access_unlock(aux_dev);
+
+ return 0;
+
+dev_init_err:
+ aux_ops->hw_access_unlock(aux_dev);
+timeout_err:
+ module_put(THIS_MODULE);
+module_get_err:
+ hdev_fini(aux_dev);
+
+ return rc;
+}
+
+/* This function can be called only from the CN driver when deleting the aux bus, because we
+ * incremented the module refcount on probing. Hence no need to protect here from hard reset.
+ */
+static void hbl_en_remove(struct auxiliary_device *adev)
+{
+ struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
+ struct hbl_en_device *hdev = aux_dev->priv;
+
+ if (!hdev)
+ return;
+
+ hbl_en_dev_fini(hdev);
+
+ /* allow module unloading as now it is detached */
+ module_put(THIS_MODULE);
+
+ hdev_fini(aux_dev);
+}
+
+static struct auxiliary_driver hbl_en_driver = {
+ .name = "eth",
+ .probe = hbl_en_probe,
+ .remove = hbl_en_remove,
+ .id_table = hbl_en_id_table,
+};
+
+static int __init hbl_en_init(void)
+{
+ pr_info("loading driver\n");
+
+ return auxiliary_driver_register(&hbl_en_driver);
+}
+
+static void __exit hbl_en_exit(void)
+{
+ auxiliary_driver_unregister(&hbl_en_driver);
+
+ pr_info("driver removed\n");
+}
+
+module_init(hbl_en_init);
+module_exit(hbl_en_exit);
diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c
new file mode 100644
index 000000000000..1d14d283409b
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c
@@ -0,0 +1,452 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "hbl_en.h"
+#include <linux/ethtool.h>
+
+#define RX_COALESCED_FRAMES_MIN 1
+#define TX_COALESCED_FRAMES_MIN 1
+#define TX_COALESCED_FRAMES_MAX 10
+
+static const char pflags_str[][ETH_GSTRING_LEN] = {
+ "pcs-link-check",
+ "phy-auto-neg-lpbk",
+};
+
+#define NIC_STAT(m) {#m, offsetof(struct hbl_en_port, net_stats.m)}
+
+static struct hbl_cn_stat netdev_eth_stats[] = {
+ NIC_STAT(rx_packets),
+ NIC_STAT(tx_packets),
+ NIC_STAT(rx_bytes),
+ NIC_STAT(tx_bytes),
+ NIC_STAT(tx_errors),
+ NIC_STAT(rx_dropped),
+ NIC_STAT(tx_dropped)
+};
+
+static size_t pflags_str_len = ARRAY_SIZE(pflags_str);
+static size_t netdev_eth_stats_len = ARRAY_SIZE(netdev_eth_stats);
+
+static void hbl_en_ethtool_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *drvinfo)
+{
+ struct hbl_en_device *hdev;
+ struct hbl_en_port *port;
+
+ port = hbl_netdev_priv(ndev);
+ hdev = port->hdev;
+
+ strscpy(drvinfo->driver, HBL_EN_NAME, sizeof(drvinfo->driver));
+ strscpy(drvinfo->fw_version, hdev->fw_ver, sizeof(drvinfo->fw_version));
+ strscpy(drvinfo->bus_info, pci_name(hdev->pdev), sizeof(drvinfo->bus_info));
+}
+
+static int hbl_en_ethtool_get_module_info(struct net_device *ndev, struct ethtool_modinfo *modinfo)
+{
+ modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
+ modinfo->type = ETH_MODULE_SFF_8636;
+
+ return 0;
+}
+
+static int hbl_en_ethtool_get_module_eeprom(struct net_device *ndev, struct ethtool_eeprom *ee,
+ u8 *data)
+{
+ struct hbl_en_device *hdev;
+ struct hbl_en_port *port;
+ u32 first, last, len;
+ u8 *qsfp_eeprom;
+
+ port = hbl_netdev_priv(ndev);
+ hdev = port->hdev;
+ qsfp_eeprom = hdev->qsfp_eeprom;
+
+ if (ee->len == 0)
+ return -EINVAL;
+
+ first = ee->offset;
+ last = ee->offset + ee->len;
+
+ if (first < ETH_MODULE_SFF_8636_LEN) {
+ len = min_t(unsigned int, last, ETH_MODULE_SFF_8079_LEN);
+ len -= first;
+
+ memcpy(data, qsfp_eeprom + first, len);
+ }
+
+ return 0;
+}
+
+static u32 hbl_en_ethtool_get_priv_flags(struct net_device *ndev)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(ndev);
+
+ return port->pflags;
+}
+
+static int hbl_en_ethtool_set_priv_flags(struct net_device *ndev, u32 priv_flags)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(ndev);
+
+ port->pflags = priv_flags;
+
+ return 0;
+}
+
+static int hbl_en_ethtool_get_link_ksettings(struct net_device *ndev,
+ struct ethtool_link_ksettings *cmd)
+{
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_en_device *hdev;
+ struct hbl_en_port *port;
+ u32 port_idx, speed;
+
+ port = hbl_netdev_priv(ndev);
+ hdev = port->hdev;
+ port_idx = port->idx;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ speed = aux_ops->get_speed(aux_dev, port_idx);
+
+ cmd->base.speed = speed;
+ cmd->base.duplex = DUPLEX_FULL;
+
+ ethtool_link_ksettings_zero_link_mode(cmd, supported);
+ ethtool_link_ksettings_zero_link_mode(cmd, advertising);
+
+ switch (speed) {
+ case SPEED_100000:
+ ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseCR4_Full);
+ ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseSR4_Full);
+ ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseKR4_Full);
+ ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseLR4_ER4_Full);
+
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseCR4_Full);
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseSR4_Full);
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseKR4_Full);
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseLR4_ER4_Full);
+
+ cmd->base.port = PORT_FIBRE;
+
+ ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
+
+ ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, Backplane);
+ break;
+ case SPEED_50000:
+ ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseSR2_Full);
+ ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseCR2_Full);
+ ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseKR2_Full);
+
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseSR2_Full);
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseCR2_Full);
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseKR2_Full);
+ break;
+ case SPEED_25000:
+ ethtool_link_ksettings_add_link_mode(cmd, supported, 25000baseCR_Full);
+
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, 25000baseCR_Full);
+ break;
+ case SPEED_200000:
+ ethtool_link_ksettings_add_link_mode(cmd, supported, 200000baseCR4_Full);
+ ethtool_link_ksettings_add_link_mode(cmd, supported, 200000baseKR4_Full);
+
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, 200000baseCR4_Full);
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, 200000baseKR4_Full);
+ break;
+ case SPEED_400000:
+ ethtool_link_ksettings_add_link_mode(cmd, supported, 400000baseCR4_Full);
+ ethtool_link_ksettings_add_link_mode(cmd, supported, 400000baseKR4_Full);
+
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, 400000baseCR4_Full);
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, 400000baseKR4_Full);
+ break;
+ default:
+ netdev_err(port->ndev, "unknown speed %d\n", speed);
+ return -EFAULT;
+ }
+
+ ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
+
+ if (port->auto_neg_enable) {
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
+ cmd->base.autoneg = AUTONEG_ENABLE;
+ if (port->auto_neg_resolved)
+ ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
+ } else {
+ cmd->base.autoneg = AUTONEG_DISABLE;
+ }
+
+ ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
+
+ if (port->pfc_enable)
+ ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause);
+
+ return 0;
+}
+
+/* only autoneg is mutable */
+static bool check_immutable_ksettings(const struct ethtool_link_ksettings *old_cmd,
+ const struct ethtool_link_ksettings *new_cmd)
+{
+ return (old_cmd->base.speed == new_cmd->base.speed) &&
+ (old_cmd->base.duplex == new_cmd->base.duplex) &&
+ (old_cmd->base.port == new_cmd->base.port) &&
+ (old_cmd->base.phy_address == new_cmd->base.phy_address) &&
+ (old_cmd->base.eth_tp_mdix_ctrl == new_cmd->base.eth_tp_mdix_ctrl) &&
+ bitmap_equal(old_cmd->link_modes.advertising, new_cmd->link_modes.advertising,
+ __ETHTOOL_LINK_MODE_MASK_NBITS);
+}
+
+static int
+hbl_en_ethtool_set_link_ksettings(struct net_device *ndev, const struct ethtool_link_ksettings *cmd)
+{
+ struct ethtool_link_ksettings curr_cmd;
+ struct hbl_en_device *hdev;
+ struct hbl_en_port *port;
+ bool auto_neg;
+ u32 port_idx;
+ int rc;
+
+ port = hbl_netdev_priv(ndev);
+ hdev = port->hdev;
+ port_idx = port->idx;
+
+ memset(&curr_cmd, 0, sizeof(struct ethtool_link_ksettings));
+
+ rc = hbl_en_ethtool_get_link_ksettings(ndev, &curr_cmd);
+ if (rc)
+ return rc;
+
+ if (!check_immutable_ksettings(&curr_cmd, cmd))
+ return -EOPNOTSUPP;
+
+ auto_neg = cmd->base.autoneg == AUTONEG_ENABLE;
+
+ if (port->auto_neg_enable == auto_neg)
+ return 0;
+
+ if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
+ netdev_err(port->ndev, "port is in reset, can't update settings\n");
+ return -EBUSY;
+ }
+
+ if (auto_neg && !(hdev->auto_neg_mask & BIT(port_idx))) {
+ netdev_err(port->ndev, "port autoneg is disabled by BMC\n");
+ rc = -EFAULT;
+ goto out;
+ }
+
+ port->auto_neg_enable = auto_neg;
+
+ if (netif_running(port->ndev)) {
+ rc = hbl_en_port_reset(port);
+ if (rc)
+ netdev_err(port->ndev, "Failed to reset port for settings update, rc %d\n",
+ rc);
+ }
+
+out:
+ atomic_set(&port->in_reset, 0);
+
+ return rc;
+}
+
+static int hbl_en_ethtool_get_sset_count(struct net_device *ndev, int sset)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(ndev);
+ struct hbl_en_device *hdev = port->hdev;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ switch (sset) {
+ case ETH_SS_STATS:
+ return netdev_eth_stats_len + aux_ops->get_cnts_num(aux_dev, port_idx);
+ case ETH_SS_PRIV_FLAGS:
+ return pflags_str_len;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static void hbl_en_ethtool_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(ndev);
+ struct hbl_en_device *hdev = port->hdev;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+ int i;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ switch (stringset) {
+ case ETH_SS_STATS:
+ for (i = 0; i < netdev_eth_stats_len; i++)
+ ethtool_puts(&data, netdev_eth_stats[i].str);
+
+ aux_ops->get_cnts_names(aux_dev, port_idx, data);
+ break;
+ case ETH_SS_PRIV_FLAGS:
+ for (i = 0; i < pflags_str_len; i++)
+ ethtool_puts(&data, pflags_str[i]);
+ break;
+ }
+}
+
+static void hbl_en_ethtool_get_ethtool_stats(struct net_device *ndev,
+ __always_unused struct ethtool_stats *stats, u64 *data)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(ndev);
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_en_device *hdev;
+ u32 port_idx;
+ char *p;
+ int i;
+
+ hdev = port->hdev;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ port_idx = port->idx;
+
+ if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
+ dev_info_ratelimited(hdev->dev, "port %d is in reset, can't get ethtool stats",
+ port_idx);
+ return;
+ }
+
+ /* Even though the Ethernet Rx/Tx flow might update the stats in parallel, there is not an
+ * absolute need for synchronisation. This is because, missing few counts of these stats is
+ * much better than adding a lock to synchronize and increase the overhead of the Rx/Tx
+ * flows. In worst case scenario, reader will get stale stats. He will receive updated
+ * stats in next read.
+ */
+ for (i = 0; i < netdev_eth_stats_len; i++) {
+ p = (char *)port + netdev_eth_stats[i].lo_offset;
+ data[i] = *(u32 *)p;
+ }
+
+ data += i;
+
+ aux_ops->get_cnts_values(aux_dev, port_idx, data);
+
+ atomic_set(&port->in_reset, 0);
+}
+
+static int hbl_en_ethtool_get_coalesce(struct net_device *ndev,
+ struct ethtool_coalesce *coal,
+ struct kernel_ethtool_coalesce *kernel_coal,
+ struct netlink_ext_ack *extack)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(ndev);
+ struct hbl_en_device *hdev = port->hdev;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ aux_ops->ctrl_lock(aux_dev, port_idx);
+
+ coal->tx_max_coalesced_frames = port->tx_max_coalesced_frames;
+ coal->rx_coalesce_usecs = port->rx_coalesce_usecs;
+ coal->rx_max_coalesced_frames = port->rx_max_coalesced_frames;
+
+ aux_ops->ctrl_unlock(aux_dev, port_idx);
+
+ return 0;
+}
+
+static int hbl_en_ethtool_set_coalesce(struct net_device *ndev,
+ struct ethtool_coalesce *coal,
+ struct kernel_ethtool_coalesce *kernel_coal,
+ struct netlink_ext_ack *extack)
+{
+ struct hbl_en_port *port = hbl_netdev_priv(ndev);
+ struct hbl_en_device *hdev = port->hdev;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+ int rc, rx_ring_size;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
+ netdev_err(port->ndev, "port is in reset, can't update settings\n");
+ return -EBUSY;
+ }
+
+ if (coal->tx_max_coalesced_frames < TX_COALESCED_FRAMES_MIN ||
+ coal->tx_max_coalesced_frames > TX_COALESCED_FRAMES_MAX) {
+ netdev_err(ndev, "tx max_coalesced_frames should be between %d and %d\n",
+ TX_COALESCED_FRAMES_MIN, TX_COALESCED_FRAMES_MAX);
+ rc = -EINVAL;
+ goto atomic_out;
+ }
+
+ rx_ring_size = hdev->asic_funcs.get_rx_ring_size(port);
+ if (coal->rx_max_coalesced_frames < RX_COALESCED_FRAMES_MIN ||
+ coal->rx_max_coalesced_frames >= rx_ring_size) {
+ netdev_err(ndev, "rx max_coalesced_frames should be between %d and %d\n",
+ RX_COALESCED_FRAMES_MIN, rx_ring_size);
+ rc = -EINVAL;
+ goto atomic_out;
+ }
+
+ aux_ops->ctrl_lock(aux_dev, port_idx);
+
+ port->tx_max_coalesced_frames = coal->tx_max_coalesced_frames;
+ port->rx_coalesce_usecs = coal->rx_coalesce_usecs;
+ port->rx_max_coalesced_frames = coal->rx_max_coalesced_frames;
+
+ rc = hdev->asic_funcs.set_coalesce(port);
+
+ aux_ops->ctrl_unlock(aux_dev, port_idx);
+
+atomic_out:
+ atomic_set(&port->in_reset, 0);
+ return rc;
+}
+
+void hbl_en_ethtool_init_coalesce(struct hbl_en_port *port)
+{
+ port->rx_coalesce_usecs = CQ_ARM_TIMEOUT_USEC;
+ port->rx_max_coalesced_frames = 1;
+ port->tx_max_coalesced_frames = 1;
+}
+
+static const struct ethtool_ops hbl_en_ethtool_ops_coalesce = {
+ .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | ETHTOOL_COALESCE_RX_MAX_FRAMES |
+ ETHTOOL_COALESCE_TX_MAX_FRAMES,
+ .get_drvinfo = hbl_en_ethtool_get_drvinfo,
+ .get_link = ethtool_op_get_link,
+ .get_module_info = hbl_en_ethtool_get_module_info,
+ .get_module_eeprom = hbl_en_ethtool_get_module_eeprom,
+ .get_priv_flags = hbl_en_ethtool_get_priv_flags,
+ .set_priv_flags = hbl_en_ethtool_set_priv_flags,
+ .get_link_ksettings = hbl_en_ethtool_get_link_ksettings,
+ .set_link_ksettings = hbl_en_ethtool_set_link_ksettings,
+ .get_sset_count = hbl_en_ethtool_get_sset_count,
+ .get_strings = hbl_en_ethtool_get_strings,
+ .get_ethtool_stats = hbl_en_ethtool_get_ethtool_stats,
+ .get_coalesce = hbl_en_ethtool_get_coalesce,
+ .set_coalesce = hbl_en_ethtool_set_coalesce,
+};
+
+const struct ethtool_ops *hbl_en_ethtool_get_ops(struct net_device *ndev)
+{
+ return &hbl_en_ethtool_ops_coalesce;
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-13 8:22 ` [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver Omer Shpigelman
@ 2024-06-13 21:49 ` Andrew Lunn
2024-06-18 6:58 ` Omer Shpigelman
2024-06-14 22:48 ` Joe Damato
` (4 subsequent siblings)
5 siblings, 1 reply; 108+ messages in thread
From: Andrew Lunn @ 2024-06-13 21:49 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel, linux-rdma, netdev, dri-devel, ogabbay, zyehudai
> +static int hbl_en_napi_poll(struct napi_struct *napi, int budget);
> +static int hbl_en_port_open(struct hbl_en_port *port);
When you do the Intel internal review, i expect this is crop up. No
forward declarations please. Put the code in the right order so they
are not needed.
> +static int hbl_en_get_src_ip(struct hbl_aux_dev *aux_dev, u32 port_idx, u32 *src_ip)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> + struct net_device *ndev = port->ndev;
> + struct in_device *in_dev;
> + struct in_ifaddr *ifa;
> + int rc = 0;
> +
> + /* for the case where no src IP is configured */
> + *src_ip = 0;
> +
> + /* rtnl lock should be acquired in relevant flows before taking configuration lock */
> + if (!rtnl_is_locked()) {
> + netdev_err(port->ndev, "Rtnl lock is not acquired, can't proceed\n");
> + rc = -EFAULT;
> + goto out;
> + }
You will find all other drivers just do:
ASSERT_RTNL().
If your locking is broken, you are probably dead anyway, so you might
as well keep going and try to explode in the most interesting way
possible.
> +static void hbl_en_reset_stats(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + port->net_stats.rx_packets = 0;
> + port->net_stats.tx_packets = 0;
> + port->net_stats.rx_bytes = 0;
> + port->net_stats.tx_bytes = 0;
> + port->net_stats.tx_errors = 0;
> + atomic64_set(&port->net_stats.rx_dropped, 0);
> + atomic64_set(&port->net_stats.tx_dropped, 0);
Why atomic64_set? Atomics are expensive, so you should not be using
them. netdev has other cheaper methods, which other Intel developers
should be happy to tell you all about.
> +static u32 hbl_en_get_mtu(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> + struct net_device *ndev = port->ndev;
> + u32 mtu;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(ndev, "port is in reset, can't get MTU\n");
> + return 0;
> + }
> +
> + mtu = ndev->mtu;
I think you need a better error message. All this does is access
ndev->mtu. What does it matter if the port is in reset? You don't
access it.
> +static int hbl_en_close(struct net_device *netdev)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + struct hbl_en_device *hdev = port->hdev;
> + ktime_t timeout;
> +
> + /* Looks like the return value of this function is not checked, so we can't just return
> + * EBUSY if the port is under reset. We need to wait until the reset is finished and then
> + * close the port. Otherwise the netdev will set the port as closed although port_close()
> + * wasn't called. Only if we waited long enough and the reset hasn't finished, we can return
> + * an error without actually closing the port as it is a fatal flow anyway.
> + */
> + timeout = ktime_add_ms(ktime_get(), PORT_RESET_TIMEOUT_MSEC);
> + while (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + /* If this is called from unregister_netdev() then the port was already closed and
> + * hence we can safely return.
> + * We could have just check the port_open boolean, but that might hide some future
> + * bugs. Hence it is better to use a dedicated flag for that.
> + */
> + if (READ_ONCE(hdev->in_teardown))
> + return 0;
> +
> + usleep_range(50, 200);
> + if (ktime_compare(ktime_get(), timeout) > 0) {
> + netdev_crit(netdev,
> + "Timeout while waiting for port to finish reset, can't close it\n"
> + );
> + return -EBUSY;
> + }
This has the usual bug. Please look at include/linux/iopoll.h.
> + timeout = ktime_add_ms(ktime_get(), PORT_RESET_TIMEOUT_MSEC);
> + while (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + usleep_range(50, 200);
> + if (ktime_compare(ktime_get(), timeout) > 0) {
> + netdev_crit(port->ndev,
> + "Timeout while waiting for port %d to finish reset\n",
> + port->idx);
> + break;
> + }
> + }
and again. Don't roll your own timeout loops like this, use the core
version.
> +static int hbl_en_change_mtu(struct net_device *netdev, int new_mtu)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + int rc = 0;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(netdev, "port is in reset, can't change MTU\n");
> + return -EBUSY;
> + }
> +
> + if (netif_running(port->ndev)) {
> + hbl_en_port_close(port);
> +
> + /* Sleep in order to let obsolete events to be dropped before re-opening the port */
> + msleep(20);
> +
> + netdev->mtu = new_mtu;
> +
> + rc = hbl_en_port_open(port);
> + if (rc)
> + netdev_err(netdev, "Failed to reinit port for MTU change, rc %d\n", rc);
Does that mean the port is FUBAR?
Most operations like this are expected to roll back to the previous
working configuration on failure. So if changing the MTU requires new
buffers in your ring, you should first allocate the new buffers, then
free the old buffers, so that if allocation fails, you still have
buffers, and the device can continue operating.
> +module_param(poll_enable, bool, 0444);
> +MODULE_PARM_DESC(poll_enable,
> + "Enable Rx polling rather than IRQ + NAPI (0 = no, 1 = yes, default: no)");
Module parameters are not liked. This probably needs to go away.
> +static int hbl_en_ethtool_get_module_info(struct net_device *ndev, struct ethtool_modinfo *modinfo)
> +{
> + modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
> + modinfo->type = ETH_MODULE_SFF_8636;
Is this an SFF, not an SFP? How else can you know what module it is
without doing an I2C transfer to ask the module what it is?
> +static int hbl_en_ethtool_get_module_eeprom(struct net_device *ndev, struct ethtool_eeprom *ee,
> + u8 *data)
> +{
This is the old API. Please update to the new API so there is access
to all the pages of the SFF/SFP.
> +static int hbl_en_ethtool_get_link_ksettings(struct net_device *ndev,
> + struct ethtool_link_ksettings *cmd)
> +{
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + struct hbl_en_device *hdev;
> + struct hbl_en_port *port;
> + u32 port_idx, speed;
> +
> + port = hbl_netdev_priv(ndev);
> + hdev = port->hdev;
> + port_idx = port->idx;
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> + speed = aux_ops->get_speed(aux_dev, port_idx);
> +
> + cmd->base.speed = speed;
> + cmd->base.duplex = DUPLEX_FULL;
> +
> + ethtool_link_ksettings_zero_link_mode(cmd, supported);
> + ethtool_link_ksettings_zero_link_mode(cmd, advertising);
> +
> + switch (speed) {
> + case SPEED_100000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseSR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseKR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseLR4_ER4_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseSR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseKR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseLR4_ER4_Full);
> +
> + cmd->base.port = PORT_FIBRE;
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Backplane);
> + break;
> + case SPEED_50000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseSR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseCR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseKR2_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseSR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseCR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseKR2_Full);
> + break;
> + case SPEED_25000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 25000baseCR_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 25000baseCR_Full);
> + break;
> + case SPEED_200000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 200000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 200000baseKR4_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 200000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 200000baseKR4_Full);
> + break;
> + case SPEED_400000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 400000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 400000baseKR4_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 400000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 400000baseKR4_Full);
> + break;
> + default:
> + netdev_err(port->ndev, "unknown speed %d\n", speed);
> + return -EFAULT;
> + }
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
> +
> + if (port->auto_neg_enable) {
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
> + cmd->base.autoneg = AUTONEG_ENABLE;
> + if (port->auto_neg_resolved)
> + ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
That looks odd. Care to explain?
> + } else {
> + cmd->base.autoneg = AUTONEG_DISABLE;
> + }
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
> +
> + if (port->pfc_enable)
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause);
And is suspect that is wrong. Everybody gets pause wrong. Please
double check my previous posts about pause.
> + if (auto_neg && !(hdev->auto_neg_mask & BIT(port_idx))) {
> + netdev_err(port->ndev, "port autoneg is disabled by BMC\n");
> + rc = -EFAULT;
> + goto out;
Don't say you support autoneg in supported if that is the case.
And EFAULT is about memory problems. EINVAL, maybe EPERM? or
EOPNOTSUPP.
Andrew
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-13 21:49 ` Andrew Lunn
@ 2024-06-18 6:58 ` Omer Shpigelman
2024-06-18 14:19 ` Andrew Lunn
0 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-18 6:58 UTC (permalink / raw)
To: Andrew Lunn
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/14/24 00:49, Andrew Lunn wrote:
> [Some people who received this message don't often get email from andrew@lunn.ch. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
>> +static int hbl_en_napi_poll(struct napi_struct *napi, int budget);
>> +static int hbl_en_port_open(struct hbl_en_port *port);
>
> When you do the Intel internal review, i expect this is crop up. No
> forward declarations please. Put the code in the right order so they
> are not needed.
>
I'll try to get rid of these forward declarations by re-odering the functions.
>> +static int hbl_en_get_src_ip(struct hbl_aux_dev *aux_dev, u32 port_idx, u32 *src_ip)
>> +{
>> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
>> + struct net_device *ndev = port->ndev;
>> + struct in_device *in_dev;
>> + struct in_ifaddr *ifa;
>> + int rc = 0;
>> +
>> + /* for the case where no src IP is configured */
>> + *src_ip = 0;
>> +
>> + /* rtnl lock should be acquired in relevant flows before taking configuration lock */
>> + if (!rtnl_is_locked()) {
>> + netdev_err(port->ndev, "Rtnl lock is not acquired, can't proceed\n");
>> + rc = -EFAULT;
>> + goto out;
>> + }
>
> You will find all other drivers just do:
>
> ASSERT_RTNL().
>
> If your locking is broken, you are probably dead anyway, so you might
> as well keep going and try to explode in the most interesting way
> possible.
>
Thanks, I'll switch to ASSERT_RTNL().
>> +static void hbl_en_reset_stats(struct hbl_aux_dev *aux_dev, u32 port_idx)
>> +{
>> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
>> +
>> + port->net_stats.rx_packets = 0;
>> + port->net_stats.tx_packets = 0;
>> + port->net_stats.rx_bytes = 0;
>> + port->net_stats.tx_bytes = 0;
>> + port->net_stats.tx_errors = 0;
>> + atomic64_set(&port->net_stats.rx_dropped, 0);
>> + atomic64_set(&port->net_stats.tx_dropped, 0);
>
> Why atomic64_set? Atomics are expensive, so you should not be using
> them. netdev has other cheaper methods, which other Intel developers
> should be happy to tell you all about.
>
We used atomic64_set as these counters are updated also from non-netdev
flow in case of HW errors.
I can switch to use u64_stats_sync is that's the intention.
I'm about to start a review process with Intel developers regardless of
this issue and I'll bring this up too.
>> +static u32 hbl_en_get_mtu(struct hbl_aux_dev *aux_dev, u32 port_idx)
>> +{
>> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
>> + struct net_device *ndev = port->ndev;
>> + u32 mtu;
>> +
>> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
>> + netdev_err(ndev, "port is in reset, can't get MTU\n");
>> + return 0;
>> + }
>> +
>> + mtu = ndev->mtu;
>
> I think you need a better error message. All this does is access
> ndev->mtu. What does it matter if the port is in reset? You don't
> access it.
>
This function is called from the CN driver to get the current MTU in order
to configure it to the HW, for exmaple when configuring an IB QP. The MTU
value might be changed by user while we execute this function. Such an MTU
change requires port reset.
Hence, if the port is under reset we cannot be sure what is the MTU value.
Since the user should not change the MTU while QPs are being configured
(but we cannot block this flow either), we report an error because the MTU
value cannot be retrieved.
The other option to read the MTU value without checking for an in-progress
reset flow but in that case the MTU value might be incorrect.
>> +static int hbl_en_close(struct net_device *netdev)
>> +{
>> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
>> + struct hbl_en_device *hdev = port->hdev;
>> + ktime_t timeout;
>> +
>> + /* Looks like the return value of this function is not checked, so we can't just return
>> + * EBUSY if the port is under reset. We need to wait until the reset is finished and then
>> + * close the port. Otherwise the netdev will set the port as closed although port_close()
>> + * wasn't called. Only if we waited long enough and the reset hasn't finished, we can return
>> + * an error without actually closing the port as it is a fatal flow anyway.
>> + */
>> + timeout = ktime_add_ms(ktime_get(), PORT_RESET_TIMEOUT_MSEC);
>> + while (atomic_cmpxchg(&port->in_reset, 0, 1)) {
>> + /* If this is called from unregister_netdev() then the port was already closed and
>> + * hence we can safely return.
>> + * We could have just check the port_open boolean, but that might hide some future
>> + * bugs. Hence it is better to use a dedicated flag for that.
>> + */
>> + if (READ_ONCE(hdev->in_teardown))
>> + return 0;
>> +
>> + usleep_range(50, 200);
>> + if (ktime_compare(ktime_get(), timeout) > 0) {
>> + netdev_crit(netdev,
>> + "Timeout while waiting for port to finish reset, can't close it\n"
>> + );
>> + return -EBUSY;
>> + }
>
> This has the usual bug. Please look at include/linux/iopoll.h.
>
I'll take a look, thanks.
>> + timeout = ktime_add_ms(ktime_get(), PORT_RESET_TIMEOUT_MSEC);
>> + while (atomic_cmpxchg(&port->in_reset, 0, 1)) {
>> + usleep_range(50, 200);
>> + if (ktime_compare(ktime_get(), timeout) > 0) {
>> + netdev_crit(port->ndev,
>> + "Timeout while waiting for port %d to finish reset\n",
>> + port->idx);
>> + break;
>> + }
>> + }
>
> and again. Don't roll your own timeout loops like this, use the core
> version.
>
I will look for some core alternative.
>> +static int hbl_en_change_mtu(struct net_device *netdev, int new_mtu)
>> +{
>> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
>> + int rc = 0;
>> +
>> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
>> + netdev_err(netdev, "port is in reset, can't change MTU\n");
>> + return -EBUSY;
>> + }
>> +
>> + if (netif_running(port->ndev)) {
>> + hbl_en_port_close(port);
>> +
>> + /* Sleep in order to let obsolete events to be dropped before re-opening the port */
>> + msleep(20);
>> +
>> + netdev->mtu = new_mtu;
>> +
>> + rc = hbl_en_port_open(port);
>> + if (rc)
>> + netdev_err(netdev, "Failed to reinit port for MTU change, rc %d\n", rc);
>
> Does that mean the port is FUBAR?
>
> Most operations like this are expected to roll back to the previous
> working configuration on failure. So if changing the MTU requires new
> buffers in your ring, you should first allocate the new buffers, then
> free the old buffers, so that if allocation fails, you still have
> buffers, and the device can continue operating.
>
A failure in opening a port is a fatal error. It shouldn't happen. This is
not something we wish to recover from.
This kind of an error indicates a severe system error that will usually
require a driver removal and reload anyway.
>> +module_param(poll_enable, bool, 0444);
>> +MODULE_PARM_DESC(poll_enable,
>> + "Enable Rx polling rather than IRQ + NAPI (0 = no, 1 = yes, default: no)");
>
> Module parameters are not liked. This probably needs to go away.
>
I see that various vendors under net/ethernet/* use module parameters.
Can't we add another one?
>> +static int hbl_en_ethtool_get_module_info(struct net_device *ndev, struct ethtool_modinfo *modinfo)
>> +{
>> + modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
>> + modinfo->type = ETH_MODULE_SFF_8636;
>
> Is this an SFF, not an SFP? How else can you know what module it is
> without doing an I2C transfer to ask the module what it is?
>
The current type is SFF and it is unlikely to be changed.
>> +static int hbl_en_ethtool_get_module_eeprom(struct net_device *ndev, struct ethtool_eeprom *ee,
>> + u8 *data)
>> +{
>
> This is the old API. Please update to the new API so there is access
> to all the pages of the SFF/SFP.
>
Are you referring to get_module_eeprom_by_page()? if so, then it is not
supported by our FW, we read the entire data on device load.
However, I can hide that behind the new API and return only the
requested page if that's the intention.
>> +static int hbl_en_ethtool_get_link_ksettings(struct net_device *ndev,
>> + struct ethtool_link_ksettings *cmd)
>> +{
>> + struct hbl_en_aux_ops *aux_ops;
>> + struct hbl_aux_dev *aux_dev;
>> + struct hbl_en_device *hdev;
>> + struct hbl_en_port *port;
>> + u32 port_idx, speed;
>> +
>> + port = hbl_netdev_priv(ndev);
>> + hdev = port->hdev;
>> + port_idx = port->idx;
>> + aux_dev = hdev->aux_dev;
>> + aux_ops = aux_dev->aux_ops;
>> + speed = aux_ops->get_speed(aux_dev, port_idx);
>> +
>> + cmd->base.speed = speed;
>> + cmd->base.duplex = DUPLEX_FULL;
>> +
>> + ethtool_link_ksettings_zero_link_mode(cmd, supported);
>> + ethtool_link_ksettings_zero_link_mode(cmd, advertising);
>> +
>> + switch (speed) {
>> + case SPEED_100000:
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseCR4_Full);
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseSR4_Full);
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseKR4_Full);
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseLR4_ER4_Full);
>> +
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseCR4_Full);
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseSR4_Full);
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseKR4_Full);
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseLR4_ER4_Full);
>> +
>> + cmd->base.port = PORT_FIBRE;
>> +
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
>> +
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Backplane);
>> + break;
>> + case SPEED_50000:
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseSR2_Full);
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseCR2_Full);
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseKR2_Full);
>> +
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseSR2_Full);
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseCR2_Full);
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseKR2_Full);
>> + break;
>> + case SPEED_25000:
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, 25000baseCR_Full);
>> +
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 25000baseCR_Full);
>> + break;
>> + case SPEED_200000:
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, 200000baseCR4_Full);
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, 200000baseKR4_Full);
>> +
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 200000baseCR4_Full);
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 200000baseKR4_Full);
>> + break;
>> + case SPEED_400000:
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, 400000baseCR4_Full);
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, 400000baseKR4_Full);
>> +
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 400000baseCR4_Full);
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 400000baseKR4_Full);
>> + break;
>> + default:
>> + netdev_err(port->ndev, "unknown speed %d\n", speed);
>> + return -EFAULT;
>> + }
>> +
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
>> +
>> + if (port->auto_neg_enable) {
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
>> + cmd->base.autoneg = AUTONEG_ENABLE;
>> + if (port->auto_neg_resolved)
>> + ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
>
> That looks odd. Care to explain?
>
The HW of all of our ports supports autoneg.
But in addition, the ports are divided to two groups:
internal: ports which are connected to other Gaudi2 ports in the same server.
external: ports which are connected to an external switch.
Only internal ports use autoneg.
The ports mask which sets each port as internal/external is fetched from
the FW on device load.
>> + } else {
>> + cmd->base.autoneg = AUTONEG_DISABLE;
>> + }
>> +
>> + ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
>> +
>> + if (port->pfc_enable)
>> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause);
>
> And is suspect that is wrong. Everybody gets pause wrong. Please
> double check my previous posts about pause.
>
Our HW supports Pause frames.
But, PFC can be disabled via lldptool for exmaple, so we won't advertise
it.
I'll try to find more info about it, but can you please share what's wrong
with the curent code?
BTW I will change it to Asym_Pause as we support Tx pause frames as well.
>> + if (auto_neg && !(hdev->auto_neg_mask & BIT(port_idx))) {
>> + netdev_err(port->ndev, "port autoneg is disabled by BMC\n");
>> + rc = -EFAULT;
>> + goto out;
>
> Don't say you support autoneg in supported if that is the case.
>
> And EFAULT is about memory problems. EINVAL, maybe EPERM? or
> EOPNOTSUPP.
>
> Andrew
Yeah, should be switched to EPERM/EOPNOTSUPP.
Regarding the support of autoneg - the HW supports autoneg but it might be
disabled by the FW. Hence we might not be able to switch it on.
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-18 6:58 ` Omer Shpigelman
@ 2024-06-18 14:19 ` Andrew Lunn
2024-06-19 7:16 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Andrew Lunn @ 2024-06-18 14:19 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
> >> +static u32 hbl_en_get_mtu(struct hbl_aux_dev *aux_dev, u32 port_idx)
> >> +{
> >> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> >> + struct net_device *ndev = port->ndev;
> >> + u32 mtu;
> >> +
> >> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> >> + netdev_err(ndev, "port is in reset, can't get MTU\n");
> >> + return 0;
> >> + }
> >> +
> >> + mtu = ndev->mtu;
> >
> > I think you need a better error message. All this does is access
> > ndev->mtu. What does it matter if the port is in reset? You don't
> > access it.
> >
>
> This function is called from the CN driver to get the current MTU in order
> to configure it to the HW, for exmaple when configuring an IB QP. The MTU
> value might be changed by user while we execute this function.
Change of MTU will happen while holding RTNL. Why not simply hold RTNL
while programming the hardware? That is the normal pattern for MAC
drivers.
> >> +static int hbl_en_change_mtu(struct net_device *netdev, int new_mtu)
> >> +{
> >> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> >> + int rc = 0;
> >> +
> >> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> >> + netdev_err(netdev, "port is in reset, can't change MTU\n");
> >> + return -EBUSY;
> >> + }
> >> +
> >> + if (netif_running(port->ndev)) {
> >> + hbl_en_port_close(port);
> >> +
> >> + /* Sleep in order to let obsolete events to be dropped before re-opening the port */
> >> + msleep(20);
> >> +
> >> + netdev->mtu = new_mtu;
> >> +
> >> + rc = hbl_en_port_open(port);
> >> + if (rc)
> >> + netdev_err(netdev, "Failed to reinit port for MTU change, rc %d\n", rc);
> >
> > Does that mean the port is FUBAR?
> >
> > Most operations like this are expected to roll back to the previous
> > working configuration on failure. So if changing the MTU requires new
> > buffers in your ring, you should first allocate the new buffers, then
> > free the old buffers, so that if allocation fails, you still have
> > buffers, and the device can continue operating.
> >
>
> A failure in opening a port is a fatal error. It shouldn't happen. This is
> not something we wish to recover from.
What could cause open to fail? Is memory allocated?
> This kind of an error indicates a severe system error that will usually
> require a driver removal and reload anyway.
>
> >> +module_param(poll_enable, bool, 0444);
> >> +MODULE_PARM_DESC(poll_enable,
> >> + "Enable Rx polling rather than IRQ + NAPI (0 = no, 1 = yes, default: no)");
> >
> > Module parameters are not liked. This probably needs to go away.
> >
>
> I see that various vendors under net/ethernet/* use module parameters.
> Can't we add another one?
Look at the history of those module parameters. Do you see many added
in the last year? 5 years?
> >> +static int hbl_en_ethtool_get_module_info(struct net_device *ndev, struct ethtool_modinfo *modinfo)
> >> +{
> >> + modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
> >> + modinfo->type = ETH_MODULE_SFF_8636;
> >
> > Is this an SFF, not an SFP? How else can you know what module it is
> > without doing an I2C transfer to ask the module what it is?
> >
>
> The current type is SFF and it is unlikely to be changed.
Well, SFF are soldered to the board, so yes, it is unlikely to
change...
Please add a comment that this is an SFF, not an SFP, so is soldered
to the board, and so it is known to be an 8636 compatible device.
> Are you referring to get_module_eeprom_by_page()? if so, then it is not
> supported by our FW, we read the entire data on device load.
> However, I can hide that behind the new API and return only the
> requested page if that's the intention.
Well, if your firmware is so limited, then you might as well stick to
the old API, and let the core do the conversion to the legacy
code. But i'm surprised you don't allow access to the temperature
sensors, received signal strength, voltages etc, which could be
exported via HWMON.
> >> + ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
> >
> > That looks odd. Care to explain?
> >
>
> The HW of all of our ports supports autoneg.
> But in addition, the ports are divided to two groups:
> internal: ports which are connected to other Gaudi2 ports in the same server.
> external: ports which are connected to an external switch.
> Only internal ports use autoneg.
> The ports mask which sets each port as internal/external is fetched from
> the FW on device load.
That is not what i meant. lc_advertising should indicate the link
modes the peer is advertising. If this was a copper link, it typically
would contain 10BaseT-Half, 10BaseT-Full, 100BaseT-Half,
100BaseT-Full, 1000BaseT-Half. Setting the Autoneg bit is pointless,
since the peer must be advertising in order that lp_advertising has a
value!
> Our HW supports Pause frames.
> But, PFC can be disabled via lldptool for exmaple, so we won't advertise
> it.
Please also implement the standard netdev way of configuring pause.
When you do that, you should start to understand how pause can be
negotiated, or forced. That is what most get wrong.
> I'll try to find more info about it, but can you please share what's wrong
> with the curent code?
> BTW I will change it to Asym_Pause as we support Tx pause frames as well.
>
> >> + if (auto_neg && !(hdev->auto_neg_mask & BIT(port_idx))) {
> >> + netdev_err(port->ndev, "port autoneg is disabled by BMC\n");
> >> + rc = -EFAULT;
> >> + goto out;
> >
> > Don't say you support autoneg in supported if that is the case.
> >
> > And EFAULT is about memory problems. EINVAL, maybe EPERM? or
> > EOPNOTSUPP.
> >
> > Andrew
>
> Yeah, should be switched to EPERM/EOPNOTSUPP.
> Regarding the support of autoneg - the HW supports autoneg but it might be
> disabled by the FW. Hence we might not be able to switch it on.
No problem, ask the firmware what it is doing, and return the reality
in ksetting. Only say you support autoneg if your firmware allows you
to perform autoneg.
Andrew
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-18 14:19 ` Andrew Lunn
@ 2024-06-19 7:16 ` Omer Shpigelman
2024-06-19 8:01 ` Przemek Kitszel
` (2 more replies)
0 siblings, 3 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-19 7:16 UTC (permalink / raw)
To: Andrew Lunn
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/18/24 17:19, Andrew Lunn wrote:
>>>> +static u32 hbl_en_get_mtu(struct hbl_aux_dev *aux_dev, u32 port_idx)
>>>> +{
>>>> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
>>>> + struct net_device *ndev = port->ndev;
>>>> + u32 mtu;
>>>> +
>>>> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
>>>> + netdev_err(ndev, "port is in reset, can't get MTU\n");
>>>> + return 0;
>>>> + }
>>>> +
>>>> + mtu = ndev->mtu;
>>>
>>> I think you need a better error message. All this does is access
>>> ndev->mtu. What does it matter if the port is in reset? You don't
>>> access it.
>>>
>>
>> This function is called from the CN driver to get the current MTU in order
>> to configure it to the HW, for exmaple when configuring an IB QP. The MTU
>> value might be changed by user while we execute this function.
>
> Change of MTU will happen while holding RTNL. Why not simply hold RTNL
> while programming the hardware? That is the normal pattern for MAC
> drivers.
>
I can hold the RTNL lock while configuring the HW but it seems like a big
overhead. Configuring the HW might take some time due to QP draining or
cache invalidation.
To me it seems unnecessary but if that's the common way then I'll change
it.
>>>> +static int hbl_en_change_mtu(struct net_device *netdev, int new_mtu)
>>>> +{
>>>> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
>>>> + int rc = 0;
>>>> +
>>>> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
>>>> + netdev_err(netdev, "port is in reset, can't change MTU\n");
>>>> + return -EBUSY;
>>>> + }
>>>> +
>>>> + if (netif_running(port->ndev)) {
>>>> + hbl_en_port_close(port);
>>>> +
>>>> + /* Sleep in order to let obsolete events to be dropped before re-opening the port */
>>>> + msleep(20);
>>>> +
>>>> + netdev->mtu = new_mtu;
>>>> +
>>>> + rc = hbl_en_port_open(port);
>>>> + if (rc)
>>>> + netdev_err(netdev, "Failed to reinit port for MTU change, rc %d\n", rc);
>>>
>>> Does that mean the port is FUBAR?
>>>
>>> Most operations like this are expected to roll back to the previous
>>> working configuration on failure. So if changing the MTU requires new
>>> buffers in your ring, you should first allocate the new buffers, then
>>> free the old buffers, so that if allocation fails, you still have
>>> buffers, and the device can continue operating.
>>>
>>
>> A failure in opening a port is a fatal error. It shouldn't happen. This is
>> not something we wish to recover from.
>
> What could cause open to fail? Is memory allocated?
>
Memory is allocated but it is freed in case of a failure.
Port opening can fail due to other reasons as well like some HW timeout
while configuring the ETH QP.
>> This kind of an error indicates a severe system error that will usually
>> require a driver removal and reload anyway.
>>
>>>> +module_param(poll_enable, bool, 0444);
>>>> +MODULE_PARM_DESC(poll_enable,
>>>> + "Enable Rx polling rather than IRQ + NAPI (0 = no, 1 = yes, default: no)");
>>>
>>> Module parameters are not liked. This probably needs to go away.
>>>
>>
>> I see that various vendors under net/ethernet/* use module parameters.
>> Can't we add another one?
>
> Look at the history of those module parameters. Do you see many added
> in the last year? 5 years?
>
I didn't check that prior to my submit. Regarding this "no new module
parameters allowed" rule, is that documented anywhere? if not, is that the
common practice? not to try to do something that was not done recently?
how "recently" is defined?
I just want to clarify this because it's hard to handle these submissions
when we write some code based on existing examples but then we are
rejected because "we don't do that here anymore".
I want to avoid future cases of this mismatch.
>>>> +static int hbl_en_ethtool_get_module_info(struct net_device *ndev, struct ethtool_modinfo *modinfo)
>>>> +{
>>>> + modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
>>>> + modinfo->type = ETH_MODULE_SFF_8636;
>>>
>>> Is this an SFF, not an SFP? How else can you know what module it is
>>> without doing an I2C transfer to ask the module what it is?
>>>
>>
>> The current type is SFF and it is unlikely to be changed.
>
> Well, SFF are soldered to the board, so yes, it is unlikely to
> change...
>
> Please add a comment that this is an SFF, not an SFP, so is soldered
> to the board, and so it is known to be an 8636 compatible device.
>
I'll add.
>> Are you referring to get_module_eeprom_by_page()? if so, then it is not
>> supported by our FW, we read the entire data on device load.
>> However, I can hide that behind the new API and return only the
>> requested page if that's the intention.
>
> Well, if your firmware is so limited, then you might as well stick to
> the old API, and let the core do the conversion to the legacy
> code. But i'm surprised you don't allow access to the temperature
> sensors, received signal strength, voltages etc, which could be
> exported via HWMON.
>
I'll stick to the old API.
Regaring the sensors, our compute driver (under accel/habanalabs) exports
them via HWMON.
>>>> + ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
>>>
>>> That looks odd. Care to explain?
>>>
>>
>> The HW of all of our ports supports autoneg.
>> But in addition, the ports are divided to two groups:
>> internal: ports which are connected to other Gaudi2 ports in the same server.
>> external: ports which are connected to an external switch.
>> Only internal ports use autoneg.
>> The ports mask which sets each port as internal/external is fetched from
>> the FW on device load.
>
> That is not what i meant. lc_advertising should indicate the link
> modes the peer is advertising. If this was a copper link, it typically
> would contain 10BaseT-Half, 10BaseT-Full, 100BaseT-Half,
> 100BaseT-Full, 1000BaseT-Half. Setting the Autoneg bit is pointless,
> since the peer must be advertising in order that lp_advertising has a
> value!
>
Sorry, but I don't get this. The problem is the setting of the Autoneg bit
in lp_advertising? is that redundant? I see that other vendors set it too
in case that Autoneg was completed.
>> Our HW supports Pause frames.
>> But, PFC can be disabled via lldptool for exmaple, so we won't advertise
>> it.
>
> Please also implement the standard netdev way of configuring pause.
> When you do that, you should start to understand how pause can be
> negotiated, or forced. That is what most get wrong.
>
Let me revisit this.
>> I'll try to find more info about it, but can you please share what's wrong
>> with the curent code?
>> BTW I will change it to Asym_Pause as we support Tx pause frames as well.
>>
>>>> + if (auto_neg && !(hdev->auto_neg_mask & BIT(port_idx))) {
>>>> + netdev_err(port->ndev, "port autoneg is disabled by BMC\n");
>>>> + rc = -EFAULT;
>>>> + goto out;
>>>
>>> Don't say you support autoneg in supported if that is the case.
>>>
>>> And EFAULT is about memory problems. EINVAL, maybe EPERM? or
>>> EOPNOTSUPP.
>>>
>>> Andrew
>>
>> Yeah, should be switched to EPERM/EOPNOTSUPP.
>> Regarding the support of autoneg - the HW supports autoneg but it might be
>> disabled by the FW. Hence we might not be able to switch it on.
>
> No problem, ask the firmware what it is doing, and return the reality
> in ksetting. Only say you support autoneg if your firmware allows you
> to perform autoneg.
>
> Andrew
>
Ok, I'll set the Autoneg support bit properly.
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-19 7:16 ` Omer Shpigelman
@ 2024-06-19 8:01 ` Przemek Kitszel
2024-06-19 12:15 ` Omer Shpigelman
2024-06-19 15:21 ` Jakub Kicinski
2024-06-19 16:13 ` Andrew Lunn
2 siblings, 1 reply; 108+ messages in thread
From: Przemek Kitszel @ 2024-06-19 8:01 UTC (permalink / raw)
To: Omer Shpigelman, Andrew Lunn
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/19/24 09:16, Omer Shpigelman wrote:
> On 6/18/24 17:19, Andrew Lunn wrote:
[...]
>>>>> +module_param(poll_enable, bool, 0444);
>>>>> +MODULE_PARM_DESC(poll_enable,
>>>>> + "Enable Rx polling rather than IRQ + NAPI (0 = no, 1 = yes, default: no)");
>>>>
>>>> Module parameters are not liked. This probably needs to go away.
>>>>
>>>
>>> I see that various vendors under net/ethernet/* use module parameters.
>>> Can't we add another one?
>>
>> Look at the history of those module parameters. Do you see many added
>> in the last year? 5 years?
>>
>
> I didn't check that prior to my submit. Regarding this "no new module
> parameters allowed" rule, is that documented anywhere? if not, is that the
> common practice? not to try to do something that was not done recently?
> how "recently" is defined?
> I just want to clarify this because it's hard to handle these submissions
> when we write some code based on existing examples but then we are
> rejected because "we don't do that here anymore".
> I want to avoid future cases of this mismatch.
>
best way is to read netdev ML, that way you will learn what interfaces
are frowned upon and which are outright banned, sometimes you could
judge yourself knowing which interfaces are most developed recently
in this module params example - they were introduced to allow init phase
configuration of the device, that could not be postponed, what in the
general case sounds like a workaround; hardest cases include huge swaths
of (physical continuous) memory to be allocated, but for that there are
now device tree binding solutions; more typical cases for networking are
resolved via devlink reload
devlink parms are also the thing that should be used as a default for
new parameters, the best if given parameter is not driver specific quirk
poll_enable sounds like something that should be a common param,
but you have to better describe what you mean there
(see napi_poll(), "Enable Rx polling" would mean to use that as default,
do you mean busy polling or what?)
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-19 8:01 ` Przemek Kitszel
@ 2024-06-19 12:15 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-19 12:15 UTC (permalink / raw)
To: Przemek Kitszel, Andrew Lunn
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/19/24 11:01, Przemek Kitszel wrote:
> On 6/19/24 09:16, Omer Shpigelman wrote:
>> On 6/18/24 17:19, Andrew Lunn wrote:
>
> [...]
>
>>>>>> +module_param(poll_enable, bool, 0444);
>>>>>> +MODULE_PARM_DESC(poll_enable,
>>>>>> + "Enable Rx polling rather than IRQ + NAPI (0 = no, 1 = yes, default: no)");
>>>>>
>>>>> Module parameters are not liked. This probably needs to go away.
>>>>>
>>>>
>>>> I see that various vendors under net/ethernet/* use module parameters.
>>>> Can't we add another one?
>>>
>>> Look at the history of those module parameters. Do you see many added
>>> in the last year? 5 years?
>>>
>>
>> I didn't check that prior to my submit. Regarding this "no new module
>> parameters allowed" rule, is that documented anywhere? if not, is that the
>> common practice? not to try to do something that was not done recently?
>> how "recently" is defined?
>> I just want to clarify this because it's hard to handle these submissions
>> when we write some code based on existing examples but then we are
>> rejected because "we don't do that here anymore".
>> I want to avoid future cases of this mismatch.
>>
>
> best way is to read netdev ML, that way you will learn what interfaces
> are frowned upon and which are outright banned, sometimes you could
> judge yourself knowing which interfaces are most developed recently
>
> in this module params example - they were introduced to allow init phase
> configuration of the device, that could not be postponed, what in the
> general case sounds like a workaround; hardest cases include huge swaths
> of (physical continuous) memory to be allocated, but for that there are
> now device tree binding solutions; more typical cases for networking are
> resolved via devlink reload
>
> devlink parms are also the thing that should be used as a default for
> new parameters, the best if given parameter is not driver specific quirk
>
> poll_enable sounds like something that should be a common param,
> but you have to better describe what you mean there
> (see napi_poll(), "Enable Rx polling" would mean to use that as default,
> do you mean busy polling or what?)
Yes, busy polling.
But never mind, I was informed that NAPI must be used so apparently I'll
need to anyway remove this polling mode and its module parameter.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-19 7:16 ` Omer Shpigelman
2024-06-19 8:01 ` Przemek Kitszel
@ 2024-06-19 15:21 ` Jakub Kicinski
2024-06-20 8:43 ` Omer Shpigelman
2024-06-19 16:13 ` Andrew Lunn
2 siblings, 1 reply; 108+ messages in thread
From: Jakub Kicinski @ 2024-06-19 15:21 UTC (permalink / raw)
To: Omer Shpigelman
Cc: Andrew Lunn, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On Wed, 19 Jun 2024 07:16:20 +0000 Omer Shpigelman wrote:
> >> Are you referring to get_module_eeprom_by_page()? if so, then it is not
> >> supported by our FW, we read the entire data on device load.
> >> However, I can hide that behind the new API and return only the
> >> requested page if that's the intention.
> >
> > Well, if your firmware is so limited, then you might as well stick to
> > the old API, and let the core do the conversion to the legacy
> > code. But i'm surprised you don't allow access to the temperature
> > sensors, received signal strength, voltages etc, which could be
> > exported via HWMON.
>
> I'll stick to the old API.
> Regaring the sensors, our compute driver (under accel/habanalabs) exports
> them via HWMON.
You support 400G, you really need to give the user the ability
to access higher pages.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-19 15:21 ` Jakub Kicinski
@ 2024-06-20 8:43 ` Omer Shpigelman
2024-06-20 13:51 ` Jakub Kicinski
0 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-20 8:43 UTC (permalink / raw)
To: Jakub Kicinski
Cc: Andrew Lunn, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On 6/19/24 18:21, Jakub Kicinski wrote:
> [Some people who received this message don't often get email from kuba@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On Wed, 19 Jun 2024 07:16:20 +0000 Omer Shpigelman wrote:
>>>> Are you referring to get_module_eeprom_by_page()? if so, then it is not
>>>> supported by our FW, we read the entire data on device load.
>>>> However, I can hide that behind the new API and return only the
>>>> requested page if that's the intention.
>>>
>>> Well, if your firmware is so limited, then you might as well stick to
>>> the old API, and let the core do the conversion to the legacy
>>> code. But i'm surprised you don't allow access to the temperature
>>> sensors, received signal strength, voltages etc, which could be
>>> exported via HWMON.
>>
>> I'll stick to the old API.
>> Regaring the sensors, our compute driver (under accel/habanalabs) exports
>> them via HWMON.
>
> You support 400G, you really need to give the user the ability
> to access higher pages.
Actually the 200G and 400G modes in the ethtool code should be removed
from this patch set. They are not relevant for Gaudi2. I'll fix it in the
next version.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-20 8:43 ` Omer Shpigelman
@ 2024-06-20 13:51 ` Jakub Kicinski
2024-06-20 19:14 ` Andrew Lunn
0 siblings, 1 reply; 108+ messages in thread
From: Jakub Kicinski @ 2024-06-20 13:51 UTC (permalink / raw)
To: Omer Shpigelman
Cc: Andrew Lunn, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On Thu, 20 Jun 2024 08:43:34 +0000 Omer Shpigelman wrote:
> > You support 400G, you really need to give the user the ability
> > to access higher pages.
>
> Actually the 200G and 400G modes in the ethtool code should be removed
> from this patch set. They are not relevant for Gaudi2. I'll fix it in the
> next version.
How do your customers / users check SFP diagnostics?
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-20 13:51 ` Jakub Kicinski
@ 2024-06-20 19:14 ` Andrew Lunn
2024-06-23 14:48 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Andrew Lunn @ 2024-06-20 19:14 UTC (permalink / raw)
To: Jakub Kicinski
Cc: Omer Shpigelman, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On Thu, Jun 20, 2024 at 06:51:35AM -0700, Jakub Kicinski wrote:
> On Thu, 20 Jun 2024 08:43:34 +0000 Omer Shpigelman wrote:
> > > You support 400G, you really need to give the user the ability
> > > to access higher pages.
> >
> > Actually the 200G and 400G modes in the ethtool code should be removed
> > from this patch set. They are not relevant for Gaudi2. I'll fix it in the
> > next version.
>
> How do your customers / users check SFP diagnostics?
And perform firmware upgrade of the SFPs?
https://lore.kernel.org/netdev/20240619121727.3643161-7-danieller@nvidia.com/T/
Andrew
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-20 19:14 ` Andrew Lunn
@ 2024-06-23 14:48 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-23 14:48 UTC (permalink / raw)
To: Andrew Lunn, Jakub Kicinski
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/20/24 22:14, Andrew Lunn wrote:
> On Thu, Jun 20, 2024 at 06:51:35AM -0700, Jakub Kicinski wrote:
>> On Thu, 20 Jun 2024 08:43:34 +0000 Omer Shpigelman wrote:
>>>> You support 400G, you really need to give the user the ability
>>>> to access higher pages.
>>>
>>> Actually the 200G and 400G modes in the ethtool code should be removed
>>> from this patch set. They are not relevant for Gaudi2. I'll fix it in the
>>> next version.
>>
>> How do your customers / users check SFP diagnostics?
>
> And perform firmware upgrade of the SFPs?
>
> https://lore.kernel.org/netdev/20240619121727.3643161-7-danieller@nvidia.com/T/
>
> Andrew
>
Via OAM I2C Master.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-19 7:16 ` Omer Shpigelman
2024-06-19 8:01 ` Przemek Kitszel
2024-06-19 15:21 ` Jakub Kicinski
@ 2024-06-19 16:13 ` Andrew Lunn
2024-06-23 6:22 ` Omer Shpigelman
2 siblings, 1 reply; 108+ messages in thread
From: Andrew Lunn @ 2024-06-19 16:13 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On Wed, Jun 19, 2024 at 07:16:20AM +0000, Omer Shpigelman wrote:
> On 6/18/24 17:19, Andrew Lunn wrote:
> >>>> +static u32 hbl_en_get_mtu(struct hbl_aux_dev *aux_dev, u32 port_idx)
> >>>> +{
> >>>> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> >>>> + struct net_device *ndev = port->ndev;
> >>>> + u32 mtu;
> >>>> +
> >>>> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> >>>> + netdev_err(ndev, "port is in reset, can't get MTU\n");
> >>>> + return 0;
> >>>> + }
> >>>> +
> >>>> + mtu = ndev->mtu;
> >>>
> >>> I think you need a better error message. All this does is access
> >>> ndev->mtu. What does it matter if the port is in reset? You don't
> >>> access it.
> >>>
> >>
> >> This function is called from the CN driver to get the current MTU in order
> >> to configure it to the HW, for exmaple when configuring an IB QP. The MTU
> >> value might be changed by user while we execute this function.
> >
> > Change of MTU will happen while holding RTNL. Why not simply hold RTNL
> > while programming the hardware? That is the normal pattern for MAC
> > drivers.
> >
>
> I can hold the RTNL lock while configuring the HW but it seems like a big
> overhead. Configuring the HW might take some time due to QP draining or
> cache invalidation.
How often does the MTU change? Once, maybe twice on boot, and never
again? MTU change is not hot path. For slow path code, KISS is much
better, so it is likely to be correct.
> To me it seems unnecessary but if that's the common way then I'll change
> it.
>
> >>>> +static int hbl_en_change_mtu(struct net_device *netdev, int new_mtu)
> >>>> +{
> >>>> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> >>>> + int rc = 0;
> >>>> +
> >>>> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> >>>> + netdev_err(netdev, "port is in reset, can't change MTU\n");
> >>>> + return -EBUSY;
> >>>> + }
> >>>> +
> >>>> + if (netif_running(port->ndev)) {
> >>>> + hbl_en_port_close(port);
> >>>> +
> >>>> + /* Sleep in order to let obsolete events to be dropped before re-opening the port */
> >>>> + msleep(20);
> >>>> +
> >>>> + netdev->mtu = new_mtu;
> >>>> +
> >>>> + rc = hbl_en_port_open(port);
> >>>> + if (rc)
> >>>> + netdev_err(netdev, "Failed to reinit port for MTU change, rc %d\n", rc);
> >>>
> >>> Does that mean the port is FUBAR?
> >>>
> >>> Most operations like this are expected to roll back to the previous
> >>> working configuration on failure. So if changing the MTU requires new
> >>> buffers in your ring, you should first allocate the new buffers, then
> >>> free the old buffers, so that if allocation fails, you still have
> >>> buffers, and the device can continue operating.
> >>>
> >>
> >> A failure in opening a port is a fatal error. It shouldn't happen. This is
> >> not something we wish to recover from.
> >
> > What could cause open to fail? Is memory allocated?
> >
>
> Memory is allocated but it is freed in case of a failure.
> Port opening can fail due to other reasons as well like some HW timeout
> while configuring the ETH QP.
If the hardware timeout because the hardware is dead, there is nothing
you can do about it. Its dead.
But what about when the system is under memory pressure? You say it
allocates memory. What happens if those allocations fail. Does
changing the MTU take me from a working system to a dead system? It is
good practice to not kill a working system under situations like
memory pressure. You try to first allocate the memory you need to
handle the new MTU, and only if successful do you free existing memory
you no longer need. That means if you cannot allocate the needed
memory, you still have the old memory, you can keep the old MTU and
return -ENOMEM, and the system keeps running.
> I didn't check that prior to my submit. Regarding this "no new module
> parameters allowed" rule, is that documented anywhere?
Lots of emails that fly passed on the mailing list. Maybe once every
couple of months when a vendor tries to mainline a new driver without
reading the mailing list for a few months to know how mainline
actually works. I _guess_ Davem has been pushing back on module
parameters for 10 years? Maybe more.
> if not, is that the
> common practice? not to try to do something that was not done recently?
> how "recently" is defined?
> I just want to clarify this because it's hard to handle these submissions
> when we write some code based on existing examples but then we are
> rejected because "we don't do that here anymore".
> I want to avoid future cases of this mismatch.
My suggestion would be to spend 30 minutes every day reading patches
and review comment on the mailing list. Avoid making the same mistakes
others make, especially newbies to mainline, and see what others are
doing in the same niche as this device. 30 minutes might seem like a
lot, but how much time did you waste implementing polling mode, now
you are going to throw it away?
> >>>> + ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
> >>>
> >>> That looks odd. Care to explain?
> >>>
> >>
> >> The HW of all of our ports supports autoneg.
> >> But in addition, the ports are divided to two groups:
> >> internal: ports which are connected to other Gaudi2 ports in the same server.
> >> external: ports which are connected to an external switch.
> >> Only internal ports use autoneg.
> >> The ports mask which sets each port as internal/external is fetched from
> >> the FW on device load.
> >
> > That is not what i meant. lc_advertising should indicate the link
> > modes the peer is advertising. If this was a copper link, it typically
> > would contain 10BaseT-Half, 10BaseT-Full, 100BaseT-Half,
> > 100BaseT-Full, 1000BaseT-Half. Setting the Autoneg bit is pointless,
> > since the peer must be advertising in order that lp_advertising has a
> > value!
> >
>
> Sorry, but I don't get this. The problem is the setting of the Autoneg bit
> in lp_advertising? is that redundant? I see that other vendors set it too
> in case that Autoneg was completed.
$ ethtool eth0
Settings for eth0:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
This is `supported`. The hardware can do these link modes.
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
It also support symmetric pause, and can do autoneg.
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
This is `advertising`, and is what this device is advertising to the
link partner. By default you copy supported into advertising, but the
user can use ethtool -s advertise N, where N is a list of link modes,
to change what is advertised to the link partner.
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
Link partner advertised pause frame use: Symmetric
Link partner advertised auto-negotiation: Yes
Link partner advertised FEC modes: Not reported
This is `lp_advertising`, what the link partner is advertising to this
device. Once you have this, you mask lp_advertising with advertising,
and generally pick the link mode with the highest bandwidth:
Speed: 1000Mb/s
Duplex: Full
So autoneg resolved to 1000baseT/Full
Andrew
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-19 16:13 ` Andrew Lunn
@ 2024-06-23 6:22 ` Omer Shpigelman
2024-06-23 14:46 ` Andrew Lunn
0 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-23 6:22 UTC (permalink / raw)
To: Andrew Lunn
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/19/24 19:13, Andrew Lunn wrote:
> On Wed, Jun 19, 2024 at 07:16:20AM +0000, Omer Shpigelman wrote:
>> On 6/18/24 17:19, Andrew Lunn wrote:
>>>>>> +static u32 hbl_en_get_mtu(struct hbl_aux_dev *aux_dev, u32 port_idx)
>>>>>> +{
>>>>>> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
>>>>>> + struct net_device *ndev = port->ndev;
>>>>>> + u32 mtu;
>>>>>> +
>>>>>> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
>>>>>> + netdev_err(ndev, "port is in reset, can't get MTU\n");
>>>>>> + return 0;
>>>>>> + }
>>>>>> +
>>>>>> + mtu = ndev->mtu;
>>>>>
>>>>> I think you need a better error message. All this does is access
>>>>> ndev->mtu. What does it matter if the port is in reset? You don't
>>>>> access it.
>>>>>
>>>>
>>>> This function is called from the CN driver to get the current MTU in order
>>>> to configure it to the HW, for exmaple when configuring an IB QP. The MTU
>>>> value might be changed by user while we execute this function.
>>>
>>> Change of MTU will happen while holding RTNL. Why not simply hold RTNL
>>> while programming the hardware? That is the normal pattern for MAC
>>> drivers.
>>>
>>
>> I can hold the RTNL lock while configuring the HW but it seems like a big
>> overhead. Configuring the HW might take some time due to QP draining or
>> cache invalidation.
>
> How often does the MTU change? Once, maybe twice on boot, and never
> again? MTU change is not hot path. For slow path code, KISS is much
> better, so it is likely to be correct.
>
Yeah, it's not a hot path so I guess we can just return the MTU value
regardless of a parallel reset flow.
>> To me it seems unnecessary but if that's the common way then I'll change
>> it.
>>
>>>>>> +static int hbl_en_change_mtu(struct net_device *netdev, int new_mtu)
>>>>>> +{
>>>>>> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
>>>>>> + int rc = 0;
>>>>>> +
>>>>>> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
>>>>>> + netdev_err(netdev, "port is in reset, can't change MTU\n");
>>>>>> + return -EBUSY;
>>>>>> + }
>>>>>> +
>>>>>> + if (netif_running(port->ndev)) {
>>>>>> + hbl_en_port_close(port);
>>>>>> +
>>>>>> + /* Sleep in order to let obsolete events to be dropped before re-opening the port */
>>>>>> + msleep(20);
>>>>>> +
>>>>>> + netdev->mtu = new_mtu;
>>>>>> +
>>>>>> + rc = hbl_en_port_open(port);
>>>>>> + if (rc)
>>>>>> + netdev_err(netdev, "Failed to reinit port for MTU change, rc %d\n", rc);
>>>>>
>>>>> Does that mean the port is FUBAR?
>>>>>
>>>>> Most operations like this are expected to roll back to the previous
>>>>> working configuration on failure. So if changing the MTU requires new
>>>>> buffers in your ring, you should first allocate the new buffers, then
>>>>> free the old buffers, so that if allocation fails, you still have
>>>>> buffers, and the device can continue operating.
>>>>>
>>>>
>>>> A failure in opening a port is a fatal error. It shouldn't happen. This is
>>>> not something we wish to recover from.
>>>
>>> What could cause open to fail? Is memory allocated?
>>>
>>
>> Memory is allocated but it is freed in case of a failure.
>> Port opening can fail due to other reasons as well like some HW timeout
>> while configuring the ETH QP.
>
> If the hardware timeout because the hardware is dead, there is nothing
> you can do about it. Its dead.
>
In our case the HW might timeout without being dead. Our ETH and RDMA QPs
are being configured in the same path in the HW so it is possible that a
timeout for ETH QP configuration will occur due to many parallel RDMA QPs
configurations and so a simple ETH QP configuration retry will solve it.
> But what about when the system is under memory pressure? You say it
> allocates memory. What happens if those allocations fail. Does
> changing the MTU take me from a working system to a dead system? It is
> good practice to not kill a working system under situations like
> memory pressure. You try to first allocate the memory you need to
> handle the new MTU, and only if successful do you free existing memory
> you no longer need. That means if you cannot allocate the needed
> memory, you still have the old memory, you can keep the old MTU and
> return -ENOMEM, and the system keeps running.
>
That's a good optimization for these kind of on-the-fly configurations but
as you wrote before, changing an MTU value is not a hot path so out of
cost-benefit considerations we didn't find it mandatory to optimize this
flow.
But let me check this option for the next patch set version.
>> I didn't check that prior to my submit. Regarding this "no new module
>> parameters allowed" rule, is that documented anywhere?
>
> Lots of emails that fly passed on the mailing list. Maybe once every
> couple of months when a vendor tries to mainline a new driver without
> reading the mailing list for a few months to know how mainline
> actually works. I _guess_ Davem has been pushing back on module
> parameters for 10 years? Maybe more.
>
>
Ok, I'll just drop it in the next patch set version.
>> if not, is that the
>> common practice? not to try to do something that was not done recently?
>> how "recently" is defined?
>> I just want to clarify this because it's hard to handle these submissions
>> when we write some code based on existing examples but then we are
>> rejected because "we don't do that here anymore".
>> I want to avoid future cases of this mismatch.
>
> My suggestion would be to spend 30 minutes every day reading patches
> and review comment on the mailing list. Avoid making the same mistakes
> others make, especially newbies to mainline, and see what others are
> doing in the same niche as this device. 30 minutes might seem like a
> lot, but how much time did you waste implementing polling mode, now
> you are going to throw it away?
>
I get your point but still it will be good if it would be documented
somewhere IMHO.
>>>>>> + ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
>>>>>
>>>>> That looks odd. Care to explain?
>>>>>
>>>>
>>>> The HW of all of our ports supports autoneg.
>>>> But in addition, the ports are divided to two groups:
>>>> internal: ports which are connected to other Gaudi2 ports in the same server.
>>>> external: ports which are connected to an external switch.
>>>> Only internal ports use autoneg.
>>>> The ports mask which sets each port as internal/external is fetched from
>>>> the FW on device load.
>>>
>>> That is not what i meant. lc_advertising should indicate the link
>>> modes the peer is advertising. If this was a copper link, it typically
>>> would contain 10BaseT-Half, 10BaseT-Full, 100BaseT-Half,
>>> 100BaseT-Full, 1000BaseT-Half. Setting the Autoneg bit is pointless,
>>> since the peer must be advertising in order that lp_advertising has a
>>> value!
>>>
>>
>> Sorry, but I don't get this. The problem is the setting of the Autoneg bit
>> in lp_advertising? is that redundant? I see that other vendors set it too
>> in case that Autoneg was completed.
>
>
> $ ethtool eth0
> Settings for eth0:
> Supported ports: [ TP MII ]
> Supported link modes: 10baseT/Half 10baseT/Full
> 100baseT/Half 100baseT/Full
> 1000baseT/Full
>
> This is `supported`. The hardware can do these link modes.
>
> Supported pause frame use: Symmetric Receive-only
> Supports auto-negotiation: Yes
>
> It also support symmetric pause, and can do autoneg.
>
> Supported FEC modes: Not reported
> Advertised link modes: 10baseT/Half 10baseT/Full
> 100baseT/Half 100baseT/Full
> 1000baseT/Full
> Advertised pause frame use: Symmetric Receive-only
> Advertised auto-negotiation: Yes
> Advertised FEC modes: Not reported
>
> This is `advertising`, and is what this device is advertising to the
> link partner. By default you copy supported into advertising, but the
> user can use ethtool -s advertise N, where N is a list of link modes,
> to change what is advertised to the link partner.
>
> Link partner advertised link modes: 10baseT/Half 10baseT/Full
> 100baseT/Half 100baseT/Full
> 1000baseT/Full
> Link partner advertised pause frame use: Symmetric
> Link partner advertised auto-negotiation: Yes
> Link partner advertised FEC modes: Not reported
>
> This is `lp_advertising`, what the link partner is advertising to this
> device. Once you have this, you mask lp_advertising with advertising,
> and generally pick the link mode with the highest bandwidth:
>
> Speed: 1000Mb/s
> Duplex: Full
>
> So autoneg resolved to 1000baseT/Full
>
> Andrew
I'm familiar with this logic but I don't understand your point. The point
you are making is that setting this Autoneg bit in lp_advertising is
pointless? I see other vendors setting it too in case that autoneg was
completed.
Is that redundant also in their case? because it looks to me that in this
case we followed the same logic and conventions other vendors followed.
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-23 6:22 ` Omer Shpigelman
@ 2024-06-23 14:46 ` Andrew Lunn
2024-06-26 10:13 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Andrew Lunn @ 2024-06-23 14:46 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
> > But what about when the system is under memory pressure? You say it
> > allocates memory. What happens if those allocations fail. Does
> > changing the MTU take me from a working system to a dead system? It is
> > good practice to not kill a working system under situations like
> > memory pressure. You try to first allocate the memory you need to
> > handle the new MTU, and only if successful do you free existing memory
> > you no longer need. That means if you cannot allocate the needed
> > memory, you still have the old memory, you can keep the old MTU and
> > return -ENOMEM, and the system keeps running.
> >
>
> That's a good optimization for these kind of on-the-fly configurations but
> as you wrote before, changing an MTU value is not a hot path so out of
> cost-benefit considerations we didn't find it mandatory to optimize this
> flow.
I would not call this an optimization. And it is not just about
changing the MTU. ethtool set_ringparam() is also likely to run into
this problem, and any other configuration which requires reallocating
the rings.
This is something else which comes up every few months on the list,
and drivers writers who monitor the list will write their drivers that
why, not 'optimise' it later.
> I get your point but still it will be good if it would be documented
> somewhere IMHO.
Kernel documentation is poor, agreed. But kernel policy is also
somewhat fluid, best practices change, and any developers can
influence that policy, different subsystems can and do have
contradictory policy, etc. The mailing list is the best place to learn
and to take part in this community. You need to be on the list for
other reasons as well.
> I'm familiar with this logic but I don't understand your point. The point
> you are making is that setting this Autoneg bit in lp_advertising is
> pointless? I see other vendors setting it too in case that autoneg was
> completed.
> Is that redundant also in their case? because it looks to me that in this
> case we followed the same logic and conventions other vendors followed.
Please show us the output from ethtool. Does it look like the example
i showed? I must admit, i'm more from the embedded world and don't
have access to high speed interfaces. But the basic concept of
auto-neg should not change that much.
Andrew
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-23 14:46 ` Andrew Lunn
@ 2024-06-26 10:13 ` Omer Shpigelman
2024-06-26 14:13 ` Andrew Lunn
0 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-26 10:13 UTC (permalink / raw)
To: Andrew Lunn
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/23/24 17:46, Andrew Lunn wrote:
>>> But what about when the system is under memory pressure? You say it
>>> allocates memory. What happens if those allocations fail. Does
>>> changing the MTU take me from a working system to a dead system? It is
>>> good practice to not kill a working system under situations like
>>> memory pressure. You try to first allocate the memory you need to
>>> handle the new MTU, and only if successful do you free existing memory
>>> you no longer need. That means if you cannot allocate the needed
>>> memory, you still have the old memory, you can keep the old MTU and
>>> return -ENOMEM, and the system keeps running.
>>>
>>
>> That's a good optimization for these kind of on-the-fly configurations but
>> as you wrote before, changing an MTU value is not a hot path so out of
>> cost-benefit considerations we didn't find it mandatory to optimize this
>> flow.
>
> I would not call this an optimization. And it is not just about
> changing the MTU. ethtool set_ringparam() is also likely to run into
> this problem, and any other configuration which requires reallocating
> the rings.
>
> This is something else which comes up every few months on the list,
> and drivers writers who monitor the list will write their drivers that
> why, not 'optimise' it later.
>
Actually I was wrong, we don't allocate memory in this port reset flow, we
only reset the rings. But I get your point, it makes sense.
>> I get your point but still it will be good if it would be documented
>> somewhere IMHO.
>
> Kernel documentation is poor, agreed. But kernel policy is also
> somewhat fluid, best practices change, and any developers can
> influence that policy, different subsystems can and do have
> contradictory policy, etc. The mailing list is the best place to learn
> and to take part in this community. You need to be on the list for
> other reasons as well.
>
Ok, got it.
>> I'm familiar with this logic but I don't understand your point. The point
>> you are making is that setting this Autoneg bit in lp_advertising is
>> pointless? I see other vendors setting it too in case that autoneg was
>> completed.
>> Is that redundant also in their case? because it looks to me that in this
>> case we followed the same logic and conventions other vendors followed.
>
> Please show us the output from ethtool. Does it look like the example
> i showed? I must admit, i'm more from the embedded world and don't
> have access to high speed interfaces. But the basic concept of
> auto-neg should not change that much.
>
> Andrew
Here is the output:
$ ethtool eth0
Settings for eth0:
Supported ports: [ FIBRE Backplane ]
Supported link modes: 100000baseKR4/Full
100000baseSR4/Full
100000baseCR4/Full
100000baseLR4_ER4/Full
Supported pause frame use: Symmetric
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 100000baseKR4/Full
100000baseSR4/Full
100000baseCR4/Full
100000baseLR4_ER4/Full
Advertised pause frame use: Symmetric
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: Not reported
Link partner advertised pause frame use: No
Link partner advertised auto-negotiation: Yes
Link partner advertised FEC modes: Not reported
Speed: 100000Mb/s
Duplex: Full
Auto-negotiation: on
There are few points to mention:
1. We don't allow to modify the advertised link modes so by definition the
advertised ones are a copy of the supported ones.
2. Reading the peer advertised link modes is not supported so we don't
report them (similarly to some other vendors).
3. Our speed is fixed and also cannot be changed so we don't mask
lp_advertising with advertising to pick the highest speed. We aim for a
specific speed and hence it's binary - or we'll have a link with that
specific speed or we won't have a link at all.
4. If we support autoneg and it was completed, we can conclude that also
our peer supports autoneg and hence we report that.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-26 10:13 ` Omer Shpigelman
@ 2024-06-26 14:13 ` Andrew Lunn
2024-06-30 7:11 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Andrew Lunn @ 2024-06-26 14:13 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
> Here is the output:
> $ ethtool eth0
> Settings for eth0:
> Supported ports: [ FIBRE Backplane ]
> Supported link modes: 100000baseKR4/Full
> 100000baseSR4/Full
> 100000baseCR4/Full
> 100000baseLR4_ER4/Full
> Supported pause frame use: Symmetric
> Supports auto-negotiation: Yes
> Supported FEC modes: Not reported
> Advertised link modes: 100000baseKR4/Full
> 100000baseSR4/Full
> 100000baseCR4/Full
> 100000baseLR4_ER4/Full
> Advertised pause frame use: Symmetric
> Advertised auto-negotiation: Yes
> Advertised FEC modes: Not reported
> Link partner advertised link modes: Not reported
> Link partner advertised pause frame use: No
> Link partner advertised auto-negotiation: Yes
> Link partner advertised FEC modes: Not reported
> Speed: 100000Mb/s
> Duplex: Full
> Auto-negotiation: on
>
> There are few points to mention:
> 1. We don't allow to modify the advertised link modes so by definition the
> advertised ones are a copy of the supported ones.
So there is no way to ask it use to use 100000baseCR4/Full, for
example? You would normally change the advertised modes to just that
one link mode, and then it has no choice. It either uses
100000baseCR4/Full, or it does not establish a link.
Also, my experience with slower modules is that one supporting
2500BaseX can also support 1000BaseX. However, there is no auto-neg
defined for speeds, just pause. So if the link peer only supports
1000BaseX, you don't get link. What you typically see is:
$ ethtool eth0
Settings for eth0:
Supported ports: [ FIBRE Backplane ]
Supported link modes: 1000baseX
2500baseX
Supported pause frame use: Symmetric
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 2500baseX
Advertised pause frame use: Symmetric
and then you use ethtool to change advertising to 1000baseX and then
you get link. Can these modules support slower speeds?
> 2. Reading the peer advertised link modes is not supported so we don't
> report them (similarly to some other vendors).
Not supported by your firmware? Or not supported by the modules?
Andrew
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-26 14:13 ` Andrew Lunn
@ 2024-06-30 7:11 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-30 7:11 UTC (permalink / raw)
To: Andrew Lunn
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/26/24 17:13, Andrew Lunn wrote:
>> Here is the output:
>> $ ethtool eth0
>> Settings for eth0:
>> Supported ports: [ FIBRE Backplane ]
>> Supported link modes: 100000baseKR4/Full
>> 100000baseSR4/Full
>> 100000baseCR4/Full
>> 100000baseLR4_ER4/Full
>> Supported pause frame use: Symmetric
>> Supports auto-negotiation: Yes
>> Supported FEC modes: Not reported
>> Advertised link modes: 100000baseKR4/Full
>> 100000baseSR4/Full
>> 100000baseCR4/Full
>> 100000baseLR4_ER4/Full
>> Advertised pause frame use: Symmetric
>> Advertised auto-negotiation: Yes
>> Advertised FEC modes: Not reported
>> Link partner advertised link modes: Not reported
>> Link partner advertised pause frame use: No
>> Link partner advertised auto-negotiation: Yes
>> Link partner advertised FEC modes: Not reported
>> Speed: 100000Mb/s
>> Duplex: Full
>> Auto-negotiation: on
>>
>> There are few points to mention:
>> 1. We don't allow to modify the advertised link modes so by definition the
>> advertised ones are a copy of the supported ones.
>
> So there is no way to ask it use to use 100000baseCR4/Full, for
> example? You would normally change the advertised modes to just that
> one link mode, and then it has no choice. It either uses
> 100000baseCR4/Full, or it does not establish a link.
>
No, our FW doesn't support it as we have no use case for that.
> Also, my experience with slower modules is that one supporting
> 2500BaseX can also support 1000BaseX. However, there is no auto-neg
> defined for speeds, just pause. So if the link peer only supports
> 1000BaseX, you don't get link. What you typically see is:
>
> $ ethtool eth0
> Settings for eth0:
> Supported ports: [ FIBRE Backplane ]
> Supported link modes: 1000baseX
> 2500baseX
> Supported pause frame use: Symmetric
> Supports auto-negotiation: Yes
> Supported FEC modes: Not reported
> Advertised link modes: 2500baseX
> Advertised pause frame use: Symmetric
>
> and then you use ethtool to change advertising to 1000baseX and then
> you get link. Can these modules support slower speeds?
>
No, we support a single speed.
>> 2. Reading the peer advertised link modes is not supported so we don't
>> report them (similarly to some other vendors).
>
> Not supported by your firmware? Or not supported by the modules?
>
Let me explain it better - Gaudi2 is not a general purpose Ethernet NIC.
Its goal is to support any Ethernet traffic that is needed for enabling
the scaling of AI neural networks training as part of HLS2 server:
https://www.intel.com/content/www/us/en/content-details/784778/hls-gaudi-2-deep-learning-server-datasheet.html
Hence, in contrary to a general purpose Ethernet NIC, it is well known who
is our peer and what are its capabilities - it is a Gaudi2 NIC or a
switch.
Technically we can read the advertised link partner modes but we had no
demand for that because the driver and the user are well aware of who is
on the other side.
Reading it from the FW will be the same as having it hard coded because
the value is already known (otherwise we won't have a link). I can add it
to lp_advertising if necessary although per my check most vendors don't
report it either.
> Andrew
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-13 8:22 ` [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver Omer Shpigelman
2024-06-13 21:49 ` Andrew Lunn
@ 2024-06-14 22:48 ` Joe Damato
2024-06-16 1:04 ` Andrew Lunn
2024-06-18 19:37 ` Omer Shpigelman
2024-06-15 0:10 ` Stephen Hemminger
` (3 subsequent siblings)
5 siblings, 2 replies; 108+ messages in thread
From: Joe Damato @ 2024-06-14 22:48 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel, linux-rdma, netdev, dri-devel, ogabbay, zyehudai
On Thu, Jun 13, 2024 at 11:22:02AM +0300, Omer Shpigelman wrote:
> This ethernet driver is initialized via auxiliary bus by the hbl_cn
> driver.
> It serves mainly for control operations that are needed for AI scaling.
>
> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> Co-developed-by: David Meriin <dmeriin@habana.ai>
> Signed-off-by: David Meriin <dmeriin@habana.ai>
> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
> ---
> MAINTAINERS | 9 +
> drivers/net/ethernet/intel/Kconfig | 18 +
> drivers/net/ethernet/intel/Makefile | 1 +
> drivers/net/ethernet/intel/hbl_en/Makefile | 9 +
> .../net/ethernet/intel/hbl_en/common/Makefile | 3 +
> .../net/ethernet/intel/hbl_en/common/hbl_en.c | 1168 +++++++++++++++++
> .../net/ethernet/intel/hbl_en/common/hbl_en.h | 206 +++
> .../intel/hbl_en/common/hbl_en_dcbnl.c | 101 ++
> .../ethernet/intel/hbl_en/common/hbl_en_drv.c | 211 +++
> .../intel/hbl_en/common/hbl_en_ethtool.c | 452 +++++++
> 10 files changed, 2178 insertions(+)
> create mode 100644 drivers/net/ethernet/intel/hbl_en/Makefile
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/Makefile
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 096439a62129..7301f38e9cfb 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -9617,6 +9617,15 @@ F: include/linux/habanalabs/
> F: include/linux/net/intel/cn*
> F: include/linux/net/intel/gaudi2*
>
> +HABANALABS ETHERNET DRIVER
> +M: Omer Shpigelman <oshpigelman@habana.ai>
> +L: netdev@vger.kernel.org
> +S: Supported
> +W: https://www.habana.ai
> +F: Documentation/networking/device_drivers/ethernet/intel/hbl.rst
> +F: drivers/net/ethernet/intel/hbl_en/
> +F: include/linux/net/intel/cn*
> +
> HACKRF MEDIA DRIVER
> L: linux-media@vger.kernel.org
> S: Orphan
> diff --git a/drivers/net/ethernet/intel/Kconfig b/drivers/net/ethernet/intel/Kconfig
> index 0d1b8a2bae99..5d07349348a0 100644
> --- a/drivers/net/ethernet/intel/Kconfig
> +++ b/drivers/net/ethernet/intel/Kconfig
> @@ -417,4 +417,22 @@ config HABANA_CN
> To compile this driver as a module, choose M here. The module
> will be called habanalabs_cn.
>
> +config HABANA_EN
> + tristate "HabanaLabs (an Intel Company) Ethernet driver"
> + depends on NETDEVICES && ETHERNET && INET
> + select HABANA_CN
> + help
> + This driver enables Ethernet functionality for the network interfaces
> + that are part of the GAUDI ASIC family of AI Accelerators.
> + For more information on how to identify your adapter, go to the
> + Adapter & Driver ID Guide that can be located at:
> +
> + <http://support.intel.com>
> +
> + More specific information on configuring the driver is in
> + <file:Documentation/networking/device_drivers/ethernet/intel/hbl.rst>.
> +
> + To compile this driver as a module, choose M here. The module
> + will be called habanalabs_en.
> +
> endif # NET_VENDOR_INTEL
> diff --git a/drivers/net/ethernet/intel/Makefile b/drivers/net/ethernet/intel/Makefile
> index 10049a28e336..ec62a0227897 100644
> --- a/drivers/net/ethernet/intel/Makefile
> +++ b/drivers/net/ethernet/intel/Makefile
> @@ -20,3 +20,4 @@ obj-$(CONFIG_FM10K) += fm10k/
> obj-$(CONFIG_ICE) += ice/
> obj-$(CONFIG_IDPF) += idpf/
> obj-$(CONFIG_HABANA_CN) += hbl_cn/
> +obj-$(CONFIG_HABANA_EN) += hbl_en/
> diff --git a/drivers/net/ethernet/intel/hbl_en/Makefile b/drivers/net/ethernet/intel/hbl_en/Makefile
> new file mode 100644
> index 000000000000..695497ab93b6
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/Makefile
> @@ -0,0 +1,9 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +#
> +# Makefile for HabanaLabs (an Intel Company) Ethernet network driver
> +#
> +
> +obj-$(CONFIG_HABANA_EN) := habanalabs_en.o
> +
> +include $(src)/common/Makefile
> +habanalabs_en-y += $(HBL_EN_COMMON_FILES)
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/Makefile b/drivers/net/ethernet/intel/hbl_en/common/Makefile
> new file mode 100644
> index 000000000000..a3ccb5dbf4a6
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +HBL_EN_COMMON_FILES := common/hbl_en_drv.o common/hbl_en.o \
> + common/hbl_en_ethtool.o common/hbl_en_dcbnl.o
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
> new file mode 100644
> index 000000000000..066be5ac2d84
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
> @@ -0,0 +1,1168 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#include "hbl_en.h"
> +#include <linux/inetdevice.h>
> +
> +#define TX_TIMEOUT (5 * HZ)
> +#define PORT_RESET_TIMEOUT_MSEC (60 * 1000ull) /* 60s */
> +
> +/**
> + * struct hbl_en_tx_pkt_work - used to schedule a work of a Tx packet.
> + * @tx_work: workqueue object to run when packet needs to be sent.
> + * @port: pointer to current port structure.
> + * @skb: copy of the packet to send.
> + */
> +struct hbl_en_tx_pkt_work {
> + struct work_struct tx_work;
> + struct hbl_en_port *port;
> + struct sk_buff *skb;
> +};
> +
> +static int hbl_en_napi_poll(struct napi_struct *napi, int budget);
> +static int hbl_en_port_open(struct hbl_en_port *port);
> +
> +static int hbl_en_ports_reopen(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> + struct hbl_en_port *port;
> + int rc = 0, i;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + /* It could be that the port was shutdown by 'ip link set down' and there is no need
> + * in reopening it.
> + * Since we mark the ports as in reset even if they are disabled, we clear the flag
> + * here anyway.
> + * See hbl_en_ports_stop_prepare() for more info.
> + */
> + if (!netif_running(port->ndev)) {
> + atomic_set(&port->in_reset, 0);
> + continue;
> + }
> +
> + rc = hbl_en_port_open(port);
> +
> + atomic_set(&port->in_reset, 0);
> +
> + if (rc)
> + break;
> + }
> +
> + hdev->in_reset = false;
> +
> + return rc;
> +}
> +
> +static void hbl_en_port_fini(struct hbl_en_port *port)
> +{
> + if (port->rx_wq)
> + destroy_workqueue(port->rx_wq);
> +}
> +
> +static int hbl_en_port_init(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + u32 port_idx = port->idx;
> + char wq_name[32];
> + int rc;
> +
> + if (hdev->poll_enable) {
> + memset(wq_name, 0, sizeof(wq_name));
> + snprintf(wq_name, sizeof(wq_name) - 1, "hbl%u-port%d-rx-wq", hdev->core_dev_id,
> + port_idx);
> + port->rx_wq = alloc_ordered_workqueue(wq_name, 0);
> + if (!port->rx_wq) {
> + dev_err(hdev->dev, "Failed to allocate Rx WQ\n");
> + rc = -ENOMEM;
> + goto fail;
> + }
> + }
> +
> + hbl_en_ethtool_init_coalesce(port);
> +
> + return 0;
> +
> +fail:
> + hbl_en_port_fini(port);
> +
> + return rc;
> +}
> +
> +static void _hbl_en_set_port_status(struct hbl_en_port *port, bool up)
> +{
> + struct net_device *ndev = port->ndev;
> + u32 port_idx = port->idx;
> +
> + if (up) {
> + netif_carrier_on(ndev);
> + netif_wake_queue(ndev);
> + } else {
> + netif_carrier_off(ndev);
> + netif_stop_queue(ndev);
> + }
> +
> + /* Unless link events are getting through the EQ, no need to print about link down events
> + * during port reset
> + */
> + if (port->hdev->has_eq || up || !atomic_read(&port->in_reset))
> + netdev_info(port->ndev, "link %s, port %d\n", up ? "up" : "down", port_idx);
> +}
> +
> +static void hbl_en_set_port_status(struct hbl_aux_dev *aux_dev, u32 port_idx, bool up)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + _hbl_en_set_port_status(port, up);
> +}
> +
> +static bool hbl_en_is_port_open(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + return port->is_initialized;
> +}
> +
> +/* get the src IP as it is done in devinet_ioctl() */
> +static int hbl_en_get_src_ip(struct hbl_aux_dev *aux_dev, u32 port_idx, u32 *src_ip)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> + struct net_device *ndev = port->ndev;
> + struct in_device *in_dev;
> + struct in_ifaddr *ifa;
> + int rc = 0;
> +
> + /* for the case where no src IP is configured */
> + *src_ip = 0;
> +
> + /* rtnl lock should be acquired in relevant flows before taking configuration lock */
> + if (!rtnl_is_locked()) {
> + netdev_err(port->ndev, "Rtnl lock is not acquired, can't proceed\n");
> + rc = -EFAULT;
> + goto out;
> + }
> +
> + in_dev = __in_dev_get_rtnl(ndev);
> + if (!in_dev) {
> + netdev_err(port->ndev, "Failed to get IPv4 struct\n");
> + rc = -EFAULT;
> + goto out;
> + }
> +
> + ifa = rtnl_dereference(in_dev->ifa_list);
> +
> + while (ifa) {
> + if (!strcmp(ndev->name, ifa->ifa_label)) {
> + /* convert the BE to native and later on it will be
> + * written to the HW as LE in QPC_SET
> + */
> + *src_ip = be32_to_cpu(ifa->ifa_local);
> + break;
> + }
> + ifa = rtnl_dereference(ifa->ifa_next);
> + }
> +out:
> + return rc;
> +}
> +
> +static void hbl_en_reset_stats(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + port->net_stats.rx_packets = 0;
> + port->net_stats.tx_packets = 0;
> + port->net_stats.rx_bytes = 0;
> + port->net_stats.tx_bytes = 0;
> + port->net_stats.tx_errors = 0;
> + atomic64_set(&port->net_stats.rx_dropped, 0);
> + atomic64_set(&port->net_stats.tx_dropped, 0);
> +}
> +
> +static u32 hbl_en_get_mtu(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> + struct net_device *ndev = port->ndev;
> + u32 mtu;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(ndev, "port is in reset, can't get MTU\n");
> + return 0;
> + }
> +
> + mtu = ndev->mtu;
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return mtu;
> +}
> +
> +static u32 hbl_en_get_pflags(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + return port->pflags;
> +}
> +
> +static void hbl_en_set_dev_lpbk(struct hbl_aux_dev *aux_dev, u32 port_idx, bool enable)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> + struct net_device *ndev = port->ndev;
> +
> + if (enable)
> + ndev->features |= NETIF_F_LOOPBACK;
> + else
> + ndev->features &= ~NETIF_F_LOOPBACK;
> +}
> +
> +/* This function should be called after ctrl_lock was taken */
> +static int hbl_en_port_open_locked(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct net_device *ndev = port->ndev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int rc;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + if (port->is_initialized)
> + return 0;
> +
> + if (!hdev->poll_enable)
> + netif_napi_add(ndev, &port->napi, hbl_en_napi_poll);
> +
> + rc = aux_ops->port_hw_init(aux_dev, port_idx);
> + if (rc) {
> + netdev_err(ndev, "Failed to configure the HW, rc %d\n", rc);
> + goto hw_init_fail;
> + }
> +
> + if (!hdev->poll_enable)
> + napi_enable(&port->napi);
> +
> + rc = hdev->asic_funcs.eth_port_open(port);
> + if (rc) {
> + netdev_err(ndev, "Failed to init H/W, rc %d\n", rc);
> + goto port_open_fail;
> + }
> +
> + rc = aux_ops->update_mtu(aux_dev, port_idx, ndev->mtu);
> + if (rc) {
> + netdev_err(ndev, "MTU update failed, rc %d\n", rc);
> + goto update_mtu_fail;
> + }
> +
> + rc = aux_ops->phy_init(aux_dev, port_idx);
> + if (rc) {
> + netdev_err(ndev, "PHY init failed, rc %d\n", rc);
> + goto phy_init_fail;
> + }
> +
> + netif_start_queue(ndev);
> +
> + port->is_initialized = true;
> +
> + return 0;
> +
> +phy_init_fail:
> + /* no need to revert the MTU change, it will be updated on next port open */
> +update_mtu_fail:
> + hdev->asic_funcs.eth_port_close(port);
> +port_open_fail:
> + if (!hdev->poll_enable)
> + napi_disable(&port->napi);
> +
> + aux_ops->port_hw_fini(aux_dev, port_idx);
> +hw_init_fail:
> + if (!hdev->poll_enable)
> + netif_napi_del(&port->napi);
> +
> + return rc;
> +}
> +
> +static int hbl_en_port_open(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int rc;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + aux_ops->ctrl_lock(aux_dev, port_idx);
> + rc = hbl_en_port_open_locked(port);
> + aux_ops->ctrl_unlock(aux_dev, port_idx);
> +
> + return rc;
> +}
> +
> +static int hbl_en_open(struct net_device *netdev)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + int rc;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(netdev, "port is in reset, can't open it\n");
> + return -EBUSY;
> + }
> +
> + rc = hbl_en_port_open(port);
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +/* This function should be called after ctrl_lock was taken */
> +static void hbl_en_port_close_locked(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + if (!port->is_initialized)
> + return;
> +
> + port->is_initialized = false;
> +
> + /* verify that the port is marked as closed before continuing */
> + mb();
> +
> + /* Print if not in hard reset flow e.g. from ip cmd */
> + if (!hdev->in_reset && netif_carrier_ok(port->ndev))
> + netdev_info(port->ndev, "port was closed\n");
> +
> + /* disable the PHY here so no link changes will occur from this point forward */
> + aux_ops->phy_fini(aux_dev, port_idx);
> +
> + /* disable Tx SW flow */
> + netif_carrier_off(port->ndev);
> + netif_tx_disable(port->ndev);
> +
> + /* stop Tx/Rx HW */
> + aux_ops->port_hw_fini(aux_dev, port_idx);
> +
> + /* disable Tx/Rx QPs */
> + hdev->asic_funcs.eth_port_close(port);
> +
> + /* stop Rx SW flow */
> + if (hdev->poll_enable) {
> + hbl_en_rx_poll_stop(port);
> + } else {
> + napi_disable(&port->napi);
> + netif_napi_del(&port->napi);
> + }
> +
> + /* Explicitly count the port close operations as we don't get a link event for this.
> + * Upon port open we receive a link event, hence no additional action required.
> + */
> + aux_ops->port_toggle_count(aux_dev, port_idx);
> +}
> +
> +static void hbl_en_port_close(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + aux_ops->ctrl_lock(aux_dev, port_idx);
> + hbl_en_port_close_locked(port);
> + aux_ops->ctrl_unlock(aux_dev, port_idx);
> +}
> +
> +/* This function should be called after ctrl_lock was taken */
> +static int __hbl_en_port_reset_locked(struct hbl_en_port *port)
> +{
> + hbl_en_port_close_locked(port);
> +
> + return hbl_en_port_open_locked(port);
> +}
> +
> +/* This function should be called after ctrl_lock was taken */
> +int hbl_en_port_reset_locked(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + return __hbl_en_port_reset_locked(port);
> +}
> +
> +int hbl_en_port_reset(struct hbl_en_port *port)
> +{
> + hbl_en_port_close(port);
> +
> + /* Sleep in order to let obsolete events to be dropped before re-opening the port */
> + msleep(20);
> +
> + return hbl_en_port_open(port);
> +}
> +
> +static int hbl_en_close(struct net_device *netdev)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + struct hbl_en_device *hdev = port->hdev;
> + ktime_t timeout;
> +
> + /* Looks like the return value of this function is not checked, so we can't just return
> + * EBUSY if the port is under reset. We need to wait until the reset is finished and then
> + * close the port. Otherwise the netdev will set the port as closed although port_close()
> + * wasn't called. Only if we waited long enough and the reset hasn't finished, we can return
> + * an error without actually closing the port as it is a fatal flow anyway.
> + */
> + timeout = ktime_add_ms(ktime_get(), PORT_RESET_TIMEOUT_MSEC);
> + while (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + /* If this is called from unregister_netdev() then the port was already closed and
> + * hence we can safely return.
> + * We could have just check the port_open boolean, but that might hide some future
> + * bugs. Hence it is better to use a dedicated flag for that.
> + */
> + if (READ_ONCE(hdev->in_teardown))
> + return 0;
> +
> + usleep_range(50, 200);
> + if (ktime_compare(ktime_get(), timeout) > 0) {
> + netdev_crit(netdev,
> + "Timeout while waiting for port to finish reset, can't close it\n"
> + );
> + return -EBUSY;
> + }
> + }
> +
> + hbl_en_port_close(port);
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return 0;
> +}
> +
> +/**
> + * hbl_en_ports_stop_prepare() - stop the Rx and Tx and synchronize with other reset flows.
> + * @aux_dev: habanalabs auxiliary device structure.
> + *
> + * This function makes sure that during the reset no packets will be processed and that
> + * ndo_open/ndo_close do not open/close the ports.
> + * A hard reset might occur right after the driver was loaded, which means before the ports
> + * initialization was finished. Therefore, even if the ports are not yet open, we mark it as in
> + * reset in order to avoid races. We clear the in reset flag later on when reopening the ports.
> + */
> +static void hbl_en_ports_stop_prepare(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> + struct hbl_en_port *port;
> + ktime_t timeout;
> + int i;
> +
> + /* Check if the ports where initialized. If not, we shouldn't mark them as in reset because
> + * they will fail to get opened.
> + */
> + if (!hdev->is_initialized || hdev->in_reset)
> + return;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + /* This function is competing with reset from ethtool/ip, so try to take the
> + * in_reset atomic and if we are already in a middle of reset, wait until reset
> + * function is finished.
> + * Reset function is designed to always finish (could take up to a few seconds in
> + * worst case).
> + * We mark also closed ports as in reset so they won't be able to get opened while
> + * the device in under reset.
> + */
> +
> + timeout = ktime_add_ms(ktime_get(), PORT_RESET_TIMEOUT_MSEC);
> + while (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + usleep_range(50, 200);
> + if (ktime_compare(ktime_get(), timeout) > 0) {
> + netdev_crit(port->ndev,
> + "Timeout while waiting for port %d to finish reset\n",
> + port->idx);
> + break;
> + }
> + }
> + }
> +
> + hdev->in_reset = true;
> +}
> +
> +static void hbl_en_ports_stop(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> + struct hbl_en_port *port;
> + int i;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + if (netif_running(port->ndev))
> + hbl_en_port_close(port);
> + }
> +}
> +
> +static int hbl_en_change_mtu(struct net_device *netdev, int new_mtu)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + int rc = 0;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(netdev, "port is in reset, can't change MTU\n");
> + return -EBUSY;
> + }
> +
> + if (netif_running(port->ndev)) {
> + hbl_en_port_close(port);
> +
> + /* Sleep in order to let obsolete events to be dropped before re-opening the port */
> + msleep(20);
> +
> + netdev->mtu = new_mtu;
> +
> + rc = hbl_en_port_open(port);
> + if (rc)
> + netdev_err(netdev, "Failed to reinit port for MTU change, rc %d\n", rc);
> + } else {
> + netdev->mtu = new_mtu;
> + }
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +/* Swap source and destination MAC addresses */
> +static inline void swap_l2(char *buf)
> +{
> + u16 *eth_hdr, tmp;
> +
> + eth_hdr = (u16 *)buf;
> + tmp = eth_hdr[0];
> + eth_hdr[0] = eth_hdr[3];
> + eth_hdr[3] = tmp;
> + tmp = eth_hdr[1];
> + eth_hdr[1] = eth_hdr[4];
> + eth_hdr[4] = tmp;
> + tmp = eth_hdr[2];
> + eth_hdr[2] = eth_hdr[5];
> + eth_hdr[5] = tmp;
> +}
> +
> +/* Swap source and destination IP addresses
> + */
> +static inline void swap_l3(char *buf)
> +{
> + u32 tmp;
> +
> + /* skip the Ethernet header and the IP header till source IP address */
> + buf += ETH_HLEN + 12;
> + tmp = ((u32 *)buf)[0];
> + ((u32 *)buf)[0] = ((u32 *)buf)[1];
> + ((u32 *)buf)[1] = tmp;
> +}
> +
> +static void do_tx_swap(struct hbl_en_port *port, struct sk_buff *skb)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + u16 *tmp_buff = (u16 *)skb->data;
> + u32 port_idx = port->idx;
> +
> + /* First, let's print the SKB we got */
> + dev_dbg_ratelimited(hdev->dev,
> + "Send [P%d]: dst-mac:%04x%04x%04x, src-mac:%04x%04x%04x, eth-type:%04x, len:%u\n",
> + port_idx, swab16(tmp_buff[0]), swab16(tmp_buff[1]), swab16(tmp_buff[2]),
> + swab16(tmp_buff[3]), swab16(tmp_buff[4]), swab16(tmp_buff[5]),
> + swab16(tmp_buff[6]), skb->len);
> +
> + /* Before submit it to HW, in case this is ipv4 pkt, swap eth/ip addresses.
> + * that way, we may send ECMP (ping) to ourselves in LB cases.
> + */
> + swap_l2(skb->data);
> + if (swab16(tmp_buff[6]) == ETH_P_IP)
> + swap_l3(skb->data);
> +}
> +
> +static bool is_pkt_swap_enabled(struct hbl_en_device *hdev)
> +{
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + return aux_ops->is_eth_lpbk(aux_dev);
> +}
> +
> +static bool is_tx_disabled(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + return aux_ops->get_mac_lpbk(aux_dev, port_idx) && !is_pkt_swap_enabled(hdev);
> +}
> +
> +static netdev_tx_t hbl_en_handle_tx(struct hbl_en_port *port, struct sk_buff *skb)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + netdev_tx_t ret;
> +
> + if (skb->len <= 0 || is_tx_disabled(port))
> + goto free_skb;
> +
> + if (skb->len > hdev->max_frm_len) {
> + netdev_err(port->ndev, "Tx pkt size %uB exceeds maximum of %uB\n", skb->len,
> + hdev->max_frm_len);
> + goto free_skb;
> + }
> +
> + if (is_pkt_swap_enabled(hdev))
> + do_tx_swap(port, skb);
> +
> + /* Pad the ethernet packets to the minimum frame size as the NIC hw doesn't do it.
> + * eth_skb_pad() frees the packet on failure, so just increment the dropped counter and
> + * return as success to avoid a retry.
> + */
> + if (skb_put_padto(skb, hdev->pad_size)) {
> + dev_err_ratelimited(hdev->dev, "Padding failed, the skb is dropped\n");
> + atomic64_inc(&port->net_stats.tx_dropped);
> + return NETDEV_TX_OK;
> + }
> +
> + ret = hdev->asic_funcs.write_pkt_to_hw(port, skb);
> + if (ret == NETDEV_TX_OK) {
> + port->net_stats.tx_packets++;
> + port->net_stats.tx_bytes += skb->len;
> + }
> +
> + return ret;
> +
> +free_skb:
> + dev_kfree_skb_any(skb);
> + return NETDEV_TX_OK;
> +}
> +
> +static netdev_tx_t hbl_en_start_xmit(struct sk_buff *skb, struct net_device *netdev)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + struct hbl_en_device *hdev;
> +
> + hdev = port->hdev;
> +
> + return hbl_en_handle_tx(port, skb);
> +}
> +
> +static int hbl_en_set_port_mac_loopback(struct hbl_en_port *port, bool enable)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct net_device *ndev = port->ndev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int rc;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + rc = aux_ops->set_mac_lpbk(aux_dev, port_idx, enable);
> + if (rc)
> + return rc;
> +
> + netdev_info(ndev, "port %u: mac loopback is %s\n", port_idx,
> + enable ? "enabled" : "disabled");
> +
> + if (netif_running(ndev)) {
> + rc = hbl_en_port_reset(port);
> + if (rc) {
> + netdev_err(ndev, "Failed to reset port %u, rc %d\n", port_idx, rc);
> + return rc;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int hbl_en_set_features(struct net_device *netdev, netdev_features_t features)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + netdev_features_t changed;
> + int rc = 0;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(netdev, "port %d is in reset, can't update settings", port->idx);
> + return -EBUSY;
> + }
> +
> + changed = netdev->features ^ features;
> +
> + if (changed & NETIF_F_LOOPBACK)
> + rc = hbl_en_set_port_mac_loopback(port, !!(features & NETIF_F_LOOPBACK));
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +static void hbl_en_handle_tx_timeout(struct net_device *netdev, unsigned int txqueue)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> +
> + port->net_stats.tx_errors++;
> + atomic64_inc(&port->net_stats.tx_dropped);
> +}
> +
> +static void hbl_en_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(dev);
> +
> + stats->rx_bytes = port->net_stats.rx_bytes;
> + stats->tx_bytes = port->net_stats.tx_bytes;
> + stats->rx_packets = port->net_stats.rx_packets;
> + stats->tx_packets = port->net_stats.tx_packets;
> + stats->tx_errors = port->net_stats.tx_errors;
> + stats->tx_dropped = (u64)atomic64_read(&port->net_stats.tx_dropped);
> + stats->rx_dropped = (u64)atomic64_read(&port->net_stats.rx_dropped);
> +}
> +
> +static const struct net_device_ops hbl_en_netdev_ops = {
> + .ndo_open = hbl_en_open,
> + .ndo_stop = hbl_en_close,
> + .ndo_start_xmit = hbl_en_start_xmit,
> + .ndo_validate_addr = eth_validate_addr,
> + .ndo_change_mtu = hbl_en_change_mtu,
> + .ndo_set_features = hbl_en_set_features,
> + .ndo_get_stats64 = hbl_en_get_stats64,
> + .ndo_tx_timeout = hbl_en_handle_tx_timeout,
> +};
> +
> +static void hbl_en_set_ops(struct net_device *ndev)
> +{
> + ndev->netdev_ops = &hbl_en_netdev_ops;
> + ndev->ethtool_ops = hbl_en_ethtool_get_ops(ndev);
> +#ifdef CONFIG_DCB
> + ndev->dcbnl_ops = &hbl_en_dcbnl_ops;
> +#endif
> +}
> +
> +static int hbl_en_port_register(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + struct hbl_en_port **ptr;
> + struct net_device *ndev;
> + int rc;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + ndev = alloc_etherdev(sizeof(struct hbl_en_port *));
> + if (!ndev) {
> + dev_err(hdev->dev, "netdevice %d alloc failed\n", port_idx);
> + return -ENOMEM;
> + }
> +
> + port->ndev = ndev;
> + SET_NETDEV_DEV(ndev, &hdev->pdev->dev);
> + ptr = netdev_priv(ndev);
> + *ptr = port;
> +
> + /* necessary for creating multiple interfaces */
> + ndev->dev_port = port_idx;
> +
> + hbl_en_set_ops(ndev);
> +
> + ndev->watchdog_timeo = TX_TIMEOUT;
> + ndev->min_mtu = hdev->min_raw_mtu;
> + ndev->max_mtu = hdev->max_raw_mtu;
> +
> + /* Add loopback capability to the device. */
> + ndev->hw_features |= NETIF_F_LOOPBACK;
> +
> + /* If this port was set to loopback, set it also to the ndev features */
> + if (aux_ops->get_mac_lpbk(aux_dev, port_idx))
> + ndev->features |= NETIF_F_LOOPBACK;
> +
> + eth_hw_addr_set(ndev, port->mac_addr);
> +
> + /* It's more an intelligent poll wherein, we enable the Rx completion EQE event and then
> + * start the poll from there.
> + * Inside the polling thread, we read packets from hardware and then reschedule the poll
> + * only if there are more packets to be processed. Else we re-enable the CQ Arm interrupt
> + * and exit the poll.
> + */
> + if (hdev->poll_enable)
> + hbl_en_rx_poll_trigger_init(port);
> +
> + netif_carrier_off(ndev);
> +
> + rc = register_netdev(ndev);
> + if (rc) {
> + dev_err(hdev->dev, "Could not register netdevice %d\n", port_idx);
> + goto err;
> + }
> +
> + return 0;
> +
> +err:
> + if (ndev) {
> + free_netdev(ndev);
> + port->ndev = NULL;
> + }
> +
> + return rc;
> +}
> +
> +static void dump_swap_pkt(struct hbl_en_port *port, struct sk_buff *skb)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + u16 *tmp_buff = (u16 *)skb->data;
> + u32 port_idx = port->idx;
> +
> + /* The SKB is ready now (before stripping-out the L2), print its content */
> + dev_dbg_ratelimited(hdev->dev,
> + "Recv [P%d]: dst-mac:%04x%04x%04x, src-mac:%04x%04x%04x, eth-type:%04x, len:%u\n",
> + port_idx, swab16(tmp_buff[0]), swab16(tmp_buff[1]), swab16(tmp_buff[2]),
> + swab16(tmp_buff[3]), swab16(tmp_buff[4]), swab16(tmp_buff[5]),
> + swab16(tmp_buff[6]), skb->len);
> +}
> +
> +int hbl_en_handle_rx(struct hbl_en_port *port, int budget)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + enum hbl_en_eth_pkt_status pkt_status;
> + struct net_device *ndev = port->ndev;
> + int rc, pkt_count = 0;
> + struct sk_buff *skb;
> + void *pkt_addr;
> + u32 pkt_size;
> +
> + if (!netif_carrier_ok(ndev))
> + return 0;
> +
> + while (pkt_count < budget) {
> + pkt_status = hdev->asic_funcs.read_pkt_from_hw(port, &pkt_addr, &pkt_size);
> +
> + if (pkt_status == ETH_PKT_NONE)
> + break;
> +
> + pkt_count++;
> +
> + if (pkt_status == ETH_PKT_DROP) {
> + atomic64_inc(&port->net_stats.rx_dropped);
> + continue;
> + }
> +
> + if (hdev->poll_enable)
> + skb = __netdev_alloc_skb_ip_align(ndev, pkt_size, GFP_KERNEL);
> + else
> + skb = napi_alloc_skb(&port->napi, pkt_size);
> +
> + if (!skb) {
> + atomic64_inc(&port->net_stats.rx_dropped);
It seems like buffer exhaustion (!skb) would be rx_missed_errors?
The documentation in include/uapi/linux/if_link.h:
* @rx_dropped: Number of packets received but not processed,
* e.g. due to lack of resources or unsupported protocol.
* For hardware interfaces this counter may include packets discarded
* due to L2 address filtering but should not include packets dropped
* by the device due to buffer exhaustion which are counted separately in
* @rx_missed_errors (since procfs folds those two counters together).
But, I don't know much about your hardware so I could be wrong.
> + break;
> + }
> +
> + skb_copy_to_linear_data(skb, pkt_addr, pkt_size);
> + skb_put(skb, pkt_size);
> +
> + if (is_pkt_swap_enabled(hdev))
> + dump_swap_pkt(port, skb);
> +
> + skb->protocol = eth_type_trans(skb, ndev);
> +
> + /* Zero the packet buffer memory to avoid leak in case of wrong
> + * size is used when next packet populates the same memory
> + */
> + memset(pkt_addr, 0, pkt_size);
> +
> + /* polling is done in thread context and hence BH should be disabled */
> + if (hdev->poll_enable)
> + local_bh_disable();
> +
> + rc = netif_receive_skb(skb);
Is there any reason in particular to call netif_receive_skb instead of
napi_gro_receive ?
> +
> + if (hdev->poll_enable)
> + local_bh_enable();
> +
> + if (rc == NET_RX_SUCCESS) {
> + port->net_stats.rx_packets++;
> + port->net_stats.rx_bytes += pkt_size;
> + } else {
> + atomic64_inc(&port->net_stats.rx_dropped);
> + }
> + }
> +
> + return pkt_count;
> +}
> +
> +static bool __hbl_en_rx_poll_schedule(struct hbl_en_port *port, unsigned long delay)
> +{
> + return queue_delayed_work(port->rx_wq, &port->rx_poll_work, delay);
> +}
> +
> +static void hbl_en_rx_poll_work(struct work_struct *work)
> +{
> + struct hbl_en_port *port = container_of(work, struct hbl_en_port, rx_poll_work.work);
> + struct hbl_en_device *hdev = port->hdev;
> + int pkt_count;
> +
> + pkt_count = hbl_en_handle_rx(port, NAPI_POLL_WEIGHT);
> +
> + /* Reschedule the poll if we have consumed budget which means we still have packets to
> + * process. Else re-enable the Rx IRQs and exit the work.
> + */
> + if (pkt_count < NAPI_POLL_WEIGHT)
> + hdev->asic_funcs.reenable_rx_irq(port);
> + else
> + __hbl_en_rx_poll_schedule(port, 0);
> +}
> +
> +/* Rx poll init and trigger routines are used in event-driven setups where
> + * Rx polling is initialized once during init or open and started/triggered by the event handler.
> + */
> +void hbl_en_rx_poll_trigger_init(struct hbl_en_port *port)
> +{
> + INIT_DELAYED_WORK(&port->rx_poll_work, hbl_en_rx_poll_work);
> +}
> +
> +bool hbl_en_rx_poll_start(struct hbl_en_port *port)
> +{
> + return __hbl_en_rx_poll_schedule(port, msecs_to_jiffies(1));
> +}
> +
> +void hbl_en_rx_poll_stop(struct hbl_en_port *port)
> +{
> + cancel_delayed_work_sync(&port->rx_poll_work);
> +}
> +
> +static int hbl_en_napi_poll(struct napi_struct *napi, int budget)
> +{
> + struct hbl_en_port *port = container_of(napi, struct hbl_en_port, napi);
> + struct hbl_en_device *hdev = port->hdev;
> + int pkt_count;
> +
> + /* exit if we are called by netpoll as we free the Tx ring via EQ (if enabled) */
> + if (!budget)
> + return 0;
> +
> + pkt_count = hbl_en_handle_rx(port, budget);
> +
> + /* If budget not fully consumed, exit the polling mode */
> + if (pkt_count < budget) {
> + napi_complete_done(napi, pkt_count);
I believe this code might be incorrect and that it should be:
if (napi_complete_done(napi, pkt_done))
hdev->asic_funcs.reenable_rx_irq(port);
> + hdev->asic_funcs.reenable_rx_irq(port);
> + }
> +
> + return pkt_count;
> +}
> +
> +static void hbl_en_port_unregister(struct hbl_en_port *port)
> +{
> + struct net_device *ndev = port->ndev;
> +
> + unregister_netdev(ndev);
> + free_netdev(ndev);
> + port->ndev = NULL;
> +}
> +
> +static int hbl_en_set_asic_funcs(struct hbl_en_device *hdev)
> +{
> + switch (hdev->asic_type) {
> + case HBL_ASIC_GAUDI2:
> + default:
> + dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static void hbl_en_handle_eqe(struct hbl_aux_dev *aux_dev, u32 port, struct hbl_cn_eqe *eqe)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> +
> + hdev->asic_funcs.handle_eqe(aux_dev, port, eqe);
> +}
> +
> +static void hbl_en_set_aux_ops(struct hbl_en_device *hdev, bool enable)
> +{
> + struct hbl_en_aux_ops *aux_ops = hdev->aux_dev->aux_ops;
> +
> + if (enable) {
> + aux_ops->ports_reopen = hbl_en_ports_reopen;
> + aux_ops->ports_stop_prepare = hbl_en_ports_stop_prepare;
> + aux_ops->ports_stop = hbl_en_ports_stop;
> + aux_ops->set_port_status = hbl_en_set_port_status;
> + aux_ops->is_port_open = hbl_en_is_port_open;
> + aux_ops->get_src_ip = hbl_en_get_src_ip;
> + aux_ops->reset_stats = hbl_en_reset_stats;
> + aux_ops->get_mtu = hbl_en_get_mtu;
> + aux_ops->get_pflags = hbl_en_get_pflags;
> + aux_ops->set_dev_lpbk = hbl_en_set_dev_lpbk;
> + aux_ops->handle_eqe = hbl_en_handle_eqe;
> + } else {
> + aux_ops->ports_reopen = NULL;
> + aux_ops->ports_stop_prepare = NULL;
> + aux_ops->ports_stop = NULL;
> + aux_ops->set_port_status = NULL;
> + aux_ops->is_port_open = NULL;
> + aux_ops->get_src_ip = NULL;
> + aux_ops->reset_stats = NULL;
> + aux_ops->get_mtu = NULL;
> + aux_ops->get_pflags = NULL;
> + aux_ops->set_dev_lpbk = NULL;
> + aux_ops->handle_eqe = NULL;
> + }
> +}
> +
> +int hbl_en_dev_init(struct hbl_en_device *hdev)
> +{
> + struct hbl_en_asic_funcs *asic_funcs = &hdev->asic_funcs;
> + struct hbl_en_port *port;
> + int rc, i, port_cnt = 0;
> +
> + /* must be called before the call to dev_init() */
> + rc = hbl_en_set_asic_funcs(hdev);
> + if (rc) {
> + dev_err(hdev->dev, "failed to set aux ops\n");
> + return rc;
> + }
> +
> + rc = asic_funcs->dev_init(hdev);
> + if (rc) {
> + dev_err(hdev->dev, "device init failed\n");
> + return rc;
> + }
> +
> + /* init the function pointers here before calling hbl_en_port_register which sets up
> + * net_device_ops, and its ops might start getting called.
> + * If any failure is encountered, these will be made NULL and the core driver won't call
> + * them.
> + */
> + hbl_en_set_aux_ops(hdev, true);
> +
> + /* Port register depends on the above initialization so it must be called here and not
> + * before that.
> + */
> + for (i = 0; i < hdev->max_num_of_ports; i++, port_cnt++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + rc = hbl_en_port_init(port);
> + if (rc) {
> + dev_err(hdev->dev, "port init failed\n");
> + goto unregister_ports;
> + }
> +
> + rc = hbl_en_port_register(port);
> + if (rc) {
> + dev_err(hdev->dev, "port register failed\n");
> +
> + hbl_en_port_fini(port);
> + goto unregister_ports;
> + }
> + }
> +
> + hdev->is_initialized = true;
> +
> + return 0;
> +
> +unregister_ports:
> + for (i = 0; i < port_cnt; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + hbl_en_port_unregister(port);
> + hbl_en_port_fini(port);
> + }
> +
> + hbl_en_set_aux_ops(hdev, false);
> +
> + asic_funcs->dev_fini(hdev);
> +
> + return rc;
> +}
> +
> +void hbl_en_dev_fini(struct hbl_en_device *hdev)
> +{
> + struct hbl_en_asic_funcs *asic_funcs = &hdev->asic_funcs;
> + struct hbl_en_port *port;
> + int i;
> +
> + hdev->in_teardown = true;
> +
> + if (!hdev->is_initialized)
> + return;
> +
> + hdev->is_initialized = false;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + /* It could be this cleanup flow is called after a failed init flow.
> + * Hence we need to check that we indeed have a netdev to unregister.
> + */
> + if (!port->ndev)
> + continue;
> +
> + hbl_en_port_unregister(port);
> + hbl_en_port_fini(port);
> + }
> +
> + hbl_en_set_aux_ops(hdev, false);
> +
> + asic_funcs->dev_fini(hdev);
> +}
> +
> +dma_addr_t hbl_en_dma_map(struct hbl_en_device *hdev, void *addr, int len)
> +{
> + dma_addr_t dma_addr;
> +
> + if (hdev->dma_map_support)
> + dma_addr = dma_map_single(&hdev->pdev->dev, addr, len, DMA_TO_DEVICE);
> + else
> + dma_addr = virt_to_phys(addr);
> +
> + return dma_addr;
> +}
> +
> +void hbl_en_dma_unmap(struct hbl_en_device *hdev, dma_addr_t dma_addr, int len)
> +{
> + if (hdev->dma_map_support)
> + dma_unmap_single(&hdev->pdev->dev, dma_addr, len, DMA_TO_DEVICE);
> +}
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
> new file mode 100644
> index 000000000000..15504c1f3cfb
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
> @@ -0,0 +1,206 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#ifndef HABANALABS_EN_H_
> +#define HABANALABS_EN_H_
> +
> +#include <linux/net/intel/cn.h>
> +
> +#include <linux/netdevice.h>
> +#include <linux/pci.h>
> +
> +#define HBL_EN_NAME "habanalabs_en"
> +
> +#define HBL_EN_PORT(aux_dev, idx) (&(((struct hbl_en_device *)(aux_dev)->priv)->ports[(idx)]))
> +
> +#define hbl_netdev_priv(ndev) \
> +({ \
> + typecheck(struct net_device *, ndev); \
> + *(struct hbl_en_port **)netdev_priv(ndev); \
> +})
> +
> +/**
> + * enum hbl_en_eth_pkt_status - status of Rx Ethernet packet.
> + * ETH_PKT_OK: packet was received successfully.
> + * ETH_PKT_DROP: packet should be dropped.
> + * ETH_PKT_NONE: no available packet.
> + */
> +enum hbl_en_eth_pkt_status {
> + ETH_PKT_OK,
> + ETH_PKT_DROP,
> + ETH_PKT_NONE
> +};
> +
> +/**
> + * struct hbl_en_net_stats - stats of Ethernet interface.
> + * rx_packets: number of packets received.
> + * tx_packets: number of packets sent.
> + * rx_bytes: total bytes of data received.
> + * tx_bytes: total bytes of data sent.
> + * tx_errors: number of errors in the TX.
> + * rx_dropped: number of packets dropped by the RX.
> + * tx_dropped: number of packets dropped by the TX.
> + */
> +struct hbl_en_net_stats {
> + u64 rx_packets;
> + u64 tx_packets;
> + u64 rx_bytes;
> + u64 tx_bytes;
> + u64 tx_errors;
> + atomic64_t rx_dropped;
> + atomic64_t tx_dropped;
> +};
> +
> +/**
> + * struct hbl_en_port - manage port common structure.
> + * @hdev: habanalabs Ethernet device structure.
> + * @ndev: network device.
> + * @rx_wq: WQ for Rx poll when we cannot schedule NAPI poll.
> + * @mac_addr: HW MAC addresses.
> + * @asic_specific: ASIC specific port structure.
> + * @napi: New API structure.
> + * @rx_poll_work: Rx work for polling mode.
> + * @net_stats: statistics of the ethernet interface.
> + * @in_reset: true if the NIC was marked as in reset, false otherwise. Used to avoid an additional
> + * stopping of the NIC if a hard reset was re-initiated.
> + * @pflags: ethtool private flags bit mask.
> + * @idx: index of this specific port.
> + * @rx_max_coalesced_frames: Maximum number of packets to receive before an RX interrupt.
> + * @tx_max_coalesced_frames: Maximum number of packets to be sent before a TX interrupt.
> + * @rx_coalesce_usecs: How many usecs to delay an RX interrupt after a packet arrives.
> + * @is_initialized: true if the port H/W is initialized, false otherwise.
> + * @pfc_enable: true if this port supports Priority Flow Control, false otherwise.
> + * @auto_neg_enable: is autoneg enabled.
> + * @auto_neg_resolved: was autoneg phase finished successfully.
> + */
> +struct hbl_en_port {
> + struct hbl_en_device *hdev;
> + struct net_device *ndev;
> + struct workqueue_struct *rx_wq;
> + char *mac_addr;
> + void *asic_specific;
> + struct napi_struct napi;
> + struct delayed_work rx_poll_work;
> + struct hbl_en_net_stats net_stats;
> + atomic_t in_reset;
> + u32 pflags;
> + u32 idx;
> + u32 rx_max_coalesced_frames;
> + u32 tx_max_coalesced_frames;
> + u16 rx_coalesce_usecs;
> + u8 is_initialized;
> + u8 pfc_enable;
> + u8 auto_neg_enable;
> + u8 auto_neg_resolved;
> +};
> +
> +/**
> + * struct hbl_en_asic_funcs - ASIC specific Ethernet functions.
> + * @dev_init: device init.
> + * @dev_fini: device cleanup.
> + * @reenable_rx_irq: re-enable Rx interrupts.
> + * @eth_port_open: initialize and open the Ethernet port.
> + * @eth_port_close: close the Ethernet port.
> + * @write_pkt_to_hw: write skb to HW.
> + * @read_pkt_from_hw: read pkt from HW.
> + * @get_pfc_cnts: get PFC counters.
> + * @set_coalesce: set Tx/Rx coalesce config in HW.
> + * @get_rx_ring size: get max number of elements the Rx ring can contain.
> + * @handle_eqe: Handle a received event.
> + */
> +struct hbl_en_asic_funcs {
> + int (*dev_init)(struct hbl_en_device *hdev);
> + void (*dev_fini)(struct hbl_en_device *hdev);
> + void (*reenable_rx_irq)(struct hbl_en_port *port);
> + int (*eth_port_open)(struct hbl_en_port *port);
> + void (*eth_port_close)(struct hbl_en_port *port);
> + netdev_tx_t (*write_pkt_to_hw)(struct hbl_en_port *port, struct sk_buff *skb);
> + int (*read_pkt_from_hw)(struct hbl_en_port *port, void **pkt_addr, u32 *pkt_size);
> + void (*get_pfc_cnts)(struct hbl_en_port *port, void *ptr);
> + int (*set_coalesce)(struct hbl_en_port *port);
> + int (*get_rx_ring_size)(struct hbl_en_port *port);
> + void (*handle_eqe)(struct hbl_aux_dev *aux_dev, u32 port_idx, struct hbl_cn_eqe *eqe);
> +};
> +
> +/**
> + * struct hbl_en_device - habanalabs Ethernet device structure.
> + * @pdev: pointer to PCI device.
> + * @dev: related kernel basic device structure.
> + * @ports: array of all ports manage common structures.
> + * @aux_dev: pointer to auxiliary device.
> + * @asic_specific: ASIC specific device structure.
> + * @fw_ver: FW version.
> + * @qsfp_eeprom: QSFPD EEPROM info.
> + * @mac_addr: array of all MAC addresses.
> + * @asic_funcs: ASIC specific Ethernet functions.
> + * @asic_type: ASIC specific type.
> + * @ports_mask: mask of available ports.
> + * @auto_neg_mask: mask of port with Autonegotiation enabled.
> + * @port_reset_timeout: max time in seconds for a port reset flow to finish.
> + * @pending_reset_long_timeout: long timeout for pending hard reset to finish in seconds.
> + * @max_frm_len: maximum allowed frame length.
> + * @raw_elem_size: size of element in raw buffers.
> + * @max_raw_mtu: maximum MTU size for raw packets.
> + * @min_raw_mtu: minimum MTU size for raw packets.
> + * @pad_size: the pad size in bytes for the skb to transmit.
> + * @core_dev_id: core device ID.
> + * @max_num_of_ports: max number of available ports;
> + * @in_reset: is the entire NIC currently under reset.
> + * @poll_enable: Enable Rx polling rather than IRQ + NAPI.
> + * @in_teardown: true if the NIC is in teardown (during device remove).
> + * @is_initialized: was the device initialized successfully.
> + * @has_eq: true if event queue is supported.
> + * @dma_map_support: HW supports DMA mapping.
> + */
> +struct hbl_en_device {
> + struct pci_dev *pdev;
> + struct device *dev;
> + struct hbl_en_port *ports;
> + struct hbl_aux_dev *aux_dev;
> + void *asic_specific;
> + char *fw_ver;
> + char *qsfp_eeprom;
> + char *mac_addr;
> + struct hbl_en_asic_funcs asic_funcs;
> + enum hbl_cn_asic_type asic_type;
> + u64 ports_mask;
> + u64 auto_neg_mask;
> + u32 port_reset_timeout;
> + u32 pending_reset_long_timeout;
> + u32 max_frm_len;
> + u32 raw_elem_size;
> + u16 max_raw_mtu;
> + u16 min_raw_mtu;
> + u16 pad_size;
> + u16 core_dev_id;
> + u8 max_num_of_ports;
> + u8 in_reset;
> + u8 poll_enable;
> + u8 in_teardown;
> + u8 is_initialized;
> + u8 has_eq;
> + u8 dma_map_support;
> +};
> +
> +int hbl_en_dev_init(struct hbl_en_device *hdev);
> +void hbl_en_dev_fini(struct hbl_en_device *hdev);
> +
> +const struct ethtool_ops *hbl_en_ethtool_get_ops(struct net_device *ndev);
> +void hbl_en_ethtool_init_coalesce(struct hbl_en_port *port);
> +
> +extern const struct dcbnl_rtnl_ops hbl_en_dcbnl_ops;
> +
> +bool hbl_en_rx_poll_start(struct hbl_en_port *port);
> +void hbl_en_rx_poll_stop(struct hbl_en_port *port);
> +void hbl_en_rx_poll_trigger_init(struct hbl_en_port *port);
> +int hbl_en_port_reset(struct hbl_en_port *port);
> +int hbl_en_port_reset_locked(struct hbl_aux_dev *aux_dev, u32 port_idx);
> +int hbl_en_handle_rx(struct hbl_en_port *port, int budget);
> +dma_addr_t hbl_en_dma_map(struct hbl_en_device *hdev, void *addr, int len);
> +void hbl_en_dma_unmap(struct hbl_en_device *hdev, dma_addr_t dma_addr, int len);
> +
> +#endif /* HABANALABS_EN_H_ */
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c
> new file mode 100644
> index 000000000000..5d718579a2b6
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c
> @@ -0,0 +1,101 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#include "hbl_en.h"
> +
> +#define PFC_PRIO_MASK_ALL GENMASK(HBL_EN_PFC_PRIO_NUM - 1, 0)
> +#define PFC_PRIO_MASK_NONE 0
> +
> +#ifdef CONFIG_DCB
> +static int hbl_en_dcbnl_ieee_getpfc(struct net_device *netdev, struct ieee_pfc *pfc)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + struct hbl_en_device *hdev;
> + u32 port_idx;
> +
> + hdev = port->hdev;
> + port_idx = port->idx;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + dev_dbg_ratelimited(hdev->dev, "port %d is in reset, can't get PFC", port_idx);
> + return -EBUSY;
> + }
> +
> + pfc->pfc_en = port->pfc_enable ? PFC_PRIO_MASK_ALL : PFC_PRIO_MASK_NONE;
> + pfc->pfc_cap = HBL_EN_PFC_PRIO_NUM;
> +
> + hdev->asic_funcs.get_pfc_cnts(port, pfc);
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return 0;
> +}
> +
> +static int hbl_en_dcbnl_ieee_setpfc(struct net_device *netdev, struct ieee_pfc *pfc)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + struct hbl_en_device *hdev;
> + u8 curr_pfc_en;
> + u32 port_idx;
> + int rc = 0;
> +
> + hdev = port->hdev;
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> + port_idx = port->idx;
> +
> + if (pfc->pfc_en & ~PFC_PRIO_MASK_ALL) {
> + dev_dbg_ratelimited(hdev->dev, "PFC supports %d priorities only, port %d\n",
> + HBL_EN_PFC_PRIO_NUM, port_idx);
> + return -EINVAL;
> + }
> +
> + if (pfc->pfc_en != PFC_PRIO_MASK_NONE && pfc->pfc_en != PFC_PRIO_MASK_ALL) {
> + dev_dbg_ratelimited(hdev->dev,
> + "PFC should be enabled/disabled on all priorities, port %d\n",
> + port_idx);
> + return -EINVAL;
> + }
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + dev_dbg_ratelimited(hdev->dev, "port %d is in reset, can't set PFC", port_idx);
> + return -EBUSY;
> + }
> +
> + curr_pfc_en = port->pfc_enable ? PFC_PRIO_MASK_ALL : PFC_PRIO_MASK_NONE;
> +
> + if (pfc->pfc_en == curr_pfc_en)
> + goto out;
> +
> + port->pfc_enable = !port->pfc_enable;
> +
> + rc = aux_ops->set_pfc(aux_dev, port_idx, port->pfc_enable);
> +
> +out:
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +static u8 hbl_en_dcbnl_getdcbx(struct net_device *netdev)
> +{
> + return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
> +}
> +
> +static u8 hbl_en_dcbnl_setdcbx(struct net_device *netdev, u8 mode)
> +{
> + return !(mode == (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE));
> +}
> +
> +const struct dcbnl_rtnl_ops hbl_en_dcbnl_ops = {
> + .ieee_getpfc = hbl_en_dcbnl_ieee_getpfc,
> + .ieee_setpfc = hbl_en_dcbnl_ieee_setpfc,
> + .getdcbx = hbl_en_dcbnl_getdcbx,
> + .setdcbx = hbl_en_dcbnl_setdcbx
> +};
> +#endif
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c
> new file mode 100644
> index 000000000000..23a87d36ded5
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c
> @@ -0,0 +1,211 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#define pr_fmt(fmt) "habanalabs_en: " fmt
> +
> +#include "hbl_en.h"
> +
> +#include <linux/module.h>
> +#include <linux/auxiliary_bus.h>
> +
> +#define HBL_DRIVER_AUTHOR "HabanaLabs Kernel Driver Team"
> +
> +#define HBL_DRIVER_DESC "HabanaLabs AI accelerators Ethernet driver"
> +
> +MODULE_AUTHOR(HBL_DRIVER_AUTHOR);
> +MODULE_DESCRIPTION(HBL_DRIVER_DESC);
> +MODULE_LICENSE("GPL");
> +
> +static bool poll_enable;
> +
> +module_param(poll_enable, bool, 0444);
> +MODULE_PARM_DESC(poll_enable,
> + "Enable Rx polling rather than IRQ + NAPI (0 = no, 1 = yes, default: no)");
> +
> +static int hdev_init(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_aux_data *aux_data = aux_dev->aux_data;
> + struct hbl_en_port *ports, *port;
> + struct hbl_en_device *hdev;
> + int rc, i;
> +
> + hdev = kzalloc(sizeof(*hdev), GFP_KERNEL);
> + if (!hdev)
> + return -ENOMEM;
> +
> + ports = kcalloc(aux_data->max_num_of_ports, sizeof(*ports), GFP_KERNEL);
> + if (!ports) {
> + rc = -ENOMEM;
> + goto ports_alloc_fail;
> + }
> +
> + aux_dev->priv = hdev;
> + hdev->aux_dev = aux_dev;
> + hdev->ports = ports;
> + hdev->pdev = aux_data->pdev;
> + hdev->dev = aux_data->dev;
> + hdev->ports_mask = aux_data->ports_mask;
> + hdev->auto_neg_mask = aux_data->auto_neg_mask;
> + hdev->max_num_of_ports = aux_data->max_num_of_ports;
> + hdev->core_dev_id = aux_data->id;
> + hdev->fw_ver = aux_data->fw_ver;
> + hdev->qsfp_eeprom = aux_data->qsfp_eeprom;
> + hdev->asic_type = aux_data->asic_type;
> + hdev->pending_reset_long_timeout = aux_data->pending_reset_long_timeout;
> + hdev->max_frm_len = aux_data->max_frm_len;
> + hdev->raw_elem_size = aux_data->raw_elem_size;
> + hdev->max_raw_mtu = aux_data->max_raw_mtu;
> + hdev->min_raw_mtu = aux_data->min_raw_mtu;
> + hdev->pad_size = ETH_ZLEN;
> + hdev->has_eq = aux_data->has_eq;
> + hdev->dma_map_support = true;
> + hdev->poll_enable = poll_enable;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> + port->hdev = hdev;
> + port->idx = i;
> + port->pfc_enable = true;
> + port->pflags = PFLAGS_PCS_LINK_CHECK | PFLAGS_PHY_AUTO_NEG_LPBK;
> + port->mac_addr = aux_data->mac_addr[i];
> + port->auto_neg_enable = !!(aux_data->auto_neg_mask & BIT(i));
> + }
> +
> + return 0;
> +
> +ports_alloc_fail:
> + kfree(hdev);
> +
> + return rc;
> +}
> +
> +static void hdev_fini(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> +
> + kfree(hdev->ports);
> + kfree(hdev);
> + aux_dev->priv = NULL;
> +}
> +
> +static const struct auxiliary_device_id hbl_en_id_table[] = {
> + { .name = "habanalabs_cn.en", },
> + {},
> +};
> +
> +MODULE_DEVICE_TABLE(auxiliary, hbl_en_id_table);
> +
> +static int hbl_en_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
> +{
> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
> + struct hbl_en_aux_ops *aux_ops = aux_dev->aux_ops;
> + struct hbl_en_device *hdev;
> + ktime_t timeout;
> + int rc;
> +
> + rc = hdev_init(aux_dev);
> + if (rc) {
> + dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
> + return -EIO;
> + }
> +
> + hdev = aux_dev->priv;
> +
> + /* don't allow module unloading while it is attached */
> + if (!try_module_get(THIS_MODULE)) {
> + dev_err(hdev->dev, "Failed to increment %s module refcount\n", HBL_EN_NAME);
> + rc = -EIO;
> + goto module_get_err;
> + }
> +
> + timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
> + while (1) {
> + aux_ops->hw_access_lock(aux_dev);
> +
> + /* if the device is operational, proceed to actual init while holding the lock in
> + * order to prevent concurrent hard reset
> + */
> + if (aux_ops->device_operational(aux_dev))
> + break;
> +
> + aux_ops->hw_access_unlock(aux_dev);
> +
> + if (ktime_compare(ktime_get(), timeout) > 0) {
> + dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
> + rc = -EBUSY;
> + goto timeout_err;
> + }
> +
> + dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing en\n");
> +
> + msleep_interruptible(MSEC_PER_SEC);
> + }
> +
> + rc = hbl_en_dev_init(hdev);
> + if (rc) {
> + dev_err(hdev->dev, "Failed to init en device\n");
> + goto dev_init_err;
> + }
> +
> + aux_ops->hw_access_unlock(aux_dev);
> +
> + return 0;
> +
> +dev_init_err:
> + aux_ops->hw_access_unlock(aux_dev);
> +timeout_err:
> + module_put(THIS_MODULE);
> +module_get_err:
> + hdev_fini(aux_dev);
> +
> + return rc;
> +}
> +
> +/* This function can be called only from the CN driver when deleting the aux bus, because we
> + * incremented the module refcount on probing. Hence no need to protect here from hard reset.
> + */
> +static void hbl_en_remove(struct auxiliary_device *adev)
> +{
> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
> + struct hbl_en_device *hdev = aux_dev->priv;
> +
> + if (!hdev)
> + return;
> +
> + hbl_en_dev_fini(hdev);
> +
> + /* allow module unloading as now it is detached */
> + module_put(THIS_MODULE);
> +
> + hdev_fini(aux_dev);
> +}
> +
> +static struct auxiliary_driver hbl_en_driver = {
> + .name = "eth",
> + .probe = hbl_en_probe,
> + .remove = hbl_en_remove,
> + .id_table = hbl_en_id_table,
> +};
> +
> +static int __init hbl_en_init(void)
> +{
> + pr_info("loading driver\n");
> +
> + return auxiliary_driver_register(&hbl_en_driver);
> +}
> +
> +static void __exit hbl_en_exit(void)
> +{
> + auxiliary_driver_unregister(&hbl_en_driver);
> +
> + pr_info("driver removed\n");
> +}
> +
> +module_init(hbl_en_init);
> +module_exit(hbl_en_exit);
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c
> new file mode 100644
> index 000000000000..1d14d283409b
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c
> @@ -0,0 +1,452 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#include "hbl_en.h"
> +#include <linux/ethtool.h>
> +
> +#define RX_COALESCED_FRAMES_MIN 1
> +#define TX_COALESCED_FRAMES_MIN 1
> +#define TX_COALESCED_FRAMES_MAX 10
> +
> +static const char pflags_str[][ETH_GSTRING_LEN] = {
> + "pcs-link-check",
> + "phy-auto-neg-lpbk",
> +};
> +
> +#define NIC_STAT(m) {#m, offsetof(struct hbl_en_port, net_stats.m)}
> +
> +static struct hbl_cn_stat netdev_eth_stats[] = {
> + NIC_STAT(rx_packets),
> + NIC_STAT(tx_packets),
> + NIC_STAT(rx_bytes),
> + NIC_STAT(tx_bytes),
> + NIC_STAT(tx_errors),
> + NIC_STAT(rx_dropped),
> + NIC_STAT(tx_dropped)
> +};
> +
> +static size_t pflags_str_len = ARRAY_SIZE(pflags_str);
> +static size_t netdev_eth_stats_len = ARRAY_SIZE(netdev_eth_stats);
> +
> +static void hbl_en_ethtool_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *drvinfo)
> +{
> + struct hbl_en_device *hdev;
> + struct hbl_en_port *port;
> +
> + port = hbl_netdev_priv(ndev);
> + hdev = port->hdev;
> +
> + strscpy(drvinfo->driver, HBL_EN_NAME, sizeof(drvinfo->driver));
> + strscpy(drvinfo->fw_version, hdev->fw_ver, sizeof(drvinfo->fw_version));
> + strscpy(drvinfo->bus_info, pci_name(hdev->pdev), sizeof(drvinfo->bus_info));
> +}
> +
> +static int hbl_en_ethtool_get_module_info(struct net_device *ndev, struct ethtool_modinfo *modinfo)
> +{
> + modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
> + modinfo->type = ETH_MODULE_SFF_8636;
> +
> + return 0;
> +}
> +
> +static int hbl_en_ethtool_get_module_eeprom(struct net_device *ndev, struct ethtool_eeprom *ee,
> + u8 *data)
> +{
> + struct hbl_en_device *hdev;
> + struct hbl_en_port *port;
> + u32 first, last, len;
> + u8 *qsfp_eeprom;
> +
> + port = hbl_netdev_priv(ndev);
> + hdev = port->hdev;
> + qsfp_eeprom = hdev->qsfp_eeprom;
> +
> + if (ee->len == 0)
> + return -EINVAL;
> +
> + first = ee->offset;
> + last = ee->offset + ee->len;
> +
> + if (first < ETH_MODULE_SFF_8636_LEN) {
> + len = min_t(unsigned int, last, ETH_MODULE_SFF_8079_LEN);
> + len -= first;
> +
> + memcpy(data, qsfp_eeprom + first, len);
> + }
> +
> + return 0;
> +}
> +
> +static u32 hbl_en_ethtool_get_priv_flags(struct net_device *ndev)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> +
> + return port->pflags;
> +}
> +
> +static int hbl_en_ethtool_set_priv_flags(struct net_device *ndev, u32 priv_flags)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> +
> + port->pflags = priv_flags;
> +
> + return 0;
> +}
> +
> +static int hbl_en_ethtool_get_link_ksettings(struct net_device *ndev,
> + struct ethtool_link_ksettings *cmd)
> +{
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + struct hbl_en_device *hdev;
> + struct hbl_en_port *port;
> + u32 port_idx, speed;
> +
> + port = hbl_netdev_priv(ndev);
> + hdev = port->hdev;
> + port_idx = port->idx;
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> + speed = aux_ops->get_speed(aux_dev, port_idx);
> +
> + cmd->base.speed = speed;
> + cmd->base.duplex = DUPLEX_FULL;
> +
> + ethtool_link_ksettings_zero_link_mode(cmd, supported);
> + ethtool_link_ksettings_zero_link_mode(cmd, advertising);
> +
> + switch (speed) {
> + case SPEED_100000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseSR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseKR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseLR4_ER4_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseSR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseKR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseLR4_ER4_Full);
> +
> + cmd->base.port = PORT_FIBRE;
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Backplane);
> + break;
> + case SPEED_50000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseSR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseCR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseKR2_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseSR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseCR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseKR2_Full);
> + break;
> + case SPEED_25000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 25000baseCR_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 25000baseCR_Full);
> + break;
> + case SPEED_200000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 200000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 200000baseKR4_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 200000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 200000baseKR4_Full);
> + break;
> + case SPEED_400000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 400000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 400000baseKR4_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 400000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 400000baseKR4_Full);
> + break;
> + default:
> + netdev_err(port->ndev, "unknown speed %d\n", speed);
> + return -EFAULT;
> + }
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
> +
> + if (port->auto_neg_enable) {
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
> + cmd->base.autoneg = AUTONEG_ENABLE;
> + if (port->auto_neg_resolved)
> + ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
> + } else {
> + cmd->base.autoneg = AUTONEG_DISABLE;
> + }
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
> +
> + if (port->pfc_enable)
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause);
> +
> + return 0;
> +}
> +
> +/* only autoneg is mutable */
> +static bool check_immutable_ksettings(const struct ethtool_link_ksettings *old_cmd,
> + const struct ethtool_link_ksettings *new_cmd)
> +{
> + return (old_cmd->base.speed == new_cmd->base.speed) &&
> + (old_cmd->base.duplex == new_cmd->base.duplex) &&
> + (old_cmd->base.port == new_cmd->base.port) &&
> + (old_cmd->base.phy_address == new_cmd->base.phy_address) &&
> + (old_cmd->base.eth_tp_mdix_ctrl == new_cmd->base.eth_tp_mdix_ctrl) &&
> + bitmap_equal(old_cmd->link_modes.advertising, new_cmd->link_modes.advertising,
> + __ETHTOOL_LINK_MODE_MASK_NBITS);
> +}
> +
> +static int
> +hbl_en_ethtool_set_link_ksettings(struct net_device *ndev, const struct ethtool_link_ksettings *cmd)
> +{
> + struct ethtool_link_ksettings curr_cmd;
> + struct hbl_en_device *hdev;
> + struct hbl_en_port *port;
> + bool auto_neg;
> + u32 port_idx;
> + int rc;
> +
> + port = hbl_netdev_priv(ndev);
> + hdev = port->hdev;
> + port_idx = port->idx;
> +
> + memset(&curr_cmd, 0, sizeof(struct ethtool_link_ksettings));
> +
> + rc = hbl_en_ethtool_get_link_ksettings(ndev, &curr_cmd);
> + if (rc)
> + return rc;
> +
> + if (!check_immutable_ksettings(&curr_cmd, cmd))
> + return -EOPNOTSUPP;
> +
> + auto_neg = cmd->base.autoneg == AUTONEG_ENABLE;
> +
> + if (port->auto_neg_enable == auto_neg)
> + return 0;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(port->ndev, "port is in reset, can't update settings\n");
> + return -EBUSY;
> + }
> +
> + if (auto_neg && !(hdev->auto_neg_mask & BIT(port_idx))) {
> + netdev_err(port->ndev, "port autoneg is disabled by BMC\n");
> + rc = -EFAULT;
> + goto out;
> + }
> +
> + port->auto_neg_enable = auto_neg;
> +
> + if (netif_running(port->ndev)) {
> + rc = hbl_en_port_reset(port);
> + if (rc)
> + netdev_err(port->ndev, "Failed to reset port for settings update, rc %d\n",
> + rc);
> + }
> +
> +out:
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +static int hbl_en_ethtool_get_sset_count(struct net_device *ndev, int sset)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + switch (sset) {
> + case ETH_SS_STATS:
> + return netdev_eth_stats_len + aux_ops->get_cnts_num(aux_dev, port_idx);
> + case ETH_SS_PRIV_FLAGS:
> + return pflags_str_len;
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static void hbl_en_ethtool_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int i;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + switch (stringset) {
> + case ETH_SS_STATS:
> + for (i = 0; i < netdev_eth_stats_len; i++)
> + ethtool_puts(&data, netdev_eth_stats[i].str);
> +
> + aux_ops->get_cnts_names(aux_dev, port_idx, data);
> + break;
> + case ETH_SS_PRIV_FLAGS:
> + for (i = 0; i < pflags_str_len; i++)
> + ethtool_puts(&data, pflags_str[i]);
> + break;
> + }
> +}
> +
> +static void hbl_en_ethtool_get_ethtool_stats(struct net_device *ndev,
> + __always_unused struct ethtool_stats *stats, u64 *data)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + struct hbl_en_device *hdev;
> + u32 port_idx;
> + char *p;
> + int i;
> +
> + hdev = port->hdev;
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> + port_idx = port->idx;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + dev_info_ratelimited(hdev->dev, "port %d is in reset, can't get ethtool stats",
> + port_idx);
> + return;
> + }
> +
> + /* Even though the Ethernet Rx/Tx flow might update the stats in parallel, there is not an
> + * absolute need for synchronisation. This is because, missing few counts of these stats is
> + * much better than adding a lock to synchronize and increase the overhead of the Rx/Tx
> + * flows. In worst case scenario, reader will get stale stats. He will receive updated
> + * stats in next read.
> + */
> + for (i = 0; i < netdev_eth_stats_len; i++) {
> + p = (char *)port + netdev_eth_stats[i].lo_offset;
> + data[i] = *(u32 *)p;
> + }
> +
> + data += i;
> +
> + aux_ops->get_cnts_values(aux_dev, port_idx, data);
> +
> + atomic_set(&port->in_reset, 0);
> +}
> +
> +static int hbl_en_ethtool_get_coalesce(struct net_device *ndev,
> + struct ethtool_coalesce *coal,
> + struct kernel_ethtool_coalesce *kernel_coal,
> + struct netlink_ext_ack *extack)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + aux_ops->ctrl_lock(aux_dev, port_idx);
> +
> + coal->tx_max_coalesced_frames = port->tx_max_coalesced_frames;
> + coal->rx_coalesce_usecs = port->rx_coalesce_usecs;
> + coal->rx_max_coalesced_frames = port->rx_max_coalesced_frames;
> +
> + aux_ops->ctrl_unlock(aux_dev, port_idx);
> +
> + return 0;
> +}
> +
> +static int hbl_en_ethtool_set_coalesce(struct net_device *ndev,
> + struct ethtool_coalesce *coal,
> + struct kernel_ethtool_coalesce *kernel_coal,
> + struct netlink_ext_ack *extack)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int rc, rx_ring_size;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(port->ndev, "port is in reset, can't update settings\n");
> + return -EBUSY;
> + }
> +
> + if (coal->tx_max_coalesced_frames < TX_COALESCED_FRAMES_MIN ||
> + coal->tx_max_coalesced_frames > TX_COALESCED_FRAMES_MAX) {
> + netdev_err(ndev, "tx max_coalesced_frames should be between %d and %d\n",
> + TX_COALESCED_FRAMES_MIN, TX_COALESCED_FRAMES_MAX);
> + rc = -EINVAL;
> + goto atomic_out;
> + }
> +
> + rx_ring_size = hdev->asic_funcs.get_rx_ring_size(port);
> + if (coal->rx_max_coalesced_frames < RX_COALESCED_FRAMES_MIN ||
> + coal->rx_max_coalesced_frames >= rx_ring_size) {
> + netdev_err(ndev, "rx max_coalesced_frames should be between %d and %d\n",
> + RX_COALESCED_FRAMES_MIN, rx_ring_size);
> + rc = -EINVAL;
> + goto atomic_out;
> + }
> +
> + aux_ops->ctrl_lock(aux_dev, port_idx);
> +
> + port->tx_max_coalesced_frames = coal->tx_max_coalesced_frames;
> + port->rx_coalesce_usecs = coal->rx_coalesce_usecs;
> + port->rx_max_coalesced_frames = coal->rx_max_coalesced_frames;
> +
> + rc = hdev->asic_funcs.set_coalesce(port);
> +
> + aux_ops->ctrl_unlock(aux_dev, port_idx);
> +
> +atomic_out:
> + atomic_set(&port->in_reset, 0);
> + return rc;
> +}
> +
> +void hbl_en_ethtool_init_coalesce(struct hbl_en_port *port)
> +{
> + port->rx_coalesce_usecs = CQ_ARM_TIMEOUT_USEC;
> + port->rx_max_coalesced_frames = 1;
> + port->tx_max_coalesced_frames = 1;
> +}
> +
> +static const struct ethtool_ops hbl_en_ethtool_ops_coalesce = {
> + .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | ETHTOOL_COALESCE_RX_MAX_FRAMES |
> + ETHTOOL_COALESCE_TX_MAX_FRAMES,
> + .get_drvinfo = hbl_en_ethtool_get_drvinfo,
> + .get_link = ethtool_op_get_link,
> + .get_module_info = hbl_en_ethtool_get_module_info,
> + .get_module_eeprom = hbl_en_ethtool_get_module_eeprom,
> + .get_priv_flags = hbl_en_ethtool_get_priv_flags,
> + .set_priv_flags = hbl_en_ethtool_set_priv_flags,
> + .get_link_ksettings = hbl_en_ethtool_get_link_ksettings,
> + .set_link_ksettings = hbl_en_ethtool_set_link_ksettings,
> + .get_sset_count = hbl_en_ethtool_get_sset_count,
> + .get_strings = hbl_en_ethtool_get_strings,
> + .get_ethtool_stats = hbl_en_ethtool_get_ethtool_stats,
> + .get_coalesce = hbl_en_ethtool_get_coalesce,
> + .set_coalesce = hbl_en_ethtool_set_coalesce,
> +};
> +
> +const struct ethtool_ops *hbl_en_ethtool_get_ops(struct net_device *ndev)
> +{
> + return &hbl_en_ethtool_ops_coalesce;
> +}
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-14 22:48 ` Joe Damato
@ 2024-06-16 1:04 ` Andrew Lunn
2024-06-18 19:37 ` Omer Shpigelman
1 sibling, 0 replies; 108+ messages in thread
From: Andrew Lunn @ 2024-06-16 1:04 UTC (permalink / raw)
To: Joe Damato, Omer Shpigelman, linux-kernel, linux-rdma, netdev,
dri-devel, ogabbay, zyehudai
On Fri, Jun 14, 2024 at 03:48:43PM -0700, Joe Damato wrote:
> On Thu, Jun 13, 2024 at 11:22:02AM +0300, Omer Shpigelman wrote:
> > This ethernet driver is initialized via auxiliary bus by the hbl_cn
> > driver.
> > It serves mainly for control operations that are needed for AI scaling.
> >
> > Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> > Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> > Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> > Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> > Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> > Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> > Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> > Co-developed-by: David Meriin <dmeriin@habana.ai>
> > Signed-off-by: David Meriin <dmeriin@habana.ai>
> > Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> > Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> > Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Hi Joe
Please trim emails to include just the relevant context when
replying. It is hard to see your comments, and so it is likely some
will be missed, and you will need to make the same comment on v2.
Andrew
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-14 22:48 ` Joe Damato
2024-06-16 1:04 ` Andrew Lunn
@ 2024-06-18 19:37 ` Omer Shpigelman
2024-06-18 21:19 ` Stephen Hemminger
1 sibling, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-18 19:37 UTC (permalink / raw)
To: Joe Damato, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On 6/15/24 01:48, Joe Damato wrote:
> [You don't often get email from jdamato@fastly.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On Thu, Jun 13, 2024 at 11:22:02AM +0300, Omer Shpigelman wrote:
>> This ethernet driver is initialized via auxiliary bus by the hbl_cn
>> driver.
>> It serves mainly for control operations that are needed for AI scaling.
>>
>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
>> Co-developed-by: David Meriin <dmeriin@habana.ai>
>> Signed-off-by: David Meriin <dmeriin@habana.ai>
>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
<...>
>> + if (hdev->poll_enable)
>> + skb = __netdev_alloc_skb_ip_align(ndev, pkt_size, GFP_KERNEL);
>> + else
>> + skb = napi_alloc_skb(&port->napi, pkt_size);
>> +
>> + if (!skb) {
>> + atomic64_inc(&port->net_stats.rx_dropped);
>
> It seems like buffer exhaustion (!skb) would be rx_missed_errors?
>
> The documentation in include/uapi/linux/if_link.h:
>
> * @rx_dropped: Number of packets received but not processed,
> * e.g. due to lack of resources or unsupported protocol.
> * For hardware interfaces this counter may include packets discarded
> * due to L2 address filtering but should not include packets dropped
> * by the device due to buffer exhaustion which are counted separately in
> * @rx_missed_errors (since procfs folds those two counters together).
>
> But, I don't know much about your hardware so I could be wrong.
>
Per my understanding rx_dropped should be used here. According the doc you
posted, rx_dropped should be used in case of dropped packets due to lack
of resources, while rx_missed_errors should be used for packets that were
dropped by the device due to buffer exhaustion, not by the driver.
Please correct me if I misunderstood something.
>> + break;
>> + }
>> +
>> + skb_copy_to_linear_data(skb, pkt_addr, pkt_size);
>> + skb_put(skb, pkt_size);
>> +
>> + if (is_pkt_swap_enabled(hdev))
>> + dump_swap_pkt(port, skb);
>> +
>> + skb->protocol = eth_type_trans(skb, ndev);
>> +
>> + /* Zero the packet buffer memory to avoid leak in case of wrong
>> + * size is used when next packet populates the same memory
>> + */
>> + memset(pkt_addr, 0, pkt_size);
>> +
>> + /* polling is done in thread context and hence BH should be disabled */
>> + if (hdev->poll_enable)
>> + local_bh_disable();
>> +
>> + rc = netif_receive_skb(skb);
>
> Is there any reason in particular to call netif_receive_skb instead of
> napi_gro_receive ?
>
As you can see, we also support polling mode which is a non-NAPI flow.
We could use napi_gro_receive() for NAPI flow and netif_receive_skb() for
polling mode but we don't support RX checksum offload anyway.
>> +
>> + if (hdev->poll_enable)
>> + local_bh_enable();
<...>
>> + pkt_count = hbl_en_handle_rx(port, budget);
>> +
>> + /* If budget not fully consumed, exit the polling mode */
>> + if (pkt_count < budget) {
>> + napi_complete_done(napi, pkt_count);
>
> I believe this code might be incorrect and that it should be:
>
> if (napi_complete_done(napi, pkt_done))
> hdev->asic_funcs.reenable_rx_irq(port);
>
Thanks, I'll add the condition.
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-18 19:37 ` Omer Shpigelman
@ 2024-06-18 21:19 ` Stephen Hemminger
2024-06-19 12:13 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Stephen Hemminger @ 2024-06-18 21:19 UTC (permalink / raw)
To: Omer Shpigelman
Cc: Joe Damato, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On Tue, 18 Jun 2024 19:37:36 +0000
Omer Shpigelman <oshpigelman@habana.ai> wrote:
> >
> > Is there any reason in particular to call netif_receive_skb instead of
> > napi_gro_receive ?
> >
>
> As you can see, we also support polling mode which is a non-NAPI flow.
> We could use napi_gro_receive() for NAPI flow and netif_receive_skb() for
> polling mode but we don't support RX checksum offload anyway.
Why non-NAPI? I thought current netdev policy was all drivers should
use NAPI.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-18 21:19 ` Stephen Hemminger
@ 2024-06-19 12:13 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-19 12:13 UTC (permalink / raw)
To: Stephen Hemminger
Cc: Joe Damato, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On 6/19/24 00:19, Stephen Hemminger wrote:
> On Tue, 18 Jun 2024 19:37:36 +0000
> Omer Shpigelman <oshpigelman@habana.ai> wrote:
>
>>>
>>> Is there any reason in particular to call netif_receive_skb instead of
>>> napi_gro_receive ?
>>>
>>
>> As you can see, we also support polling mode which is a non-NAPI flow.
>> We could use napi_gro_receive() for NAPI flow and netif_receive_skb() for
>> polling mode but we don't support RX checksum offload anyway.
>
> Why non-NAPI? I thought current netdev policy was all drivers should
> use NAPI.
If that's the current policy then I can remove this non-NAPI mode.
I see on another thread that module parameters are not allowed so
apparently I'll need to remove this polling mode anyway as it is set by a
module parameter.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-13 8:22 ` [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver Omer Shpigelman
2024-06-13 21:49 ` Andrew Lunn
2024-06-14 22:48 ` Joe Damato
@ 2024-06-15 0:10 ` Stephen Hemminger
2024-06-19 12:07 ` Omer Shpigelman
2024-06-15 0:16 ` Stephen Hemminger
` (2 subsequent siblings)
5 siblings, 1 reply; 108+ messages in thread
From: Stephen Hemminger @ 2024-06-15 0:10 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel, linux-rdma, netdev, dri-devel, ogabbay, zyehudai
On Thu, 13 Jun 2024 11:22:02 +0300
Omer Shpigelman <oshpigelman@habana.ai> wrote:
> +static int hbl_en_ports_reopen(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> + struct hbl_en_port *port;
> + int rc = 0, i;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + /* It could be that the port was shutdown by 'ip link set down' and there is no need
> + * in reopening it.
> + * Since we mark the ports as in reset even if they are disabled, we clear the flag
> + * here anyway.
> + * See hbl_en_ports_stop_prepare() for more info.
> + */
> + if (!netif_running(port->ndev)) {
> + atomic_set(&port->in_reset, 0);
> + continue;
> + }
> +
Rather than duplicating network device state in your own flags, it would be better to use
existing infrastructure. Read Documentation/networking/operstates.rst
Then you could also get rid of the kludge timer stuff in hbl_en_close().
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-15 0:10 ` Stephen Hemminger
@ 2024-06-19 12:07 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-19 12:07 UTC (permalink / raw)
To: Stephen Hemminger
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/15/24 03:10, Stephen Hemminger wrote:
> [You don't often get email from stephen@networkplumber.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On Thu, 13 Jun 2024 11:22:02 +0300
> Omer Shpigelman <oshpigelman@habana.ai> wrote:
>
>> +static int hbl_en_ports_reopen(struct hbl_aux_dev *aux_dev)
>> +{
>> + struct hbl_en_device *hdev = aux_dev->priv;
>> + struct hbl_en_port *port;
>> + int rc = 0, i;
>> +
>> + for (i = 0; i < hdev->max_num_of_ports; i++) {
>> + if (!(hdev->ports_mask & BIT(i)))
>> + continue;
>> +
>> + port = &hdev->ports[i];
>> +
>> + /* It could be that the port was shutdown by 'ip link set down' and there is no need
>> + * in reopening it.
>> + * Since we mark the ports as in reset even if they are disabled, we clear the flag
>> + * here anyway.
>> + * See hbl_en_ports_stop_prepare() for more info.
>> + */
>> + if (!netif_running(port->ndev)) {
>> + atomic_set(&port->in_reset, 0);
>> + continue;
>> + }
>> +
>
> Rather than duplicating network device state in your own flags, it would be better to use
> existing infrastructure. Read Documentation/networking/operstates.rst
>
> Then you could also get rid of the kludge timer stuff in hbl_en_close().
>
I think that additional explanation is needed here.
In addition to netdev flows, we also support an internal reset flow
(that's what the in_reset boolean indicates).
Our NIC driver is an extension of the compute driver (they share the same
HW) and a reset flow might be needed due to some compute operation which
is entirely unrelated to the NIC driver. But we must not access the HW
while this reset flow is executed.
Note that this internal reset flow originates from the compute driver and
hence we might have parallel netdev operations that should be blocked
meanwhile.
The internal reset flow has 2 phases - teardown and re-init. This reopen
function is called during the re-init phase to restore the NIC ports, but
only if they were actually opened prior to the reset flow.
Regarding hbl_en_close() - during the port close we need to write to the
HW so due to the explanation above, also there we should wait for an
existing internal reset flow to finish first.
Let me know if that's clear enough and addresses your concerns.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-13 8:22 ` [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver Omer Shpigelman
` (2 preceding siblings ...)
2024-06-15 0:10 ` Stephen Hemminger
@ 2024-06-15 0:16 ` Stephen Hemminger
2024-06-18 19:39 ` Omer Shpigelman
2024-06-15 10:55 ` Zhu Yanjun
2024-06-15 17:13 ` Zhu Yanjun
5 siblings, 1 reply; 108+ messages in thread
From: Stephen Hemminger @ 2024-06-15 0:16 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel, linux-rdma, netdev, dri-devel, ogabbay, zyehudai
> +
> +/* get the src IP as it is done in devinet_ioctl() */
> +static int hbl_en_get_src_ip(struct hbl_aux_dev *aux_dev, u32 port_idx, u32 *src_ip)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> + struct net_device *ndev = port->ndev;
> + struct in_device *in_dev;
> + struct in_ifaddr *ifa;
> + int rc = 0;
> +
> + /* for the case where no src IP is configured */
> + *src_ip = 0;
> +
> + /* rtnl lock should be acquired in relevant flows before taking configuration lock */
> + if (!rtnl_is_locked()) {
> + netdev_err(port->ndev, "Rtnl lock is not acquired, can't proceed\n");
> + rc = -EFAULT;
> + goto out;
> + }
> +
> + in_dev = __in_dev_get_rtnl(ndev);
> + if (!in_dev) {
> + netdev_err(port->ndev, "Failed to get IPv4 struct\n");
> + rc = -EFAULT;
> + goto out;
> + }
> +
> + ifa = rtnl_dereference(in_dev->ifa_list);
> +
> + while (ifa) {
> + if (!strcmp(ndev->name, ifa->ifa_label)) {
> + /* convert the BE to native and later on it will be
> + * written to the HW as LE in QPC_SET
> + */
> + *src_ip = be32_to_cpu(ifa->ifa_local);
> + break;
> + }
> + ifa = rtnl_dereference(ifa->ifa_next);
> + }
> +out:
> + return rc;
> +}
Does this device require IPv4? What about users and infrastructures that use IPv6 only?
IPv4 is legacy at this point.
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-15 0:16 ` Stephen Hemminger
@ 2024-06-18 19:39 ` Omer Shpigelman
2024-06-19 15:40 ` Andrew Lunn
0 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-18 19:39 UTC (permalink / raw)
To: Stephen Hemminger
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/15/24 03:16, Stephen Hemminger wrote:
> [You don't often get email from stephen@networkplumber.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
>> +
>> +/* get the src IP as it is done in devinet_ioctl() */
>> +static int hbl_en_get_src_ip(struct hbl_aux_dev *aux_dev, u32 port_idx, u32 *src_ip)
>> +{
>> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
>> + struct net_device *ndev = port->ndev;
>> + struct in_device *in_dev;
>> + struct in_ifaddr *ifa;
>> + int rc = 0;
>> +
>> + /* for the case where no src IP is configured */
>> + *src_ip = 0;
>> +
>> + /* rtnl lock should be acquired in relevant flows before taking configuration lock */
>> + if (!rtnl_is_locked()) {
>> + netdev_err(port->ndev, "Rtnl lock is not acquired, can't proceed\n");
>> + rc = -EFAULT;
>> + goto out;
>> + }
>> +
>> + in_dev = __in_dev_get_rtnl(ndev);
>> + if (!in_dev) {
>> + netdev_err(port->ndev, "Failed to get IPv4 struct\n");
>> + rc = -EFAULT;
>> + goto out;
>> + }
>> +
>> + ifa = rtnl_dereference(in_dev->ifa_list);
>> +
>> + while (ifa) {
>> + if (!strcmp(ndev->name, ifa->ifa_label)) {
>> + /* convert the BE to native and later on it will be
>> + * written to the HW as LE in QPC_SET
>> + */
>> + *src_ip = be32_to_cpu(ifa->ifa_local);
>> + break;
>> + }
>> + ifa = rtnl_dereference(ifa->ifa_next);
>> + }
>> +out:
>> + return rc;
>> +}
>
> Does this device require IPv4? What about users and infrastructures that use IPv6 only?
> IPv4 is legacy at this point.
Gaudi2 supports IPv4 only.
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-18 19:39 ` Omer Shpigelman
@ 2024-06-19 15:40 ` Andrew Lunn
2024-06-20 8:36 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Andrew Lunn @ 2024-06-19 15:40 UTC (permalink / raw)
To: Omer Shpigelman
Cc: Stephen Hemminger, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
> > Does this device require IPv4? What about users and infrastructures that use IPv6 only?
> > IPv4 is legacy at this point.
>
> Gaudi2 supports IPv4 only.
Really? I guess really old stuff, SLIP from 1988 does not support
IPv6, but i don't remember seeing anything from this century which
does not support passing IPv6 frames over a netdev.
Andrew
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-19 15:40 ` Andrew Lunn
@ 2024-06-20 8:36 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-20 8:36 UTC (permalink / raw)
To: Andrew Lunn
Cc: Stephen Hemminger, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On 6/19/24 18:40, Andrew Lunn wrote:
>>> Does this device require IPv4? What about users and infrastructures that use IPv6 only?
>>> IPv4 is legacy at this point.
>>
>> Gaudi2 supports IPv4 only.
>
> Really? I guess really old stuff, SLIP from 1988 does not support
> IPv6, but i don't remember seeing anything from this century which
> does not support passing IPv6 frames over a netdev.
>
> Andrew
We support IPv6 for ETH, not for RDMA. For RDMA, IPv4 is good enough for
our use case so IPv6 was not required. Stephen's comment was about the
code where the CN driver fetches the port IP for configuring it to the
RDMA QPs. It is an RDMA specific path.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-13 8:22 ` [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver Omer Shpigelman
` (3 preceding siblings ...)
2024-06-15 0:16 ` Stephen Hemminger
@ 2024-06-15 10:55 ` Zhu Yanjun
2024-06-18 11:16 ` Omer Shpigelman
2024-06-15 17:13 ` Zhu Yanjun
5 siblings, 1 reply; 108+ messages in thread
From: Zhu Yanjun @ 2024-06-15 10:55 UTC (permalink / raw)
To: Omer Shpigelman, linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, zyehudai
在 2024/6/13 16:22, Omer Shpigelman 写道:
> This ethernet driver is initialized via auxiliary bus by the hbl_cn
> driver.
> It serves mainly for control operations that are needed for AI scaling.
>
> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> Co-developed-by: David Meriin <dmeriin@habana.ai>
> Signed-off-by: David Meriin <dmeriin@habana.ai>
> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
> ---
> MAINTAINERS | 9 +
> drivers/net/ethernet/intel/Kconfig | 18 +
> drivers/net/ethernet/intel/Makefile | 1 +
> drivers/net/ethernet/intel/hbl_en/Makefile | 9 +
> .../net/ethernet/intel/hbl_en/common/Makefile | 3 +
> .../net/ethernet/intel/hbl_en/common/hbl_en.c | 1168 +++++++++++++++++
> .../net/ethernet/intel/hbl_en/common/hbl_en.h | 206 +++
> .../intel/hbl_en/common/hbl_en_dcbnl.c | 101 ++
> .../ethernet/intel/hbl_en/common/hbl_en_drv.c | 211 +++
> .../intel/hbl_en/common/hbl_en_ethtool.c | 452 +++++++
> 10 files changed, 2178 insertions(+)
> create mode 100644 drivers/net/ethernet/intel/hbl_en/Makefile
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/Makefile
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 096439a62129..7301f38e9cfb 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -9617,6 +9617,15 @@ F: include/linux/habanalabs/
> F: include/linux/net/intel/cn*
> F: include/linux/net/intel/gaudi2*
>
> +HABANALABS ETHERNET DRIVER
> +M: Omer Shpigelman <oshpigelman@habana.ai>
> +L: netdev@vger.kernel.org
> +S: Supported
> +W: https://www.habana.ai
> +F: Documentation/networking/device_drivers/ethernet/intel/hbl.rst
> +F: drivers/net/ethernet/intel/hbl_en/
> +F: include/linux/net/intel/cn*
> +
> HACKRF MEDIA DRIVER
> L: linux-media@vger.kernel.org
> S: Orphan
> diff --git a/drivers/net/ethernet/intel/Kconfig b/drivers/net/ethernet/intel/Kconfig
> index 0d1b8a2bae99..5d07349348a0 100644
> --- a/drivers/net/ethernet/intel/Kconfig
> +++ b/drivers/net/ethernet/intel/Kconfig
> @@ -417,4 +417,22 @@ config HABANA_CN
> To compile this driver as a module, choose M here. The module
> will be called habanalabs_cn.
>
> +config HABANA_EN
> + tristate "HabanaLabs (an Intel Company) Ethernet driver"
> + depends on NETDEVICES && ETHERNET && INET
> + select HABANA_CN
> + help
> + This driver enables Ethernet functionality for the network interfaces
> + that are part of the GAUDI ASIC family of AI Accelerators.
> + For more information on how to identify your adapter, go to the
> + Adapter & Driver ID Guide that can be located at:
> +
> + <http://support.intel.com>
> +
> + More specific information on configuring the driver is in
> + <file:Documentation/networking/device_drivers/ethernet/intel/hbl.rst>.
> +
> + To compile this driver as a module, choose M here. The module
> + will be called habanalabs_en.
> +
> endif # NET_VENDOR_INTEL
> diff --git a/drivers/net/ethernet/intel/Makefile b/drivers/net/ethernet/intel/Makefile
> index 10049a28e336..ec62a0227897 100644
> --- a/drivers/net/ethernet/intel/Makefile
> +++ b/drivers/net/ethernet/intel/Makefile
> @@ -20,3 +20,4 @@ obj-$(CONFIG_FM10K) += fm10k/
> obj-$(CONFIG_ICE) += ice/
> obj-$(CONFIG_IDPF) += idpf/
> obj-$(CONFIG_HABANA_CN) += hbl_cn/
> +obj-$(CONFIG_HABANA_EN) += hbl_en/
> diff --git a/drivers/net/ethernet/intel/hbl_en/Makefile b/drivers/net/ethernet/intel/hbl_en/Makefile
> new file mode 100644
> index 000000000000..695497ab93b6
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/Makefile
> @@ -0,0 +1,9 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +#
> +# Makefile for HabanaLabs (an Intel Company) Ethernet network driver
> +#
> +
> +obj-$(CONFIG_HABANA_EN) := habanalabs_en.o
> +
> +include $(src)/common/Makefile
> +habanalabs_en-y += $(HBL_EN_COMMON_FILES)
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/Makefile b/drivers/net/ethernet/intel/hbl_en/common/Makefile
> new file mode 100644
> index 000000000000..a3ccb5dbf4a6
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +HBL_EN_COMMON_FILES := common/hbl_en_drv.o common/hbl_en.o \
> + common/hbl_en_ethtool.o common/hbl_en_dcbnl.o
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
> new file mode 100644
> index 000000000000..066be5ac2d84
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
> @@ -0,0 +1,1168 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#include "hbl_en.h"
> +#include <linux/inetdevice.h>
> +
> +#define TX_TIMEOUT (5 * HZ)
> +#define PORT_RESET_TIMEOUT_MSEC (60 * 1000ull) /* 60s */
> +
> +/**
> + * struct hbl_en_tx_pkt_work - used to schedule a work of a Tx packet.
> + * @tx_work: workqueue object to run when packet needs to be sent.
> + * @port: pointer to current port structure.
> + * @skb: copy of the packet to send.
> + */
> +struct hbl_en_tx_pkt_work {
> + struct work_struct tx_work;
> + struct hbl_en_port *port;
> + struct sk_buff *skb;
> +};
> +
> +static int hbl_en_napi_poll(struct napi_struct *napi, int budget);
> +static int hbl_en_port_open(struct hbl_en_port *port);
> +
> +static int hbl_en_ports_reopen(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> + struct hbl_en_port *port;
> + int rc = 0, i;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + /* It could be that the port was shutdown by 'ip link set down' and there is no need
> + * in reopening it.
> + * Since we mark the ports as in reset even if they are disabled, we clear the flag
> + * here anyway.
> + * See hbl_en_ports_stop_prepare() for more info.
> + */
> + if (!netif_running(port->ndev)) {
> + atomic_set(&port->in_reset, 0);
> + continue;
> + }
> +
> + rc = hbl_en_port_open(port);
> +
> + atomic_set(&port->in_reset, 0);
> +
> + if (rc)
> + break;
> + }
> +
> + hdev->in_reset = false;
> +
> + return rc;
> +}
> +
> +static void hbl_en_port_fini(struct hbl_en_port *port)
> +{
> + if (port->rx_wq)
> + destroy_workqueue(port->rx_wq);
> +}
> +
> +static int hbl_en_port_init(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + u32 port_idx = port->idx;
> + char wq_name[32];
> + int rc;
> +
> + if (hdev->poll_enable) {
> + memset(wq_name, 0, sizeof(wq_name));
> + snprintf(wq_name, sizeof(wq_name) - 1, "hbl%u-port%d-rx-wq", hdev->core_dev_id,
> + port_idx);
> + port->rx_wq = alloc_ordered_workqueue(wq_name, 0);
> + if (!port->rx_wq) {
> + dev_err(hdev->dev, "Failed to allocate Rx WQ\n");
> + rc = -ENOMEM;
> + goto fail;
> + }
> + }
> +
> + hbl_en_ethtool_init_coalesce(port);
> +
> + return 0;
> +
> +fail:
> + hbl_en_port_fini(port);
> +
> + return rc;
> +}
> +
> +static void _hbl_en_set_port_status(struct hbl_en_port *port, bool up)
> +{
> + struct net_device *ndev = port->ndev;
> + u32 port_idx = port->idx;
> +
> + if (up) {
> + netif_carrier_on(ndev);
> + netif_wake_queue(ndev);
> + } else {
> + netif_carrier_off(ndev);
> + netif_stop_queue(ndev);
> + }
> +
> + /* Unless link events are getting through the EQ, no need to print about link down events
> + * during port reset
> + */
> + if (port->hdev->has_eq || up || !atomic_read(&port->in_reset))
> + netdev_info(port->ndev, "link %s, port %d\n", up ? "up" : "down", port_idx);
> +}
> +
> +static void hbl_en_set_port_status(struct hbl_aux_dev *aux_dev, u32 port_idx, bool up)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + _hbl_en_set_port_status(port, up);
> +}
> +
> +static bool hbl_en_is_port_open(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + return port->is_initialized;
> +}
> +
> +/* get the src IP as it is done in devinet_ioctl() */
> +static int hbl_en_get_src_ip(struct hbl_aux_dev *aux_dev, u32 port_idx, u32 *src_ip)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> + struct net_device *ndev = port->ndev;
> + struct in_device *in_dev;
> + struct in_ifaddr *ifa;
> + int rc = 0;
> +
> + /* for the case where no src IP is configured */
> + *src_ip = 0;
> +
> + /* rtnl lock should be acquired in relevant flows before taking configuration lock */
> + if (!rtnl_is_locked()) {
> + netdev_err(port->ndev, "Rtnl lock is not acquired, can't proceed\n");
> + rc = -EFAULT;
> + goto out;
> + }
> +
> + in_dev = __in_dev_get_rtnl(ndev);
> + if (!in_dev) {
> + netdev_err(port->ndev, "Failed to get IPv4 struct\n");
> + rc = -EFAULT;
> + goto out;
> + }
> +
> + ifa = rtnl_dereference(in_dev->ifa_list);
> +
> + while (ifa) {
> + if (!strcmp(ndev->name, ifa->ifa_label)) {
> + /* convert the BE to native and later on it will be
> + * written to the HW as LE in QPC_SET
> + */
> + *src_ip = be32_to_cpu(ifa->ifa_local);
> + break;
> + }
> + ifa = rtnl_dereference(ifa->ifa_next);
> + }
> +out:
> + return rc;
> +}
> +
> +static void hbl_en_reset_stats(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + port->net_stats.rx_packets = 0;
> + port->net_stats.tx_packets = 0;
> + port->net_stats.rx_bytes = 0;
> + port->net_stats.tx_bytes = 0;
> + port->net_stats.tx_errors = 0;
> + atomic64_set(&port->net_stats.rx_dropped, 0);
> + atomic64_set(&port->net_stats.tx_dropped, 0);
> +}
> +
> +static u32 hbl_en_get_mtu(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> + struct net_device *ndev = port->ndev;
> + u32 mtu;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(ndev, "port is in reset, can't get MTU\n");
> + return 0;
> + }
> +
> + mtu = ndev->mtu;
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return mtu;
> +}
> +
> +static u32 hbl_en_get_pflags(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + return port->pflags;
> +}
> +
> +static void hbl_en_set_dev_lpbk(struct hbl_aux_dev *aux_dev, u32 port_idx, bool enable)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> + struct net_device *ndev = port->ndev;
> +
> + if (enable)
> + ndev->features |= NETIF_F_LOOPBACK;
> + else
> + ndev->features &= ~NETIF_F_LOOPBACK;
> +}
> +
> +/* This function should be called after ctrl_lock was taken */
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/dev-tools/sparse.rst?h=v6.10-rc3#n64
"
__must_hold - The specified lock is held on function entry and exit.
"
Add "__must_hold" to confirm "The specified lock is held on function
entry and exit." ?
Zhu Yanjun
> +static int hbl_en_port_open_locked(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct net_device *ndev = port->ndev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int rc;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + if (port->is_initialized)
> + return 0;
> +
> + if (!hdev->poll_enable)
> + netif_napi_add(ndev, &port->napi, hbl_en_napi_poll);
> +
> + rc = aux_ops->port_hw_init(aux_dev, port_idx);
> + if (rc) {
> + netdev_err(ndev, "Failed to configure the HW, rc %d\n", rc);
> + goto hw_init_fail;
> + }
> +
> + if (!hdev->poll_enable)
> + napi_enable(&port->napi);
> +
> + rc = hdev->asic_funcs.eth_port_open(port);
> + if (rc) {
> + netdev_err(ndev, "Failed to init H/W, rc %d\n", rc);
> + goto port_open_fail;
> + }
> +
> + rc = aux_ops->update_mtu(aux_dev, port_idx, ndev->mtu);
> + if (rc) {
> + netdev_err(ndev, "MTU update failed, rc %d\n", rc);
> + goto update_mtu_fail;
> + }
> +
> + rc = aux_ops->phy_init(aux_dev, port_idx);
> + if (rc) {
> + netdev_err(ndev, "PHY init failed, rc %d\n", rc);
> + goto phy_init_fail;
> + }
> +
> + netif_start_queue(ndev);
> +
> + port->is_initialized = true;
> +
> + return 0;
> +
> +phy_init_fail:
> + /* no need to revert the MTU change, it will be updated on next port open */
> +update_mtu_fail:
> + hdev->asic_funcs.eth_port_close(port);
> +port_open_fail:
> + if (!hdev->poll_enable)
> + napi_disable(&port->napi);
> +
> + aux_ops->port_hw_fini(aux_dev, port_idx);
> +hw_init_fail:
> + if (!hdev->poll_enable)
> + netif_napi_del(&port->napi);
> +
> + return rc;
> +}
> +
> +static int hbl_en_port_open(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int rc;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + aux_ops->ctrl_lock(aux_dev, port_idx);
> + rc = hbl_en_port_open_locked(port);
> + aux_ops->ctrl_unlock(aux_dev, port_idx);
> +
> + return rc;
> +}
> +
> +static int hbl_en_open(struct net_device *netdev)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + int rc;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(netdev, "port is in reset, can't open it\n");
> + return -EBUSY;
> + }
> +
> + rc = hbl_en_port_open(port);
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +/* This function should be called after ctrl_lock was taken */
> +static void hbl_en_port_close_locked(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + if (!port->is_initialized)
> + return;
> +
> + port->is_initialized = false;
> +
> + /* verify that the port is marked as closed before continuing */
> + mb();
> +
> + /* Print if not in hard reset flow e.g. from ip cmd */
> + if (!hdev->in_reset && netif_carrier_ok(port->ndev))
> + netdev_info(port->ndev, "port was closed\n");
> +
> + /* disable the PHY here so no link changes will occur from this point forward */
> + aux_ops->phy_fini(aux_dev, port_idx);
> +
> + /* disable Tx SW flow */
> + netif_carrier_off(port->ndev);
> + netif_tx_disable(port->ndev);
> +
> + /* stop Tx/Rx HW */
> + aux_ops->port_hw_fini(aux_dev, port_idx);
> +
> + /* disable Tx/Rx QPs */
> + hdev->asic_funcs.eth_port_close(port);
> +
> + /* stop Rx SW flow */
> + if (hdev->poll_enable) {
> + hbl_en_rx_poll_stop(port);
> + } else {
> + napi_disable(&port->napi);
> + netif_napi_del(&port->napi);
> + }
> +
> + /* Explicitly count the port close operations as we don't get a link event for this.
> + * Upon port open we receive a link event, hence no additional action required.
> + */
> + aux_ops->port_toggle_count(aux_dev, port_idx);
> +}
> +
> +static void hbl_en_port_close(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + aux_ops->ctrl_lock(aux_dev, port_idx);
> + hbl_en_port_close_locked(port);
> + aux_ops->ctrl_unlock(aux_dev, port_idx);
> +}
> +
> +/* This function should be called after ctrl_lock was taken */
> +static int __hbl_en_port_reset_locked(struct hbl_en_port *port)
> +{
> + hbl_en_port_close_locked(port);
> +
> + return hbl_en_port_open_locked(port);
> +}
> +
> +/* This function should be called after ctrl_lock was taken */
> +int hbl_en_port_reset_locked(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + return __hbl_en_port_reset_locked(port);
> +}
> +
> +int hbl_en_port_reset(struct hbl_en_port *port)
> +{
> + hbl_en_port_close(port);
> +
> + /* Sleep in order to let obsolete events to be dropped before re-opening the port */
> + msleep(20);
> +
> + return hbl_en_port_open(port);
> +}
> +
> +static int hbl_en_close(struct net_device *netdev)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + struct hbl_en_device *hdev = port->hdev;
> + ktime_t timeout;
> +
> + /* Looks like the return value of this function is not checked, so we can't just return
> + * EBUSY if the port is under reset. We need to wait until the reset is finished and then
> + * close the port. Otherwise the netdev will set the port as closed although port_close()
> + * wasn't called. Only if we waited long enough and the reset hasn't finished, we can return
> + * an error without actually closing the port as it is a fatal flow anyway.
> + */
> + timeout = ktime_add_ms(ktime_get(), PORT_RESET_TIMEOUT_MSEC);
> + while (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + /* If this is called from unregister_netdev() then the port was already closed and
> + * hence we can safely return.
> + * We could have just check the port_open boolean, but that might hide some future
> + * bugs. Hence it is better to use a dedicated flag for that.
> + */
> + if (READ_ONCE(hdev->in_teardown))
> + return 0;
> +
> + usleep_range(50, 200);
> + if (ktime_compare(ktime_get(), timeout) > 0) {
> + netdev_crit(netdev,
> + "Timeout while waiting for port to finish reset, can't close it\n"
> + );
> + return -EBUSY;
> + }
> + }
> +
> + hbl_en_port_close(port);
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return 0;
> +}
> +
> +/**
> + * hbl_en_ports_stop_prepare() - stop the Rx and Tx and synchronize with other reset flows.
> + * @aux_dev: habanalabs auxiliary device structure.
> + *
> + * This function makes sure that during the reset no packets will be processed and that
> + * ndo_open/ndo_close do not open/close the ports.
> + * A hard reset might occur right after the driver was loaded, which means before the ports
> + * initialization was finished. Therefore, even if the ports are not yet open, we mark it as in
> + * reset in order to avoid races. We clear the in reset flag later on when reopening the ports.
> + */
> +static void hbl_en_ports_stop_prepare(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> + struct hbl_en_port *port;
> + ktime_t timeout;
> + int i;
> +
> + /* Check if the ports where initialized. If not, we shouldn't mark them as in reset because
> + * they will fail to get opened.
> + */
> + if (!hdev->is_initialized || hdev->in_reset)
> + return;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + /* This function is competing with reset from ethtool/ip, so try to take the
> + * in_reset atomic and if we are already in a middle of reset, wait until reset
> + * function is finished.
> + * Reset function is designed to always finish (could take up to a few seconds in
> + * worst case).
> + * We mark also closed ports as in reset so they won't be able to get opened while
> + * the device in under reset.
> + */
> +
> + timeout = ktime_add_ms(ktime_get(), PORT_RESET_TIMEOUT_MSEC);
> + while (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + usleep_range(50, 200);
> + if (ktime_compare(ktime_get(), timeout) > 0) {
> + netdev_crit(port->ndev,
> + "Timeout while waiting for port %d to finish reset\n",
> + port->idx);
> + break;
> + }
> + }
> + }
> +
> + hdev->in_reset = true;
> +}
> +
> +static void hbl_en_ports_stop(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> + struct hbl_en_port *port;
> + int i;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + if (netif_running(port->ndev))
> + hbl_en_port_close(port);
> + }
> +}
> +
> +static int hbl_en_change_mtu(struct net_device *netdev, int new_mtu)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + int rc = 0;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(netdev, "port is in reset, can't change MTU\n");
> + return -EBUSY;
> + }
> +
> + if (netif_running(port->ndev)) {
> + hbl_en_port_close(port);
> +
> + /* Sleep in order to let obsolete events to be dropped before re-opening the port */
> + msleep(20);
> +
> + netdev->mtu = new_mtu;
> +
> + rc = hbl_en_port_open(port);
> + if (rc)
> + netdev_err(netdev, "Failed to reinit port for MTU change, rc %d\n", rc);
> + } else {
> + netdev->mtu = new_mtu;
> + }
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +/* Swap source and destination MAC addresses */
> +static inline void swap_l2(char *buf)
> +{
> + u16 *eth_hdr, tmp;
> +
> + eth_hdr = (u16 *)buf;
> + tmp = eth_hdr[0];
> + eth_hdr[0] = eth_hdr[3];
> + eth_hdr[3] = tmp;
> + tmp = eth_hdr[1];
> + eth_hdr[1] = eth_hdr[4];
> + eth_hdr[4] = tmp;
> + tmp = eth_hdr[2];
> + eth_hdr[2] = eth_hdr[5];
> + eth_hdr[5] = tmp;
> +}
> +
> +/* Swap source and destination IP addresses
> + */
> +static inline void swap_l3(char *buf)
> +{
> + u32 tmp;
> +
> + /* skip the Ethernet header and the IP header till source IP address */
> + buf += ETH_HLEN + 12;
> + tmp = ((u32 *)buf)[0];
> + ((u32 *)buf)[0] = ((u32 *)buf)[1];
> + ((u32 *)buf)[1] = tmp;
> +}
> +
> +static void do_tx_swap(struct hbl_en_port *port, struct sk_buff *skb)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + u16 *tmp_buff = (u16 *)skb->data;
> + u32 port_idx = port->idx;
> +
> + /* First, let's print the SKB we got */
> + dev_dbg_ratelimited(hdev->dev,
> + "Send [P%d]: dst-mac:%04x%04x%04x, src-mac:%04x%04x%04x, eth-type:%04x, len:%u\n",
> + port_idx, swab16(tmp_buff[0]), swab16(tmp_buff[1]), swab16(tmp_buff[2]),
> + swab16(tmp_buff[3]), swab16(tmp_buff[4]), swab16(tmp_buff[5]),
> + swab16(tmp_buff[6]), skb->len);
> +
> + /* Before submit it to HW, in case this is ipv4 pkt, swap eth/ip addresses.
> + * that way, we may send ECMP (ping) to ourselves in LB cases.
> + */
> + swap_l2(skb->data);
> + if (swab16(tmp_buff[6]) == ETH_P_IP)
> + swap_l3(skb->data);
> +}
> +
> +static bool is_pkt_swap_enabled(struct hbl_en_device *hdev)
> +{
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + return aux_ops->is_eth_lpbk(aux_dev);
> +}
> +
> +static bool is_tx_disabled(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + return aux_ops->get_mac_lpbk(aux_dev, port_idx) && !is_pkt_swap_enabled(hdev);
> +}
> +
> +static netdev_tx_t hbl_en_handle_tx(struct hbl_en_port *port, struct sk_buff *skb)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + netdev_tx_t ret;
> +
> + if (skb->len <= 0 || is_tx_disabled(port))
> + goto free_skb;
> +
> + if (skb->len > hdev->max_frm_len) {
> + netdev_err(port->ndev, "Tx pkt size %uB exceeds maximum of %uB\n", skb->len,
> + hdev->max_frm_len);
> + goto free_skb;
> + }
> +
> + if (is_pkt_swap_enabled(hdev))
> + do_tx_swap(port, skb);
> +
> + /* Pad the ethernet packets to the minimum frame size as the NIC hw doesn't do it.
> + * eth_skb_pad() frees the packet on failure, so just increment the dropped counter and
> + * return as success to avoid a retry.
> + */
> + if (skb_put_padto(skb, hdev->pad_size)) {
> + dev_err_ratelimited(hdev->dev, "Padding failed, the skb is dropped\n");
> + atomic64_inc(&port->net_stats.tx_dropped);
> + return NETDEV_TX_OK;
> + }
> +
> + ret = hdev->asic_funcs.write_pkt_to_hw(port, skb);
> + if (ret == NETDEV_TX_OK) {
> + port->net_stats.tx_packets++;
> + port->net_stats.tx_bytes += skb->len;
> + }
> +
> + return ret;
> +
> +free_skb:
> + dev_kfree_skb_any(skb);
> + return NETDEV_TX_OK;
> +}
> +
> +static netdev_tx_t hbl_en_start_xmit(struct sk_buff *skb, struct net_device *netdev)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + struct hbl_en_device *hdev;
> +
> + hdev = port->hdev;
> +
> + return hbl_en_handle_tx(port, skb);
> +}
> +
> +static int hbl_en_set_port_mac_loopback(struct hbl_en_port *port, bool enable)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct net_device *ndev = port->ndev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int rc;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + rc = aux_ops->set_mac_lpbk(aux_dev, port_idx, enable);
> + if (rc)
> + return rc;
> +
> + netdev_info(ndev, "port %u: mac loopback is %s\n", port_idx,
> + enable ? "enabled" : "disabled");
> +
> + if (netif_running(ndev)) {
> + rc = hbl_en_port_reset(port);
> + if (rc) {
> + netdev_err(ndev, "Failed to reset port %u, rc %d\n", port_idx, rc);
> + return rc;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int hbl_en_set_features(struct net_device *netdev, netdev_features_t features)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + netdev_features_t changed;
> + int rc = 0;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(netdev, "port %d is in reset, can't update settings", port->idx);
> + return -EBUSY;
> + }
> +
> + changed = netdev->features ^ features;
> +
> + if (changed & NETIF_F_LOOPBACK)
> + rc = hbl_en_set_port_mac_loopback(port, !!(features & NETIF_F_LOOPBACK));
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +static void hbl_en_handle_tx_timeout(struct net_device *netdev, unsigned int txqueue)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> +
> + port->net_stats.tx_errors++;
> + atomic64_inc(&port->net_stats.tx_dropped);
> +}
> +
> +static void hbl_en_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(dev);
> +
> + stats->rx_bytes = port->net_stats.rx_bytes;
> + stats->tx_bytes = port->net_stats.tx_bytes;
> + stats->rx_packets = port->net_stats.rx_packets;
> + stats->tx_packets = port->net_stats.tx_packets;
> + stats->tx_errors = port->net_stats.tx_errors;
> + stats->tx_dropped = (u64)atomic64_read(&port->net_stats.tx_dropped);
> + stats->rx_dropped = (u64)atomic64_read(&port->net_stats.rx_dropped);
> +}
> +
> +static const struct net_device_ops hbl_en_netdev_ops = {
> + .ndo_open = hbl_en_open,
> + .ndo_stop = hbl_en_close,
> + .ndo_start_xmit = hbl_en_start_xmit,
> + .ndo_validate_addr = eth_validate_addr,
> + .ndo_change_mtu = hbl_en_change_mtu,
> + .ndo_set_features = hbl_en_set_features,
> + .ndo_get_stats64 = hbl_en_get_stats64,
> + .ndo_tx_timeout = hbl_en_handle_tx_timeout,
> +};
> +
> +static void hbl_en_set_ops(struct net_device *ndev)
> +{
> + ndev->netdev_ops = &hbl_en_netdev_ops;
> + ndev->ethtool_ops = hbl_en_ethtool_get_ops(ndev);
> +#ifdef CONFIG_DCB
> + ndev->dcbnl_ops = &hbl_en_dcbnl_ops;
> +#endif
> +}
> +
> +static int hbl_en_port_register(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + struct hbl_en_port **ptr;
> + struct net_device *ndev;
> + int rc;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + ndev = alloc_etherdev(sizeof(struct hbl_en_port *));
> + if (!ndev) {
> + dev_err(hdev->dev, "netdevice %d alloc failed\n", port_idx);
> + return -ENOMEM;
> + }
> +
> + port->ndev = ndev;
> + SET_NETDEV_DEV(ndev, &hdev->pdev->dev);
> + ptr = netdev_priv(ndev);
> + *ptr = port;
> +
> + /* necessary for creating multiple interfaces */
> + ndev->dev_port = port_idx;
> +
> + hbl_en_set_ops(ndev);
> +
> + ndev->watchdog_timeo = TX_TIMEOUT;
> + ndev->min_mtu = hdev->min_raw_mtu;
> + ndev->max_mtu = hdev->max_raw_mtu;
> +
> + /* Add loopback capability to the device. */
> + ndev->hw_features |= NETIF_F_LOOPBACK;
> +
> + /* If this port was set to loopback, set it also to the ndev features */
> + if (aux_ops->get_mac_lpbk(aux_dev, port_idx))
> + ndev->features |= NETIF_F_LOOPBACK;
> +
> + eth_hw_addr_set(ndev, port->mac_addr);
> +
> + /* It's more an intelligent poll wherein, we enable the Rx completion EQE event and then
> + * start the poll from there.
> + * Inside the polling thread, we read packets from hardware and then reschedule the poll
> + * only if there are more packets to be processed. Else we re-enable the CQ Arm interrupt
> + * and exit the poll.
> + */
> + if (hdev->poll_enable)
> + hbl_en_rx_poll_trigger_init(port);
> +
> + netif_carrier_off(ndev);
> +
> + rc = register_netdev(ndev);
> + if (rc) {
> + dev_err(hdev->dev, "Could not register netdevice %d\n", port_idx);
> + goto err;
> + }
> +
> + return 0;
> +
> +err:
> + if (ndev) {
> + free_netdev(ndev);
> + port->ndev = NULL;
> + }
> +
> + return rc;
> +}
> +
> +static void dump_swap_pkt(struct hbl_en_port *port, struct sk_buff *skb)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + u16 *tmp_buff = (u16 *)skb->data;
> + u32 port_idx = port->idx;
> +
> + /* The SKB is ready now (before stripping-out the L2), print its content */
> + dev_dbg_ratelimited(hdev->dev,
> + "Recv [P%d]: dst-mac:%04x%04x%04x, src-mac:%04x%04x%04x, eth-type:%04x, len:%u\n",
> + port_idx, swab16(tmp_buff[0]), swab16(tmp_buff[1]), swab16(tmp_buff[2]),
> + swab16(tmp_buff[3]), swab16(tmp_buff[4]), swab16(tmp_buff[5]),
> + swab16(tmp_buff[6]), skb->len);
> +}
> +
> +int hbl_en_handle_rx(struct hbl_en_port *port, int budget)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + enum hbl_en_eth_pkt_status pkt_status;
> + struct net_device *ndev = port->ndev;
> + int rc, pkt_count = 0;
> + struct sk_buff *skb;
> + void *pkt_addr;
> + u32 pkt_size;
> +
> + if (!netif_carrier_ok(ndev))
> + return 0;
> +
> + while (pkt_count < budget) {
> + pkt_status = hdev->asic_funcs.read_pkt_from_hw(port, &pkt_addr, &pkt_size);
> +
> + if (pkt_status == ETH_PKT_NONE)
> + break;
> +
> + pkt_count++;
> +
> + if (pkt_status == ETH_PKT_DROP) {
> + atomic64_inc(&port->net_stats.rx_dropped);
> + continue;
> + }
> +
> + if (hdev->poll_enable)
> + skb = __netdev_alloc_skb_ip_align(ndev, pkt_size, GFP_KERNEL);
> + else
> + skb = napi_alloc_skb(&port->napi, pkt_size);
> +
> + if (!skb) {
> + atomic64_inc(&port->net_stats.rx_dropped);
> + break;
> + }
> +
> + skb_copy_to_linear_data(skb, pkt_addr, pkt_size);
> + skb_put(skb, pkt_size);
> +
> + if (is_pkt_swap_enabled(hdev))
> + dump_swap_pkt(port, skb);
> +
> + skb->protocol = eth_type_trans(skb, ndev);
> +
> + /* Zero the packet buffer memory to avoid leak in case of wrong
> + * size is used when next packet populates the same memory
> + */
> + memset(pkt_addr, 0, pkt_size);
> +
> + /* polling is done in thread context and hence BH should be disabled */
> + if (hdev->poll_enable)
> + local_bh_disable();
> +
> + rc = netif_receive_skb(skb);
> +
> + if (hdev->poll_enable)
> + local_bh_enable();
> +
> + if (rc == NET_RX_SUCCESS) {
> + port->net_stats.rx_packets++;
> + port->net_stats.rx_bytes += pkt_size;
> + } else {
> + atomic64_inc(&port->net_stats.rx_dropped);
> + }
> + }
> +
> + return pkt_count;
> +}
> +
> +static bool __hbl_en_rx_poll_schedule(struct hbl_en_port *port, unsigned long delay)
> +{
> + return queue_delayed_work(port->rx_wq, &port->rx_poll_work, delay);
> +}
> +
> +static void hbl_en_rx_poll_work(struct work_struct *work)
> +{
> + struct hbl_en_port *port = container_of(work, struct hbl_en_port, rx_poll_work.work);
> + struct hbl_en_device *hdev = port->hdev;
> + int pkt_count;
> +
> + pkt_count = hbl_en_handle_rx(port, NAPI_POLL_WEIGHT);
> +
> + /* Reschedule the poll if we have consumed budget which means we still have packets to
> + * process. Else re-enable the Rx IRQs and exit the work.
> + */
> + if (pkt_count < NAPI_POLL_WEIGHT)
> + hdev->asic_funcs.reenable_rx_irq(port);
> + else
> + __hbl_en_rx_poll_schedule(port, 0);
> +}
> +
> +/* Rx poll init and trigger routines are used in event-driven setups where
> + * Rx polling is initialized once during init or open and started/triggered by the event handler.
> + */
> +void hbl_en_rx_poll_trigger_init(struct hbl_en_port *port)
> +{
> + INIT_DELAYED_WORK(&port->rx_poll_work, hbl_en_rx_poll_work);
> +}
> +
> +bool hbl_en_rx_poll_start(struct hbl_en_port *port)
> +{
> + return __hbl_en_rx_poll_schedule(port, msecs_to_jiffies(1));
> +}
> +
> +void hbl_en_rx_poll_stop(struct hbl_en_port *port)
> +{
> + cancel_delayed_work_sync(&port->rx_poll_work);
> +}
> +
> +static int hbl_en_napi_poll(struct napi_struct *napi, int budget)
> +{
> + struct hbl_en_port *port = container_of(napi, struct hbl_en_port, napi);
> + struct hbl_en_device *hdev = port->hdev;
> + int pkt_count;
> +
> + /* exit if we are called by netpoll as we free the Tx ring via EQ (if enabled) */
> + if (!budget)
> + return 0;
> +
> + pkt_count = hbl_en_handle_rx(port, budget);
> +
> + /* If budget not fully consumed, exit the polling mode */
> + if (pkt_count < budget) {
> + napi_complete_done(napi, pkt_count);
> + hdev->asic_funcs.reenable_rx_irq(port);
> + }
> +
> + return pkt_count;
> +}
> +
> +static void hbl_en_port_unregister(struct hbl_en_port *port)
> +{
> + struct net_device *ndev = port->ndev;
> +
> + unregister_netdev(ndev);
> + free_netdev(ndev);
> + port->ndev = NULL;
> +}
> +
> +static int hbl_en_set_asic_funcs(struct hbl_en_device *hdev)
> +{
> + switch (hdev->asic_type) {
> + case HBL_ASIC_GAUDI2:
> + default:
> + dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static void hbl_en_handle_eqe(struct hbl_aux_dev *aux_dev, u32 port, struct hbl_cn_eqe *eqe)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> +
> + hdev->asic_funcs.handle_eqe(aux_dev, port, eqe);
> +}
> +
> +static void hbl_en_set_aux_ops(struct hbl_en_device *hdev, bool enable)
> +{
> + struct hbl_en_aux_ops *aux_ops = hdev->aux_dev->aux_ops;
> +
> + if (enable) {
> + aux_ops->ports_reopen = hbl_en_ports_reopen;
> + aux_ops->ports_stop_prepare = hbl_en_ports_stop_prepare;
> + aux_ops->ports_stop = hbl_en_ports_stop;
> + aux_ops->set_port_status = hbl_en_set_port_status;
> + aux_ops->is_port_open = hbl_en_is_port_open;
> + aux_ops->get_src_ip = hbl_en_get_src_ip;
> + aux_ops->reset_stats = hbl_en_reset_stats;
> + aux_ops->get_mtu = hbl_en_get_mtu;
> + aux_ops->get_pflags = hbl_en_get_pflags;
> + aux_ops->set_dev_lpbk = hbl_en_set_dev_lpbk;
> + aux_ops->handle_eqe = hbl_en_handle_eqe;
> + } else {
> + aux_ops->ports_reopen = NULL;
> + aux_ops->ports_stop_prepare = NULL;
> + aux_ops->ports_stop = NULL;
> + aux_ops->set_port_status = NULL;
> + aux_ops->is_port_open = NULL;
> + aux_ops->get_src_ip = NULL;
> + aux_ops->reset_stats = NULL;
> + aux_ops->get_mtu = NULL;
> + aux_ops->get_pflags = NULL;
> + aux_ops->set_dev_lpbk = NULL;
> + aux_ops->handle_eqe = NULL;
> + }
> +}
> +
> +int hbl_en_dev_init(struct hbl_en_device *hdev)
> +{
> + struct hbl_en_asic_funcs *asic_funcs = &hdev->asic_funcs;
> + struct hbl_en_port *port;
> + int rc, i, port_cnt = 0;
> +
> + /* must be called before the call to dev_init() */
> + rc = hbl_en_set_asic_funcs(hdev);
> + if (rc) {
> + dev_err(hdev->dev, "failed to set aux ops\n");
> + return rc;
> + }
> +
> + rc = asic_funcs->dev_init(hdev);
> + if (rc) {
> + dev_err(hdev->dev, "device init failed\n");
> + return rc;
> + }
> +
> + /* init the function pointers here before calling hbl_en_port_register which sets up
> + * net_device_ops, and its ops might start getting called.
> + * If any failure is encountered, these will be made NULL and the core driver won't call
> + * them.
> + */
> + hbl_en_set_aux_ops(hdev, true);
> +
> + /* Port register depends on the above initialization so it must be called here and not
> + * before that.
> + */
> + for (i = 0; i < hdev->max_num_of_ports; i++, port_cnt++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + rc = hbl_en_port_init(port);
> + if (rc) {
> + dev_err(hdev->dev, "port init failed\n");
> + goto unregister_ports;
> + }
> +
> + rc = hbl_en_port_register(port);
> + if (rc) {
> + dev_err(hdev->dev, "port register failed\n");
> +
> + hbl_en_port_fini(port);
> + goto unregister_ports;
> + }
> + }
> +
> + hdev->is_initialized = true;
> +
> + return 0;
> +
> +unregister_ports:
> + for (i = 0; i < port_cnt; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + hbl_en_port_unregister(port);
> + hbl_en_port_fini(port);
> + }
> +
> + hbl_en_set_aux_ops(hdev, false);
> +
> + asic_funcs->dev_fini(hdev);
> +
> + return rc;
> +}
> +
> +void hbl_en_dev_fini(struct hbl_en_device *hdev)
> +{
> + struct hbl_en_asic_funcs *asic_funcs = &hdev->asic_funcs;
> + struct hbl_en_port *port;
> + int i;
> +
> + hdev->in_teardown = true;
> +
> + if (!hdev->is_initialized)
> + return;
> +
> + hdev->is_initialized = false;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + /* It could be this cleanup flow is called after a failed init flow.
> + * Hence we need to check that we indeed have a netdev to unregister.
> + */
> + if (!port->ndev)
> + continue;
> +
> + hbl_en_port_unregister(port);
> + hbl_en_port_fini(port);
> + }
> +
> + hbl_en_set_aux_ops(hdev, false);
> +
> + asic_funcs->dev_fini(hdev);
> +}
> +
> +dma_addr_t hbl_en_dma_map(struct hbl_en_device *hdev, void *addr, int len)
> +{
> + dma_addr_t dma_addr;
> +
> + if (hdev->dma_map_support)
> + dma_addr = dma_map_single(&hdev->pdev->dev, addr, len, DMA_TO_DEVICE);
> + else
> + dma_addr = virt_to_phys(addr);
> +
> + return dma_addr;
> +}
> +
> +void hbl_en_dma_unmap(struct hbl_en_device *hdev, dma_addr_t dma_addr, int len)
> +{
> + if (hdev->dma_map_support)
> + dma_unmap_single(&hdev->pdev->dev, dma_addr, len, DMA_TO_DEVICE);
> +}
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
> new file mode 100644
> index 000000000000..15504c1f3cfb
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
> @@ -0,0 +1,206 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#ifndef HABANALABS_EN_H_
> +#define HABANALABS_EN_H_
> +
> +#include <linux/net/intel/cn.h>
> +
> +#include <linux/netdevice.h>
> +#include <linux/pci.h>
> +
> +#define HBL_EN_NAME "habanalabs_en"
> +
> +#define HBL_EN_PORT(aux_dev, idx) (&(((struct hbl_en_device *)(aux_dev)->priv)->ports[(idx)]))
> +
> +#define hbl_netdev_priv(ndev) \
> +({ \
> + typecheck(struct net_device *, ndev); \
> + *(struct hbl_en_port **)netdev_priv(ndev); \
> +})
> +
> +/**
> + * enum hbl_en_eth_pkt_status - status of Rx Ethernet packet.
> + * ETH_PKT_OK: packet was received successfully.
> + * ETH_PKT_DROP: packet should be dropped.
> + * ETH_PKT_NONE: no available packet.
> + */
> +enum hbl_en_eth_pkt_status {
> + ETH_PKT_OK,
> + ETH_PKT_DROP,
> + ETH_PKT_NONE
> +};
> +
> +/**
> + * struct hbl_en_net_stats - stats of Ethernet interface.
> + * rx_packets: number of packets received.
> + * tx_packets: number of packets sent.
> + * rx_bytes: total bytes of data received.
> + * tx_bytes: total bytes of data sent.
> + * tx_errors: number of errors in the TX.
> + * rx_dropped: number of packets dropped by the RX.
> + * tx_dropped: number of packets dropped by the TX.
> + */
> +struct hbl_en_net_stats {
> + u64 rx_packets;
> + u64 tx_packets;
> + u64 rx_bytes;
> + u64 tx_bytes;
> + u64 tx_errors;
> + atomic64_t rx_dropped;
> + atomic64_t tx_dropped;
> +};
> +
> +/**
> + * struct hbl_en_port - manage port common structure.
> + * @hdev: habanalabs Ethernet device structure.
> + * @ndev: network device.
> + * @rx_wq: WQ for Rx poll when we cannot schedule NAPI poll.
> + * @mac_addr: HW MAC addresses.
> + * @asic_specific: ASIC specific port structure.
> + * @napi: New API structure.
> + * @rx_poll_work: Rx work for polling mode.
> + * @net_stats: statistics of the ethernet interface.
> + * @in_reset: true if the NIC was marked as in reset, false otherwise. Used to avoid an additional
> + * stopping of the NIC if a hard reset was re-initiated.
> + * @pflags: ethtool private flags bit mask.
> + * @idx: index of this specific port.
> + * @rx_max_coalesced_frames: Maximum number of packets to receive before an RX interrupt.
> + * @tx_max_coalesced_frames: Maximum number of packets to be sent before a TX interrupt.
> + * @rx_coalesce_usecs: How many usecs to delay an RX interrupt after a packet arrives.
> + * @is_initialized: true if the port H/W is initialized, false otherwise.
> + * @pfc_enable: true if this port supports Priority Flow Control, false otherwise.
> + * @auto_neg_enable: is autoneg enabled.
> + * @auto_neg_resolved: was autoneg phase finished successfully.
> + */
> +struct hbl_en_port {
> + struct hbl_en_device *hdev;
> + struct net_device *ndev;
> + struct workqueue_struct *rx_wq;
> + char *mac_addr;
> + void *asic_specific;
> + struct napi_struct napi;
> + struct delayed_work rx_poll_work;
> + struct hbl_en_net_stats net_stats;
> + atomic_t in_reset;
> + u32 pflags;
> + u32 idx;
> + u32 rx_max_coalesced_frames;
> + u32 tx_max_coalesced_frames;
> + u16 rx_coalesce_usecs;
> + u8 is_initialized;
> + u8 pfc_enable;
> + u8 auto_neg_enable;
> + u8 auto_neg_resolved;
> +};
> +
> +/**
> + * struct hbl_en_asic_funcs - ASIC specific Ethernet functions.
> + * @dev_init: device init.
> + * @dev_fini: device cleanup.
> + * @reenable_rx_irq: re-enable Rx interrupts.
> + * @eth_port_open: initialize and open the Ethernet port.
> + * @eth_port_close: close the Ethernet port.
> + * @write_pkt_to_hw: write skb to HW.
> + * @read_pkt_from_hw: read pkt from HW.
> + * @get_pfc_cnts: get PFC counters.
> + * @set_coalesce: set Tx/Rx coalesce config in HW.
> + * @get_rx_ring size: get max number of elements the Rx ring can contain.
> + * @handle_eqe: Handle a received event.
> + */
> +struct hbl_en_asic_funcs {
> + int (*dev_init)(struct hbl_en_device *hdev);
> + void (*dev_fini)(struct hbl_en_device *hdev);
> + void (*reenable_rx_irq)(struct hbl_en_port *port);
> + int (*eth_port_open)(struct hbl_en_port *port);
> + void (*eth_port_close)(struct hbl_en_port *port);
> + netdev_tx_t (*write_pkt_to_hw)(struct hbl_en_port *port, struct sk_buff *skb);
> + int (*read_pkt_from_hw)(struct hbl_en_port *port, void **pkt_addr, u32 *pkt_size);
> + void (*get_pfc_cnts)(struct hbl_en_port *port, void *ptr);
> + int (*set_coalesce)(struct hbl_en_port *port);
> + int (*get_rx_ring_size)(struct hbl_en_port *port);
> + void (*handle_eqe)(struct hbl_aux_dev *aux_dev, u32 port_idx, struct hbl_cn_eqe *eqe);
> +};
> +
> +/**
> + * struct hbl_en_device - habanalabs Ethernet device structure.
> + * @pdev: pointer to PCI device.
> + * @dev: related kernel basic device structure.
> + * @ports: array of all ports manage common structures.
> + * @aux_dev: pointer to auxiliary device.
> + * @asic_specific: ASIC specific device structure.
> + * @fw_ver: FW version.
> + * @qsfp_eeprom: QSFPD EEPROM info.
> + * @mac_addr: array of all MAC addresses.
> + * @asic_funcs: ASIC specific Ethernet functions.
> + * @asic_type: ASIC specific type.
> + * @ports_mask: mask of available ports.
> + * @auto_neg_mask: mask of port with Autonegotiation enabled.
> + * @port_reset_timeout: max time in seconds for a port reset flow to finish.
> + * @pending_reset_long_timeout: long timeout for pending hard reset to finish in seconds.
> + * @max_frm_len: maximum allowed frame length.
> + * @raw_elem_size: size of element in raw buffers.
> + * @max_raw_mtu: maximum MTU size for raw packets.
> + * @min_raw_mtu: minimum MTU size for raw packets.
> + * @pad_size: the pad size in bytes for the skb to transmit.
> + * @core_dev_id: core device ID.
> + * @max_num_of_ports: max number of available ports;
> + * @in_reset: is the entire NIC currently under reset.
> + * @poll_enable: Enable Rx polling rather than IRQ + NAPI.
> + * @in_teardown: true if the NIC is in teardown (during device remove).
> + * @is_initialized: was the device initialized successfully.
> + * @has_eq: true if event queue is supported.
> + * @dma_map_support: HW supports DMA mapping.
> + */
> +struct hbl_en_device {
> + struct pci_dev *pdev;
> + struct device *dev;
> + struct hbl_en_port *ports;
> + struct hbl_aux_dev *aux_dev;
> + void *asic_specific;
> + char *fw_ver;
> + char *qsfp_eeprom;
> + char *mac_addr;
> + struct hbl_en_asic_funcs asic_funcs;
> + enum hbl_cn_asic_type asic_type;
> + u64 ports_mask;
> + u64 auto_neg_mask;
> + u32 port_reset_timeout;
> + u32 pending_reset_long_timeout;
> + u32 max_frm_len;
> + u32 raw_elem_size;
> + u16 max_raw_mtu;
> + u16 min_raw_mtu;
> + u16 pad_size;
> + u16 core_dev_id;
> + u8 max_num_of_ports;
> + u8 in_reset;
> + u8 poll_enable;
> + u8 in_teardown;
> + u8 is_initialized;
> + u8 has_eq;
> + u8 dma_map_support;
> +};
> +
> +int hbl_en_dev_init(struct hbl_en_device *hdev);
> +void hbl_en_dev_fini(struct hbl_en_device *hdev);
> +
> +const struct ethtool_ops *hbl_en_ethtool_get_ops(struct net_device *ndev);
> +void hbl_en_ethtool_init_coalesce(struct hbl_en_port *port);
> +
> +extern const struct dcbnl_rtnl_ops hbl_en_dcbnl_ops;
> +
> +bool hbl_en_rx_poll_start(struct hbl_en_port *port);
> +void hbl_en_rx_poll_stop(struct hbl_en_port *port);
> +void hbl_en_rx_poll_trigger_init(struct hbl_en_port *port);
> +int hbl_en_port_reset(struct hbl_en_port *port);
> +int hbl_en_port_reset_locked(struct hbl_aux_dev *aux_dev, u32 port_idx);
> +int hbl_en_handle_rx(struct hbl_en_port *port, int budget);
> +dma_addr_t hbl_en_dma_map(struct hbl_en_device *hdev, void *addr, int len);
> +void hbl_en_dma_unmap(struct hbl_en_device *hdev, dma_addr_t dma_addr, int len);
> +
> +#endif /* HABANALABS_EN_H_ */
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c
> new file mode 100644
> index 000000000000..5d718579a2b6
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c
> @@ -0,0 +1,101 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#include "hbl_en.h"
> +
> +#define PFC_PRIO_MASK_ALL GENMASK(HBL_EN_PFC_PRIO_NUM - 1, 0)
> +#define PFC_PRIO_MASK_NONE 0
> +
> +#ifdef CONFIG_DCB
> +static int hbl_en_dcbnl_ieee_getpfc(struct net_device *netdev, struct ieee_pfc *pfc)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + struct hbl_en_device *hdev;
> + u32 port_idx;
> +
> + hdev = port->hdev;
> + port_idx = port->idx;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + dev_dbg_ratelimited(hdev->dev, "port %d is in reset, can't get PFC", port_idx);
> + return -EBUSY;
> + }
> +
> + pfc->pfc_en = port->pfc_enable ? PFC_PRIO_MASK_ALL : PFC_PRIO_MASK_NONE;
> + pfc->pfc_cap = HBL_EN_PFC_PRIO_NUM;
> +
> + hdev->asic_funcs.get_pfc_cnts(port, pfc);
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return 0;
> +}
> +
> +static int hbl_en_dcbnl_ieee_setpfc(struct net_device *netdev, struct ieee_pfc *pfc)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + struct hbl_en_device *hdev;
> + u8 curr_pfc_en;
> + u32 port_idx;
> + int rc = 0;
> +
> + hdev = port->hdev;
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> + port_idx = port->idx;
> +
> + if (pfc->pfc_en & ~PFC_PRIO_MASK_ALL) {
> + dev_dbg_ratelimited(hdev->dev, "PFC supports %d priorities only, port %d\n",
> + HBL_EN_PFC_PRIO_NUM, port_idx);
> + return -EINVAL;
> + }
> +
> + if (pfc->pfc_en != PFC_PRIO_MASK_NONE && pfc->pfc_en != PFC_PRIO_MASK_ALL) {
> + dev_dbg_ratelimited(hdev->dev,
> + "PFC should be enabled/disabled on all priorities, port %d\n",
> + port_idx);
> + return -EINVAL;
> + }
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + dev_dbg_ratelimited(hdev->dev, "port %d is in reset, can't set PFC", port_idx);
> + return -EBUSY;
> + }
> +
> + curr_pfc_en = port->pfc_enable ? PFC_PRIO_MASK_ALL : PFC_PRIO_MASK_NONE;
> +
> + if (pfc->pfc_en == curr_pfc_en)
> + goto out;
> +
> + port->pfc_enable = !port->pfc_enable;
> +
> + rc = aux_ops->set_pfc(aux_dev, port_idx, port->pfc_enable);
> +
> +out:
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +static u8 hbl_en_dcbnl_getdcbx(struct net_device *netdev)
> +{
> + return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
> +}
> +
> +static u8 hbl_en_dcbnl_setdcbx(struct net_device *netdev, u8 mode)
> +{
> + return !(mode == (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE));
> +}
> +
> +const struct dcbnl_rtnl_ops hbl_en_dcbnl_ops = {
> + .ieee_getpfc = hbl_en_dcbnl_ieee_getpfc,
> + .ieee_setpfc = hbl_en_dcbnl_ieee_setpfc,
> + .getdcbx = hbl_en_dcbnl_getdcbx,
> + .setdcbx = hbl_en_dcbnl_setdcbx
> +};
> +#endif
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c
> new file mode 100644
> index 000000000000..23a87d36ded5
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c
> @@ -0,0 +1,211 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#define pr_fmt(fmt) "habanalabs_en: " fmt
> +
> +#include "hbl_en.h"
> +
> +#include <linux/module.h>
> +#include <linux/auxiliary_bus.h>
> +
> +#define HBL_DRIVER_AUTHOR "HabanaLabs Kernel Driver Team"
> +
> +#define HBL_DRIVER_DESC "HabanaLabs AI accelerators Ethernet driver"
> +
> +MODULE_AUTHOR(HBL_DRIVER_AUTHOR);
> +MODULE_DESCRIPTION(HBL_DRIVER_DESC);
> +MODULE_LICENSE("GPL");
> +
> +static bool poll_enable;
> +
> +module_param(poll_enable, bool, 0444);
> +MODULE_PARM_DESC(poll_enable,
> + "Enable Rx polling rather than IRQ + NAPI (0 = no, 1 = yes, default: no)");
> +
> +static int hdev_init(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_aux_data *aux_data = aux_dev->aux_data;
> + struct hbl_en_port *ports, *port;
> + struct hbl_en_device *hdev;
> + int rc, i;
> +
> + hdev = kzalloc(sizeof(*hdev), GFP_KERNEL);
> + if (!hdev)
> + return -ENOMEM;
> +
> + ports = kcalloc(aux_data->max_num_of_ports, sizeof(*ports), GFP_KERNEL);
> + if (!ports) {
> + rc = -ENOMEM;
> + goto ports_alloc_fail;
> + }
> +
> + aux_dev->priv = hdev;
> + hdev->aux_dev = aux_dev;
> + hdev->ports = ports;
> + hdev->pdev = aux_data->pdev;
> + hdev->dev = aux_data->dev;
> + hdev->ports_mask = aux_data->ports_mask;
> + hdev->auto_neg_mask = aux_data->auto_neg_mask;
> + hdev->max_num_of_ports = aux_data->max_num_of_ports;
> + hdev->core_dev_id = aux_data->id;
> + hdev->fw_ver = aux_data->fw_ver;
> + hdev->qsfp_eeprom = aux_data->qsfp_eeprom;
> + hdev->asic_type = aux_data->asic_type;
> + hdev->pending_reset_long_timeout = aux_data->pending_reset_long_timeout;
> + hdev->max_frm_len = aux_data->max_frm_len;
> + hdev->raw_elem_size = aux_data->raw_elem_size;
> + hdev->max_raw_mtu = aux_data->max_raw_mtu;
> + hdev->min_raw_mtu = aux_data->min_raw_mtu;
> + hdev->pad_size = ETH_ZLEN;
> + hdev->has_eq = aux_data->has_eq;
> + hdev->dma_map_support = true;
> + hdev->poll_enable = poll_enable;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> + port->hdev = hdev;
> + port->idx = i;
> + port->pfc_enable = true;
> + port->pflags = PFLAGS_PCS_LINK_CHECK | PFLAGS_PHY_AUTO_NEG_LPBK;
> + port->mac_addr = aux_data->mac_addr[i];
> + port->auto_neg_enable = !!(aux_data->auto_neg_mask & BIT(i));
> + }
> +
> + return 0;
> +
> +ports_alloc_fail:
> + kfree(hdev);
> +
> + return rc;
> +}
> +
> +static void hdev_fini(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> +
> + kfree(hdev->ports);
> + kfree(hdev);
> + aux_dev->priv = NULL;
> +}
> +
> +static const struct auxiliary_device_id hbl_en_id_table[] = {
> + { .name = "habanalabs_cn.en", },
> + {},
> +};
> +
> +MODULE_DEVICE_TABLE(auxiliary, hbl_en_id_table);
> +
> +static int hbl_en_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
> +{
> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
> + struct hbl_en_aux_ops *aux_ops = aux_dev->aux_ops;
> + struct hbl_en_device *hdev;
> + ktime_t timeout;
> + int rc;
> +
> + rc = hdev_init(aux_dev);
> + if (rc) {
> + dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
> + return -EIO;
> + }
> +
> + hdev = aux_dev->priv;
> +
> + /* don't allow module unloading while it is attached */
> + if (!try_module_get(THIS_MODULE)) {
> + dev_err(hdev->dev, "Failed to increment %s module refcount\n", HBL_EN_NAME);
> + rc = -EIO;
> + goto module_get_err;
> + }
> +
> + timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
> + while (1) {
> + aux_ops->hw_access_lock(aux_dev);
> +
> + /* if the device is operational, proceed to actual init while holding the lock in
> + * order to prevent concurrent hard reset
> + */
> + if (aux_ops->device_operational(aux_dev))
> + break;
> +
> + aux_ops->hw_access_unlock(aux_dev);
> +
> + if (ktime_compare(ktime_get(), timeout) > 0) {
> + dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
> + rc = -EBUSY;
> + goto timeout_err;
> + }
> +
> + dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing en\n");
> +
> + msleep_interruptible(MSEC_PER_SEC);
> + }
> +
> + rc = hbl_en_dev_init(hdev);
> + if (rc) {
> + dev_err(hdev->dev, "Failed to init en device\n");
> + goto dev_init_err;
> + }
> +
> + aux_ops->hw_access_unlock(aux_dev);
> +
> + return 0;
> +
> +dev_init_err:
> + aux_ops->hw_access_unlock(aux_dev);
> +timeout_err:
> + module_put(THIS_MODULE);
> +module_get_err:
> + hdev_fini(aux_dev);
> +
> + return rc;
> +}
> +
> +/* This function can be called only from the CN driver when deleting the aux bus, because we
> + * incremented the module refcount on probing. Hence no need to protect here from hard reset.
> + */
> +static void hbl_en_remove(struct auxiliary_device *adev)
> +{
> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
> + struct hbl_en_device *hdev = aux_dev->priv;
> +
> + if (!hdev)
> + return;
> +
> + hbl_en_dev_fini(hdev);
> +
> + /* allow module unloading as now it is detached */
> + module_put(THIS_MODULE);
> +
> + hdev_fini(aux_dev);
> +}
> +
> +static struct auxiliary_driver hbl_en_driver = {
> + .name = "eth",
> + .probe = hbl_en_probe,
> + .remove = hbl_en_remove,
> + .id_table = hbl_en_id_table,
> +};
> +
> +static int __init hbl_en_init(void)
> +{
> + pr_info("loading driver\n");
> +
> + return auxiliary_driver_register(&hbl_en_driver);
> +}
> +
> +static void __exit hbl_en_exit(void)
> +{
> + auxiliary_driver_unregister(&hbl_en_driver);
> +
> + pr_info("driver removed\n");
> +}
> +
> +module_init(hbl_en_init);
> +module_exit(hbl_en_exit);
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c
> new file mode 100644
> index 000000000000..1d14d283409b
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c
> @@ -0,0 +1,452 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#include "hbl_en.h"
> +#include <linux/ethtool.h>
> +
> +#define RX_COALESCED_FRAMES_MIN 1
> +#define TX_COALESCED_FRAMES_MIN 1
> +#define TX_COALESCED_FRAMES_MAX 10
> +
> +static const char pflags_str[][ETH_GSTRING_LEN] = {
> + "pcs-link-check",
> + "phy-auto-neg-lpbk",
> +};
> +
> +#define NIC_STAT(m) {#m, offsetof(struct hbl_en_port, net_stats.m)}
> +
> +static struct hbl_cn_stat netdev_eth_stats[] = {
> + NIC_STAT(rx_packets),
> + NIC_STAT(tx_packets),
> + NIC_STAT(rx_bytes),
> + NIC_STAT(tx_bytes),
> + NIC_STAT(tx_errors),
> + NIC_STAT(rx_dropped),
> + NIC_STAT(tx_dropped)
> +};
> +
> +static size_t pflags_str_len = ARRAY_SIZE(pflags_str);
> +static size_t netdev_eth_stats_len = ARRAY_SIZE(netdev_eth_stats);
> +
> +static void hbl_en_ethtool_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *drvinfo)
> +{
> + struct hbl_en_device *hdev;
> + struct hbl_en_port *port;
> +
> + port = hbl_netdev_priv(ndev);
> + hdev = port->hdev;
> +
> + strscpy(drvinfo->driver, HBL_EN_NAME, sizeof(drvinfo->driver));
> + strscpy(drvinfo->fw_version, hdev->fw_ver, sizeof(drvinfo->fw_version));
> + strscpy(drvinfo->bus_info, pci_name(hdev->pdev), sizeof(drvinfo->bus_info));
> +}
> +
> +static int hbl_en_ethtool_get_module_info(struct net_device *ndev, struct ethtool_modinfo *modinfo)
> +{
> + modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
> + modinfo->type = ETH_MODULE_SFF_8636;
> +
> + return 0;
> +}
> +
> +static int hbl_en_ethtool_get_module_eeprom(struct net_device *ndev, struct ethtool_eeprom *ee,
> + u8 *data)
> +{
> + struct hbl_en_device *hdev;
> + struct hbl_en_port *port;
> + u32 first, last, len;
> + u8 *qsfp_eeprom;
> +
> + port = hbl_netdev_priv(ndev);
> + hdev = port->hdev;
> + qsfp_eeprom = hdev->qsfp_eeprom;
> +
> + if (ee->len == 0)
> + return -EINVAL;
> +
> + first = ee->offset;
> + last = ee->offset + ee->len;
> +
> + if (first < ETH_MODULE_SFF_8636_LEN) {
> + len = min_t(unsigned int, last, ETH_MODULE_SFF_8079_LEN);
> + len -= first;
> +
> + memcpy(data, qsfp_eeprom + first, len);
> + }
> +
> + return 0;
> +}
> +
> +static u32 hbl_en_ethtool_get_priv_flags(struct net_device *ndev)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> +
> + return port->pflags;
> +}
> +
> +static int hbl_en_ethtool_set_priv_flags(struct net_device *ndev, u32 priv_flags)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> +
> + port->pflags = priv_flags;
> +
> + return 0;
> +}
> +
> +static int hbl_en_ethtool_get_link_ksettings(struct net_device *ndev,
> + struct ethtool_link_ksettings *cmd)
> +{
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + struct hbl_en_device *hdev;
> + struct hbl_en_port *port;
> + u32 port_idx, speed;
> +
> + port = hbl_netdev_priv(ndev);
> + hdev = port->hdev;
> + port_idx = port->idx;
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> + speed = aux_ops->get_speed(aux_dev, port_idx);
> +
> + cmd->base.speed = speed;
> + cmd->base.duplex = DUPLEX_FULL;
> +
> + ethtool_link_ksettings_zero_link_mode(cmd, supported);
> + ethtool_link_ksettings_zero_link_mode(cmd, advertising);
> +
> + switch (speed) {
> + case SPEED_100000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseSR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseKR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseLR4_ER4_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseSR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseKR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseLR4_ER4_Full);
> +
> + cmd->base.port = PORT_FIBRE;
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Backplane);
> + break;
> + case SPEED_50000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseSR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseCR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseKR2_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseSR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseCR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseKR2_Full);
> + break;
> + case SPEED_25000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 25000baseCR_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 25000baseCR_Full);
> + break;
> + case SPEED_200000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 200000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 200000baseKR4_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 200000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 200000baseKR4_Full);
> + break;
> + case SPEED_400000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 400000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 400000baseKR4_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 400000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 400000baseKR4_Full);
> + break;
> + default:
> + netdev_err(port->ndev, "unknown speed %d\n", speed);
> + return -EFAULT;
> + }
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
> +
> + if (port->auto_neg_enable) {
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
> + cmd->base.autoneg = AUTONEG_ENABLE;
> + if (port->auto_neg_resolved)
> + ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
> + } else {
> + cmd->base.autoneg = AUTONEG_DISABLE;
> + }
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
> +
> + if (port->pfc_enable)
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause);
> +
> + return 0;
> +}
> +
> +/* only autoneg is mutable */
> +static bool check_immutable_ksettings(const struct ethtool_link_ksettings *old_cmd,
> + const struct ethtool_link_ksettings *new_cmd)
> +{
> + return (old_cmd->base.speed == new_cmd->base.speed) &&
> + (old_cmd->base.duplex == new_cmd->base.duplex) &&
> + (old_cmd->base.port == new_cmd->base.port) &&
> + (old_cmd->base.phy_address == new_cmd->base.phy_address) &&
> + (old_cmd->base.eth_tp_mdix_ctrl == new_cmd->base.eth_tp_mdix_ctrl) &&
> + bitmap_equal(old_cmd->link_modes.advertising, new_cmd->link_modes.advertising,
> + __ETHTOOL_LINK_MODE_MASK_NBITS);
> +}
> +
> +static int
> +hbl_en_ethtool_set_link_ksettings(struct net_device *ndev, const struct ethtool_link_ksettings *cmd)
> +{
> + struct ethtool_link_ksettings curr_cmd;
> + struct hbl_en_device *hdev;
> + struct hbl_en_port *port;
> + bool auto_neg;
> + u32 port_idx;
> + int rc;
> +
> + port = hbl_netdev_priv(ndev);
> + hdev = port->hdev;
> + port_idx = port->idx;
> +
> + memset(&curr_cmd, 0, sizeof(struct ethtool_link_ksettings));
> +
> + rc = hbl_en_ethtool_get_link_ksettings(ndev, &curr_cmd);
> + if (rc)
> + return rc;
> +
> + if (!check_immutable_ksettings(&curr_cmd, cmd))
> + return -EOPNOTSUPP;
> +
> + auto_neg = cmd->base.autoneg == AUTONEG_ENABLE;
> +
> + if (port->auto_neg_enable == auto_neg)
> + return 0;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(port->ndev, "port is in reset, can't update settings\n");
> + return -EBUSY;
> + }
> +
> + if (auto_neg && !(hdev->auto_neg_mask & BIT(port_idx))) {
> + netdev_err(port->ndev, "port autoneg is disabled by BMC\n");
> + rc = -EFAULT;
> + goto out;
> + }
> +
> + port->auto_neg_enable = auto_neg;
> +
> + if (netif_running(port->ndev)) {
> + rc = hbl_en_port_reset(port);
> + if (rc)
> + netdev_err(port->ndev, "Failed to reset port for settings update, rc %d\n",
> + rc);
> + }
> +
> +out:
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +static int hbl_en_ethtool_get_sset_count(struct net_device *ndev, int sset)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + switch (sset) {
> + case ETH_SS_STATS:
> + return netdev_eth_stats_len + aux_ops->get_cnts_num(aux_dev, port_idx);
> + case ETH_SS_PRIV_FLAGS:
> + return pflags_str_len;
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static void hbl_en_ethtool_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int i;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + switch (stringset) {
> + case ETH_SS_STATS:
> + for (i = 0; i < netdev_eth_stats_len; i++)
> + ethtool_puts(&data, netdev_eth_stats[i].str);
> +
> + aux_ops->get_cnts_names(aux_dev, port_idx, data);
> + break;
> + case ETH_SS_PRIV_FLAGS:
> + for (i = 0; i < pflags_str_len; i++)
> + ethtool_puts(&data, pflags_str[i]);
> + break;
> + }
> +}
> +
> +static void hbl_en_ethtool_get_ethtool_stats(struct net_device *ndev,
> + __always_unused struct ethtool_stats *stats, u64 *data)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + struct hbl_en_device *hdev;
> + u32 port_idx;
> + char *p;
> + int i;
> +
> + hdev = port->hdev;
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> + port_idx = port->idx;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + dev_info_ratelimited(hdev->dev, "port %d is in reset, can't get ethtool stats",
> + port_idx);
> + return;
> + }
> +
> + /* Even though the Ethernet Rx/Tx flow might update the stats in parallel, there is not an
> + * absolute need for synchronisation. This is because, missing few counts of these stats is
> + * much better than adding a lock to synchronize and increase the overhead of the Rx/Tx
> + * flows. In worst case scenario, reader will get stale stats. He will receive updated
> + * stats in next read.
> + */
> + for (i = 0; i < netdev_eth_stats_len; i++) {
> + p = (char *)port + netdev_eth_stats[i].lo_offset;
> + data[i] = *(u32 *)p;
> + }
> +
> + data += i;
> +
> + aux_ops->get_cnts_values(aux_dev, port_idx, data);
> +
> + atomic_set(&port->in_reset, 0);
> +}
> +
> +static int hbl_en_ethtool_get_coalesce(struct net_device *ndev,
> + struct ethtool_coalesce *coal,
> + struct kernel_ethtool_coalesce *kernel_coal,
> + struct netlink_ext_ack *extack)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + aux_ops->ctrl_lock(aux_dev, port_idx);
> +
> + coal->tx_max_coalesced_frames = port->tx_max_coalesced_frames;
> + coal->rx_coalesce_usecs = port->rx_coalesce_usecs;
> + coal->rx_max_coalesced_frames = port->rx_max_coalesced_frames;
> +
> + aux_ops->ctrl_unlock(aux_dev, port_idx);
> +
> + return 0;
> +}
> +
> +static int hbl_en_ethtool_set_coalesce(struct net_device *ndev,
> + struct ethtool_coalesce *coal,
> + struct kernel_ethtool_coalesce *kernel_coal,
> + struct netlink_ext_ack *extack)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int rc, rx_ring_size;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(port->ndev, "port is in reset, can't update settings\n");
> + return -EBUSY;
> + }
> +
> + if (coal->tx_max_coalesced_frames < TX_COALESCED_FRAMES_MIN ||
> + coal->tx_max_coalesced_frames > TX_COALESCED_FRAMES_MAX) {
> + netdev_err(ndev, "tx max_coalesced_frames should be between %d and %d\n",
> + TX_COALESCED_FRAMES_MIN, TX_COALESCED_FRAMES_MAX);
> + rc = -EINVAL;
> + goto atomic_out;
> + }
> +
> + rx_ring_size = hdev->asic_funcs.get_rx_ring_size(port);
> + if (coal->rx_max_coalesced_frames < RX_COALESCED_FRAMES_MIN ||
> + coal->rx_max_coalesced_frames >= rx_ring_size) {
> + netdev_err(ndev, "rx max_coalesced_frames should be between %d and %d\n",
> + RX_COALESCED_FRAMES_MIN, rx_ring_size);
> + rc = -EINVAL;
> + goto atomic_out;
> + }
> +
> + aux_ops->ctrl_lock(aux_dev, port_idx);
> +
> + port->tx_max_coalesced_frames = coal->tx_max_coalesced_frames;
> + port->rx_coalesce_usecs = coal->rx_coalesce_usecs;
> + port->rx_max_coalesced_frames = coal->rx_max_coalesced_frames;
> +
> + rc = hdev->asic_funcs.set_coalesce(port);
> +
> + aux_ops->ctrl_unlock(aux_dev, port_idx);
> +
> +atomic_out:
> + atomic_set(&port->in_reset, 0);
> + return rc;
> +}
> +
> +void hbl_en_ethtool_init_coalesce(struct hbl_en_port *port)
> +{
> + port->rx_coalesce_usecs = CQ_ARM_TIMEOUT_USEC;
> + port->rx_max_coalesced_frames = 1;
> + port->tx_max_coalesced_frames = 1;
> +}
> +
> +static const struct ethtool_ops hbl_en_ethtool_ops_coalesce = {
> + .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | ETHTOOL_COALESCE_RX_MAX_FRAMES |
> + ETHTOOL_COALESCE_TX_MAX_FRAMES,
> + .get_drvinfo = hbl_en_ethtool_get_drvinfo,
> + .get_link = ethtool_op_get_link,
> + .get_module_info = hbl_en_ethtool_get_module_info,
> + .get_module_eeprom = hbl_en_ethtool_get_module_eeprom,
> + .get_priv_flags = hbl_en_ethtool_get_priv_flags,
> + .set_priv_flags = hbl_en_ethtool_set_priv_flags,
> + .get_link_ksettings = hbl_en_ethtool_get_link_ksettings,
> + .set_link_ksettings = hbl_en_ethtool_set_link_ksettings,
> + .get_sset_count = hbl_en_ethtool_get_sset_count,
> + .get_strings = hbl_en_ethtool_get_strings,
> + .get_ethtool_stats = hbl_en_ethtool_get_ethtool_stats,
> + .get_coalesce = hbl_en_ethtool_get_coalesce,
> + .set_coalesce = hbl_en_ethtool_set_coalesce,
> +};
> +
> +const struct ethtool_ops *hbl_en_ethtool_get_ops(struct net_device *ndev)
> +{
> + return &hbl_en_ethtool_ops_coalesce;
> +}
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-13 8:22 ` [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver Omer Shpigelman
` (4 preceding siblings ...)
2024-06-15 10:55 ` Zhu Yanjun
@ 2024-06-15 17:13 ` Zhu Yanjun
2024-06-16 1:08 ` Andrew Lunn
5 siblings, 1 reply; 108+ messages in thread
From: Zhu Yanjun @ 2024-06-15 17:13 UTC (permalink / raw)
To: Omer Shpigelman, linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, zyehudai
在 2024/6/13 16:22, Omer Shpigelman 写道:
> This ethernet driver is initialized via auxiliary bus by the hbl_cn
> driver.
> It serves mainly for control operations that are needed for AI scaling.
>
> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> Co-developed-by: David Meriin <dmeriin@habana.ai>
> Signed-off-by: David Meriin <dmeriin@habana.ai>
> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
> ---
> MAINTAINERS | 9 +
> drivers/net/ethernet/intel/Kconfig | 18 +
> drivers/net/ethernet/intel/Makefile | 1 +
> drivers/net/ethernet/intel/hbl_en/Makefile | 9 +
> .../net/ethernet/intel/hbl_en/common/Makefile | 3 +
> .../net/ethernet/intel/hbl_en/common/hbl_en.c | 1168 +++++++++++++++++
> .../net/ethernet/intel/hbl_en/common/hbl_en.h | 206 +++
> .../intel/hbl_en/common/hbl_en_dcbnl.c | 101 ++
> .../ethernet/intel/hbl_en/common/hbl_en_drv.c | 211 +++
> .../intel/hbl_en/common/hbl_en_ethtool.c | 452 +++++++
> 10 files changed, 2178 insertions(+)
> create mode 100644 drivers/net/ethernet/intel/hbl_en/Makefile
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/Makefile
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 096439a62129..7301f38e9cfb 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -9617,6 +9617,15 @@ F: include/linux/habanalabs/
> F: include/linux/net/intel/cn*
> F: include/linux/net/intel/gaudi2*
>
> +HABANALABS ETHERNET DRIVER
> +M: Omer Shpigelman <oshpigelman@habana.ai>
> +L: netdev@vger.kernel.org
> +S: Supported
> +W: https://www.habana.ai
> +F: Documentation/networking/device_drivers/ethernet/intel/hbl.rst
> +F: drivers/net/ethernet/intel/hbl_en/
> +F: include/linux/net/intel/cn*
> +
> HACKRF MEDIA DRIVER
> L: linux-media@vger.kernel.org
> S: Orphan
> diff --git a/drivers/net/ethernet/intel/Kconfig b/drivers/net/ethernet/intel/Kconfig
> index 0d1b8a2bae99..5d07349348a0 100644
> --- a/drivers/net/ethernet/intel/Kconfig
> +++ b/drivers/net/ethernet/intel/Kconfig
> @@ -417,4 +417,22 @@ config HABANA_CN
> To compile this driver as a module, choose M here. The module
> will be called habanalabs_cn.
>
> +config HABANA_EN
> + tristate "HabanaLabs (an Intel Company) Ethernet driver"
> + depends on NETDEVICES && ETHERNET && INET
> + select HABANA_CN
> + help
> + This driver enables Ethernet functionality for the network interfaces
> + that are part of the GAUDI ASIC family of AI Accelerators.
> + For more information on how to identify your adapter, go to the
> + Adapter & Driver ID Guide that can be located at:
> +
> + <http://support.intel.com>
> +
> + More specific information on configuring the driver is in
> + <file:Documentation/networking/device_drivers/ethernet/intel/hbl.rst>.
> +
> + To compile this driver as a module, choose M here. The module
> + will be called habanalabs_en.
> +
> endif # NET_VENDOR_INTEL
> diff --git a/drivers/net/ethernet/intel/Makefile b/drivers/net/ethernet/intel/Makefile
> index 10049a28e336..ec62a0227897 100644
> --- a/drivers/net/ethernet/intel/Makefile
> +++ b/drivers/net/ethernet/intel/Makefile
> @@ -20,3 +20,4 @@ obj-$(CONFIG_FM10K) += fm10k/
> obj-$(CONFIG_ICE) += ice/
> obj-$(CONFIG_IDPF) += idpf/
> obj-$(CONFIG_HABANA_CN) += hbl_cn/
> +obj-$(CONFIG_HABANA_EN) += hbl_en/
> diff --git a/drivers/net/ethernet/intel/hbl_en/Makefile b/drivers/net/ethernet/intel/hbl_en/Makefile
> new file mode 100644
> index 000000000000..695497ab93b6
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/Makefile
> @@ -0,0 +1,9 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +#
> +# Makefile for HabanaLabs (an Intel Company) Ethernet network driver
> +#
> +
> +obj-$(CONFIG_HABANA_EN) := habanalabs_en.o
> +
> +include $(src)/common/Makefile
> +habanalabs_en-y += $(HBL_EN_COMMON_FILES)
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/Makefile b/drivers/net/ethernet/intel/hbl_en/common/Makefile
> new file mode 100644
> index 000000000000..a3ccb5dbf4a6
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +HBL_EN_COMMON_FILES := common/hbl_en_drv.o common/hbl_en.o \
> + common/hbl_en_ethtool.o common/hbl_en_dcbnl.o
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
> new file mode 100644
> index 000000000000..066be5ac2d84
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
> @@ -0,0 +1,1168 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#include "hbl_en.h"
> +#include <linux/inetdevice.h>
> +
> +#define TX_TIMEOUT (5 * HZ)
> +#define PORT_RESET_TIMEOUT_MSEC (60 * 1000ull) /* 60s */
> +
> +/**
> + * struct hbl_en_tx_pkt_work - used to schedule a work of a Tx packet.
> + * @tx_work: workqueue object to run when packet needs to be sent.
> + * @port: pointer to current port structure.
> + * @skb: copy of the packet to send.
> + */
> +struct hbl_en_tx_pkt_work {
> + struct work_struct tx_work;
> + struct hbl_en_port *port;
> + struct sk_buff *skb;
> +};
> +
> +static int hbl_en_napi_poll(struct napi_struct *napi, int budget);
> +static int hbl_en_port_open(struct hbl_en_port *port);
> +
> +static int hbl_en_ports_reopen(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> + struct hbl_en_port *port;
> + int rc = 0, i;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + /* It could be that the port was shutdown by 'ip link set down' and there is no need
> + * in reopening it.
> + * Since we mark the ports as in reset even if they are disabled, we clear the flag
> + * here anyway.
> + * See hbl_en_ports_stop_prepare() for more info.
> + */
> + if (!netif_running(port->ndev)) {
> + atomic_set(&port->in_reset, 0);
> + continue;
> + }
> +
> + rc = hbl_en_port_open(port);
> +
> + atomic_set(&port->in_reset, 0);
> +
> + if (rc)
> + break;
> + }
> +
> + hdev->in_reset = false;
> +
> + return rc;
> +}
> +
> +static void hbl_en_port_fini(struct hbl_en_port *port)
> +{
> + if (port->rx_wq)
> + destroy_workqueue(port->rx_wq);
> +}
> +
> +static int hbl_en_port_init(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + u32 port_idx = port->idx;
> + char wq_name[32];
> + int rc;
> +
> + if (hdev->poll_enable) {
> + memset(wq_name, 0, sizeof(wq_name));
> + snprintf(wq_name, sizeof(wq_name) - 1, "hbl%u-port%d-rx-wq", hdev->core_dev_id,
> + port_idx);
> + port->rx_wq = alloc_ordered_workqueue(wq_name, 0);
> + if (!port->rx_wq) {
> + dev_err(hdev->dev, "Failed to allocate Rx WQ\n");
> + rc = -ENOMEM;
> + goto fail;
> + }
> + }
> +
> + hbl_en_ethtool_init_coalesce(port);
> +
> + return 0;
> +
> +fail:
> + hbl_en_port_fini(port);
> +
> + return rc;
> +}
> +
> +static void _hbl_en_set_port_status(struct hbl_en_port *port, bool up)
> +{
> + struct net_device *ndev = port->ndev;
> + u32 port_idx = port->idx;
> +
> + if (up) {
> + netif_carrier_on(ndev);
> + netif_wake_queue(ndev);
> + } else {
> + netif_carrier_off(ndev);
> + netif_stop_queue(ndev);
> + }
> +
> + /* Unless link events are getting through the EQ, no need to print about link down events
> + * during port reset
> + */
> + if (port->hdev->has_eq || up || !atomic_read(&port->in_reset))
> + netdev_info(port->ndev, "link %s, port %d\n", up ? "up" : "down", port_idx);
> +}
> +
> +static void hbl_en_set_port_status(struct hbl_aux_dev *aux_dev, u32 port_idx, bool up)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + _hbl_en_set_port_status(port, up);
> +}
> +
> +static bool hbl_en_is_port_open(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + return port->is_initialized;
> +}
> +
> +/* get the src IP as it is done in devinet_ioctl() */
> +static int hbl_en_get_src_ip(struct hbl_aux_dev *aux_dev, u32 port_idx, u32 *src_ip)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> + struct net_device *ndev = port->ndev;
> + struct in_device *in_dev;
> + struct in_ifaddr *ifa;
> + int rc = 0;
> +
> + /* for the case where no src IP is configured */
> + *src_ip = 0;
> +
> + /* rtnl lock should be acquired in relevant flows before taking configuration lock */
> + if (!rtnl_is_locked()) {
> + netdev_err(port->ndev, "Rtnl lock is not acquired, can't proceed\n");
> + rc = -EFAULT;
> + goto out;
> + }
> +
> + in_dev = __in_dev_get_rtnl(ndev);
> + if (!in_dev) {
> + netdev_err(port->ndev, "Failed to get IPv4 struct\n");
> + rc = -EFAULT;
> + goto out;
> + }
> +
> + ifa = rtnl_dereference(in_dev->ifa_list);
> +
> + while (ifa) {
> + if (!strcmp(ndev->name, ifa->ifa_label)) {
> + /* convert the BE to native and later on it will be
> + * written to the HW as LE in QPC_SET
> + */
> + *src_ip = be32_to_cpu(ifa->ifa_local);
> + break;
> + }
> + ifa = rtnl_dereference(ifa->ifa_next);
> + }
> +out:
> + return rc;
> +}
> +
> +static void hbl_en_reset_stats(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + port->net_stats.rx_packets = 0;
> + port->net_stats.tx_packets = 0;
> + port->net_stats.rx_bytes = 0;
> + port->net_stats.tx_bytes = 0;
> + port->net_stats.tx_errors = 0;
> + atomic64_set(&port->net_stats.rx_dropped, 0);
> + atomic64_set(&port->net_stats.tx_dropped, 0);
per-cpu variable is better?
Zhu Yanjun
> +}
> +
> +static u32 hbl_en_get_mtu(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> + struct net_device *ndev = port->ndev;
> + u32 mtu;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(ndev, "port is in reset, can't get MTU\n");
> + return 0;
> + }
> +
> + mtu = ndev->mtu;
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return mtu;
> +}
> +
> +static u32 hbl_en_get_pflags(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + return port->pflags;
> +}
> +
> +static void hbl_en_set_dev_lpbk(struct hbl_aux_dev *aux_dev, u32 port_idx, bool enable)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> + struct net_device *ndev = port->ndev;
> +
> + if (enable)
> + ndev->features |= NETIF_F_LOOPBACK;
> + else
> + ndev->features &= ~NETIF_F_LOOPBACK;
> +}
> +
> +/* This function should be called after ctrl_lock was taken */
> +static int hbl_en_port_open_locked(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct net_device *ndev = port->ndev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int rc;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + if (port->is_initialized)
> + return 0;
> +
> + if (!hdev->poll_enable)
> + netif_napi_add(ndev, &port->napi, hbl_en_napi_poll);
> +
> + rc = aux_ops->port_hw_init(aux_dev, port_idx);
> + if (rc) {
> + netdev_err(ndev, "Failed to configure the HW, rc %d\n", rc);
> + goto hw_init_fail;
> + }
> +
> + if (!hdev->poll_enable)
> + napi_enable(&port->napi);
> +
> + rc = hdev->asic_funcs.eth_port_open(port);
> + if (rc) {
> + netdev_err(ndev, "Failed to init H/W, rc %d\n", rc);
> + goto port_open_fail;
> + }
> +
> + rc = aux_ops->update_mtu(aux_dev, port_idx, ndev->mtu);
> + if (rc) {
> + netdev_err(ndev, "MTU update failed, rc %d\n", rc);
> + goto update_mtu_fail;
> + }
> +
> + rc = aux_ops->phy_init(aux_dev, port_idx);
> + if (rc) {
> + netdev_err(ndev, "PHY init failed, rc %d\n", rc);
> + goto phy_init_fail;
> + }
> +
> + netif_start_queue(ndev);
> +
> + port->is_initialized = true;
> +
> + return 0;
> +
> +phy_init_fail:
> + /* no need to revert the MTU change, it will be updated on next port open */
> +update_mtu_fail:
> + hdev->asic_funcs.eth_port_close(port);
> +port_open_fail:
> + if (!hdev->poll_enable)
> + napi_disable(&port->napi);
> +
> + aux_ops->port_hw_fini(aux_dev, port_idx);
> +hw_init_fail:
> + if (!hdev->poll_enable)
> + netif_napi_del(&port->napi);
> +
> + return rc;
> +}
> +
> +static int hbl_en_port_open(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int rc;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + aux_ops->ctrl_lock(aux_dev, port_idx);
> + rc = hbl_en_port_open_locked(port);
> + aux_ops->ctrl_unlock(aux_dev, port_idx);
> +
> + return rc;
> +}
> +
> +static int hbl_en_open(struct net_device *netdev)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + int rc;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(netdev, "port is in reset, can't open it\n");
> + return -EBUSY;
> + }
> +
> + rc = hbl_en_port_open(port);
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +/* This function should be called after ctrl_lock was taken */
> +static void hbl_en_port_close_locked(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + if (!port->is_initialized)
> + return;
> +
> + port->is_initialized = false;
> +
> + /* verify that the port is marked as closed before continuing */
> + mb();
> +
> + /* Print if not in hard reset flow e.g. from ip cmd */
> + if (!hdev->in_reset && netif_carrier_ok(port->ndev))
> + netdev_info(port->ndev, "port was closed\n");
> +
> + /* disable the PHY here so no link changes will occur from this point forward */
> + aux_ops->phy_fini(aux_dev, port_idx);
> +
> + /* disable Tx SW flow */
> + netif_carrier_off(port->ndev);
> + netif_tx_disable(port->ndev);
> +
> + /* stop Tx/Rx HW */
> + aux_ops->port_hw_fini(aux_dev, port_idx);
> +
> + /* disable Tx/Rx QPs */
> + hdev->asic_funcs.eth_port_close(port);
> +
> + /* stop Rx SW flow */
> + if (hdev->poll_enable) {
> + hbl_en_rx_poll_stop(port);
> + } else {
> + napi_disable(&port->napi);
> + netif_napi_del(&port->napi);
> + }
> +
> + /* Explicitly count the port close operations as we don't get a link event for this.
> + * Upon port open we receive a link event, hence no additional action required.
> + */
> + aux_ops->port_toggle_count(aux_dev, port_idx);
> +}
> +
> +static void hbl_en_port_close(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + aux_ops->ctrl_lock(aux_dev, port_idx);
> + hbl_en_port_close_locked(port);
> + aux_ops->ctrl_unlock(aux_dev, port_idx);
> +}
> +
> +/* This function should be called after ctrl_lock was taken */
> +static int __hbl_en_port_reset_locked(struct hbl_en_port *port)
> +{
> + hbl_en_port_close_locked(port);
> +
> + return hbl_en_port_open_locked(port);
> +}
> +
> +/* This function should be called after ctrl_lock was taken */
> +int hbl_en_port_reset_locked(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> +
> + return __hbl_en_port_reset_locked(port);
> +}
> +
> +int hbl_en_port_reset(struct hbl_en_port *port)
> +{
> + hbl_en_port_close(port);
> +
> + /* Sleep in order to let obsolete events to be dropped before re-opening the port */
> + msleep(20);
> +
> + return hbl_en_port_open(port);
> +}
> +
> +static int hbl_en_close(struct net_device *netdev)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + struct hbl_en_device *hdev = port->hdev;
> + ktime_t timeout;
> +
> + /* Looks like the return value of this function is not checked, so we can't just return
> + * EBUSY if the port is under reset. We need to wait until the reset is finished and then
> + * close the port. Otherwise the netdev will set the port as closed although port_close()
> + * wasn't called. Only if we waited long enough and the reset hasn't finished, we can return
> + * an error without actually closing the port as it is a fatal flow anyway.
> + */
> + timeout = ktime_add_ms(ktime_get(), PORT_RESET_TIMEOUT_MSEC);
> + while (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + /* If this is called from unregister_netdev() then the port was already closed and
> + * hence we can safely return.
> + * We could have just check the port_open boolean, but that might hide some future
> + * bugs. Hence it is better to use a dedicated flag for that.
> + */
> + if (READ_ONCE(hdev->in_teardown))
> + return 0;
> +
> + usleep_range(50, 200);
> + if (ktime_compare(ktime_get(), timeout) > 0) {
> + netdev_crit(netdev,
> + "Timeout while waiting for port to finish reset, can't close it\n"
> + );
> + return -EBUSY;
> + }
> + }
> +
> + hbl_en_port_close(port);
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return 0;
> +}
> +
> +/**
> + * hbl_en_ports_stop_prepare() - stop the Rx and Tx and synchronize with other reset flows.
> + * @aux_dev: habanalabs auxiliary device structure.
> + *
> + * This function makes sure that during the reset no packets will be processed and that
> + * ndo_open/ndo_close do not open/close the ports.
> + * A hard reset might occur right after the driver was loaded, which means before the ports
> + * initialization was finished. Therefore, even if the ports are not yet open, we mark it as in
> + * reset in order to avoid races. We clear the in reset flag later on when reopening the ports.
> + */
> +static void hbl_en_ports_stop_prepare(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> + struct hbl_en_port *port;
> + ktime_t timeout;
> + int i;
> +
> + /* Check if the ports where initialized. If not, we shouldn't mark them as in reset because
> + * they will fail to get opened.
> + */
> + if (!hdev->is_initialized || hdev->in_reset)
> + return;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + /* This function is competing with reset from ethtool/ip, so try to take the
> + * in_reset atomic and if we are already in a middle of reset, wait until reset
> + * function is finished.
> + * Reset function is designed to always finish (could take up to a few seconds in
> + * worst case).
> + * We mark also closed ports as in reset so they won't be able to get opened while
> + * the device in under reset.
> + */
> +
> + timeout = ktime_add_ms(ktime_get(), PORT_RESET_TIMEOUT_MSEC);
> + while (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + usleep_range(50, 200);
> + if (ktime_compare(ktime_get(), timeout) > 0) {
> + netdev_crit(port->ndev,
> + "Timeout while waiting for port %d to finish reset\n",
> + port->idx);
> + break;
> + }
> + }
> + }
> +
> + hdev->in_reset = true;
> +}
> +
> +static void hbl_en_ports_stop(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> + struct hbl_en_port *port;
> + int i;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + if (netif_running(port->ndev))
> + hbl_en_port_close(port);
> + }
> +}
> +
> +static int hbl_en_change_mtu(struct net_device *netdev, int new_mtu)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + int rc = 0;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(netdev, "port is in reset, can't change MTU\n");
> + return -EBUSY;
> + }
> +
> + if (netif_running(port->ndev)) {
> + hbl_en_port_close(port);
> +
> + /* Sleep in order to let obsolete events to be dropped before re-opening the port */
> + msleep(20);
> +
> + netdev->mtu = new_mtu;
> +
> + rc = hbl_en_port_open(port);
> + if (rc)
> + netdev_err(netdev, "Failed to reinit port for MTU change, rc %d\n", rc);
> + } else {
> + netdev->mtu = new_mtu;
> + }
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +/* Swap source and destination MAC addresses */
> +static inline void swap_l2(char *buf)
> +{
> + u16 *eth_hdr, tmp;
> +
> + eth_hdr = (u16 *)buf;
> + tmp = eth_hdr[0];
> + eth_hdr[0] = eth_hdr[3];
> + eth_hdr[3] = tmp;
> + tmp = eth_hdr[1];
> + eth_hdr[1] = eth_hdr[4];
> + eth_hdr[4] = tmp;
> + tmp = eth_hdr[2];
> + eth_hdr[2] = eth_hdr[5];
> + eth_hdr[5] = tmp;
> +}
> +
> +/* Swap source and destination IP addresses
> + */
> +static inline void swap_l3(char *buf)
> +{
> + u32 tmp;
> +
> + /* skip the Ethernet header and the IP header till source IP address */
> + buf += ETH_HLEN + 12;
> + tmp = ((u32 *)buf)[0];
> + ((u32 *)buf)[0] = ((u32 *)buf)[1];
> + ((u32 *)buf)[1] = tmp;
> +}
> +
> +static void do_tx_swap(struct hbl_en_port *port, struct sk_buff *skb)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + u16 *tmp_buff = (u16 *)skb->data;
> + u32 port_idx = port->idx;
> +
> + /* First, let's print the SKB we got */
> + dev_dbg_ratelimited(hdev->dev,
> + "Send [P%d]: dst-mac:%04x%04x%04x, src-mac:%04x%04x%04x, eth-type:%04x, len:%u\n",
> + port_idx, swab16(tmp_buff[0]), swab16(tmp_buff[1]), swab16(tmp_buff[2]),
> + swab16(tmp_buff[3]), swab16(tmp_buff[4]), swab16(tmp_buff[5]),
> + swab16(tmp_buff[6]), skb->len);
> +
> + /* Before submit it to HW, in case this is ipv4 pkt, swap eth/ip addresses.
> + * that way, we may send ECMP (ping) to ourselves in LB cases.
> + */
> + swap_l2(skb->data);
> + if (swab16(tmp_buff[6]) == ETH_P_IP)
> + swap_l3(skb->data);
> +}
> +
> +static bool is_pkt_swap_enabled(struct hbl_en_device *hdev)
> +{
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + return aux_ops->is_eth_lpbk(aux_dev);
> +}
> +
> +static bool is_tx_disabled(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + return aux_ops->get_mac_lpbk(aux_dev, port_idx) && !is_pkt_swap_enabled(hdev);
> +}
> +
> +static netdev_tx_t hbl_en_handle_tx(struct hbl_en_port *port, struct sk_buff *skb)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + netdev_tx_t ret;
> +
> + if (skb->len <= 0 || is_tx_disabled(port))
> + goto free_skb;
> +
> + if (skb->len > hdev->max_frm_len) {
> + netdev_err(port->ndev, "Tx pkt size %uB exceeds maximum of %uB\n", skb->len,
> + hdev->max_frm_len);
> + goto free_skb;
> + }
> +
> + if (is_pkt_swap_enabled(hdev))
> + do_tx_swap(port, skb);
> +
> + /* Pad the ethernet packets to the minimum frame size as the NIC hw doesn't do it.
> + * eth_skb_pad() frees the packet on failure, so just increment the dropped counter and
> + * return as success to avoid a retry.
> + */
> + if (skb_put_padto(skb, hdev->pad_size)) {
> + dev_err_ratelimited(hdev->dev, "Padding failed, the skb is dropped\n");
> + atomic64_inc(&port->net_stats.tx_dropped);
> + return NETDEV_TX_OK;
> + }
> +
> + ret = hdev->asic_funcs.write_pkt_to_hw(port, skb);
> + if (ret == NETDEV_TX_OK) {
> + port->net_stats.tx_packets++;
> + port->net_stats.tx_bytes += skb->len;
> + }
> +
> + return ret;
> +
> +free_skb:
> + dev_kfree_skb_any(skb);
> + return NETDEV_TX_OK;
> +}
> +
> +static netdev_tx_t hbl_en_start_xmit(struct sk_buff *skb, struct net_device *netdev)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + struct hbl_en_device *hdev;
> +
> + hdev = port->hdev;
> +
> + return hbl_en_handle_tx(port, skb);
> +}
> +
> +static int hbl_en_set_port_mac_loopback(struct hbl_en_port *port, bool enable)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct net_device *ndev = port->ndev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int rc;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + rc = aux_ops->set_mac_lpbk(aux_dev, port_idx, enable);
> + if (rc)
> + return rc;
> +
> + netdev_info(ndev, "port %u: mac loopback is %s\n", port_idx,
> + enable ? "enabled" : "disabled");
> +
> + if (netif_running(ndev)) {
> + rc = hbl_en_port_reset(port);
> + if (rc) {
> + netdev_err(ndev, "Failed to reset port %u, rc %d\n", port_idx, rc);
> + return rc;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int hbl_en_set_features(struct net_device *netdev, netdev_features_t features)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + netdev_features_t changed;
> + int rc = 0;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(netdev, "port %d is in reset, can't update settings", port->idx);
> + return -EBUSY;
> + }
> +
> + changed = netdev->features ^ features;
> +
> + if (changed & NETIF_F_LOOPBACK)
> + rc = hbl_en_set_port_mac_loopback(port, !!(features & NETIF_F_LOOPBACK));
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +static void hbl_en_handle_tx_timeout(struct net_device *netdev, unsigned int txqueue)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> +
> + port->net_stats.tx_errors++;
> + atomic64_inc(&port->net_stats.tx_dropped);
> +}
> +
> +static void hbl_en_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(dev);
> +
> + stats->rx_bytes = port->net_stats.rx_bytes;
> + stats->tx_bytes = port->net_stats.tx_bytes;
> + stats->rx_packets = port->net_stats.rx_packets;
> + stats->tx_packets = port->net_stats.tx_packets;
> + stats->tx_errors = port->net_stats.tx_errors;
> + stats->tx_dropped = (u64)atomic64_read(&port->net_stats.tx_dropped);
> + stats->rx_dropped = (u64)atomic64_read(&port->net_stats.rx_dropped);
> +}
> +
> +static const struct net_device_ops hbl_en_netdev_ops = {
> + .ndo_open = hbl_en_open,
> + .ndo_stop = hbl_en_close,
> + .ndo_start_xmit = hbl_en_start_xmit,
> + .ndo_validate_addr = eth_validate_addr,
> + .ndo_change_mtu = hbl_en_change_mtu,
> + .ndo_set_features = hbl_en_set_features,
> + .ndo_get_stats64 = hbl_en_get_stats64,
> + .ndo_tx_timeout = hbl_en_handle_tx_timeout,
> +};
> +
> +static void hbl_en_set_ops(struct net_device *ndev)
> +{
> + ndev->netdev_ops = &hbl_en_netdev_ops;
> + ndev->ethtool_ops = hbl_en_ethtool_get_ops(ndev);
> +#ifdef CONFIG_DCB
> + ndev->dcbnl_ops = &hbl_en_dcbnl_ops;
> +#endif
> +}
> +
> +static int hbl_en_port_register(struct hbl_en_port *port)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + struct hbl_en_port **ptr;
> + struct net_device *ndev;
> + int rc;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + ndev = alloc_etherdev(sizeof(struct hbl_en_port *));
> + if (!ndev) {
> + dev_err(hdev->dev, "netdevice %d alloc failed\n", port_idx);
> + return -ENOMEM;
> + }
> +
> + port->ndev = ndev;
> + SET_NETDEV_DEV(ndev, &hdev->pdev->dev);
> + ptr = netdev_priv(ndev);
> + *ptr = port;
> +
> + /* necessary for creating multiple interfaces */
> + ndev->dev_port = port_idx;
> +
> + hbl_en_set_ops(ndev);
> +
> + ndev->watchdog_timeo = TX_TIMEOUT;
> + ndev->min_mtu = hdev->min_raw_mtu;
> + ndev->max_mtu = hdev->max_raw_mtu;
> +
> + /* Add loopback capability to the device. */
> + ndev->hw_features |= NETIF_F_LOOPBACK;
> +
> + /* If this port was set to loopback, set it also to the ndev features */
> + if (aux_ops->get_mac_lpbk(aux_dev, port_idx))
> + ndev->features |= NETIF_F_LOOPBACK;
> +
> + eth_hw_addr_set(ndev, port->mac_addr);
> +
> + /* It's more an intelligent poll wherein, we enable the Rx completion EQE event and then
> + * start the poll from there.
> + * Inside the polling thread, we read packets from hardware and then reschedule the poll
> + * only if there are more packets to be processed. Else we re-enable the CQ Arm interrupt
> + * and exit the poll.
> + */
> + if (hdev->poll_enable)
> + hbl_en_rx_poll_trigger_init(port);
> +
> + netif_carrier_off(ndev);
> +
> + rc = register_netdev(ndev);
> + if (rc) {
> + dev_err(hdev->dev, "Could not register netdevice %d\n", port_idx);
> + goto err;
> + }
> +
> + return 0;
> +
> +err:
> + if (ndev) {
> + free_netdev(ndev);
> + port->ndev = NULL;
> + }
> +
> + return rc;
> +}
> +
> +static void dump_swap_pkt(struct hbl_en_port *port, struct sk_buff *skb)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + u16 *tmp_buff = (u16 *)skb->data;
> + u32 port_idx = port->idx;
> +
> + /* The SKB is ready now (before stripping-out the L2), print its content */
> + dev_dbg_ratelimited(hdev->dev,
> + "Recv [P%d]: dst-mac:%04x%04x%04x, src-mac:%04x%04x%04x, eth-type:%04x, len:%u\n",
> + port_idx, swab16(tmp_buff[0]), swab16(tmp_buff[1]), swab16(tmp_buff[2]),
> + swab16(tmp_buff[3]), swab16(tmp_buff[4]), swab16(tmp_buff[5]),
> + swab16(tmp_buff[6]), skb->len);
> +}
> +
> +int hbl_en_handle_rx(struct hbl_en_port *port, int budget)
> +{
> + struct hbl_en_device *hdev = port->hdev;
> + enum hbl_en_eth_pkt_status pkt_status;
> + struct net_device *ndev = port->ndev;
> + int rc, pkt_count = 0;
> + struct sk_buff *skb;
> + void *pkt_addr;
> + u32 pkt_size;
> +
> + if (!netif_carrier_ok(ndev))
> + return 0;
> +
> + while (pkt_count < budget) {
> + pkt_status = hdev->asic_funcs.read_pkt_from_hw(port, &pkt_addr, &pkt_size);
> +
> + if (pkt_status == ETH_PKT_NONE)
> + break;
> +
> + pkt_count++;
> +
> + if (pkt_status == ETH_PKT_DROP) {
> + atomic64_inc(&port->net_stats.rx_dropped);
> + continue;
> + }
> +
> + if (hdev->poll_enable)
> + skb = __netdev_alloc_skb_ip_align(ndev, pkt_size, GFP_KERNEL);
> + else
> + skb = napi_alloc_skb(&port->napi, pkt_size);
> +
> + if (!skb) {
> + atomic64_inc(&port->net_stats.rx_dropped);
> + break;
> + }
> +
> + skb_copy_to_linear_data(skb, pkt_addr, pkt_size);
> + skb_put(skb, pkt_size);
> +
> + if (is_pkt_swap_enabled(hdev))
> + dump_swap_pkt(port, skb);
> +
> + skb->protocol = eth_type_trans(skb, ndev);
> +
> + /* Zero the packet buffer memory to avoid leak in case of wrong
> + * size is used when next packet populates the same memory
> + */
> + memset(pkt_addr, 0, pkt_size);
> +
> + /* polling is done in thread context and hence BH should be disabled */
> + if (hdev->poll_enable)
> + local_bh_disable();
> +
> + rc = netif_receive_skb(skb);
> +
> + if (hdev->poll_enable)
> + local_bh_enable();
> +
> + if (rc == NET_RX_SUCCESS) {
> + port->net_stats.rx_packets++;
> + port->net_stats.rx_bytes += pkt_size;
> + } else {
> + atomic64_inc(&port->net_stats.rx_dropped);
> + }
> + }
> +
> + return pkt_count;
> +}
> +
> +static bool __hbl_en_rx_poll_schedule(struct hbl_en_port *port, unsigned long delay)
> +{
> + return queue_delayed_work(port->rx_wq, &port->rx_poll_work, delay);
> +}
> +
> +static void hbl_en_rx_poll_work(struct work_struct *work)
> +{
> + struct hbl_en_port *port = container_of(work, struct hbl_en_port, rx_poll_work.work);
> + struct hbl_en_device *hdev = port->hdev;
> + int pkt_count;
> +
> + pkt_count = hbl_en_handle_rx(port, NAPI_POLL_WEIGHT);
> +
> + /* Reschedule the poll if we have consumed budget which means we still have packets to
> + * process. Else re-enable the Rx IRQs and exit the work.
> + */
> + if (pkt_count < NAPI_POLL_WEIGHT)
> + hdev->asic_funcs.reenable_rx_irq(port);
> + else
> + __hbl_en_rx_poll_schedule(port, 0);
> +}
> +
> +/* Rx poll init and trigger routines are used in event-driven setups where
> + * Rx polling is initialized once during init or open and started/triggered by the event handler.
> + */
> +void hbl_en_rx_poll_trigger_init(struct hbl_en_port *port)
> +{
> + INIT_DELAYED_WORK(&port->rx_poll_work, hbl_en_rx_poll_work);
> +}
> +
> +bool hbl_en_rx_poll_start(struct hbl_en_port *port)
> +{
> + return __hbl_en_rx_poll_schedule(port, msecs_to_jiffies(1));
> +}
> +
> +void hbl_en_rx_poll_stop(struct hbl_en_port *port)
> +{
> + cancel_delayed_work_sync(&port->rx_poll_work);
> +}
> +
> +static int hbl_en_napi_poll(struct napi_struct *napi, int budget)
> +{
> + struct hbl_en_port *port = container_of(napi, struct hbl_en_port, napi);
> + struct hbl_en_device *hdev = port->hdev;
> + int pkt_count;
> +
> + /* exit if we are called by netpoll as we free the Tx ring via EQ (if enabled) */
> + if (!budget)
> + return 0;
> +
> + pkt_count = hbl_en_handle_rx(port, budget);
> +
> + /* If budget not fully consumed, exit the polling mode */
> + if (pkt_count < budget) {
> + napi_complete_done(napi, pkt_count);
> + hdev->asic_funcs.reenable_rx_irq(port);
> + }
> +
> + return pkt_count;
> +}
> +
> +static void hbl_en_port_unregister(struct hbl_en_port *port)
> +{
> + struct net_device *ndev = port->ndev;
> +
> + unregister_netdev(ndev);
> + free_netdev(ndev);
> + port->ndev = NULL;
> +}
> +
> +static int hbl_en_set_asic_funcs(struct hbl_en_device *hdev)
> +{
> + switch (hdev->asic_type) {
> + case HBL_ASIC_GAUDI2:
> + default:
> + dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static void hbl_en_handle_eqe(struct hbl_aux_dev *aux_dev, u32 port, struct hbl_cn_eqe *eqe)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> +
> + hdev->asic_funcs.handle_eqe(aux_dev, port, eqe);
> +}
> +
> +static void hbl_en_set_aux_ops(struct hbl_en_device *hdev, bool enable)
> +{
> + struct hbl_en_aux_ops *aux_ops = hdev->aux_dev->aux_ops;
> +
> + if (enable) {
> + aux_ops->ports_reopen = hbl_en_ports_reopen;
> + aux_ops->ports_stop_prepare = hbl_en_ports_stop_prepare;
> + aux_ops->ports_stop = hbl_en_ports_stop;
> + aux_ops->set_port_status = hbl_en_set_port_status;
> + aux_ops->is_port_open = hbl_en_is_port_open;
> + aux_ops->get_src_ip = hbl_en_get_src_ip;
> + aux_ops->reset_stats = hbl_en_reset_stats;
> + aux_ops->get_mtu = hbl_en_get_mtu;
> + aux_ops->get_pflags = hbl_en_get_pflags;
> + aux_ops->set_dev_lpbk = hbl_en_set_dev_lpbk;
> + aux_ops->handle_eqe = hbl_en_handle_eqe;
> + } else {
> + aux_ops->ports_reopen = NULL;
> + aux_ops->ports_stop_prepare = NULL;
> + aux_ops->ports_stop = NULL;
> + aux_ops->set_port_status = NULL;
> + aux_ops->is_port_open = NULL;
> + aux_ops->get_src_ip = NULL;
> + aux_ops->reset_stats = NULL;
> + aux_ops->get_mtu = NULL;
> + aux_ops->get_pflags = NULL;
> + aux_ops->set_dev_lpbk = NULL;
> + aux_ops->handle_eqe = NULL;
> + }
> +}
> +
> +int hbl_en_dev_init(struct hbl_en_device *hdev)
> +{
> + struct hbl_en_asic_funcs *asic_funcs = &hdev->asic_funcs;
> + struct hbl_en_port *port;
> + int rc, i, port_cnt = 0;
> +
> + /* must be called before the call to dev_init() */
> + rc = hbl_en_set_asic_funcs(hdev);
> + if (rc) {
> + dev_err(hdev->dev, "failed to set aux ops\n");
> + return rc;
> + }
> +
> + rc = asic_funcs->dev_init(hdev);
> + if (rc) {
> + dev_err(hdev->dev, "device init failed\n");
> + return rc;
> + }
> +
> + /* init the function pointers here before calling hbl_en_port_register which sets up
> + * net_device_ops, and its ops might start getting called.
> + * If any failure is encountered, these will be made NULL and the core driver won't call
> + * them.
> + */
> + hbl_en_set_aux_ops(hdev, true);
> +
> + /* Port register depends on the above initialization so it must be called here and not
> + * before that.
> + */
> + for (i = 0; i < hdev->max_num_of_ports; i++, port_cnt++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + rc = hbl_en_port_init(port);
> + if (rc) {
> + dev_err(hdev->dev, "port init failed\n");
> + goto unregister_ports;
> + }
> +
> + rc = hbl_en_port_register(port);
> + if (rc) {
> + dev_err(hdev->dev, "port register failed\n");
> +
> + hbl_en_port_fini(port);
> + goto unregister_ports;
> + }
> + }
> +
> + hdev->is_initialized = true;
> +
> + return 0;
> +
> +unregister_ports:
> + for (i = 0; i < port_cnt; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + hbl_en_port_unregister(port);
> + hbl_en_port_fini(port);
> + }
> +
> + hbl_en_set_aux_ops(hdev, false);
> +
> + asic_funcs->dev_fini(hdev);
> +
> + return rc;
> +}
> +
> +void hbl_en_dev_fini(struct hbl_en_device *hdev)
> +{
> + struct hbl_en_asic_funcs *asic_funcs = &hdev->asic_funcs;
> + struct hbl_en_port *port;
> + int i;
> +
> + hdev->in_teardown = true;
> +
> + if (!hdev->is_initialized)
> + return;
> +
> + hdev->is_initialized = false;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> +
> + /* It could be this cleanup flow is called after a failed init flow.
> + * Hence we need to check that we indeed have a netdev to unregister.
> + */
> + if (!port->ndev)
> + continue;
> +
> + hbl_en_port_unregister(port);
> + hbl_en_port_fini(port);
> + }
> +
> + hbl_en_set_aux_ops(hdev, false);
> +
> + asic_funcs->dev_fini(hdev);
> +}
> +
> +dma_addr_t hbl_en_dma_map(struct hbl_en_device *hdev, void *addr, int len)
> +{
> + dma_addr_t dma_addr;
> +
> + if (hdev->dma_map_support)
> + dma_addr = dma_map_single(&hdev->pdev->dev, addr, len, DMA_TO_DEVICE);
> + else
> + dma_addr = virt_to_phys(addr);
> +
> + return dma_addr;
> +}
> +
> +void hbl_en_dma_unmap(struct hbl_en_device *hdev, dma_addr_t dma_addr, int len)
> +{
> + if (hdev->dma_map_support)
> + dma_unmap_single(&hdev->pdev->dev, dma_addr, len, DMA_TO_DEVICE);
> +}
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
> new file mode 100644
> index 000000000000..15504c1f3cfb
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
> @@ -0,0 +1,206 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#ifndef HABANALABS_EN_H_
> +#define HABANALABS_EN_H_
> +
> +#include <linux/net/intel/cn.h>
> +
> +#include <linux/netdevice.h>
> +#include <linux/pci.h>
> +
> +#define HBL_EN_NAME "habanalabs_en"
> +
> +#define HBL_EN_PORT(aux_dev, idx) (&(((struct hbl_en_device *)(aux_dev)->priv)->ports[(idx)]))
> +
> +#define hbl_netdev_priv(ndev) \
> +({ \
> + typecheck(struct net_device *, ndev); \
> + *(struct hbl_en_port **)netdev_priv(ndev); \
> +})
> +
> +/**
> + * enum hbl_en_eth_pkt_status - status of Rx Ethernet packet.
> + * ETH_PKT_OK: packet was received successfully.
> + * ETH_PKT_DROP: packet should be dropped.
> + * ETH_PKT_NONE: no available packet.
> + */
> +enum hbl_en_eth_pkt_status {
> + ETH_PKT_OK,
> + ETH_PKT_DROP,
> + ETH_PKT_NONE
> +};
> +
> +/**
> + * struct hbl_en_net_stats - stats of Ethernet interface.
> + * rx_packets: number of packets received.
> + * tx_packets: number of packets sent.
> + * rx_bytes: total bytes of data received.
> + * tx_bytes: total bytes of data sent.
> + * tx_errors: number of errors in the TX.
> + * rx_dropped: number of packets dropped by the RX.
> + * tx_dropped: number of packets dropped by the TX.
> + */
> +struct hbl_en_net_stats {
> + u64 rx_packets;
> + u64 tx_packets;
> + u64 rx_bytes;
> + u64 tx_bytes;
> + u64 tx_errors;
> + atomic64_t rx_dropped;
> + atomic64_t tx_dropped;
> +};
> +
> +/**
> + * struct hbl_en_port - manage port common structure.
> + * @hdev: habanalabs Ethernet device structure.
> + * @ndev: network device.
> + * @rx_wq: WQ for Rx poll when we cannot schedule NAPI poll.
> + * @mac_addr: HW MAC addresses.
> + * @asic_specific: ASIC specific port structure.
> + * @napi: New API structure.
> + * @rx_poll_work: Rx work for polling mode.
> + * @net_stats: statistics of the ethernet interface.
> + * @in_reset: true if the NIC was marked as in reset, false otherwise. Used to avoid an additional
> + * stopping of the NIC if a hard reset was re-initiated.
> + * @pflags: ethtool private flags bit mask.
> + * @idx: index of this specific port.
> + * @rx_max_coalesced_frames: Maximum number of packets to receive before an RX interrupt.
> + * @tx_max_coalesced_frames: Maximum number of packets to be sent before a TX interrupt.
> + * @rx_coalesce_usecs: How many usecs to delay an RX interrupt after a packet arrives.
> + * @is_initialized: true if the port H/W is initialized, false otherwise.
> + * @pfc_enable: true if this port supports Priority Flow Control, false otherwise.
> + * @auto_neg_enable: is autoneg enabled.
> + * @auto_neg_resolved: was autoneg phase finished successfully.
> + */
> +struct hbl_en_port {
> + struct hbl_en_device *hdev;
> + struct net_device *ndev;
> + struct workqueue_struct *rx_wq;
> + char *mac_addr;
> + void *asic_specific;
> + struct napi_struct napi;
> + struct delayed_work rx_poll_work;
> + struct hbl_en_net_stats net_stats;
> + atomic_t in_reset;
> + u32 pflags;
> + u32 idx;
> + u32 rx_max_coalesced_frames;
> + u32 tx_max_coalesced_frames;
> + u16 rx_coalesce_usecs;
> + u8 is_initialized;
> + u8 pfc_enable;
> + u8 auto_neg_enable;
> + u8 auto_neg_resolved;
> +};
> +
> +/**
> + * struct hbl_en_asic_funcs - ASIC specific Ethernet functions.
> + * @dev_init: device init.
> + * @dev_fini: device cleanup.
> + * @reenable_rx_irq: re-enable Rx interrupts.
> + * @eth_port_open: initialize and open the Ethernet port.
> + * @eth_port_close: close the Ethernet port.
> + * @write_pkt_to_hw: write skb to HW.
> + * @read_pkt_from_hw: read pkt from HW.
> + * @get_pfc_cnts: get PFC counters.
> + * @set_coalesce: set Tx/Rx coalesce config in HW.
> + * @get_rx_ring size: get max number of elements the Rx ring can contain.
> + * @handle_eqe: Handle a received event.
> + */
> +struct hbl_en_asic_funcs {
> + int (*dev_init)(struct hbl_en_device *hdev);
> + void (*dev_fini)(struct hbl_en_device *hdev);
> + void (*reenable_rx_irq)(struct hbl_en_port *port);
> + int (*eth_port_open)(struct hbl_en_port *port);
> + void (*eth_port_close)(struct hbl_en_port *port);
> + netdev_tx_t (*write_pkt_to_hw)(struct hbl_en_port *port, struct sk_buff *skb);
> + int (*read_pkt_from_hw)(struct hbl_en_port *port, void **pkt_addr, u32 *pkt_size);
> + void (*get_pfc_cnts)(struct hbl_en_port *port, void *ptr);
> + int (*set_coalesce)(struct hbl_en_port *port);
> + int (*get_rx_ring_size)(struct hbl_en_port *port);
> + void (*handle_eqe)(struct hbl_aux_dev *aux_dev, u32 port_idx, struct hbl_cn_eqe *eqe);
> +};
> +
> +/**
> + * struct hbl_en_device - habanalabs Ethernet device structure.
> + * @pdev: pointer to PCI device.
> + * @dev: related kernel basic device structure.
> + * @ports: array of all ports manage common structures.
> + * @aux_dev: pointer to auxiliary device.
> + * @asic_specific: ASIC specific device structure.
> + * @fw_ver: FW version.
> + * @qsfp_eeprom: QSFPD EEPROM info.
> + * @mac_addr: array of all MAC addresses.
> + * @asic_funcs: ASIC specific Ethernet functions.
> + * @asic_type: ASIC specific type.
> + * @ports_mask: mask of available ports.
> + * @auto_neg_mask: mask of port with Autonegotiation enabled.
> + * @port_reset_timeout: max time in seconds for a port reset flow to finish.
> + * @pending_reset_long_timeout: long timeout for pending hard reset to finish in seconds.
> + * @max_frm_len: maximum allowed frame length.
> + * @raw_elem_size: size of element in raw buffers.
> + * @max_raw_mtu: maximum MTU size for raw packets.
> + * @min_raw_mtu: minimum MTU size for raw packets.
> + * @pad_size: the pad size in bytes for the skb to transmit.
> + * @core_dev_id: core device ID.
> + * @max_num_of_ports: max number of available ports;
> + * @in_reset: is the entire NIC currently under reset.
> + * @poll_enable: Enable Rx polling rather than IRQ + NAPI.
> + * @in_teardown: true if the NIC is in teardown (during device remove).
> + * @is_initialized: was the device initialized successfully.
> + * @has_eq: true if event queue is supported.
> + * @dma_map_support: HW supports DMA mapping.
> + */
> +struct hbl_en_device {
> + struct pci_dev *pdev;
> + struct device *dev;
> + struct hbl_en_port *ports;
> + struct hbl_aux_dev *aux_dev;
> + void *asic_specific;
> + char *fw_ver;
> + char *qsfp_eeprom;
> + char *mac_addr;
> + struct hbl_en_asic_funcs asic_funcs;
> + enum hbl_cn_asic_type asic_type;
> + u64 ports_mask;
> + u64 auto_neg_mask;
> + u32 port_reset_timeout;
> + u32 pending_reset_long_timeout;
> + u32 max_frm_len;
> + u32 raw_elem_size;
> + u16 max_raw_mtu;
> + u16 min_raw_mtu;
> + u16 pad_size;
> + u16 core_dev_id;
> + u8 max_num_of_ports;
> + u8 in_reset;
> + u8 poll_enable;
> + u8 in_teardown;
> + u8 is_initialized;
> + u8 has_eq;
> + u8 dma_map_support;
> +};
> +
> +int hbl_en_dev_init(struct hbl_en_device *hdev);
> +void hbl_en_dev_fini(struct hbl_en_device *hdev);
> +
> +const struct ethtool_ops *hbl_en_ethtool_get_ops(struct net_device *ndev);
> +void hbl_en_ethtool_init_coalesce(struct hbl_en_port *port);
> +
> +extern const struct dcbnl_rtnl_ops hbl_en_dcbnl_ops;
> +
> +bool hbl_en_rx_poll_start(struct hbl_en_port *port);
> +void hbl_en_rx_poll_stop(struct hbl_en_port *port);
> +void hbl_en_rx_poll_trigger_init(struct hbl_en_port *port);
> +int hbl_en_port_reset(struct hbl_en_port *port);
> +int hbl_en_port_reset_locked(struct hbl_aux_dev *aux_dev, u32 port_idx);
> +int hbl_en_handle_rx(struct hbl_en_port *port, int budget);
> +dma_addr_t hbl_en_dma_map(struct hbl_en_device *hdev, void *addr, int len);
> +void hbl_en_dma_unmap(struct hbl_en_device *hdev, dma_addr_t dma_addr, int len);
> +
> +#endif /* HABANALABS_EN_H_ */
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c
> new file mode 100644
> index 000000000000..5d718579a2b6
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c
> @@ -0,0 +1,101 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#include "hbl_en.h"
> +
> +#define PFC_PRIO_MASK_ALL GENMASK(HBL_EN_PFC_PRIO_NUM - 1, 0)
> +#define PFC_PRIO_MASK_NONE 0
> +
> +#ifdef CONFIG_DCB
> +static int hbl_en_dcbnl_ieee_getpfc(struct net_device *netdev, struct ieee_pfc *pfc)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + struct hbl_en_device *hdev;
> + u32 port_idx;
> +
> + hdev = port->hdev;
> + port_idx = port->idx;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + dev_dbg_ratelimited(hdev->dev, "port %d is in reset, can't get PFC", port_idx);
> + return -EBUSY;
> + }
> +
> + pfc->pfc_en = port->pfc_enable ? PFC_PRIO_MASK_ALL : PFC_PRIO_MASK_NONE;
> + pfc->pfc_cap = HBL_EN_PFC_PRIO_NUM;
> +
> + hdev->asic_funcs.get_pfc_cnts(port, pfc);
> +
> + atomic_set(&port->in_reset, 0);
> +
> + return 0;
> +}
> +
> +static int hbl_en_dcbnl_ieee_setpfc(struct net_device *netdev, struct ieee_pfc *pfc)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(netdev);
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + struct hbl_en_device *hdev;
> + u8 curr_pfc_en;
> + u32 port_idx;
> + int rc = 0;
> +
> + hdev = port->hdev;
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> + port_idx = port->idx;
> +
> + if (pfc->pfc_en & ~PFC_PRIO_MASK_ALL) {
> + dev_dbg_ratelimited(hdev->dev, "PFC supports %d priorities only, port %d\n",
> + HBL_EN_PFC_PRIO_NUM, port_idx);
> + return -EINVAL;
> + }
> +
> + if (pfc->pfc_en != PFC_PRIO_MASK_NONE && pfc->pfc_en != PFC_PRIO_MASK_ALL) {
> + dev_dbg_ratelimited(hdev->dev,
> + "PFC should be enabled/disabled on all priorities, port %d\n",
> + port_idx);
> + return -EINVAL;
> + }
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + dev_dbg_ratelimited(hdev->dev, "port %d is in reset, can't set PFC", port_idx);
> + return -EBUSY;
> + }
> +
> + curr_pfc_en = port->pfc_enable ? PFC_PRIO_MASK_ALL : PFC_PRIO_MASK_NONE;
> +
> + if (pfc->pfc_en == curr_pfc_en)
> + goto out;
> +
> + port->pfc_enable = !port->pfc_enable;
> +
> + rc = aux_ops->set_pfc(aux_dev, port_idx, port->pfc_enable);
> +
> +out:
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +static u8 hbl_en_dcbnl_getdcbx(struct net_device *netdev)
> +{
> + return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
> +}
> +
> +static u8 hbl_en_dcbnl_setdcbx(struct net_device *netdev, u8 mode)
> +{
> + return !(mode == (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE));
> +}
> +
> +const struct dcbnl_rtnl_ops hbl_en_dcbnl_ops = {
> + .ieee_getpfc = hbl_en_dcbnl_ieee_getpfc,
> + .ieee_setpfc = hbl_en_dcbnl_ieee_setpfc,
> + .getdcbx = hbl_en_dcbnl_getdcbx,
> + .setdcbx = hbl_en_dcbnl_setdcbx
> +};
> +#endif
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c
> new file mode 100644
> index 000000000000..23a87d36ded5
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c
> @@ -0,0 +1,211 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#define pr_fmt(fmt) "habanalabs_en: " fmt
> +
> +#include "hbl_en.h"
> +
> +#include <linux/module.h>
> +#include <linux/auxiliary_bus.h>
> +
> +#define HBL_DRIVER_AUTHOR "HabanaLabs Kernel Driver Team"
> +
> +#define HBL_DRIVER_DESC "HabanaLabs AI accelerators Ethernet driver"
> +
> +MODULE_AUTHOR(HBL_DRIVER_AUTHOR);
> +MODULE_DESCRIPTION(HBL_DRIVER_DESC);
> +MODULE_LICENSE("GPL");
> +
> +static bool poll_enable;
> +
> +module_param(poll_enable, bool, 0444);
> +MODULE_PARM_DESC(poll_enable,
> + "Enable Rx polling rather than IRQ + NAPI (0 = no, 1 = yes, default: no)");
> +
> +static int hdev_init(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_aux_data *aux_data = aux_dev->aux_data;
> + struct hbl_en_port *ports, *port;
> + struct hbl_en_device *hdev;
> + int rc, i;
> +
> + hdev = kzalloc(sizeof(*hdev), GFP_KERNEL);
> + if (!hdev)
> + return -ENOMEM;
> +
> + ports = kcalloc(aux_data->max_num_of_ports, sizeof(*ports), GFP_KERNEL);
> + if (!ports) {
> + rc = -ENOMEM;
> + goto ports_alloc_fail;
> + }
> +
> + aux_dev->priv = hdev;
> + hdev->aux_dev = aux_dev;
> + hdev->ports = ports;
> + hdev->pdev = aux_data->pdev;
> + hdev->dev = aux_data->dev;
> + hdev->ports_mask = aux_data->ports_mask;
> + hdev->auto_neg_mask = aux_data->auto_neg_mask;
> + hdev->max_num_of_ports = aux_data->max_num_of_ports;
> + hdev->core_dev_id = aux_data->id;
> + hdev->fw_ver = aux_data->fw_ver;
> + hdev->qsfp_eeprom = aux_data->qsfp_eeprom;
> + hdev->asic_type = aux_data->asic_type;
> + hdev->pending_reset_long_timeout = aux_data->pending_reset_long_timeout;
> + hdev->max_frm_len = aux_data->max_frm_len;
> + hdev->raw_elem_size = aux_data->raw_elem_size;
> + hdev->max_raw_mtu = aux_data->max_raw_mtu;
> + hdev->min_raw_mtu = aux_data->min_raw_mtu;
> + hdev->pad_size = ETH_ZLEN;
> + hdev->has_eq = aux_data->has_eq;
> + hdev->dma_map_support = true;
> + hdev->poll_enable = poll_enable;
> +
> + for (i = 0; i < hdev->max_num_of_ports; i++) {
> + if (!(hdev->ports_mask & BIT(i)))
> + continue;
> +
> + port = &hdev->ports[i];
> + port->hdev = hdev;
> + port->idx = i;
> + port->pfc_enable = true;
> + port->pflags = PFLAGS_PCS_LINK_CHECK | PFLAGS_PHY_AUTO_NEG_LPBK;
> + port->mac_addr = aux_data->mac_addr[i];
> + port->auto_neg_enable = !!(aux_data->auto_neg_mask & BIT(i));
> + }
> +
> + return 0;
> +
> +ports_alloc_fail:
> + kfree(hdev);
> +
> + return rc;
> +}
> +
> +static void hdev_fini(struct hbl_aux_dev *aux_dev)
> +{
> + struct hbl_en_device *hdev = aux_dev->priv;
> +
> + kfree(hdev->ports);
> + kfree(hdev);
> + aux_dev->priv = NULL;
> +}
> +
> +static const struct auxiliary_device_id hbl_en_id_table[] = {
> + { .name = "habanalabs_cn.en", },
> + {},
> +};
> +
> +MODULE_DEVICE_TABLE(auxiliary, hbl_en_id_table);
> +
> +static int hbl_en_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
> +{
> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
> + struct hbl_en_aux_ops *aux_ops = aux_dev->aux_ops;
> + struct hbl_en_device *hdev;
> + ktime_t timeout;
> + int rc;
> +
> + rc = hdev_init(aux_dev);
> + if (rc) {
> + dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
> + return -EIO;
> + }
> +
> + hdev = aux_dev->priv;
> +
> + /* don't allow module unloading while it is attached */
> + if (!try_module_get(THIS_MODULE)) {
> + dev_err(hdev->dev, "Failed to increment %s module refcount\n", HBL_EN_NAME);
> + rc = -EIO;
> + goto module_get_err;
> + }
> +
> + timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
> + while (1) {
> + aux_ops->hw_access_lock(aux_dev);
> +
> + /* if the device is operational, proceed to actual init while holding the lock in
> + * order to prevent concurrent hard reset
> + */
> + if (aux_ops->device_operational(aux_dev))
> + break;
> +
> + aux_ops->hw_access_unlock(aux_dev);
> +
> + if (ktime_compare(ktime_get(), timeout) > 0) {
> + dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
> + rc = -EBUSY;
> + goto timeout_err;
> + }
> +
> + dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing en\n");
> +
> + msleep_interruptible(MSEC_PER_SEC);
> + }
> +
> + rc = hbl_en_dev_init(hdev);
> + if (rc) {
> + dev_err(hdev->dev, "Failed to init en device\n");
> + goto dev_init_err;
> + }
> +
> + aux_ops->hw_access_unlock(aux_dev);
> +
> + return 0;
> +
> +dev_init_err:
> + aux_ops->hw_access_unlock(aux_dev);
> +timeout_err:
> + module_put(THIS_MODULE);
> +module_get_err:
> + hdev_fini(aux_dev);
> +
> + return rc;
> +}
> +
> +/* This function can be called only from the CN driver when deleting the aux bus, because we
> + * incremented the module refcount on probing. Hence no need to protect here from hard reset.
> + */
> +static void hbl_en_remove(struct auxiliary_device *adev)
> +{
> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
> + struct hbl_en_device *hdev = aux_dev->priv;
> +
> + if (!hdev)
> + return;
> +
> + hbl_en_dev_fini(hdev);
> +
> + /* allow module unloading as now it is detached */
> + module_put(THIS_MODULE);
> +
> + hdev_fini(aux_dev);
> +}
> +
> +static struct auxiliary_driver hbl_en_driver = {
> + .name = "eth",
> + .probe = hbl_en_probe,
> + .remove = hbl_en_remove,
> + .id_table = hbl_en_id_table,
> +};
> +
> +static int __init hbl_en_init(void)
> +{
> + pr_info("loading driver\n");
> +
> + return auxiliary_driver_register(&hbl_en_driver);
> +}
> +
> +static void __exit hbl_en_exit(void)
> +{
> + auxiliary_driver_unregister(&hbl_en_driver);
> +
> + pr_info("driver removed\n");
> +}
> +
> +module_init(hbl_en_init);
> +module_exit(hbl_en_exit);
> diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c
> new file mode 100644
> index 000000000000..1d14d283409b
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c
> @@ -0,0 +1,452 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2020-2024 HabanaLabs, Ltd.
> + * Copyright (C) 2023-2024, Intel Corporation.
> + * All Rights Reserved.
> + */
> +
> +#include "hbl_en.h"
> +#include <linux/ethtool.h>
> +
> +#define RX_COALESCED_FRAMES_MIN 1
> +#define TX_COALESCED_FRAMES_MIN 1
> +#define TX_COALESCED_FRAMES_MAX 10
> +
> +static const char pflags_str[][ETH_GSTRING_LEN] = {
> + "pcs-link-check",
> + "phy-auto-neg-lpbk",
> +};
> +
> +#define NIC_STAT(m) {#m, offsetof(struct hbl_en_port, net_stats.m)}
> +
> +static struct hbl_cn_stat netdev_eth_stats[] = {
> + NIC_STAT(rx_packets),
> + NIC_STAT(tx_packets),
> + NIC_STAT(rx_bytes),
> + NIC_STAT(tx_bytes),
> + NIC_STAT(tx_errors),
> + NIC_STAT(rx_dropped),
> + NIC_STAT(tx_dropped)
> +};
> +
> +static size_t pflags_str_len = ARRAY_SIZE(pflags_str);
> +static size_t netdev_eth_stats_len = ARRAY_SIZE(netdev_eth_stats);
> +
> +static void hbl_en_ethtool_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *drvinfo)
> +{
> + struct hbl_en_device *hdev;
> + struct hbl_en_port *port;
> +
> + port = hbl_netdev_priv(ndev);
> + hdev = port->hdev;
> +
> + strscpy(drvinfo->driver, HBL_EN_NAME, sizeof(drvinfo->driver));
> + strscpy(drvinfo->fw_version, hdev->fw_ver, sizeof(drvinfo->fw_version));
> + strscpy(drvinfo->bus_info, pci_name(hdev->pdev), sizeof(drvinfo->bus_info));
> +}
> +
> +static int hbl_en_ethtool_get_module_info(struct net_device *ndev, struct ethtool_modinfo *modinfo)
> +{
> + modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
> + modinfo->type = ETH_MODULE_SFF_8636;
> +
> + return 0;
> +}
> +
> +static int hbl_en_ethtool_get_module_eeprom(struct net_device *ndev, struct ethtool_eeprom *ee,
> + u8 *data)
> +{
> + struct hbl_en_device *hdev;
> + struct hbl_en_port *port;
> + u32 first, last, len;
> + u8 *qsfp_eeprom;
> +
> + port = hbl_netdev_priv(ndev);
> + hdev = port->hdev;
> + qsfp_eeprom = hdev->qsfp_eeprom;
> +
> + if (ee->len == 0)
> + return -EINVAL;
> +
> + first = ee->offset;
> + last = ee->offset + ee->len;
> +
> + if (first < ETH_MODULE_SFF_8636_LEN) {
> + len = min_t(unsigned int, last, ETH_MODULE_SFF_8079_LEN);
> + len -= first;
> +
> + memcpy(data, qsfp_eeprom + first, len);
> + }
> +
> + return 0;
> +}
> +
> +static u32 hbl_en_ethtool_get_priv_flags(struct net_device *ndev)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> +
> + return port->pflags;
> +}
> +
> +static int hbl_en_ethtool_set_priv_flags(struct net_device *ndev, u32 priv_flags)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> +
> + port->pflags = priv_flags;
> +
> + return 0;
> +}
> +
> +static int hbl_en_ethtool_get_link_ksettings(struct net_device *ndev,
> + struct ethtool_link_ksettings *cmd)
> +{
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + struct hbl_en_device *hdev;
> + struct hbl_en_port *port;
> + u32 port_idx, speed;
> +
> + port = hbl_netdev_priv(ndev);
> + hdev = port->hdev;
> + port_idx = port->idx;
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> + speed = aux_ops->get_speed(aux_dev, port_idx);
> +
> + cmd->base.speed = speed;
> + cmd->base.duplex = DUPLEX_FULL;
> +
> + ethtool_link_ksettings_zero_link_mode(cmd, supported);
> + ethtool_link_ksettings_zero_link_mode(cmd, advertising);
> +
> + switch (speed) {
> + case SPEED_100000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseSR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseKR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 100000baseLR4_ER4_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseSR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseKR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 100000baseLR4_ER4_Full);
> +
> + cmd->base.port = PORT_FIBRE;
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Backplane);
> + break;
> + case SPEED_50000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseSR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseCR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 50000baseKR2_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseSR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseCR2_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 50000baseKR2_Full);
> + break;
> + case SPEED_25000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 25000baseCR_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 25000baseCR_Full);
> + break;
> + case SPEED_200000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 200000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 200000baseKR4_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 200000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 200000baseKR4_Full);
> + break;
> + case SPEED_400000:
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 400000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, supported, 400000baseKR4_Full);
> +
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 400000baseCR4_Full);
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, 400000baseKR4_Full);
> + break;
> + default:
> + netdev_err(port->ndev, "unknown speed %d\n", speed);
> + return -EFAULT;
> + }
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
> +
> + if (port->auto_neg_enable) {
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
> + cmd->base.autoneg = AUTONEG_ENABLE;
> + if (port->auto_neg_resolved)
> + ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
> + } else {
> + cmd->base.autoneg = AUTONEG_DISABLE;
> + }
> +
> + ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
> +
> + if (port->pfc_enable)
> + ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause);
> +
> + return 0;
> +}
> +
> +/* only autoneg is mutable */
> +static bool check_immutable_ksettings(const struct ethtool_link_ksettings *old_cmd,
> + const struct ethtool_link_ksettings *new_cmd)
> +{
> + return (old_cmd->base.speed == new_cmd->base.speed) &&
> + (old_cmd->base.duplex == new_cmd->base.duplex) &&
> + (old_cmd->base.port == new_cmd->base.port) &&
> + (old_cmd->base.phy_address == new_cmd->base.phy_address) &&
> + (old_cmd->base.eth_tp_mdix_ctrl == new_cmd->base.eth_tp_mdix_ctrl) &&
> + bitmap_equal(old_cmd->link_modes.advertising, new_cmd->link_modes.advertising,
> + __ETHTOOL_LINK_MODE_MASK_NBITS);
> +}
> +
> +static int
> +hbl_en_ethtool_set_link_ksettings(struct net_device *ndev, const struct ethtool_link_ksettings *cmd)
> +{
> + struct ethtool_link_ksettings curr_cmd;
> + struct hbl_en_device *hdev;
> + struct hbl_en_port *port;
> + bool auto_neg;
> + u32 port_idx;
> + int rc;
> +
> + port = hbl_netdev_priv(ndev);
> + hdev = port->hdev;
> + port_idx = port->idx;
> +
> + memset(&curr_cmd, 0, sizeof(struct ethtool_link_ksettings));
> +
> + rc = hbl_en_ethtool_get_link_ksettings(ndev, &curr_cmd);
> + if (rc)
> + return rc;
> +
> + if (!check_immutable_ksettings(&curr_cmd, cmd))
> + return -EOPNOTSUPP;
> +
> + auto_neg = cmd->base.autoneg == AUTONEG_ENABLE;
> +
> + if (port->auto_neg_enable == auto_neg)
> + return 0;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(port->ndev, "port is in reset, can't update settings\n");
> + return -EBUSY;
> + }
> +
> + if (auto_neg && !(hdev->auto_neg_mask & BIT(port_idx))) {
> + netdev_err(port->ndev, "port autoneg is disabled by BMC\n");
> + rc = -EFAULT;
> + goto out;
> + }
> +
> + port->auto_neg_enable = auto_neg;
> +
> + if (netif_running(port->ndev)) {
> + rc = hbl_en_port_reset(port);
> + if (rc)
> + netdev_err(port->ndev, "Failed to reset port for settings update, rc %d\n",
> + rc);
> + }
> +
> +out:
> + atomic_set(&port->in_reset, 0);
> +
> + return rc;
> +}
> +
> +static int hbl_en_ethtool_get_sset_count(struct net_device *ndev, int sset)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + switch (sset) {
> + case ETH_SS_STATS:
> + return netdev_eth_stats_len + aux_ops->get_cnts_num(aux_dev, port_idx);
> + case ETH_SS_PRIV_FLAGS:
> + return pflags_str_len;
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static void hbl_en_ethtool_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int i;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + switch (stringset) {
> + case ETH_SS_STATS:
> + for (i = 0; i < netdev_eth_stats_len; i++)
> + ethtool_puts(&data, netdev_eth_stats[i].str);
> +
> + aux_ops->get_cnts_names(aux_dev, port_idx, data);
> + break;
> + case ETH_SS_PRIV_FLAGS:
> + for (i = 0; i < pflags_str_len; i++)
> + ethtool_puts(&data, pflags_str[i]);
> + break;
> + }
> +}
> +
> +static void hbl_en_ethtool_get_ethtool_stats(struct net_device *ndev,
> + __always_unused struct ethtool_stats *stats, u64 *data)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + struct hbl_en_device *hdev;
> + u32 port_idx;
> + char *p;
> + int i;
> +
> + hdev = port->hdev;
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> + port_idx = port->idx;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + dev_info_ratelimited(hdev->dev, "port %d is in reset, can't get ethtool stats",
> + port_idx);
> + return;
> + }
> +
> + /* Even though the Ethernet Rx/Tx flow might update the stats in parallel, there is not an
> + * absolute need for synchronisation. This is because, missing few counts of these stats is
> + * much better than adding a lock to synchronize and increase the overhead of the Rx/Tx
> + * flows. In worst case scenario, reader will get stale stats. He will receive updated
> + * stats in next read.
> + */
> + for (i = 0; i < netdev_eth_stats_len; i++) {
> + p = (char *)port + netdev_eth_stats[i].lo_offset;
> + data[i] = *(u32 *)p;
> + }
> +
> + data += i;
> +
> + aux_ops->get_cnts_values(aux_dev, port_idx, data);
> +
> + atomic_set(&port->in_reset, 0);
> +}
> +
> +static int hbl_en_ethtool_get_coalesce(struct net_device *ndev,
> + struct ethtool_coalesce *coal,
> + struct kernel_ethtool_coalesce *kernel_coal,
> + struct netlink_ext_ack *extack)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + aux_ops->ctrl_lock(aux_dev, port_idx);
> +
> + coal->tx_max_coalesced_frames = port->tx_max_coalesced_frames;
> + coal->rx_coalesce_usecs = port->rx_coalesce_usecs;
> + coal->rx_max_coalesced_frames = port->rx_max_coalesced_frames;
> +
> + aux_ops->ctrl_unlock(aux_dev, port_idx);
> +
> + return 0;
> +}
> +
> +static int hbl_en_ethtool_set_coalesce(struct net_device *ndev,
> + struct ethtool_coalesce *coal,
> + struct kernel_ethtool_coalesce *kernel_coal,
> + struct netlink_ext_ack *extack)
> +{
> + struct hbl_en_port *port = hbl_netdev_priv(ndev);
> + struct hbl_en_device *hdev = port->hdev;
> + struct hbl_en_aux_ops *aux_ops;
> + struct hbl_aux_dev *aux_dev;
> + u32 port_idx = port->idx;
> + int rc, rx_ring_size;
> +
> + aux_dev = hdev->aux_dev;
> + aux_ops = aux_dev->aux_ops;
> +
> + if (atomic_cmpxchg(&port->in_reset, 0, 1)) {
> + netdev_err(port->ndev, "port is in reset, can't update settings\n");
> + return -EBUSY;
> + }
> +
> + if (coal->tx_max_coalesced_frames < TX_COALESCED_FRAMES_MIN ||
> + coal->tx_max_coalesced_frames > TX_COALESCED_FRAMES_MAX) {
> + netdev_err(ndev, "tx max_coalesced_frames should be between %d and %d\n",
> + TX_COALESCED_FRAMES_MIN, TX_COALESCED_FRAMES_MAX);
> + rc = -EINVAL;
> + goto atomic_out;
> + }
> +
> + rx_ring_size = hdev->asic_funcs.get_rx_ring_size(port);
> + if (coal->rx_max_coalesced_frames < RX_COALESCED_FRAMES_MIN ||
> + coal->rx_max_coalesced_frames >= rx_ring_size) {
> + netdev_err(ndev, "rx max_coalesced_frames should be between %d and %d\n",
> + RX_COALESCED_FRAMES_MIN, rx_ring_size);
> + rc = -EINVAL;
> + goto atomic_out;
> + }
> +
> + aux_ops->ctrl_lock(aux_dev, port_idx);
> +
> + port->tx_max_coalesced_frames = coal->tx_max_coalesced_frames;
> + port->rx_coalesce_usecs = coal->rx_coalesce_usecs;
> + port->rx_max_coalesced_frames = coal->rx_max_coalesced_frames;
> +
> + rc = hdev->asic_funcs.set_coalesce(port);
> +
> + aux_ops->ctrl_unlock(aux_dev, port_idx);
> +
> +atomic_out:
> + atomic_set(&port->in_reset, 0);
> + return rc;
> +}
> +
> +void hbl_en_ethtool_init_coalesce(struct hbl_en_port *port)
> +{
> + port->rx_coalesce_usecs = CQ_ARM_TIMEOUT_USEC;
> + port->rx_max_coalesced_frames = 1;
> + port->tx_max_coalesced_frames = 1;
> +}
> +
> +static const struct ethtool_ops hbl_en_ethtool_ops_coalesce = {
> + .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | ETHTOOL_COALESCE_RX_MAX_FRAMES |
> + ETHTOOL_COALESCE_TX_MAX_FRAMES,
> + .get_drvinfo = hbl_en_ethtool_get_drvinfo,
> + .get_link = ethtool_op_get_link,
> + .get_module_info = hbl_en_ethtool_get_module_info,
> + .get_module_eeprom = hbl_en_ethtool_get_module_eeprom,
> + .get_priv_flags = hbl_en_ethtool_get_priv_flags,
> + .set_priv_flags = hbl_en_ethtool_set_priv_flags,
> + .get_link_ksettings = hbl_en_ethtool_get_link_ksettings,
> + .set_link_ksettings = hbl_en_ethtool_set_link_ksettings,
> + .get_sset_count = hbl_en_ethtool_get_sset_count,
> + .get_strings = hbl_en_ethtool_get_strings,
> + .get_ethtool_stats = hbl_en_ethtool_get_ethtool_stats,
> + .get_coalesce = hbl_en_ethtool_get_coalesce,
> + .set_coalesce = hbl_en_ethtool_set_coalesce,
> +};
> +
> +const struct ethtool_ops *hbl_en_ethtool_get_ops(struct net_device *ndev)
> +{
> + return &hbl_en_ethtool_ops_coalesce;
> +}
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver
2024-06-15 17:13 ` Zhu Yanjun
@ 2024-06-16 1:08 ` Andrew Lunn
0 siblings, 0 replies; 108+ messages in thread
From: Andrew Lunn @ 2024-06-16 1:08 UTC (permalink / raw)
To: Zhu Yanjun
Cc: Omer Shpigelman, linux-kernel, linux-rdma, netdev, dri-devel,
ogabbay, zyehudai
> > +static void hbl_en_reset_stats(struct hbl_aux_dev *aux_dev, u32 port_idx)
> > +{
> > + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> > +
> > + port->net_stats.rx_packets = 0;
> > + port->net_stats.tx_packets = 0;
> > + port->net_stats.rx_bytes = 0;
> > + port->net_stats.tx_bytes = 0;
> > + port->net_stats.tx_errors = 0;
> > + atomic64_set(&port->net_stats.rx_dropped, 0);
> > + atomic64_set(&port->net_stats.tx_dropped, 0);
>
> per-cpu variable is better?
Please trim replies to just the needed context. Is this the only
comment in this 2300 line email? Do i need to keep searching for more
comments?
Andrew
^ permalink raw reply [flat|nested] 108+ messages in thread
* [PATCH 10/15] net: hbl_en: gaudi2: ASIC specific support
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
` (8 preceding siblings ...)
2024-06-13 8:22 ` [PATCH 09/15] net: hbl_en: add habanalabs Ethernet driver Omer Shpigelman
@ 2024-06-13 8:22 ` Omer Shpigelman
2024-06-13 8:22 ` [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver Omer Shpigelman
` (6 subsequent siblings)
16 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:22 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
Add Gaudi2 ASIC specific support for ethernet purpose which includes HW
specific configurations and operations.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
MAINTAINERS | 1 +
drivers/net/ethernet/intel/hbl_en/Makefile | 3 +
.../net/ethernet/intel/hbl_en/common/hbl_en.c | 2 +
.../net/ethernet/intel/hbl_en/common/hbl_en.h | 2 +
.../net/ethernet/intel/hbl_en/gaudi2/Makefile | 2 +
.../ethernet/intel/hbl_en/gaudi2/gaudi2_en.c | 728 ++++++++++++++++++
.../ethernet/intel/hbl_en/gaudi2/gaudi2_en.h | 53 ++
.../intel/hbl_en/gaudi2/gaudi2_en_dcbnl.c | 32 +
8 files changed, 823 insertions(+)
create mode 100644 drivers/net/ethernet/intel/hbl_en/gaudi2/Makefile
create mode 100644 drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en.c
create mode 100644 drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en.h
create mode 100644 drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en_dcbnl.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 7301f38e9cfb..01b82e9b672c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9625,6 +9625,7 @@ W: https://www.habana.ai
F: Documentation/networking/device_drivers/ethernet/intel/hbl.rst
F: drivers/net/ethernet/intel/hbl_en/
F: include/linux/net/intel/cn*
+F: include/linux/net/intel/gaudi2*
HACKRF MEDIA DRIVER
L: linux-media@vger.kernel.org
diff --git a/drivers/net/ethernet/intel/hbl_en/Makefile b/drivers/net/ethernet/intel/hbl_en/Makefile
index 695497ab93b6..adc81ddf7d10 100644
--- a/drivers/net/ethernet/intel/hbl_en/Makefile
+++ b/drivers/net/ethernet/intel/hbl_en/Makefile
@@ -7,3 +7,6 @@ obj-$(CONFIG_HABANA_EN) := habanalabs_en.o
include $(src)/common/Makefile
habanalabs_en-y += $(HBL_EN_COMMON_FILES)
+
+include $(src)/gaudi2/Makefile
+habanalabs_en-y += $(HBL_EN_GAUDI2_FILES)
diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
index 066be5ac2d84..7f071aea1b8e 100644
--- a/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
+++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
@@ -997,6 +997,8 @@ static int hbl_en_set_asic_funcs(struct hbl_en_device *hdev)
{
switch (hdev->asic_type) {
case HBL_ASIC_GAUDI2:
+ gaudi2_en_set_asic_funcs(hdev);
+ break;
default:
dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type);
return -EINVAL;
diff --git a/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
index 15504c1f3cfb..20259d610081 100644
--- a/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
+++ b/drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
@@ -203,4 +203,6 @@ int hbl_en_handle_rx(struct hbl_en_port *port, int budget);
dma_addr_t hbl_en_dma_map(struct hbl_en_device *hdev, void *addr, int len);
void hbl_en_dma_unmap(struct hbl_en_device *hdev, dma_addr_t dma_addr, int len);
+void gaudi2_en_set_asic_funcs(struct hbl_en_device *hdev);
+
#endif /* HABANALABS_EN_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_en/gaudi2/Makefile b/drivers/net/ethernet/intel/hbl_en/gaudi2/Makefile
new file mode 100644
index 000000000000..e95e714bcecf
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_en/gaudi2/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+HBL_EN_GAUDI2_FILES := gaudi2/gaudi2_en.o gaudi2/gaudi2_en_dcbnl.o
diff --git a/drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en.c b/drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en.c
new file mode 100644
index 000000000000..5be6d1d6aa3d
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en.c
@@ -0,0 +1,728 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "gaudi2_en.h"
+
+#include <linux/circ_buf.h>
+
+#define RING_SIZE_MASK(ring) ((ring)->count - 1)
+
+static void req_qpc_init(struct gaudi2_qpc_requester *req_qpc, unsigned int mtu, int last_idx,
+ u32 schedq_num, bool enable)
+{
+ REQ_QPC_SET_TRANSPORT_SERVICE(*req_qpc, TS_RAW);
+ REQ_QPC_SET_LAST_IDX(*req_qpc, last_idx);
+ REQ_QPC_SET_WQ_TYPE(*req_qpc, 1);
+ REQ_QPC_SET_WQ_BASE_ADDR(*req_qpc, 0);
+ REQ_QPC_SET_MTU(*req_qpc, mtu);
+ REQ_QPC_SET_REMOTE_WQ_LOG_SZ(*req_qpc, 1);
+ REQ_QPC_SET_VALID(*req_qpc, (u64)enable);
+ REQ_QPC_SET_TRUST_LEVEL(*req_qpc, SECURED);
+ REQ_QPC_SET_PORT(*req_qpc, 0);
+ REQ_QPC_SET_DATA_MMU_BYPASS(*req_qpc, 1);
+ REQ_QPC_SET_BURST_SIZE(*req_qpc, 1);
+ REQ_QPC_SET_SCHD_Q_NUM(*req_qpc, schedq_num);
+ /* Due to a HW bug, backpressure is indicated on the ETH QP after some time. In order to
+ * avoid the BP message being sent, set the QP as backpressured to begin with. This will
+ * have no further impact, as the BP mechanism is associated with RDMA only.
+ */
+ REQ_QPC_SET_WQ_BACK_PRESSURE(*req_qpc, 1);
+}
+
+static void res_qpc_init(struct gaudi2_qpc_responder *res_qpc, u32 raw_qpn, u32 schedq_num,
+ bool enable)
+{
+ RES_QPC_SET_TRANSPORT_SERVICE(*res_qpc, TS_RAW);
+ RES_QPC_SET_VALID(*res_qpc, (u64)enable);
+ RES_QPC_SET_TRUST_LEVEL(*res_qpc, SECURED);
+ RES_QPC_SET_PORT(*res_qpc, 0);
+ RES_QPC_SET_CQ_NUM(*res_qpc, raw_qpn);
+ RES_QPC_SET_DATA_MMU_BYPASS(*res_qpc, 1);
+ RES_QPC_SET_SCHD_Q_NUM(*res_qpc, schedq_num);
+}
+
+static int gaudi2_en_read_pkt_from_hw(struct hbl_en_port *port, void **pkt_addr, u32 *pkt_size)
+{
+ struct gaudi2_en_port *gaudi2_port = port->asic_specific;
+ struct hbl_en_device *hdev = port->hdev;
+ struct hbl_cn_ring *rx_ring, *cq_ring;
+ enum hbl_en_eth_pkt_status pkt_status;
+ struct gaudi2_en_aux_ops *aux_ops;
+ struct gaudi2_en_device *gaudi2;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+ struct gaudi2_cqe *cqe_p;
+ u32 pi, size, wqe_idx;
+
+ gaudi2 = hdev->asic_specific;
+ aux_ops = gaudi2->aux_ops;
+ aux_dev = hdev->aux_dev;
+
+ rx_ring = gaudi2_port->rx_ring;
+ cq_ring = gaudi2_port->cq_ring;
+
+ /* check if packet is available by reading the PI */
+ if (cq_ring->ci_shadow == cq_ring->pi_shadow) {
+ pi = *((u32 *)RING_PI_ADDRESS(cq_ring));
+ if (pi == cq_ring->pi_shadow)
+ return ETH_PKT_NONE;
+
+ cq_ring->pi_shadow = pi;
+ }
+
+ cqe_p = (struct gaudi2_cqe *)RING_BUF_ADDRESS(cq_ring) +
+ (cq_ring->ci_shadow & RING_SIZE_MASK(cq_ring));
+
+ if (!CQE_IS_VALID(cqe_p)) {
+ dev_warn_ratelimited(hdev->dev, "Port-%d got invalid CQE on CQ\n", port_idx);
+ return ETH_PKT_DROP;
+ }
+
+ pkt_status = ETH_PKT_OK;
+
+ /* wqe index will point to the buffer consumed by HW */
+ wqe_idx = CQE_WQE_IDX(cqe_p) & RING_SIZE_MASK(rx_ring);
+ size = CQE_RAW_PKT_SIZE(cqe_p);
+
+ /* Since CQE is valid, SW must consume it, even if packet would eventually be dropped. */
+ if (size > hdev->max_frm_len || size == 0) {
+ dev_warn_ratelimited(hdev->dev, "Port-%d got invalid packet size %u\n",
+ port_idx, size);
+ pkt_status = ETH_PKT_DROP;
+ }
+
+ *pkt_addr = RING_BUF_ADDRESS(rx_ring) + wqe_idx * hdev->raw_elem_size;
+ *pkt_size = size;
+
+ cq_ring->ci_shadow++;
+
+ /* Mark the CQ-entry is not valid */
+ CQE_SET_INVALID(cqe_p);
+
+ /* inform the HW with our current CI */
+ aux_ops->write_rx_ci(aux_dev, port_idx, cq_ring->ci_shadow);
+
+ return pkt_status;
+}
+
+static int gaudi2_en_get_rx_ring_size(struct hbl_en_port *port)
+{
+ struct gaudi2_en_port *gaudi2_port = port->asic_specific;
+ struct hbl_cn_ring *rx_ring;
+
+ rx_ring = gaudi2_port->rx_ring;
+
+ return RING_SIZE_MASK(rx_ring);
+}
+
+static void gaudi2_en_configure_cq(struct hbl_en_port *port, bool enable)
+{
+ struct hbl_en_device *hdev = port->hdev;
+ struct gaudi2_en_aux_ops *aux_ops;
+ struct gaudi2_en_device *gaudi2;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+
+ gaudi2 = hdev->asic_specific;
+ aux_ops = gaudi2->aux_ops;
+ aux_dev = hdev->aux_dev;
+
+ /* if rx_coalesce_usecs is 0 then timer should be disabled */
+ aux_ops->configure_cq(aux_dev, port_idx, port->rx_coalesce_usecs,
+ port->rx_coalesce_usecs ? enable : false);
+}
+
+static void gaudi2_en_arm_cq(struct hbl_en_port *port)
+{
+ struct gaudi2_en_port *gaudi2_port = port->asic_specific;
+ struct hbl_en_device *hdev = port->hdev;
+ struct gaudi2_en_aux_ops *aux_ops;
+ struct gaudi2_en_device *gaudi2;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+
+ gaudi2 = hdev->asic_specific;
+ aux_ops = gaudi2->aux_ops;
+ aux_dev = hdev->aux_dev;
+
+ /* The trigger happens only when PI > IDX, therefore subtract 1 from arming index */
+ aux_ops->arm_cq(aux_dev, port_idx,
+ gaudi2_port->cq_ring->ci_shadow + port->rx_max_coalesced_frames - 1);
+}
+
+static int gaudi2_en_set_coalesce(struct hbl_en_port *port)
+{
+ struct hbl_en_device *hdev = port->hdev;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port_idx = port->idx;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ if (!aux_ops->is_port_open(aux_dev, port_idx))
+ return 0;
+
+ gaudi2_en_configure_cq(port, port->is_initialized);
+ gaudi2_en_arm_cq(port);
+
+ return 0;
+}
+
+static int gaudi2_en_config_qp(struct hbl_en_port *port, bool enable)
+{
+ struct gaudi2_en_port *gaudi2_port = port->asic_specific;
+ struct hbl_en_device *hdev = gaudi2_port->hdev;
+ struct gaudi2_qpc_requester req_qpc = {};
+ struct gaudi2_qpc_responder res_qpc = {};
+ struct net_device *ndev = port->ndev;
+ struct gaudi2_en_aux_data *aux_data;
+ u32 port_idx, raw_qpn, schedq_num;
+ struct gaudi2_en_device *gaudi2;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ struct qpc_mask mask = {};
+ int last_idx, rc;
+ unsigned int mtu;
+
+ gaudi2 = hdev->asic_specific;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ aux_data = gaudi2->aux_data;
+ port_idx = gaudi2_port->idx;
+ raw_qpn = aux_data->raw_qpn;
+ schedq_num = aux_data->schedq_num;
+ mtu = ndev->mtu + HBL_EN_MAX_HEADERS_SZ;
+
+ /* Need to configure the log of the MTU value minus 1KB as this is the minimum valid MTU.
+ * If the MTU value is not a power of 2, use the next possible value.
+ */
+ mtu = __fls(mtu) - 10 + !is_power_of_2(mtu);
+
+ last_idx = gaudi2_port->wq_ring->count - 1;
+
+ if (!enable) {
+ rc = aux_ops->eq_dispatcher_unregister_qp(aux_dev, port_idx, raw_qpn);
+ if (rc) {
+ netdev_err(ndev, "Failed to unregister QP, %d\n", rc);
+ return rc;
+ }
+
+ REQ_QPC_SET_VALID(mask, 1);
+ rc = aux_ops->qpc_write(aux_dev, port_idx, &req_qpc, &mask, raw_qpn, true);
+ if (rc) {
+ netdev_err(ndev, "Failed to configure requester QP, %d\n", rc);
+ return rc;
+ }
+
+ memset(&mask, 0, sizeof(mask));
+ RES_QPC_SET_VALID(mask, 1);
+ rc = aux_ops->qpc_write(aux_dev, port_idx, &res_qpc, &mask, raw_qpn, false);
+ if (rc)
+ netdev_err(ndev, "Failed to configure responder QP, %d\n", rc);
+
+ return rc;
+ }
+
+ memset(&res_qpc, 0, sizeof(res_qpc));
+ res_qpc_init(&res_qpc, raw_qpn, schedq_num, enable);
+ rc = aux_ops->qpc_write(aux_dev, port_idx, &res_qpc, NULL, raw_qpn, false);
+ if (rc) {
+ netdev_err(ndev, "Failed to configure responder QP, %d\n", rc);
+ goto qp_register_fail;
+ }
+
+ memset(&req_qpc, 0, sizeof(req_qpc));
+ req_qpc_init(&req_qpc, mtu, last_idx, schedq_num, enable);
+ rc = aux_ops->qpc_write(aux_dev, port_idx, &req_qpc, NULL, raw_qpn, true);
+ if (rc) {
+ netdev_err(ndev, "Failed to configure requester QP, %d\n", rc);
+ goto qp_register_fail;
+ }
+
+ rc = aux_ops->eq_dispatcher_register_qp(aux_dev, port_idx, aux_data->kernel_asid, raw_qpn);
+ if (rc) {
+ netdev_err(ndev, "Failed to register QP, %d\n", rc);
+ goto qp_register_fail;
+ }
+
+ return 0;
+
+qp_register_fail:
+ memset(&res_qpc, 0, sizeof(res_qpc));
+ RES_QPC_SET_VALID(res_qpc, 0);
+ aux_ops->qpc_write(aux_dev, port_idx, &res_qpc, NULL, raw_qpn, false);
+ memset(&req_qpc, 0, sizeof(req_qpc));
+ REQ_QPC_SET_VALID(req_qpc, 0);
+ aux_ops->qpc_write(aux_dev, port_idx, &req_qpc, NULL, raw_qpn, true);
+
+ return rc;
+}
+
+static void gaudi2_en_tx_done(struct gaudi2_en_port *gaudi2_port, struct hbl_cn_eqe *eqe_p)
+{
+ u32 port_idx, raw_qpn, handled_ci, pi, previous_pi;
+ struct hbl_en_device *hdev = gaudi2_port->hdev;
+ struct gaudi2_en_aux_data *asic_aux_data;
+ struct hbl_en_aux_data *aux_data;
+ struct gaudi2_en_tx_buf *tx_buf;
+ struct netdev_queue *netdev_txq;
+ struct hbl_aux_dev *aux_dev;
+ struct net_device *ndev;
+
+ port_idx = gaudi2_port->idx;
+ ndev = hdev->ports[port_idx].ndev;
+ aux_dev = hdev->aux_dev;
+ aux_data = aux_dev->aux_data;
+ asic_aux_data = aux_data->asic_specific;
+ raw_qpn = asic_aux_data->raw_qpn;
+
+ if (EQE_RAW_TX_EVENT_QPN(eqe_p) != raw_qpn) {
+ netdev_warn(ndev, "tx-done: port %d got wrong QP (%d vs %d); ignoring", port_idx,
+ EQE_RAW_TX_EVENT_QPN(eqe_p), raw_qpn);
+ return;
+ }
+
+ if (EQE_RAW_TX_EVENT_IDX(eqe_p) >= asic_aux_data->tx_ring_len) {
+ netdev_err(ndev, "tx-done: port %d got invalid WQE index (%d max %d); ignoring",
+ port_idx, EQE_RAW_TX_EVENT_IDX(eqe_p), asic_aux_data->tx_ring_len - 1);
+ return;
+ }
+
+ netdev_txq = netdev_get_tx_queue(ndev, 0);
+
+ /* Here we need to acquire the Tx lock (which is acquired also by the Tx handler) in order
+ * to prevent races when accessing to the Tx buffer and stopping/waking the netdev queue.
+ */
+ __netif_tx_lock_bh(netdev_txq);
+
+ /* Check if the index we got is in the current data bounds (indicated by the CI and PI).
+ * The out of bounds region is [PI,CI-1] circulary
+ */
+ pi = gaudi2_port->tx_buf_info_pi;
+ previous_pi = CIRC_CNT(pi, 1, asic_aux_data->tx_ring_len);
+
+ if (CIRC_CNT(previous_pi, EQE_RAW_TX_EVENT_IDX(eqe_p), asic_aux_data->tx_ring_len) >=
+ CIRC_CNT(pi, gaudi2_port->tx_buf_info_ci, asic_aux_data->tx_ring_len)) {
+ dev_warn_ratelimited(hdev->dev,
+ "tx-done: port %d got stale WQE index (expecting values between 0x%x to 0x%x, got 0x%x); ignoring",
+ port_idx, gaudi2_port->tx_buf_info_ci, pi,
+ EQE_RAW_TX_EVENT_IDX(eqe_p));
+ goto out;
+ }
+
+ /* Handle all entries up to the entry reported in the event */
+ do {
+ tx_buf = gaudi2_port->tx_buf_info + gaudi2_port->tx_buf_info_ci;
+ if (!tx_buf->skb) {
+ dev_warn_ratelimited(hdev->dev,
+ "Port-%d attempted to free a NULL element in TX ring (ci 0x%x, pi 0x%x, idx 0x%x)\n",
+ port_idx, gaudi2_port->tx_buf_info_ci, pi,
+ EQE_RAW_TX_EVENT_IDX(eqe_p));
+ goto out;
+ }
+ hbl_en_dma_unmap(hdev, tx_buf->dma_addr, tx_buf->len);
+ dev_consume_skb_any(tx_buf->skb);
+
+ tx_buf->skb = NULL;
+ handled_ci = gaudi2_port->tx_buf_info_ci;
+ gaudi2_port->tx_buf_info_ci =
+ (gaudi2_port->tx_buf_info_ci + 1) & (asic_aux_data->tx_ring_len - 1);
+ } while (EQE_RAW_TX_EVENT_IDX(eqe_p) != handled_ci);
+
+ /* No need to check for fifo space because if queue was stopped then fifo has room by now
+ * as it cleaned within a device cycle. In addition, wake the queue only if link is UP.
+ */
+ if (netif_queue_stopped(ndev) && netif_carrier_ok(ndev))
+ netif_wake_queue(ndev);
+
+out:
+ __netif_tx_unlock_bh(netdev_txq);
+}
+
+static u32 gaudi2_en_get_overrun_cnt(struct hbl_aux_dev *aux_dev, u32 port_idx)
+{
+ struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
+ struct gaudi2_en_port *gaudi2_port;
+
+ gaudi2_port = port->asic_specific;
+
+ return gaudi2_port->fifo_overrun_err_cnt;
+}
+
+static void gaudi2_en_handle_eqe(struct hbl_aux_dev *aux_dev, u32 port_idx, struct hbl_cn_eqe *eqe)
+{
+ struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
+ u32 event_type = EQE_TYPE(eqe), qp, synd;
+ struct hbl_en_device *hdev = port->hdev;
+ struct gaudi2_en_aux_ops *asic_aux_ops;
+ struct gaudi2_en_port *gaudi2_port;
+ struct hbl_en_aux_ops *aux_ops;
+
+ gaudi2_port = port->asic_specific;
+ aux_ops = hdev->aux_dev->aux_ops;
+ asic_aux_ops = aux_ops->asic_ops;
+
+ if (!EQE_IS_VALID(eqe)) {
+ dev_warn_ratelimited(hdev->dev, "Port-%d got invalid EQE on EQ!\n", port_idx);
+ return;
+ }
+
+ switch (event_type) {
+ case EQE_COMP_ERR:
+ dev_warn_ratelimited(hdev->dev, "Port-%d cq-err event CQ:%d PI:0x%x\n",
+ port_idx, EQE_CQ_EVENT_CQ_NUM(eqe), EQE_CQ_EVENT_PI(eqe));
+
+ atomic64_inc(&port->net_stats.rx_dropped);
+ /* CQ is configured to generate BP on such cases hence we just need to handle
+ * the packets in the Rx buffer
+ */
+ fallthrough;
+ case EQE_COMP:
+ if (!hdev->poll_enable) {
+ /* napi_schedule() eventually calls __raise_softirq_irqoff() which sets the
+ * net Rx softirq to run. Since we are in thread context here, the pending
+ * softirq flag won't be checked and the Rx softirq won't be invoked. Hence
+ * we need to use the bh_disable/enable pair to invoke it.
+ */
+ local_bh_disable();
+ napi_schedule(&port->napi);
+ local_bh_enable();
+ } else {
+ hbl_en_rx_poll_start(port);
+ }
+ break;
+ case EQE_RAW_TX_COMP:
+ gaudi2_en_tx_done(gaudi2_port, eqe);
+ break;
+ case EQE_QP_ERR:
+ synd = EQE_QP_EVENT_ERR_SYND(eqe);
+ qp = EQE_QP_EVENT_QPN(eqe);
+ dev_err_ratelimited(hdev->dev, "Port-%d qp-err event QP:%d err:%d %s\n", port_idx,
+ qp, synd, asic_aux_ops->qp_err_syndrome_to_str(synd));
+
+ /* In case of QP error we need to reset the port. We are calling the "locked"
+ * version of that function since the port->control_lock has been already
+ * taken at the beginning of the EQ handler.
+ */
+ dev_err_ratelimited(hdev->dev, "Going to reset port %d\n", port_idx);
+ aux_ops->track_ext_port_reset(aux_dev, port_idx, synd);
+ hbl_en_port_reset_locked(aux_dev, port_idx);
+ break;
+ case EQE_DB_FIFO_OVERRUN:
+ dev_warn_ratelimited(hdev->dev, "Port-%d db-fifo overrun event\n", port_idx);
+ gaudi2_port->fifo_overrun_err_cnt++;
+ atomic64_inc(&port->net_stats.tx_dropped);
+ break;
+ default:
+ dev_warn_ratelimited(hdev->dev, "Port-%d unsupported event type: %d", port_idx,
+ event_type);
+ break;
+ }
+}
+
+static netdev_tx_t gaudi2_en_write_pkt_to_hw(struct hbl_en_port *port, struct sk_buff *skb)
+{
+ u32 port_idx, tx_buf_info_pi, pi, space_left_in_qp, wq_ring_pi;
+ struct gaudi2_en_port *gaudi2_port = port->asic_specific;
+ struct hbl_en_device *hdev = gaudi2_port->hdev;
+ struct gaudi2_en_aux_data *asic_aux_data;
+ struct net_device *ndev = port->ndev;
+ struct gaudi2_en_aux_ops *aux_ops;
+ struct hbl_en_aux_data *aux_data;
+ struct gaudi2_en_device *gaudi2;
+ struct gaudi2_sq_wqe *wqe_p;
+ struct hbl_cn_ring *wq_ring;
+ struct hbl_aux_dev *aux_dev;
+ bool db_fifo_full_after_tx;
+ dma_addr_t dma_addr;
+ int rc;
+
+ tx_buf_info_pi = gaudi2_port->tx_buf_info_pi;
+ port_idx = port->idx;
+ gaudi2 = hdev->asic_specific;
+ aux_ops = gaudi2->aux_ops;
+ aux_dev = hdev->aux_dev;
+ aux_data = aux_dev->aux_data;
+ asic_aux_data = aux_data->asic_specific;
+ wq_ring = gaudi2_port->wq_ring;
+
+ dma_addr = hbl_en_dma_map(hdev, skb->data, skb->len);
+ if (unlikely(dma_mapping_error(hdev->dev, dma_addr))) {
+ dev_err_ratelimited(hdev->dev, "port %d failed to map DMA address\n", port_idx);
+ dev_kfree_skb_any(skb);
+ return NETDEV_TX_OK;
+ }
+
+ gaudi2_port->tx_buf_info[tx_buf_info_pi].dma_addr = dma_addr;
+ gaudi2_port->tx_buf_info[tx_buf_info_pi].skb = skb;
+ gaudi2_port->tx_buf_info[tx_buf_info_pi].len = skb->len;
+ gaudi2_port->tx_buf_info_pi = (tx_buf_info_pi + 1) & (asic_aux_data->tx_ring_len - 1);
+
+ /* point on the next WQE */
+ pi = wq_ring->pi_shadow;
+ wq_ring_pi = (wq_ring->pi_shadow + 1) & (wq_ring->count - 1);
+
+ wqe_p = (struct gaudi2_sq_wqe *)RING_BUF_ADDRESS(wq_ring) + pi;
+ memset(wqe_p, 0, sizeof(*wqe_p));
+
+ /* for ethernet only, turn on the solicite event bit */
+ CFG_SQ_WQE_RESET(wqe_p);
+ CFG_SQ_WQE_OPCODE(wqe_p, WQE_LINEAR);
+ CFG_SQ_WQE_INDEX(wqe_p, pi & 0xff);
+ CFG_SQ_WQE_INLINE(wqe_p, 0);
+ CFG_SQ_WQE_LOCAL_ADDRESS(wqe_p, dma_addr);
+ CFG_SQ_WQE_SIZE(wqe_p, (u64)skb->len);
+ CFG_SQ_WQE_SOL_EVENT(wqe_p, (pi % port->tx_max_coalesced_frames) ? 0 : 1);
+
+ /* make sure data is filled before ringing the db */
+ mb();
+
+ /* Ring doorbell */
+ rc = aux_ops->ring_tx_doorbell(aux_dev, port_idx, wq_ring_pi, &db_fifo_full_after_tx);
+ if (rc) {
+ /* Fifo is full, revert indices, unmap the skb, stop queue and return the error. */
+ gaudi2_port->tx_buf_info_pi = tx_buf_info_pi;
+ hbl_en_dma_unmap(hdev, dma_addr, skb->len);
+ gaudi2_port->tx_buf_info[tx_buf_info_pi].skb = NULL;
+
+ netdev_dbg(ndev, "port: %d stop queue due to full fifo - packet not sent\n",
+ port_idx);
+ netif_stop_queue(skb->dev);
+
+ return NETDEV_TX_BUSY;
+ }
+
+ wq_ring->pi_shadow = wq_ring_pi;
+
+ /* Check if we have enough space on the QP-WQ for the next xmit. */
+ space_left_in_qp = CIRC_SPACE(gaudi2_port->tx_buf_info_pi, gaudi2_port->tx_buf_info_ci,
+ asic_aux_data->tx_ring_len);
+ if (!space_left_in_qp || db_fifo_full_after_tx) {
+ netdev_dbg(ndev, "port: %d stop queue due to full %s\n", port_idx,
+ db_fifo_full_after_tx ? "fifo" : "WQ");
+ netif_stop_queue(skb->dev);
+ }
+
+ return NETDEV_TX_OK;
+}
+
+static int gaudi2_en_port_open(struct hbl_en_port *port)
+{
+ struct gaudi2_en_port *gaudi2_port = port->asic_specific;
+ struct hbl_cn_ring *wq_ring, *cq_ring;
+ int rc;
+
+ /* Reset Tx ring shadow PI/CI */
+ wq_ring = gaudi2_port->wq_ring;
+ wq_ring->pi_shadow = 0;
+ wq_ring->ci_shadow = 0; /* Unused */
+
+ /* Reset SW Tx buffer PI/CI */
+ gaudi2_port->tx_buf_info_pi = 0;
+ gaudi2_port->tx_buf_info_ci = 0;
+
+ /* Reset FIFO overrun error counter */
+ gaudi2_port->fifo_overrun_err_cnt = 0;
+
+ /* Reset CQ ring HW PI and shadow PI/CI */
+ cq_ring = gaudi2_port->cq_ring;
+ *((u32 *)RING_PI_ADDRESS(cq_ring)) = 0;
+ cq_ring->pi_shadow = 0;
+ cq_ring->ci_shadow = 0;
+
+ rc = gaudi2_en_config_qp(port, true);
+ if (rc) {
+ netdev_warn(port->ndev, "Failed to configure QPs, %d\n", rc);
+ return rc;
+ }
+
+ /* We would need the CQ-ARM for both polling and NAPI flows. This is because, even in
+ * polling mode, we would start the Rx Poll only upon the CQ-ARM event triggering the EQ
+ * for Rx completion.
+ */
+ gaudi2_en_configure_cq(port, true);
+ gaudi2_en_arm_cq(port);
+
+ return 0;
+}
+
+static void gaudi2_en_db_fifo_reset(struct gaudi2_en_port *gaudi2_port)
+{
+ struct hbl_en_device *hdev = gaudi2_port->hdev;
+ struct gaudi2_en_aux_ops *asic_aux_ops;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ asic_aux_ops = aux_ops->asic_ops;
+
+ asic_aux_ops->db_fifo_reset(aux_dev, gaudi2_port->idx);
+}
+
+static void gaudi2_en_flush_tx_buffer(struct gaudi2_en_port *gaudi2_port)
+{
+ struct hbl_en_device *hdev = gaudi2_port->hdev;
+ struct gaudi2_en_aux_data *asic_aux_data;
+ struct hbl_en_aux_data *aux_data;
+ struct gaudi2_en_tx_buf *tx_buf;
+ struct hbl_aux_dev *aux_dev;
+ u32 ci, pi;
+
+ aux_dev = hdev->aux_dev;
+ aux_data = aux_dev->aux_data;
+ asic_aux_data = aux_data->asic_specific;
+ ci = gaudi2_port->tx_buf_info_ci;
+ pi = gaudi2_port->tx_buf_info_pi;
+
+ while (ci != pi) {
+ tx_buf = &gaudi2_port->tx_buf_info[ci];
+ hbl_en_dma_unmap(hdev, tx_buf->dma_addr, tx_buf->len);
+ dev_kfree_skb_any(tx_buf->skb);
+
+ ci = (ci + 1) & (asic_aux_data->tx_ring_len - 1);
+ }
+
+ gaudi2_port->tx_buf_info_ci = ci;
+}
+
+static void gaudi2_en_port_close(struct hbl_en_port *port)
+{
+ struct gaudi2_en_port *gaudi2_port = port->asic_specific;
+ int rc;
+
+ gaudi2_en_configure_cq(port, false);
+
+ /* disable ETH Rx/Tx in H/W */
+ rc = gaudi2_en_config_qp(port, false);
+ if (rc)
+ netdev_warn(port->ndev, "Failed to destroy QPs, %d\n", rc);
+
+ gaudi2_en_db_fifo_reset(gaudi2_port);
+
+ /* Discard skbs safely from tx_buf as we won't get the tx_done call from the EQ now that the
+ * port is closed.
+ */
+ gaudi2_en_flush_tx_buffer(gaudi2_port);
+}
+
+static int gaudi2_en_dev_init(struct hbl_en_device *hdev)
+{
+ struct hbl_aux_dev *aux_dev = hdev->aux_dev;
+ struct gaudi2_en_port *gaudi2_port, *ports;
+ struct gaudi2_en_aux_data *asic_aux_data;
+ struct gaudi2_en_aux_ops *asic_aux_ops;
+ struct hbl_en_aux_data *aux_data;
+ struct gaudi2_en_device *gaudi2;
+ struct hbl_en_aux_ops *aux_ops;
+ int i, rc = 0, ports_cnt = 0;
+ struct hbl_en_port *port;
+ u32 tx_ring_size;
+
+ aux_data = aux_dev->aux_data;
+ asic_aux_data = aux_data->asic_specific;
+ aux_ops = aux_dev->aux_ops;
+ asic_aux_ops = aux_ops->asic_ops;
+
+ gaudi2 = kzalloc(sizeof(*gaudi2), GFP_KERNEL);
+ if (!gaudi2)
+ return -ENOMEM;
+
+ ports = kcalloc(hdev->max_num_of_ports, sizeof(*ports), GFP_KERNEL);
+ if (!ports) {
+ rc = -ENOMEM;
+ goto ports_alloc_fail;
+ }
+
+ tx_ring_size = asic_aux_data->tx_ring_len * sizeof(struct gaudi2_en_tx_buf);
+
+ for (i = 0; i < hdev->max_num_of_ports; i++, ports_cnt++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ gaudi2_port = &ports[i];
+ gaudi2_port->tx_buf_info = kzalloc(tx_ring_size, GFP_KERNEL);
+ if (!gaudi2_port->tx_buf_info) {
+ rc = -ENOMEM;
+ goto ports_init_fail;
+ }
+
+ gaudi2_port->idx = i;
+ gaudi2_port->hdev = hdev;
+ gaudi2_port->rx_ring = asic_aux_data->rx_rings[i];
+ gaudi2_port->cq_ring = asic_aux_data->cq_rings[i];
+ gaudi2_port->wq_ring = asic_aux_data->wq_rings[i];
+ port = &hdev->ports[i];
+ port->asic_specific = gaudi2_port;
+ }
+
+ asic_aux_ops->port_reset_locked = hbl_en_port_reset_locked;
+ asic_aux_ops->get_overrun_cnt = gaudi2_en_get_overrun_cnt;
+
+ gaudi2->ports = ports;
+ gaudi2->aux_data = asic_aux_data;
+ gaudi2->aux_ops = asic_aux_ops;
+
+ hdev->asic_specific = gaudi2;
+
+ hdev->pad_size = gaudi2->aux_data->pad_size;
+
+ return 0;
+
+ports_init_fail:
+ for (i = 0; i < ports_cnt; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ gaudi2_port = &ports[i];
+ kfree(gaudi2_port->tx_buf_info);
+ }
+
+ kfree(ports);
+ports_alloc_fail:
+ kfree(gaudi2);
+
+ return rc;
+}
+
+static void gaudi2_en_dev_fini(struct hbl_en_device *hdev)
+{
+ struct gaudi2_en_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_en_port *gaudi2_port;
+ int i;
+
+ if (!gaudi2)
+ return;
+
+ for (i = 0; i < hdev->max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ gaudi2_port = &gaudi2->ports[i];
+ kfree(gaudi2_port->tx_buf_info);
+ }
+
+ kfree(gaudi2->ports);
+ kfree(gaudi2);
+}
+
+void gaudi2_en_set_asic_funcs(struct hbl_en_device *hdev)
+{
+ struct hbl_en_asic_funcs *asic_funcs = &hdev->asic_funcs;
+
+ asic_funcs->dev_init = gaudi2_en_dev_init;
+ asic_funcs->dev_fini = gaudi2_en_dev_fini;
+ asic_funcs->eth_port_open = gaudi2_en_port_open;
+ asic_funcs->eth_port_close = gaudi2_en_port_close;
+ asic_funcs->reenable_rx_irq = gaudi2_en_arm_cq;
+ asic_funcs->write_pkt_to_hw = gaudi2_en_write_pkt_to_hw;
+ asic_funcs->read_pkt_from_hw = gaudi2_en_read_pkt_from_hw;
+ asic_funcs->get_pfc_cnts = gaudi2_en_dcbnl_get_pfc_cnts;
+ asic_funcs->set_coalesce = gaudi2_en_set_coalesce;
+ asic_funcs->get_rx_ring_size = gaudi2_en_get_rx_ring_size;
+ asic_funcs->handle_eqe = gaudi2_en_handle_eqe;
+}
diff --git a/drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en.h b/drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en.h
new file mode 100644
index 000000000000..ec5084462899
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#ifndef GAUDI2_EN_H_
+#define GAUDI2_EN_H_
+
+#include <linux/net/intel/gaudi2.h>
+
+#include "../common/hbl_en.h"
+
+/**
+ * struct gaudi2_en_device - Gaudi2 device structure.
+ * @ports: array of Gaudi2 ports structures.
+ * @aux_data: relevant data from the core device.
+ * @aux_ops: pointer functions for core <-> en drivers communication.
+ */
+struct gaudi2_en_device {
+ struct gaudi2_en_port *ports;
+ struct gaudi2_en_aux_data *aux_data;
+ struct gaudi2_en_aux_ops *aux_ops;
+};
+
+/**
+ * struct gaudi2_en_port - Gaudi2 port structure.
+ * @hdev: habanalabs device structure.
+ * @rx_ring: raw skb ring.
+ * @cq_ring: packets completion ring.
+ * @wq_ring: work queue ring.
+ * @tx_buf_info: Tx packets ring.
+ * @idx: port index.
+ * @tx_buf_info_pi: Tx producer index.
+ * @tx_buf_info_ci: Tx consumer index.
+ * @fifo_overrrun_err_cnt: error count of fifo overrun
+ */
+struct gaudi2_en_port {
+ struct hbl_en_device *hdev;
+ struct hbl_cn_ring *rx_ring;
+ struct hbl_cn_ring *cq_ring;
+ struct hbl_cn_ring *wq_ring;
+ struct gaudi2_en_tx_buf *tx_buf_info;
+ u32 idx;
+ u32 tx_buf_info_pi;
+ u32 tx_buf_info_ci;
+ u32 fifo_overrun_err_cnt;
+};
+
+void gaudi2_en_dcbnl_get_pfc_cnts(struct hbl_en_port *port, void *ptr);
+
+#endif /* GAUDI2_EN_H_ */
diff --git a/drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en_dcbnl.c b/drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en_dcbnl.c
new file mode 100644
index 000000000000..f565d7648823
--- /dev/null
+++ b/drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en_dcbnl.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "gaudi2_en.h"
+
+void gaudi2_en_dcbnl_get_pfc_cnts(struct hbl_en_port *port, void *ptr)
+{
+#ifdef CONFIG_DCB
+ struct hbl_en_device *hdev = port->hdev;
+ struct gaudi2_en_aux_ops *asic_aux_ops;
+ struct hbl_en_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ struct ieee_pfc *pfc = ptr;
+ u64 indications, requests;
+ u32 port_idx = port->idx;
+ int pfc_prio;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ asic_aux_ops = aux_ops->asic_ops;
+
+ for (pfc_prio = 0; pfc_prio < HBL_EN_PFC_PRIO_NUM; pfc_prio++) {
+ asic_aux_ops->get_pfc_cnts(aux_dev, port_idx, pfc_prio, &indications, &requests);
+
+ pfc->indications[pfc_prio] = indications;
+ pfc->requests[pfc_prio] = requests;
+ }
+#endif
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
` (9 preceding siblings ...)
2024-06-13 8:22 ` [PATCH 10/15] net: hbl_en: gaudi2: ASIC specific support Omer Shpigelman
@ 2024-06-13 8:22 ` Omer Shpigelman
2024-06-13 19:18 ` Leon Romanovsky
2024-06-17 14:17 ` Jason Gunthorpe
2024-06-13 8:22 ` [PATCH 12/15] RDMA/hbl: direct verbs support Omer Shpigelman
` (5 subsequent siblings)
16 siblings, 2 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:22 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
Add an RDMA driver of Gaudi ASICs family for AI scaling.
The driver itself is agnostic to the ASIC in action, it operates according
to the capabilities that were passed on device initialization.
The device is initialized by the hbl_cn driver via auxiliary bus.
The driver also supports QP resource tracking and port/device HW counters.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
MAINTAINERS | 10 +
drivers/infiniband/Kconfig | 1 +
drivers/infiniband/hw/Makefile | 1 +
drivers/infiniband/hw/hbl/Kconfig | 17 +
drivers/infiniband/hw/hbl/Makefile | 8 +
drivers/infiniband/hw/hbl/hbl.h | 326 +++
drivers/infiniband/hw/hbl/hbl_main.c | 478 ++++
drivers/infiniband/hw/hbl/hbl_verbs.c | 2686 ++++++++++++++++++++++
include/uapi/rdma/hbl-abi.h | 204 ++
include/uapi/rdma/hbl_user_ioctl_cmds.h | 66 +
include/uapi/rdma/hbl_user_ioctl_verbs.h | 106 +
include/uapi/rdma/ib_user_ioctl_verbs.h | 1 +
12 files changed, 3904 insertions(+)
create mode 100644 drivers/infiniband/hw/hbl/Kconfig
create mode 100644 drivers/infiniband/hw/hbl/Makefile
create mode 100644 drivers/infiniband/hw/hbl/hbl.h
create mode 100644 drivers/infiniband/hw/hbl/hbl_main.c
create mode 100644 drivers/infiniband/hw/hbl/hbl_verbs.c
create mode 100644 include/uapi/rdma/hbl-abi.h
create mode 100644 include/uapi/rdma/hbl_user_ioctl_cmds.h
create mode 100644 include/uapi/rdma/hbl_user_ioctl_verbs.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 01b82e9b672c..d754eb13cb58 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9627,6 +9627,16 @@ F: drivers/net/ethernet/intel/hbl_en/
F: include/linux/net/intel/cn*
F: include/linux/net/intel/gaudi2*
+HABANALABS IB DRIVER
+M: Omer Shpigelman <oshpigelman@habana.ai>
+L: linux-rdma@vger.kernel.org
+S: Supported
+W: https://www.habana.ai
+Q: https://patchwork.kernel.org/project/linux-rdma/list/
+F: drivers/infiniband/hw/hbl/
+F: include/linux/net/intel/cn*
+F: include/uapi/rdma/hbl-abi.h
+
HACKRF MEDIA DRIVER
L: linux-media@vger.kernel.org
S: Orphan
diff --git a/drivers/infiniband/Kconfig b/drivers/infiniband/Kconfig
index a5827d11e934..8f913558b816 100644
--- a/drivers/infiniband/Kconfig
+++ b/drivers/infiniband/Kconfig
@@ -83,6 +83,7 @@ source "drivers/infiniband/hw/bnxt_re/Kconfig"
source "drivers/infiniband/hw/cxgb4/Kconfig"
source "drivers/infiniband/hw/efa/Kconfig"
source "drivers/infiniband/hw/erdma/Kconfig"
+source "drivers/infiniband/hw/hbl/Kconfig"
source "drivers/infiniband/hw/hfi1/Kconfig"
source "drivers/infiniband/hw/hns/Kconfig"
source "drivers/infiniband/hw/irdma/Kconfig"
diff --git a/drivers/infiniband/hw/Makefile b/drivers/infiniband/hw/Makefile
index 1211f4317a9f..e8fc49b1bb03 100644
--- a/drivers/infiniband/hw/Makefile
+++ b/drivers/infiniband/hw/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_INFINIBAND_MTHCA) += mthca/
obj-$(CONFIG_INFINIBAND_QIB) += qib/
obj-$(CONFIG_INFINIBAND_CXGB4) += cxgb4/
obj-$(CONFIG_INFINIBAND_EFA) += efa/
+obj-$(CONFIG_INFINIBAND_HBL) += hbl/
obj-$(CONFIG_INFINIBAND_IRDMA) += irdma/
obj-$(CONFIG_MANA_INFINIBAND) += mana/
obj-$(CONFIG_MLX4_INFINIBAND) += mlx4/
diff --git a/drivers/infiniband/hw/hbl/Kconfig b/drivers/infiniband/hw/hbl/Kconfig
new file mode 100644
index 000000000000..90c865a82540
--- /dev/null
+++ b/drivers/infiniband/hw/hbl/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# HabanaLabs (an Intel Company) Infiniband driver configuration
+#
+
+config INFINIBAND_HBL
+ tristate "HabanaLabs (an Intel Company) InfiniBand driver"
+ depends on NETDEVICES && ETHERNET && PCI && INET
+ select HABANA_CN
+ help
+ This driver enables InfiniBand functionality for the network
+ interfaces that are part of the GAUDI ASIC family of AI Accelerators.
+ The network interfaces are mainly used for scaling-out the training of
+ AI Neural Networks through ROCEv2 protocol.
+
+ To compile this driver as a module, choose M here. The module
+ will be called habanalabs_ib.
diff --git a/drivers/infiniband/hw/hbl/Makefile b/drivers/infiniband/hw/hbl/Makefile
new file mode 100644
index 000000000000..659d4bbfec0f
--- /dev/null
+++ b/drivers/infiniband/hw/hbl/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Makefile for HabanaLabs (an Intel Company) Infiniband driver
+#
+
+obj-$(CONFIG_INFINIBAND_HBL) := habanalabs_ib.o
+
+habanalabs_ib-y += hbl_main.o hbl_verbs.o
diff --git a/drivers/infiniband/hw/hbl/hbl.h b/drivers/infiniband/hw/hbl/hbl.h
new file mode 100644
index 000000000000..4fbe2368fd11
--- /dev/null
+++ b/drivers/infiniband/hw/hbl/hbl.h
@@ -0,0 +1,326 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2022-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#ifndef _HBL_H_
+#define _HBL_H_
+
+#include <linux/net/intel/cn.h>
+
+#include <uapi/rdma/hbl-abi.h>
+#include <uapi/rdma/hbl_user_ioctl_cmds.h>
+#include <uapi/rdma/hbl_user_ioctl_verbs.h>
+#include <rdma/ib_verbs.h>
+#include <linux/pci.h>
+#include <rdma/uverbs_ioctl.h>
+#include <linux/xarray.h>
+
+#define HBL_IB_MAX_PORT_GIDS 13
+
+/* For internal ports, only one GID is required and that is based on the MAC address. */
+#define HBL_IB_MAX_PORT_GIDS_INTERNAL 1
+
+/* define maximum supported send and receive SGEs */
+#define HBL_IB_MAX_SEND_SGE 2
+#define HBL_IB_MAX_RECV_SGE 2
+
+#define HBL_IB_EQ_PORT_FIELD_MASK 0xFFFF
+#define HBL_IB_EQ_PORT_FIELD_SIZE 16
+
+/**
+ * struct hbl_ib_user_mmap_entry - Mmap information.
+ * @rdma_entry: IB core rdma mmap entry.
+ * @info: Information for performing mmap.
+ */
+struct hbl_ib_user_mmap_entry {
+ struct rdma_user_mmap_entry rdma_entry;
+ struct hbl_ib_mem_info info;
+};
+
+/**
+ * struct hbl_ib_pd - Habanalabs IB PD.
+ * @ibpd: IB core PD.
+ * @pdn: PD ID.
+ */
+struct hbl_ib_pd {
+ struct ib_pd ibpd;
+ u32 pdn;
+};
+
+/**
+ * struct hbl_ib_ucontext - Habanalabs IB user context.
+ * @ibucontext: IB core user context.
+ * @qp_xarray: QP handle.
+ * @cn_ctx: CN context private data.
+ * @pd_allocated: is PD allocated.
+ * @ports_mask: Mask of ports associated with this context.
+ */
+struct hbl_ib_ucontext {
+ struct ib_ucontext ibucontext;
+ struct xarray qp_xarray;
+ void *cn_ctx;
+ atomic_t pd_allocated;
+ u64 ports_mask;
+};
+
+/**
+ * struct hbl_ib_cq - Habanalabs IB CQ.
+ * @ibcq: IB core CQ.
+ * @hctx: HBL IB context.
+ * @mem_handle_entry: Mmap entry for the mem handle.
+ * @pi_handle_entry: Mmap entry for the pi handle.
+ * @regs_handle_entry: Mmap entry for the regs handle.
+ * @port_cq: contains the hbl_ib_cq structure per port.
+ * @cq_type: Type of CQ resource
+ * @cq_num: CQ number that was allocated.
+ * @hbl_port_num: hbl port number that matches with the core code's port number.
+ * @is_native: If this is native create cq call or dv create cq call.
+ */
+struct hbl_ib_cq {
+ struct ib_cq ibcq;
+ struct hbl_ib_ucontext *hctx;
+ struct rdma_user_mmap_entry *mem_handle_entry;
+ struct rdma_user_mmap_entry *pi_handle_entry;
+ struct rdma_user_mmap_entry *regs_handle_entry;
+ struct hbl_ib_cq *port_cq;
+ enum hbl_ibv_cq_type cq_type;
+ u32 cq_num;
+ u8 hbl_port_num;
+ u8 is_native;
+};
+
+/**
+ * struct hbl_ib_qp - Habanalabs IB QP.
+ * @ibqp: IB core QP.
+ * @hctx: hbl IB context.
+ * @swq_mem_handle_entry: Mmap entry for the swq mem handle.
+ * @rwq_mem_handle_entry: Mmap entry for the rwq mem handle.
+ * @qp_state: Current QP state.
+ * @wq_type: WQ type.
+ * @qp_id: hbl core QP ID.
+ * @dest_qp_num: destination qp number.
+ * @max_send_wr: maximum send work requests supported.
+ * @max_recv_wr: maximum receive work requests supported.
+ * @mtu: QP mtu.
+ * @dst_ip_addr: destination IPv4 address.
+ * @dst_mac_addr: destination MAC address.
+ * @wq_granularity: send WQE granularity.
+ */
+struct hbl_ib_qp {
+ struct ib_qp ibqp;
+ struct hbl_ib_ucontext *hctx;
+ struct rdma_user_mmap_entry *swq_mem_handle_entry;
+ struct rdma_user_mmap_entry *rwq_mem_handle_entry;
+ enum ib_qp_state qp_state;
+ enum qpc_req_wq_type wq_type;
+ u32 qp_id;
+ u32 dest_qp_num;
+ u32 max_send_wr;
+ u32 max_recv_wr;
+ u32 mtu;
+ u32 dst_ip_addr;
+ u8 dst_mac_addr[ETH_ALEN];
+ u8 wq_granularity;
+};
+
+/**
+ * struct gid_entry - IB GID structure.
+ * @gid: IB global identifier.
+ * @gid_type: IB GID type.
+ */
+struct gid_entry {
+ union ib_gid gid;
+ enum ib_gid_type gid_type;
+};
+
+/**
+ * struct hbl_ib_port_init_params - Habanalabs IB port input parameters.
+ * @wq_arr_attr: Array of WQ-array attributes for each WQ-array type.
+ * @qp_wq_bp_offs: Offsets in NIC memory to signal a back pressure.
+ * @hbl_port_num: hbl port number that matches with the core code's port number.
+ * @advanced: WQ should support advanced operations such as RDV, QMan, WTD, etc.
+ * @adaptive_timeout_en: Enable adaptive_timeout feature on the port.
+ */
+struct hbl_ib_port_init_params {
+ struct hbl_wq_array_attr wq_arr_attr[HBL_IB_WQ_ARRAY_TYPE_MAX];
+ u32 qp_wq_bp_offs[HBL_IB_MAX_BP_OFFS];
+ u32 hbl_port_num;
+ u8 advanced;
+ u8 adaptive_timeout_en;
+};
+
+/**
+ * struct hbl_ib_port - Habanalabs IB port.
+ * @hdev: Habanalabs IB device.
+ * @hctx: hbl IB context.
+ * @gids: Array of GIDs (group IDs).
+ * @hbl_ibcq_tbl: CQ IDs table.
+ * @eq_comp: Completion object for event queue.
+ * @eq_thread: Event queue thread.
+ * @eq_lock: Event queue handling synchronization object.
+ * @port: Port ID.
+ * @mtu: Port MTU.
+ * @swqs_enabled: Array of send WQs from each type which indicate if WQ is enabled.
+ * @rwqs_enabled: Array of receive WQs from each type which indicate if WQ is enabled.
+ * @open: Port initialized.
+ */
+struct hbl_ib_port {
+ struct hbl_ib_device *hdev;
+ struct hbl_ib_ucontext *hctx;
+ struct gid_entry gids[HBL_IB_MAX_PORT_GIDS];
+ struct xarray hbl_ibcq_tbl;
+ struct completion eq_comp;
+ struct task_struct *eq_thread;
+ atomic_t eq_lock;
+ u32 port;
+ u32 mtu;
+ u8 swqs_enabled[HBL_IB_WQ_ARRAY_TYPE_MAX];
+ u8 rwqs_enabled[HBL_IB_WQ_ARRAY_TYPE_MAX];
+ u8 open;
+};
+
+/**
+ * struct hbl_ib_device_stats - IB device counters structure.
+ * @fatal_event: Fatal events counter.
+ */
+struct hbl_ib_device_stats {
+ atomic_t fatal_event;
+};
+
+/**
+ * struct hbl_ib_port_stats - IB port counters info.
+ * @stat_desc: Core rdma stats structure of the counters.
+ * @names: Names of the counters.
+ * @num: Number of counters.
+ */
+struct hbl_ib_port_stats {
+ struct rdma_stat_desc *stat_desc;
+ u8 **names;
+ u32 num;
+};
+
+/**
+ * struct hbl_ib_device - habanalabs IB device structure.
+ * @ibdev: IB device.
+ * @dev_stats: Device counters.
+ * @netdev_notifier: netdev events notifier.
+ * @port_stats: Array of port counters.
+ * @pdev: Pointer to PCI device.
+ * @dev: Related kernel basic device structure.
+ * @aux_dev: Pointer to auxiliary device.
+ * @ib_port: IB port structure.
+ * @hbl_to_ib_port_map: mapping array between hbl port to IB port.
+ * @dev_lock: Device lock for configuration serialization.
+ * @ctx_open: User context allocated.
+ * @ports_mask: Mask of available ports.
+ * @ext_ports_mask: Mask of external ports (subset of ports_mask).
+ * @pending_reset_long_timeout: Long timeout for pending hard reset to finish in seconds.
+ * @id: Core device ID.
+ * @max_num_of_ports: Maximum number of ports supported by ASIC.
+ * @mixed_qp_wq_types: Using mixed QP WQ types is supported.
+ * @umr_support: device supports UMR.
+ * @cc_support: device supports congestion control.
+ */
+struct hbl_ib_device {
+ struct ib_device ibdev;
+ struct hbl_ib_device_stats dev_stats;
+ struct notifier_block netdev_notifier;
+ struct hbl_ib_port_stats *port_stats;
+ struct pci_dev *pdev;
+ struct device *dev;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_port *ib_port;
+ u32 *hbl_to_ib_port_map;
+ atomic_t ctx_open;
+ u64 ports_mask;
+ u64 ext_ports_mask;
+ u32 pending_reset_long_timeout;
+ u16 id;
+ u8 max_num_of_ports;
+ u8 mixed_qp_wq_types;
+ u8 umr_support;
+ u8 cc_support;
+};
+
+extern const struct ib_device_ops hbl_ib_dev_ops;
+extern const struct uapi_definition hbl_usr_fifo_defs[];
+extern const struct uapi_definition hbl_set_port_ex_defs[];
+extern const struct uapi_definition hbl_query_port_defs[];
+extern const struct uapi_definition hbl_encap_defs[];
+
+static inline struct hbl_ib_device *to_hbl_ib_dev(struct ib_device *ibdev)
+{
+ return container_of(ibdev, struct hbl_ib_device, ibdev);
+}
+
+static inline struct hbl_ib_ucontext *to_hbl_ib_ucontext(struct ib_ucontext *ibucontext)
+{
+ return container_of(ibucontext, struct hbl_ib_ucontext, ibucontext);
+}
+
+static inline u32 hbl_to_ib_port_num(struct hbl_ib_device *hdev, u32 hbl_port_num)
+{
+ return hdev->hbl_to_ib_port_map[hbl_port_num];
+}
+
+static inline int ib_to_hbl_port_num(struct hbl_ib_device *hdev, u32 ib_port_num, u32 *hbl_port_num)
+{
+ u32 hbl_port;
+
+ if (!ib_port_num)
+ return -EINVAL;
+
+ for (hbl_port = 0; hbl_port < hdev->max_num_of_ports; hbl_port++)
+ if (hbl_to_ib_port_num(hdev, hbl_port) == ib_port_num) {
+ *hbl_port_num = hbl_port;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static inline struct hbl_ib_user_mmap_entry *
+to_hbl_ib_user_mmap_entry(struct rdma_user_mmap_entry *rdma_entry)
+{
+ return container_of(rdma_entry, struct hbl_ib_user_mmap_entry, rdma_entry);
+}
+
+struct rdma_user_mmap_entry *
+hbl_ib_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address, size_t length,
+ u64 *offset);
+
+#define hbl_ibdev_emerg(ibdev, format, ...) ibdev_emerg(ibdev, format, ##__VA_ARGS__)
+#define hbl_ibdev_alert(ibdev, format, ...) ibdev_alert(ibdev, format, ##__VA_ARGS__)
+#define hbl_ibdev_crit(ibdev, format, ...) ibdev_crit(ibdev, format, ##__VA_ARGS__)
+#define hbl_ibdev_err(ibdev, format, ...) ibdev_err(ibdev, format, ##__VA_ARGS__)
+#define hbl_ibdev_warn(ibdev, format, ...) ibdev_warn(ibdev, format, ##__VA_ARGS__)
+#define hbl_ibdev_notice(ibdev, format, ...) ibdev_notice(ibdev, format, ##__VA_ARGS__)
+#define hbl_ibdev_info(ibdev, format, ...) ibdev_info(ibdev, format, ##__VA_ARGS__)
+#define hbl_ibdev_dbg(ibdev, format, ...) ibdev_dbg(ibdev, format, ##__VA_ARGS__)
+
+#define hbl_ibdev_emerg_ratelimited(ibdev, fmt, ...) \
+ ibdev_emerg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
+#define hbl_ibdev_alert_ratelimited(ibdev, fmt, ...) \
+ ibdev_alert_ratelimited(ibdev, fmt, ##__VA_ARGS__)
+#define hbl_ibdev_crit_ratelimited(ibdev, fmt, ...) \
+ ibdev_crit_ratelimited(ibdev, fmt, ##__VA_ARGS__)
+#define hbl_ibdev_err_ratelimited(ibdev, fmt, ...) \
+ ibdev_err_ratelimited(ibdev, fmt, ##__VA_ARGS__)
+#define hbl_ibdev_warn_ratelimited(ibdev, fmt, ...) \
+ ibdev_warn_ratelimited(ibdev, fmt, ##__VA_ARGS__)
+#define hbl_ibdev_notice_ratelimited(ibdev, fmt, ...) \
+ ibdev_notice_ratelimited(ibdev, fmt, ##__VA_ARGS__)
+#define hbl_ibdev_info_ratelimited(ibdev, fmt, ...) \
+ ibdev_info_ratelimited(ibdev, fmt, ##__VA_ARGS__)
+#define hbl_ibdev_dbg_ratelimited(ibdev, fmt, ...) \
+ ibdev_dbg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
+
+int hbl_ib_port_init(struct hbl_ib_ucontext *hctx, struct hbl_ib_port_init_params *init_params);
+void hbl_ib_eqe_handler(struct hbl_ib_port *ib_port);
+void hbl_ib_eqe_null_work(struct hbl_aux_dev *aux_dev, u32 port);
+void hbl_ib_eqe_work_schd(struct hbl_aux_dev *aux_dev, u32 port);
+
+#endif /* _HBL_H_ */
diff --git a/drivers/infiniband/hw/hbl/hbl_main.c b/drivers/infiniband/hw/hbl/hbl_main.c
new file mode 100644
index 000000000000..98d3ed46bfe2
--- /dev/null
+++ b/drivers/infiniband/hw/hbl/hbl_main.c
@@ -0,0 +1,478 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#define pr_fmt(fmt) "habanalabs_ib: " fmt
+
+#include "hbl.h"
+
+#include <linux/module.h>
+#include <linux/auxiliary_bus.h>
+
+#define HBL_DRIVER_AUTHOR "HabanaLabs Kernel Driver Team"
+
+#define HBL_DRIVER_DESC "HabanaLabs AI accelerators InfiniBand driver"
+
+MODULE_AUTHOR(HBL_DRIVER_AUTHOR);
+MODULE_DESCRIPTION(HBL_DRIVER_DESC);
+MODULE_LICENSE("GPL");
+
+#define MTU_DEFAULT SZ_4K
+
+static void hbl_ib_port_event(struct ib_device *ibdev, u32 port_num, enum ib_event_type reason)
+{
+ struct ib_event event;
+
+ event.device = ibdev;
+ event.element.port_num = port_num;
+ event.event = reason;
+
+ ib_dispatch_event(&event);
+}
+
+static void hbl_ib_port_mtu_update(struct ib_device *ibdev, u32 hbl_port, u32 mtu)
+{
+ struct hbl_ib_device *hdev = to_hbl_ib_dev(ibdev);
+
+ hdev->ib_port[hbl_port].mtu = mtu;
+}
+
+static bool hbl_ib_match_netdev(struct ib_device *ibdev, struct net_device *netdev)
+{
+ struct hbl_ib_device *hdev = to_hbl_ib_dev(ibdev);
+ struct hbl_ib_aux_data *aux_data;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = hdev->aux_dev;
+ aux_data = aux_dev->aux_data;
+
+ /* IB and EN share the same PCI device, hence we can find the correct netdev to bind to
+ * ibdev through the pointer to this device and port index.
+ */
+ if (&hdev->pdev->dev == netdev->dev.parent)
+ return true;
+
+ return false;
+}
+
+static int hbl_ib_netdev_event(struct notifier_block *notifier, unsigned long event, void *ptr)
+{
+ struct hbl_ib_device *hdev = container_of(notifier, struct hbl_ib_device, netdev_notifier);
+ struct net_device *netdev = netdev_notifier_info_to_dev(ptr);
+ struct ib_device *ibdev = &hdev->ibdev;
+ u32 ib_port;
+
+ if (hbl_ib_match_netdev(ibdev, netdev))
+ ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
+ else
+ return NOTIFY_DONE;
+
+ switch (event) {
+ case NETDEV_UP:
+ hbl_ib_port_event(ibdev, ib_port, IB_EVENT_PORT_ACTIVE);
+ break;
+ case NETDEV_DOWN:
+ hbl_ib_port_event(ibdev, ib_port, IB_EVENT_PORT_ERR);
+ break;
+ case NETDEV_REGISTER:
+ ib_device_set_netdev(ibdev, netdev, ib_port);
+ hbl_ib_port_mtu_update(ibdev, netdev->dev_port, netdev->mtu);
+ break;
+ case NETDEV_UNREGISTER:
+ hbl_ib_port_mtu_update(ibdev, netdev->dev_port, MTU_DEFAULT);
+ ib_device_set_netdev(ibdev, NULL, ib_port);
+ break;
+ case NETDEV_CHANGEMTU:
+ hbl_ib_port_mtu_update(ibdev, netdev->dev_port, netdev->mtu);
+ break;
+ default:
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
+static void hbl_ib_dispatch_fatal_event(struct hbl_aux_dev *aux_dev, u32 asid)
+{
+ struct hbl_ib_device *hdev = aux_dev->priv;
+ struct ib_event ibev = {};
+
+ atomic_inc(&hdev->dev_stats.fatal_event);
+
+ hbl_ibdev_err(&hdev->ibdev, "raising fatal event for context with ASID %d\n", asid);
+
+ ibev.device = &hdev->ibdev;
+ ibev.event = IB_EVENT_DEVICE_FATAL;
+ ibev.element.port_num = HBL_IB_EQ_PORT_FIELD_MASK | (asid << HBL_IB_EQ_PORT_FIELD_SIZE);
+ ib_dispatch_event(&ibev);
+}
+
+static void hbl_ib_set_aux_ops(struct hbl_ib_device *hdev, bool enable)
+{
+ struct hbl_aux_dev *aux_dev = hdev->aux_dev;
+ struct hbl_ib_aux_ops *aux_ops;
+
+ aux_ops = aux_dev->aux_ops;
+
+ /* map cn2ib functions */
+ if (enable)
+ aux_ops->eqe_work_schd = hbl_ib_eqe_null_work;
+ else
+ aux_ops->eqe_work_schd = NULL;
+
+ aux_ops->dispatch_fatal_event = hbl_ib_dispatch_fatal_event;
+}
+
+static int hbl_ib_dev_init(struct hbl_ib_device *hdev)
+{
+ char name[IB_DEVICE_NAME_MAX] = {0};
+ struct ib_device *ibdev;
+ u32 max_num_of_ports;
+ int rc, i, port_cnt;
+
+ ibdev = &hdev->ibdev;
+
+ ibdev->node_type = RDMA_NODE_UNSPECIFIED;
+ ibdev->dev.parent = &hdev->pdev->dev;
+
+ max_num_of_ports = hdev->max_num_of_ports;
+
+ /* Allocation of the mapping array between hbl<->ib ports.
+ * We don't need to initialize this array with some special value as 0 is an invalid value
+ * for IB port.
+ */
+ hdev->hbl_to_ib_port_map = kcalloc(max_num_of_ports, sizeof(u32), GFP_KERNEL);
+ if (!hdev->hbl_to_ib_port_map)
+ return -ENOMEM;
+
+ port_cnt = 0;
+ for (i = 0; i < max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ port_cnt++;
+ hdev->hbl_to_ib_port_map[i] = port_cnt;
+ }
+
+ ibdev->phys_port_cnt = port_cnt;
+
+ /* The number of Completion vectors (i.e. MSI-X vectors) available for this RDMA device.
+ * For now have it as '1'
+ */
+ ibdev->num_comp_vectors = 1;
+
+ ib_set_device_ops(ibdev, &hbl_ib_dev_ops);
+
+ /* The CN driver might start calling the aux functions after registering the device so set
+ * the callbacks here.
+ */
+ hbl_ib_set_aux_ops(hdev, true);
+
+ snprintf(name, sizeof(name), "hbl_%d", hdev->id);
+
+ rc = ib_register_device(ibdev, name, &hdev->pdev->dev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to register IB device, err %d\n", rc);
+ goto ibdev_register_fail;
+ }
+
+ hdev->netdev_notifier.notifier_call = hbl_ib_netdev_event;
+
+ rc = register_netdevice_notifier(&hdev->netdev_notifier);
+ if (rc) {
+ hbl_ibdev_err(ibdev, "Failed to register netdev notifier, err %d\n", rc);
+ goto notifier_register_fail;
+ }
+
+ hbl_ibdev_info(ibdev, "IB device registered\n");
+
+ return 0;
+
+notifier_register_fail:
+ ib_unregister_device(ibdev);
+ibdev_register_fail:
+ hbl_ib_set_aux_ops(hdev, false);
+ kfree(hdev->hbl_to_ib_port_map);
+ return rc;
+}
+
+static void hbl_ib_dev_fini(struct hbl_ib_device *hdev)
+{
+ struct ib_device *ibdev = &hdev->ibdev;
+
+ hbl_ibdev_info(ibdev, "Unregister IB device\n");
+ unregister_netdevice_notifier(&hdev->netdev_notifier);
+ ib_unregister_device(ibdev);
+ hbl_ib_set_aux_ops(hdev, false);
+ kfree(hdev->hbl_to_ib_port_map);
+}
+
+/* Initialize an array of strings to hold the counters names.
+ * We get the names as one long spaced string and then we convert it to an array of strings like the
+ * IB counters API expects.
+ */
+static int hbl_ib_cnts_init(struct hbl_ib_device *hdev, int port)
+{
+ struct hbl_ib_port_cnts_data *cnts_data;
+ struct hbl_ib_port_stats *port_stats;
+ struct rdma_stat_desc *stat_desc;
+ struct hbl_ib_aux_data *aux_data;
+ u8 *ptr, *data, **data2;
+ int cnt_num, i;
+
+ aux_data = hdev->aux_dev->aux_data;
+ port_stats = &hdev->port_stats[port];
+ cnts_data = &aux_data->cnts_data[port];
+ cnt_num = cnts_data->num;
+
+ /* array for strings and pointers for them */
+ data = kcalloc(cnt_num, (sizeof(u8 *) + HBL_IB_CNT_NAME_LEN), GFP_KERNEL);
+ if (!data)
+ goto exit_err;
+
+ stat_desc = kcalloc(cnt_num, sizeof(*stat_desc), GFP_KERNEL);
+ if (!stat_desc)
+ goto free_data;
+
+ /* copy the strings after the pointers to them */
+ ptr = data + cnt_num * sizeof(u8 *);
+ memcpy(ptr, cnts_data->names, cnt_num * HBL_IB_CNT_NAME_LEN);
+
+ data2 = (u8 **)data;
+
+ /* set the pointers to the strings */
+ for (i = 0; i < cnt_num; i++)
+ data2[i] = ptr + i * HBL_IB_CNT_NAME_LEN;
+
+ port_stats->num = cnt_num;
+ port_stats->names = data2;
+
+ for (i = 0; i < cnt_num; i++)
+ stat_desc[i].name = data2[i];
+
+ port_stats->stat_desc = stat_desc;
+
+ return 0;
+
+free_data:
+ kfree(data);
+exit_err:
+ return -ENOMEM;
+}
+
+static void hbl_ib_cnts_fini(struct hbl_ib_device *hdev, int port)
+{
+ kfree(hdev->port_stats[port].stat_desc);
+ kfree(hdev->port_stats[port].names);
+}
+
+static int hdev_init(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_ib_aux_data *aux_data = aux_dev->aux_data;
+ struct hbl_ib_device *hdev;
+ int rc, i;
+
+ hdev = ib_alloc_device(hbl_ib_device, ibdev);
+ if (!hdev)
+ return -ENOMEM;
+
+ aux_dev->priv = hdev;
+ hdev->aux_dev = aux_dev;
+ hdev->pdev = aux_data->pdev;
+ hdev->dev = aux_data->dev;
+ hdev->ports_mask = aux_data->ports_mask;
+ hdev->ext_ports_mask = aux_data->ext_ports_mask;
+ hdev->pending_reset_long_timeout = aux_data->pending_reset_long_timeout;
+ hdev->id = aux_data->id;
+ hdev->max_num_of_ports = aux_data->max_num_of_ports;
+ hdev->mixed_qp_wq_types = aux_data->mixed_qp_wq_types;
+ hdev->umr_support = aux_data->umr_support;
+ hdev->cc_support = aux_data->cc_support;
+
+ /* Allocate port structs */
+ hdev->ib_port = kcalloc(hdev->max_num_of_ports, sizeof(*hdev->ib_port), GFP_KERNEL);
+ if (!hdev->ib_port) {
+ rc = -ENOMEM;
+ goto free_device;
+ }
+
+ /* Set default MTU value that can be overridden later by netdev */
+ for (i = 0; i < hdev->max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ hdev->ib_port[i].mtu = MTU_DEFAULT;
+ }
+
+ hdev->port_stats = kcalloc(hdev->max_num_of_ports, sizeof(*hdev->port_stats), GFP_KERNEL);
+ if (!hdev->port_stats) {
+ rc = -ENOMEM;
+ goto free_ports;
+ }
+
+ for (i = 0; i < hdev->max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ rc = hbl_ib_cnts_init(hdev, i);
+ if (rc)
+ goto free_cnts;
+ }
+
+ return 0;
+
+free_cnts:
+ for (--i; i >= 0; i--) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ hbl_ib_cnts_fini(hdev, i);
+ }
+ kfree(hdev->port_stats);
+free_ports:
+ kfree(hdev->ib_port);
+free_device:
+ aux_dev->priv = NULL;
+ ib_dealloc_device(&hdev->ibdev);
+
+ return rc;
+}
+
+static void hdev_fini(struct hbl_aux_dev *aux_dev)
+{
+ struct hbl_ib_device *hdev = aux_dev->priv;
+ int i;
+
+ for (i = 0; i < hdev->max_num_of_ports; i++) {
+ if (!(hdev->ports_mask & BIT(i)))
+ continue;
+
+ hbl_ib_cnts_fini(hdev, i);
+ }
+ kfree(hdev->port_stats);
+
+ kfree(hdev->ib_port);
+
+ aux_dev->priv = NULL;
+ ib_dealloc_device(&hdev->ibdev);
+}
+
+static const struct auxiliary_device_id hbl_ib_id_table[] = {
+ { .name = "habanalabs_cn.ib", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(auxiliary, hbl_ib_id_table);
+
+static int hbl_ib_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
+{
+ struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
+ struct hbl_ib_aux_ops *aux_ops = aux_dev->aux_ops;
+ struct hbl_ib_device *hdev;
+ ktime_t timeout;
+ int rc;
+
+ rc = hdev_init(aux_dev);
+ if (rc) {
+ dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
+ return -EIO;
+ }
+
+ hdev = aux_dev->priv;
+
+ /* don't allow module unloading while it is attached */
+ if (!try_module_get(THIS_MODULE)) {
+ dev_err(hdev->dev, "Failed to increment %s module refcount\n",
+ module_name(THIS_MODULE));
+ rc = -EIO;
+ goto module_get_err;
+ }
+
+ timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
+ while (1) {
+ aux_ops->hw_access_lock(aux_dev);
+
+ /* if the device is operational, proceed to actual init while holding the lock in
+ * order to prevent concurrent hard reset
+ */
+ if (aux_ops->device_operational(aux_dev))
+ break;
+
+ aux_ops->hw_access_unlock(aux_dev);
+
+ if (ktime_compare(ktime_get(), timeout) > 0) {
+ dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
+ rc = -EBUSY;
+ goto timeout_err;
+ }
+
+ dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing IB\n");
+
+ msleep_interruptible(MSEC_PER_SEC);
+ }
+
+ rc = hbl_ib_dev_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init ib device\n");
+ goto dev_init_err;
+ }
+
+ aux_ops->hw_access_unlock(aux_dev);
+
+ return 0;
+
+dev_init_err:
+ aux_ops->hw_access_unlock(aux_dev);
+timeout_err:
+ module_put(THIS_MODULE);
+module_get_err:
+ hdev_fini(aux_dev);
+
+ return rc;
+}
+
+/* This function can be called only from the CN driver when deleting the aux bus, because we
+ * incremented the module refcount on probing. Hence no need to protect here from hard reset.
+ */
+static void hbl_ib_remove(struct auxiliary_device *adev)
+{
+ struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
+ struct hbl_ib_device *hdev = aux_dev->priv;
+
+ if (!hdev)
+ return;
+
+ hbl_ib_dev_fini(hdev);
+
+ /* allow module unloading as now it is detached */
+ module_put(THIS_MODULE);
+
+ hdev_fini(aux_dev);
+}
+
+static struct auxiliary_driver hbl_ib_driver = {
+ .name = "ib",
+ .probe = hbl_ib_probe,
+ .remove = hbl_ib_remove,
+ .id_table = hbl_ib_id_table,
+};
+
+static int __init hbl_ib_init(void)
+{
+ pr_info("loading driver\n");
+
+ return auxiliary_driver_register(&hbl_ib_driver);
+}
+
+static void __exit hbl_ib_exit(void)
+{
+ auxiliary_driver_unregister(&hbl_ib_driver);
+
+ pr_info("driver removed\n");
+}
+
+module_init(hbl_ib_init);
+module_exit(hbl_ib_exit)
diff --git a/drivers/infiniband/hw/hbl/hbl_verbs.c b/drivers/infiniband/hw/hbl/hbl_verbs.c
new file mode 100644
index 000000000000..624bcd7290f0
--- /dev/null
+++ b/drivers/infiniband/hw/hbl/hbl_verbs.c
@@ -0,0 +1,2686 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include <rdma/ib_addr.h>
+#include <rdma/uverbs_ioctl.h>
+#include <linux/net/intel/cni.h>
+#include <linux/bitfield.h>
+#include <linux/ctype.h>
+#include <linux/vmalloc.h>
+
+#include "hbl.h"
+#include <uapi/rdma/hbl_user_ioctl_cmds.h>
+#include <uapi/rdma/hbl_user_ioctl_verbs.h>
+
+#define HBL_IB_MAX_QP BIT(10)
+#define HBL_IB_MAX_CQE BIT(13)
+#define HBL_IB_MAX_MSG_SIZE SZ_1G
+#define HBL_IB_DEFAULT_MAX_NUM_OF_QPS 128
+#define HBL_IB_DEFAULT_MAX_NUM_WQES_IN_WQ 256
+#define HBL_IB_DEFAULT_WQ_MEM_ID HBL_CNI_MEM_HOST
+#define HBL_IB_DUMP_QP_SZ SZ_1K
+
+static int verify_qp_xarray(struct hbl_ib_qp *hblqp);
+static void qp_user_mmap_entries_remove(struct hbl_ib_qp *qp);
+
+enum hbl_ib_device_stats_type {
+ FATAL_EVENT,
+};
+
+static const struct rdma_stat_desc hbl_ib_device_stats[] = {
+ { .name = "fatal_event",},
+};
+
+static inline struct hbl_ib_pd *to_hbl_ib_pd(struct ib_pd *ibpd)
+{
+ return container_of(ibpd, struct hbl_ib_pd, ibpd);
+}
+
+static inline struct hbl_ib_qp *to_hbl_ib_qp(struct ib_qp *ibqp)
+{
+ return container_of(ibqp, struct hbl_ib_qp, ibqp);
+}
+
+static inline struct hbl_ib_cq *to_hbl_ib_cq(struct ib_cq *ibcq)
+{
+ return container_of(ibcq, struct hbl_ib_cq, ibcq);
+}
+
+static inline u64 to_hbl_port_mask(struct hbl_ib_device *hdev, u64 ib_port_mask)
+{
+ u32 hbl_port_num, ib_port_num;
+ u64 hbl_port_mask = 0x0;
+
+ for (hbl_port_num = 0; hbl_port_num < hdev->max_num_of_ports; hbl_port_num++) {
+ ib_port_num = hbl_to_ib_port_num(hdev, hbl_port_num);
+ if (!ib_port_num)
+ continue;
+
+ if (ib_port_mask & BIT_ULL(ib_port_num))
+ hbl_port_mask |= BIT_ULL(hbl_port_num);
+ }
+
+ return hbl_port_mask;
+}
+
+static inline u64 to_ib_port_mask(struct hbl_ib_device *hdev, u64 hbl_port_mask)
+{
+ u32 hbl_port_num, ib_port_num;
+ u64 ib_port_mask = 0x0;
+
+ for (hbl_port_num = 0; hbl_port_num < hdev->max_num_of_ports; hbl_port_num++) {
+ if (!(hbl_port_mask & BIT(hbl_port_num)))
+ continue;
+
+ ib_port_num = hbl_to_ib_port_num(hdev, hbl_port_num);
+
+ /* The IB ports are 1 based, hence getting zero value means that we have bug in the
+ * hbl<->ib port mapping.
+ */
+ WARN_ON(!ib_port_num);
+
+ ib_port_mask |= BIT_ULL(ib_port_num);
+ }
+
+ return ib_port_mask;
+}
+
+struct rdma_user_mmap_entry *
+hbl_ib_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 handle, size_t length, u64 *offset)
+{
+ struct hbl_ib_user_mmap_entry *entry;
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ int rc;
+
+ ibdev = ucontext->device;
+ hdev = to_hbl_ib_dev(ibdev);
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ entry = kzalloc(sizeof(*entry), GFP_KERNEL);
+ if (!entry)
+ return ERR_PTR(-ENOMEM);
+
+ rc = aux_ops->query_mem_handle(aux_dev, handle, &entry->info);
+ if (rc)
+ goto err_free_entry;
+
+ rc = rdma_user_mmap_entry_insert_range(ucontext, &entry->rdma_entry, length, 1, U32_MAX);
+ if (rc)
+ goto err_free_entry;
+
+ *offset = rdma_user_mmap_get_offset(&entry->rdma_entry);
+
+ return &entry->rdma_entry;
+
+err_free_entry:
+ kfree(entry);
+ return ERR_PTR(rc);
+}
+
+static int to_hbl_wq_arr_types(struct ib_device *ibdev, enum hbl_ib_wq_array_type ib_wq_arr_type,
+ enum hbl_nic_mem_type *swq_type, enum hbl_nic_mem_type *rwq_type)
+{
+ switch (ib_wq_arr_type) {
+ case HBL_IB_WQ_ARRAY_TYPE_GENERIC:
+ *swq_type = HBL_CNI_USER_WQ_SEND;
+ *rwq_type = HBL_CNI_USER_WQ_RECV;
+ break;
+ default:
+ hbl_ibdev_err(ibdev, "Invalid WQ array type %d\n", ib_wq_arr_type);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int hbl_ib_wqs_init(struct hbl_ib_port *ib_port, struct hbl_ib_ucontext *hctx,
+ struct hbl_ib_port_init_params *init_params,
+ enum hbl_ib_wq_array_type ib_wq_arr_type)
+{
+ struct hbl_cni_user_wq_arr_unset_in wq_arr_unset_in = {};
+ struct hbl_cni_user_wq_arr_set_out wq_arr_set_out = {};
+ struct hbl_cni_user_wq_arr_set_in wq_arr_set_in = {};
+ enum hbl_nic_mem_type swq_type, rwq_type;
+ struct hbl_wq_array_attr *wq_arr_attr;
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ u32 port;
+ int rc;
+
+ hdev = ib_port->hdev;
+ port = ib_port->port;
+ ibdev = &hdev->ibdev;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ rc = to_hbl_wq_arr_types(ibdev, ib_wq_arr_type, &swq_type, &rwq_type);
+ if (rc)
+ return rc;
+
+ wq_arr_attr = &init_params->wq_arr_attr[ib_wq_arr_type];
+
+ if (!wq_arr_attr->max_num_of_wqs || !wq_arr_attr->max_num_of_wqes_in_wq)
+ return 0;
+
+ wq_arr_set_in.port = port;
+ wq_arr_set_in.num_of_wqs = wq_arr_attr->max_num_of_wqs;
+ wq_arr_set_in.num_of_wq_entries = wq_arr_attr->max_num_of_wqes_in_wq;
+ wq_arr_set_in.mem_id = wq_arr_attr->mem_id;
+ wq_arr_set_in.swq_granularity = wq_arr_attr->swq_granularity;
+
+ wq_arr_set_in.type = swq_type;
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_WQ_SET, &wq_arr_set_in,
+ &wq_arr_set_out);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to set send WQ, port %d\n", port);
+ return rc;
+ }
+
+ ib_port->swqs_enabled[ib_wq_arr_type] = true;
+
+ wq_arr_set_in.type = rwq_type;
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_WQ_SET, &wq_arr_set_in,
+ &wq_arr_set_out);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to set recv WQ, port %d\n", port);
+ goto clear_send_wq;
+ }
+
+ ib_port->rwqs_enabled[ib_wq_arr_type] = true;
+
+ return 0;
+
+clear_send_wq:
+ wq_arr_unset_in.port = port;
+ wq_arr_unset_in.type = swq_type;
+ aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_WQ_UNSET, &wq_arr_unset_in, NULL);
+ ib_port->swqs_enabled[ib_wq_arr_type] = false;
+
+ return rc;
+}
+
+static void hbl_ib_wqs_fini(struct hbl_ib_port *ib_port, struct hbl_ib_ucontext *hctx,
+ enum hbl_ib_wq_array_type ib_wq_arr_type)
+{
+ struct hbl_cni_user_wq_arr_unset_in wq_arr_unset_in = {};
+ enum hbl_nic_mem_type swq_type, rwq_type;
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ u32 port;
+ int rc;
+
+ hdev = ib_port->hdev;
+ port = ib_port->port;
+ ibdev = &hdev->ibdev;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ rc = to_hbl_wq_arr_types(ibdev, ib_wq_arr_type, &swq_type, &rwq_type);
+ if (rc)
+ return;
+
+ wq_arr_unset_in.port = port;
+
+ if (ib_port->rwqs_enabled[ib_wq_arr_type]) {
+ wq_arr_unset_in.type = rwq_type;
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_WQ_UNSET,
+ &wq_arr_unset_in, NULL);
+ if (rc)
+ hbl_ibdev_dbg(ibdev, "failed to unset recv WQ, port %d\n", port);
+
+ ib_port->rwqs_enabled[ib_wq_arr_type] = false;
+ }
+
+ if (ib_port->swqs_enabled[ib_wq_arr_type]) {
+ wq_arr_unset_in.type = swq_type;
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_WQ_UNSET,
+ &wq_arr_unset_in, NULL);
+ if (rc)
+ hbl_ibdev_dbg(ibdev, "failed to unset send WQ, port %d\n", port);
+
+ ib_port->swqs_enabled[ib_wq_arr_type] = false;
+ }
+}
+
+static void hbl_ib_port_clear(struct hbl_ib_ucontext *hctx, int port)
+{
+ struct hbl_ib_device *hdev = to_hbl_ib_dev(hctx->ibucontext.device);
+ struct hbl_ib_port *ib_port = &hdev->ib_port[port];
+
+ /* Clean IB port struct from previous CTX allocations */
+ memset(ib_port, 0, sizeof(*ib_port));
+}
+
+static int hbl_ib_eq_func(void *param)
+{
+ unsigned long timeout = msecs_to_jiffies(60 * MSEC_PER_SEC);
+ struct hbl_ib_port *ib_port = param;
+ int rc;
+
+ while (!kthread_should_stop()) {
+ /* Use timeout to avoid warnings for sleeping too long */
+ rc = wait_for_completion_interruptible_timeout(&ib_port->eq_comp, timeout);
+
+ /* No need to iterate on the devices when timed out or signaled, but only when
+ * completed.
+ */
+ if (rc > 0)
+ hbl_ib_eqe_handler(ib_port);
+ }
+
+ return 0;
+}
+
+static int hbl_ib_eq_init(struct hbl_ib_port *ib_port)
+{
+ struct ib_device *ibdev = &ib_port->hdev->ibdev;
+ char eq_th_name[32] = {0};
+ u32 port = ib_port->port;
+ int rc;
+
+ init_completion(&ib_port->eq_comp);
+ atomic_set(&ib_port->eq_lock, 0);
+
+ snprintf(eq_th_name, sizeof(eq_th_name) - 1, "hbl_eq%d", port);
+ ib_port->eq_thread = kthread_run(hbl_ib_eq_func, ib_port, eq_th_name);
+ if (IS_ERR(ib_port->eq_thread)) {
+ rc = PTR_ERR(ib_port->eq_thread);
+ hbl_ibdev_dbg(ibdev, "failed to create an EQ thread, port %d, err %d\n", port, rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static void hbl_ib_eqe_fini(struct hbl_ib_port *ib_port)
+{
+ while (atomic_cmpxchg(&ib_port->eq_lock, 0, 1))
+ usleep_range(50, 200);
+
+ complete_all(&ib_port->eq_comp);
+ kthread_stop(ib_port->eq_thread);
+}
+
+int hbl_ib_port_init(struct hbl_ib_ucontext *hctx, struct hbl_ib_port_init_params *init_params)
+{
+ struct hbl_cni_set_user_app_params_in set_app_params_in = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_port *ib_port;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ u32 port;
+ int rc;
+
+ hdev = to_hbl_ib_dev(hctx->ibucontext.device);
+ ibdev = &hdev->ibdev;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ port = init_params->hbl_port_num;
+
+ ib_port = &hdev->ib_port[port];
+
+ ib_port->hdev = hdev;
+ ib_port->port = port;
+
+ ib_port->hctx = hctx;
+
+ set_app_params_in.port = port;
+ set_app_params_in.advanced = init_params->advanced;
+ set_app_params_in.adaptive_timeout_en = init_params->adaptive_timeout_en;
+ memcpy(set_app_params_in.bp_offs, init_params->qp_wq_bp_offs,
+ sizeof(set_app_params_in.bp_offs));
+
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_SET_USER_APP_PARAMS,
+ &set_app_params_in, NULL);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to set app params, port %d\n", port);
+ return rc;
+ }
+
+ /* Create pointer table to hold pointer to allocated ib_cq structs.
+ * We need them to post dispatch IB events.
+ */
+ xa_init(&ib_port->hbl_ibcq_tbl);
+
+ rc = hbl_ib_wqs_init(ib_port, hctx, init_params, HBL_IB_WQ_ARRAY_TYPE_GENERIC);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to init WQs, port %d\n", port);
+ goto destroy_xa;
+ }
+
+ rc = hbl_ib_eq_init(ib_port);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to init EQ completion object, port %d\n", port);
+ goto clean_wqs;
+ }
+
+ ib_port->open = true;
+
+ return 0;
+
+clean_wqs:
+ hbl_ib_wqs_fini(ib_port, hctx, HBL_IB_WQ_ARRAY_TYPE_GENERIC);
+destroy_xa:
+ xa_destroy(&ib_port->hbl_ibcq_tbl);
+ return rc;
+}
+
+static void hbl_ib_port_fini(struct hbl_ib_ucontext *hctx, u32 port)
+{
+ struct hbl_ib_port *ib_port;
+ struct hbl_ib_device *hdev;
+
+ hdev = to_hbl_ib_dev(hctx->ibucontext.device);
+ ib_port = &hdev->ib_port[port];
+
+ if (!ib_port->open)
+ return;
+
+ hbl_ib_eqe_fini(ib_port);
+
+ hbl_ib_wqs_fini(ib_port, hctx, HBL_IB_WQ_ARRAY_TYPE_GENERIC);
+
+ xa_destroy(&ib_port->hbl_ibcq_tbl);
+}
+
+static int hbl_ib_alloc_ucontext(struct ib_ucontext *ibucontext, struct ib_udata *udata)
+{
+ struct hbl_ib_device *hdev = to_hbl_ib_dev(ibucontext->device);
+ struct hbl_ib_ucontext *hctx = to_hbl_ib_ucontext(ibucontext);
+ struct hbl_ib_port_init_params port_init_params = {};
+ struct hbl_ibv_alloc_ucontext_resp resp = {};
+ struct ib_device *ibdev = ibucontext->device;
+ struct hbl_aux_dev *aux_dev = hdev->aux_dev;
+ struct hbl_ibv_alloc_ucontext_req req = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ u64 user_ports_mask;
+ int rc, i;
+
+ aux_ops = aux_dev->aux_ops;
+
+ rc = ib_copy_from_udata(&req, udata, min(sizeof(req), udata->inlen));
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to copy in udata for alloc_ucontext\n");
+ return rc;
+ }
+
+ user_ports_mask = req.ports_mask;
+
+ /* If the user didn't provide mask, we should use the core mask, which is 0-based.
+ * Otherwise, the user provides 1-based mask, so we need to convert it to core mask.
+ */
+ if (!user_ports_mask)
+ user_ports_mask = hdev->ports_mask;
+ else
+ user_ports_mask = to_hbl_port_mask(hdev, user_ports_mask);
+
+ if (user_ports_mask & ~hdev->ports_mask) {
+ hbl_ibdev_dbg(ibdev, "user ports mask (0x%llx) contains a disabled port\n",
+ user_ports_mask);
+ return -EINVAL;
+ }
+
+ if (atomic_cmpxchg(&hdev->ctx_open, 0, 1)) {
+ hbl_ibdev_dbg(ibdev, "ucontext is already allocated\n");
+ return -EBUSY;
+ }
+
+ rc = aux_ops->alloc_ucontext(aux_dev, req.core_fd, &hctx->cn_ctx);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "alloc context failed\n");
+ goto exit;
+ }
+
+ /* Clear all the Ports */
+ for (i = 0; i < hdev->max_num_of_ports; i++)
+ hbl_ib_port_clear(hctx, i);
+
+ xa_init_flags(&hctx->qp_xarray, XA_FLAGS_ALLOC);
+
+ /* If alloc context called from non-DV flow, need to initialize the ports here */
+ if (!req.use_dvs) {
+ struct hbl_wq_array_attr *gen_wq_arr_attr =
+ &port_init_params.wq_arr_attr[HBL_IB_WQ_ARRAY_TYPE_GENERIC];
+
+ gen_wq_arr_attr->max_num_of_wqs = HBL_IB_DEFAULT_MAX_NUM_OF_QPS;
+ gen_wq_arr_attr->max_num_of_wqes_in_wq = HBL_IB_DEFAULT_MAX_NUM_WQES_IN_WQ;
+ gen_wq_arr_attr->mem_id = HBL_IB_DEFAULT_WQ_MEM_ID;
+
+ for (i = 0; i < hdev->max_num_of_ports; i++) {
+ if (!(user_ports_mask & BIT(i)))
+ continue;
+
+ port_init_params.hbl_port_num = i;
+ rc = hbl_ib_port_init(hctx, &port_init_params);
+ if (rc)
+ goto uninit_ports;
+ }
+ }
+
+ hctx->ports_mask = user_ports_mask;
+
+ /* Here we should return ib mask, which is 1-based */
+ resp.ports_mask = to_ib_port_mask(hdev, user_ports_mask);
+
+ if (hdev->umr_support)
+ resp.cap_mask |= HBL_UCONTEXT_CAP_MMAP_UMR;
+ if (hdev->cc_support)
+ resp.cap_mask |= HBL_UCONTEXT_CAP_CC;
+
+ rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to copy out udata for alloc ucontext\n");
+ goto uninit_ports;
+ }
+
+ /* User context is allocated - set the handler for future EQE (should be last) */
+ aux_ops->eqe_work_schd = hbl_ib_eqe_work_schd;
+
+ hbl_ibdev_dbg(ibdev, "IB context was allocated\n");
+
+ return 0;
+
+uninit_ports:
+ for (--i; i >= 0; i--) {
+ if (!(user_ports_mask & BIT(i)))
+ continue;
+
+ hbl_ib_port_fini(hctx, i);
+ }
+ xa_destroy(&hctx->qp_xarray);
+ aux_ops->dealloc_ucontext(aux_dev, hctx->cn_ctx);
+exit:
+ atomic_set(&hdev->ctx_open, 0);
+
+ return rc;
+}
+
+static void hbl_ib_dealloc_ucontext(struct ib_ucontext *ibucontext)
+{
+ struct hbl_ib_device *hdev = to_hbl_ib_dev(ibucontext->device);
+ struct hbl_ib_ucontext *hctx = to_hbl_ib_ucontext(ibucontext);
+ struct hbl_aux_dev *aux_dev = hdev->aux_dev;
+ struct hbl_ib_aux_ops *aux_ops;
+ int i;
+
+ aux_ops = aux_dev->aux_ops;
+
+ /* User context is dealocated, prevent from future EQE call the handler */
+ aux_ops->eqe_work_schd = hbl_ib_eqe_null_work;
+
+ for (i = 0; i < hdev->max_num_of_ports; i++) {
+ if (!(hctx->ports_mask & BIT(i)))
+ continue;
+
+ hbl_ib_port_fini(hctx, i);
+ }
+
+ /* Core uverbs enforces that all ucontext sub-resources (e.g. QPs) are already released by
+ * the time we reach here. Hence, no need to check for active xarray IDs.
+ */
+ xa_destroy(&hctx->qp_xarray);
+
+ aux_ops->dealloc_ucontext(aux_dev, hctx->cn_ctx);
+
+ atomic_set(&hdev->ctx_open, 0);
+
+ hbl_ibdev_dbg(&hdev->ibdev, "IB context was deallocated\n");
+}
+
+static void hbl_ib_get_dev_fw_str(struct ib_device *device, char *str)
+{
+ struct hbl_ib_device *hdev = to_hbl_ib_dev(device);
+ struct hbl_aux_dev *aux_dev = hdev->aux_dev;
+ struct hbl_ib_device_attr dev_attr = {};
+ struct hbl_ib_aux_ops *aux_ops;
+
+ aux_ops = aux_dev->aux_ops;
+ aux_ops->query_device(aux_dev, &dev_attr);
+
+ snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%u.%u", (u32)(dev_attr.fw_ver >> 32),
+ (u16)FIELD_GET((0xffff << 16), dev_attr.fw_ver), (u16)(dev_attr.fw_ver & 0xffff));
+}
+
+static enum rdma_link_layer hbl_ib_port_link_layer(struct ib_device *ibdev, u32 port_num)
+{
+ return IB_LINK_LAYER_ETHERNET;
+}
+
+static int hbl_ib_get_port_immutable(struct ib_device *ibdev, u32 port_num,
+ struct ib_port_immutable *immutable)
+{
+ struct hbl_ib_device *hdev = to_hbl_ib_dev(ibdev);
+ struct ib_port_attr attr;
+ u32 hport = 0;
+ int rc;
+
+ rc = ib_to_hbl_port_num(hdev, port_num, &hport);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u\n", port_num);
+ return rc;
+ }
+
+ rc = ib_query_port(ibdev, port_num, &attr);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Couldn't query port %d, rc %d\n", port_num, rc);
+ return rc;
+ }
+
+ immutable->pkey_tbl_len = attr.pkey_tbl_len;
+ immutable->gid_tbl_len = attr.gid_tbl_len;
+
+ if (hdev->ext_ports_mask & BIT(hport))
+ /* RoCEv1 is used for MAC based address resolution on L2 networks.
+ * while RoCEv2 is used for IP based address resolution on L3 networks.
+ */
+ immutable->core_cap_flags = RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP |
+ RDMA_CORE_CAP_PROT_ROCE;
+ else
+ /* Since the internal ports are not advertised to netdev, we need to advertise them
+ * as plain IB to the IB core.
+ */
+ immutable->core_cap_flags = RDMA_CORE_CAP_PROT_IB;
+
+ return 0;
+}
+
+static int hbl_ib_query_device(struct ib_device *ibdev, struct ib_device_attr *props,
+ struct ib_udata *udata)
+{
+ struct hbl_ib_device *hdev = to_hbl_ib_dev(ibdev);
+ struct hbl_aux_dev *aux_dev = hdev->aux_dev;
+ struct hbl_ib_device_attr dev_attr = {};
+ struct hbl_ib_aux_ops *aux_ops;
+
+ aux_ops = aux_dev->aux_ops;
+
+ if (udata && udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen)) {
+ hbl_ibdev_dbg(ibdev, "Incompatible ABI params, udata not cleared\n");
+ return -EINVAL;
+ }
+
+ memset(props, 0, sizeof(*props));
+
+ aux_ops->query_device(aux_dev, &dev_attr);
+
+ props->fw_ver = dev_attr.fw_ver;
+ props->max_mr = 1;
+ props->max_mr_size = dev_attr.max_mr_size;
+ props->page_size_cap = dev_attr.page_size_cap;
+
+ props->vendor_id = dev_attr.vendor_id;
+ props->vendor_part_id = dev_attr.vendor_part_id;
+ props->hw_ver = dev_attr.hw_ver;
+
+ props->max_qp = dev_attr.max_qp;
+ props->max_qp_wr = dev_attr.max_qp_wr;
+
+ props->device_cap_flags = IB_DEVICE_RAW_MULTI |
+ IB_DEVICE_CHANGE_PHY_PORT |
+ IB_DEVICE_CURR_QP_STATE_MOD |
+ IB_DEVICE_SHUTDOWN_PORT |
+ IB_DEVICE_PORT_ACTIVE_EVENT |
+ IB_DEVICE_RC_RNR_NAK_GEN |
+ IB_DEVICE_N_NOTIFY_CQ;
+
+ /* RR is unsupported but we need at least 2 max sge to pass pyverbs test */
+ props->max_send_sge = HBL_IB_MAX_SEND_SGE;
+ props->max_recv_sge = HBL_IB_MAX_RECV_SGE;
+
+ /* RD is unsupported */
+ props->max_sge_rd = 0;
+ props->max_cq = 1;
+ props->max_cqe = dev_attr.max_cqe;
+
+ props->max_pd = 1;
+ props->atomic_cap = IB_ATOMIC_NONE;
+ props->max_raw_ipv6_qp = 1;
+ props->max_raw_ethy_qp = 1;
+ props->max_pkeys = 1;
+
+ if (udata && udata->outlen)
+ hbl_ibdev_dbg(ibdev, "Failed to copy udata for query_device\n");
+
+ return 0;
+}
+
+static u32 conv_lane_to_ib_width(u32 num_lanes)
+{
+ switch (num_lanes) {
+ case 1:
+ return IB_WIDTH_1X;
+ case 2:
+ return IB_WIDTH_2X;
+ case 4:
+ return IB_WIDTH_4X;
+ default:
+ return IB_WIDTH_4X;
+ }
+}
+
+static u32 conv_speed_to_ib_speed(u32 port_speed, u8 lanes)
+{
+ u32 speed_per_lane = port_speed / lanes;
+
+ switch (speed_per_lane) {
+ case SPEED_25000:
+ return IB_SPEED_EDR;
+ case SPEED_50000:
+ return IB_SPEED_HDR;
+ case SPEED_100000:
+ return IB_SPEED_NDR;
+ default:
+ return IB_SPEED_HDR;
+ }
+}
+
+static int hbl_ib_query_port(struct ib_device *ibdev, u32 port, struct ib_port_attr *props)
+{
+ struct hbl_ib_device *hdev = to_hbl_ib_dev(ibdev);
+ struct hbl_aux_dev *aux_dev = hdev->aux_dev;
+ struct hbl_ib_port_attr port_attr = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ u32 hport;
+ int rc;
+
+ rc = ib_to_hbl_port_num(hdev, port, &hport);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u\n", port);
+ return rc;
+ }
+
+ aux_ops = aux_dev->aux_ops;
+ aux_ops->query_port(aux_dev, hport, &port_attr);
+
+ props->state = port_attr.open ? IB_PORT_ACTIVE : IB_PORT_DOWN;
+ props->max_mtu = ib_mtu_int_to_enum(port_attr.max_mtu);
+
+ /* external ports: Use value initialized in hbl_ib_port.
+ * Internal ports: Hard code 4KB for now
+ */
+ props->active_mtu = ib_mtu_int_to_enum(hdev->ib_port[hport].mtu);
+ if (hdev->ext_ports_mask & BIT(hport))
+ props->gid_tbl_len = HBL_IB_MAX_PORT_GIDS;
+ else
+ props->gid_tbl_len = HBL_IB_MAX_PORT_GIDS_INTERNAL;
+
+ props->max_msg_sz = port_attr.max_msg_sz;
+ props->pkey_tbl_len = 1;
+
+ props->active_speed = conv_speed_to_ib_speed(port_attr.speed, port_attr.num_lanes);
+ props->active_width = conv_lane_to_ib_width(port_attr.num_lanes);
+
+ props->phys_state = port_attr.link_up ? IB_PORT_PHYS_STATE_LINK_UP :
+ IB_PORT_PHYS_STATE_DISABLED;
+
+ return 0;
+}
+
+static int hbl_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
+{
+ struct hbl_ib_ucontext *hctx = rdma_udata_to_drv_context(udata, struct hbl_ib_ucontext,
+ ibucontext);
+ struct hbl_ib_pd *pd = to_hbl_ib_pd(ibpd);
+ struct hbl_ibv_alloc_pd_resp resp = {};
+ struct ib_device *ibdev = ibpd->device;
+ int rc;
+
+ if (udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen)) {
+ hbl_ibdev_dbg(ibdev, "Incompatible ABI params, udata not cleared\n");
+ return -EINVAL;
+ }
+
+ /* currently only a single PD is supoprted */
+ if (atomic_cmpxchg(&hctx->pd_allocated, 0, 1)) {
+ hbl_ibdev_dbg(ibdev, "no available PD\n");
+ return -ESRCH;
+ }
+
+ pd->pdn = 1;
+ resp.pdn = pd->pdn;
+
+ if (udata->outlen) {
+ rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed to copy udata for alloc_pd\n");
+ goto err;
+ }
+ }
+
+ hbl_ibdev_dbg(ibdev, "allocated PD %d\n", pd->pdn);
+
+ return 0;
+
+err:
+ atomic_set(&hctx->pd_allocated, 0);
+
+ return rc;
+}
+
+static void cq_user_mmap_entries_remove(struct hbl_ib_cq *cq)
+{
+ if (cq->regs_handle_entry)
+ rdma_user_mmap_entry_remove(cq->regs_handle_entry);
+
+ rdma_user_mmap_entry_remove(cq->pi_handle_entry);
+ rdma_user_mmap_entry_remove(cq->mem_handle_entry);
+}
+
+static int cq_user_mmap_entries_setup(struct hbl_ib_device *dev, struct hbl_ib_cq *cq,
+ struct hbl_ib_ucontext *hctx, u32 cq_size, u64 *mem_handle,
+ u64 *pi_handle, u64 *regs_handle)
+{
+ int rc;
+
+ cq->mem_handle_entry = hbl_ib_user_mmap_entry_insert(&hctx->ibucontext, *mem_handle,
+ cq_size, mem_handle);
+ if (IS_ERR(cq->mem_handle_entry))
+ return PTR_ERR(cq->mem_handle_entry);
+
+ cq->pi_handle_entry = hbl_ib_user_mmap_entry_insert(&hctx->ibucontext, *pi_handle,
+ PAGE_SIZE, pi_handle);
+ if (IS_ERR(cq->pi_handle_entry)) {
+ rc = PTR_ERR(cq->pi_handle_entry);
+ goto err_free_mem;
+ }
+
+ if (regs_handle) {
+ cq->regs_handle_entry = hbl_ib_user_mmap_entry_insert(&hctx->ibucontext,
+ *regs_handle, PAGE_SIZE,
+ regs_handle);
+ if (IS_ERR(cq->regs_handle_entry)) {
+ rc = PTR_ERR(cq->regs_handle_entry);
+ goto err_free_pi;
+ }
+ }
+
+ return 0;
+
+err_free_pi:
+ rdma_user_mmap_entry_remove(cq->pi_handle_entry);
+
+err_free_mem:
+ rdma_user_mmap_entry_remove(cq->mem_handle_entry);
+
+ return rc;
+}
+
+/* Get the max supported port from ports_mask.
+ * based on MSB we are counting the maximum valid ports.
+ */
+static int get_max_ports_from_port_mask(int ports_mask)
+{
+ int max_num_ports = 0;
+ int msb_index = 0;
+
+ if (ports_mask == 0)
+ return -1;
+
+ while (ports_mask > 1) {
+ ports_mask >>= 1;
+ msb_index++;
+ }
+
+ max_num_ports = msb_index + 1;
+
+ return max_num_ports;
+}
+
+static int __create_per_port_cq(struct hbl_ib_cq *hblcq, struct hbl_ib_device *hdev,
+ const struct ib_cq_init_attr *attr, struct ib_udata *udata)
+{
+ u64 mmap_set_mask = 0, cq_set_mask = 0, ports_mask, ib_ports_mask;
+ struct hbl_cni_alloc_user_cq_id_out alloc_cq_out = {};
+ struct hbl_cni_alloc_user_cq_id_in alloc_cq_in = {};
+ struct hbl_cni_user_cq_id_unset_in cq_unset_in = {};
+ struct hbl_cni_user_cq_id_set_out cq_set_out = {};
+ struct hbl_ibv_port_create_cq_resp *port_cq_resp;
+ struct hbl_cni_user_cq_id_set_in cq_set_in = {};
+ struct hbl_ibv_create_cq_resp *resp = NULL;
+ struct hbl_ib_device_attr dev_attr = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_ib_cq *port_hblcq;
+ struct hbl_ib_port *ib_port;
+ struct hbl_aux_dev *aux_dev;
+ u32 cq_ib_port, cq_num, i;
+ struct ib_device *ibdev;
+ size_t resp_size;
+ int cqes, rc = 0;
+ int max_ports;
+
+ ibdev = &hdev->ibdev;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ cqes = attr->cqe;
+ hctx = hblcq->hctx;
+ ports_mask = hctx->ports_mask;
+
+ ib_ports_mask = to_ib_port_mask(hdev, ports_mask);
+ max_ports = get_max_ports_from_port_mask(ib_ports_mask);
+ if (max_ports < 0) {
+ hbl_ibdev_dbg(ibdev, "port mask is empty: %llx\n", ib_ports_mask);
+ return -EINVAL;
+ }
+
+ resp = kzalloc((sizeof(struct hbl_ibv_port_create_cq_resp) * max_ports) +
+ (sizeof(struct hbl_ibv_create_cq_resp)), GFP_KERNEL);
+ resp_size = (sizeof(struct hbl_ibv_port_create_cq_resp) * max_ports) +
+ (sizeof(struct hbl_ibv_create_cq_resp));
+
+ hblcq->port_cq = kzalloc((sizeof(struct hbl_ib_cq) * max_ports), GFP_KERNEL);
+
+ for (i = 0; i < max_ports; i++) {
+ if (!(ports_mask & BIT(i)))
+ continue;
+
+ cq_ib_port = hbl_to_ib_port_num(hdev, i);
+ ib_port = &hdev->ib_port[i];
+
+ /* Step 1: Alloc cq */
+ alloc_cq_in.port = i;
+
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_ALLOC_USER_CQ_ID,
+ &alloc_cq_in, &alloc_cq_out);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Allocation of cq_id failed, port: %u\n", i);
+ goto err_cq;
+ }
+
+ cq_num = alloc_cq_out.id;
+
+ port_hblcq = &hblcq->port_cq[cq_ib_port];
+ port_hblcq->hbl_port_num = i;
+ port_hblcq->cq_num = cq_num;
+ port_hblcq->cq_type = HBL_CQ_TYPE_QP;
+
+ cq_set_mask |= BIT(cq_ib_port);
+ aux_ops->query_device(aux_dev, &dev_attr);
+
+ if (cqes < dev_attr.min_cq_entries) {
+ cqes = dev_attr.min_cq_entries;
+ hbl_ibdev_dbg(ibdev,
+ "Requested cqe: %d is less than minimum required cqe: %d. Hence ceiling it to min required CQE\n",
+ cqes, dev_attr.min_cq_entries);
+ }
+
+ /* Step 2: USER_CQ Set */
+ cq_set_in.port = i;
+ cq_set_in.id = cq_num;
+ cq_set_in.num_of_cqes = cqes;
+
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_CQ_ID_SET, &cq_set_in,
+ &cq_set_out);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "CQ_ID Set failed, port: %u\n", i);
+ goto err_cq;
+ }
+
+ port_cq_resp = &resp->port_cq_resp[cq_ib_port];
+ port_cq_resp->cq_num = cq_num;
+ port_cq_resp->mem_handle = cq_set_out.mem_handle;
+ port_cq_resp->pi_handle = cq_set_out.pi_handle;
+ port_cq_resp->regs_handle = cq_set_out.regs_handle;
+ port_cq_resp->regs_offset = cq_set_out.regs_offset;
+ port_cq_resp->cq_size = PAGE_ALIGN(dev_attr.cqe_size * cqes);
+
+ rc = cq_user_mmap_entries_setup(hdev, &hblcq->port_cq[cq_ib_port], hctx,
+ port_cq_resp->cq_size, &port_cq_resp->mem_handle,
+ &port_cq_resp->pi_handle,
+ &port_cq_resp->regs_handle);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "unable to set up cq mmap entries\n");
+ goto err_cq;
+ }
+
+ mmap_set_mask |= BIT(cq_ib_port);
+ xa_store(&ib_port->hbl_ibcq_tbl, cq_num, &hblcq->ibcq, GFP_KERNEL);
+ }
+
+ if (udata->outlen) {
+ rc = ib_copy_to_udata(udata, resp, min(resp_size, udata->outlen));
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed to copy udata to userspace\n");
+ goto err_cq;
+ }
+ }
+
+ kfree(resp);
+ return 0;
+
+err_cq:
+ for (i = 0; i < hdev->max_num_of_ports; i++) {
+ if (mmap_set_mask & BIT(i))
+ cq_user_mmap_entries_remove(&hblcq->port_cq[i]);
+
+ if (cq_set_mask & BIT(i)) {
+ cq_unset_in.port = hblcq->port_cq[i].hbl_port_num;
+ cq_unset_in.id = hblcq->port_cq[i].cq_num;
+ if (aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_CQ_ID_UNSET,
+ &cq_unset_in, NULL)) {
+ hbl_ibdev_dbg(ibdev, "Failed to destroy cq, port: %d, cq_num: %d\n",
+ cq_unset_in.port, hblcq->port_cq[i].cq_num);
+ }
+ }
+ }
+
+ kfree(hblcq->port_cq);
+ kfree(resp);
+
+ return rc;
+}
+
+static int __create_cq(struct hbl_ib_cq *hblcq, struct hbl_ib_device *hdev,
+ const struct ib_cq_init_attr *attr, struct ib_udata *udata, u32 hbl_port_num)
+{
+ struct hbl_cni_alloc_user_cq_id_out alloc_cq_out = {};
+ struct hbl_cni_alloc_user_cq_id_in alloc_cq_in = {};
+ struct hbl_cni_user_cq_id_unset_in cq_unset_in = {};
+ struct hbl_cni_user_cq_id_set_out cq_set_out = {};
+ struct hbl_cni_user_cq_id_set_in cq_set_in = {};
+ struct hbl_ibv_create_cq_resp resp = {};
+ struct hbl_ib_device_attr dev_attr = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_ib_port *ib_port;
+ struct hbl_aux_dev *aux_dev;
+ struct ib_device *ibdev;
+ int cqes, rc;
+ u32 cq_num;
+
+ ibdev = &hdev->ibdev;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ cqes = attr->cqe;
+ ib_port = &hdev->ib_port[hbl_port_num];
+ hctx = hblcq->hctx;
+
+ /* Step 1: Alloc cq */
+ alloc_cq_in.port = hbl_port_num;
+
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_ALLOC_USER_CQ_ID, &alloc_cq_in,
+ &alloc_cq_out);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Allocation of cq_id failed, port: %d\n", hbl_port_num);
+ return rc;
+ }
+
+ cq_num = alloc_cq_out.id;
+
+ aux_ops->query_device(aux_dev, &dev_attr);
+
+ /* If the number of cqes requested by the IB user is less than the minimum required by the
+ * HW, ceil it to min required cq entries. This is needed to pass the test_cq pyverbs test.
+ */
+ if (cqes < dev_attr.min_cq_entries) {
+ cqes = dev_attr.min_cq_entries;
+ hbl_ibdev_dbg(ibdev,
+ "Requested cqe: %d is less than minimum required cqe: %d. Hence ceiling it to min required CQE\n",
+ cqes, dev_attr.min_cq_entries);
+ }
+
+ /* Step 2: USER_CQ Set */
+ cq_set_in.port = hbl_port_num;
+ cq_set_in.id = cq_num;
+ cq_set_in.num_of_cqes = cqes;
+
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_CQ_ID_SET, &cq_set_in,
+ &cq_set_out);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "CQ_ID Set failed, port: %d\n", hbl_port_num);
+ goto unset_cq;
+ }
+
+ resp.cq_num = cq_num;
+ resp.mem_handle = cq_set_out.mem_handle;
+ resp.pi_handle = cq_set_out.pi_handle;
+ resp.regs_handle = cq_set_out.regs_handle;
+ resp.regs_offset = cq_set_out.regs_offset;
+ resp.cq_size = PAGE_ALIGN(dev_attr.cqe_size * cqes);
+
+ rc = cq_user_mmap_entries_setup(hdev, hblcq, hctx, resp.cq_size, &resp.mem_handle,
+ &resp.pi_handle, &resp.regs_handle);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "unable to set up cq mmap entries\n");
+ goto unset_cq;
+ }
+
+ if (udata->outlen) {
+ rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed to copy udata to userspace\n");
+ goto unset_mmap_entries;
+ }
+ }
+
+ /* Number of cqes that are allocated. Also store the relevant data needed for
+ * destroying the cq.
+ */
+ hblcq->ibcq.cqe = cqes;
+ hblcq->hbl_port_num = hbl_port_num;
+ hblcq->cq_num = cq_num;
+ hblcq->cq_type = HBL_CQ_TYPE_QP;
+
+ xa_store(&ib_port->hbl_ibcq_tbl, cq_num, &hblcq->ibcq, GFP_KERNEL);
+
+ return 0;
+
+unset_mmap_entries:
+ cq_user_mmap_entries_remove(hblcq);
+
+unset_cq:
+ cq_unset_in.port = hbl_port_num;
+ cq_unset_in.id = cq_num;
+
+ if (aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_CQ_ID_UNSET, &cq_unset_in,
+ NULL))
+ hbl_ibdev_dbg(ibdev, "Failed to destroy cq, port: %d, cq_num: %d\n",
+ hbl_port_num, cq_num);
+
+ return rc;
+}
+
+static int __create_cc_cq(struct hbl_ib_cq *hblcq, struct hbl_ib_device *hdev,
+ const struct ib_cq_init_attr *attr, struct ib_udata *udata,
+ u32 hbl_port_num)
+{
+ struct hbl_cni_user_ccq_unset_in cc_cq_unset_in = {};
+ struct hbl_cni_user_ccq_set_out cc_cq_set_out = {};
+ struct hbl_cni_user_ccq_set_in cc_cq_set_in = {};
+ struct hbl_ibv_create_cq_resp resp = {};
+ struct hbl_ib_device_attr dev_attr = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_aux_dev *aux_dev;
+ struct ib_device *ibdev;
+ int rc;
+
+ ibdev = &hdev->ibdev;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ hctx = hblcq->hctx;
+
+ cc_cq_set_in.port = hbl_port_num;
+ cc_cq_set_in.num_of_entries = attr->cqe;
+
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_CCQ_SET, &cc_cq_set_in,
+ &cc_cq_set_out);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to set CC CQ, port %d\n", hbl_port_num);
+ return rc;
+ }
+
+ aux_ops->query_device(aux_dev, &dev_attr);
+
+ resp.cq_num = cc_cq_set_out.id;
+ resp.mem_handle = cc_cq_set_out.mem_handle;
+ resp.pi_handle = cc_cq_set_out.pi_handle;
+ resp.cq_size = PAGE_ALIGN(dev_attr.cqe_size * attr->cqe);
+
+ rc = cq_user_mmap_entries_setup(hdev, hblcq, hctx, resp.cq_size, &resp.mem_handle,
+ &resp.pi_handle, NULL);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "unable to set up cq mmap entries\n");
+ goto err_cc_cq_unset;
+ }
+
+ if (udata->outlen) {
+ rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed to copy udata to userspace\n");
+ goto err_mmap_entries_unset;
+ }
+ }
+
+ /* Number of cqes that are allocated. Also store the relevant data needed for destroying the
+ * cq.
+ */
+ hblcq->ibcq.cqe = attr->cqe;
+ hblcq->hbl_port_num = hbl_port_num;
+ hblcq->cq_num = cc_cq_set_out.id;
+ hblcq->cq_type = HBL_CQ_TYPE_CC;
+
+ return 0;
+
+err_mmap_entries_unset:
+ cq_user_mmap_entries_remove(hblcq);
+
+err_cc_cq_unset:
+ cc_cq_unset_in.port = hbl_port_num;
+
+ if (aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_CCQ_UNSET, &cc_cq_unset_in,
+ NULL))
+ hbl_ibdev_dbg(ibdev, "failed to unset CC CQ, port %d\n", hbl_port_num);
+
+ return rc;
+}
+
+static int create_cq(struct hbl_ib_cq *hblcq, struct hbl_ib_device *hdev,
+ const struct ib_cq_init_attr *attr, struct ib_udata *udata)
+{
+ struct hbl_ibv_create_cq_req cmd = {};
+ struct hbl_ib_ucontext *hctx;
+ struct ib_device *ibdev;
+ u32 hbl_port_num = 0;
+ int rc;
+
+ hctx = rdma_udata_to_drv_context(udata, struct hbl_ib_ucontext, ibucontext);
+ ibdev = &hdev->ibdev;
+
+ if (attr->flags) {
+ hbl_ibdev_dbg(ibdev, "attr->flags: %d but should be 0\n", attr->flags);
+ return -EOPNOTSUPP;
+ }
+
+ rc = ib_copy_from_udata(&cmd, udata, min(sizeof(cmd), udata->inlen));
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed to copy udata from user space\n");
+ return rc;
+ }
+
+ /* For native CQ port number is not relevant */
+ if (!(cmd.flags & CQ_FLAG_NATIVE)) {
+ rc = ib_to_hbl_port_num(hdev, cmd.port_num, &hbl_port_num);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u\n", cmd.port_num);
+ return rc;
+ }
+
+ if (!(hctx->ports_mask & BIT(hbl_port_num))) {
+ hbl_ibdev_dbg(ibdev,
+ "port %d is not part of the context's ports mask 0x%llx\n",
+ hbl_port_num, hctx->ports_mask);
+ return -EINVAL;
+ }
+ }
+
+ hblcq->hctx = hctx;
+
+ switch (cmd.cq_type) {
+ case HBL_CQ_TYPE_QP:
+ if (cmd.flags & CQ_FLAG_NATIVE) {
+ hblcq->is_native = true;
+ rc = __create_per_port_cq(hblcq, hdev, attr, udata);
+ } else {
+ rc = __create_cq(hblcq, hdev, attr, udata, hbl_port_num);
+ }
+ break;
+ case HBL_CQ_TYPE_CC:
+ rc = __create_cc_cq(hblcq, hdev, attr, udata, hbl_port_num);
+ break;
+ default:
+ hbl_ibdev_dbg(ibdev, "Invalid CQ resource requested %u\n", cmd.cq_type);
+ rc = -EINVAL;
+ }
+
+ return rc;
+}
+
+static int hbl_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
+ struct ib_udata *udata)
+{
+ struct hbl_ib_device *hdev = to_hbl_ib_dev(ibcq->device);
+ struct hbl_ib_cq *hblcq = to_hbl_ib_cq(ibcq);
+ int rc;
+
+ rc = create_cq(hblcq, hdev, attr, udata);
+ if (rc) {
+ hbl_ibdev_dbg(&hdev->ibdev, "Failed to create a CQ\n");
+ return rc;
+ }
+
+ return 0;
+}
+
+static int create_qp(struct hbl_ib_qp *hblqp, struct ib_qp_init_attr *qp_init_attr,
+ struct ib_udata *udata)
+{
+ struct hbl_ib_ucontext *hctx = rdma_udata_to_drv_context(udata, struct hbl_ib_ucontext,
+ ibucontext);
+ struct ib_device *ibdev = hblqp->ibqp.device;
+ u32 qp_num;
+ int rc;
+
+ /* Allocate an IB QP handle. Note,
+ * - It doesn't map to HW QPC index.
+ * - No HW or hbl_cn QP resources are allocated yet.
+ */
+ rc = xa_alloc(&hctx->qp_xarray, &qp_num, hblqp, xa_limit_32b, GFP_KERNEL);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed to allocate IB QP handle\n");
+ return rc;
+ }
+
+ hblqp->ibqp.qp_num = qp_num;
+ hblqp->qp_state = IB_QPS_RESET;
+ hblqp->hctx = hctx;
+
+ /* Cache the required QP params */
+ hblqp->max_send_wr = qp_init_attr->cap.max_send_wr;
+ hblqp->max_recv_wr = qp_init_attr->cap.max_recv_wr;
+
+ return 0;
+}
+
+static int hbl_ib_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *qp_init_attr,
+ struct ib_udata *udata)
+{
+ struct hbl_ib_qp *hblqp = to_hbl_ib_qp(ibqp);
+
+ return create_qp(hblqp, qp_init_attr, udata);
+}
+
+static int __hbl_ib_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
+{
+ struct hbl_ib_ucontext *hctx = rdma_udata_to_drv_context(udata, struct hbl_ib_ucontext,
+ ibucontext);
+ struct hbl_ib_pd *pd = to_hbl_ib_pd(ibpd);
+ struct ib_device *ibdev = ibpd->device;
+
+ hbl_ibdev_dbg(ibdev, "deallocated PD %d\n", pd->pdn);
+
+ atomic_set(&hctx->pd_allocated, 0);
+
+ return 0;
+}
+
+static int hbl_ib_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
+{
+ return __hbl_ib_dealloc_pd(ibpd, udata);
+}
+
+static int hbl_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata)
+{
+ return -EOPNOTSUPP;
+}
+
+static void __destroy_per_port_cq(struct hbl_ib_cq *hblcq, struct hbl_ib_device *hdev)
+{
+ struct hbl_cni_user_cq_id_unset_in cq_unset_in = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_ib_ucontext *hctx;
+ u32 cq_ib_port, hbl_port_num;
+ struct hbl_ib_cq *port_hblcq;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_port *ib_port;
+ struct ib_device *ibdev;
+ u64 ports_mask, i;
+ int rc;
+
+ ibdev = &hdev->ibdev;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ hctx = hblcq->hctx;
+ ports_mask = hctx->ports_mask;
+
+ for (i = 0; i < hdev->max_num_of_ports; i++) {
+ if (!(ports_mask & BIT(i)))
+ continue;
+
+ cq_ib_port = hbl_to_ib_port_num(hdev, i);
+ port_hblcq = &hblcq->port_cq[cq_ib_port];
+
+ cq_user_mmap_entries_remove(port_hblcq);
+
+ hbl_port_num = port_hblcq->hbl_port_num;
+ ib_port = &hdev->ib_port[hbl_port_num];
+ xa_erase(&ib_port->hbl_ibcq_tbl, port_hblcq->cq_num);
+ cq_unset_in.port = port_hblcq->hbl_port_num;
+ cq_unset_in.id = port_hblcq->cq_num;
+
+ if (aux_ops->device_operational(aux_dev)) {
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_CQ_ID_UNSET,
+ &cq_unset_in, NULL);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed to destroy cq, port: %d, cq_num: %d\n",
+ hblcq->hbl_port_num, hblcq->cq_num);
+ }
+ }
+ }
+
+ kfree(hblcq->port_cq);
+}
+
+static int destroy_cq(struct ib_cq *ibcq)
+{
+ struct hbl_cni_user_ccq_unset_in cc_cq_unset_in = {};
+ struct hbl_cni_user_cq_id_unset_in cq_unset_in = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_port *ib_port;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ struct hbl_ib_cq *hblcq;
+ int rc;
+
+ hblcq = to_hbl_ib_cq(ibcq);
+ ibdev = ibcq->device;
+ hdev = to_hbl_ib_dev(ibdev);
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ ib_port = &hdev->ib_port[hblcq->hbl_port_num];
+ hctx = hblcq->hctx;
+
+ if (hblcq->is_native) {
+ __destroy_per_port_cq(hblcq, hdev);
+ } else {
+ cq_user_mmap_entries_remove(hblcq);
+
+ if (hblcq->cq_type == HBL_CQ_TYPE_QP) {
+ xa_erase(&ib_port->hbl_ibcq_tbl, hblcq->cq_num);
+ cq_unset_in.port = hblcq->hbl_port_num;
+ cq_unset_in.id = hblcq->cq_num;
+
+ if (aux_ops->device_operational(aux_dev)) {
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx,
+ HBL_CNI_OP_USER_CQ_ID_UNSET, &cq_unset_in,
+ NULL);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev,
+ "Failed to destroy cq, port: %d, cq_num: %d\n",
+ hblcq->hbl_port_num, hblcq->cq_num);
+ return rc;
+ }
+ }
+ } else {
+ cc_cq_unset_in.port = hblcq->hbl_port_num;
+
+ if (aux_ops->device_operational(aux_dev)) {
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx,
+ HBL_CNI_OP_USER_CCQ_UNSET, &cc_cq_unset_in,
+ NULL);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to unset CC CQ, port %d\n",
+ hblcq->hbl_port_num);
+ return rc;
+ }
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int hbl_ib_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata)
+{
+ int rc;
+
+ rc = destroy_cq(ibcq);
+ if (rc)
+ return rc;
+
+ return 0;
+}
+
+static int __destroy_qp(struct hbl_ib_qp *hblqp)
+{
+ struct hbl_cni_destroy_conn_in destroy_conn_in = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ struct ib_qp *ibqp;
+ u32 hbl_port;
+ int rc;
+
+ ibqp = &hblqp->ibqp;
+ ibdev = ibqp->device;
+ hdev = to_hbl_ib_dev(ibdev);
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ hctx = hblqp->hctx;
+
+ qp_user_mmap_entries_remove(hblqp);
+
+ rc = ib_to_hbl_port_num(hdev, ibqp->port, &hbl_port);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u, IB QP %u\n", ibqp->port, ibqp->qp_num);
+ return rc;
+ }
+
+ destroy_conn_in.port = hbl_port;
+ destroy_conn_in.conn_id = hblqp->qp_id;
+
+ if (aux_ops->device_operational(aux_dev)) {
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_DESTROY_CONN,
+ &destroy_conn_in, NULL);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed to destroy QP id %d, port %d\n", hblqp->qp_id,
+ hbl_port);
+ return rc;
+ }
+ }
+ return 0;
+}
+
+static int destroy_qp(struct hbl_ib_qp *hblqp)
+{
+ struct hbl_ib_ucontext *hctx;
+ struct ib_qp *ibqp;
+ int rc;
+
+ rc = verify_qp_xarray(hblqp);
+ if (rc)
+ return rc;
+
+ ibqp = &hblqp->ibqp;
+ hctx = hblqp->hctx;
+
+ if (hblqp->qp_state >= IB_QPS_INIT) {
+ rc = __destroy_qp(hblqp);
+ if (rc)
+ return rc;
+ }
+
+ xa_erase(&hctx->qp_xarray, ibqp->qp_num);
+
+ return 0;
+}
+
+static int hbl_ib_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
+{
+ struct hbl_ib_qp *hblqp = to_hbl_ib_qp(ibqp);
+ int rc;
+
+ rc = destroy_qp(hblqp);
+ if (rc)
+ return rc;
+
+ return 0;
+}
+
+static struct rdma_hw_stats *__hbl_ib_alloc_hw_stats(struct ib_device *ibdev, u32 port_num)
+{
+ struct rdma_stat_desc *hbl_ib_port_stats;
+ struct hbl_ib_port_stats *port_stats;
+ struct hbl_ib_device *hdev;
+ u32 port;
+ int rc;
+
+ if (!port_num)
+ return rdma_alloc_hw_stats_struct(hbl_ib_device_stats,
+ ARRAY_SIZE(hbl_ib_device_stats),
+ RDMA_HW_STATS_DEFAULT_LIFESPAN);
+
+ hdev = to_hbl_ib_dev(ibdev);
+
+ rc = ib_to_hbl_port_num(hdev, port_num, &port);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u\n", port_num);
+ return NULL;
+ }
+
+ port_stats = &hdev->port_stats[port];
+
+ hbl_ib_port_stats = port_stats->stat_desc;
+
+ return rdma_alloc_hw_stats_struct(hbl_ib_port_stats, port_stats->num,
+ RDMA_HW_STATS_DEFAULT_LIFESPAN);
+}
+
+static struct rdma_hw_stats *hbl_ib_alloc_hw_port_stats(struct ib_device *ibdev, u32 port_num)
+{
+ return __hbl_ib_alloc_hw_stats(ibdev, port_num);
+}
+
+static struct rdma_hw_stats *hbl_ib_alloc_hw_device_stats(struct ib_device *ibdev)
+{
+ return __hbl_ib_alloc_hw_stats(ibdev, 0);
+}
+
+static int hbl_ib_get_hw_stats(struct ib_device *ibdev, struct rdma_hw_stats *stats, u32 port_num,
+ int index)
+{
+ struct hbl_ib_device *hdev = to_hbl_ib_dev(ibdev);
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ u32 port;
+ int rc;
+
+ if (!port_num) {
+ stats->value[FATAL_EVENT] = atomic_read(&hdev->dev_stats.fatal_event);
+
+ return ARRAY_SIZE(hbl_ib_device_stats);
+ }
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ rc = ib_to_hbl_port_num(hdev, port_num, &port);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u\n", port_num);
+ return rc;
+ }
+
+ if (!aux_ops->device_operational(aux_dev)) {
+ hbl_ibdev_dbg(ibdev, "device not operational, can't get stats\n");
+ return -EINVAL;
+ }
+
+ aux_ops->get_cnts_values(aux_dev, port, stats->value);
+
+ return stats->num_counters;
+}
+
+static int hbl_ib_mmap(struct ib_ucontext *ibucontext, struct vm_area_struct *vma)
+{
+ struct rdma_user_mmap_entry *rdma_entry;
+ struct hbl_ib_user_mmap_entry *entry;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ int rc;
+
+ ibdev = ibucontext->device;
+ hdev = to_hbl_ib_dev(ibdev);
+
+ rdma_entry = rdma_user_mmap_entry_get(ibucontext, vma);
+ if (!rdma_entry) {
+ hbl_ibdev_dbg(&hdev->ibdev, "pgoff[%#lx] does not have valid entry\n",
+ vma->vm_pgoff);
+ return -EINVAL;
+ }
+
+ entry = to_hbl_ib_user_mmap_entry(rdma_entry);
+
+ switch (entry->info.mtype) {
+ case HBL_IB_MEM_HW_BLOCK:
+ vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | VM_DONTCOPY |
+ VM_NORESERVE);
+
+ rc = rdma_user_mmap_io(ibucontext, vma, entry->info.bus_addr >> PAGE_SHIFT,
+ entry->rdma_entry.npages * PAGE_SIZE,
+ vma->vm_page_prot, rdma_entry);
+ break;
+ case HBL_IB_MEM_HOST_DMA_COHERENT:
+ case HBL_IB_MEM_HOST_MAP_ONLY:
+ if (entry->info.vmalloc) {
+ vm_flags_set(vma, VM_DONTEXPAND | VM_DONTDUMP | VM_DONTCOPY | VM_NORESERVE);
+
+ rc = remap_vmalloc_range(vma, entry->info.cpu_addr, 0);
+ } else {
+ vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
+ VM_DONTCOPY | VM_NORESERVE);
+
+ rc = remap_pfn_range(vma, vma->vm_start,
+ virt_to_phys(entry->info.cpu_addr) >> PAGE_SHIFT,
+ vma->vm_end - vma->vm_start, vma->vm_page_prot);
+ }
+ break;
+ case HBL_IB_MEM_HOST_VIRTUAL:
+ vm_flags_set(vma, VM_DONTEXPAND | VM_DONTDUMP | VM_DONTCOPY | VM_NORESERVE);
+
+ rc = remap_vmalloc_range(vma, entry->info.cpu_addr, 0);
+ break;
+ default:
+ hbl_ibdev_dbg(&hdev->ibdev,
+ "pgoff[%#lx] does not have valid entry memory type %d\n",
+ vma->vm_pgoff, entry->info.mtype);
+ rc = -EINVAL;
+ }
+
+ rdma_user_mmap_entry_put(rdma_entry);
+
+ return rc;
+}
+
+static void hbl_ib_mmap_free(struct rdma_user_mmap_entry *rdma_entry)
+{
+ struct hbl_ib_user_mmap_entry *entry = to_hbl_ib_user_mmap_entry(rdma_entry);
+
+ kfree(entry);
+}
+
+static int verify_qp_xarray(struct hbl_ib_qp *hblqp)
+{
+ struct ib_device *ibdev;
+ struct ib_qp *ibqp;
+
+ ibqp = &hblqp->ibqp;
+ ibdev = ibqp->device;
+
+ hblqp = xa_load(&hblqp->hctx->qp_xarray, ibqp->qp_num);
+ if (!hblqp) {
+ hbl_ibdev_dbg(ibdev, "Invalid IB QP %d modified\n", ibqp->qp_num);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int verify_modify_qp(struct hbl_ib_qp *hblqp, struct ib_qp_attr *qp_attr, int qp_attr_mask)
+{
+ struct ib_device *ibdev;
+ struct ib_qp *ibqp;
+ int rc;
+
+ ibqp = &hblqp->ibqp;
+ ibdev = ibqp->device;
+
+ rc = verify_qp_xarray(hblqp);
+ if (rc)
+ return rc;
+
+ /* Verify state change and corresponding QP attribute mask. */
+ if (!ib_modify_qp_is_ok(hblqp->qp_state, qp_attr->qp_state, IB_QPT_RC, qp_attr_mask)) {
+ hbl_ibdev_dbg(ibdev, "Invalid IB QP %d params\n", ibqp->qp_num);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int get_qp_wq_type(struct hbl_ib_device *hdev, enum qpc_req_wq_type *to, u8 from)
+{
+ if (from & HBL_WQ_READ_RDV_ENDP) {
+ if (hweight_long(from) != 1)
+ return -EINVAL;
+
+ *to = QPC_REQ_WQ_TYPE_RDV_READ;
+
+ return 0;
+ }
+
+ if (from & HBL_WQ_SEND_RDV) {
+ if (hweight_long(from) != 1)
+ return -EINVAL;
+
+ *to = QPC_REQ_WQ_TYPE_RDV_WRITE;
+
+ return 0;
+ }
+
+ if (from & (HBL_WQ_WRITE | HBL_WQ_RECV_RDV | HBL_WQ_READ_RDV)) {
+ if (hdev->mixed_qp_wq_types) {
+ if ((from & HBL_WQ_RECV_RDV) && (from & HBL_WQ_READ_RDV))
+ return -EINVAL;
+ } else {
+ if (hweight_long(from) != 1)
+ return -EINVAL;
+ }
+
+ *to = QPC_REQ_WQ_TYPE_WRITE;
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int alloc_qp(struct hbl_ib_qp *hblqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
+ struct hbl_ibv_modify_qp_req *modify_qp_req,
+ struct hbl_ibv_modify_qp_resp *modify_qp_resp)
+{
+ struct hbl_cni_alloc_conn_out alloc_conn_out = {};
+ struct hbl_cni_alloc_conn_in alloc_conn_in = {};
+ enum qpc_req_wq_type hbl_wq_type;
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ struct ib_qp *ibqp;
+ u8 ib_wq_type;
+ u32 hbl_port;
+ int rc;
+
+ ibqp = &hblqp->ibqp;
+ ibdev = ibqp->device;
+ hdev = to_hbl_ib_dev(ibdev);
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ hctx = hblqp->hctx;
+
+ rc = ib_to_hbl_port_num(hdev, qp_attr->port_num, &hbl_port);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u\n", qp_attr->port_num);
+ return rc;
+ }
+
+ ib_wq_type = modify_qp_req->wq_type;
+ rc = get_qp_wq_type(hdev, &hbl_wq_type, ib_wq_type);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid WQ type mask %d, port %u\n", ib_wq_type, hbl_port);
+ return rc;
+ }
+
+ alloc_conn_in.port = hbl_port;
+
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_ALLOC_CONN, &alloc_conn_in,
+ &alloc_conn_out);
+
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed to allocate QP, port %d\n", hbl_port);
+ return rc;
+ }
+
+ hblqp->qp_id = alloc_conn_out.conn_id;
+ hblqp->qp_state = IB_QPS_INIT;
+ hblqp->wq_type = hbl_wq_type;
+ hblqp->wq_granularity = modify_qp_req->wq_granularity;
+
+ modify_qp_resp->qp_num = hblqp->qp_id;
+
+ return 0;
+}
+
+static u8 get_req_cq_number(struct hbl_ib_qp *hblqp)
+{
+ struct hbl_ib_cq *hblcq;
+ struct ib_cq *ibcq;
+ struct ib_qp *ibqp;
+
+ ibqp = &hblqp->ibqp;
+ ibcq = ibqp->send_cq;
+ hblcq = to_hbl_ib_cq(ibcq);
+
+ return hblcq->is_native ? hblcq->port_cq[ibqp->port].cq_num : hblcq->cq_num;
+}
+
+static u8 get_res_cq_number(struct hbl_ib_qp *hblqp)
+{
+ struct hbl_ib_cq *hblcq;
+ struct ib_qp *ibqp;
+ struct ib_cq *ibcq;
+
+ ibqp = &hblqp->ibqp;
+ ibcq = ibqp->recv_cq;
+ hblcq = to_hbl_ib_cq(ibcq);
+
+ return hblcq->is_native ? hblcq->port_cq[ibqp->port].cq_num : hblcq->cq_num;
+}
+
+static void copy_mac_reverse(u8 *dst, u8 *src)
+{
+ int i;
+
+ for (i = 0; i < ETH_ALEN; i++)
+ dst[i] = src[(ETH_ALEN - 1) - i];
+}
+
+static inline bool is_l2_gid(struct in6_addr *addr)
+{
+ return (addr->s6_addr32[0] == htonl(0xfe800000)) && (addr->s6_addr32[1] == 0);
+}
+
+static int set_res_qp_ctx(struct hbl_ib_qp *hblqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
+ struct hbl_ibv_modify_qp_req *modify_qp_req)
+{
+ struct hbl_cni_res_conn_ctx_in res_conn_ctx_in = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ union ib_gid *dgid;
+ struct ib_qp *ibqp;
+ u32 hbl_port;
+ int rc;
+
+ ibqp = &hblqp->ibqp;
+ ibdev = ibqp->device;
+ hdev = to_hbl_ib_dev(ibdev);
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ dgid = &qp_attr->ah_attr.grh.dgid;
+ hctx = hblqp->hctx;
+
+ rc = ib_to_hbl_port_num(hdev, ibqp->port, &hbl_port);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u\n, IB QP %u", ibqp->port, ibqp->qp_num);
+ return rc;
+ }
+
+ /* If the ports are internal, anyway we don't use the dst_mac_addr when configuring the QPC.
+ * Instead we use the broadcast MAC for dest MAC. Refer the ASIC specific set_res_qp_ctx
+ */
+ if (hdev->ext_ports_mask & BIT(hbl_port)) {
+ copy_mac_reverse(hblqp->dst_mac_addr, qp_attr->ah_attr.roce.dmac);
+ memcpy(res_conn_ctx_in.dst_mac_addr, hblqp->dst_mac_addr, ETH_ALEN);
+ }
+
+ if ((hdev->ext_ports_mask & BIT(hbl_port)) && !is_l2_gid((struct in6_addr *)dgid->raw)) {
+ hblqp->dst_ip_addr = htonl(((struct in6_addr *)dgid->raw)->s6_addr32[3]);
+ res_conn_ctx_in.dst_ip_addr = hblqp->dst_ip_addr;
+ }
+
+ res_conn_ctx_in.dst_conn_id = qp_attr->dest_qp_num;
+ res_conn_ctx_in.port = hbl_port;
+ res_conn_ctx_in.conn_id = hblqp->qp_id;
+ res_conn_ctx_in.cq_number = get_res_cq_number(hblqp);
+ res_conn_ctx_in.local_key = modify_qp_req->local_key;
+ res_conn_ctx_in.priority = modify_qp_req->priority;
+ res_conn_ctx_in.loopback = modify_qp_req->loopback;
+ res_conn_ctx_in.wq_peer_size = hblqp->max_send_wr;
+ res_conn_ctx_in.rdv = hblqp->wq_type == QPC_REQ_WQ_TYPE_RDV_READ ||
+ hblqp->wq_type == QPC_REQ_WQ_TYPE_RDV_WRITE;
+ res_conn_ctx_in.conn_peer = hblqp->qp_id;
+ res_conn_ctx_in.wq_peer_granularity = hblqp->wq_granularity;
+ res_conn_ctx_in.encap_en = modify_qp_req->encap_en;
+ res_conn_ctx_in.encap_id = modify_qp_req->encap_num;
+
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_SET_RES_CONN_CTX, &res_conn_ctx_in,
+ NULL);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed to config RTR, QP %d, port %d\n", hblqp->qp_id,
+ hbl_port);
+ return rc;
+ }
+
+ hblqp->qp_state = IB_QPS_RTR;
+ hblqp->dest_qp_num = qp_attr->dest_qp_num;
+
+ if (qp_attr->path_mtu == HBL_IB_MTU_8192)
+ hblqp->mtu = 8192;
+ else
+ hblqp->mtu = ib_mtu_enum_to_int(qp_attr->path_mtu);
+
+ return 0;
+}
+
+static void qp_user_mmap_entries_remove(struct hbl_ib_qp *qp)
+{
+ if (qp->rwq_mem_handle_entry)
+ rdma_user_mmap_entry_remove(qp->rwq_mem_handle_entry);
+ if (qp->swq_mem_handle_entry)
+ rdma_user_mmap_entry_remove(qp->swq_mem_handle_entry);
+}
+
+static int qp_user_mmap_entries_setup(struct hbl_ib_device *dev, struct hbl_ib_qp *qp,
+ struct hbl_ib_ucontext *hctx,
+ struct hbl_ibv_modify_qp_resp *resp)
+{
+ int rc;
+
+ if (resp->swq_mem_handle) {
+ qp->swq_mem_handle_entry = hbl_ib_user_mmap_entry_insert(&hctx->ibucontext,
+ resp->swq_mem_handle,
+ resp->swq_mem_size,
+ &resp->swq_mem_handle);
+ if (IS_ERR(qp->swq_mem_handle_entry)) {
+ rc = PTR_ERR(qp->swq_mem_handle_entry);
+ goto reset_swq_entry;
+ }
+ }
+
+ if (resp->rwq_mem_handle) {
+ qp->rwq_mem_handle_entry = hbl_ib_user_mmap_entry_insert(&hctx->ibucontext,
+ resp->rwq_mem_handle,
+ resp->rwq_mem_size,
+ &resp->rwq_mem_handle);
+ if (IS_ERR(qp->rwq_mem_handle_entry)) {
+ rc = PTR_ERR(qp->rwq_mem_handle_entry);
+ goto reset_rwq_entry;
+ }
+ }
+
+ return 0;
+
+reset_rwq_entry:
+ qp->rwq_mem_handle_entry = NULL;
+ if (qp->swq_mem_handle_entry)
+ rdma_user_mmap_entry_remove(qp->swq_mem_handle_entry);
+
+reset_swq_entry:
+ qp->swq_mem_handle_entry = NULL;
+
+ return rc;
+}
+
+static int set_req_qp_ctx(struct hbl_ib_qp *hblqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
+ struct hbl_ibv_modify_qp_req *modify_qp_req,
+ struct hbl_ibv_modify_qp_resp *modify_qp_resp)
+{
+ struct hbl_cni_req_conn_ctx_out req_conn_ctx_out = {};
+ struct hbl_cni_req_conn_ctx_in req_conn_ctx_in = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ struct ib_qp *ibqp;
+ u32 hbl_port;
+ int rc;
+
+ ibqp = &hblqp->ibqp;
+ ibdev = ibqp->device;
+ hdev = to_hbl_ib_dev(ibdev);
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ hctx = hblqp->hctx;
+
+ rc = ib_to_hbl_port_num(hdev, ibqp->port, &hbl_port);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u, IB QP %u\n", ibqp->port, ibqp->qp_num);
+ return rc;
+ }
+
+ req_conn_ctx_in.port = hbl_port;
+ req_conn_ctx_in.conn_id = hblqp->qp_id;
+ req_conn_ctx_in.dst_conn_id = hblqp->dest_qp_num;
+ req_conn_ctx_in.wq_type = hblqp->wq_type;
+ req_conn_ctx_in.wq_size = hblqp->max_send_wr;
+ req_conn_ctx_in.cq_number = get_req_cq_number(hblqp);
+ req_conn_ctx_in.remote_key = modify_qp_req->remote_key;
+ req_conn_ctx_in.priority = modify_qp_req->priority;
+ req_conn_ctx_in.timer_granularity = qp_attr->timeout;
+
+ if (modify_qp_req->dest_wq_size) {
+ if (!is_power_of_2(modify_qp_req->dest_wq_size)) {
+ hbl_ibdev_dbg(ibdev, "dest_wq_size :%d is not power of 2, QP %d, port %d\n",
+ modify_qp_req->dest_wq_size, hblqp->qp_id, hbl_port);
+ return -EINVAL;
+ }
+ req_conn_ctx_in.wq_remote_log_size = ilog2(modify_qp_req->dest_wq_size);
+ }
+
+ req_conn_ctx_in.congestion_en = modify_qp_req->congestion_en;
+ req_conn_ctx_in.congestion_wnd = modify_qp_req->congestion_wnd;
+ req_conn_ctx_in.loopback = modify_qp_req->loopback;
+ req_conn_ctx_in.compression_en = modify_qp_req->compression_en;
+ req_conn_ctx_in.encap_en = modify_qp_req->encap_en;
+ req_conn_ctx_in.encap_id = modify_qp_req->encap_num;
+ req_conn_ctx_in.swq_granularity = hblqp->wq_granularity;
+ req_conn_ctx_in.mtu = hblqp->mtu;
+
+ /* If the ports are internal, anyway we don't use the dst_mac_addr when configuring the QPC.
+ * Instead we use the broadcast MAC for dest MAC. Refer the ASIC specific set_req_qp_ctx
+ */
+ if (hdev->ext_ports_mask & BIT(hbl_port)) {
+ memcpy(req_conn_ctx_in.dst_mac_addr, hblqp->dst_mac_addr, ETH_ALEN);
+ req_conn_ctx_in.dst_ip_addr = hblqp->dst_ip_addr;
+ }
+
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_SET_REQ_CONN_CTX, &req_conn_ctx_in,
+ &req_conn_ctx_out);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed to config RTS, QP %d, port %d\n",
+ hblqp->qp_id, hbl_port);
+ return rc;
+ }
+
+ modify_qp_resp->swq_mem_handle = req_conn_ctx_out.swq_mem_handle;
+ modify_qp_resp->swq_mem_size = req_conn_ctx_out.swq_mem_size;
+ modify_qp_resp->rwq_mem_handle = req_conn_ctx_out.rwq_mem_handle;
+ modify_qp_resp->rwq_mem_size = req_conn_ctx_out.rwq_mem_size;
+
+ WARN_ON_ONCE(!PAGE_ALIGNED(modify_qp_resp->swq_mem_size));
+ WARN_ON_ONCE(!PAGE_ALIGNED(modify_qp_resp->rwq_mem_size));
+
+ rc = qp_user_mmap_entries_setup(hdev, hblqp, hctx, modify_qp_resp);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed create mmap entries for QP %d, port %d\n",
+ hblqp->qp_id, hbl_port);
+ return rc;
+ }
+
+ hblqp->qp_state = IB_QPS_RTS;
+
+ return 0;
+}
+
+static int reset_qp(struct hbl_ib_qp *hblqp)
+{
+ struct ib_device *ibdev;
+ struct ib_qp *ibqp;
+ int rc;
+
+ ibqp = &hblqp->ibqp;
+ ibdev = ibqp->device;
+
+ rc = __destroy_qp(hblqp);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed to reset QP %d, port %d\n", hblqp->qp_id, ibqp->port);
+ return rc;
+ }
+
+ hblqp->qp_state = IB_QPS_RESET;
+
+ return 0;
+}
+
+static int hbl_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
+ struct ib_udata *udata)
+{
+ struct hbl_ibv_modify_qp_resp modify_qp_resp = {};
+ struct hbl_ibv_modify_qp_req modify_qp_req = {};
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ struct hbl_ib_qp *hblqp;
+ u32 ib_port, hbl_port;
+ int rc;
+
+ ibdev = ibqp->device;
+ hdev = to_hbl_ib_dev(ibdev);
+ hblqp = to_hbl_ib_qp(ibqp);
+ hctx = hblqp->hctx;
+
+ rc = verify_modify_qp(hblqp, qp_attr, qp_attr_mask);
+ if (rc)
+ return rc;
+
+ ib_port = (qp_attr_mask & IB_QP_PORT) ? qp_attr->port_num : hblqp->ibqp.port;
+
+ rc = ib_to_hbl_port_num(hdev, ib_port, &hbl_port);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u\n", ib_port);
+ return rc;
+ }
+
+ if (!(hctx->ports_mask & BIT(hbl_port))) {
+ hbl_ibdev_dbg(ibdev, "port %d is not part of the context's ports mask 0x%llx\n",
+ hbl_port, hctx->ports_mask);
+ return -EINVAL;
+ }
+
+ rc = ib_copy_from_udata(&modify_qp_req, udata, min(sizeof(modify_qp_req), udata->inlen));
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed to copy from modify QP udata\n");
+ return rc;
+ }
+
+ if ((qp_attr_mask & IB_QP_STATE) && qp_attr->qp_state == IB_QPS_RESET) {
+ /* QP state transition IB_QPS_RESET ==> IB_QPS_RESET is NoOps */
+ if (hblqp->qp_state != IB_QPS_RESET) {
+ rc = reset_qp(hblqp);
+ if (rc)
+ return rc;
+ }
+ }
+
+ if ((qp_attr_mask & IB_QP_STATE) && qp_attr->qp_state == IB_QPS_INIT) {
+ /* QP state transition IB_QPS_INIT ==> IB_QPS_INIT. Destroy old QP. */
+ if (hblqp->qp_state == IB_QPS_INIT) {
+ rc = reset_qp(hblqp);
+ if (rc)
+ return rc;
+ }
+
+ rc = alloc_qp(hblqp, qp_attr, qp_attr_mask, &modify_qp_req, &modify_qp_resp);
+ if (rc)
+ return rc;
+ }
+
+ if ((qp_attr_mask & IB_QP_STATE) && qp_attr->qp_state == IB_QPS_RTR) {
+ rc = set_res_qp_ctx(hblqp, qp_attr, qp_attr_mask, &modify_qp_req);
+ if (rc)
+ goto err_reset_qp;
+ }
+
+ if ((qp_attr_mask & IB_QP_STATE) && qp_attr->qp_state == IB_QPS_RTS) {
+ rc = set_req_qp_ctx(hblqp, qp_attr, qp_attr_mask, &modify_qp_req, &modify_qp_resp);
+ if (rc)
+ goto err_reset_qp;
+ }
+
+ rc = ib_copy_to_udata(udata, &modify_qp_resp, min(sizeof(modify_qp_resp), udata->outlen));
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "Failed to copy to QP modify udata\n");
+ goto err_reset_qp;
+ }
+
+ return 0;
+
+err_reset_qp:
+ reset_qp(hblqp);
+
+ return rc;
+}
+
+static int hbl_ib_query_gid(struct ib_device *ibdev, u32 port, int index, union ib_gid *gid)
+{
+ /* The IB core would query the GID for non-ROCE ports i.e. internal ports */
+ memset(gid->raw, 0xFF, sizeof(gid->raw));
+
+ return 0;
+}
+
+static int hbl_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, u16 *pkey)
+{
+ if (index > 0)
+ return -EINVAL;
+
+ *pkey = 0xffff;
+
+ return 0;
+}
+
+static int hbl_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
+ struct ib_qp_init_attr *qp_init_attr)
+{
+ struct hbl_ib_qp *hblqp;
+
+ hblqp = to_hbl_ib_qp(ibqp);
+
+ memset(qp_attr, 0, sizeof(*qp_attr));
+ memset(qp_init_attr, 0, sizeof(*qp_init_attr));
+
+ qp_attr->qp_state = hblqp->qp_state;
+ qp_attr->dest_qp_num = hblqp->dest_qp_num;
+ qp_attr->port_num = ibqp->port;
+
+ qp_init_attr->cap.max_send_wr = hblqp->max_send_wr;
+ qp_init_attr->cap.max_recv_wr = hblqp->max_recv_wr;
+
+ /* We need to populate these 2 params to pass query_qp pyverbs test */
+ qp_init_attr->cap.max_send_sge = HBL_IB_MAX_SEND_SGE;
+ qp_init_attr->cap.max_recv_sge = HBL_IB_MAX_RECV_SGE;
+
+ /* Both xrcd and qp_access_flags are not used by our flows, so we may override them in order
+ * to pass extra data for EQ events.
+ */
+ qp_attr->qp_access_flags = (int)(uintptr_t)ibqp->xrcd;
+
+ return 0;
+}
+
+static struct ib_mr *hbl_ib_reg_mr(struct ib_pd *ibpd, u64 start, u64 length, u64 virt_addr,
+ int access_flags, struct ib_udata *udata)
+{
+ return ERR_PTR(-EOPNOTSUPP);
+}
+
+static struct ib_mr *hbl_ib_reg_user_mr_dmabuf(struct ib_pd *ibpd, u64 start, u64 length,
+ u64 virt_addr, int fd, int access_flags,
+ struct ib_udata *udata)
+{
+ return ERR_PTR(-EOPNOTSUPP);
+}
+
+/* The GID table is created and maintained by the kernel rdma cache module based on the gid_tbl_len
+ * provided. add_gid callback would be called whenever a new GID entry is added to the GID table. We
+ * get the gid details as part of the attr param. We can store that for our reference.
+ */
+static int hbl_ib_add_gid(const struct ib_gid_attr *attr, void **context)
+{
+ struct hbl_ib_device *hdev = to_hbl_ib_dev(attr->device);
+ struct hbl_aux_dev *aux_dev = hdev->aux_dev;
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_ib_port *ib_port;
+ union hbl_ib_sockaddr {
+ struct sockaddr_in saddr_in;
+ struct sockaddr_in6 saddr_in6;
+ } sa;
+ u32 port, ip_addr;
+ int rc;
+
+ rc = ib_to_hbl_port_num(hdev, attr->port_num, &port);
+ if (rc) {
+ hbl_ibdev_dbg(&hdev->ibdev, "invalid IB port %u\n", attr->port_num);
+ return rc;
+ }
+
+ ib_port = &hdev->ib_port[port];
+ aux_ops = aux_dev->aux_ops;
+
+ memcpy(ib_port->gids[attr->index].gid.raw, attr->gid.raw, sizeof(attr->gid));
+ ib_port->gids[attr->index].gid_type = attr->gid_type;
+
+ if (ipv6_addr_v4mapped((struct in6_addr *)&attr->gid)) {
+ rdma_gid2ip((struct sockaddr *)&sa, &ib_port->gids[attr->index].gid);
+ ip_addr = be32_to_cpu(sa.saddr_in.sin_addr.s_addr);
+ aux_ops->set_ip_addr_encap(aux_dev, ip_addr, port);
+ }
+
+ return 0;
+}
+
+static int hbl_ib_del_gid(const struct ib_gid_attr *attr, void **context)
+{
+ struct hbl_ib_device *hdev = to_hbl_ib_dev(attr->device);
+ struct hbl_ib_port *ib_port;
+
+ if (attr->port_num > hdev->max_num_of_ports) {
+ hbl_ibdev_dbg(&hdev->ibdev, "%s, port num: %d out of bounds\n", __func__,
+ attr->port_num);
+ return -EINVAL;
+ }
+
+ ib_port = &hdev->ib_port[attr->port_num - 1];
+
+ /* validate the params */
+ if (attr->index >= HBL_IB_MAX_PORT_GIDS) {
+ hbl_ibdev_dbg(&hdev->ibdev, "%s, GID index: %d out of bounds\n", __func__,
+ attr->index);
+ return -EINVAL;
+ }
+
+ memset(ib_port->gids[attr->index].gid.raw, 0, sizeof(attr->gid));
+ ib_port->gids[attr->index].gid_type = 0;
+
+ return 0;
+}
+
+static int hbl_ib_fill_data(struct sk_buff *msg, struct ib_qp *ibqp, bool req, bool print_qp_id)
+{
+ char *data_buf, *str_buf, *ptr, *ptr2, *ptr3, *full_name, *name, *val, *prefix;
+ struct hbl_ib_dump_qp_attr attr = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ struct hbl_ib_qp *hblqp;
+ int rc = 0, len, i;
+ u32 hbl_port;
+
+ ibdev = ibqp->device;
+ hblqp = to_hbl_ib_qp(ibqp);
+ hdev = to_hbl_ib_dev(ibdev);
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ rc = ib_to_hbl_port_num(hdev, ibqp->port, &hbl_port);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u\n", ibqp->port);
+ return rc;
+ }
+
+ data_buf = kzalloc(HBL_IB_DUMP_QP_SZ, GFP_KERNEL);
+ if (!data_buf)
+ return -ENOMEM;
+
+ str_buf = kcalloc(2, NAME_MAX, GFP_KERNEL);
+ if (!str_buf) {
+ rc = -ENOMEM;
+ goto free_data_buf;
+ }
+
+ prefix = req ? "req_" : "res_";
+
+ full_name = str_buf;
+ memcpy(full_name, prefix, strlen(prefix));
+ name = full_name + strlen(prefix);
+
+ val = full_name + NAME_MAX;
+
+ attr.port = hbl_port;
+ attr.qpn = hblqp->qp_id;
+ attr.req = req;
+ attr.full = false;
+ attr.force = true;
+
+ rc = aux_ops->dump_qp(aux_dev, &attr, data_buf, HBL_IB_DUMP_QP_SZ);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to dump QP %d, port %d\n", attr.qpn, attr.port);
+ rc = -ENODATA;
+ goto free_str_buf;
+ }
+
+ if (print_qp_id) {
+ snprintf(val, NAME_MAX, "%u", hblqp->qp_id);
+ rc = rdma_nl_put_driver_string(msg, "qp_id", val);
+ if (rc)
+ goto free_str_buf;
+ }
+
+ /* skip first line */
+ ptr = strchr(data_buf, '\n');
+ ptr++;
+
+ while (1) {
+ ptr2 = strchr(ptr, ':');
+ if (!ptr2)
+ break;
+
+ /* Skip section headlines and any empty lines - they don't have (:) separator */
+ do {
+ ptr3 = strchr(ptr, '\n');
+ if (!ptr3 || ptr3 >= ptr2)
+ break;
+
+ ptr = ptr3 + 1;
+ } while (1);
+
+ /* extract attribute name */
+ len = ptr2 - ptr;
+ memcpy(name, ptr, len);
+ name[len] = '\0';
+
+ /* to lowercase and no spaces */
+ for (i = 0; i < len; i++)
+ if (isspace(name[i]))
+ name[i] = '_';
+ else
+ name[i] = tolower(name[i]);
+
+ /* skip ':' and the following space */
+ ptr = ptr2 + 2;
+
+ ptr2 = strchr(ptr, '\n');
+
+ /* extract attribute value */
+ len = ptr2 - ptr;
+ memcpy(val, ptr, len);
+ val[len] = '\0';
+
+ if (rdma_nl_put_driver_string(msg, full_name, val)) {
+ rc = -EMSGSIZE;
+ goto free_str_buf;
+ }
+
+ /* move to next line */
+ ptr = ptr2 + 1;
+ }
+
+free_str_buf:
+ kfree(str_buf);
+free_data_buf:
+ kfree(data_buf);
+
+ return rc;
+}
+
+static int hbl_ib_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ibqp)
+{
+ struct ib_device *ibdev = ibqp->device;
+ struct nlattr *table_attr;
+ int rc;
+
+ table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER);
+ if (!table_attr)
+ return -EMSGSIZE;
+
+ rc = hbl_ib_fill_data(msg, ibqp, true, true);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed get REQ QP %d data, port %d\n", ibqp->qp_num,
+ ibqp->port);
+ rc = -ENODATA;
+ goto free_table;
+ }
+
+ rc = hbl_ib_fill_data(msg, ibqp, false, false);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed get RES QP %d data, port %d\n", ibqp->qp_num,
+ ibqp->port);
+ rc = -ENODATA;
+ goto free_table;
+ }
+
+ nla_nest_end(msg, table_attr);
+
+ return 0;
+
+free_table:
+ nla_nest_cancel(msg, table_attr);
+ return rc;
+}
+
+void hbl_ib_eqe_null_work(struct hbl_aux_dev *aux_dev, u32 port)
+{
+}
+
+void hbl_ib_eqe_work_schd(struct hbl_aux_dev *aux_dev, u32 port)
+{
+ struct hbl_ib_device *hdev = aux_dev->priv;
+ struct hbl_ib_port *ib_port;
+
+ ib_port = &hdev->ib_port[port];
+
+ if (!ib_port->open)
+ return;
+
+ /* Use this atomic to prevent a race - a thread handling received EQE in hbl_cn enters here
+ * to wake up the EQ thread while another thread is executing hbl_ib_port_fini which
+ * releases it. In such case the first thread might access a released resource.
+ */
+ if (atomic_cmpxchg(&ib_port->eq_lock, 0, 1))
+ return;
+
+ complete(&ib_port->eq_comp);
+
+ atomic_set(&ib_port->eq_lock, 0);
+}
+
+static bool hbl_ib_dispatch_event_qp(struct hbl_ib_device *hdev, struct hbl_ib_ucontext *hctx,
+ u32 port, u32 qpn, enum ib_event_type event_type,
+ u64 extra_data)
+{
+ struct ib_event ibev = {};
+ struct hbl_ib_qp *hblqp;
+ bool found_qp = false;
+ unsigned long id = 0;
+ struct ib_qp *ibqp;
+ u32 qp_port;
+ int rc;
+
+ xa_lock(&hctx->qp_xarray);
+ xa_for_each(&hctx->qp_xarray, id, hblqp) {
+ ibqp = &hblqp->ibqp;
+
+ rc = ib_to_hbl_port_num(hdev, ibqp->port, &qp_port);
+ if (rc) {
+ hbl_ibdev_dbg(&hdev->ibdev, "invalid IB port %u, IB QP %u\n", ibqp->port,
+ ibqp->qp_num);
+ continue;
+ }
+
+ /* We need to iterate over all QPs that are allocated
+ * under this CTX as we need to perform backward mapping
+ * of QP ID we have in HBL to the corresponding IB QP struct
+ */
+ if (hblqp->qp_id == qpn && qp_port == port) {
+ /* xrcd is not used by our flows, so we may override it in order to pass
+ * extra data for EQ events.
+ * This is not part of the event, but rather part of the qp structure.
+ * Meaning an additional QP event will override the value stored in xrcd.
+ * Since this is an error case, the QP should not receive anymore events.
+ */
+ ibqp->xrcd = (void *)extra_data;
+ ibev.event = event_type;
+ ibev.element.qp = ibqp;
+
+ ibqp->event_handler(&ibev, ibqp->qp_context);
+
+ /* We should mark the QP as in error state */
+ hblqp->qp_state = IB_QPS_ERR;
+
+ found_qp = true;
+ break;
+ }
+ }
+
+ xa_unlock(&hctx->qp_xarray);
+
+ return found_qp;
+}
+
+void hbl_ib_eqe_handler(struct hbl_ib_port *ib_port)
+{
+ struct hbl_ib_ucontext *hctx = ib_port->hctx;
+ struct hbl_cni_eq_poll_out eq_poll_out = {};
+ struct hbl_ib_device *hdev = ib_port->hdev;
+ struct hbl_cni_eq_poll_in eq_poll_in = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ enum ib_event_type event_type;
+ struct hbl_aux_dev *aux_dev;
+ struct ib_event ibev = {};
+ u32 port = ib_port->port;
+ bool found_qp = false;
+ struct ib_cq *ibcq;
+ int rc;
+
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+ eq_poll_in.port = port;
+
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_EQ_POLL, &eq_poll_in,
+ &eq_poll_out);
+ if (rc) {
+ hbl_ibdev_err(&hdev->ibdev, "port %d - EQ poll failed %d\n", port, rc);
+ return;
+ }
+
+ switch (eq_poll_out.status) {
+ case HBL_CNI_EQ_POLL_STATUS_SUCCESS:
+
+ ibev.device = &hdev->ibdev;
+
+ switch (eq_poll_out.ev_type) {
+ case HBL_CNI_EQ_EVENT_TYPE_CQ_ERR:
+ hbl_ibdev_dbg(&hdev->ibdev, "port %d cq %d - received CQ ERR event\n", port,
+ eq_poll_out.idx);
+
+ xa_lock(&ib_port->hbl_ibcq_tbl);
+ ibcq = xa_load(&ib_port->hbl_ibcq_tbl, eq_poll_out.idx);
+
+ if (ibcq) {
+ ibev.element.cq = ibcq;
+ ibev.event = IB_EVENT_CQ_ERR;
+
+ ibcq->event_handler(&ibev, ibcq->cq_context);
+ } else {
+ hbl_ibdev_err(&hdev->ibdev,
+ "port %d cq %d - received CQ ERR event, but CQ is not allocated\n",
+ port, eq_poll_out.idx);
+ }
+
+ xa_unlock(&ib_port->hbl_ibcq_tbl);
+ break;
+ case HBL_CNI_EQ_EVENT_TYPE_QP_ERR:
+ /* In IBv we can't pass the syndrome value to user space via IB events
+ * mechanism, and hence we will print it instead.
+ */
+ hbl_ibdev_err(&hdev->ibdev, "port %d qp %d - received QP ERR syndrome: %s\n",
+ port, eq_poll_out.idx,
+ aux_ops->qp_syndrome_to_str(aux_dev, eq_poll_out.ev_data));
+
+ event_type = eq_poll_out.is_req ? IB_EVENT_QP_REQ_ERR : IB_EVENT_QP_FATAL;
+
+ found_qp = hbl_ib_dispatch_event_qp(hdev, hctx, port, eq_poll_out.idx,
+ event_type, eq_poll_out.ev_data);
+
+ if (!found_qp)
+ hbl_ibdev_err(&hdev->ibdev,
+ "port %d qp %d - received QP ERR event, but QP is not allocated\n",
+ port, eq_poll_out.idx);
+
+ break;
+ case HBL_CNI_EQ_EVENT_TYPE_DB_FIFO_ERR:
+ hbl_ibdev_err(&hdev->ibdev, "port %d user fifo %d error\n", port,
+ eq_poll_out.idx);
+
+ ibev.event = IB_EVENT_DEVICE_FATAL;
+ ibev.element.port_num = (port & HBL_IB_EQ_PORT_FIELD_MASK) |
+ (eq_poll_out.idx << HBL_IB_EQ_PORT_FIELD_SIZE);
+ ib_dispatch_event(&ibev);
+ break;
+ case HBL_CNI_EQ_EVENT_TYPE_CCQ:
+ hbl_ibdev_dbg(&hdev->ibdev, "Port %u: got completion on congestion CQ %u\n",
+ port, eq_poll_out.idx);
+
+ ibev.event = IB_EVENT_SM_CHANGE;
+ ibev.element.port_num = (port & HBL_IB_EQ_PORT_FIELD_MASK) |
+ (eq_poll_out.idx << HBL_IB_EQ_PORT_FIELD_SIZE);
+ ib_dispatch_event(&ibev);
+ break;
+ case HBL_CNI_EQ_EVENT_TYPE_WTD_SECURITY_ERR:
+ hbl_ibdev_dbg(&hdev->ibdev, "Port %u: got WTD security error on QP %u\n",
+ port, eq_poll_out.idx);
+
+ found_qp = hbl_ib_dispatch_event_qp(hdev, hctx, port, eq_poll_out.idx,
+ IB_EVENT_PATH_MIG, 0);
+
+ if (!found_qp)
+ hbl_ibdev_err(&hdev->ibdev,
+ "port %d qp %d - received WTD security event, but QP is not allocated\n",
+ port, eq_poll_out.idx);
+ break;
+ case HBL_CNI_EQ_EVENT_TYPE_NUMERICAL_ERR:
+ hbl_ibdev_dbg(&hdev->ibdev, "Port %u: got numerical error on QP %u\n",
+ port, eq_poll_out.idx);
+
+ found_qp = hbl_ib_dispatch_event_qp(hdev, hctx, port, eq_poll_out.idx,
+ IB_EVENT_PATH_MIG_ERR, 0);
+
+ if (!found_qp)
+ hbl_ibdev_err(&hdev->ibdev,
+ "port %d qp %d - received numerical error event, but QP is not allocated\n",
+ port, eq_poll_out.idx);
+ break;
+ case HBL_CNI_EQ_EVENT_TYPE_LINK_STATUS:
+ hbl_ibdev_dbg(&hdev->ibdev, "port %d link %s\n", port,
+ eq_poll_out.ev_data ? "up" : "down");
+
+ ibev.event = eq_poll_out.ev_data ?
+ IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
+ ibev.element.port_num = port;
+ ib_dispatch_event(&ibev);
+ break;
+ case HBL_CNI_EQ_EVENT_TYPE_QP_ALIGN_COUNTERS:
+ hbl_ibdev_dbg(&hdev->ibdev,
+ "port %d qp %d - Align QP counters on QP timeout\n", port,
+ eq_poll_out.idx);
+
+ found_qp = hbl_ib_dispatch_event_qp(hdev, hctx, port, eq_poll_out.idx,
+ IB_EVENT_QP_LAST_WQE_REACHED, 0);
+
+ if (!found_qp)
+ hbl_ibdev_err(&hdev->ibdev,
+ "port %d qp %d - received Align QP counters event, but QP is not allocated\n",
+ port, eq_poll_out.idx);
+ break;
+ default:
+ hbl_ibdev_dbg(&hdev->ibdev, "port %d EQ poll success, event %d\n", port,
+ eq_poll_out.ev_type);
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+const struct ib_device_ops hbl_ib_dev_ops = {
+ .owner = THIS_MODULE,
+ .driver_id = RDMA_DRIVER_HBL,
+ .uverbs_abi_ver = HBL_IB_UVERBS_ABI_VERSION,
+
+ .add_gid = hbl_ib_add_gid,
+ .del_gid = hbl_ib_del_gid,
+ .alloc_hw_port_stats = hbl_ib_alloc_hw_port_stats,
+ .alloc_hw_device_stats = hbl_ib_alloc_hw_device_stats,
+ .alloc_pd = hbl_ib_alloc_pd,
+ .alloc_ucontext = hbl_ib_alloc_ucontext,
+ .create_cq = hbl_ib_create_cq,
+ .create_qp = hbl_ib_create_qp,
+ .dealloc_pd = hbl_ib_dealloc_pd,
+ .dealloc_ucontext = hbl_ib_dealloc_ucontext,
+ .dereg_mr = hbl_ib_dereg_mr,
+ .destroy_cq = hbl_ib_destroy_cq,
+ .destroy_qp = hbl_ib_destroy_qp,
+ .fill_res_qp_entry = hbl_ib_fill_res_qp_entry,
+ .get_hw_stats = hbl_ib_get_hw_stats,
+ .get_dev_fw_str = hbl_ib_get_dev_fw_str,
+ .get_link_layer = hbl_ib_port_link_layer,
+ .get_port_immutable = hbl_ib_get_port_immutable,
+ .mmap = hbl_ib_mmap,
+ .mmap_free = hbl_ib_mmap_free,
+ .modify_qp = hbl_ib_modify_qp,
+ .query_device = hbl_ib_query_device,
+ .query_gid = hbl_ib_query_gid,
+ .query_pkey = hbl_ib_query_pkey,
+ .query_port = hbl_ib_query_port,
+ .query_qp = hbl_ib_query_qp,
+ .reg_user_mr = hbl_ib_reg_mr,
+ .reg_user_mr_dmabuf = hbl_ib_reg_user_mr_dmabuf,
+
+ INIT_RDMA_OBJ_SIZE(ib_cq, hbl_ib_cq, ibcq),
+ INIT_RDMA_OBJ_SIZE(ib_pd, hbl_ib_pd, ibpd),
+ INIT_RDMA_OBJ_SIZE(ib_qp, hbl_ib_qp, ibqp),
+ INIT_RDMA_OBJ_SIZE(ib_ucontext, hbl_ib_ucontext, ibucontext),
+};
diff --git a/include/uapi/rdma/hbl-abi.h b/include/uapi/rdma/hbl-abi.h
new file mode 100644
index 000000000000..c545e07c9734
--- /dev/null
+++ b/include/uapi/rdma/hbl-abi.h
@@ -0,0 +1,204 @@
+/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) */
+/*
+ * Copyright 2022-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#ifndef HBL_IB_ABI_USER_H
+#define HBL_IB_ABI_USER_H
+
+#include <linux/types.h>
+
+/* Increment this value if any changes that break userspace ABI compatibility are made. */
+#define HBL_IB_UVERBS_ABI_VERSION 1
+
+#define HBL_IB_MTU_8192 6
+
+/**
+ * struct hbl_ibv_alloc_ucontext_req - Request udata for alloc ucontext.
+ * @ports_mask: Mask of ports associated with this context. 0 is for all available ports.
+ * @core_fd: Core device file descriptor.
+ * @use_dvs: Indicates if we're going to use our DVs.
+ */
+struct hbl_ibv_alloc_ucontext_req {
+ __aligned_u64 ports_mask;
+ __s32 core_fd;
+ __u8 use_dvs;
+ __u8 reserved[3];
+};
+
+/**
+ * enum hbl_ibv_ucontext_cap - Device capabilities.
+ * @HBL_UCONTEXT_CAP_MMAP_UMR: User memory region.
+ * @HBL_UCONTEXT_CAP_CC: Congestion control.
+ */
+enum hbl_ibv_ucontext_cap {
+ HBL_UCONTEXT_CAP_MMAP_UMR = 1 << 0,
+ HBL_UCONTEXT_CAP_CC = 1 << 1,
+};
+
+/**
+ * struct hbl_ibv_alloc_ucontext_resp - Response udata for alloc ucontext.
+ * @ports_mask: Mask of ports associated with this context.
+ * @cap_mask: Capabilities mask.
+ */
+struct hbl_ibv_alloc_ucontext_resp {
+ __aligned_u64 ports_mask;
+ __aligned_u64 cap_mask;
+};
+
+/**
+ * struct hbl_ibv_alloc_pd_resp - Response udata for alloc PD.
+ * @pdn: PD number.
+ */
+struct hbl_ibv_alloc_pd_resp {
+ __u32 pdn;
+ __u32 reserved;
+};
+
+/**
+ * enum hbl_ibv_qp_wq_types - QP WQ types.
+ * @HBL_WQ_WRITE: WRITE or "native" SEND operations are allowed on this QP.
+ * NOTE: the last is not supported!
+ * @HBL_WQ_RECV_RDV: RECEIVE-RDV or WRITE operations are allowed on this QP.
+ * NOTE: posting all operations at the same time is not supported!
+ * @HBL_WQ_READ_RDV: READ-RDV or WRITE operations are allowed on this QP.
+ * NOTE: posting all operations at the same time is not supported!
+ * @HBL_WQ_SEND_RDV: SEND-RDV operation is allowed on this QP.
+ * @HBL_WQ_READ_RDV_ENDP: No operation is allowed on this endpoint QP!
+ */
+enum hbl_ibv_qp_wq_types {
+ HBL_WQ_WRITE = 0x1,
+ HBL_WQ_RECV_RDV = 0x2,
+ HBL_WQ_READ_RDV = 0x4,
+ HBL_WQ_SEND_RDV = 0x8,
+ HBL_WQ_READ_RDV_ENDP = 0x10,
+};
+
+/**
+ * struct hbl_ibv_modify_qp_req - Request udata for modify QP.
+ * @local_key: Unique key for local memory access.
+ * @remote_key: Unique key for remote memory access.
+ * @congestion_wnd: Congestion-Window size.
+ * @dest_wq_size: Number of WQEs on the destination.
+ * @priority: Requester/responder QP priority.
+ * @wq_type: WQ type. e.g. write, rdv etc
+ * @loopback: QP loopback enable/disable.
+ * @congestion_en: Congestion-control enable/disable.
+ * @compression_en: Compression enable/disable.
+ * @encap_en: Encapsulation enable flag.
+ * @encap_num: Encapsulation number.
+ * @wq_granularity: WQ granularity [0 for 32B or 1 for 64B].
+ */
+struct hbl_ibv_modify_qp_req {
+ __u32 local_key;
+ __u32 remote_key;
+ __u32 congestion_wnd;
+ __u32 reserved0;
+ __u32 dest_wq_size;
+ __u8 priority;
+ __u8 wq_type;
+ __u8 loopback;
+ __u8 congestion_en;
+ __u8 reserved1;
+ __u8 reserved2;
+ __u8 compression_en;
+ __u8 reserved3;
+ __u8 encap_en;
+ __u8 encap_num;
+ __u8 reserved4;
+ __u8 wq_granularity;
+ __u8 reserved5;
+ __u8 reserved6[5];
+};
+
+/**
+ * struct hbl_ibv_modify_qp_resp - Response udata for modify QP.
+ * @swq_mem_handle: Send WQ mmap handle.
+ * @rwq_mem_handle: Receive WQ mmap handle.
+ * @swq_mem_size: Send WQ mmap size.
+ * @rwq_mem_size: Receive WQ mmap size.
+ * @qp_num: HBL QP num.
+ */
+struct hbl_ibv_modify_qp_resp {
+ __aligned_u64 swq_mem_handle;
+ __aligned_u64 rwq_mem_handle;
+ __u32 swq_mem_size;
+ __u32 rwq_mem_size;
+ __u32 qp_num;
+ __u32 reserved;
+};
+
+/**
+ * enum hbl_ibv_cq_type - CQ types, used during allocation of CQs.
+ * @HBL_CQ_TYPE_QP: Standard CQ used for completion of a operation for a QP.
+ * @HBL_CQ_TYPE_CC: Congestion control CQ.
+ */
+enum hbl_ibv_cq_type {
+ HBL_CQ_TYPE_QP,
+ HBL_CQ_TYPE_CC,
+};
+
+/**
+ * hbl_ibv_cq_req_flags - CQ req flag used for distinguision between CQ based on attributes.
+ * @CQ_FLAG_NATIVE: Bit 1 is set, it represents the CQ is called for native create CQ.
+ */
+enum hbl_ibv_cq_req_flags {
+ CQ_FLAG_NATIVE = 1 << 0,
+};
+
+/**
+ * struct hbl_ibv_create_cq_req - Request udata for create CQ.
+ * @port_num: IB Port number.
+ * @cq_type: Type of CQ resource as mentioned in hbl_ibv_cq_type.
+ * @flags: CQ req flag used for cq attributes.
+ */
+struct hbl_ibv_create_cq_req {
+ __u32 port_num;
+ __u8 cq_type;
+ __u8 flags;
+ __u8 reserved[2];
+};
+
+/**
+ * struct hbl_ibv_port_create_cq_resp - Response udata for create CQ.
+ * @mem_handle: Handle for the CQ buffer.
+ * @pi_handle: Handle for the Pi memory.
+ * @regs_handle: Handle for the CQ UMR register.
+ * @regs_offset: Register offset of CQ UMR register.
+ * @cq_num: CQ number that is allocated.
+ * @cq_size: Size of the CQ.
+ */
+struct hbl_ibv_port_create_cq_resp {
+ __aligned_u64 mem_handle;
+ __aligned_u64 pi_handle;
+ __aligned_u64 regs_handle;
+ __u32 regs_offset;
+ __u32 cq_num;
+ __u32 cq_size;
+ __u32 reserved;
+};
+
+/**
+ * struct hbl_ibv_create_cq_resp - Response udata for create CQ.
+ * @mem_handle: Handle for the CQ buffer.
+ * @pi_handle: Handle for the Pi memory.
+ * @regs_handle: Handle for the CQ UMR register.
+ * @regs_offset: Register offset of CQ UMR register.
+ * @cq_num: CQ number that is allocated.
+ * @cq_size: Size of the CQ.
+ * @port_cq_resp: response data for create CQ per port.
+ */
+struct hbl_ibv_create_cq_resp {
+ __aligned_u64 mem_handle;
+ __aligned_u64 pi_handle;
+ __aligned_u64 regs_handle;
+ __u32 regs_offset;
+ __u32 cq_num;
+ __u32 cq_size;
+ __u32 reserved;
+ struct hbl_ibv_port_create_cq_resp port_cq_resp[];
+};
+
+#endif /* HBL_IB_ABI_USER_H */
diff --git a/include/uapi/rdma/hbl_user_ioctl_cmds.h b/include/uapi/rdma/hbl_user_ioctl_cmds.h
new file mode 100644
index 000000000000..7ac2bf116385
--- /dev/null
+++ b/include/uapi/rdma/hbl_user_ioctl_cmds.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) */
+/*
+ * Copyright 2022-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#ifndef HBL_IB_USER_IOCTL_CMDS_H
+#define HBL_IB_USER_IOCTL_CMDS_H
+
+#include <linux/types.h>
+#include <rdma/ib_user_ioctl_cmds.h>
+
+enum hbl_ib_objects {
+ HBL_IB_OBJECT_USR_FIFO = (1U << UVERBS_ID_NS_SHIFT),
+ HBL_IB_OBJECT_SET_PORT_EX,
+ HBL_IB_OBJECT_QUERY_PORT,
+ HBL_IB_OBJECT_RESERVED,
+ HBL_IB_OBJECT_ENCAP,
+};
+
+enum hbl_ib_usr_fifo_obj_methods {
+ HBL_IB_METHOD_USR_FIFO_OBJ_CREATE = (1U << UVERBS_ID_NS_SHIFT),
+ HBL_IB_METHOD_USR_FIFO_OBJ_DESTROY,
+};
+
+enum hbl_ib_usr_fifo_create_attrs {
+ HBL_IB_ATTR_USR_FIFO_CREATE_IN = (1U << UVERBS_ID_NS_SHIFT),
+ HBL_IB_ATTR_USR_FIFO_CREATE_OUT,
+ HBL_IB_ATTR_USR_FIFO_CREATE_HANDLE,
+};
+
+enum hbl_ib_usr_fifo_destroy_attrs {
+ HBL_IB_ATTR_USR_FIFO_DESTROY_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
+};
+
+enum hbl_ib_device_methods {
+ HBL_IB_METHOD_SET_PORT_EX = (1U << UVERBS_ID_NS_SHIFT),
+ HBL_IB_METHOD_QUERY_PORT,
+};
+
+enum hbl_ib_set_port_ex_attrs {
+ HBL_IB_ATTR_SET_PORT_EX_IN = (1U << UVERBS_ID_NS_SHIFT),
+};
+
+enum hbl_ib_query_port_attrs {
+ HBL_IB_ATTR_QUERY_PORT_IN = (1U << UVERBS_ID_NS_SHIFT),
+ HBL_IB_ATTR_QUERY_PORT_OUT,
+};
+
+enum hbl_ib_encap_methods {
+ HBL_IB_METHOD_ENCAP_CREATE = (1U << UVERBS_ID_NS_SHIFT),
+ HBL_IB_METHOD_ENCAP_DESTROY,
+};
+
+enum hbl_ib_encap_create_attrs {
+ HBL_IB_ATTR_ENCAP_CREATE_IN = (1U << UVERBS_ID_NS_SHIFT),
+ HBL_IB_ATTR_ENCAP_CREATE_OUT,
+ HBL_IB_ATTR_ENCAP_CREATE_HANDLE,
+};
+
+enum hbl_ib_encap_destroy_attrs {
+ HBL_IB_ATTR_ENCAP_DESTROY_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
+};
+
+#endif /* HBL_IB_USER_IOCTL_CMDS_H */
diff --git a/include/uapi/rdma/hbl_user_ioctl_verbs.h b/include/uapi/rdma/hbl_user_ioctl_verbs.h
new file mode 100644
index 000000000000..ce896f5c58ba
--- /dev/null
+++ b/include/uapi/rdma/hbl_user_ioctl_verbs.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) */
+/*
+ * Copyright 2022-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#ifndef HBL_IB_USER_IOCTL_VERBS_H
+#define HBL_IB_USER_IOCTL_VERBS_H
+
+#include <linux/types.h>
+
+#define HBL_IB_MAX_BP_OFFS 16
+
+enum hbl_ib_wq_array_type {
+ HBL_IB_WQ_ARRAY_TYPE_GENERIC,
+ HBL_IB_WQ_ARRAY_TYPE_RESERVED1,
+ HBL_IB_WQ_ARRAY_TYPE_RESERVED2,
+ HBL_IB_WQ_ARRAY_TYPE_RESERVED3,
+ HBL_IB_WQ_ARRAY_TYPE_RESERVED4,
+ HBL_IB_WQ_ARRAY_TYPE_MAX,
+};
+
+struct hbl_wq_array_attr {
+ __u32 max_num_of_wqs;
+ __u32 max_num_of_wqes_in_wq;
+ __u8 mem_id;
+ __u8 swq_granularity;
+ __u8 reserved0[6];
+ __aligned_u64 reserved1[2];
+};
+
+struct hbl_uapi_usr_fifo_create_in {
+ __u32 port_num;
+ __u32 reserved0;
+ __u32 reserved1;
+ __u32 usr_fifo_num_hint;
+ __u8 mode;
+ __u8 reserved2;
+ __u8 reserved3[6];
+};
+
+struct hbl_uapi_usr_fifo_create_out {
+ __aligned_u64 ci_handle;
+ __aligned_u64 regs_handle;
+ __u32 usr_fifo_num;
+ __u32 regs_offset;
+ __u32 size;
+ __u32 bp_thresh;
+};
+
+struct hbl_uapi_set_port_ex_in {
+ struct hbl_wq_array_attr wq_arr_attr[HBL_IB_WQ_ARRAY_TYPE_MAX];
+ /* Pointer to u32 array */
+ __aligned_u64 qp_wq_bp_offs;
+ __u32 qp_wq_bp_offs_cnt;
+ __u32 port_num;
+ __aligned_u64 reserved0;
+ __u32 reserved1;
+ __u8 reserved2;
+ __u8 advanced;
+ __u8 adaptive_timeout_en;
+ __u8 reserved3;
+};
+
+struct hbl_uapi_query_port_in {
+ __u32 port_num;
+ __u32 reserved;
+};
+
+struct hbl_uapi_query_port_out {
+ __u32 max_num_of_qps;
+ __u32 num_allocated_qps;
+ __u32 max_allocated_qp_num;
+ __u32 max_cq_size;
+ __u32 reserved0;
+ __u32 reserved1;
+ __u32 reserved2;
+ __u32 reserved3;
+ __u32 reserved4;
+ __u8 advanced;
+ __u8 max_num_of_cqs;
+ __u8 max_num_of_usr_fifos;
+ __u8 max_num_of_encaps;
+ __u8 nic_macro_idx;
+ __u8 nic_phys_port_idx;
+ __u8 reserved[6];
+};
+
+struct hbl_uapi_encap_create_in {
+ __aligned_u64 tnl_hdr_ptr;
+ __u32 tnl_hdr_size;
+ __u32 port_num;
+ __u32 ipv4_addr;
+ __u16 udp_dst_port;
+ __u16 ip_proto;
+ __u8 encap_type;
+ __u8 reserved[7];
+};
+
+struct hbl_uapi_encap_create_out {
+ __u32 encap_num;
+ __u32 reserved;
+};
+
+#endif /* HBL_IB_USER_IOCTL_VERBS_H */
diff --git a/include/uapi/rdma/ib_user_ioctl_verbs.h b/include/uapi/rdma/ib_user_ioctl_verbs.h
index fe15bc7e9f70..016ac5c8fdea 100644
--- a/include/uapi/rdma/ib_user_ioctl_verbs.h
+++ b/include/uapi/rdma/ib_user_ioctl_verbs.h
@@ -255,6 +255,7 @@ enum rdma_driver_id {
RDMA_DRIVER_SIW,
RDMA_DRIVER_ERDMA,
RDMA_DRIVER_MANA,
+ RDMA_DRIVER_HBL,
};
enum ib_uverbs_gid_type {
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-13 8:22 ` [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver Omer Shpigelman
@ 2024-06-13 19:18 ` Leon Romanovsky
2024-06-17 17:43 ` Omer Shpigelman
2024-06-17 14:17 ` Jason Gunthorpe
1 sibling, 1 reply; 108+ messages in thread
From: Leon Romanovsky @ 2024-06-13 19:18 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel, linux-rdma, netdev, dri-devel, ogabbay, zyehudai
On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
> Add an RDMA driver of Gaudi ASICs family for AI scaling.
> The driver itself is agnostic to the ASIC in action, it operates according
> to the capabilities that were passed on device initialization.
> The device is initialized by the hbl_cn driver via auxiliary bus.
> The driver also supports QP resource tracking and port/device HW counters.
>
> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> Co-developed-by: David Meriin <dmeriin@habana.ai>
> Signed-off-by: David Meriin <dmeriin@habana.ai>
> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
I afraid that you misinterpreted the "Co-developed-by" tag. All these
people are probably touch the code and not actually sit together at
the same room and write the code together. So, please remove the
extensive "Co-developed-by" tags.
It is not full review yet, but simple pass-by-comments.
> ---
> MAINTAINERS | 10 +
> drivers/infiniband/Kconfig | 1 +
> drivers/infiniband/hw/Makefile | 1 +
> drivers/infiniband/hw/hbl/Kconfig | 17 +
> drivers/infiniband/hw/hbl/Makefile | 8 +
> drivers/infiniband/hw/hbl/hbl.h | 326 +++
> drivers/infiniband/hw/hbl/hbl_main.c | 478 ++++
> drivers/infiniband/hw/hbl/hbl_verbs.c | 2686 ++++++++++++++++++++++
> include/uapi/rdma/hbl-abi.h | 204 ++
> include/uapi/rdma/hbl_user_ioctl_cmds.h | 66 +
> include/uapi/rdma/hbl_user_ioctl_verbs.h | 106 +
> include/uapi/rdma/ib_user_ioctl_verbs.h | 1 +
> 12 files changed, 3904 insertions(+)
> create mode 100644 drivers/infiniband/hw/hbl/Kconfig
> create mode 100644 drivers/infiniband/hw/hbl/Makefile
> create mode 100644 drivers/infiniband/hw/hbl/hbl.h
> create mode 100644 drivers/infiniband/hw/hbl/hbl_main.c
> create mode 100644 drivers/infiniband/hw/hbl/hbl_verbs.c
> create mode 100644 include/uapi/rdma/hbl-abi.h
> create mode 100644 include/uapi/rdma/hbl_user_ioctl_cmds.h
> create mode 100644 include/uapi/rdma/hbl_user_ioctl_verbs.h
<...>
> +#define hbl_ibdev_emerg(ibdev, format, ...) ibdev_emerg(ibdev, format, ##__VA_ARGS__)
> +#define hbl_ibdev_alert(ibdev, format, ...) ibdev_alert(ibdev, format, ##__VA_ARGS__)
> +#define hbl_ibdev_crit(ibdev, format, ...) ibdev_crit(ibdev, format, ##__VA_ARGS__)
> +#define hbl_ibdev_err(ibdev, format, ...) ibdev_err(ibdev, format, ##__VA_ARGS__)
> +#define hbl_ibdev_warn(ibdev, format, ...) ibdev_warn(ibdev, format, ##__VA_ARGS__)
> +#define hbl_ibdev_notice(ibdev, format, ...) ibdev_notice(ibdev, format, ##__VA_ARGS__)
> +#define hbl_ibdev_info(ibdev, format, ...) ibdev_info(ibdev, format, ##__VA_ARGS__)
> +#define hbl_ibdev_dbg(ibdev, format, ...) ibdev_dbg(ibdev, format, ##__VA_ARGS__)
> +
> +#define hbl_ibdev_emerg_ratelimited(ibdev, fmt, ...) \
> + ibdev_emerg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> +#define hbl_ibdev_alert_ratelimited(ibdev, fmt, ...) \
> + ibdev_alert_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> +#define hbl_ibdev_crit_ratelimited(ibdev, fmt, ...) \
> + ibdev_crit_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> +#define hbl_ibdev_err_ratelimited(ibdev, fmt, ...) \
> + ibdev_err_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> +#define hbl_ibdev_warn_ratelimited(ibdev, fmt, ...) \
> + ibdev_warn_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> +#define hbl_ibdev_notice_ratelimited(ibdev, fmt, ...) \
> + ibdev_notice_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> +#define hbl_ibdev_info_ratelimited(ibdev, fmt, ...) \
> + ibdev_info_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> +#define hbl_ibdev_dbg_ratelimited(ibdev, fmt, ...) \
> + ibdev_dbg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> +
Please don't redefine the existing macros. Just use the existing ones.
<...>
> + if (hbl_ib_match_netdev(ibdev, netdev))
> + ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
> + else
> + return NOTIFY_DONE;
It is not kernel coding style. Please write:
if (!hbl_ib_match_netdev(ibdev, netdev))
return NOTIFY_DONE;
ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
> +
<...>
> +static int hbl_ib_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
> +{
> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
> + struct hbl_ib_aux_ops *aux_ops = aux_dev->aux_ops;
> + struct hbl_ib_device *hdev;
> + ktime_t timeout;
> + int rc;
> +
> + rc = hdev_init(aux_dev);
> + if (rc) {
> + dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
> + return -EIO;
> + }
> +
> + hdev = aux_dev->priv;
> +
> + /* don't allow module unloading while it is attached */
> + if (!try_module_get(THIS_MODULE)) {
This part makes wonder, what are you trying to do here? What doesn't work for you
in standard driver core and module load mechanism?
> + dev_err(hdev->dev, "Failed to increment %s module refcount\n",
> + module_name(THIS_MODULE));
> + rc = -EIO;
> + goto module_get_err;
> + }
> +
> + timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
> + while (1) {
> + aux_ops->hw_access_lock(aux_dev);
> +
> + /* if the device is operational, proceed to actual init while holding the lock in
> + * order to prevent concurrent hard reset
> + */
> + if (aux_ops->device_operational(aux_dev))
> + break;
> +
> + aux_ops->hw_access_unlock(aux_dev);
> +
> + if (ktime_compare(ktime_get(), timeout) > 0) {
> + dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
> + rc = -EBUSY;
> + goto timeout_err;
> + }
> +
> + dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing IB\n");
> +
> + msleep_interruptible(MSEC_PER_SEC);
> + }
The code above is unexpected.
> +
> + rc = hbl_ib_dev_init(hdev);
> + if (rc) {
> + dev_err(hdev->dev, "Failed to init ib device\n");
> + goto dev_init_err;
> + }
> +
> + aux_ops->hw_access_unlock(aux_dev);
> +
> + return 0;
> +
> +dev_init_err:
> + aux_ops->hw_access_unlock(aux_dev);
> +timeout_err:
> + module_put(THIS_MODULE);
> +module_get_err:
> + hdev_fini(aux_dev);
> +
> + return rc;
> +}
<...>
> +static int __init hbl_ib_init(void)
> +{
> + pr_info("loading driver\n");
Please remove all these debug prints and leave only the necessary ones.
> +
> + return auxiliary_driver_register(&hbl_ib_driver);
> +}
> +
> +static void __exit hbl_ib_exit(void)
> +{
> + auxiliary_driver_unregister(&hbl_ib_driver);
> +
> + pr_info("driver removed\n");
> +}
> +
> +module_init(hbl_ib_init);
> +module_exit(hbl_ib_exit)
Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-13 19:18 ` Leon Romanovsky
@ 2024-06-17 17:43 ` Omer Shpigelman
2024-06-17 19:04 ` Leon Romanovsky
0 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-17 17:43 UTC (permalink / raw)
To: Leon Romanovsky
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/13/24 22:18, Leon Romanovsky wrote:
> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
>> Add an RDMA driver of Gaudi ASICs family for AI scaling.
>> The driver itself is agnostic to the ASIC in action, it operates according
>> to the capabilities that were passed on device initialization.
>> The device is initialized by the hbl_cn driver via auxiliary bus.
>> The driver also supports QP resource tracking and port/device HW counters.
>>
>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
>> Co-developed-by: David Meriin <dmeriin@habana.ai>
>> Signed-off-by: David Meriin <dmeriin@habana.ai>
>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
>
> I afraid that you misinterpreted the "Co-developed-by" tag. All these
> people are probably touch the code and not actually sit together at
> the same room and write the code together. So, please remove the
> extensive "Co-developed-by" tags.
>
> It is not full review yet, but simple pass-by-comments.
>
Actually except of two, all of the mentioned persons sat in the same room
and developed the code together.
The remaining two are located on a different site (but also together).
Isn't that what "Co-developed-by" tag for?
I wanted to give them credit for writing the code but I can remove if it's
not common.
>> ---
>> MAINTAINERS | 10 +
>> drivers/infiniband/Kconfig | 1 +
>> drivers/infiniband/hw/Makefile | 1 +
>> drivers/infiniband/hw/hbl/Kconfig | 17 +
>> drivers/infiniband/hw/hbl/Makefile | 8 +
>> drivers/infiniband/hw/hbl/hbl.h | 326 +++
>> drivers/infiniband/hw/hbl/hbl_main.c | 478 ++++
>> drivers/infiniband/hw/hbl/hbl_verbs.c | 2686 ++++++++++++++++++++++
>> include/uapi/rdma/hbl-abi.h | 204 ++
>> include/uapi/rdma/hbl_user_ioctl_cmds.h | 66 +
>> include/uapi/rdma/hbl_user_ioctl_verbs.h | 106 +
>> include/uapi/rdma/ib_user_ioctl_verbs.h | 1 +
>> 12 files changed, 3904 insertions(+)
>> create mode 100644 drivers/infiniband/hw/hbl/Kconfig
>> create mode 100644 drivers/infiniband/hw/hbl/Makefile
>> create mode 100644 drivers/infiniband/hw/hbl/hbl.h
>> create mode 100644 drivers/infiniband/hw/hbl/hbl_main.c
>> create mode 100644 drivers/infiniband/hw/hbl/hbl_verbs.c
>> create mode 100644 include/uapi/rdma/hbl-abi.h
>> create mode 100644 include/uapi/rdma/hbl_user_ioctl_cmds.h
>> create mode 100644 include/uapi/rdma/hbl_user_ioctl_verbs.h
>
> <...>
>
>> +#define hbl_ibdev_emerg(ibdev, format, ...) ibdev_emerg(ibdev, format, ##__VA_ARGS__)
>> +#define hbl_ibdev_alert(ibdev, format, ...) ibdev_alert(ibdev, format, ##__VA_ARGS__)
>> +#define hbl_ibdev_crit(ibdev, format, ...) ibdev_crit(ibdev, format, ##__VA_ARGS__)
>> +#define hbl_ibdev_err(ibdev, format, ...) ibdev_err(ibdev, format, ##__VA_ARGS__)
>> +#define hbl_ibdev_warn(ibdev, format, ...) ibdev_warn(ibdev, format, ##__VA_ARGS__)
>> +#define hbl_ibdev_notice(ibdev, format, ...) ibdev_notice(ibdev, format, ##__VA_ARGS__)
>> +#define hbl_ibdev_info(ibdev, format, ...) ibdev_info(ibdev, format, ##__VA_ARGS__)
>> +#define hbl_ibdev_dbg(ibdev, format, ...) ibdev_dbg(ibdev, format, ##__VA_ARGS__)
>> +
>> +#define hbl_ibdev_emerg_ratelimited(ibdev, fmt, ...) \
>> + ibdev_emerg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>> +#define hbl_ibdev_alert_ratelimited(ibdev, fmt, ...) \
>> + ibdev_alert_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>> +#define hbl_ibdev_crit_ratelimited(ibdev, fmt, ...) \
>> + ibdev_crit_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>> +#define hbl_ibdev_err_ratelimited(ibdev, fmt, ...) \
>> + ibdev_err_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>> +#define hbl_ibdev_warn_ratelimited(ibdev, fmt, ...) \
>> + ibdev_warn_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>> +#define hbl_ibdev_notice_ratelimited(ibdev, fmt, ...) \
>> + ibdev_notice_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>> +#define hbl_ibdev_info_ratelimited(ibdev, fmt, ...) \
>> + ibdev_info_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>> +#define hbl_ibdev_dbg_ratelimited(ibdev, fmt, ...) \
>> + ibdev_dbg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>> +
>
> Please don't redefine the existing macros. Just use the existing ones.
>
>
> <...>
>
That's a leftover from some debug code. I'll remove.
>> + if (hbl_ib_match_netdev(ibdev, netdev))
>> + ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
>> + else
>> + return NOTIFY_DONE;
>
> It is not kernel coding style. Please write:
> if (!hbl_ib_match_netdev(ibdev, netdev))
> return NOTIFY_DONE;
>
> ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
>
I'll fix the code, thanks.
>> +
>
> <...>
>
>> +static int hbl_ib_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
>> +{
>> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
>> + struct hbl_ib_aux_ops *aux_ops = aux_dev->aux_ops;
>> + struct hbl_ib_device *hdev;
>> + ktime_t timeout;
>> + int rc;
>> +
>> + rc = hdev_init(aux_dev);
>> + if (rc) {
>> + dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
>> + return -EIO;
>> + }
>> +
>> + hdev = aux_dev->priv;
>> +
>> + /* don't allow module unloading while it is attached */
>> + if (!try_module_get(THIS_MODULE)) {
>
> This part makes wonder, what are you trying to do here? What doesn't work for you
> in standard driver core and module load mechanism?
>
Before auxiliary bus was introduced, we used EXPORT_SYMBOLs for inter
driver communication. That incremented the refcount of the used module so
it couldn't be removed while it is in use.
Auxiliary bus usage doesn't increment the used module refcount and hence
the used module can be removed while it is in use and that's something
we don't want to allow.
We could solve it by some global locking or in_use atomic but the most
simple and clean way is just to increment the used module refcount on
auxiliary device probe and decrement it on auxiliary device removal.
>> + dev_err(hdev->dev, "Failed to increment %s module refcount\n",
>> + module_name(THIS_MODULE));
>> + rc = -EIO;
>> + goto module_get_err;
>> + }
>> +
>> + timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
>> + while (1) {
>> + aux_ops->hw_access_lock(aux_dev);
>> +
>> + /* if the device is operational, proceed to actual init while holding the lock in
>> + * order to prevent concurrent hard reset
>> + */
>> + if (aux_ops->device_operational(aux_dev))
>> + break;
>> +
>> + aux_ops->hw_access_unlock(aux_dev);
>> +
>> + if (ktime_compare(ktime_get(), timeout) > 0) {
>> + dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
>> + rc = -EBUSY;
>> + goto timeout_err;
>> + }
>> +
>> + dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing IB\n");
>> +
>> + msleep_interruptible(MSEC_PER_SEC);
>> + }
>
> The code above is unexpected.
>
We have no control on when the user insmod the IB driver. As a result it
is possible that the IB auxiliary device will be probed while the compute
device is under reset (due to some HW error). During device reset we must
not access the HW. We should wait for the compute device to finish the
reset flow before we continue with the IB device probe and block any
compute device reset flow meanwhile.
>> +
>> + rc = hbl_ib_dev_init(hdev);
>> + if (rc) {
>> + dev_err(hdev->dev, "Failed to init ib device\n");
>> + goto dev_init_err;
>> + }
>> +
>> + aux_ops->hw_access_unlock(aux_dev);
>> +
>> + return 0;
>> +
>> +dev_init_err:
>> + aux_ops->hw_access_unlock(aux_dev);
>> +timeout_err:
>> + module_put(THIS_MODULE);
>> +module_get_err:
>> + hdev_fini(aux_dev);
>> +
>> + return rc;
>> +}
>
> <...>
>
>> +static int __init hbl_ib_init(void)
>> +{
>> + pr_info("loading driver\n");
>
> Please remove all these debug prints and leave only the necessary ones.
>
Sure, will remove.
>> +
>> + return auxiliary_driver_register(&hbl_ib_driver);
>> +}
>> +
>> +static void __exit hbl_ib_exit(void)
>> +{
>> + auxiliary_driver_unregister(&hbl_ib_driver);
>> +
>> + pr_info("driver removed\n");
>> +}
>> +
>> +module_init(hbl_ib_init);
>> +module_exit(hbl_ib_exit)
>
> Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-17 17:43 ` Omer Shpigelman
@ 2024-06-17 19:04 ` Leon Romanovsky
2024-06-18 11:08 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Leon Romanovsky @ 2024-06-17 19:04 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On Mon, Jun 17, 2024 at 05:43:49PM +0000, Omer Shpigelman wrote:
> On 6/13/24 22:18, Leon Romanovsky wrote:
> > [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
> >> Add an RDMA driver of Gaudi ASICs family for AI scaling.
> >> The driver itself is agnostic to the ASIC in action, it operates according
> >> to the capabilities that were passed on device initialization.
> >> The device is initialized by the hbl_cn driver via auxiliary bus.
> >> The driver also supports QP resource tracking and port/device HW counters.
> >>
> >> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> >> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> >> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> >> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> >> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> >> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> >> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> >> Co-developed-by: David Meriin <dmeriin@habana.ai>
> >> Signed-off-by: David Meriin <dmeriin@habana.ai>
> >> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> >> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> >> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> >> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
> >
> > I afraid that you misinterpreted the "Co-developed-by" tag. All these
> > people are probably touch the code and not actually sit together at
> > the same room and write the code together. So, please remove the
> > extensive "Co-developed-by" tags.
> >
> > It is not full review yet, but simple pass-by-comments.
> >
>
> Actually except of two, all of the mentioned persons sat in the same room
> and developed the code together.
> The remaining two are located on a different site (but also together).
> Isn't that what "Co-developed-by" tag for?
> I wanted to give them credit for writing the code but I can remove if it's
> not common.
Signed-off-by will be enough to give them credit.
>
> >> ---
> >> MAINTAINERS | 10 +
> >> drivers/infiniband/Kconfig | 1 +
> >> drivers/infiniband/hw/Makefile | 1 +
> >> drivers/infiniband/hw/hbl/Kconfig | 17 +
> >> drivers/infiniband/hw/hbl/Makefile | 8 +
> >> drivers/infiniband/hw/hbl/hbl.h | 326 +++
> >> drivers/infiniband/hw/hbl/hbl_main.c | 478 ++++
> >> drivers/infiniband/hw/hbl/hbl_verbs.c | 2686 ++++++++++++++++++++++
> >> include/uapi/rdma/hbl-abi.h | 204 ++
> >> include/uapi/rdma/hbl_user_ioctl_cmds.h | 66 +
> >> include/uapi/rdma/hbl_user_ioctl_verbs.h | 106 +
> >> include/uapi/rdma/ib_user_ioctl_verbs.h | 1 +
> >> 12 files changed, 3904 insertions(+)
> >> create mode 100644 drivers/infiniband/hw/hbl/Kconfig
> >> create mode 100644 drivers/infiniband/hw/hbl/Makefile
> >> create mode 100644 drivers/infiniband/hw/hbl/hbl.h
> >> create mode 100644 drivers/infiniband/hw/hbl/hbl_main.c
> >> create mode 100644 drivers/infiniband/hw/hbl/hbl_verbs.c
> >> create mode 100644 include/uapi/rdma/hbl-abi.h
> >> create mode 100644 include/uapi/rdma/hbl_user_ioctl_cmds.h
> >> create mode 100644 include/uapi/rdma/hbl_user_ioctl_verbs.h
> >
> > <...>
> >
> >> +#define hbl_ibdev_emerg(ibdev, format, ...) ibdev_emerg(ibdev, format, ##__VA_ARGS__)
> >> +#define hbl_ibdev_alert(ibdev, format, ...) ibdev_alert(ibdev, format, ##__VA_ARGS__)
> >> +#define hbl_ibdev_crit(ibdev, format, ...) ibdev_crit(ibdev, format, ##__VA_ARGS__)
> >> +#define hbl_ibdev_err(ibdev, format, ...) ibdev_err(ibdev, format, ##__VA_ARGS__)
> >> +#define hbl_ibdev_warn(ibdev, format, ...) ibdev_warn(ibdev, format, ##__VA_ARGS__)
> >> +#define hbl_ibdev_notice(ibdev, format, ...) ibdev_notice(ibdev, format, ##__VA_ARGS__)
> >> +#define hbl_ibdev_info(ibdev, format, ...) ibdev_info(ibdev, format, ##__VA_ARGS__)
> >> +#define hbl_ibdev_dbg(ibdev, format, ...) ibdev_dbg(ibdev, format, ##__VA_ARGS__)
> >> +
> >> +#define hbl_ibdev_emerg_ratelimited(ibdev, fmt, ...) \
> >> + ibdev_emerg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >> +#define hbl_ibdev_alert_ratelimited(ibdev, fmt, ...) \
> >> + ibdev_alert_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >> +#define hbl_ibdev_crit_ratelimited(ibdev, fmt, ...) \
> >> + ibdev_crit_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >> +#define hbl_ibdev_err_ratelimited(ibdev, fmt, ...) \
> >> + ibdev_err_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >> +#define hbl_ibdev_warn_ratelimited(ibdev, fmt, ...) \
> >> + ibdev_warn_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >> +#define hbl_ibdev_notice_ratelimited(ibdev, fmt, ...) \
> >> + ibdev_notice_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >> +#define hbl_ibdev_info_ratelimited(ibdev, fmt, ...) \
> >> + ibdev_info_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >> +#define hbl_ibdev_dbg_ratelimited(ibdev, fmt, ...) \
> >> + ibdev_dbg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >> +
> >
> > Please don't redefine the existing macros. Just use the existing ones.
> >
> >
> > <...>
> >
>
> That's a leftover from some debug code. I'll remove.
>
> >> + if (hbl_ib_match_netdev(ibdev, netdev))
> >> + ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
> >> + else
> >> + return NOTIFY_DONE;
> >
> > It is not kernel coding style. Please write:
> > if (!hbl_ib_match_netdev(ibdev, netdev))
> > return NOTIFY_DONE;
> >
> > ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
> >
>
> I'll fix the code, thanks.
>
> >> +
> >
> > <...>
> >
> >> +static int hbl_ib_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
> >> +{
> >> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
> >> + struct hbl_ib_aux_ops *aux_ops = aux_dev->aux_ops;
> >> + struct hbl_ib_device *hdev;
> >> + ktime_t timeout;
> >> + int rc;
> >> +
> >> + rc = hdev_init(aux_dev);
> >> + if (rc) {
> >> + dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
> >> + return -EIO;
> >> + }
> >> +
> >> + hdev = aux_dev->priv;
> >> +
> >> + /* don't allow module unloading while it is attached */
> >> + if (!try_module_get(THIS_MODULE)) {
> >
> > This part makes wonder, what are you trying to do here? What doesn't work for you
> > in standard driver core and module load mechanism?
> >
>
> Before auxiliary bus was introduced, we used EXPORT_SYMBOLs for inter
> driver communication. That incremented the refcount of the used module so
> it couldn't be removed while it is in use.
> Auxiliary bus usage doesn't increment the used module refcount and hence
> the used module can be removed while it is in use and that's something
> we don't want to allow.
> We could solve it by some global locking or in_use atomic but the most
> simple and clean way is just to increment the used module refcount on
> auxiliary device probe and decrement it on auxiliary device removal.
No, you was supposed to continue to use EXPORT_SYMBOLs and don't
invent auxiliary ops structure (this is why you lost module
reference counting).
>
> >> + dev_err(hdev->dev, "Failed to increment %s module refcount\n",
> >> + module_name(THIS_MODULE));
> >> + rc = -EIO;
> >> + goto module_get_err;
> >> + }
> >> +
> >> + timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
> >> + while (1) {
> >> + aux_ops->hw_access_lock(aux_dev);
> >> +
> >> + /* if the device is operational, proceed to actual init while holding the lock in
> >> + * order to prevent concurrent hard reset
> >> + */
> >> + if (aux_ops->device_operational(aux_dev))
> >> + break;
> >> +
> >> + aux_ops->hw_access_unlock(aux_dev);
> >> +
> >> + if (ktime_compare(ktime_get(), timeout) > 0) {
> >> + dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
> >> + rc = -EBUSY;
> >> + goto timeout_err;
> >> + }
> >> +
> >> + dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing IB\n");
> >> +
> >> + msleep_interruptible(MSEC_PER_SEC);
> >> + }
> >
> > The code above is unexpected.
> >
>
> We have no control on when the user insmod the IB driver.
It is not true, this is controlled through module dependencies
mechanism.
> As a result it is possible that the IB auxiliary device will be probed
> while the compute device is under reset (due to some HW error).
No, it is not possible. If you structure your driver right.
Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-17 19:04 ` Leon Romanovsky
@ 2024-06-18 11:08 ` Omer Shpigelman
2024-06-18 12:58 ` Leon Romanovsky
2024-06-18 16:01 ` Przemek Kitszel
0 siblings, 2 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-18 11:08 UTC (permalink / raw)
To: Leon Romanovsky
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/17/24 22:04, Leon Romanovsky wrote:
> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On Mon, Jun 17, 2024 at 05:43:49PM +0000, Omer Shpigelman wrote:
>> On 6/13/24 22:18, Leon Romanovsky wrote:
>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>
>>> On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
>>>> Add an RDMA driver of Gaudi ASICs family for AI scaling.
>>>> The driver itself is agnostic to the ASIC in action, it operates according
>>>> to the capabilities that were passed on device initialization.
>>>> The device is initialized by the hbl_cn driver via auxiliary bus.
>>>> The driver also supports QP resource tracking and port/device HW counters.
>>>>
>>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
>>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
>>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
>>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
>>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
>>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
>>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
>>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
>>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
>>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
>>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
>>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
>>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
>>>
>>> I afraid that you misinterpreted the "Co-developed-by" tag. All these
>>> people are probably touch the code and not actually sit together at
>>> the same room and write the code together. So, please remove the
>>> extensive "Co-developed-by" tags.
>>>
>>> It is not full review yet, but simple pass-by-comments.
>>>
>>
>> Actually except of two, all of the mentioned persons sat in the same room
>> and developed the code together.
>> The remaining two are located on a different site (but also together).
>> Isn't that what "Co-developed-by" tag for?
>> I wanted to give them credit for writing the code but I can remove if it's
>> not common.
>
> Signed-off-by will be enough to give them credit.
>
Ok, good enough.
>>
>>>> ---
>>>> MAINTAINERS | 10 +
>>>> drivers/infiniband/Kconfig | 1 +
>>>> drivers/infiniband/hw/Makefile | 1 +
>>>> drivers/infiniband/hw/hbl/Kconfig | 17 +
>>>> drivers/infiniband/hw/hbl/Makefile | 8 +
>>>> drivers/infiniband/hw/hbl/hbl.h | 326 +++
>>>> drivers/infiniband/hw/hbl/hbl_main.c | 478 ++++
>>>> drivers/infiniband/hw/hbl/hbl_verbs.c | 2686 ++++++++++++++++++++++
>>>> include/uapi/rdma/hbl-abi.h | 204 ++
>>>> include/uapi/rdma/hbl_user_ioctl_cmds.h | 66 +
>>>> include/uapi/rdma/hbl_user_ioctl_verbs.h | 106 +
>>>> include/uapi/rdma/ib_user_ioctl_verbs.h | 1 +
>>>> 12 files changed, 3904 insertions(+)
>>>> create mode 100644 drivers/infiniband/hw/hbl/Kconfig
>>>> create mode 100644 drivers/infiniband/hw/hbl/Makefile
>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl.h
>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl_main.c
>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl_verbs.c
>>>> create mode 100644 include/uapi/rdma/hbl-abi.h
>>>> create mode 100644 include/uapi/rdma/hbl_user_ioctl_cmds.h
>>>> create mode 100644 include/uapi/rdma/hbl_user_ioctl_verbs.h
>>>
>>> <...>
>>>
>>>> +#define hbl_ibdev_emerg(ibdev, format, ...) ibdev_emerg(ibdev, format, ##__VA_ARGS__)
>>>> +#define hbl_ibdev_alert(ibdev, format, ...) ibdev_alert(ibdev, format, ##__VA_ARGS__)
>>>> +#define hbl_ibdev_crit(ibdev, format, ...) ibdev_crit(ibdev, format, ##__VA_ARGS__)
>>>> +#define hbl_ibdev_err(ibdev, format, ...) ibdev_err(ibdev, format, ##__VA_ARGS__)
>>>> +#define hbl_ibdev_warn(ibdev, format, ...) ibdev_warn(ibdev, format, ##__VA_ARGS__)
>>>> +#define hbl_ibdev_notice(ibdev, format, ...) ibdev_notice(ibdev, format, ##__VA_ARGS__)
>>>> +#define hbl_ibdev_info(ibdev, format, ...) ibdev_info(ibdev, format, ##__VA_ARGS__)
>>>> +#define hbl_ibdev_dbg(ibdev, format, ...) ibdev_dbg(ibdev, format, ##__VA_ARGS__)
>>>> +
>>>> +#define hbl_ibdev_emerg_ratelimited(ibdev, fmt, ...) \
>>>> + ibdev_emerg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>> +#define hbl_ibdev_alert_ratelimited(ibdev, fmt, ...) \
>>>> + ibdev_alert_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>> +#define hbl_ibdev_crit_ratelimited(ibdev, fmt, ...) \
>>>> + ibdev_crit_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>> +#define hbl_ibdev_err_ratelimited(ibdev, fmt, ...) \
>>>> + ibdev_err_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>> +#define hbl_ibdev_warn_ratelimited(ibdev, fmt, ...) \
>>>> + ibdev_warn_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>> +#define hbl_ibdev_notice_ratelimited(ibdev, fmt, ...) \
>>>> + ibdev_notice_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>> +#define hbl_ibdev_info_ratelimited(ibdev, fmt, ...) \
>>>> + ibdev_info_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>> +#define hbl_ibdev_dbg_ratelimited(ibdev, fmt, ...) \
>>>> + ibdev_dbg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>> +
>>>
>>> Please don't redefine the existing macros. Just use the existing ones.
>>>
>>>
>>> <...>
>>>
>>
>> That's a leftover from some debug code. I'll remove.
>>
>>>> + if (hbl_ib_match_netdev(ibdev, netdev))
>>>> + ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
>>>> + else
>>>> + return NOTIFY_DONE;
>>>
>>> It is not kernel coding style. Please write:
>>> if (!hbl_ib_match_netdev(ibdev, netdev))
>>> return NOTIFY_DONE;
>>>
>>> ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
>>>
>>
>> I'll fix the code, thanks.
>>
>>>> +
>>>
>>> <...>
>>>
>>>> +static int hbl_ib_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
>>>> +{
>>>> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
>>>> + struct hbl_ib_aux_ops *aux_ops = aux_dev->aux_ops;
>>>> + struct hbl_ib_device *hdev;
>>>> + ktime_t timeout;
>>>> + int rc;
>>>> +
>>>> + rc = hdev_init(aux_dev);
>>>> + if (rc) {
>>>> + dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
>>>> + return -EIO;
>>>> + }
>>>> +
>>>> + hdev = aux_dev->priv;
>>>> +
>>>> + /* don't allow module unloading while it is attached */
>>>> + if (!try_module_get(THIS_MODULE)) {
>>>
>>> This part makes wonder, what are you trying to do here? What doesn't work for you
>>> in standard driver core and module load mechanism?
>>>
>>
>> Before auxiliary bus was introduced, we used EXPORT_SYMBOLs for inter
>> driver communication. That incremented the refcount of the used module so
>> it couldn't be removed while it is in use.
>> Auxiliary bus usage doesn't increment the used module refcount and hence
>> the used module can be removed while it is in use and that's something
>> we don't want to allow.
>> We could solve it by some global locking or in_use atomic but the most
>> simple and clean way is just to increment the used module refcount on
>> auxiliary device probe and decrement it on auxiliary device removal.
>
> No, you was supposed to continue to use EXPORT_SYMBOLs and don't
> invent auxiliary ops structure (this is why you lost module
> reference counting).
>
Sorry, but according to the auxiliary bus doc, a domain-specific ops
structure can be used.
We followed the usage example described at drivers/base/auxiliary.c.
What am I missing?
Moreover, we'd like to support the mode where the IB or the ETH driver is
not loaded at all. But this cannot be achieved if we use EXPORT_SYMBOLs
exclusively for inter driver communication.
>>
>>>> + dev_err(hdev->dev, "Failed to increment %s module refcount\n",
>>>> + module_name(THIS_MODULE));
>>>> + rc = -EIO;
>>>> + goto module_get_err;
>>>> + }
>>>> +
>>>> + timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
>>>> + while (1) {
>>>> + aux_ops->hw_access_lock(aux_dev);
>>>> +
>>>> + /* if the device is operational, proceed to actual init while holding the lock in
>>>> + * order to prevent concurrent hard reset
>>>> + */
>>>> + if (aux_ops->device_operational(aux_dev))
>>>> + break;
>>>> +
>>>> + aux_ops->hw_access_unlock(aux_dev);
>>>> +
>>>> + if (ktime_compare(ktime_get(), timeout) > 0) {
>>>> + dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
>>>> + rc = -EBUSY;
>>>> + goto timeout_err;
>>>> + }
>>>> +
>>>> + dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing IB\n");
>>>> +
>>>> + msleep_interruptible(MSEC_PER_SEC);
>>>> + }
>>>
>>> The code above is unexpected.
>>>
>>
>> We have no control on when the user insmod the IB driver.
>
> It is not true, this is controlled through module dependencies
> mechanism.
>
Yeah, if we would use EXPORT_SYMBOLs for inter driver communication but
we don't.
>> As a result it is possible that the IB auxiliary device will be probed
>> while the compute device is under reset (due to some HW error).
>
> No, it is not possible. If you structure your driver right.
>
Again, it is not possible if we would use EXPORT_SYMBOLs.
Please let me know if we misunderstood something because AFAIU we followed
the auxiliary bus doc usage example.
> Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-18 11:08 ` Omer Shpigelman
@ 2024-06-18 12:58 ` Leon Romanovsky
2024-06-19 9:27 ` Omer Shpigelman
2024-06-18 16:01 ` Przemek Kitszel
1 sibling, 1 reply; 108+ messages in thread
From: Leon Romanovsky @ 2024-06-18 12:58 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On Tue, Jun 18, 2024 at 11:08:34AM +0000, Omer Shpigelman wrote:
> On 6/17/24 22:04, Leon Romanovsky wrote:
> > [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > On Mon, Jun 17, 2024 at 05:43:49PM +0000, Omer Shpigelman wrote:
> >> On 6/13/24 22:18, Leon Romanovsky wrote:
> >>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >>>
> >>> On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
> >>>> Add an RDMA driver of Gaudi ASICs family for AI scaling.
> >>>> The driver itself is agnostic to the ASIC in action, it operates according
> >>>> to the capabilities that were passed on device initialization.
> >>>> The device is initialized by the hbl_cn driver via auxiliary bus.
> >>>> The driver also supports QP resource tracking and port/device HW counters.
> >>>>
> >>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> >>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> >>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> >>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> >>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> >>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> >>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> >>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
> >>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
> >>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> >>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> >>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> >>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
> >>>
> >>> I afraid that you misinterpreted the "Co-developed-by" tag. All these
> >>> people are probably touch the code and not actually sit together at
> >>> the same room and write the code together. So, please remove the
> >>> extensive "Co-developed-by" tags.
> >>>
> >>> It is not full review yet, but simple pass-by-comments.
> >>>
> >>
> >> Actually except of two, all of the mentioned persons sat in the same room
> >> and developed the code together.
> >> The remaining two are located on a different site (but also together).
> >> Isn't that what "Co-developed-by" tag for?
> >> I wanted to give them credit for writing the code but I can remove if it's
> >> not common.
> >
> > Signed-off-by will be enough to give them credit.
> >
>
> Ok, good enough.
>
> >>
> >>>> ---
> >>>> MAINTAINERS | 10 +
> >>>> drivers/infiniband/Kconfig | 1 +
> >>>> drivers/infiniband/hw/Makefile | 1 +
> >>>> drivers/infiniband/hw/hbl/Kconfig | 17 +
> >>>> drivers/infiniband/hw/hbl/Makefile | 8 +
> >>>> drivers/infiniband/hw/hbl/hbl.h | 326 +++
> >>>> drivers/infiniband/hw/hbl/hbl_main.c | 478 ++++
> >>>> drivers/infiniband/hw/hbl/hbl_verbs.c | 2686 ++++++++++++++++++++++
> >>>> include/uapi/rdma/hbl-abi.h | 204 ++
> >>>> include/uapi/rdma/hbl_user_ioctl_cmds.h | 66 +
> >>>> include/uapi/rdma/hbl_user_ioctl_verbs.h | 106 +
> >>>> include/uapi/rdma/ib_user_ioctl_verbs.h | 1 +
> >>>> 12 files changed, 3904 insertions(+)
> >>>> create mode 100644 drivers/infiniband/hw/hbl/Kconfig
> >>>> create mode 100644 drivers/infiniband/hw/hbl/Makefile
> >>>> create mode 100644 drivers/infiniband/hw/hbl/hbl.h
> >>>> create mode 100644 drivers/infiniband/hw/hbl/hbl_main.c
> >>>> create mode 100644 drivers/infiniband/hw/hbl/hbl_verbs.c
> >>>> create mode 100644 include/uapi/rdma/hbl-abi.h
> >>>> create mode 100644 include/uapi/rdma/hbl_user_ioctl_cmds.h
> >>>> create mode 100644 include/uapi/rdma/hbl_user_ioctl_verbs.h
> >>>
> >>> <...>
> >>>
> >>>> +#define hbl_ibdev_emerg(ibdev, format, ...) ibdev_emerg(ibdev, format, ##__VA_ARGS__)
> >>>> +#define hbl_ibdev_alert(ibdev, format, ...) ibdev_alert(ibdev, format, ##__VA_ARGS__)
> >>>> +#define hbl_ibdev_crit(ibdev, format, ...) ibdev_crit(ibdev, format, ##__VA_ARGS__)
> >>>> +#define hbl_ibdev_err(ibdev, format, ...) ibdev_err(ibdev, format, ##__VA_ARGS__)
> >>>> +#define hbl_ibdev_warn(ibdev, format, ...) ibdev_warn(ibdev, format, ##__VA_ARGS__)
> >>>> +#define hbl_ibdev_notice(ibdev, format, ...) ibdev_notice(ibdev, format, ##__VA_ARGS__)
> >>>> +#define hbl_ibdev_info(ibdev, format, ...) ibdev_info(ibdev, format, ##__VA_ARGS__)
> >>>> +#define hbl_ibdev_dbg(ibdev, format, ...) ibdev_dbg(ibdev, format, ##__VA_ARGS__)
> >>>> +
> >>>> +#define hbl_ibdev_emerg_ratelimited(ibdev, fmt, ...) \
> >>>> + ibdev_emerg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>> +#define hbl_ibdev_alert_ratelimited(ibdev, fmt, ...) \
> >>>> + ibdev_alert_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>> +#define hbl_ibdev_crit_ratelimited(ibdev, fmt, ...) \
> >>>> + ibdev_crit_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>> +#define hbl_ibdev_err_ratelimited(ibdev, fmt, ...) \
> >>>> + ibdev_err_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>> +#define hbl_ibdev_warn_ratelimited(ibdev, fmt, ...) \
> >>>> + ibdev_warn_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>> +#define hbl_ibdev_notice_ratelimited(ibdev, fmt, ...) \
> >>>> + ibdev_notice_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>> +#define hbl_ibdev_info_ratelimited(ibdev, fmt, ...) \
> >>>> + ibdev_info_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>> +#define hbl_ibdev_dbg_ratelimited(ibdev, fmt, ...) \
> >>>> + ibdev_dbg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>> +
> >>>
> >>> Please don't redefine the existing macros. Just use the existing ones.
> >>>
> >>>
> >>> <...>
> >>>
> >>
> >> That's a leftover from some debug code. I'll remove.
> >>
> >>>> + if (hbl_ib_match_netdev(ibdev, netdev))
> >>>> + ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
> >>>> + else
> >>>> + return NOTIFY_DONE;
> >>>
> >>> It is not kernel coding style. Please write:
> >>> if (!hbl_ib_match_netdev(ibdev, netdev))
> >>> return NOTIFY_DONE;
> >>>
> >>> ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
> >>>
> >>
> >> I'll fix the code, thanks.
> >>
> >>>> +
> >>>
> >>> <...>
> >>>
> >>>> +static int hbl_ib_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
> >>>> +{
> >>>> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
> >>>> + struct hbl_ib_aux_ops *aux_ops = aux_dev->aux_ops;
> >>>> + struct hbl_ib_device *hdev;
> >>>> + ktime_t timeout;
> >>>> + int rc;
> >>>> +
> >>>> + rc = hdev_init(aux_dev);
> >>>> + if (rc) {
> >>>> + dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
> >>>> + return -EIO;
> >>>> + }
> >>>> +
> >>>> + hdev = aux_dev->priv;
> >>>> +
> >>>> + /* don't allow module unloading while it is attached */
> >>>> + if (!try_module_get(THIS_MODULE)) {
> >>>
> >>> This part makes wonder, what are you trying to do here? What doesn't work for you
> >>> in standard driver core and module load mechanism?
> >>>
> >>
> >> Before auxiliary bus was introduced, we used EXPORT_SYMBOLs for inter
> >> driver communication. That incremented the refcount of the used module so
> >> it couldn't be removed while it is in use.
> >> Auxiliary bus usage doesn't increment the used module refcount and hence
> >> the used module can be removed while it is in use and that's something
> >> we don't want to allow.
> >> We could solve it by some global locking or in_use atomic but the most
> >> simple and clean way is just to increment the used module refcount on
> >> auxiliary device probe and decrement it on auxiliary device removal.
> >
> > No, you was supposed to continue to use EXPORT_SYMBOLs and don't
> > invent auxiliary ops structure (this is why you lost module
> > reference counting).
> >
>
> Sorry, but according to the auxiliary bus doc, a domain-specific ops
> structure can be used.
> We followed the usage example described at drivers/base/auxiliary.c.
> What am I missing?
Being the one who implemented auxiliary bus in the kernel and converted
number of drivers to use it, I strongly recommend do NOT follow the example
provided there.
So you are missing "best practice", and "best practice" is to use
EXPORT_SYMBOLs and rely on module reference counting.
> Moreover, we'd like to support the mode where the IB or the ETH driver is
> not loaded at all. But this cannot be achieved if we use EXPORT_SYMBOLs
> exclusively for inter driver communication.
It is not true and not how the kernel works. You can perfectly load core
driver without IB and ETH, at some extent this is how mlx5 driver works.
>
> >>
> >>>> + dev_err(hdev->dev, "Failed to increment %s module refcount\n",
> >>>> + module_name(THIS_MODULE));
> >>>> + rc = -EIO;
> >>>> + goto module_get_err;
> >>>> + }
> >>>> +
> >>>> + timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
> >>>> + while (1) {
> >>>> + aux_ops->hw_access_lock(aux_dev);
> >>>> +
> >>>> + /* if the device is operational, proceed to actual init while holding the lock in
> >>>> + * order to prevent concurrent hard reset
> >>>> + */
> >>>> + if (aux_ops->device_operational(aux_dev))
> >>>> + break;
> >>>> +
> >>>> + aux_ops->hw_access_unlock(aux_dev);
> >>>> +
> >>>> + if (ktime_compare(ktime_get(), timeout) > 0) {
> >>>> + dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
> >>>> + rc = -EBUSY;
> >>>> + goto timeout_err;
> >>>> + }
> >>>> +
> >>>> + dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing IB\n");
> >>>> +
> >>>> + msleep_interruptible(MSEC_PER_SEC);
> >>>> + }
> >>>
> >>> The code above is unexpected.
> >>>
> >>
> >> We have no control on when the user insmod the IB driver.
> >
> > It is not true, this is controlled through module dependencies
> > mechanism.
> >
>
> Yeah, if we would use EXPORT_SYMBOLs for inter driver communication but
> we don't.
So please use it and don't add complexity where it is not needed.
>
> >> As a result it is possible that the IB auxiliary device will be probed
> >> while the compute device is under reset (due to some HW error).
> >
> > No, it is not possible. If you structure your driver right.
> >
>
> Again, it is not possible if we would use EXPORT_SYMBOLs.
> Please let me know if we misunderstood something because AFAIU we followed
> the auxiliary bus doc usage example.
It is better to follow actual drivers that use auxiliary bus and see how
they implemented it and not rely on examples in the documentation.
Thanks
>
> > Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-18 12:58 ` Leon Romanovsky
@ 2024-06-19 9:27 ` Omer Shpigelman
2024-06-19 10:52 ` Leon Romanovsky
0 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-19 9:27 UTC (permalink / raw)
To: Leon Romanovsky, gregkh@linuxfoundation.org
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/18/24 15:58, Leon Romanovsky wrote:
> On Tue, Jun 18, 2024 at 11:08:34AM +0000, Omer Shpigelman wrote:
>> On 6/17/24 22:04, Leon Romanovsky wrote:
>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>
>>> On Mon, Jun 17, 2024 at 05:43:49PM +0000, Omer Shpigelman wrote:
>>>> On 6/13/24 22:18, Leon Romanovsky wrote:
>>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>>
>>>>> On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
>>>>>> Add an RDMA driver of Gaudi ASICs family for AI scaling.
>>>>>> The driver itself is agnostic to the ASIC in action, it operates according
>>>>>> to the capabilities that were passed on device initialization.
>>>>>> The device is initialized by the hbl_cn driver via auxiliary bus.
>>>>>> The driver also supports QP resource tracking and port/device HW counters.
>>>>>>
>>>>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
>>>>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
>>>>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
>>>>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
>>>>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
>>>>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
>>>>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
>>>>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
>>>>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
>>>>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
>>>>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
>>>>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
>>>>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
>>>>>
>>>>> I afraid that you misinterpreted the "Co-developed-by" tag. All these
>>>>> people are probably touch the code and not actually sit together at
>>>>> the same room and write the code together. So, please remove the
>>>>> extensive "Co-developed-by" tags.
>>>>>
>>>>> It is not full review yet, but simple pass-by-comments.
>>>>>
>>>>
>>>> Actually except of two, all of the mentioned persons sat in the same room
>>>> and developed the code together.
>>>> The remaining two are located on a different site (but also together).
>>>> Isn't that what "Co-developed-by" tag for?
>>>> I wanted to give them credit for writing the code but I can remove if it's
>>>> not common.
>>>
>>> Signed-off-by will be enough to give them credit.
>>>
>>
>> Ok, good enough.
>>
>>>>
>>>>>> ---
>>>>>> MAINTAINERS | 10 +
>>>>>> drivers/infiniband/Kconfig | 1 +
>>>>>> drivers/infiniband/hw/Makefile | 1 +
>>>>>> drivers/infiniband/hw/hbl/Kconfig | 17 +
>>>>>> drivers/infiniband/hw/hbl/Makefile | 8 +
>>>>>> drivers/infiniband/hw/hbl/hbl.h | 326 +++
>>>>>> drivers/infiniband/hw/hbl/hbl_main.c | 478 ++++
>>>>>> drivers/infiniband/hw/hbl/hbl_verbs.c | 2686 ++++++++++++++++++++++
>>>>>> include/uapi/rdma/hbl-abi.h | 204 ++
>>>>>> include/uapi/rdma/hbl_user_ioctl_cmds.h | 66 +
>>>>>> include/uapi/rdma/hbl_user_ioctl_verbs.h | 106 +
>>>>>> include/uapi/rdma/ib_user_ioctl_verbs.h | 1 +
>>>>>> 12 files changed, 3904 insertions(+)
>>>>>> create mode 100644 drivers/infiniband/hw/hbl/Kconfig
>>>>>> create mode 100644 drivers/infiniband/hw/hbl/Makefile
>>>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl.h
>>>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl_main.c
>>>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl_verbs.c
>>>>>> create mode 100644 include/uapi/rdma/hbl-abi.h
>>>>>> create mode 100644 include/uapi/rdma/hbl_user_ioctl_cmds.h
>>>>>> create mode 100644 include/uapi/rdma/hbl_user_ioctl_verbs.h
>>>>>
>>>>> <...>
>>>>>
>>>>>> +#define hbl_ibdev_emerg(ibdev, format, ...) ibdev_emerg(ibdev, format, ##__VA_ARGS__)
>>>>>> +#define hbl_ibdev_alert(ibdev, format, ...) ibdev_alert(ibdev, format, ##__VA_ARGS__)
>>>>>> +#define hbl_ibdev_crit(ibdev, format, ...) ibdev_crit(ibdev, format, ##__VA_ARGS__)
>>>>>> +#define hbl_ibdev_err(ibdev, format, ...) ibdev_err(ibdev, format, ##__VA_ARGS__)
>>>>>> +#define hbl_ibdev_warn(ibdev, format, ...) ibdev_warn(ibdev, format, ##__VA_ARGS__)
>>>>>> +#define hbl_ibdev_notice(ibdev, format, ...) ibdev_notice(ibdev, format, ##__VA_ARGS__)
>>>>>> +#define hbl_ibdev_info(ibdev, format, ...) ibdev_info(ibdev, format, ##__VA_ARGS__)
>>>>>> +#define hbl_ibdev_dbg(ibdev, format, ...) ibdev_dbg(ibdev, format, ##__VA_ARGS__)
>>>>>> +
>>>>>> +#define hbl_ibdev_emerg_ratelimited(ibdev, fmt, ...) \
>>>>>> + ibdev_emerg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>> +#define hbl_ibdev_alert_ratelimited(ibdev, fmt, ...) \
>>>>>> + ibdev_alert_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>> +#define hbl_ibdev_crit_ratelimited(ibdev, fmt, ...) \
>>>>>> + ibdev_crit_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>> +#define hbl_ibdev_err_ratelimited(ibdev, fmt, ...) \
>>>>>> + ibdev_err_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>> +#define hbl_ibdev_warn_ratelimited(ibdev, fmt, ...) \
>>>>>> + ibdev_warn_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>> +#define hbl_ibdev_notice_ratelimited(ibdev, fmt, ...) \
>>>>>> + ibdev_notice_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>> +#define hbl_ibdev_info_ratelimited(ibdev, fmt, ...) \
>>>>>> + ibdev_info_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>> +#define hbl_ibdev_dbg_ratelimited(ibdev, fmt, ...) \
>>>>>> + ibdev_dbg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>> +
>>>>>
>>>>> Please don't redefine the existing macros. Just use the existing ones.
>>>>>
>>>>>
>>>>> <...>
>>>>>
>>>>
>>>> That's a leftover from some debug code. I'll remove.
>>>>
>>>>>> + if (hbl_ib_match_netdev(ibdev, netdev))
>>>>>> + ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
>>>>>> + else
>>>>>> + return NOTIFY_DONE;
>>>>>
>>>>> It is not kernel coding style. Please write:
>>>>> if (!hbl_ib_match_netdev(ibdev, netdev))
>>>>> return NOTIFY_DONE;
>>>>>
>>>>> ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
>>>>>
>>>>
>>>> I'll fix the code, thanks.
>>>>
>>>>>> +
>>>>>
>>>>> <...>
>>>>>
>>>>>> +static int hbl_ib_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
>>>>>> +{
>>>>>> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
>>>>>> + struct hbl_ib_aux_ops *aux_ops = aux_dev->aux_ops;
>>>>>> + struct hbl_ib_device *hdev;
>>>>>> + ktime_t timeout;
>>>>>> + int rc;
>>>>>> +
>>>>>> + rc = hdev_init(aux_dev);
>>>>>> + if (rc) {
>>>>>> + dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
>>>>>> + return -EIO;
>>>>>> + }
>>>>>> +
>>>>>> + hdev = aux_dev->priv;
>>>>>> +
>>>>>> + /* don't allow module unloading while it is attached */
>>>>>> + if (!try_module_get(THIS_MODULE)) {
>>>>>
>>>>> This part makes wonder, what are you trying to do here? What doesn't work for you
>>>>> in standard driver core and module load mechanism?
>>>>>
>>>>
>>>> Before auxiliary bus was introduced, we used EXPORT_SYMBOLs for inter
>>>> driver communication. That incremented the refcount of the used module so
>>>> it couldn't be removed while it is in use.
>>>> Auxiliary bus usage doesn't increment the used module refcount and hence
>>>> the used module can be removed while it is in use and that's something
>>>> we don't want to allow.
>>>> We could solve it by some global locking or in_use atomic but the most
>>>> simple and clean way is just to increment the used module refcount on
>>>> auxiliary device probe and decrement it on auxiliary device removal.
>>>
>>> No, you was supposed to continue to use EXPORT_SYMBOLs and don't
>>> invent auxiliary ops structure (this is why you lost module
>>> reference counting).
>>>
>>
>> Sorry, but according to the auxiliary bus doc, a domain-specific ops
>> structure can be used.
>> We followed the usage example described at drivers/base/auxiliary.c.
>> What am I missing?
>
> Being the one who implemented auxiliary bus in the kernel and converted
> number of drivers to use it, I strongly recommend do NOT follow the example
> provided there.
>
> So you are missing "best practice", and "best practice" is to use
> EXPORT_SYMBOLs and rely on module reference counting.
>
It is not just the usage example but also the general feature doc before
it:
"The generic behavior can be extended and specialized as needed by
encapsulating an auxiliary_device within other domain-specific structures
and the use of .ops callbacks."
It is also mentioned there that the ops structure are used for specific
auxiliary device operations while EXPORT_SYMBOLs should be used for common
infrastrucure the parent driver exposes:
"Note that ops are intended as a way to augment instance behavior within a
class of auxiliary devices, it is not the mechanism for exporting common
infrastructure from the parent."
All of our ops callbacks are meant to provide functionality related to the
auxiliary device, they are not just general/common infrastructure.
Why do we have this doc if we should ignore it? why wasn't the doc
modified according to the "best practice" you described? the doc is
misleading.
Adding gregkh here as he requested the auxiliary bus feature IIRC.
Greg - isn't the doc legit? should EXPORT_SYMBOLs necessarily be used
together with auxiliary bus rather than ops structure?
As we saw it, auxiliary bus gives us the flexibility to choose which
modules will be loaded while EXPORT_SYMBOLs enforces the dependencies
which might not be needed in some cases.
>> Moreover, we'd like to support the mode where the IB or the ETH driver is
>> not loaded at all. But this cannot be achieved if we use EXPORT_SYMBOLs
>> exclusively for inter driver communication.
>
> It is not true and not how the kernel works. You can perfectly load core
> driver without IB and ETH, at some extent this is how mlx5 driver works.
>
mlx5 IB driver doesn't export any symbol that is used by the core driver,
that's why the core driver can be loaded without the IB driver (althought
you'll get circular dependency if you would export).
If relying on exported symbols only, then our IB and ETH drivers will need
to export symbols too because the core driver accesses them post probing.
Hence we won't be able to load the core driver without both of them (or
loading anything due to circular dependency).
Unless we'll use dynamic symbol lookup and I don't think that's your
intention.
>>
>>>>
>>>>>> + dev_err(hdev->dev, "Failed to increment %s module refcount\n",
>>>>>> + module_name(THIS_MODULE));
>>>>>> + rc = -EIO;
>>>>>> + goto module_get_err;
>>>>>> + }
>>>>>> +
>>>>>> + timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
>>>>>> + while (1) {
>>>>>> + aux_ops->hw_access_lock(aux_dev);
>>>>>> +
>>>>>> + /* if the device is operational, proceed to actual init while holding the lock in
>>>>>> + * order to prevent concurrent hard reset
>>>>>> + */
>>>>>> + if (aux_ops->device_operational(aux_dev))
>>>>>> + break;
>>>>>> +
>>>>>> + aux_ops->hw_access_unlock(aux_dev);
>>>>>> +
>>>>>> + if (ktime_compare(ktime_get(), timeout) > 0) {
>>>>>> + dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
>>>>>> + rc = -EBUSY;
>>>>>> + goto timeout_err;
>>>>>> + }
>>>>>> +
>>>>>> + dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing IB\n");
>>>>>> +
>>>>>> + msleep_interruptible(MSEC_PER_SEC);
>>>>>> + }
>>>>>
>>>>> The code above is unexpected.
>>>>>
>>>>
>>>> We have no control on when the user insmod the IB driver.
>>>
>>> It is not true, this is controlled through module dependencies
>>> mechanism.
>>>
>>
>> Yeah, if we would use EXPORT_SYMBOLs for inter driver communication but
>> we don't.
>
> So please use it and don't add complexity where it is not needed.
>
>>
>>>> As a result it is possible that the IB auxiliary device will be probed
>>>> while the compute device is under reset (due to some HW error).
>>>
>>> No, it is not possible. If you structure your driver right.
>>>
>>
>> Again, it is not possible if we would use EXPORT_SYMBOLs.
>> Please let me know if we misunderstood something because AFAIU we followed
>> the auxiliary bus doc usage example.
>
> It is better to follow actual drivers that use auxiliary bus and see how
> they implemented it and not rely on examples in the documentation.
>
But isn't that what the doc for? to explain the guidelines? and it's not
that there is a big red note there of "this example should not be taken as
is, please look at your subsystem guidelines".
> Thanks
>
>>
>>> Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-19 9:27 ` Omer Shpigelman
@ 2024-06-19 10:52 ` Leon Romanovsky
2024-06-24 8:47 ` Omer Shpigelman
2024-06-28 10:24 ` Omer Shpigelman
0 siblings, 2 replies; 108+ messages in thread
From: Leon Romanovsky @ 2024-06-19 10:52 UTC (permalink / raw)
To: Omer Shpigelman
Cc: gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On Wed, Jun 19, 2024 at 09:27:54AM +0000, Omer Shpigelman wrote:
> On 6/18/24 15:58, Leon Romanovsky wrote:
> > On Tue, Jun 18, 2024 at 11:08:34AM +0000, Omer Shpigelman wrote:
> >> On 6/17/24 22:04, Leon Romanovsky wrote:
> >>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >>>
> >>> On Mon, Jun 17, 2024 at 05:43:49PM +0000, Omer Shpigelman wrote:
> >>>> On 6/13/24 22:18, Leon Romanovsky wrote:
> >>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >>>>>
> >>>>> On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
> >>>>>> Add an RDMA driver of Gaudi ASICs family for AI scaling.
> >>>>>> The driver itself is agnostic to the ASIC in action, it operates according
> >>>>>> to the capabilities that were passed on device initialization.
> >>>>>> The device is initialized by the hbl_cn driver via auxiliary bus.
> >>>>>> The driver also supports QP resource tracking and port/device HW counters.
> >>>>>>
> >>>>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> >>>>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> >>>>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> >>>>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> >>>>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> >>>>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> >>>>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> >>>>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
> >>>>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
> >>>>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> >>>>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> >>>>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> >>>>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
> >>>>>
> >>>>> I afraid that you misinterpreted the "Co-developed-by" tag. All these
> >>>>> people are probably touch the code and not actually sit together at
> >>>>> the same room and write the code together. So, please remove the
> >>>>> extensive "Co-developed-by" tags.
> >>>>>
> >>>>> It is not full review yet, but simple pass-by-comments.
> >>>>>
> >>>>
> >>>> Actually except of two, all of the mentioned persons sat in the same room
> >>>> and developed the code together.
> >>>> The remaining two are located on a different site (but also together).
> >>>> Isn't that what "Co-developed-by" tag for?
> >>>> I wanted to give them credit for writing the code but I can remove if it's
> >>>> not common.
> >>>
> >>> Signed-off-by will be enough to give them credit.
> >>>
> >>
> >> Ok, good enough.
> >>
> >>>>
> >>>>>> ---
> >>>>>> MAINTAINERS | 10 +
> >>>>>> drivers/infiniband/Kconfig | 1 +
> >>>>>> drivers/infiniband/hw/Makefile | 1 +
> >>>>>> drivers/infiniband/hw/hbl/Kconfig | 17 +
> >>>>>> drivers/infiniband/hw/hbl/Makefile | 8 +
> >>>>>> drivers/infiniband/hw/hbl/hbl.h | 326 +++
> >>>>>> drivers/infiniband/hw/hbl/hbl_main.c | 478 ++++
> >>>>>> drivers/infiniband/hw/hbl/hbl_verbs.c | 2686 ++++++++++++++++++++++
> >>>>>> include/uapi/rdma/hbl-abi.h | 204 ++
> >>>>>> include/uapi/rdma/hbl_user_ioctl_cmds.h | 66 +
> >>>>>> include/uapi/rdma/hbl_user_ioctl_verbs.h | 106 +
> >>>>>> include/uapi/rdma/ib_user_ioctl_verbs.h | 1 +
> >>>>>> 12 files changed, 3904 insertions(+)
> >>>>>> create mode 100644 drivers/infiniband/hw/hbl/Kconfig
> >>>>>> create mode 100644 drivers/infiniband/hw/hbl/Makefile
> >>>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl.h
> >>>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl_main.c
> >>>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl_verbs.c
> >>>>>> create mode 100644 include/uapi/rdma/hbl-abi.h
> >>>>>> create mode 100644 include/uapi/rdma/hbl_user_ioctl_cmds.h
> >>>>>> create mode 100644 include/uapi/rdma/hbl_user_ioctl_verbs.h
> >>>>>
> >>>>> <...>
> >>>>>
> >>>>>> +#define hbl_ibdev_emerg(ibdev, format, ...) ibdev_emerg(ibdev, format, ##__VA_ARGS__)
> >>>>>> +#define hbl_ibdev_alert(ibdev, format, ...) ibdev_alert(ibdev, format, ##__VA_ARGS__)
> >>>>>> +#define hbl_ibdev_crit(ibdev, format, ...) ibdev_crit(ibdev, format, ##__VA_ARGS__)
> >>>>>> +#define hbl_ibdev_err(ibdev, format, ...) ibdev_err(ibdev, format, ##__VA_ARGS__)
> >>>>>> +#define hbl_ibdev_warn(ibdev, format, ...) ibdev_warn(ibdev, format, ##__VA_ARGS__)
> >>>>>> +#define hbl_ibdev_notice(ibdev, format, ...) ibdev_notice(ibdev, format, ##__VA_ARGS__)
> >>>>>> +#define hbl_ibdev_info(ibdev, format, ...) ibdev_info(ibdev, format, ##__VA_ARGS__)
> >>>>>> +#define hbl_ibdev_dbg(ibdev, format, ...) ibdev_dbg(ibdev, format, ##__VA_ARGS__)
> >>>>>> +
> >>>>>> +#define hbl_ibdev_emerg_ratelimited(ibdev, fmt, ...) \
> >>>>>> + ibdev_emerg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>> +#define hbl_ibdev_alert_ratelimited(ibdev, fmt, ...) \
> >>>>>> + ibdev_alert_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>> +#define hbl_ibdev_crit_ratelimited(ibdev, fmt, ...) \
> >>>>>> + ibdev_crit_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>> +#define hbl_ibdev_err_ratelimited(ibdev, fmt, ...) \
> >>>>>> + ibdev_err_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>> +#define hbl_ibdev_warn_ratelimited(ibdev, fmt, ...) \
> >>>>>> + ibdev_warn_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>> +#define hbl_ibdev_notice_ratelimited(ibdev, fmt, ...) \
> >>>>>> + ibdev_notice_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>> +#define hbl_ibdev_info_ratelimited(ibdev, fmt, ...) \
> >>>>>> + ibdev_info_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>> +#define hbl_ibdev_dbg_ratelimited(ibdev, fmt, ...) \
> >>>>>> + ibdev_dbg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>> +
> >>>>>
> >>>>> Please don't redefine the existing macros. Just use the existing ones.
> >>>>>
> >>>>>
> >>>>> <...>
> >>>>>
> >>>>
> >>>> That's a leftover from some debug code. I'll remove.
> >>>>
> >>>>>> + if (hbl_ib_match_netdev(ibdev, netdev))
> >>>>>> + ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
> >>>>>> + else
> >>>>>> + return NOTIFY_DONE;
> >>>>>
> >>>>> It is not kernel coding style. Please write:
> >>>>> if (!hbl_ib_match_netdev(ibdev, netdev))
> >>>>> return NOTIFY_DONE;
> >>>>>
> >>>>> ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
> >>>>>
> >>>>
> >>>> I'll fix the code, thanks.
> >>>>
> >>>>>> +
> >>>>>
> >>>>> <...>
> >>>>>
> >>>>>> +static int hbl_ib_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
> >>>>>> +{
> >>>>>> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
> >>>>>> + struct hbl_ib_aux_ops *aux_ops = aux_dev->aux_ops;
> >>>>>> + struct hbl_ib_device *hdev;
> >>>>>> + ktime_t timeout;
> >>>>>> + int rc;
> >>>>>> +
> >>>>>> + rc = hdev_init(aux_dev);
> >>>>>> + if (rc) {
> >>>>>> + dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
> >>>>>> + return -EIO;
> >>>>>> + }
> >>>>>> +
> >>>>>> + hdev = aux_dev->priv;
> >>>>>> +
> >>>>>> + /* don't allow module unloading while it is attached */
> >>>>>> + if (!try_module_get(THIS_MODULE)) {
> >>>>>
> >>>>> This part makes wonder, what are you trying to do here? What doesn't work for you
> >>>>> in standard driver core and module load mechanism?
> >>>>>
> >>>>
> >>>> Before auxiliary bus was introduced, we used EXPORT_SYMBOLs for inter
> >>>> driver communication. That incremented the refcount of the used module so
> >>>> it couldn't be removed while it is in use.
> >>>> Auxiliary bus usage doesn't increment the used module refcount and hence
> >>>> the used module can be removed while it is in use and that's something
> >>>> we don't want to allow.
> >>>> We could solve it by some global locking or in_use atomic but the most
> >>>> simple and clean way is just to increment the used module refcount on
> >>>> auxiliary device probe and decrement it on auxiliary device removal.
> >>>
> >>> No, you was supposed to continue to use EXPORT_SYMBOLs and don't
> >>> invent auxiliary ops structure (this is why you lost module
> >>> reference counting).
> >>>
> >>
> >> Sorry, but according to the auxiliary bus doc, a domain-specific ops
> >> structure can be used.
> >> We followed the usage example described at drivers/base/auxiliary.c.
> >> What am I missing?
> >
> > Being the one who implemented auxiliary bus in the kernel and converted
> > number of drivers to use it, I strongly recommend do NOT follow the example
> > provided there.
> >
> > So you are missing "best practice", and "best practice" is to use
> > EXPORT_SYMBOLs and rely on module reference counting.
> >
>
> It is not just the usage example but also the general feature doc before
> it:
> "The generic behavior can be extended and specialized as needed by
> encapsulating an auxiliary_device within other domain-specific structures
> and the use of .ops callbacks."
> It is also mentioned there that the ops structure are used for specific
> auxiliary device operations while EXPORT_SYMBOLs should be used for common
> infrastrucure the parent driver exposes:
> "Note that ops are intended as a way to augment instance behavior within a
> class of auxiliary devices, it is not the mechanism for exporting common
> infrastructure from the parent."
> All of our ops callbacks are meant to provide functionality related to the
> auxiliary device, they are not just general/common infrastructure.
Of course they are common, otherwise why did you put them in common code?
For example, you have callbacks to lock and unlock internal HW access,
how is it not common?
>
> Why do we have this doc if we should ignore it? why wasn't the doc
> modified according to the "best practice" you described? the doc is
> misleading.
Because this is how upstream kernel development works. We are trying to
come to the agreement and get the best solution for the problem. Sometimes,
the outcome of the discussion is not "the best solution", but "good
enough". This doc can be served as an example. Everyone involved in the
development of auxbus and later usage of it, were focused on implementation,
documentation was good enough as it didn't limit anyone who actually
used it.
>
> Adding gregkh here as he requested the auxiliary bus feature IIRC.
> Greg - isn't the doc legit? should EXPORT_SYMBOLs necessarily be used
> together with auxiliary bus rather than ops structure?
This is not what you are doing here. You completely ditched EXPORT_SYMBOLs
and reinvented module reference counting which overcomplicated the code
just to avoid using standard kernel mechanism.
> As we saw it, auxiliary bus gives us the flexibility to choose which
> modules will be loaded while EXPORT_SYMBOLs enforces the dependencies
> which might not be needed in some cases.
>
> >> Moreover, we'd like to support the mode where the IB or the ETH driver is
> >> not loaded at all. But this cannot be achieved if we use EXPORT_SYMBOLs
> >> exclusively for inter driver communication.
> >
> > It is not true and not how the kernel works. You can perfectly load core
> > driver without IB and ETH, at some extent this is how mlx5 driver works.
> >
>
> mlx5 IB driver doesn't export any symbol that is used by the core driver,
> that's why the core driver can be loaded without the IB driver (althought
> you'll get circular dependency if you would export).
Yes, IB and ETH drivers are "users" of core driver. As RDMA maintainer,
I'm reluctant to accept code that exports symbols from IB drivers to
other subsystems. We have drivers/infiniband/core/ for that.
> If relying on exported symbols only, then our IB and ETH drivers will need
> to export symbols too because the core driver accesses them post probing.
So you should fix your core driver. This is exactly what auxbus model
proposes.
> Hence we won't be able to load the core driver without both of them (or
> loading anything due to circular dependency).
> Unless we'll use dynamic symbol lookup and I don't think that's your
> intention.
No it is not.
>
> >>
> >>>>
> >>>>>> + dev_err(hdev->dev, "Failed to increment %s module refcount\n",
> >>>>>> + module_name(THIS_MODULE));
> >>>>>> + rc = -EIO;
> >>>>>> + goto module_get_err;
> >>>>>> + }
> >>>>>> +
> >>>>>> + timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
> >>>>>> + while (1) {
> >>>>>> + aux_ops->hw_access_lock(aux_dev);
> >>>>>> +
> >>>>>> + /* if the device is operational, proceed to actual init while holding the lock in
> >>>>>> + * order to prevent concurrent hard reset
> >>>>>> + */
> >>>>>> + if (aux_ops->device_operational(aux_dev))
> >>>>>> + break;
> >>>>>> +
> >>>>>> + aux_ops->hw_access_unlock(aux_dev);
> >>>>>> +
> >>>>>> + if (ktime_compare(ktime_get(), timeout) > 0) {
> >>>>>> + dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
> >>>>>> + rc = -EBUSY;
> >>>>>> + goto timeout_err;
> >>>>>> + }
> >>>>>> +
> >>>>>> + dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing IB\n");
> >>>>>> +
> >>>>>> + msleep_interruptible(MSEC_PER_SEC);
> >>>>>> + }
> >>>>>
> >>>>> The code above is unexpected.
> >>>>>
> >>>>
> >>>> We have no control on when the user insmod the IB driver.
> >>>
> >>> It is not true, this is controlled through module dependencies
> >>> mechanism.
> >>>
> >>
> >> Yeah, if we would use EXPORT_SYMBOLs for inter driver communication but
> >> we don't.
> >
> > So please use it and don't add complexity where it is not needed.
> >
> >>
> >>>> As a result it is possible that the IB auxiliary device will be probed
> >>>> while the compute device is under reset (due to some HW error).
> >>>
> >>> No, it is not possible. If you structure your driver right.
> >>>
> >>
> >> Again, it is not possible if we would use EXPORT_SYMBOLs.
> >> Please let me know if we misunderstood something because AFAIU we followed
> >> the auxiliary bus doc usage example.
> >
> > It is better to follow actual drivers that use auxiliary bus and see how
> > they implemented it and not rely on examples in the documentation.
> >
>
> But isn't that what the doc for? to explain the guidelines? and it's not
> that there is a big red note there of "this example should not be taken as
> is, please look at your subsystem guidelines".
At the beginning that doc was located in Documentation/ folder and no one
really cared about it. After moving from Documentation/ to drivers/base/auxiliary.c,
it became more visible, but still no one relied on it. You are first one
who read.
There is no subsystem rules here. Everyone relied on EXPORT_SYMBOLs and didn't
use ops structure. Kernel is evolving project, there is no need to find a rule
for everything.
Thanks
>
> > Thanks
> >
> >>
> >>> Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-19 10:52 ` Leon Romanovsky
@ 2024-06-24 8:47 ` Omer Shpigelman
2024-06-24 9:10 ` Leon Romanovsky
2024-06-28 10:24 ` Omer Shpigelman
1 sibling, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-24 8:47 UTC (permalink / raw)
To: Leon Romanovsky
Cc: gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On 6/19/24 13:52, Leon Romanovsky wrote:
> On Wed, Jun 19, 2024 at 09:27:54AM +0000, Omer Shpigelman wrote:
>> On 6/18/24 15:58, Leon Romanovsky wrote:
>>> On Tue, Jun 18, 2024 at 11:08:34AM +0000, Omer Shpigelman wrote:
>>>> On 6/17/24 22:04, Leon Romanovsky wrote:
>>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>>
>>>>> On Mon, Jun 17, 2024 at 05:43:49PM +0000, Omer Shpigelman wrote:
>>>>>> On 6/13/24 22:18, Leon Romanovsky wrote:
>>>>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>>>>
>>>>>>> On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
>>>>>>>> Add an RDMA driver of Gaudi ASICs family for AI scaling.
>>>>>>>> The driver itself is agnostic to the ASIC in action, it operates according
>>>>>>>> to the capabilities that were passed on device initialization.
>>>>>>>> The device is initialized by the hbl_cn driver via auxiliary bus.
>>>>>>>> The driver also supports QP resource tracking and port/device HW counters.
>>>>>>>>
>>>>>>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
>>>>>>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
>>>>>>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
>>>>>>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
>>>>>>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
>>>>>>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
>>>>>>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
>>>>>>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
>>>>>>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
>>>>>>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
>>>>>>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
>>>>>>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
>>>>>>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
>>>>>>>
>>>>>>> I afraid that you misinterpreted the "Co-developed-by" tag. All these
>>>>>>> people are probably touch the code and not actually sit together at
>>>>>>> the same room and write the code together. So, please remove the
>>>>>>> extensive "Co-developed-by" tags.
>>>>>>>
>>>>>>> It is not full review yet, but simple pass-by-comments.
>>>>>>>
>>>>>>
>>>>>> Actually except of two, all of the mentioned persons sat in the same room
>>>>>> and developed the code together.
>>>>>> The remaining two are located on a different site (but also together).
>>>>>> Isn't that what "Co-developed-by" tag for?
>>>>>> I wanted to give them credit for writing the code but I can remove if it's
>>>>>> not common.
>>>>>
>>>>> Signed-off-by will be enough to give them credit.
>>>>>
>>>>
>>>> Ok, good enough.
>>>>
>>>>>>
>>>>>>>> ---
>>>>>>>> MAINTAINERS | 10 +
>>>>>>>> drivers/infiniband/Kconfig | 1 +
>>>>>>>> drivers/infiniband/hw/Makefile | 1 +
>>>>>>>> drivers/infiniband/hw/hbl/Kconfig | 17 +
>>>>>>>> drivers/infiniband/hw/hbl/Makefile | 8 +
>>>>>>>> drivers/infiniband/hw/hbl/hbl.h | 326 +++
>>>>>>>> drivers/infiniband/hw/hbl/hbl_main.c | 478 ++++
>>>>>>>> drivers/infiniband/hw/hbl/hbl_verbs.c | 2686 ++++++++++++++++++++++
>>>>>>>> include/uapi/rdma/hbl-abi.h | 204 ++
>>>>>>>> include/uapi/rdma/hbl_user_ioctl_cmds.h | 66 +
>>>>>>>> include/uapi/rdma/hbl_user_ioctl_verbs.h | 106 +
>>>>>>>> include/uapi/rdma/ib_user_ioctl_verbs.h | 1 +
>>>>>>>> 12 files changed, 3904 insertions(+)
>>>>>>>> create mode 100644 drivers/infiniband/hw/hbl/Kconfig
>>>>>>>> create mode 100644 drivers/infiniband/hw/hbl/Makefile
>>>>>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl.h
>>>>>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl_main.c
>>>>>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl_verbs.c
>>>>>>>> create mode 100644 include/uapi/rdma/hbl-abi.h
>>>>>>>> create mode 100644 include/uapi/rdma/hbl_user_ioctl_cmds.h
>>>>>>>> create mode 100644 include/uapi/rdma/hbl_user_ioctl_verbs.h
>>>>>>>
>>>>>>> <...>
>>>>>>>
>>>>>>>> +#define hbl_ibdev_emerg(ibdev, format, ...) ibdev_emerg(ibdev, format, ##__VA_ARGS__)
>>>>>>>> +#define hbl_ibdev_alert(ibdev, format, ...) ibdev_alert(ibdev, format, ##__VA_ARGS__)
>>>>>>>> +#define hbl_ibdev_crit(ibdev, format, ...) ibdev_crit(ibdev, format, ##__VA_ARGS__)
>>>>>>>> +#define hbl_ibdev_err(ibdev, format, ...) ibdev_err(ibdev, format, ##__VA_ARGS__)
>>>>>>>> +#define hbl_ibdev_warn(ibdev, format, ...) ibdev_warn(ibdev, format, ##__VA_ARGS__)
>>>>>>>> +#define hbl_ibdev_notice(ibdev, format, ...) ibdev_notice(ibdev, format, ##__VA_ARGS__)
>>>>>>>> +#define hbl_ibdev_info(ibdev, format, ...) ibdev_info(ibdev, format, ##__VA_ARGS__)
>>>>>>>> +#define hbl_ibdev_dbg(ibdev, format, ...) ibdev_dbg(ibdev, format, ##__VA_ARGS__)
>>>>>>>> +
>>>>>>>> +#define hbl_ibdev_emerg_ratelimited(ibdev, fmt, ...) \
>>>>>>>> + ibdev_emerg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>>>> +#define hbl_ibdev_alert_ratelimited(ibdev, fmt, ...) \
>>>>>>>> + ibdev_alert_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>>>> +#define hbl_ibdev_crit_ratelimited(ibdev, fmt, ...) \
>>>>>>>> + ibdev_crit_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>>>> +#define hbl_ibdev_err_ratelimited(ibdev, fmt, ...) \
>>>>>>>> + ibdev_err_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>>>> +#define hbl_ibdev_warn_ratelimited(ibdev, fmt, ...) \
>>>>>>>> + ibdev_warn_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>>>> +#define hbl_ibdev_notice_ratelimited(ibdev, fmt, ...) \
>>>>>>>> + ibdev_notice_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>>>> +#define hbl_ibdev_info_ratelimited(ibdev, fmt, ...) \
>>>>>>>> + ibdev_info_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>>>> +#define hbl_ibdev_dbg_ratelimited(ibdev, fmt, ...) \
>>>>>>>> + ibdev_dbg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
>>>>>>>> +
>>>>>>>
>>>>>>> Please don't redefine the existing macros. Just use the existing ones.
>>>>>>>
>>>>>>>
>>>>>>> <...>
>>>>>>>
>>>>>>
>>>>>> That's a leftover from some debug code. I'll remove.
>>>>>>
>>>>>>>> + if (hbl_ib_match_netdev(ibdev, netdev))
>>>>>>>> + ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
>>>>>>>> + else
>>>>>>>> + return NOTIFY_DONE;
>>>>>>>
>>>>>>> It is not kernel coding style. Please write:
>>>>>>> if (!hbl_ib_match_netdev(ibdev, netdev))
>>>>>>> return NOTIFY_DONE;
>>>>>>>
>>>>>>> ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
>>>>>>>
>>>>>>
>>>>>> I'll fix the code, thanks.
>>>>>>
>>>>>>>> +
>>>>>>>
>>>>>>> <...>
>>>>>>>
>>>>>>>> +static int hbl_ib_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
>>>>>>>> +{
>>>>>>>> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
>>>>>>>> + struct hbl_ib_aux_ops *aux_ops = aux_dev->aux_ops;
>>>>>>>> + struct hbl_ib_device *hdev;
>>>>>>>> + ktime_t timeout;
>>>>>>>> + int rc;
>>>>>>>> +
>>>>>>>> + rc = hdev_init(aux_dev);
>>>>>>>> + if (rc) {
>>>>>>>> + dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
>>>>>>>> + return -EIO;
>>>>>>>> + }
>>>>>>>> +
>>>>>>>> + hdev = aux_dev->priv;
>>>>>>>> +
>>>>>>>> + /* don't allow module unloading while it is attached */
>>>>>>>> + if (!try_module_get(THIS_MODULE)) {
>>>>>>>
>>>>>>> This part makes wonder, what are you trying to do here? What doesn't work for you
>>>>>>> in standard driver core and module load mechanism?
>>>>>>>
>>>>>>
>>>>>> Before auxiliary bus was introduced, we used EXPORT_SYMBOLs for inter
>>>>>> driver communication. That incremented the refcount of the used module so
>>>>>> it couldn't be removed while it is in use.
>>>>>> Auxiliary bus usage doesn't increment the used module refcount and hence
>>>>>> the used module can be removed while it is in use and that's something
>>>>>> we don't want to allow.
>>>>>> We could solve it by some global locking or in_use atomic but the most
>>>>>> simple and clean way is just to increment the used module refcount on
>>>>>> auxiliary device probe and decrement it on auxiliary device removal.
>>>>>
>>>>> No, you was supposed to continue to use EXPORT_SYMBOLs and don't
>>>>> invent auxiliary ops structure (this is why you lost module
>>>>> reference counting).
>>>>>
>>>>
>>>> Sorry, but according to the auxiliary bus doc, a domain-specific ops
>>>> structure can be used.
>>>> We followed the usage example described at drivers/base/auxiliary.c.
>>>> What am I missing?
>>>
>>> Being the one who implemented auxiliary bus in the kernel and converted
>>> number of drivers to use it, I strongly recommend do NOT follow the example
>>> provided there.
>>>
>>> So you are missing "best practice", and "best practice" is to use
>>> EXPORT_SYMBOLs and rely on module reference counting.
>>>
>>
>> It is not just the usage example but also the general feature doc before
>> it:
>> "The generic behavior can be extended and specialized as needed by
>> encapsulating an auxiliary_device within other domain-specific structures
>> and the use of .ops callbacks."
>> It is also mentioned there that the ops structure are used for specific
>> auxiliary device operations while EXPORT_SYMBOLs should be used for common
>> infrastrucure the parent driver exposes:
>> "Note that ops are intended as a way to augment instance behavior within a
>> class of auxiliary devices, it is not the mechanism for exporting common
>> infrastructure from the parent."
>> All of our ops callbacks are meant to provide functionality related to the
>> auxiliary device, they are not just general/common infrastructure.
>
> Of course they are common, otherwise why did you put them in common code?
> For example, you have callbacks to lock and unlock internal HW access,
> how is it not common?
>
As I saw it, the "common" functions are general capabilities the parent
driver exposes, not necessaritly related to the auxiliary device.
But let me revisit this and try to restructure the code so the parent
driver will use EXPORT_SYMBOLs.
>>
>> Why do we have this doc if we should ignore it? why wasn't the doc
>> modified according to the "best practice" you described? the doc is
>> misleading.
>
> Because this is how upstream kernel development works. We are trying to
> come to the agreement and get the best solution for the problem. Sometimes,
> the outcome of the discussion is not "the best solution", but "good
> enough". This doc can be served as an example. Everyone involved in the
> development of auxbus and later usage of it, were focused on implementation,
> documentation was good enough as it didn't limit anyone who actually
> used it.
>
I get your point but still I think that the doc is misleading if it shows
a usage exmaple but practically no one should follow it.
Better to remove this usage exmaple completely IMHO.
>>
>> Adding gregkh here as he requested the auxiliary bus feature IIRC.
>> Greg - isn't the doc legit? should EXPORT_SYMBOLs necessarily be used
>> together with auxiliary bus rather than ops structure?
>
> This is not what you are doing here. You completely ditched EXPORT_SYMBOLs
> and reinvented module reference counting which overcomplicated the code
> just to avoid using standard kernel mechanism.
>
>> As we saw it, auxiliary bus gives us the flexibility to choose which
>> modules will be loaded while EXPORT_SYMBOLs enforces the dependencies
>> which might not be needed in some cases.
>>
>>>> Moreover, we'd like to support the mode where the IB or the ETH driver is
>>>> not loaded at all. But this cannot be achieved if we use EXPORT_SYMBOLs
>>>> exclusively for inter driver communication.
>>>
>>> It is not true and not how the kernel works. You can perfectly load core
>>> driver without IB and ETH, at some extent this is how mlx5 driver works.
>>>
>>
>> mlx5 IB driver doesn't export any symbol that is used by the core driver,
>> that's why the core driver can be loaded without the IB driver (althought
>> you'll get circular dependency if you would export).
>
> Yes, IB and ETH drivers are "users" of core driver. As RDMA maintainer,
> I'm reluctant to accept code that exports symbols from IB drivers to
> other subsystems. We have drivers/infiniband/core/ for that.
>
So we'll need to restructure the code to follow this limitation. We'll
take care of it for the next patch set version.
BTW if you won't allow such driver specific EXPORT_SYMBOLs, I think it is
good to have it documented similarly to other "don't do" guideliens in the
infiniband doc.
That's because in the net/ethernet subsystem for exmaple it is very common
to add such driver specific EXPORT_SYMBOLs.
>> If relying on exported symbols only, then our IB and ETH drivers will need
>> to export symbols too because the core driver accesses them post probing.
>
> So you should fix your core driver. This is exactly what auxbus model
> proposes.
>
>> Hence we won't be able to load the core driver without both of them (or
>> loading anything due to circular dependency).
>> Unless we'll use dynamic symbol lookup and I don't think that's your
>> intention.
>
> No it is not.
>
>>
>>>>
>>>>>>
>>>>>>>> + dev_err(hdev->dev, "Failed to increment %s module refcount\n",
>>>>>>>> + module_name(THIS_MODULE));
>>>>>>>> + rc = -EIO;
>>>>>>>> + goto module_get_err;
>>>>>>>> + }
>>>>>>>> +
>>>>>>>> + timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
>>>>>>>> + while (1) {
>>>>>>>> + aux_ops->hw_access_lock(aux_dev);
>>>>>>>> +
>>>>>>>> + /* if the device is operational, proceed to actual init while holding the lock in
>>>>>>>> + * order to prevent concurrent hard reset
>>>>>>>> + */
>>>>>>>> + if (aux_ops->device_operational(aux_dev))
>>>>>>>> + break;
>>>>>>>> +
>>>>>>>> + aux_ops->hw_access_unlock(aux_dev);
>>>>>>>> +
>>>>>>>> + if (ktime_compare(ktime_get(), timeout) > 0) {
>>>>>>>> + dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
>>>>>>>> + rc = -EBUSY;
>>>>>>>> + goto timeout_err;
>>>>>>>> + }
>>>>>>>> +
>>>>>>>> + dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing IB\n");
>>>>>>>> +
>>>>>>>> + msleep_interruptible(MSEC_PER_SEC);
>>>>>>>> + }
>>>>>>>
>>>>>>> The code above is unexpected.
>>>>>>>
>>>>>>
>>>>>> We have no control on when the user insmod the IB driver.
>>>>>
>>>>> It is not true, this is controlled through module dependencies
>>>>> mechanism.
>>>>>
>>>>
>>>> Yeah, if we would use EXPORT_SYMBOLs for inter driver communication but
>>>> we don't.
>>>
>>> So please use it and don't add complexity where it is not needed.
>>>
>>>>
>>>>>> As a result it is possible that the IB auxiliary device will be probed
>>>>>> while the compute device is under reset (due to some HW error).
>>>>>
>>>>> No, it is not possible. If you structure your driver right.
>>>>>
>>>>
>>>> Again, it is not possible if we would use EXPORT_SYMBOLs.
>>>> Please let me know if we misunderstood something because AFAIU we followed
>>>> the auxiliary bus doc usage example.
>>>
>>> It is better to follow actual drivers that use auxiliary bus and see how
>>> they implemented it and not rely on examples in the documentation.
>>>
>>
>> But isn't that what the doc for? to explain the guidelines? and it's not
>> that there is a big red note there of "this example should not be taken as
>> is, please look at your subsystem guidelines".
>
> At the beginning that doc was located in Documentation/ folder and no one
> really cared about it. After moving from Documentation/ to drivers/base/auxiliary.c,
> it became more visible, but still no one relied on it. You are first one
> who read.
>
> There is no subsystem rules here. Everyone relied on EXPORT_SYMBOLs and didn't
> use ops structure. Kernel is evolving project, there is no need to find a rule
> for everything.
>
> Thanks
>
>>
>>> Thanks
>>>
>>>>
>>>>> Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-24 8:47 ` Omer Shpigelman
@ 2024-06-24 9:10 ` Leon Romanovsky
0 siblings, 0 replies; 108+ messages in thread
From: Leon Romanovsky @ 2024-06-24 9:10 UTC (permalink / raw)
To: Omer Shpigelman
Cc: gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On Mon, Jun 24, 2024 at 08:47:41AM +0000, Omer Shpigelman wrote:
> On 6/19/24 13:52, Leon Romanovsky wrote:
> > On Wed, Jun 19, 2024 at 09:27:54AM +0000, Omer Shpigelman wrote:
> >> On 6/18/24 15:58, Leon Romanovsky wrote:
> >>> On Tue, Jun 18, 2024 at 11:08:34AM +0000, Omer Shpigelman wrote:
> >>>> On 6/17/24 22:04, Leon Romanovsky wrote:
> >>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >>>>>
> >>>>> On Mon, Jun 17, 2024 at 05:43:49PM +0000, Omer Shpigelman wrote:
> >>>>>> On 6/13/24 22:18, Leon Romanovsky wrote:
> >>>>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >>>>>>>
> >>>>>>> On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
> >>>>>>>> Add an RDMA driver of Gaudi ASICs family for AI scaling.
> >>>>>>>> The driver itself is agnostic to the ASIC in action, it operates according
> >>>>>>>> to the capabilities that were passed on device initialization.
> >>>>>>>> The device is initialized by the hbl_cn driver via auxiliary bus.
> >>>>>>>> The driver also supports QP resource tracking and port/device HW counters.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> >>>>>>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> >>>>>>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> >>>>>>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> >>>>>>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> >>>>>>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> >>>>>>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> >>>>>>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
> >>>>>>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
> >>>>>>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> >>>>>>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> >>>>>>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> >>>>>>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
> >>>>>>>
> >>>>>>> I afraid that you misinterpreted the "Co-developed-by" tag. All these
> >>>>>>> people are probably touch the code and not actually sit together at
> >>>>>>> the same room and write the code together. So, please remove the
> >>>>>>> extensive "Co-developed-by" tags.
> >>>>>>>
> >>>>>>> It is not full review yet, but simple pass-by-comments.
> >>>>>>>
> >>>>>>
> >>>>>> Actually except of two, all of the mentioned persons sat in the same room
> >>>>>> and developed the code together.
> >>>>>> The remaining two are located on a different site (but also together).
> >>>>>> Isn't that what "Co-developed-by" tag for?
> >>>>>> I wanted to give them credit for writing the code but I can remove if it's
> >>>>>> not common.
> >>>>>
> >>>>> Signed-off-by will be enough to give them credit.
> >>>>>
> >>>>
> >>>> Ok, good enough.
> >>>>
> >>>>>>
> >>>>>>>> ---
> >>>>>>>> MAINTAINERS | 10 +
> >>>>>>>> drivers/infiniband/Kconfig | 1 +
> >>>>>>>> drivers/infiniband/hw/Makefile | 1 +
> >>>>>>>> drivers/infiniband/hw/hbl/Kconfig | 17 +
> >>>>>>>> drivers/infiniband/hw/hbl/Makefile | 8 +
> >>>>>>>> drivers/infiniband/hw/hbl/hbl.h | 326 +++
> >>>>>>>> drivers/infiniband/hw/hbl/hbl_main.c | 478 ++++
> >>>>>>>> drivers/infiniband/hw/hbl/hbl_verbs.c | 2686 ++++++++++++++++++++++
> >>>>>>>> include/uapi/rdma/hbl-abi.h | 204 ++
> >>>>>>>> include/uapi/rdma/hbl_user_ioctl_cmds.h | 66 +
> >>>>>>>> include/uapi/rdma/hbl_user_ioctl_verbs.h | 106 +
> >>>>>>>> include/uapi/rdma/ib_user_ioctl_verbs.h | 1 +
> >>>>>>>> 12 files changed, 3904 insertions(+)
> >>>>>>>> create mode 100644 drivers/infiniband/hw/hbl/Kconfig
> >>>>>>>> create mode 100644 drivers/infiniband/hw/hbl/Makefile
> >>>>>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl.h
> >>>>>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl_main.c
> >>>>>>>> create mode 100644 drivers/infiniband/hw/hbl/hbl_verbs.c
> >>>>>>>> create mode 100644 include/uapi/rdma/hbl-abi.h
> >>>>>>>> create mode 100644 include/uapi/rdma/hbl_user_ioctl_cmds.h
> >>>>>>>> create mode 100644 include/uapi/rdma/hbl_user_ioctl_verbs.h
> >>>>>>>
> >>>>>>> <...>
> >>>>>>>
> >>>>>>>> +#define hbl_ibdev_emerg(ibdev, format, ...) ibdev_emerg(ibdev, format, ##__VA_ARGS__)
> >>>>>>>> +#define hbl_ibdev_alert(ibdev, format, ...) ibdev_alert(ibdev, format, ##__VA_ARGS__)
> >>>>>>>> +#define hbl_ibdev_crit(ibdev, format, ...) ibdev_crit(ibdev, format, ##__VA_ARGS__)
> >>>>>>>> +#define hbl_ibdev_err(ibdev, format, ...) ibdev_err(ibdev, format, ##__VA_ARGS__)
> >>>>>>>> +#define hbl_ibdev_warn(ibdev, format, ...) ibdev_warn(ibdev, format, ##__VA_ARGS__)
> >>>>>>>> +#define hbl_ibdev_notice(ibdev, format, ...) ibdev_notice(ibdev, format, ##__VA_ARGS__)
> >>>>>>>> +#define hbl_ibdev_info(ibdev, format, ...) ibdev_info(ibdev, format, ##__VA_ARGS__)
> >>>>>>>> +#define hbl_ibdev_dbg(ibdev, format, ...) ibdev_dbg(ibdev, format, ##__VA_ARGS__)
> >>>>>>>> +
> >>>>>>>> +#define hbl_ibdev_emerg_ratelimited(ibdev, fmt, ...) \
> >>>>>>>> + ibdev_emerg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>>>> +#define hbl_ibdev_alert_ratelimited(ibdev, fmt, ...) \
> >>>>>>>> + ibdev_alert_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>>>> +#define hbl_ibdev_crit_ratelimited(ibdev, fmt, ...) \
> >>>>>>>> + ibdev_crit_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>>>> +#define hbl_ibdev_err_ratelimited(ibdev, fmt, ...) \
> >>>>>>>> + ibdev_err_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>>>> +#define hbl_ibdev_warn_ratelimited(ibdev, fmt, ...) \
> >>>>>>>> + ibdev_warn_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>>>> +#define hbl_ibdev_notice_ratelimited(ibdev, fmt, ...) \
> >>>>>>>> + ibdev_notice_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>>>> +#define hbl_ibdev_info_ratelimited(ibdev, fmt, ...) \
> >>>>>>>> + ibdev_info_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>>>> +#define hbl_ibdev_dbg_ratelimited(ibdev, fmt, ...) \
> >>>>>>>> + ibdev_dbg_ratelimited(ibdev, fmt, ##__VA_ARGS__)
> >>>>>>>> +
> >>>>>>>
> >>>>>>> Please don't redefine the existing macros. Just use the existing ones.
> >>>>>>>
> >>>>>>>
> >>>>>>> <...>
> >>>>>>>
> >>>>>>
> >>>>>> That's a leftover from some debug code. I'll remove.
> >>>>>>
> >>>>>>>> + if (hbl_ib_match_netdev(ibdev, netdev))
> >>>>>>>> + ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
> >>>>>>>> + else
> >>>>>>>> + return NOTIFY_DONE;
> >>>>>>>
> >>>>>>> It is not kernel coding style. Please write:
> >>>>>>> if (!hbl_ib_match_netdev(ibdev, netdev))
> >>>>>>> return NOTIFY_DONE;
> >>>>>>>
> >>>>>>> ib_port = hbl_to_ib_port_num(hdev, netdev->dev_port);
> >>>>>>>
> >>>>>>
> >>>>>> I'll fix the code, thanks.
> >>>>>>
> >>>>>>>> +
> >>>>>>>
> >>>>>>> <...>
> >>>>>>>
> >>>>>>>> +static int hbl_ib_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
> >>>>>>>> +{
> >>>>>>>> + struct hbl_aux_dev *aux_dev = container_of(adev, struct hbl_aux_dev, adev);
> >>>>>>>> + struct hbl_ib_aux_ops *aux_ops = aux_dev->aux_ops;
> >>>>>>>> + struct hbl_ib_device *hdev;
> >>>>>>>> + ktime_t timeout;
> >>>>>>>> + int rc;
> >>>>>>>> +
> >>>>>>>> + rc = hdev_init(aux_dev);
> >>>>>>>> + if (rc) {
> >>>>>>>> + dev_err(&aux_dev->adev.dev, "Failed to init hdev\n");
> >>>>>>>> + return -EIO;
> >>>>>>>> + }
> >>>>>>>> +
> >>>>>>>> + hdev = aux_dev->priv;
> >>>>>>>> +
> >>>>>>>> + /* don't allow module unloading while it is attached */
> >>>>>>>> + if (!try_module_get(THIS_MODULE)) {
> >>>>>>>
> >>>>>>> This part makes wonder, what are you trying to do here? What doesn't work for you
> >>>>>>> in standard driver core and module load mechanism?
> >>>>>>>
> >>>>>>
> >>>>>> Before auxiliary bus was introduced, we used EXPORT_SYMBOLs for inter
> >>>>>> driver communication. That incremented the refcount of the used module so
> >>>>>> it couldn't be removed while it is in use.
> >>>>>> Auxiliary bus usage doesn't increment the used module refcount and hence
> >>>>>> the used module can be removed while it is in use and that's something
> >>>>>> we don't want to allow.
> >>>>>> We could solve it by some global locking or in_use atomic but the most
> >>>>>> simple and clean way is just to increment the used module refcount on
> >>>>>> auxiliary device probe and decrement it on auxiliary device removal.
> >>>>>
> >>>>> No, you was supposed to continue to use EXPORT_SYMBOLs and don't
> >>>>> invent auxiliary ops structure (this is why you lost module
> >>>>> reference counting).
> >>>>>
> >>>>
> >>>> Sorry, but according to the auxiliary bus doc, a domain-specific ops
> >>>> structure can be used.
> >>>> We followed the usage example described at drivers/base/auxiliary.c.
> >>>> What am I missing?
> >>>
> >>> Being the one who implemented auxiliary bus in the kernel and converted
> >>> number of drivers to use it, I strongly recommend do NOT follow the example
> >>> provided there.
> >>>
> >>> So you are missing "best practice", and "best practice" is to use
> >>> EXPORT_SYMBOLs and rely on module reference counting.
> >>>
> >>
> >> It is not just the usage example but also the general feature doc before
> >> it:
> >> "The generic behavior can be extended and specialized as needed by
> >> encapsulating an auxiliary_device within other domain-specific structures
> >> and the use of .ops callbacks."
> >> It is also mentioned there that the ops structure are used for specific
> >> auxiliary device operations while EXPORT_SYMBOLs should be used for common
> >> infrastrucure the parent driver exposes:
> >> "Note that ops are intended as a way to augment instance behavior within a
> >> class of auxiliary devices, it is not the mechanism for exporting common
> >> infrastructure from the parent."
> >> All of our ops callbacks are meant to provide functionality related to the
> >> auxiliary device, they are not just general/common infrastructure.
> >
> > Of course they are common, otherwise why did you put them in common code?
> > For example, you have callbacks to lock and unlock internal HW access,
> > how is it not common?
> >
>
> As I saw it, the "common" functions are general capabilities the parent
> driver exposes, not necessaritly related to the auxiliary device.
> But let me revisit this and try to restructure the code so the parent
> driver will use EXPORT_SYMBOLs.
>
> >>
> >> Why do we have this doc if we should ignore it? why wasn't the doc
> >> modified according to the "best practice" you described? the doc is
> >> misleading.
> >
> > Because this is how upstream kernel development works. We are trying to
> > come to the agreement and get the best solution for the problem. Sometimes,
> > the outcome of the discussion is not "the best solution", but "good
> > enough". This doc can be served as an example. Everyone involved in the
> > development of auxbus and later usage of it, were focused on implementation,
> > documentation was good enough as it didn't limit anyone who actually
> > used it.
> >
>
> I get your point but still I think that the doc is misleading if it shows
> a usage exmaple but practically no one should follow it.
> Better to remove this usage exmaple completely IMHO.
We (developers) didn't want that example in first place. I'm not going
to argue again in order to attempt to remove it.
>
> >>
> >> Adding gregkh here as he requested the auxiliary bus feature IIRC.
> >> Greg - isn't the doc legit? should EXPORT_SYMBOLs necessarily be used
> >> together with auxiliary bus rather than ops structure?
> >
> > This is not what you are doing here. You completely ditched EXPORT_SYMBOLs
> > and reinvented module reference counting which overcomplicated the code
> > just to avoid using standard kernel mechanism.
> >
> >> As we saw it, auxiliary bus gives us the flexibility to choose which
> >> modules will be loaded while EXPORT_SYMBOLs enforces the dependencies
> >> which might not be needed in some cases.
> >>
> >>>> Moreover, we'd like to support the mode where the IB or the ETH driver is
> >>>> not loaded at all. But this cannot be achieved if we use EXPORT_SYMBOLs
> >>>> exclusively for inter driver communication.
> >>>
> >>> It is not true and not how the kernel works. You can perfectly load core
> >>> driver without IB and ETH, at some extent this is how mlx5 driver works.
> >>>
> >>
> >> mlx5 IB driver doesn't export any symbol that is used by the core driver,
> >> that's why the core driver can be loaded without the IB driver (althought
> >> you'll get circular dependency if you would export).
> >
> > Yes, IB and ETH drivers are "users" of core driver. As RDMA maintainer,
> > I'm reluctant to accept code that exports symbols from IB drivers to
> > other subsystems. We have drivers/infiniband/core/ for that.
> >
>
> So we'll need to restructure the code to follow this limitation. We'll
> take care of it for the next patch set version.
> BTW if you won't allow such driver specific EXPORT_SYMBOLs, I think it is
> good to have it documented similarly to other "don't do" guideliens in the
> infiniband doc.
> That's because in the net/ethernet subsystem for exmaple it is very common
> to add such driver specific EXPORT_SYMBOLs.
Yes, this is technical limitation, it is because PCI core (driver common code)
is located in drivers/net and not because of policy to accept EXPORT_SYMBOLs
in netdev.
If you put your driver common code in other place, you won't need any EXPORT_SYMBOLs
in drivers/net.
>
> >> If relying on exported symbols only, then our IB and ETH drivers will need
> >> to export symbols too because the core driver accesses them post probing.
> >
> > So you should fix your core driver. This is exactly what auxbus model
> > proposes.
> >
> >> Hence we won't be able to load the core driver without both of them (or
> >> loading anything due to circular dependency).
> >> Unless we'll use dynamic symbol lookup and I don't think that's your
> >> intention.
> >
> > No it is not.
> >
> >>
> >>>>
> >>>>>>
> >>>>>>>> + dev_err(hdev->dev, "Failed to increment %s module refcount\n",
> >>>>>>>> + module_name(THIS_MODULE));
> >>>>>>>> + rc = -EIO;
> >>>>>>>> + goto module_get_err;
> >>>>>>>> + }
> >>>>>>>> +
> >>>>>>>> + timeout = ktime_add_ms(ktime_get(), hdev->pending_reset_long_timeout * MSEC_PER_SEC);
> >>>>>>>> + while (1) {
> >>>>>>>> + aux_ops->hw_access_lock(aux_dev);
> >>>>>>>> +
> >>>>>>>> + /* if the device is operational, proceed to actual init while holding the lock in
> >>>>>>>> + * order to prevent concurrent hard reset
> >>>>>>>> + */
> >>>>>>>> + if (aux_ops->device_operational(aux_dev))
> >>>>>>>> + break;
> >>>>>>>> +
> >>>>>>>> + aux_ops->hw_access_unlock(aux_dev);
> >>>>>>>> +
> >>>>>>>> + if (ktime_compare(ktime_get(), timeout) > 0) {
> >>>>>>>> + dev_err(hdev->dev, "Timeout while waiting for hard reset to finish\n");
> >>>>>>>> + rc = -EBUSY;
> >>>>>>>> + goto timeout_err;
> >>>>>>>> + }
> >>>>>>>> +
> >>>>>>>> + dev_notice_once(hdev->dev, "Waiting for hard reset to finish before probing IB\n");
> >>>>>>>> +
> >>>>>>>> + msleep_interruptible(MSEC_PER_SEC);
> >>>>>>>> + }
> >>>>>>>
> >>>>>>> The code above is unexpected.
> >>>>>>>
> >>>>>>
> >>>>>> We have no control on when the user insmod the IB driver.
> >>>>>
> >>>>> It is not true, this is controlled through module dependencies
> >>>>> mechanism.
> >>>>>
> >>>>
> >>>> Yeah, if we would use EXPORT_SYMBOLs for inter driver communication but
> >>>> we don't.
> >>>
> >>> So please use it and don't add complexity where it is not needed.
> >>>
> >>>>
> >>>>>> As a result it is possible that the IB auxiliary device will be probed
> >>>>>> while the compute device is under reset (due to some HW error).
> >>>>>
> >>>>> No, it is not possible. If you structure your driver right.
> >>>>>
> >>>>
> >>>> Again, it is not possible if we would use EXPORT_SYMBOLs.
> >>>> Please let me know if we misunderstood something because AFAIU we followed
> >>>> the auxiliary bus doc usage example.
> >>>
> >>> It is better to follow actual drivers that use auxiliary bus and see how
> >>> they implemented it and not rely on examples in the documentation.
> >>>
> >>
> >> But isn't that what the doc for? to explain the guidelines? and it's not
> >> that there is a big red note there of "this example should not be taken as
> >> is, please look at your subsystem guidelines".
> >
> > At the beginning that doc was located in Documentation/ folder and no one
> > really cared about it. After moving from Documentation/ to drivers/base/auxiliary.c,
> > it became more visible, but still no one relied on it. You are first one
> > who read.
> >
> > There is no subsystem rules here. Everyone relied on EXPORT_SYMBOLs and didn't
> > use ops structure. Kernel is evolving project, there is no need to find a rule
> > for everything.
> >
> > Thanks
> >
> >>
> >>> Thanks
> >>>
> >>>>
> >>>>> Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-19 10:52 ` Leon Romanovsky
2024-06-24 8:47 ` Omer Shpigelman
@ 2024-06-28 10:24 ` Omer Shpigelman
2024-06-30 13:29 ` Leon Romanovsky
2024-07-12 13:08 ` Jason Gunthorpe
1 sibling, 2 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-28 10:24 UTC (permalink / raw)
To: Leon Romanovsky
Cc: gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On 6/19/24 13:52, Leon Romanovsky wrote:
> On Wed, Jun 19, 2024 at 09:27:54AM +0000, Omer Shpigelman wrote:
>> On 6/18/24 15:58, Leon Romanovsky wrote:
>>> On Tue, Jun 18, 2024 at 11:08:34AM +0000, Omer Shpigelman wrote:
>>>> On 6/17/24 22:04, Leon Romanovsky wrote:
>>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>>
>>>>> On Mon, Jun 17, 2024 at 05:43:49PM +0000, Omer Shpigelman wrote:
>>>>>> On 6/13/24 22:18, Leon Romanovsky wrote:
>>>>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>>>>
>>>>>>> On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
>>>>>>>> Add an RDMA driver of Gaudi ASICs family for AI scaling.
>>>>>>>> The driver itself is agnostic to the ASIC in action, it operates according
>>>>>>>> to the capabilities that were passed on device initialization.
>>>>>>>> The device is initialized by the hbl_cn driver via auxiliary bus.
>>>>>>>> The driver also supports QP resource tracking and port/device HW counters.
>>>>>>>>
>>>>>>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
>>>>>>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
>>>>>>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
>>>>>>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
>>>>>>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
>>>>>>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
>>>>>>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
>>>>>>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
>>>>>>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
>>>>>>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
>>>>>>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
>>>>>>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
>>>>>>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
>>>>>>>
<...>
>> mlx5 IB driver doesn't export any symbol that is used by the core driver,
>> that's why the core driver can be loaded without the IB driver (althought
>> you'll get circular dependency if you would export).
>
> Yes, IB and ETH drivers are "users" of core driver. As RDMA maintainer,
> I'm reluctant to accept code that exports symbols from IB drivers to
> other subsystems. We have drivers/infiniband/core/ for that.
>
We need the core driver to access the IB driver (and to the ETH driver as
well). As you wrote, we can't use exported symbols from our IB driver nor
rely on function pointers, but what about providing the core driver an ops
structure? meaning exporting a register function from the core driver that
should be called by the IB driver during auxiliary device probe.
Something like:
int hbl_cn_register_ib_aux_dev(struct auxiliary_device *adev,
struct hbl_ib_ops *ops)
{
...
}
EXPORT_SYMBOL(hbl_cn_register_ib_aux_dev);
That's how only the parent driver exports symbols to the son driver so the
IB driver is a "user" of the core driver and so we count on the internal
module reference counter. But we also get the ability to access the IB
driver from the core driver (to report a HW error for example).
>> If relying on exported symbols only, then our IB and ETH drivers will need
>> to export symbols too because the core driver accesses them post probing.
>
> So you should fix your core driver. This is exactly what auxbus model
> proposes.
>
>> Hence we won't be able to load the core driver without both of them (or
>> loading anything due to circular dependency).
>> Unless we'll use dynamic symbol lookup and I don't think that's your
>> intention.
>
> No it is not.
>
<...>
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-28 10:24 ` Omer Shpigelman
@ 2024-06-30 13:29 ` Leon Romanovsky
2024-07-01 10:46 ` Omer Shpigelman
2024-07-12 13:08 ` Jason Gunthorpe
1 sibling, 1 reply; 108+ messages in thread
From: Leon Romanovsky @ 2024-06-30 13:29 UTC (permalink / raw)
To: Omer Shpigelman
Cc: gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On Fri, Jun 28, 2024 at 10:24:32AM +0000, Omer Shpigelman wrote:
> On 6/19/24 13:52, Leon Romanovsky wrote:
> > On Wed, Jun 19, 2024 at 09:27:54AM +0000, Omer Shpigelman wrote:
> >> On 6/18/24 15:58, Leon Romanovsky wrote:
> >>> On Tue, Jun 18, 2024 at 11:08:34AM +0000, Omer Shpigelman wrote:
> >>>> On 6/17/24 22:04, Leon Romanovsky wrote:
> >>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >>>>>
> >>>>> On Mon, Jun 17, 2024 at 05:43:49PM +0000, Omer Shpigelman wrote:
> >>>>>> On 6/13/24 22:18, Leon Romanovsky wrote:
> >>>>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >>>>>>>
> >>>>>>> On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
> >>>>>>>> Add an RDMA driver of Gaudi ASICs family for AI scaling.
> >>>>>>>> The driver itself is agnostic to the ASIC in action, it operates according
> >>>>>>>> to the capabilities that were passed on device initialization.
> >>>>>>>> The device is initialized by the hbl_cn driver via auxiliary bus.
> >>>>>>>> The driver also supports QP resource tracking and port/device HW counters.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> >>>>>>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> >>>>>>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> >>>>>>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> >>>>>>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> >>>>>>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> >>>>>>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> >>>>>>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
> >>>>>>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
> >>>>>>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> >>>>>>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> >>>>>>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> >>>>>>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
> >>>>>>>
>
> <...>
>
> >> mlx5 IB driver doesn't export any symbol that is used by the core driver,
> >> that's why the core driver can be loaded without the IB driver (althought
> >> you'll get circular dependency if you would export).
> >
> > Yes, IB and ETH drivers are "users" of core driver. As RDMA maintainer,
> > I'm reluctant to accept code that exports symbols from IB drivers to
> > other subsystems. We have drivers/infiniband/core/ for that.
> >
>
> We need the core driver to access the IB driver (and to the ETH driver as
> well). As you wrote, we can't use exported symbols from our IB driver nor
> rely on function pointers, but what about providing the core driver an ops
> structure? meaning exporting a register function from the core driver that
> should be called by the IB driver during auxiliary device probe.
> Something like:
>
> int hbl_cn_register_ib_aux_dev(struct auxiliary_device *adev,
> struct hbl_ib_ops *ops)
> {
> ...
> }
> EXPORT_SYMBOL(hbl_cn_register_ib_aux_dev);
>
> That's how only the parent driver exports symbols to the son driver so the
> IB driver is a "user" of the core driver and so we count on the internal
> module reference counter. But we also get the ability to access the IB
> driver from the core driver (to report a HW error for example).
Before you are talking about solutions, please explain in technical
terms why you absolutely need to access IB from core driver and any
other possible way is not possible.
Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-30 13:29 ` Leon Romanovsky
@ 2024-07-01 10:46 ` Omer Shpigelman
2024-07-01 12:46 ` Leon Romanovsky
0 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-07-01 10:46 UTC (permalink / raw)
To: Leon Romanovsky
Cc: gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On 6/30/24 16:29, Leon Romanovsky wrote:
> On Fri, Jun 28, 2024 at 10:24:32AM +0000, Omer Shpigelman wrote:
>> On 6/19/24 13:52, Leon Romanovsky wrote:
>>> On Wed, Jun 19, 2024 at 09:27:54AM +0000, Omer Shpigelman wrote:
>>>> On 6/18/24 15:58, Leon Romanovsky wrote:
>>>>> On Tue, Jun 18, 2024 at 11:08:34AM +0000, Omer Shpigelman wrote:
>>>>>> On 6/17/24 22:04, Leon Romanovsky wrote:
>>>>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>>>>
>>>>>>> On Mon, Jun 17, 2024 at 05:43:49PM +0000, Omer Shpigelman wrote:
>>>>>>>> On 6/13/24 22:18, Leon Romanovsky wrote:
>>>>>>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>>>>>>
>>>>>>>>> On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
>>>>>>>>>> Add an RDMA driver of Gaudi ASICs family for AI scaling.
>>>>>>>>>> The driver itself is agnostic to the ASIC in action, it operates according
>>>>>>>>>> to the capabilities that were passed on device initialization.
>>>>>>>>>> The device is initialized by the hbl_cn driver via auxiliary bus.
>>>>>>>>>> The driver also supports QP resource tracking and port/device HW counters.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
>>>>>>>>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
>>>>>>>>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
>>>>>>>>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
>>>>>>>>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
>>>>>>>>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
>>>>>>>>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
>>>>>>>>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
>>>>>>>>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
>>>>>>>>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
>>>>>>>>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
>>>>>>>>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
>>>>>>>>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
>>>>>>>>>
>>
>> <...>
>>
>>>> mlx5 IB driver doesn't export any symbol that is used by the core driver,
>>>> that's why the core driver can be loaded without the IB driver (althought
>>>> you'll get circular dependency if you would export).
>>>
>>> Yes, IB and ETH drivers are "users" of core driver. As RDMA maintainer,
>>> I'm reluctant to accept code that exports symbols from IB drivers to
>>> other subsystems. We have drivers/infiniband/core/ for that.
>>>
>>
>> We need the core driver to access the IB driver (and to the ETH driver as
>> well). As you wrote, we can't use exported symbols from our IB driver nor
>> rely on function pointers, but what about providing the core driver an ops
>> structure? meaning exporting a register function from the core driver that
>> should be called by the IB driver during auxiliary device probe.
>> Something like:
>>
>> int hbl_cn_register_ib_aux_dev(struct auxiliary_device *adev,
>> struct hbl_ib_ops *ops)
>> {
>> ...
>> }
>> EXPORT_SYMBOL(hbl_cn_register_ib_aux_dev);
>>
>> That's how only the parent driver exports symbols to the son driver so the
>> IB driver is a "user" of the core driver and so we count on the internal
>> module reference counter. But we also get the ability to access the IB
>> driver from the core driver (to report a HW error for example).
>
> Before you are talking about solutions, please explain in technical
> terms why you absolutely need to access IB from core driver and any
> other possible way is not possible.
>
> Thanks
First of all, as a general assumption, everything we do today can also be
done with unidirectional drivers communication only. If the parent driver
cannot access the son driver directly, then we can have a blocking command
queue on the parent side that the parent driver will push to it and the
son driver will fetch from it, execute the command and unblock the parent.
That will work but it adds complexity which I'm not sure that is needed.
The second point is not necessarily about the direction of the
communication but more about generally using function pointers rather than
exported symbols - we have 2 flavors of functions for inter driver
communications: common functions and ASIC specific functions. The ASIC
specific functions are exposed and initialized per ASIC. If we convert
them to EXPORT_SYMBOLs then we expose ASIC specific functions regardless
of the ASIC in action.
Again, that will work but seems unnecessary. We can check the ASIC type
that was passed in each exported function and fail if a wrong ASIC type
was used, but it seems to me like an incorrect approach to use exported
symbols for ASIC specific communication. EXPORT_SYMBOLs were meant to be
used for driver level communication, not for utilizing device specific
capabilities. For that, an ops struct seems more appropriate.
That's why I'm suggesting to combine both exported symbols and function
pointers.
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-07-01 10:46 ` Omer Shpigelman
@ 2024-07-01 12:46 ` Leon Romanovsky
0 siblings, 0 replies; 108+ messages in thread
From: Leon Romanovsky @ 2024-07-01 12:46 UTC (permalink / raw)
To: Omer Shpigelman
Cc: gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
dri-devel@lists.freedesktop.org, ogabbay@kernel.org,
Zvika Yehudai
On Mon, Jul 01, 2024 at 10:46:48AM +0000, Omer Shpigelman wrote:
> On 6/30/24 16:29, Leon Romanovsky wrote:
> > On Fri, Jun 28, 2024 at 10:24:32AM +0000, Omer Shpigelman wrote:
> >> On 6/19/24 13:52, Leon Romanovsky wrote:
> >>> On Wed, Jun 19, 2024 at 09:27:54AM +0000, Omer Shpigelman wrote:
> >>>> On 6/18/24 15:58, Leon Romanovsky wrote:
> >>>>> On Tue, Jun 18, 2024 at 11:08:34AM +0000, Omer Shpigelman wrote:
> >>>>>> On 6/17/24 22:04, Leon Romanovsky wrote:
> >>>>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >>>>>>>
> >>>>>>> On Mon, Jun 17, 2024 at 05:43:49PM +0000, Omer Shpigelman wrote:
> >>>>>>>> On 6/13/24 22:18, Leon Romanovsky wrote:
> >>>>>>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >>>>>>>>>
> >>>>>>>>> On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
> >>>>>>>>>> Add an RDMA driver of Gaudi ASICs family for AI scaling.
> >>>>>>>>>> The driver itself is agnostic to the ASIC in action, it operates according
> >>>>>>>>>> to the capabilities that were passed on device initialization.
> >>>>>>>>>> The device is initialized by the hbl_cn driver via auxiliary bus.
> >>>>>>>>>> The driver also supports QP resource tracking and port/device HW counters.
> >>>>>>>>>>
> >>>>>>>>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
> >>>>>>>>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
> >>>>>>>>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
> >>>>>>>>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
> >>>>>>>>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
> >>>>>>>>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
> >>>>>>>>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
> >>>>>>>>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
> >>>>>>>>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
> >>>>>>>>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
> >>>>>>>>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
> >>>>>>>>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
> >>>>>>>>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
> >>>>>>>>>
> >>
> >> <...>
> >>
> >>>> mlx5 IB driver doesn't export any symbol that is used by the core driver,
> >>>> that's why the core driver can be loaded without the IB driver (althought
> >>>> you'll get circular dependency if you would export).
> >>>
> >>> Yes, IB and ETH drivers are "users" of core driver. As RDMA maintainer,
> >>> I'm reluctant to accept code that exports symbols from IB drivers to
> >>> other subsystems. We have drivers/infiniband/core/ for that.
> >>>
> >>
> >> We need the core driver to access the IB driver (and to the ETH driver as
> >> well). As you wrote, we can't use exported symbols from our IB driver nor
> >> rely on function pointers, but what about providing the core driver an ops
> >> structure? meaning exporting a register function from the core driver that
> >> should be called by the IB driver during auxiliary device probe.
> >> Something like:
> >>
> >> int hbl_cn_register_ib_aux_dev(struct auxiliary_device *adev,
> >> struct hbl_ib_ops *ops)
> >> {
> >> ...
> >> }
> >> EXPORT_SYMBOL(hbl_cn_register_ib_aux_dev);
> >>
> >> That's how only the parent driver exports symbols to the son driver so the
> >> IB driver is a "user" of the core driver and so we count on the internal
> >> module reference counter. But we also get the ability to access the IB
> >> driver from the core driver (to report a HW error for example).
> >
> > Before you are talking about solutions, please explain in technical
> > terms why you absolutely need to access IB from core driver and any
> > other possible way is not possible.
> >
> > Thanks
>
> First of all, as a general assumption, everything we do today can also be
> done with unidirectional drivers communication only. If the parent driver
> cannot access the son driver directly, then we can have a blocking command
> queue on the parent side that the parent driver will push to it and the
> son driver will fetch from it, execute the command and unblock the parent.
> That will work but it adds complexity which I'm not sure that is needed.
> The second point is not necessarily about the direction of the
> communication but more about generally using function pointers rather than
> exported symbols - we have 2 flavors of functions for inter driver
> communications: common functions and ASIC specific functions. The ASIC
> specific functions are exposed and initialized per ASIC. If we convert
> them to EXPORT_SYMBOLs then we expose ASIC specific functions regardless
> of the ASIC in action.
> Again, that will work but seems unnecessary. We can check the ASIC type
> that was passed in each exported function and fail if a wrong ASIC type
> was used, but it seems to me like an incorrect approach to use exported
> symbols for ASIC specific communication. EXPORT_SYMBOLs were meant to be
> used for driver level communication, not for utilizing device specific
> capabilities. For that, an ops struct seems more appropriate.
> That's why I'm suggesting to combine both exported symbols and function
> pointers.
Thanks for the explanation. I understand your concerns, but I don't see
any technical justification for the need to access IB driver from the
core.
Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-28 10:24 ` Omer Shpigelman
2024-06-30 13:29 ` Leon Romanovsky
@ 2024-07-12 13:08 ` Jason Gunthorpe
2024-07-14 10:18 ` Omer Shpigelman
1 sibling, 1 reply; 108+ messages in thread
From: Jason Gunthorpe @ 2024-07-12 13:08 UTC (permalink / raw)
To: Omer Shpigelman
Cc: Leon Romanovsky, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On Fri, Jun 28, 2024 at 10:24:32AM +0000, Omer Shpigelman wrote:
> We need the core driver to access the IB driver (and to the ETH driver as
> well). As you wrote, we can't use exported symbols from our IB driver nor
> rely on function pointers, but what about providing the core driver an ops
> structure? meaning exporting a register function from the core driver that
> should be called by the IB driver during auxiliary device probe.
> Something like:
>
> int hbl_cn_register_ib_aux_dev(struct auxiliary_device *adev,
> struct hbl_ib_ops *ops)
> {
> ...
> }
> EXPORT_SYMBOL(hbl_cn_register_ib_aux_dev);
Definately do not do some kind of double-register like this.
The auxiliary_device scheme can already be extended to provide ops for
each sub device.
Like
struct habana_driver {
struct auxiliary_driver base;
const struct habana_ops *ops;
};
If the ops are justified or not is a different question.
> module reference counter. But we also get the ability to access the IB
> driver from the core driver (to report a HW error for example).
Report a HW error seems reasonable to me
Other driver have used notifier chains for this kind of stuff though.
Jason
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-07-12 13:08 ` Jason Gunthorpe
@ 2024-07-14 10:18 ` Omer Shpigelman
2024-07-16 13:40 ` Jason Gunthorpe
0 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-07-14 10:18 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Leon Romanovsky, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 7/12/24 16:08, Jason Gunthorpe wrote:
> [You don't often get email from jgg@ziepe.ca. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On Fri, Jun 28, 2024 at 10:24:32AM +0000, Omer Shpigelman wrote:
>
>> We need the core driver to access the IB driver (and to the ETH driver as
>> well). As you wrote, we can't use exported symbols from our IB driver nor
>> rely on function pointers, but what about providing the core driver an ops
>> structure? meaning exporting a register function from the core driver that
>> should be called by the IB driver during auxiliary device probe.
>> Something like:
>>
>> int hbl_cn_register_ib_aux_dev(struct auxiliary_device *adev,
>> struct hbl_ib_ops *ops)
>> {
>> ...
>> }
>> EXPORT_SYMBOL(hbl_cn_register_ib_aux_dev);
>
> Definately do not do some kind of double-register like this.
>
> The auxiliary_device scheme can already be extended to provide ops for
> each sub device.
>
> Like
>
> struct habana_driver {
> struct auxiliary_driver base;
> const struct habana_ops *ops;
> };
>
> If the ops are justified or not is a different question.
>
Well, I suggested this double-register option because I got a comment that
the design pattern of embedded ops structure shouldn't be used.
So I'm confused now...
>> module reference counter. But we also get the ability to access the IB
>> driver from the core driver (to report a HW error for example).
>
> Report a HW error seems reasonable to me
>
> Other driver have used notifier chains for this kind of stuff though.
>
> Jason
I'll look into the option of using notifier chains in this case, although
as I saw it, the notifier chains are more suitable for broadcast updates
where the updater is not necessarily aware of the identity nor the number
of the subscribers. It looks kind of overkill for our error reporting case
which is simpler.
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-07-14 10:18 ` Omer Shpigelman
@ 2024-07-16 13:40 ` Jason Gunthorpe
2024-07-17 7:08 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Jason Gunthorpe @ 2024-07-16 13:40 UTC (permalink / raw)
To: Omer Shpigelman
Cc: Leon Romanovsky, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On Sun, Jul 14, 2024 at 10:18:12AM +0000, Omer Shpigelman wrote:
> On 7/12/24 16:08, Jason Gunthorpe wrote:
> > [You don't often get email from jgg@ziepe.ca. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > On Fri, Jun 28, 2024 at 10:24:32AM +0000, Omer Shpigelman wrote:
> >
> >> We need the core driver to access the IB driver (and to the ETH driver as
> >> well). As you wrote, we can't use exported symbols from our IB driver nor
> >> rely on function pointers, but what about providing the core driver an ops
> >> structure? meaning exporting a register function from the core driver that
> >> should be called by the IB driver during auxiliary device probe.
> >> Something like:
> >>
> >> int hbl_cn_register_ib_aux_dev(struct auxiliary_device *adev,
> >> struct hbl_ib_ops *ops)
> >> {
> >> ...
> >> }
> >> EXPORT_SYMBOL(hbl_cn_register_ib_aux_dev);
> >
> > Definately do not do some kind of double-register like this.
> >
> > The auxiliary_device scheme can already be extended to provide ops for
> > each sub device.
> >
> > Like
> >
> > struct habana_driver {
> > struct auxiliary_driver base;
> > const struct habana_ops *ops;
> > };
> >
> > If the ops are justified or not is a different question.
> >
>
> Well, I suggested this double-register option because I got a comment that
> the design pattern of embedded ops structure shouldn't be used.
> So I'm confused now...
Yeah, don't stick ops in random places, but the device_driver is the
right place.
> I'll look into the option of using notifier chains in this case, although
> as I saw it, the notifier chains are more suitable for broadcast updates
> where the updater is not necessarily aware of the identity nor the number
> of the subscribers.
Yes, that is right.
Jason
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-07-16 13:40 ` Jason Gunthorpe
@ 2024-07-17 7:08 ` Omer Shpigelman
2024-07-17 7:36 ` Leon Romanovsky
0 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-07-17 7:08 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Leon Romanovsky, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 7/16/24 16:40, Jason Gunthorpe wrote:
> On Sun, Jul 14, 2024 at 10:18:12AM +0000, Omer Shpigelman wrote:
>> On 7/12/24 16:08, Jason Gunthorpe wrote:
>>> [You don't often get email from jgg@ziepe.ca. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>
>>> On Fri, Jun 28, 2024 at 10:24:32AM +0000, Omer Shpigelman wrote:
>>>
>>>> We need the core driver to access the IB driver (and to the ETH driver as
>>>> well). As you wrote, we can't use exported symbols from our IB driver nor
>>>> rely on function pointers, but what about providing the core driver an ops
>>>> structure? meaning exporting a register function from the core driver that
>>>> should be called by the IB driver during auxiliary device probe.
>>>> Something like:
>>>>
>>>> int hbl_cn_register_ib_aux_dev(struct auxiliary_device *adev,
>>>> struct hbl_ib_ops *ops)
>>>> {
>>>> ...
>>>> }
>>>> EXPORT_SYMBOL(hbl_cn_register_ib_aux_dev);
>>>
>>> Definately do not do some kind of double-register like this.
>>>
>>> The auxiliary_device scheme can already be extended to provide ops for
>>> each sub device.
>>>
>>> Like
>>>
>>> struct habana_driver {
>>> struct auxiliary_driver base;
>>> const struct habana_ops *ops;
>>> };
>>>
>>> If the ops are justified or not is a different question.
>>>
>>
>> Well, I suggested this double-register option because I got a comment that
>> the design pattern of embedded ops structure shouldn't be used.
>> So I'm confused now...
>
> Yeah, don't stick ops in random places, but the device_driver is the
> right place.
>
Sorry, let me explain again. My original code has an ops structure
exactly like you are suggesting now (see struct hbl_aux_dev in the first
patch of the series). But I was instructed not to use this ops structure
and to rely on exported symbols for inter-driver communication.
I'll be happy to use this ops structure like in your example rather than
converting my code to use exported symbols.
Leon - am I missing anything? what's the verdict here?
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-07-17 7:08 ` Omer Shpigelman
@ 2024-07-17 7:36 ` Leon Romanovsky
2024-07-17 10:51 ` Omer Shpigelman
0 siblings, 1 reply; 108+ messages in thread
From: Leon Romanovsky @ 2024-07-17 7:36 UTC (permalink / raw)
To: Omer Shpigelman
Cc: Jason Gunthorpe, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On Wed, Jul 17, 2024 at 07:08:59AM +0000, Omer Shpigelman wrote:
> On 7/16/24 16:40, Jason Gunthorpe wrote:
> > On Sun, Jul 14, 2024 at 10:18:12AM +0000, Omer Shpigelman wrote:
> >> On 7/12/24 16:08, Jason Gunthorpe wrote:
> >>> [You don't often get email from jgg@ziepe.ca. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >>>
> >>> On Fri, Jun 28, 2024 at 10:24:32AM +0000, Omer Shpigelman wrote:
> >>>
> >>>> We need the core driver to access the IB driver (and to the ETH driver as
> >>>> well). As you wrote, we can't use exported symbols from our IB driver nor
> >>>> rely on function pointers, but what about providing the core driver an ops
> >>>> structure? meaning exporting a register function from the core driver that
> >>>> should be called by the IB driver during auxiliary device probe.
> >>>> Something like:
> >>>>
> >>>> int hbl_cn_register_ib_aux_dev(struct auxiliary_device *adev,
> >>>> struct hbl_ib_ops *ops)
> >>>> {
> >>>> ...
> >>>> }
> >>>> EXPORT_SYMBOL(hbl_cn_register_ib_aux_dev);
> >>>
> >>> Definately do not do some kind of double-register like this.
> >>>
> >>> The auxiliary_device scheme can already be extended to provide ops for
> >>> each sub device.
> >>>
> >>> Like
> >>>
> >>> struct habana_driver {
> >>> struct auxiliary_driver base;
> >>> const struct habana_ops *ops;
> >>> };
> >>>
> >>> If the ops are justified or not is a different question.
> >>>
> >>
> >> Well, I suggested this double-register option because I got a comment that
> >> the design pattern of embedded ops structure shouldn't be used.
> >> So I'm confused now...
> >
> > Yeah, don't stick ops in random places, but the device_driver is the
> > right place.
> >
>
> Sorry, let me explain again. My original code has an ops structure
> exactly like you are suggesting now (see struct hbl_aux_dev in the first
> patch of the series). But I was instructed not to use this ops structure
> and to rely on exported symbols for inter-driver communication.
> I'll be happy to use this ops structure like in your example rather than
> converting my code to use exported symbols.
> Leon - am I missing anything? what's the verdict here?
You are missing the main sentence from Jason's response: "don't stick ops in random places".
It is fine to have ops in device driver, so the core driver can call them. However, in your
original code, you added ops everywhere. It caused to the need to implement module reference
counting and crazy stuff like calls to lock and unlock functions from the aux driver to the core.
Verdict is still the same. Core driver should provide EXPORT_SYMBOLs, so the aux driver can call
them directly and enjoy from proper module loading and unloading.
The aux driver can have ops in the device driver, so the core driver can call them to perform something
specific for that aux driver.
Calls between aux drivers should be done via the core driver.
Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-07-17 7:36 ` Leon Romanovsky
@ 2024-07-17 10:51 ` Omer Shpigelman
2024-07-17 11:56 ` Jason Gunthorpe
2024-07-17 12:33 ` Leon Romanovsky
0 siblings, 2 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-07-17 10:51 UTC (permalink / raw)
To: Leon Romanovsky
Cc: Jason Gunthorpe, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 7/17/24 10:36, Leon Romanovsky wrote:
> On Wed, Jul 17, 2024 at 07:08:59AM +0000, Omer Shpigelman wrote:
>> On 7/16/24 16:40, Jason Gunthorpe wrote:
>>> On Sun, Jul 14, 2024 at 10:18:12AM +0000, Omer Shpigelman wrote:
>>>> On 7/12/24 16:08, Jason Gunthorpe wrote:
>>>>> [You don't often get email from jgg@ziepe.ca. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>>
>>>>> On Fri, Jun 28, 2024 at 10:24:32AM +0000, Omer Shpigelman wrote:
>>>>>
>>>>>> We need the core driver to access the IB driver (and to the ETH driver as
>>>>>> well). As you wrote, we can't use exported symbols from our IB driver nor
>>>>>> rely on function pointers, but what about providing the core driver an ops
>>>>>> structure? meaning exporting a register function from the core driver that
>>>>>> should be called by the IB driver during auxiliary device probe.
>>>>>> Something like:
>>>>>>
>>>>>> int hbl_cn_register_ib_aux_dev(struct auxiliary_device *adev,
>>>>>> struct hbl_ib_ops *ops)
>>>>>> {
>>>>>> ...
>>>>>> }
>>>>>> EXPORT_SYMBOL(hbl_cn_register_ib_aux_dev);
>>>>>
>>>>> Definately do not do some kind of double-register like this.
>>>>>
>>>>> The auxiliary_device scheme can already be extended to provide ops for
>>>>> each sub device.
>>>>>
>>>>> Like
>>>>>
>>>>> struct habana_driver {
>>>>> struct auxiliary_driver base;
>>>>> const struct habana_ops *ops;
>>>>> };
>>>>>
>>>>> If the ops are justified or not is a different question.
>>>>>
>>>>
>>>> Well, I suggested this double-register option because I got a comment that
>>>> the design pattern of embedded ops structure shouldn't be used.
>>>> So I'm confused now...
>>>
>>> Yeah, don't stick ops in random places, but the device_driver is the
>>> right place.
>>>
>>
>> Sorry, let me explain again. My original code has an ops structure
>> exactly like you are suggesting now (see struct hbl_aux_dev in the first
>> patch of the series). But I was instructed not to use this ops structure
>> and to rely on exported symbols for inter-driver communication.
>> I'll be happy to use this ops structure like in your example rather than
>> converting my code to use exported symbols.
>> Leon - am I missing anything? what's the verdict here?
>
> You are missing the main sentence from Jason's response: "don't stick ops in random places".
>
> It is fine to have ops in device driver, so the core driver can call them. However, in your
> original code, you added ops everywhere. It caused to the need to implement module reference
> counting and crazy stuff like calls to lock and unlock functions from the aux driver to the core.
>
> Verdict is still the same. Core driver should provide EXPORT_SYMBOLs, so the aux driver can call
> them directly and enjoy from proper module loading and unloading.
>
> The aux driver can have ops in the device driver, so the core driver can call them to perform something
> specific for that aux driver.
>
> Calls between aux drivers should be done via the core driver.
>
> Thanks
The only place we have an ops structure is in the device driver,
similarly to Jason's example. In our code it is struct hbl_aux_dev. What
other random places did you see?
We have several auxiliary devices so we have several instances of this
structure but the definition is in a single place.
The module reference counting is unrelated to the ops structure - we used
it to block the son driver removal while the parent driver can access it.
Even with exported symbols we would use it. Anyway, in v2 we'd like to
allow the son driver removal before the parent so this module reference
counting will be removed.
The lock/unlock functions are also unrelated to the ops structure, we would
add these even with exported symbols. The reason is that our NIC drivers
are the sons/grandsons of a compute device which can enter a reset flow as
part of a TDR mechanism. During this flow we must not access the HW so we
need to block a parallel son device probing.
In addition, we don't have any direct communication between the aux
drivers, everything is done via the parent driver.
Given all of the above, what is the problem with our current code? we did
exactly what Jason wrote in his example - having an ops structure in the
device driver to allow inter-driver communication.
The only issue I see here is the question if this ops structure is for
unidirectional communication (meaning parent to son only) or for
bidirectional communication between the drivers (meaning also son to
parent). That's the only point that was not mentioned by Jason while you
are clear about the answer.
AFAIU EXPORT_SYMBOLs should be used to expose driver level operations, not
operations which are device specific (and that's our case). Hence we used
this ops structure also for son-to-parent communication, although we can
switch them with exported symbols if we have to.
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-07-17 10:51 ` Omer Shpigelman
@ 2024-07-17 11:56 ` Jason Gunthorpe
2024-07-17 12:33 ` Leon Romanovsky
1 sibling, 0 replies; 108+ messages in thread
From: Jason Gunthorpe @ 2024-07-17 11:56 UTC (permalink / raw)
To: Omer Shpigelman
Cc: Leon Romanovsky, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On Wed, Jul 17, 2024 at 10:51:03AM +0000, Omer Shpigelman wrote:
> The only place we have an ops structure is in the device driver,
> similarly to Jason's example. In our code it is struct
> hbl_aux_dev. What
No, hbl_aux_dev is an 'struct auxiliary_device', not a 'struct
device_driver', it is different. I did literally mean struct
device_driver.
Jason
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-07-17 10:51 ` Omer Shpigelman
2024-07-17 11:56 ` Jason Gunthorpe
@ 2024-07-17 12:33 ` Leon Romanovsky
2024-07-18 6:54 ` Omer Shpigelman
1 sibling, 1 reply; 108+ messages in thread
From: Leon Romanovsky @ 2024-07-17 12:33 UTC (permalink / raw)
To: Omer Shpigelman
Cc: Jason Gunthorpe, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On Wed, Jul 17, 2024 at 10:51:03AM +0000, Omer Shpigelman wrote:
> On 7/17/24 10:36, Leon Romanovsky wrote:
> > On Wed, Jul 17, 2024 at 07:08:59AM +0000, Omer Shpigelman wrote:
> >> On 7/16/24 16:40, Jason Gunthorpe wrote:
> >>> On Sun, Jul 14, 2024 at 10:18:12AM +0000, Omer Shpigelman wrote:
> >>>> On 7/12/24 16:08, Jason Gunthorpe wrote:
> >>>>> [You don't often get email from jgg@ziepe.ca. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >>>>>
> >>>>> On Fri, Jun 28, 2024 at 10:24:32AM +0000, Omer Shpigelman wrote:
> >>>>>
> >>>>>> We need the core driver to access the IB driver (and to the ETH driver as
> >>>>>> well). As you wrote, we can't use exported symbols from our IB driver nor
> >>>>>> rely on function pointers, but what about providing the core driver an ops
> >>>>>> structure? meaning exporting a register function from the core driver that
> >>>>>> should be called by the IB driver during auxiliary device probe.
> >>>>>> Something like:
> >>>>>>
> >>>>>> int hbl_cn_register_ib_aux_dev(struct auxiliary_device *adev,
> >>>>>> struct hbl_ib_ops *ops)
> >>>>>> {
> >>>>>> ...
> >>>>>> }
> >>>>>> EXPORT_SYMBOL(hbl_cn_register_ib_aux_dev);
> >>>>>
> >>>>> Definately do not do some kind of double-register like this.
> >>>>>
> >>>>> The auxiliary_device scheme can already be extended to provide ops for
> >>>>> each sub device.
> >>>>>
> >>>>> Like
> >>>>>
> >>>>> struct habana_driver {
> >>>>> struct auxiliary_driver base;
> >>>>> const struct habana_ops *ops;
> >>>>> };
> >>>>>
> >>>>> If the ops are justified or not is a different question.
> >>>>>
> >>>>
> >>>> Well, I suggested this double-register option because I got a comment that
> >>>> the design pattern of embedded ops structure shouldn't be used.
> >>>> So I'm confused now...
> >>>
> >>> Yeah, don't stick ops in random places, but the device_driver is the
> >>> right place.
> >>>
> >>
> >> Sorry, let me explain again. My original code has an ops structure
> >> exactly like you are suggesting now (see struct hbl_aux_dev in the first
> >> patch of the series). But I was instructed not to use this ops structure
> >> and to rely on exported symbols for inter-driver communication.
> >> I'll be happy to use this ops structure like in your example rather than
> >> converting my code to use exported symbols.
> >> Leon - am I missing anything? what's the verdict here?
> >
> > You are missing the main sentence from Jason's response: "don't stick ops in random places".
> >
> > It is fine to have ops in device driver, so the core driver can call them. However, in your
> > original code, you added ops everywhere. It caused to the need to implement module reference
> > counting and crazy stuff like calls to lock and unlock functions from the aux driver to the core.
> >
> > Verdict is still the same. Core driver should provide EXPORT_SYMBOLs, so the aux driver can call
> > them directly and enjoy from proper module loading and unloading.
> >
> > The aux driver can have ops in the device driver, so the core driver can call them to perform something
> > specific for that aux driver.
> >
> > Calls between aux drivers should be done via the core driver.
> >
> > Thanks
>
> The only place we have an ops structure is in the device driver,
> similarly to Jason's example. In our code it is struct hbl_aux_dev. What
> other random places did you see?
This is exactly random place.
I suggest you to take time, learn how existing drivers in netdev and
RDMA uses auxbus infrastructure and follow the same pattern. There are
many examples already in the kernel.
And no, if you do everything right, you won't need custom module
reference counting and other hacks. There is nothing special in your
device/driver which requires special treatment.
Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-07-17 12:33 ` Leon Romanovsky
@ 2024-07-18 6:54 ` Omer Shpigelman
2024-07-18 8:31 ` Leon Romanovsky
0 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-07-18 6:54 UTC (permalink / raw)
To: Leon Romanovsky
Cc: Jason Gunthorpe, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 7/17/24 15:33, Leon Romanovsky wrote:
> On Wed, Jul 17, 2024 at 10:51:03AM +0000, Omer Shpigelman wrote:
>> On 7/17/24 10:36, Leon Romanovsky wrote:
>>> On Wed, Jul 17, 2024 at 07:08:59AM +0000, Omer Shpigelman wrote:
>>>> On 7/16/24 16:40, Jason Gunthorpe wrote:
>>>>> On Sun, Jul 14, 2024 at 10:18:12AM +0000, Omer Shpigelman wrote:
>>>>>> On 7/12/24 16:08, Jason Gunthorpe wrote:
>>>>>>> [You don't often get email from jgg@ziepe.ca. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>>>>
>>>>>>> On Fri, Jun 28, 2024 at 10:24:32AM +0000, Omer Shpigelman wrote:
>>>>>>>
>>>>>>>> We need the core driver to access the IB driver (and to the ETH driver as
>>>>>>>> well). As you wrote, we can't use exported symbols from our IB driver nor
>>>>>>>> rely on function pointers, but what about providing the core driver an ops
>>>>>>>> structure? meaning exporting a register function from the core driver that
>>>>>>>> should be called by the IB driver during auxiliary device probe.
>>>>>>>> Something like:
>>>>>>>>
>>>>>>>> int hbl_cn_register_ib_aux_dev(struct auxiliary_device *adev,
>>>>>>>> struct hbl_ib_ops *ops)
>>>>>>>> {
>>>>>>>> ...
>>>>>>>> }
>>>>>>>> EXPORT_SYMBOL(hbl_cn_register_ib_aux_dev);
>>>>>>>
>>>>>>> Definately do not do some kind of double-register like this.
>>>>>>>
>>>>>>> The auxiliary_device scheme can already be extended to provide ops for
>>>>>>> each sub device.
>>>>>>>
>>>>>>> Like
>>>>>>>
>>>>>>> struct habana_driver {
>>>>>>> struct auxiliary_driver base;
>>>>>>> const struct habana_ops *ops;
>>>>>>> };
>>>>>>>
>>>>>>> If the ops are justified or not is a different question.
>>>>>>>
>>>>>>
>>>>>> Well, I suggested this double-register option because I got a comment that
>>>>>> the design pattern of embedded ops structure shouldn't be used.
>>>>>> So I'm confused now...
>>>>>
>>>>> Yeah, don't stick ops in random places, but the device_driver is the
>>>>> right place.
>>>>>
>>>>
>>>> Sorry, let me explain again. My original code has an ops structure
>>>> exactly like you are suggesting now (see struct hbl_aux_dev in the first
>>>> patch of the series). But I was instructed not to use this ops structure
>>>> and to rely on exported symbols for inter-driver communication.
>>>> I'll be happy to use this ops structure like in your example rather than
>>>> converting my code to use exported symbols.
>>>> Leon - am I missing anything? what's the verdict here?
>>>
>>> You are missing the main sentence from Jason's response: "don't stick ops in random places".
>>>
>>> It is fine to have ops in device driver, so the core driver can call them. However, in your
>>> original code, you added ops everywhere. It caused to the need to implement module reference
>>> counting and crazy stuff like calls to lock and unlock functions from the aux driver to the core.
>>>
>>> Verdict is still the same. Core driver should provide EXPORT_SYMBOLs, so the aux driver can call
>>> them directly and enjoy from proper module loading and unloading.
>>>
>>> The aux driver can have ops in the device driver, so the core driver can call them to perform something
>>> specific for that aux driver.
>>>
>>> Calls between aux drivers should be done via the core driver.
>>>
>>> Thanks
>>
>> The only place we have an ops structure is in the device driver,
>> similarly to Jason's example. In our code it is struct hbl_aux_dev. What
>> other random places did you see?
>
> This is exactly random place.
>
> I suggest you to take time, learn how existing drivers in netdev and
> RDMA uses auxbus infrastructure and follow the same pattern. There are
> many examples already in the kernel.
>
> And no, if you do everything right, you won't need custom module
> reference counting and other hacks. There is nothing special in your
> device/driver which requires special treatment.
>
> Thanks
How come it is a random place?
Look at irdma/i40e - they have an ops struct (struct i40e_ops) embedded
in their shared aux struct (struct i40e_auxiliary_device) which is the
wrapper of the base aux struct (struct auxiliary_device).
This is very similar to what we have - a pointer to an ops struct
(void *aux_ops) embedded in our shared aux struct (struct hbl_aux_dev)
which is the wrapper of the base struct (struct auxiliary_device).
The only difference is that they put their ops struct inside some info
struct (struct i40e_info) and we have a separate pointer for that info
(void *aux_data).
In addition, they use the ops struct for accessing the net driver from the
RDMA driver, meaning son-to-parent communication instead of having an
exported symbol e.g. i40e_client_request_reset().
They have only a single operation as EXPORT_SYMBOL function for
(un)registering the son - i40e_client_device_register() and
i40e_client_device_unregister().
So what is the problem with how we implemented it?
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-07-18 6:54 ` Omer Shpigelman
@ 2024-07-18 8:31 ` Leon Romanovsky
0 siblings, 0 replies; 108+ messages in thread
From: Leon Romanovsky @ 2024-07-18 8:31 UTC (permalink / raw)
To: Omer Shpigelman
Cc: Jason Gunthorpe, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On Thu, Jul 18, 2024 at 06:54:17AM +0000, Omer Shpigelman wrote:
> On 7/17/24 15:33, Leon Romanovsky wrote:
> > On Wed, Jul 17, 2024 at 10:51:03AM +0000, Omer Shpigelman wrote:
> >> On 7/17/24 10:36, Leon Romanovsky wrote:
> >>> On Wed, Jul 17, 2024 at 07:08:59AM +0000, Omer Shpigelman wrote:
> >>>> On 7/16/24 16:40, Jason Gunthorpe wrote:
> >>>>> On Sun, Jul 14, 2024 at 10:18:12AM +0000, Omer Shpigelman wrote:
> >>>>>> On 7/12/24 16:08, Jason Gunthorpe wrote:
<...>
> So what is the problem with how we implemented it?
Please do you homework and send new version of the patch series.
Thanks
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-18 11:08 ` Omer Shpigelman
2024-06-18 12:58 ` Leon Romanovsky
@ 2024-06-18 16:01 ` Przemek Kitszel
2024-06-19 9:34 ` Omer Shpigelman
1 sibling, 1 reply; 108+ messages in thread
From: Przemek Kitszel @ 2024-06-18 16:01 UTC (permalink / raw)
To: Omer Shpigelman, Leon Romanovsky
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/18/24 13:08, Omer Shpigelman wrote:
> On 6/17/24 22:04, Leon Romanovsky wrote:
>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>
>> On Mon, Jun 17, 2024 at 05:43:49PM +0000, Omer Shpigelman wrote:
>>> On 6/13/24 22:18, Leon Romanovsky wrote:
>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>
>>>> On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
>>>>> Add an RDMA driver of Gaudi ASICs family for AI scaling.
>>>>> The driver itself is agnostic to the ASIC in action, it operates according
>>>>> to the capabilities that were passed on device initialization.
>>>>> The device is initialized by the hbl_cn driver via auxiliary bus.
>>>>> The driver also supports QP resource tracking and port/device HW counters.
>>>>>
>>>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
>>>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
>>>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
>>>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
>>>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
>>>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
>>>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
>>>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
>>>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
>>>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
>>>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
>>>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
>>>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
>>>>
>>>> I afraid that you misinterpreted the "Co-developed-by" tag. All these
>>>> people are probably touch the code and not actually sit together at
>>>> the same room and write the code together. So, please remove the
>>>> extensive "Co-developed-by" tags.
>>>>
>>>> It is not full review yet, but simple pass-by-comments.
>>>>
>>>
>>> Actually except of two, all of the mentioned persons sat in the same room
>>> and developed the code together.
>>> The remaining two are located on a different site (but also together).
>>> Isn't that what "Co-developed-by" tag for?
>>> I wanted to give them credit for writing the code but I can remove if it's
>>> not common.
>>
>> Signed-off-by will be enough to give them credit.
>>
>
> Ok, good enough.
>
I would say that a lone sign-off give a little of credit compared to the
co-developed-by tag. OTOH the list here is unusually long. What makes it
even more tricky to evaluate is the fact that there is a lot of code ;)
So, I would suggest to re-evaluate this on your next (trimmed down)
revisions.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-18 16:01 ` Przemek Kitszel
@ 2024-06-19 9:34 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-19 9:34 UTC (permalink / raw)
To: Przemek Kitszel, Leon Romanovsky
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/18/24 19:01, Przemek Kitszel wrote:
> On 6/18/24 13:08, Omer Shpigelman wrote:
>> On 6/17/24 22:04, Leon Romanovsky wrote:
>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>
>>> On Mon, Jun 17, 2024 at 05:43:49PM +0000, Omer Shpigelman wrote:
>>>> On 6/13/24 22:18, Leon Romanovsky wrote:
>>>>> [Some people who received this message don't often get email from leon@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>>
>>>>> On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
>>>>>> Add an RDMA driver of Gaudi ASICs family for AI scaling.
>>>>>> The driver itself is agnostic to the ASIC in action, it operates according
>>>>>> to the capabilities that were passed on device initialization.
>>>>>> The device is initialized by the hbl_cn driver via auxiliary bus.
>>>>>> The driver also supports QP resource tracking and port/device HW counters.
>>>>>>
>>>>>> Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
>>>>>> Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
>>>>>> Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
>>>>>> Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
>>>>>> Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
>>>>>> Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
>>>>>> Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
>>>>>> Co-developed-by: David Meriin <dmeriin@habana.ai>
>>>>>> Signed-off-by: David Meriin <dmeriin@habana.ai>
>>>>>> Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
>>>>>> Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
>>>>>> Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
>>>>>> Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
>>>>>
>>>>> I afraid that you misinterpreted the "Co-developed-by" tag. All these
>>>>> people are probably touch the code and not actually sit together at
>>>>> the same room and write the code together. So, please remove the
>>>>> extensive "Co-developed-by" tags.
>>>>>
>>>>> It is not full review yet, but simple pass-by-comments.
>>>>>
>>>>
>>>> Actually except of two, all of the mentioned persons sat in the same room
>>>> and developed the code together.
>>>> The remaining two are located on a different site (but also together).
>>>> Isn't that what "Co-developed-by" tag for?
>>>> I wanted to give them credit for writing the code but I can remove if it's
>>>> not common.
>>>
>>> Signed-off-by will be enough to give them credit.
>>>
>>
>> Ok, good enough.
>>
>
> I would say that a lone sign-off give a little of credit compared to the
> co-developed-by tag. OTOH the list here is unusually long. What makes it
> even more tricky to evaluate is the fact that there is a lot of code ;)
>
> So, I would suggest to re-evaluate this on your next (trimmed down)
> revisions.
You are right about the smaller credit Signed-off-by gives compared to
Co-developed-by, but yeah, the list is unusually long.
I'll try to split it to smaller patches and give credit only to the
specific persons involved.
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-13 8:22 ` [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver Omer Shpigelman
2024-06-13 19:18 ` Leon Romanovsky
@ 2024-06-17 14:17 ` Jason Gunthorpe
2024-06-19 9:39 ` Omer Shpigelman
1 sibling, 1 reply; 108+ messages in thread
From: Jason Gunthorpe @ 2024-06-17 14:17 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel, linux-rdma, netdev, dri-devel, ogabbay, zyehudai
On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
> Add an RDMA driver of Gaudi ASICs family for AI scaling.
> The driver itself is agnostic to the ASIC in action, it operates according
> to the capabilities that were passed on device initialization.
> The device is initialized by the hbl_cn driver via auxiliary bus.
> The driver also supports QP resource tracking and port/device HW counters.
I'm glad to finally see this, I've been talking to habana folks a long
time now to get this worked out!
This will need to be split up more, like others have said. I'd post
the RDMA series assuming that the basic ethernet driver is merged. You
don't need to combine basic ethernet with rdma in the same series.
Jason
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver
2024-06-17 14:17 ` Jason Gunthorpe
@ 2024-06-19 9:39 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-19 9:39 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/17/24 17:17, Jason Gunthorpe wrote:
> [You don't often get email from jgg@ziepe.ca. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On Thu, Jun 13, 2024 at 11:22:04AM +0300, Omer Shpigelman wrote:
>> Add an RDMA driver of Gaudi ASICs family for AI scaling.
>> The driver itself is agnostic to the ASIC in action, it operates according
>> to the capabilities that were passed on device initialization.
>> The device is initialized by the hbl_cn driver via auxiliary bus.
>> The driver also supports QP resource tracking and port/device HW counters.
>
> I'm glad to finally see this, I've been talking to habana folks a long
> time now to get this worked out!
>
> This will need to be split up more, like others have said. I'd post
> the RDMA series assuming that the basic ethernet driver is merged. You
> don't need to combine basic ethernet with rdma in the same series.
>
> Jason
Yeah, I'll push one driver at a time in multiple patch sets with smaller
patches.
It's just that all the 4 drivers are operating together, they are not
operational separately. That's why I thought it will give more context to
see the entire picture when reviewing.
^ permalink raw reply [flat|nested] 108+ messages in thread
* [PATCH 12/15] RDMA/hbl: direct verbs support
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
` (10 preceding siblings ...)
2024-06-13 8:22 ` [PATCH 11/15] RDMA/hbl: add habanalabs RDMA driver Omer Shpigelman
@ 2024-06-13 8:22 ` Omer Shpigelman
2024-06-13 8:22 ` [PATCH 13/15] accel/habanalabs: network scaling support Omer Shpigelman
` (4 subsequent siblings)
16 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:22 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
Add direct verbs (DV) uAPI.
The added operations are:
query_port: query vendor specific port attributes.
set_port_ex: set port extended settings.
usr_fifo: set user FIFO object for triggering HW doorbells.
encap: set port encapsulation (UDP/IPv4).
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
drivers/infiniband/hw/hbl/Kconfig | 1 +
drivers/infiniband/hw/hbl/Makefile | 4 +
drivers/infiniband/hw/hbl/hbl_encap.c | 216 +++++++++++++++++
drivers/infiniband/hw/hbl/hbl_main.c | 15 ++
drivers/infiniband/hw/hbl/hbl_query_port.c | 96 ++++++++
drivers/infiniband/hw/hbl/hbl_set_port_ex.c | 96 ++++++++
drivers/infiniband/hw/hbl/hbl_usr_fifo.c | 252 ++++++++++++++++++++
7 files changed, 680 insertions(+)
create mode 100644 drivers/infiniband/hw/hbl/hbl_encap.c
create mode 100644 drivers/infiniband/hw/hbl/hbl_query_port.c
create mode 100644 drivers/infiniband/hw/hbl/hbl_set_port_ex.c
create mode 100644 drivers/infiniband/hw/hbl/hbl_usr_fifo.c
diff --git a/drivers/infiniband/hw/hbl/Kconfig b/drivers/infiniband/hw/hbl/Kconfig
index 90c865a82540..db09ecb3968a 100644
--- a/drivers/infiniband/hw/hbl/Kconfig
+++ b/drivers/infiniband/hw/hbl/Kconfig
@@ -6,6 +6,7 @@
config INFINIBAND_HBL
tristate "HabanaLabs (an Intel Company) InfiniBand driver"
depends on NETDEVICES && ETHERNET && PCI && INET
+ depends on INFINIBAND_USER_ACCESS
select HABANA_CN
help
This driver enables InfiniBand functionality for the network
diff --git a/drivers/infiniband/hw/hbl/Makefile b/drivers/infiniband/hw/hbl/Makefile
index 659d4bbfec0f..86f53ca6b9d5 100644
--- a/drivers/infiniband/hw/hbl/Makefile
+++ b/drivers/infiniband/hw/hbl/Makefile
@@ -6,3 +6,7 @@
obj-$(CONFIG_INFINIBAND_HBL) := habanalabs_ib.o
habanalabs_ib-y += hbl_main.o hbl_verbs.o
+
+habanalabs_ib-$(CONFIG_INFINIBAND_USER_ACCESS) += hbl_encap.o hbl_query_port.o \
+ hbl_set_port_ex.o \
+ hbl_usr_fifo.o
diff --git a/drivers/infiniband/hw/hbl/hbl_encap.c b/drivers/infiniband/hw/hbl/hbl_encap.c
new file mode 100644
index 000000000000..bcc198059664
--- /dev/null
+++ b/drivers/infiniband/hw/hbl/hbl_encap.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "hbl.h"
+#include <rdma/ib_user_verbs.h>
+#include <rdma/ib_addr.h>
+#include <rdma/uverbs_ioctl.h>
+#include <linux/net/intel/cni.h>
+
+#include <rdma/uverbs_ioctl.h>
+#include <uapi/rdma/hbl_user_ioctl_cmds.h>
+
+#define UVERBS_MODULE_NAME hbl
+#include <rdma/uverbs_named_ioctl.h>
+
+struct hbl_encap {
+ u32 port_num;
+ u32 encap_num;
+};
+
+static int UVERBS_HANDLER(HBL_IB_METHOD_ENCAP_CREATE)(struct uverbs_attr_bundle *attrs)
+{
+ struct hbl_cni_user_encap_alloc_out alloc_encap_out = {};
+ struct hbl_cni_user_encap_alloc_in alloc_encap_in = {};
+ struct hbl_cni_user_encap_unset_in unset_encap_in = {};
+ struct hbl_cni_user_encap_set_in set_encap_in = {};
+ struct hbl_uapi_encap_create_out out = {};
+ struct hbl_uapi_encap_create_in in = {};
+ u32 port, tnl_hdr_size, encap_num;
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_encap *encap_pdata;
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ struct ib_uobject *uobj;
+ u64 tnl_hdr_ptr;
+ u8 encap_type;
+ int rc;
+
+ hctx = to_hbl_ib_ucontext(ib_uverbs_get_ucontext(attrs));
+ if (IS_ERR(hctx))
+ return PTR_ERR(hctx);
+
+ uobj = uverbs_attr_get_uobject(attrs, HBL_IB_ATTR_ENCAP_CREATE_HANDLE);
+ hdev = to_hbl_ib_dev(hctx->ibucontext.device);
+ ibdev = &hdev->ibdev;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ rc = uverbs_copy_from(&in, attrs, HBL_IB_ATTR_ENCAP_CREATE_IN);
+ if (rc)
+ return rc;
+
+ rc = ib_to_hbl_port_num(hdev, in.port_num, &port);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u\n", in.port_num);
+ return rc;
+ }
+
+ if (!(hctx->ports_mask & BIT(port))) {
+ hbl_ibdev_dbg(ibdev, "port %d is not part of the context's ports mask 0x%llx\n",
+ port, hctx->ports_mask);
+ return -EINVAL;
+ }
+
+ encap_pdata = kzalloc(sizeof(*encap_pdata), GFP_KERNEL);
+ if (!encap_pdata)
+ return -ENOMEM;
+
+ encap_type = in.encap_type;
+
+ alloc_encap_in.port = port;
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_ENCAP_ALLOC, &alloc_encap_in,
+ &alloc_encap_out);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to alloc encap for port %d\n", port);
+ goto err_free_pdata;
+ }
+
+ encap_num = alloc_encap_out.id;
+
+ if (encap_type != HBL_CNI_ENCAP_NONE) {
+ tnl_hdr_ptr = in.tnl_hdr_ptr;
+ tnl_hdr_size = in.tnl_hdr_size;
+ } else {
+ tnl_hdr_ptr = 0;
+ tnl_hdr_size = 0;
+ }
+
+ encap_pdata->port_num = port;
+ encap_pdata->encap_num = encap_num;
+
+ set_encap_in.tnl_hdr_ptr = tnl_hdr_ptr;
+ set_encap_in.tnl_hdr_size = tnl_hdr_size;
+ set_encap_in.port = port;
+ set_encap_in.id = encap_num;
+ set_encap_in.encap_type = encap_type;
+
+ switch (encap_type) {
+ case HBL_CNI_ENCAP_NONE:
+ set_encap_in.ipv4_addr = in.ipv4_addr;
+ break;
+ case HBL_CNI_ENCAP_OVER_UDP:
+ set_encap_in.udp_dst_port = in.udp_dst_port;
+ break;
+ case HBL_CNI_ENCAP_OVER_IPV4:
+ set_encap_in.ip_proto = in.ip_proto;
+ break;
+ default:
+ break;
+ }
+
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_ENCAP_SET, &set_encap_in,
+ NULL);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to set encap for port %d\n", port);
+ goto err_encap_unset;
+ }
+
+ out.encap_num = encap_num;
+ uobj->object = encap_pdata;
+
+ rc = uverbs_copy_to_struct_or_zero(attrs, HBL_IB_ATTR_ENCAP_CREATE_OUT, &out, sizeof(out));
+ if (rc)
+ goto err_encap_unset;
+
+ return 0;
+
+err_encap_unset:
+ unset_encap_in.port = port;
+ unset_encap_in.id = encap_num;
+
+ if (aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_ENCAP_UNSET, &unset_encap_in,
+ NULL))
+ hbl_ibdev_dbg(ibdev, "failed to unset encap for port %d, encap_num %d\n", port,
+ encap_num);
+
+err_free_pdata:
+ kfree(encap_pdata);
+
+ return rc;
+}
+
+static int hbl_free_encap(struct ib_uobject *uobject, enum rdma_remove_reason why,
+ struct uverbs_attr_bundle *attrs)
+{
+ struct hbl_cni_user_encap_unset_in unset_encap_in = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_encap *encap_pdata;
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ int rc;
+
+ hctx = to_hbl_ib_ucontext(ib_uverbs_get_ucontext(attrs));
+ if (IS_ERR(hctx))
+ return PTR_ERR(hctx);
+
+ encap_pdata = uobject->object;
+ hdev = to_hbl_ib_dev(hctx->ibucontext.device);
+ ibdev = &hdev->ibdev;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ unset_encap_in.port = encap_pdata->port_num;
+ unset_encap_in.id = encap_pdata->encap_num;
+ if (aux_ops->device_operational(aux_dev)) {
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_ENCAP_UNSET,
+ &unset_encap_in, NULL);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to unset encap for port %d, id %d\n",
+ unset_encap_in.port, unset_encap_in.id);
+ return rc;
+ }
+ }
+
+ kfree(encap_pdata);
+
+ return 0;
+}
+
+DECLARE_UVERBS_NAMED_METHOD(
+ HBL_IB_METHOD_ENCAP_CREATE,
+ UVERBS_ATTR_IDR(HBL_IB_ATTR_ENCAP_CREATE_HANDLE,
+ HBL_IB_OBJECT_ENCAP,
+ UVERBS_ACCESS_NEW,
+ UA_MANDATORY),
+ UVERBS_ATTR_PTR_IN(HBL_IB_ATTR_ENCAP_CREATE_IN,
+ UVERBS_ATTR_STRUCT(struct hbl_uapi_encap_create_in, reserved),
+ UA_MANDATORY),
+ UVERBS_ATTR_PTR_OUT(HBL_IB_ATTR_ENCAP_CREATE_OUT,
+ UVERBS_ATTR_STRUCT(struct hbl_uapi_encap_create_out, reserved),
+ UA_MANDATORY));
+
+DECLARE_UVERBS_NAMED_METHOD_DESTROY(
+ HBL_IB_METHOD_ENCAP_DESTROY,
+ UVERBS_ATTR_IDR(HBL_IB_ATTR_ENCAP_DESTROY_HANDLE,
+ HBL_IB_OBJECT_ENCAP,
+ UVERBS_ACCESS_DESTROY,
+ UA_MANDATORY));
+
+DECLARE_UVERBS_NAMED_OBJECT(HBL_IB_OBJECT_ENCAP,
+ UVERBS_TYPE_ALLOC_IDR(hbl_free_encap),
+ &UVERBS_METHOD(HBL_IB_METHOD_ENCAP_CREATE),
+ &UVERBS_METHOD(HBL_IB_METHOD_ENCAP_DESTROY));
+
+const struct uapi_definition hbl_encap_defs[] = {
+ UAPI_DEF_CHAIN_OBJ_TREE_NAMED(HBL_IB_OBJECT_ENCAP),
+ {},
+};
diff --git a/drivers/infiniband/hw/hbl/hbl_main.c b/drivers/infiniband/hw/hbl/hbl_main.c
index 98d3ed46bfe2..6bee35695a06 100644
--- a/drivers/infiniband/hw/hbl/hbl_main.c
+++ b/drivers/infiniband/hw/hbl/hbl_main.c
@@ -22,6 +22,16 @@ MODULE_LICENSE("GPL");
#define MTU_DEFAULT SZ_4K
+static const struct uapi_definition hbl_defs[] = {
+#if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
+ UAPI_DEF_CHAIN(hbl_usr_fifo_defs),
+ UAPI_DEF_CHAIN(hbl_set_port_ex_defs),
+ UAPI_DEF_CHAIN(hbl_query_port_defs),
+ UAPI_DEF_CHAIN(hbl_encap_defs),
+#endif
+ {}
+};
+
static void hbl_ib_port_event(struct ib_device *ibdev, u32 port_num, enum ib_event_type reason)
{
struct ib_event event;
@@ -166,6 +176,11 @@ static int hbl_ib_dev_init(struct hbl_ib_device *hdev)
ib_set_device_ops(ibdev, &hbl_ib_dev_ops);
+ if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
+ ibdev->driver_def = hbl_defs;
+ else
+ dev_info(hdev->dev, "IB user access is disabled\n");
+
/* The CN driver might start calling the aux functions after registering the device so set
* the callbacks here.
*/
diff --git a/drivers/infiniband/hw/hbl/hbl_query_port.c b/drivers/infiniband/hw/hbl/hbl_query_port.c
new file mode 100644
index 000000000000..1882507b0b58
--- /dev/null
+++ b/drivers/infiniband/hw/hbl/hbl_query_port.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "hbl.h"
+#include <rdma/ib_user_verbs.h>
+#include <rdma/ib_addr.h>
+#include <rdma/uverbs_ioctl.h>
+#include <linux/net/intel/cni.h>
+
+#include <rdma/uverbs_ioctl.h>
+#include <uapi/rdma/hbl_user_ioctl_cmds.h>
+#include <uapi/rdma/hbl_user_ioctl_verbs.h>
+
+#define UVERBS_MODULE_NAME hbl
+#include <rdma/uverbs_named_ioctl.h>
+
+static int UVERBS_HANDLER(HBL_IB_METHOD_QUERY_PORT)(struct uverbs_attr_bundle *attrs)
+{
+ struct hbl_cni_get_user_app_params_out app_params_out = {};
+ struct hbl_cni_get_user_app_params_in app_params_in = {};
+ struct hbl_uapi_query_port_out out = {};
+ struct hbl_uapi_query_port_in in = {};
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ int rc;
+
+ hctx = to_hbl_ib_ucontext(ib_uverbs_get_ucontext(attrs));
+ if (IS_ERR(hctx))
+ return PTR_ERR(hctx);
+
+ hdev = to_hbl_ib_dev(hctx->ibucontext.device);
+ ibdev = &hdev->ibdev;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ rc = uverbs_copy_from(&in, attrs, HBL_IB_ATTR_QUERY_PORT_IN);
+ if (rc)
+ return rc;
+
+ rc = ib_to_hbl_port_num(hdev, in.port_num, &app_params_in.port);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u\n", in.port_num);
+ return rc;
+ }
+
+ if (!(hctx->ports_mask & BIT(app_params_in.port))) {
+ hbl_ibdev_dbg(ibdev, "port %d is not part of the context's ports mask 0x%llx\n",
+ app_params_in.port, hctx->ports_mask);
+ return -EINVAL;
+ }
+
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_GET_USER_APP_PARAMS,
+ &app_params_in, &app_params_out);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to get user params for port %d\n", app_params_in.port);
+ return rc;
+ }
+
+ out.max_num_of_qps = app_params_out.max_num_of_qps;
+ out.num_allocated_qps = app_params_out.num_allocated_qps;
+ out.max_allocated_qp_num = app_params_out.max_allocated_qp_idx;
+ out.max_cq_size = app_params_out.max_cq_size;
+ out.advanced = app_params_out.advanced;
+ out.max_num_of_cqs = app_params_out.max_num_of_cqs;
+ out.max_num_of_usr_fifos = app_params_out.max_num_of_db_fifos;
+ out.max_num_of_encaps = app_params_out.max_num_of_encaps;
+ out.nic_macro_idx = app_params_out.nic_macro_idx;
+ out.nic_phys_port_idx = app_params_out.nic_phys_port_idx;
+
+ rc = uverbs_copy_to_struct_or_zero(attrs, HBL_IB_ATTR_QUERY_PORT_OUT, &out, sizeof(out));
+
+ return rc;
+}
+
+DECLARE_UVERBS_NAMED_METHOD(
+ HBL_IB_METHOD_QUERY_PORT,
+ UVERBS_ATTR_PTR_IN(HBL_IB_ATTR_QUERY_PORT_IN,
+ UVERBS_ATTR_STRUCT(struct hbl_uapi_query_port_in, reserved),
+ UA_MANDATORY),
+ UVERBS_ATTR_PTR_OUT(HBL_IB_ATTR_QUERY_PORT_OUT,
+ UVERBS_ATTR_STRUCT(struct hbl_uapi_query_port_out, reserved),
+ UA_MANDATORY));
+
+DECLARE_UVERBS_GLOBAL_METHODS(HBL_IB_OBJECT_QUERY_PORT, &UVERBS_METHOD(HBL_IB_METHOD_QUERY_PORT));
+
+const struct uapi_definition hbl_query_port_defs[] = {
+ UAPI_DEF_CHAIN_OBJ_TREE_NAMED(HBL_IB_OBJECT_QUERY_PORT),
+ {},
+};
diff --git a/drivers/infiniband/hw/hbl/hbl_set_port_ex.c b/drivers/infiniband/hw/hbl/hbl_set_port_ex.c
new file mode 100644
index 000000000000..15b509506cca
--- /dev/null
+++ b/drivers/infiniband/hw/hbl/hbl_set_port_ex.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "hbl.h"
+#include <rdma/ib_user_verbs.h>
+#include <rdma/ib_addr.h>
+#include <rdma/uverbs_ioctl.h>
+#include <linux/net/intel/cni.h>
+
+#include <rdma/uverbs_ioctl.h>
+#include <uapi/rdma/hbl_user_ioctl_cmds.h>
+#include <uapi/rdma/hbl_user_ioctl_verbs.h>
+
+#define UVERBS_MODULE_NAME hbl
+#include <rdma/uverbs_named_ioctl.h>
+
+static int UVERBS_HANDLER(HBL_IB_METHOD_SET_PORT_EX)(struct uverbs_attr_bundle *attrs)
+{
+ struct hbl_ib_port_init_params port_init_params = {};
+ struct hbl_uapi_set_port_ex_in in = {};
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ u32 hbl_port;
+ int rc, i;
+
+ hctx = to_hbl_ib_ucontext(ib_uverbs_get_ucontext(attrs));
+ if (IS_ERR(hctx))
+ return PTR_ERR(hctx);
+
+ hdev = to_hbl_ib_dev(hctx->ibucontext.device);
+ ibdev = &hdev->ibdev;
+
+ rc = uverbs_copy_from(&in, attrs, HBL_IB_ATTR_SET_PORT_EX_IN);
+ if (rc)
+ return rc;
+
+ rc = ib_to_hbl_port_num(hdev, in.port_num, &hbl_port);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u\n", in.port_num);
+ return rc;
+ }
+
+ if (!(hctx->ports_mask & BIT(hbl_port))) {
+ hbl_ibdev_dbg(ibdev, "port %d is not part of the context's ports mask 0x%llx\n",
+ hbl_port, hctx->ports_mask);
+ return -EINVAL;
+ }
+
+ if (!in.qp_wq_bp_offs && in.qp_wq_bp_offs_cnt > 0)
+ return -EINVAL;
+
+ port_init_params.hbl_port_num = hbl_port;
+
+ for (i = 0; i < HBL_IB_WQ_ARRAY_TYPE_MAX; i++) {
+ port_init_params.wq_arr_attr[i].max_num_of_wqs =
+ in.wq_arr_attr[i].max_num_of_wqs;
+ port_init_params.wq_arr_attr[i].max_num_of_wqes_in_wq =
+ in.wq_arr_attr[i].max_num_of_wqes_in_wq;
+ port_init_params.wq_arr_attr[i].mem_id = in.wq_arr_attr[i].mem_id;
+ port_init_params.wq_arr_attr[i].swq_granularity =
+ in.wq_arr_attr[i].swq_granularity;
+ }
+
+ if (copy_from_user(port_init_params.qp_wq_bp_offs, u64_to_user_ptr(in.qp_wq_bp_offs),
+ sizeof(port_init_params.qp_wq_bp_offs[0]) *
+ min((u32)HBL_IB_MAX_BP_OFFS, in.qp_wq_bp_offs_cnt)))
+ return -EFAULT;
+
+ port_init_params.advanced = in.advanced;
+ port_init_params.adaptive_timeout_en = in.adaptive_timeout_en;
+
+ rc = hbl_ib_port_init(hctx, &port_init_params);
+ if (rc)
+ hbl_ibdev_dbg(ibdev, "failed(%d) to set port %u extended params\n", rc, hbl_port);
+
+ return rc;
+}
+
+DECLARE_UVERBS_NAMED_METHOD(
+ HBL_IB_METHOD_SET_PORT_EX,
+ UVERBS_ATTR_PTR_IN(HBL_IB_ATTR_SET_PORT_EX_IN,
+ UVERBS_ATTR_STRUCT(struct hbl_uapi_set_port_ex_in, reserved3),
+ UA_MANDATORY));
+
+DECLARE_UVERBS_GLOBAL_METHODS(HBL_IB_OBJECT_SET_PORT_EX,
+ &UVERBS_METHOD(HBL_IB_METHOD_SET_PORT_EX));
+
+const struct uapi_definition hbl_set_port_ex_defs[] = {
+ UAPI_DEF_CHAIN_OBJ_TREE_NAMED(HBL_IB_OBJECT_SET_PORT_EX),
+ {},
+};
diff --git a/drivers/infiniband/hw/hbl/hbl_usr_fifo.c b/drivers/infiniband/hw/hbl/hbl_usr_fifo.c
new file mode 100644
index 000000000000..37f387a99f40
--- /dev/null
+++ b/drivers/infiniband/hw/hbl/hbl_usr_fifo.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "hbl.h"
+#include <rdma/ib_user_verbs.h>
+#include <rdma/ib_addr.h>
+#include <rdma/uverbs_ioctl.h>
+#include <linux/net/intel/cni.h>
+
+#include <rdma/uverbs_ioctl.h>
+#include <uapi/rdma/hbl_user_ioctl_cmds.h>
+#include <uapi/rdma/hbl_user_ioctl_verbs.h>
+
+#define UVERBS_MODULE_NAME hbl
+#include <rdma/uverbs_named_ioctl.h>
+
+/**
+ * struct hbl_usr_fifo - This structure will be stored inside the uobject.
+ * @ci_entry: The rdma_user_mmap_entry for the mapped ci.
+ * @regs_entry: The rdma_user_mmap_entry for the mapped registers.
+ * @port: The port of this fifo.
+ * @id: The id of this fifo.
+ */
+struct hbl_usr_fifo {
+ struct rdma_user_mmap_entry *ci_entry;
+ struct rdma_user_mmap_entry *regs_entry;
+ u32 port;
+ u32 id;
+};
+
+static void user_fifo_mmap_entry_remove(struct hbl_usr_fifo *usr_fifo)
+{
+ rdma_user_mmap_entry_remove(usr_fifo->regs_entry);
+ if (usr_fifo->ci_entry)
+ rdma_user_mmap_entry_remove(usr_fifo->ci_entry);
+}
+
+static int user_fifo_mmap_entry_setup(struct hbl_ib_device *dev, struct hbl_ib_ucontext *hctx,
+ struct hbl_usr_fifo *usr_fifo,
+ struct hbl_uapi_usr_fifo_create_out *out)
+{
+ if (out->ci_handle) {
+ usr_fifo->ci_entry = hbl_ib_user_mmap_entry_insert(&hctx->ibucontext,
+ out->ci_handle,
+ PAGE_SIZE, &out->ci_handle);
+ if (IS_ERR(usr_fifo->ci_entry))
+ return PTR_ERR(usr_fifo->ci_entry);
+ }
+
+ usr_fifo->regs_entry = hbl_ib_user_mmap_entry_insert(&hctx->ibucontext, out->regs_handle,
+ PAGE_SIZE, &out->regs_handle);
+ if (IS_ERR(usr_fifo->regs_entry))
+ goto err_free_ci;
+
+ return 0;
+
+err_free_ci:
+ if (usr_fifo->ci_entry)
+ rdma_user_mmap_entry_remove(usr_fifo->ci_entry);
+
+ return PTR_ERR(usr_fifo->regs_entry);
+}
+
+static int UVERBS_HANDLER(HBL_IB_METHOD_USR_FIFO_OBJ_CREATE)(struct uverbs_attr_bundle *attrs)
+{
+ struct hbl_cni_alloc_user_db_fifo_out alloc_db_fifo_out = {};
+ struct hbl_cni_alloc_user_db_fifo_in alloc_db_fifo_in = {};
+ struct hbl_cni_user_db_fifo_unset_in db_fifo_unset_in = {};
+ struct hbl_cni_user_db_fifo_set_out db_fifo_set_out = {};
+ struct hbl_cni_user_db_fifo_set_in db_fifo_set_in = {};
+ struct hbl_uapi_usr_fifo_create_out out = {};
+ struct hbl_uapi_usr_fifo_create_in in = {};
+ struct hbl_usr_fifo *usr_fifo_pdata;
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ struct ib_uobject *uobj;
+ u32 port, id;
+ u8 mode;
+ int rc;
+
+ hctx = to_hbl_ib_ucontext(ib_uverbs_get_ucontext(attrs));
+ if (IS_ERR(hctx))
+ return PTR_ERR(hctx);
+
+ uobj = uverbs_attr_get_uobject(attrs, HBL_IB_ATTR_USR_FIFO_CREATE_HANDLE);
+ hdev = to_hbl_ib_dev(hctx->ibucontext.device);
+ ibdev = &hdev->ibdev;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ rc = uverbs_copy_from(&in, attrs, HBL_IB_ATTR_USR_FIFO_CREATE_IN);
+ if (rc)
+ return rc;
+
+ rc = ib_to_hbl_port_num(hdev, in.port_num, &port);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "invalid IB port %u\n", in.port_num);
+ return rc;
+ }
+
+ if (!(hctx->ports_mask & BIT(port))) {
+ hbl_ibdev_dbg(ibdev, "port %d is not part of the context's ports mask 0x%llx\n",
+ port, hctx->ports_mask);
+ return -EINVAL;
+ }
+
+ usr_fifo_pdata = kzalloc(sizeof(*usr_fifo_pdata), GFP_KERNEL);
+ if (!usr_fifo_pdata)
+ return -ENOMEM;
+
+ mode = in.mode;
+
+ alloc_db_fifo_in.port = port;
+ alloc_db_fifo_in.id_hint = in.usr_fifo_num_hint;
+
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_ALLOC_USER_DB_FIFO,
+ &alloc_db_fifo_in, &alloc_db_fifo_out);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to alloc db fifo, port %d\n", port);
+ goto err_free_pdata;
+ }
+
+ id = alloc_db_fifo_out.id;
+
+ usr_fifo_pdata->port = port;
+ usr_fifo_pdata->id = id;
+
+ db_fifo_set_in.port = port;
+ db_fifo_set_in.id = id;
+ db_fifo_set_in.mode = mode;
+
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_DB_FIFO_SET, &db_fifo_set_in,
+ &db_fifo_set_out);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to set db fifo %d, port %d\n", id, port);
+ goto err_usr_fifo_unset;
+ }
+
+ out.usr_fifo_num = id;
+ out.ci_handle = db_fifo_set_out.ci_handle;
+ out.regs_handle = db_fifo_set_out.regs_handle;
+ out.regs_offset = db_fifo_set_out.regs_offset;
+ out.size = db_fifo_set_out.fifo_size;
+ out.bp_thresh = db_fifo_set_out.fifo_bp_thresh;
+
+ rc = user_fifo_mmap_entry_setup(hdev, hctx, usr_fifo_pdata, &out);
+ if (rc)
+ goto err_usr_fifo_unset;
+
+ uobj->object = usr_fifo_pdata;
+
+ rc = uverbs_copy_to_struct_or_zero(attrs, HBL_IB_ATTR_USR_FIFO_CREATE_OUT, &out,
+ sizeof(out));
+ if (rc)
+ goto err_remove_mmap_entries;
+
+ return 0;
+
+err_remove_mmap_entries:
+ user_fifo_mmap_entry_remove(usr_fifo_pdata);
+
+err_usr_fifo_unset:
+ db_fifo_unset_in.port = port;
+ db_fifo_unset_in.id = id;
+
+ if (aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_DB_FIFO_UNSET,
+ &db_fifo_unset_in, NULL))
+ hbl_ibdev_dbg(ibdev, "failed to unset db fifo %d, port %d\n", id, port);
+
+err_free_pdata:
+ kfree(usr_fifo_pdata);
+ return rc;
+}
+
+static int hbl_free_usr_fifo(struct ib_uobject *uobject, enum rdma_remove_reason why,
+ struct uverbs_attr_bundle *attrs)
+{
+ struct hbl_cni_user_db_fifo_unset_in db_fifo_unset_in = {};
+ struct hbl_usr_fifo *usr_fifo_pdata;
+ struct hbl_ib_aux_ops *aux_ops;
+ struct hbl_ib_ucontext *hctx;
+ struct hbl_aux_dev *aux_dev;
+ struct hbl_ib_device *hdev;
+ struct ib_device *ibdev;
+ int rc;
+
+ hctx = to_hbl_ib_ucontext(ib_uverbs_get_ucontext(attrs));
+ if (IS_ERR(hctx))
+ return PTR_ERR(hctx);
+
+ usr_fifo_pdata = uobject->object;
+ hdev = to_hbl_ib_dev(hctx->ibucontext.device);
+ ibdev = &hdev->ibdev;
+ aux_dev = hdev->aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ db_fifo_unset_in.port = usr_fifo_pdata->port;
+ db_fifo_unset_in.id = usr_fifo_pdata->id;
+
+ user_fifo_mmap_entry_remove(usr_fifo_pdata);
+
+ if (aux_ops->device_operational(aux_dev)) {
+ rc = aux_ops->cmd_ctrl(aux_dev, hctx->cn_ctx, HBL_CNI_OP_USER_DB_FIFO_UNSET,
+ &db_fifo_unset_in, NULL);
+ if (rc) {
+ hbl_ibdev_dbg(ibdev, "failed to unset db fifo %d, port %d\n",
+ usr_fifo_pdata->id, usr_fifo_pdata->port);
+ return rc;
+ }
+ }
+
+ kfree(usr_fifo_pdata);
+
+ return 0;
+}
+
+DECLARE_UVERBS_NAMED_METHOD(
+ HBL_IB_METHOD_USR_FIFO_OBJ_CREATE,
+ UVERBS_ATTR_IDR(HBL_IB_ATTR_USR_FIFO_CREATE_HANDLE,
+ HBL_IB_OBJECT_USR_FIFO,
+ UVERBS_ACCESS_NEW,
+ UA_MANDATORY),
+ UVERBS_ATTR_PTR_IN(HBL_IB_ATTR_USR_FIFO_CREATE_IN,
+ UVERBS_ATTR_STRUCT(struct hbl_uapi_usr_fifo_create_in, reserved3),
+ UA_MANDATORY),
+ UVERBS_ATTR_PTR_OUT(HBL_IB_ATTR_USR_FIFO_CREATE_OUT,
+ UVERBS_ATTR_STRUCT(struct hbl_uapi_usr_fifo_create_out, bp_thresh),
+ UA_MANDATORY));
+
+DECLARE_UVERBS_NAMED_METHOD_DESTROY(
+ HBL_IB_METHOD_USR_FIFO_OBJ_DESTROY,
+ UVERBS_ATTR_IDR(HBL_IB_ATTR_USR_FIFO_DESTROY_HANDLE,
+ HBL_IB_OBJECT_USR_FIFO,
+ UVERBS_ACCESS_DESTROY,
+ UA_MANDATORY));
+
+DECLARE_UVERBS_NAMED_OBJECT(HBL_IB_OBJECT_USR_FIFO,
+ UVERBS_TYPE_ALLOC_IDR(hbl_free_usr_fifo),
+ &UVERBS_METHOD(HBL_IB_METHOD_USR_FIFO_OBJ_CREATE),
+ &UVERBS_METHOD(HBL_IB_METHOD_USR_FIFO_OBJ_DESTROY));
+
+const struct uapi_definition hbl_usr_fifo_defs[] = {
+ UAPI_DEF_CHAIN_OBJ_TREE_NAMED(HBL_IB_OBJECT_USR_FIFO),
+ {},
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* [PATCH 13/15] accel/habanalabs: network scaling support
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
` (11 preceding siblings ...)
2024-06-13 8:22 ` [PATCH 12/15] RDMA/hbl: direct verbs support Omer Shpigelman
@ 2024-06-13 8:22 ` Omer Shpigelman
2024-06-19 18:41 ` Sunil Kovvuri Goutham
2024-06-13 8:22 ` [PATCH 14/15] accel/habanalabs/gaudi2: CN registers header files Omer Shpigelman
` (3 subsequent siblings)
16 siblings, 1 reply; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:22 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
Add common support for AI scaling over the network.
Initialize the hbl_cn driver via auxiliary bus and serve as its adapter
for accessing the device.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
drivers/accel/habanalabs/Kconfig | 1 +
drivers/accel/habanalabs/Makefile | 3 +
drivers/accel/habanalabs/cn/Makefile | 2 +
drivers/accel/habanalabs/cn/cn.c | 815 ++++++++++++++++++
drivers/accel/habanalabs/cn/cn.h | 133 +++
.../habanalabs/common/command_submission.c | 2 +-
drivers/accel/habanalabs/common/device.c | 23 +
drivers/accel/habanalabs/common/firmware_if.c | 20 +
drivers/accel/habanalabs/common/habanalabs.h | 43 +-
.../accel/habanalabs/common/habanalabs_drv.c | 37 +-
.../habanalabs/common/habanalabs_ioctl.c | 2 +
drivers/accel/habanalabs/common/memory.c | 123 +++
drivers/accel/habanalabs/gaudi/gaudi.c | 14 +-
drivers/accel/habanalabs/gaudi2/gaudi2.c | 14 +-
.../accel/habanalabs/gaudi2/gaudi2_security.c | 16 +-
drivers/accel/habanalabs/goya/goya.c | 6 +
.../include/hw_ip/nic/nic_general.h | 15 +
include/uapi/drm/habanalabs_accel.h | 10 +-
18 files changed, 1251 insertions(+), 28 deletions(-)
create mode 100644 drivers/accel/habanalabs/cn/Makefile
create mode 100644 drivers/accel/habanalabs/cn/cn.c
create mode 100644 drivers/accel/habanalabs/cn/cn.h
create mode 100644 drivers/accel/habanalabs/include/hw_ip/nic/nic_general.h
diff --git a/drivers/accel/habanalabs/Kconfig b/drivers/accel/habanalabs/Kconfig
index be85336107f9..dcc8d294b761 100644
--- a/drivers/accel/habanalabs/Kconfig
+++ b/drivers/accel/habanalabs/Kconfig
@@ -13,6 +13,7 @@ config DRM_ACCEL_HABANALABS
select DMA_SHARED_BUFFER
select CRC32
select FW_LOADER
+ select AUXILIARY_BUS
help
Enables PCIe card driver for Habana's AI Processors (AIP) that are
designed to accelerate Deep Learning inference and training workloads.
diff --git a/drivers/accel/habanalabs/Makefile b/drivers/accel/habanalabs/Makefile
index 98510cdd5066..37e216689d1a 100644
--- a/drivers/accel/habanalabs/Makefile
+++ b/drivers/accel/habanalabs/Makefile
@@ -8,6 +8,9 @@ obj-$(CONFIG_DRM_ACCEL_HABANALABS) := habanalabs.o
include $(src)/common/Makefile
habanalabs-y += $(HL_COMMON_FILES)
+include $(src)/cn/Makefile
+habanalabs-y += $(HL_CN_FILES)
+
include $(src)/gaudi2/Makefile
habanalabs-y += $(HL_GAUDI2_FILES)
diff --git a/drivers/accel/habanalabs/cn/Makefile b/drivers/accel/habanalabs/cn/Makefile
new file mode 100644
index 000000000000..b90d5a93a632
--- /dev/null
+++ b/drivers/accel/habanalabs/cn/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+HL_CN_FILES := cn/cn.o
diff --git a/drivers/accel/habanalabs/cn/cn.c b/drivers/accel/habanalabs/cn/cn.c
new file mode 100644
index 000000000000..29e4c2292391
--- /dev/null
+++ b/drivers/accel/habanalabs/cn/cn.c
@@ -0,0 +1,815 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "cn.h"
+
+#include "../common/habanalabs.h"
+#include <linux/file.h>
+
+static int hl_cn_send_empty_status(struct hl_device *hdev, int port)
+{
+ struct hl_cn_funcs *cn_funcs = hdev->asic_funcs->cn_funcs;
+ struct cpucp_nic_status status = {};
+ struct hl_cn_properties *cn_props;
+ struct cpucp_nic_status_packet *pkt;
+ size_t total_pkt_size, data_size;
+ u64 result;
+ int rc;
+
+ cn_props = &hdev->asic_prop.cn_props;
+ data_size = cn_props->status_packet_size;
+
+ total_pkt_size = sizeof(struct cpucp_nic_status_packet) + data_size;
+
+ /* data should be aligned to 8 bytes in order to CPU-CP to copy it */
+ total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
+
+ /* total_pkt_size is casted to u16 later on */
+ if (total_pkt_size > USHRT_MAX) {
+ dev_err(hdev->dev, "NIC status data is too big\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ pkt = kzalloc(total_pkt_size, GFP_KERNEL);
+ if (!pkt) {
+ rc = -ENOMEM;
+ goto out;
+ }
+
+ status.port = cpu_to_le32(port);
+ status.up = false;
+
+ pkt->length = cpu_to_le32(data_size / sizeof(u32));
+ memcpy(&pkt->data, &status, data_size);
+
+ pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_NIC_STATUS << CPUCP_PKT_CTL_OPCODE_SHIFT);
+
+ rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt, total_pkt_size, 0, &result);
+
+ if (rc)
+ dev_err(hdev->dev, "failed to send NIC status, port %d\n", port);
+
+ kfree(pkt);
+out:
+ cn_funcs->port_funcs->post_send_status(hdev, port);
+
+ return rc;
+}
+
+static bool hl_cn_device_operational(struct hbl_aux_dev *aux_dev)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+
+ return hl_device_operational(hdev, NULL);
+}
+
+static void hl_cn_hw_access_lock(struct hbl_aux_dev *aux_dev)
+ __acquires(&hdev->cn.hw_access_lock)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+
+ mutex_lock(&hdev->cn.hw_access_lock);
+}
+
+static void hl_cn_hw_access_unlock(struct hbl_aux_dev *aux_dev)
+ __releases(&hdev->cn.hw_access_lock)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+
+ mutex_unlock(&hdev->cn.hw_access_lock);
+}
+
+static void hl_cn_device_reset(struct hbl_aux_dev *aux_dev)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+
+ hl_device_reset(hdev, HL_DRV_RESET_HARD);
+}
+
+void *hl_cn_dma_alloc_coherent(struct hbl_aux_dev *aux_dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t flag)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+
+ return hl_asic_dma_alloc_coherent(hdev, size, dma_handle, flag);
+}
+
+void hl_cn_dma_free_coherent(struct hbl_aux_dev *aux_dev, size_t size, void *cpu_addr,
+ dma_addr_t dma_handle)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+
+ hl_asic_dma_free_coherent(hdev, size, cpu_addr, dma_handle);
+}
+
+void *hl_cn_dma_pool_zalloc(struct hbl_aux_dev *aux_dev, size_t size, gfp_t mem_flags,
+ dma_addr_t *dma_handle)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+
+ return hl_asic_dma_pool_zalloc(hdev, size, mem_flags, dma_handle);
+}
+
+void hl_cn_dma_pool_free(struct hbl_aux_dev *aux_dev, void *vaddr, dma_addr_t dma_addr)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+
+ hl_asic_dma_pool_free(hdev, vaddr, dma_addr);
+}
+
+static int hl_cn_vm_dev_mmu_map(struct hbl_aux_dev *aux_dev, u64 vm_handle,
+ enum hbl_cn_mem_type mem_type, u64 addr, u64 dva, size_t size)
+
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+
+ return hl_map_vmalloc_range(cn->ctx, addr, dva, size);
+}
+
+static void hl_cn_vm_dev_mmu_unmap(struct hbl_aux_dev *aux_dev, u64 vm_handle, u64 dva, size_t size)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+ int rc;
+
+ rc = hl_unmap_vmalloc_range(cn->ctx, dva);
+ if (rc)
+ dev_crit(hdev->dev, "Failed to unmap dva 0x%llx with size 0x%lx, err %d\n", dva,
+ size, rc);
+}
+
+static int hl_cn_vm_reserve_dva_block(struct hbl_aux_dev *aux_dev, u64 vm_handle, u64 size,
+ u64 *dva)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+ u64 addr;
+
+ addr = hl_reserve_va_block(hdev, cn->ctx, HL_VA_RANGE_TYPE_HOST, size, PAGE_SIZE);
+ if (!addr)
+ return -ENOMEM;
+
+ *dva = addr;
+
+ return 0;
+}
+
+static void hl_cn_vm_unreserve_dva_block(struct hbl_aux_dev *aux_dev, u64 vm_handle, u64 dva,
+ u64 size)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+
+ hl_unreserve_va_block(hdev, cn->ctx, dva, size);
+}
+
+void hl_cn_spmu_get_stats_info(struct hbl_aux_dev *aux_dev, u32 port, struct hbl_cn_stat **stats,
+ u32 *n_stats)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+ struct hl_cn_port_funcs *port_funcs = hdev->asic_funcs->cn_funcs->port_funcs;
+
+ port_funcs->spmu_get_stats_info(hdev, port, stats, n_stats);
+}
+
+int hl_cn_spmu_config(struct hbl_aux_dev *aux_dev, u32 port, u32 num_event_types, u32 event_types[],
+ bool enable)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+ struct hl_cn_port_funcs *port_funcs = hdev->asic_funcs->cn_funcs->port_funcs;
+
+ return port_funcs->spmu_config(hdev, port, num_event_types, event_types, enable);
+}
+
+int hl_cn_spmu_sample(struct hbl_aux_dev *aux_dev, u32 port, u32 num_out_data, u64 out_data[])
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+ struct hl_cn_port_funcs *port_funcs = hdev->asic_funcs->cn_funcs->port_funcs;
+
+ return port_funcs->spmu_sample(hdev, port, num_out_data, out_data);
+}
+
+int hl_cn_poll_reg(struct hbl_aux_dev *aux_dev, u32 reg, u64 timeout_us, hbl_cn_poll_cond_func func,
+ void *arg)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+ u32 val;
+
+ return hl_poll_timeout(hdev, reg, val, func(val, arg), 1000, timeout_us);
+}
+
+int hl_cn_send_cpu_message(struct hbl_aux_dev *aux_dev, u32 *msg, u16 len, u32 timeout, u64 *result)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+
+ return hdev->asic_funcs->send_cpu_message(hdev, msg, len, timeout, result);
+}
+
+void hl_cn_post_send_status(struct hbl_aux_dev *aux_dev, u32 port)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+ struct hl_cn_port_funcs *port_funcs = hdev->asic_funcs->cn_funcs->port_funcs;
+
+ port_funcs->post_send_status(hdev, port);
+}
+
+static u32 hl_cn_dram_readl(struct hbl_aux_dev *aux_dev, u64 addr)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+ u64 val = 0;
+ int rc;
+
+ rc = hdev->asic_funcs->access_dev_mem(hdev, PCI_REGION_DRAM, addr, &val, DEBUGFS_READ32);
+ if (rc)
+ dev_crit(hdev->dev, "Failed to readl from dev_mem addr 0x%llx\n", addr);
+
+ return val;
+}
+
+static void hl_cn_dram_writel(struct hbl_aux_dev *aux_dev, u32 val, u64 addr)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+ u64 data = val;
+ int rc;
+
+ rc = hdev->asic_funcs->access_dev_mem(hdev, PCI_REGION_DRAM, addr, &data, DEBUGFS_WRITE32);
+ if (rc)
+ dev_crit(hdev->dev, "Failed to writel to dev_mem addr 0x%llx\n", addr);
+}
+
+static u32 hl_cn_rreg(struct hbl_aux_dev *aux_dev, u32 reg)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+
+ return hdev->asic_funcs->rreg(hdev, reg);
+}
+
+static void hl_cn_wreg(struct hbl_aux_dev *aux_dev, u32 reg, u32 val)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+
+ return hdev->asic_funcs->wreg(hdev, reg, val);
+}
+
+static int hl_cn_get_reg_pcie_addr(struct hbl_aux_dev *aux_dev, u32 reg, u64 *pci_addr)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+
+ return hdev->asic_funcs->get_reg_pcie_addr(hdev, reg, pci_addr);
+}
+
+static int hl_cn_register_cn_user_context(struct hbl_aux_dev *aux_dev, int user_fd,
+ const void *cn_ctx, u64 *comp_handle, u64 *vm_handle)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+ struct drm_file *file_priv;
+ struct hl_fpriv *hpriv;
+ struct file *file;
+ int rc = 0;
+
+ if (atomic_cmpxchg(&cn->ctx_registered, 0, 1)) {
+ dev_dbg(hdev->dev, "user context is already registered\n");
+ return -EBUSY;
+ }
+
+ /* CN driver can independently manage its resources and context.
+ * However, for HL devices, corresponding HW resources can also be managed by compute side.
+ * To avoid contention (e.g. abrupt application close) between them, enforce orderly FD
+ * closure. This facilitates that CN destroy runs first, followed by compute fini.
+ */
+ file = fget(user_fd);
+ if (!file || !hl_check_fd(file)) {
+ rc = -EBADF;
+ goto file_err;
+ }
+
+ mutex_lock(&hdev->fpriv_list_lock);
+
+ if (list_empty(&hdev->fpriv_list)) {
+ dev_dbg(hdev->dev, "no open user context\n");
+ rc = -ESRCH;
+ goto open_ctx_err;
+ }
+
+ /* The list should contain a single element as currently only a single user context is
+ * allowed. Therefore get the first entry.
+ */
+ hpriv = list_first_entry(&hdev->fpriv_list, struct hl_fpriv, dev_node);
+
+ file_priv = file->private_data;
+ if (hpriv != file_priv->driver_priv) {
+ dev_dbg(hdev->dev, "user FD mismatch\n");
+ rc = -EINVAL;
+ goto fd_mismatch_err;
+ }
+
+ mutex_unlock(&hdev->fpriv_list_lock);
+
+ /* these must have different values to allow data transfer */
+ *comp_handle = 0;
+ *vm_handle = 1;
+
+ return 0;
+
+fd_mismatch_err:
+open_ctx_err:
+ mutex_unlock(&hdev->fpriv_list_lock);
+ fput(file);
+file_err:
+ atomic_set(&cn->ctx_registered, 0);
+
+ return rc;
+}
+
+static void hl_cn_deregister_cn_user_context(struct hbl_aux_dev *aux_dev, u64 vm_handle)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+ struct hl_fpriv *hpriv;
+ struct file *file;
+
+ mutex_lock(&hdev->fpriv_list_lock);
+ hpriv = list_first_entry(&hdev->fpriv_list, struct hl_fpriv, dev_node);
+ mutex_unlock(&hdev->fpriv_list_lock);
+
+ file = hpriv->file_priv->filp;
+
+ /* We can assert here that all CN resources which might have dependency on compute side are
+ * already released. Hence, release reference to compute file.
+ */
+ fput(file);
+
+ atomic_set(&cn->ctx_registered, 0);
+}
+
+static int hl_cn_vm_create(struct hbl_aux_dev *aux_dev, u64 comp_handle, u32 flags, u64 *vm_handle)
+{
+ *vm_handle = 0;
+
+ return 0;
+}
+
+static void hl_cn_vm_destroy(struct hbl_aux_dev *aux_dev, u64 vm_handle)
+{
+
+}
+
+static int hl_cn_get_vm_info(struct hbl_aux_dev *aux_dev, u64 vm_handle,
+ struct hbl_cn_vm_info *vm_info)
+{
+ vm_info->mmu_mode = HBL_CN_MMU_MODE_EXTERNAL;
+ vm_info->ext_mmu.work_id = 1;
+
+ return 0;
+}
+
+static void hl_cn_get_cpucp_info(struct hbl_aux_dev *aux_dev,
+ struct hbl_cn_cpucp_info *hl_cn_cpucp_info)
+{
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+ struct hl_device *hdev = container_of(cn, struct hl_device, cn);
+ struct hbl_cn_cpucp_info *cn_cpucp_info;
+
+ cn_cpucp_info = &hdev->asic_prop.cn_props.cpucp_info;
+
+ memcpy(hl_cn_cpucp_info, cn_cpucp_info, sizeof(*cn_cpucp_info));
+}
+
+static void hl_cn_cpucp_info_le_to_cpu(struct cpucp_nic_info *cpucp_nic_info,
+ struct hbl_cn_cpucp_info *hbl_cn_cpucp_info)
+{
+ int i;
+
+ for (i = 0 ; i < CPUCP_MAX_NICS ; i++) {
+ memcpy(&hbl_cn_cpucp_info->mac_addrs[i], &cpucp_nic_info->mac_addrs[i],
+ sizeof(cpucp_nic_info->mac_addrs[i]));
+ hbl_cn_cpucp_info->tx_swap_map[i] = le16_to_cpu(cpucp_nic_info->tx_swap_map[i]);
+ }
+
+ for (i = 0 ; i < CPUCP_NIC_MASK_ARR_LEN ; i++) {
+ hbl_cn_cpucp_info->link_mask[i] = le64_to_cpu(cpucp_nic_info->link_mask[i]);
+ hbl_cn_cpucp_info->link_ext_mask[i] = le64_to_cpu(cpucp_nic_info->link_ext_mask[i]);
+ hbl_cn_cpucp_info->auto_neg_mask[i] = le64_to_cpu(cpucp_nic_info->auto_neg_mask[i]);
+ }
+
+ for (i = 0 ; i < CPUCP_NIC_POLARITY_ARR_LEN ; i++) {
+ hbl_cn_cpucp_info->pol_tx_mask[i] = le64_to_cpu(cpucp_nic_info->pol_tx_mask[i]);
+ hbl_cn_cpucp_info->pol_rx_mask[i] = le64_to_cpu(cpucp_nic_info->pol_rx_mask[i]);
+ }
+
+ hbl_cn_cpucp_info->serdes_type = (enum cpucp_serdes_type)
+ le16_to_cpu(cpucp_nic_info->serdes_type);
+
+ memcpy(hbl_cn_cpucp_info->qsfp_eeprom, cpucp_nic_info->qsfp_eeprom,
+ sizeof(cpucp_nic_info->qsfp_eeprom));
+}
+
+static int hl_cn_get_asic_type(struct hl_device *hdev, enum hbl_cn_asic_type *asic_type)
+
+{
+ switch (hdev->asic_type) {
+ case ASIC_GAUDI2:
+ case ASIC_GAUDI2B:
+ case ASIC_GAUDI2C:
+ *asic_type = HBL_ASIC_GAUDI2;
+ break;
+ default:
+ dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int hl_cn_aux_data_init(struct hl_device *hdev)
+{
+ struct hl_cn_funcs *cn_funcs = hdev->asic_funcs->cn_funcs;
+ struct asic_fixed_properties *asic_props = &hdev->asic_prop;
+ struct hbl_cn_aux_data *aux_data;
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hl_cn *cn = &hdev->cn;
+ struct hbl_aux_dev *aux_dev;
+ u64 dram_kmd_size;
+ int rc;
+
+ aux_data = kzalloc(sizeof(*aux_data), GFP_KERNEL);
+ if (!aux_data)
+ return -ENOMEM;
+
+ aux_ops = kzalloc(sizeof(*aux_ops), GFP_KERNEL);
+ if (!aux_ops) {
+ rc = -ENOMEM;
+ goto free_aux_data;
+ }
+
+ aux_dev = &cn->cn_aux_dev;
+ aux_dev->aux_data = aux_data;
+ aux_dev->aux_ops = aux_ops;
+ aux_dev->type = HBL_AUX_DEV_CN;
+
+ aux_data->pdev = hdev->pdev;
+ aux_data->dev = hdev->dev;
+ aux_data->ports_mask = cn->ports_mask;
+ aux_data->ext_ports_mask = cn->eth_ports_mask;
+ aux_data->auto_neg_mask = cn->auto_neg_mask;
+ aux_data->fw_ver = asic_props->cpucp_info.cpucp_version;
+ aux_data->nic_drv_addr = asic_props->nic_drv_addr;
+ aux_data->nic_drv_size = asic_props->nic_drv_size;
+ aux_data->macro_cfg_size = asic_props->macro_cfg_size;
+ aux_data->pending_reset_long_timeout = hdev->pldm ? HL_PLDM_HARD_RESET_MAX_TIMEOUT :
+ HL_HARD_RESET_MAX_TIMEOUT;
+ aux_data->id = hdev->cdev_idx;
+ aux_data->pldm = hdev->pldm;
+ aux_data->skip_phy_init = hdev->cn.skip_phy_init;
+ aux_data->load_phy_fw = hdev->cn.load_fw;
+ aux_data->cpucp_fw = !!(hdev->fw_components & FW_TYPE_BOOT_CPU);
+ aux_data->supports_coresight = hdev->supports_coresight;
+ aux_data->use_fw_serdes_info = cn->use_fw_serdes_info;
+ aux_data->cache_line_size = asic_props->cache_line_size;
+ aux_data->clk = asic_props->clk;
+ aux_data->kernel_asid = HL_KERNEL_ASID_ID;
+ aux_data->card_location = cn->card_location;
+ aux_data->mmu_enable = true;
+ aux_data->lanes_per_port = cn->lanes_per_port;
+ aux_data->device_timeout = HL_DEVICE_TIMEOUT_USEC;
+ aux_data->fw_major_version = hdev->fw_inner_major_ver;
+ aux_data->fw_minor_version = hdev->fw_inner_minor_ver;
+ aux_data->fw_app_cpu_boot_dev_sts0 = asic_props->fw_app_cpu_boot_dev_sts0;
+ aux_data->fw_app_cpu_boot_dev_sts1 = asic_props->fw_app_cpu_boot_dev_sts1;
+ aux_data->cpucp_checkers_shift = NIC_CHECKERS_CHECK_SHIFT;
+
+ rc = hl_cn_get_asic_type(hdev, &aux_data->asic_type);
+ if (rc) {
+ dev_err(hdev->dev, "failed to set eth aux data asic type\n");
+ goto free_aux_ops;
+ }
+
+ dram_kmd_size = asic_props->dram_user_base_address - asic_props->dram_base_address;
+ aux_data->dram_size = (asic_props->dram_size < dram_kmd_size) ? 0 : dram_kmd_size;
+
+ /* set cn -> accel ops */
+ aux_ops->device_operational = hl_cn_device_operational;
+ aux_ops->hw_access_lock = hl_cn_hw_access_lock;
+ aux_ops->hw_access_unlock = hl_cn_hw_access_unlock;
+ aux_ops->device_reset = hl_cn_device_reset;
+ aux_ops->vm_dev_mmu_map = hl_cn_vm_dev_mmu_map;
+ aux_ops->vm_dev_mmu_unmap = hl_cn_vm_dev_mmu_unmap;
+ aux_ops->vm_reserve_dva_block = hl_cn_vm_reserve_dva_block;
+ aux_ops->vm_unreserve_dva_block = hl_cn_vm_unreserve_dva_block;
+ aux_ops->dram_readl = hl_cn_dram_readl;
+ aux_ops->dram_writel = hl_cn_dram_writel;
+ aux_ops->rreg = hl_cn_rreg;
+ aux_ops->wreg = hl_cn_wreg;
+ aux_ops->get_reg_pcie_addr = hl_cn_get_reg_pcie_addr;
+ aux_ops->register_cn_user_context = hl_cn_register_cn_user_context;
+ aux_ops->deregister_cn_user_context = hl_cn_deregister_cn_user_context;
+ aux_ops->vm_create = hl_cn_vm_create;
+ aux_ops->vm_destroy = hl_cn_vm_destroy;
+ aux_ops->get_vm_info = hl_cn_get_vm_info;
+ aux_ops->poll_reg = hl_cn_poll_reg;
+ aux_ops->get_cpucp_info = hl_cn_get_cpucp_info;
+
+ cn_funcs->set_cn_data(hdev);
+
+ return 0;
+
+free_aux_ops:
+ kfree(aux_ops);
+free_aux_data:
+ kfree(aux_data);
+
+ return rc;
+}
+
+static void hl_cn_aux_data_fini(struct hl_device *hdev)
+{
+ struct hbl_aux_dev *aux_dev = &hdev->cn.cn_aux_dev;
+
+ kfree(aux_dev->aux_ops);
+ kfree(aux_dev->aux_data);
+}
+
+static void cn_adev_release(struct device *dev)
+{
+ struct hbl_aux_dev *aux_dev = container_of(dev, struct hbl_aux_dev, adev.dev);
+ struct hl_cn *cn = container_of(aux_dev, struct hl_cn, cn_aux_dev);
+
+ cn->is_cn_aux_dev_initialized = false;
+}
+
+static int hl_cn_aux_drv_init(struct hl_device *hdev)
+{
+ struct hl_cn *cn = &hdev->cn;
+ struct hbl_aux_dev *aux_dev = &cn->cn_aux_dev;
+ struct auxiliary_device *adev;
+ int rc;
+
+ rc = hl_cn_aux_data_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "CN aux data init failed\n");
+ return rc;
+ }
+
+ adev = &aux_dev->adev;
+ adev->id = hdev->id;
+ adev->name = "cn";
+ adev->dev.parent = hdev->dev;
+ adev->dev.release = cn_adev_release;
+
+ rc = auxiliary_device_init(adev);
+ if (rc) {
+ dev_err(hdev->dev, "CN auxiliary_device_init failed\n");
+ goto aux_data_free;
+ }
+
+ rc = auxiliary_device_add(adev);
+ if (rc) {
+ dev_err(hdev->dev, "CN auxiliary_device_add failed\n");
+ goto uninit_adev;
+ }
+
+ cn->is_cn_aux_dev_initialized = true;
+
+ return 0;
+
+uninit_adev:
+ auxiliary_device_uninit(adev);
+aux_data_free:
+ hl_cn_aux_data_fini(hdev);
+
+ return rc;
+}
+
+static void hl_cn_aux_drv_fini(struct hl_device *hdev)
+{
+ struct hl_cn *cn = &hdev->cn;
+ struct auxiliary_device *adev;
+
+ if (!cn->is_cn_aux_dev_initialized)
+ return;
+
+ adev = &cn->cn_aux_dev.adev;
+
+ auxiliary_device_delete(adev);
+ auxiliary_device_uninit(adev);
+
+ hl_cn_aux_data_fini(hdev);
+}
+
+int hl_cn_reopen(struct hl_device *hdev)
+{
+ struct hl_cn_funcs *cn_funcs = hdev->asic_funcs->cn_funcs;
+ struct hbl_aux_dev *aux_dev = &hdev->cn.cn_aux_dev;
+ struct hbl_cn_aux_ops *aux_ops = aux_dev->aux_ops;
+ int rc;
+
+ /* check if the NIC is enabled */
+ if (!hdev->cn.ports_mask)
+ return 0;
+
+ if (aux_ops->ports_reopen) {
+ rc = aux_ops->ports_reopen(aux_dev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to reopen the eth ports, %d\n", rc);
+ return rc;
+ }
+ }
+
+ cn_funcs->set_hw_cap(hdev, true);
+
+ return 0;
+}
+
+int hl_cn_init(struct hl_device *hdev)
+{
+ struct hl_cn_properties *cn_props = &hdev->asic_prop.cn_props;
+ struct hl_cn_funcs *cn_funcs = hdev->asic_funcs->cn_funcs;
+ struct hl_cn *cn = &hdev->cn;
+ int rc;
+
+ /*
+ * In init flow we initialize the NIC ports from scratch. In hard reset
+ * flow, we get here after the NIC ports were halted, hence we only need to reopen them.
+ */
+ if (hdev->reset_info.in_reset)
+ return hl_cn_reopen(hdev);
+
+ cn->ports_mask &= GENMASK(cn_props->max_num_of_ports - 1, 0);
+ cn->ports_ext_mask &= cn->ports_mask;
+ cn->auto_neg_mask &= cn->ports_mask;
+
+ /* check if the NIC is enabled */
+ if (!hdev->cn.ports_mask)
+ return 0;
+
+ rc = cn_funcs->pre_core_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to pre init the NIC, %d\n", rc);
+ return rc;
+ }
+
+ /* check if all ports are disabled by the FW */
+ if (!hdev->cn.ports_mask) {
+ dev_dbg(hdev->dev, "all NIC ports are disabled by the FW\n");
+ return 0;
+ }
+
+ cn->eth_ports_mask = hdev->cn.eth_on_internal ? hdev->cn.ports_mask :
+ hdev->cn.ports_ext_mask;
+
+ /* verify the kernel module name as the auxiliary drivers will bind according to it */
+ WARN_ONCE(strcmp(HL_NAME, KBUILD_MODNAME),
+ "habanalabs name not in sync with kernel module name");
+
+ rc = hl_cn_aux_drv_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init CN driver, %d\n", rc);
+ return rc;
+ }
+
+ cn_funcs->set_hw_cap(hdev, true);
+
+ cn->is_initialized = true;
+
+ return 0;
+}
+
+void hl_cn_fini(struct hl_device *hdev)
+{
+ struct hl_cn *cn = &hdev->cn;
+
+ /* The NIC capability bit of each ASIC cannot be used as a prerequisite for this function,
+ * as we may arrive here after a failing hard reset w/o calling to hl_cn_reopen().
+ * But we can check if the NIC is totally disabled.
+ */
+ if (!hdev->cn.ports_mask)
+ return;
+
+ if (!cn->is_initialized)
+ return;
+
+ hl_cn_aux_drv_fini(hdev);
+
+ cn->is_initialized = false;
+}
+
+void hl_cn_stop(struct hl_device *hdev)
+{
+ struct hl_cn_funcs *cn_funcs = hdev->asic_funcs->cn_funcs;
+ struct hl_cn *cn = &hdev->cn;
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = &cn->cn_aux_dev;
+ aux_ops = aux_dev->aux_ops;
+
+ if (!cn_funcs->get_hw_cap(hdev))
+ return;
+
+ if (aux_ops->ports_stop)
+ aux_ops->ports_stop(aux_dev);
+
+ /* Set NIC as not initialized. */
+ cn_funcs->set_hw_cap(hdev, false);
+}
+
+void hl_cn_hard_reset_prepare(struct hl_device *hdev, bool fw_reset)
+{
+ struct hl_cn_funcs *cn_funcs = hdev->asic_funcs->cn_funcs;
+
+ if (!cn_funcs->get_hw_cap(hdev))
+ return;
+
+ cn_funcs->port_funcs->ports_stop_prepare(hdev, fw_reset, hdev->device_fini_pending);
+}
+
+int hl_cn_send_status(struct hl_device *hdev, int port, u8 cmd, u8 period)
+{
+ struct hl_cn_funcs *cn_funcs = hdev->asic_funcs->cn_funcs;
+
+ if (!cn_funcs->get_hw_cap(hdev)) {
+ if (cmd != HBL_CN_STATUS_PERIODIC_STOP)
+ return hl_cn_send_empty_status(hdev, port);
+ return 0;
+ }
+
+ return cn_funcs->port_funcs->send_port_cpucp_status(hdev, port, cmd, period);
+}
+
+void hl_cn_synchronize_irqs(struct hl_device *hdev)
+{
+ struct hl_cn_funcs *cn_funcs = hdev->asic_funcs->cn_funcs;
+ struct hbl_aux_dev *aux_dev = &hdev->cn.cn_aux_dev;
+ struct hbl_cn_aux_ops *aux_ops;
+
+ aux_ops = aux_dev->aux_ops;
+
+ if (!cn_funcs->get_hw_cap(hdev))
+ return;
+
+ if (aux_ops->synchronize_irqs)
+ aux_ops->synchronize_irqs(aux_dev);
+}
+
+int hl_cn_cpucp_info_get(struct hl_device *hdev)
+{
+ struct asic_fixed_properties *prop = &hdev->asic_prop;
+ struct cpucp_nic_info *cpucp_nic_info;
+ dma_addr_t cpucp_nic_info_dma_addr;
+ int rc;
+
+ cpucp_nic_info = hl_cpu_accessible_dma_pool_alloc(hdev,
+ sizeof(struct cpucp_nic_info),
+ &cpucp_nic_info_dma_addr);
+ if (!cpucp_nic_info) {
+ dev_err(hdev->dev,
+ "Failed to allocate DMA memory for CPU-CP NIC info packet\n");
+ return -ENOMEM;
+ }
+
+ memset(cpucp_nic_info, 0, sizeof(struct cpucp_nic_info));
+
+ /* Unfortunately, 0 is a valid type in this field from f/w perspective,
+ * so to support older f/w where they don't return this field, put
+ * here the max value so when converting serdes type to server type,
+ * we will put the UNKNOWN value into the server type.
+ */
+ cpucp_nic_info->serdes_type = cpu_to_le16(U16_MAX);
+
+ rc = hl_fw_cpucp_nic_info_get(hdev, cpucp_nic_info_dma_addr);
+ if (rc)
+ goto out;
+
+ hl_cn_cpucp_info_le_to_cpu(cpucp_nic_info, &prop->cn_props.cpucp_info);
+
+out:
+ hl_cpu_accessible_dma_pool_free(hdev, sizeof(struct cpucp_nic_info), cpucp_nic_info);
+
+ return 0;
+}
diff --git a/drivers/accel/habanalabs/cn/cn.h b/drivers/accel/habanalabs/cn/cn.h
new file mode 100644
index 000000000000..8cab5423aaca
--- /dev/null
+++ b/drivers/accel/habanalabs/cn/cn.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef CN_H_
+#define CN_H_
+
+#include <uapi/drm/habanalabs_accel.h>
+#include <linux/net/intel/cn_aux.h>
+
+#include <linux/kfifo.h>
+#include <linux/hashtable.h>
+#include <linux/ctype.h>
+
+#include <linux/habanalabs/cpucp_if.h>
+
+struct hl_device;
+struct hl_ctx;
+
+#define NIC_MACRO_CFG_SIZE hdev->asic_prop.macro_cfg_size
+#define NIC_MACRO_CFG_BASE(port) (NIC_MACRO_CFG_SIZE * ((port) >> 1))
+#define NIC_MACRO_WREG32(reg, val) WREG32(NIC_MACRO_CFG_BASE(port) + (reg), (val))
+
+/**
+ * struct hl_cn - habanalabs CN common structure.
+ * @cn_aux_dev: pointer to CN auxiliary device structure.
+ * @ctx: compute user context.
+ * @hw_access_lock: protects the HW access from CN flows.
+ * @ports_mask: contains mask of the CN ports that are enabled, as received from the f/w. This
+ * field can contain different values based on the server type
+ * @ports_ext_mask: contains mask of the CN ports that are external (used for scale-out), as
+ * received from the f/w. This field can contain different values based on the
+ * server type.
+ * @auto_neg_mask: mask of ports with Autonegotiation enabled.
+ * @eth_ports_mask: Ethernet ports enable mask.
+ * @ctx_registered: is user context registered.
+ * @card_location: the OAM number in the HLS (relevant for PMC card type).
+ * @lanes_per_port: number of physical lanes per port.
+ * @use_fw_serdes_info: true if NIC should use serdes values from F/W, false if CN should use hard
+ * coded values.
+ * @is_cn_aux_dev_initialized: true if the CN auxiliary device is initialized.
+ * @is_initialized: is device initialized.
+ * @load_fw: load PHY FW from ASIC path.
+ * @skip_phy_init: skip PHY init phase.
+ * @eth_on_internal: set internal ports as Ethernet ports.
+ */
+struct hl_cn {
+ struct hbl_aux_dev cn_aux_dev;
+ struct hl_ctx *ctx;
+ struct mutex hw_access_lock;
+ u64 ports_mask;
+ u64 ports_ext_mask;
+ u64 auto_neg_mask;
+ u64 eth_ports_mask;
+ atomic_t ctx_registered;
+ u32 card_location;
+ u8 lanes_per_port;
+ u8 use_fw_serdes_info;
+ u8 is_cn_aux_dev_initialized;
+ u8 is_initialized;
+ u8 load_fw;
+ u8 skip_phy_init;
+ u8 eth_on_internal;
+};
+
+/**
+ * struct hl_cn_port_funcs - ASIC specific CN functions that are called from common code for a
+ * specific port.
+ * @spmu_get_stats_info: get SPMU statistics information.
+ * @spmu_config: config the SPMU.
+ * @spmu_sample: read the SPMU counters.
+ * @post_send_status: ASIC-specific handler for post sending status packet to FW.
+ * @ports_stop_prepare: prepare the ports for a stop.
+ * @send_port_cpucp_status: Send port status to FW.
+ */
+struct hl_cn_port_funcs {
+ void (*spmu_get_stats_info)(struct hl_device *hdev, u32 port, struct hbl_cn_stat **stats,
+ u32 *n_stats);
+ int (*spmu_config)(struct hl_device *hdev, u32 port, u32 num_event_types, u32 event_types[],
+ bool enable);
+ int (*spmu_sample)(struct hl_device *hdev, u32 port, u32 num_out_data, u64 out_data[]);
+ void (*post_send_status)(struct hl_device *hdev, u32 port);
+ void (*ports_stop_prepare)(struct hl_device *hdev, bool fw_reset, bool in_teardown);
+ int (*send_port_cpucp_status)(struct hl_device *hdev, u32 port, u8 cmd, u8 period);
+};
+
+/**
+ * struct hl_cn_funcs - ASIC specific CN functions that are called from common code.
+ * @pre_core_init: NIC initializations to be done only once on device probe.
+ * @get_hw_cap: check rather HW capability bitmap is set for NIC.
+ * @set_hw_cap: set HW capability (on/off).
+ * @set_cn_data: ASIC data to be used by the CN driver.
+ * @port_funcs: functions called from common code for a specific NIC port.
+ */
+struct hl_cn_funcs {
+ int (*pre_core_init)(struct hl_device *hdev);
+ bool (*get_hw_cap)(struct hl_device *hdev);
+ void (*set_hw_cap)(struct hl_device *hdev, bool enable);
+ void (*set_cn_data)(struct hl_device *hdev);
+ struct hl_cn_port_funcs *port_funcs;
+};
+
+int hl_cn_init(struct hl_device *hdev);
+void hl_cn_fini(struct hl_device *hdev);
+void hl_cn_stop(struct hl_device *hdev);
+int hl_cn_reopen(struct hl_device *hdev);
+int hl_cn_send_status(struct hl_device *hdev, int port, u8 cmd, u8 period);
+void hl_cn_hard_reset_prepare(struct hl_device *hdev, bool fw_reset);
+void hl_cn_synchronize_irqs(struct hl_device *hdev);
+int hl_cn_cpucp_info_get(struct hl_device *hdev);
+void *hl_cn_dma_alloc_coherent(struct hbl_aux_dev *aux_dev, size_t size, dma_addr_t *dma_handle,
+ gfp_t flag);
+void hl_cn_dma_free_coherent(struct hbl_aux_dev *aux_dev, size_t size, void *cpu_addr,
+ dma_addr_t dma_handle);
+void *hl_cn_dma_pool_zalloc(struct hbl_aux_dev *aux_dev, size_t size, gfp_t mem_flags,
+ dma_addr_t *dma_handle);
+void hl_cn_dma_pool_free(struct hbl_aux_dev *aux_dev, void *vaddr, dma_addr_t dma_addr);
+void hl_cn_spmu_get_stats_info(struct hbl_aux_dev *aux_dev, u32 port, struct hbl_cn_stat **stats,
+ u32 *n_stats);
+int hl_cn_spmu_config(struct hbl_aux_dev *aux_dev, u32 port, u32 num_event_types, u32 event_types[],
+ bool enable);
+int hl_cn_spmu_sample(struct hbl_aux_dev *aux_dev, u32 port, u32 num_out_data, u64 out_data[]);
+int hl_cn_poll_reg(struct hbl_aux_dev *aux_dev, u32 reg, u64 timeout_us, hbl_cn_poll_cond_func func,
+ void *arg);
+int hl_cn_send_cpu_message(struct hbl_aux_dev *aux_dev, u32 *msg, u16 len, u32 timeout,
+ u64 *result);
+void hl_cn_post_send_status(struct hbl_aux_dev *aux_dev, u32 port);
+
+#endif /* CN_H_ */
diff --git a/drivers/accel/habanalabs/common/command_submission.c b/drivers/accel/habanalabs/common/command_submission.c
index 39e23d625a3c..bba6765100b2 100644
--- a/drivers/accel/habanalabs/common/command_submission.c
+++ b/drivers/accel/habanalabs/common/command_submission.c
@@ -2262,7 +2262,7 @@ static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type,
goto free_cs_chunk_array;
}
- if (!hdev->nic_ports_mask) {
+ if (!hdev->cn.ports_mask) {
atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
atomic64_inc(&cntr->validation_drop_cnt);
dev_err(hdev->dev,
diff --git a/drivers/accel/habanalabs/common/device.c b/drivers/accel/habanalabs/common/device.c
index 8f92445c5a90..bda3524fb1b4 100644
--- a/drivers/accel/habanalabs/common/device.c
+++ b/drivers/accel/habanalabs/common/device.c
@@ -963,6 +963,7 @@ static int device_early_init(struct hl_device *hdev)
INIT_LIST_HEAD(&hdev->fpriv_ctrl_list);
mutex_init(&hdev->fpriv_list_lock);
mutex_init(&hdev->fpriv_ctrl_list_lock);
+ mutex_init(&hdev->cn.hw_access_lock);
mutex_init(&hdev->clk_throttling.lock);
return 0;
@@ -1007,6 +1008,7 @@ static void device_early_fini(struct hl_device *hdev)
mutex_destroy(&hdev->debug_lock);
mutex_destroy(&hdev->send_cpu_message_lock);
+ mutex_destroy(&hdev->cn.hw_access_lock);
mutex_destroy(&hdev->fpriv_list_lock);
mutex_destroy(&hdev->fpriv_ctrl_list_lock);
@@ -1251,6 +1253,10 @@ static void take_release_locks(struct hl_device *hdev)
mutex_unlock(&hdev->fpriv_list_lock);
mutex_lock(&hdev->fpriv_ctrl_list_lock);
mutex_unlock(&hdev->fpriv_ctrl_list_lock);
+
+ /* Flush CN flows */
+ mutex_lock(&hdev->cn.hw_access_lock);
+ mutex_unlock(&hdev->cn.hw_access_lock);
}
static void hl_abort_waiting_for_completions(struct hl_device *hdev)
@@ -1868,6 +1874,12 @@ int hl_device_reset(struct hl_device *hdev, u32 flags)
goto out_err;
}
+ rc = hdev->asic_funcs->cn_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init CN driver\n");
+ goto out_err;
+ }
+
if (!hdev->asic_prop.fw_security_enabled)
hl_fw_set_max_power(hdev);
} else {
@@ -2330,6 +2342,14 @@ int hl_device_init(struct hl_device *hdev)
goto out_disabled;
}
+ /* must be called after sysfs init for the auxiliary bus */
+ rc = hdev->asic_funcs->cn_init(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to init CN driver\n");
+ rc = 0;
+ goto out_disabled;
+ }
+
/* Need to call this again because the max power might change,
* depending on card type for certain ASICs
*/
@@ -2517,6 +2537,9 @@ void hl_device_fini(struct hl_device *hdev)
hl_cb_pool_fini(hdev);
+ /* CN uses the kernel context for MMU mappings, therefore must be cleaned before it */
+ hdev->asic_funcs->cn_fini(hdev);
+
/* Reset the H/W. It will be in idle state after this returns */
rc = hdev->asic_funcs->hw_fini(hdev, true, false);
if (rc)
diff --git a/drivers/accel/habanalabs/common/firmware_if.c b/drivers/accel/habanalabs/common/firmware_if.c
index 4bd02778a970..52bbfa093ae3 100644
--- a/drivers/accel/habanalabs/common/firmware_if.c
+++ b/drivers/accel/habanalabs/common/firmware_if.c
@@ -1040,6 +1040,26 @@ int hl_fw_get_monitor_dump(struct hl_device *hdev, void *data)
return rc;
}
+int hl_fw_cpucp_nic_info_get(struct hl_device *hdev, dma_addr_t cpucp_nic_info_dma_addr)
+{
+ struct cpucp_packet pkt = {};
+ u64 result;
+ int rc;
+
+ pkt.ctl = cpu_to_le32(CPUCP_PACKET_NIC_INFO_GET <<
+ CPUCP_PKT_CTL_OPCODE_SHIFT);
+ pkt.addr = cpu_to_le64(cpucp_nic_info_dma_addr);
+ pkt.data_max_size = cpu_to_le32(sizeof(struct cpucp_nic_info));
+
+ rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+ HL_CPUCP_INFO_TIMEOUT_USEC, &result);
+ if (rc)
+ dev_err(hdev->dev,
+ "Failed to handle CPU-CP NIC info pkt, error %d\n", rc);
+
+ return rc;
+}
+
int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev,
struct hl_info_pci_counters *counters)
{
diff --git a/drivers/accel/habanalabs/common/habanalabs.h b/drivers/accel/habanalabs/common/habanalabs.h
index 48f0f3eea1ef..907e54ce0066 100644
--- a/drivers/accel/habanalabs/common/habanalabs.h
+++ b/drivers/accel/habanalabs/common/habanalabs.h
@@ -32,6 +32,7 @@
#include <drm/drm_device.h>
#include <drm/drm_file.h>
+#include "../cn/cn.h"
#include "security.h"
#define HL_NAME "habanalabs"
@@ -542,11 +543,25 @@ struct hl_hints_range {
u64 end_addr;
};
+/**
+ * struct hl_cn_properties - ASIC specific properties.
+ * @cpucp_info: received various information from CPU-CP regarding the NIC
+ * H/W, e.g. MAC addresses.
+ * @status_packet_size: size of the status packet we are going to send to F/W.
+ * @max_num_of_ports: maximum number of ports supported by ASIC.
+ */
+struct hl_cn_properties {
+ struct hbl_cn_cpucp_info cpucp_info;
+ u32 status_packet_size;
+ u8 max_num_of_ports;
+};
+
/**
* struct asic_fixed_properties - ASIC specific immutable properties.
* @hw_queues_props: H/W queues properties.
* @special_blocks: points to an array containing special blocks info.
* @skip_special_blocks_cfg: special blocks skip configs.
+ * @cn_props: CN driver properties.
* @cpucp_info: received various information from CPU-CP regarding the H/W, e.g.
* available sensors.
* @uboot_ver: F/W U-boot version.
@@ -590,6 +605,9 @@ struct hl_hints_range {
* @max_freq_value: current max clk frequency.
* @engine_core_interrupt_reg_addr: interrupt register address for engine core to use
* in order to raise events toward FW.
+ * @nic_drv_addr: base address for NIC driver on DRAM.
+ * @nic_drv_size: driver size reserved for NIC driver on DRAM.
+ * @macro_cfg_size: the size of the macro configuration space.
* @clk_pll_index: clock PLL index that specify which PLL determines the clock
* we display to the user
* @mmu_pgt_size: MMU page tables total size.
@@ -666,6 +684,7 @@ struct hl_hints_range {
* @cache_line_size: device cache line size.
* @server_type: Server type that the ASIC is currently installed in.
* The value is according to enum hl_server_type in uapi file.
+ * @clk: clock frequency in MHz.
* @completion_queues_count: number of completion queues.
* @completion_mode: 0 - job based completion, 1 - cs based completion
* @mme_master_slave_mode: 0 - Each MME works independently, 1 - MME works
@@ -705,6 +724,7 @@ struct asic_fixed_properties {
struct hw_queue_properties *hw_queues_props;
struct hl_special_block_info *special_blocks;
struct hl_skip_blocks_cfg skip_special_blocks_cfg;
+ struct hl_cn_properties cn_props;
struct cpucp_info cpucp_info;
char uboot_ver[VERSION_MAX_LEN];
char preboot_ver[VERSION_MAX_LEN];
@@ -742,6 +762,9 @@ struct asic_fixed_properties {
u64 host_end_address;
u64 max_freq_value;
u64 engine_core_interrupt_reg_addr;
+ u64 nic_drv_addr;
+ u64 nic_drv_size;
+ u32 macro_cfg_size;
u32 clk_pll_index;
u32 mmu_pgt_size;
u32 mmu_pte_size;
@@ -796,6 +819,7 @@ struct asic_fixed_properties {
u16 eq_interrupt_id;
u16 cache_line_size;
u16 server_type;
+ u16 clk;
u8 completion_queues_count;
u8 completion_mode;
u8 mme_master_slave_mode;
@@ -1562,10 +1586,14 @@ struct engines_data {
* then the timeout is the default timeout for the specific
* ASIC
* @get_hw_state: retrieve the H/W state
+ * @cn_init: init the CN H/W and I/F. This should be called in the final stage of the init flow, as
+ * we must not have anything that might fail during its initialization after the CN init.
+ * @cn_fini: perform CN cleanup.
* @pci_bars_map: Map PCI BARs.
* @init_iatu: Initialize the iATU unit inside the PCI controller.
* @rreg: Read a register. Needed for simulator support.
* @wreg: Write a register. Needed for simulator support.
+ * @get_reg_pcie_addr: Retrieve pci address.
* @halt_coresight: stop the ETF and ETR traces.
* @ctx_init: context dependent initialization.
* @ctx_fini: context dependent cleanup.
@@ -1617,6 +1645,7 @@ struct engines_data {
* @send_device_activity: indication to FW about device availability
* @set_dram_properties: set DRAM related properties.
* @set_binning_masks: set binning/enable masks for all relevant components.
+ * @cn_funcs: ASIC specific CN functions.
*/
struct hl_asic_funcs {
int (*early_init)(struct hl_device *hdev);
@@ -1692,10 +1721,13 @@ struct hl_asic_funcs {
int (*get_monitor_dump)(struct hl_device *hdev, void *data);
int (*send_cpu_message)(struct hl_device *hdev, u32 *msg,
u16 len, u32 timeout, u64 *result);
+ int (*cn_init)(struct hl_device *hdev);
+ void (*cn_fini)(struct hl_device *hdev);
int (*pci_bars_map)(struct hl_device *hdev);
int (*init_iatu)(struct hl_device *hdev);
u32 (*rreg)(struct hl_device *hdev, u32 reg);
void (*wreg)(struct hl_device *hdev, u32 reg, u32 val);
+ int (*get_reg_pcie_addr)(struct hl_device *hdev, u32 reg, u64 *pci_addr);
void (*halt_coresight)(struct hl_device *hdev, struct hl_ctx *ctx);
int (*ctx_init)(struct hl_ctx *ctx);
void (*ctx_fini)(struct hl_ctx *ctx);
@@ -1751,6 +1783,7 @@ struct hl_asic_funcs {
int (*send_device_activity)(struct hl_device *hdev, bool open);
int (*set_dram_properties)(struct hl_device *hdev);
int (*set_binning_masks)(struct hl_device *hdev);
+ struct hl_cn_funcs *cn_funcs;
};
@@ -3234,6 +3267,7 @@ struct hl_reset_info {
* @asic_prop: ASIC specific immutable properties.
* @asic_funcs: ASIC specific functions.
* @asic_specific: ASIC specific information to use only from ASIC files.
+ * @cn: CN common structure.
* @vm: virtual memory manager for MMU.
* @hwmon_dev: H/W monitor device.
* @hl_chip_info: ASIC's sensors information.
@@ -3353,7 +3387,6 @@ struct hl_reset_info {
* @supports_ctx_switch: true if a ctx switch is required upon first submission.
* @support_preboot_binning: true if we support read binning info from preboot.
* @eq_heartbeat_received: indication that eq heartbeat event has received from FW.
- * @nic_ports_mask: Controls which NIC ports are enabled. Used only for testing.
* @fw_components: Controls which f/w components to load to the device. There are multiple f/w
* stages and sometimes we want to stop at a certain stage. Used only for testing.
* @mmu_disable: Disable the device MMU(s). Used only for testing.
@@ -3413,6 +3446,7 @@ struct hl_device {
struct asic_fixed_properties asic_prop;
const struct hl_asic_funcs *asic_funcs;
void *asic_specific;
+ struct hl_cn cn;
struct hl_vm vm;
struct device *hwmon_dev;
struct hwmon_chip_info *hl_chip_info;
@@ -3518,7 +3552,6 @@ struct hl_device {
u8 eq_heartbeat_received;
/* Parameters for bring-up to be upstreamed */
- u64 nic_ports_mask;
u64 fw_components;
u8 mmu_disable;
u8 cpu_queues_enable;
@@ -3843,6 +3876,8 @@ void hl_userptr_delete_list(struct hl_device *hdev,
bool hl_userptr_is_pinned(struct hl_device *hdev, u64 addr, u32 size,
struct list_head *userptr_list,
struct hl_userptr **userptr);
+int hl_map_vmalloc_range(struct hl_ctx *ctx, u64 vmalloc_va, u64 device_va, u64 size);
+int hl_unmap_vmalloc_range(struct hl_ctx *ctx, u64 device_va);
int hl_mmu_init(struct hl_device *hdev);
void hl_mmu_fini(struct hl_device *hdev);
@@ -3943,6 +3978,7 @@ int hl_fw_cpucp_handshake(struct hl_device *hdev,
u32 boot_err1_reg);
int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size);
int hl_fw_get_monitor_dump(struct hl_device *hdev, void *data);
+int hl_fw_cpucp_nic_info_get(struct hl_device *hdev, dma_addr_t cpucp_nic_info_dma_addr);
int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev,
struct hl_info_pci_counters *counters);
int hl_fw_cpucp_total_energy_get(struct hl_device *hdev,
@@ -4059,6 +4095,9 @@ void hl_capture_engine_err(struct hl_device *hdev, u16 engine_id, u16 error_coun
void hl_enable_err_info_capture(struct hl_error_info *captured_err_info);
void hl_init_cpu_for_irq(struct hl_device *hdev);
void hl_set_irq_affinity(struct hl_device *hdev, int irq);
+int hl_get_hw_block_handle(struct hl_device *hdev, u64 address,
+ u64 *handle, u32 *size);
+bool hl_check_fd(struct file *file);
#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/accel/habanalabs/common/habanalabs_drv.c b/drivers/accel/habanalabs/common/habanalabs_drv.c
index e542fd40e16c..cee81375bfdc 100644
--- a/drivers/accel/habanalabs/common/habanalabs_drv.c
+++ b/drivers/accel/habanalabs/common/habanalabs_drv.c
@@ -110,6 +110,11 @@ static const struct drm_driver hl_driver = {
.num_ioctls = ARRAY_SIZE(hl_drm_ioctls)
};
+bool hl_check_fd(struct file *filp)
+{
+ return (filp->f_op == &hl_fops);
+}
+
/*
* get_asic_type - translate device id to asic type
*
@@ -328,9 +333,27 @@ int hl_device_open_ctrl(struct inode *inode, struct file *filp)
return rc;
}
+static u32 get_dev_nic_ports_mask(struct hl_device *hdev)
+{
+ enum hl_asic_type asic_type = hdev->asic_type;
+ u32 mask;
+
+ switch (asic_type) {
+ case ASIC_GAUDI2:
+ case ASIC_GAUDI2B:
+ case ASIC_GAUDI2C:
+ /* 24 ports are supported */
+ mask = 0xFFFFFF;
+ break;
+ default:
+ mask = 0;
+ }
+
+ return mask;
+}
+
static void set_driver_behavior_per_device(struct hl_device *hdev)
{
- hdev->nic_ports_mask = 0;
hdev->fw_components = FW_TYPE_ALL_TYPES;
hdev->cpu_queues_enable = 1;
hdev->pldm = 0;
@@ -338,6 +361,7 @@ static void set_driver_behavior_per_device(struct hl_device *hdev)
hdev->bmc_enable = 1;
hdev->reset_on_preboot_fail = 1;
hdev->heartbeat = 1;
+ hdev->card_type = cpucp_card_type_pmc;
}
static void copy_kernel_module_params_to_device(struct hl_device *hdev)
@@ -377,6 +401,8 @@ static void fixup_device_params_per_asic(struct hl_device *hdev, int timeout)
static int fixup_device_params(struct hl_device *hdev)
{
+ struct hl_cn *cn = &hdev->cn;
+ u32 dev_nic_ports_mask;
int tmp_timeout;
tmp_timeout = timeout_locked;
@@ -405,6 +431,15 @@ static int fixup_device_params(struct hl_device *hdev)
/* If CPU queues not enabled, no way to do heartbeat */
if (!hdev->cpu_queues_enable)
hdev->heartbeat = 0;
+
+ /* Adjust NIC ports parameters according to the device in-hand */
+ dev_nic_ports_mask = get_dev_nic_ports_mask(hdev);
+
+ cn->ports_mask = dev_nic_ports_mask;
+ cn->ports_ext_mask = dev_nic_ports_mask;
+ cn->auto_neg_mask = dev_nic_ports_mask;
+ cn->skip_phy_init = hdev->pldm;
+
fixup_device_params_per_asic(hdev, tmp_timeout);
return 0;
diff --git a/drivers/accel/habanalabs/common/habanalabs_ioctl.c b/drivers/accel/habanalabs/common/habanalabs_ioctl.c
index 1dd6e23172ca..d8809c74ac0f 100644
--- a/drivers/accel/habanalabs/common/habanalabs_ioctl.c
+++ b/drivers/accel/habanalabs/common/habanalabs_ioctl.c
@@ -108,6 +108,8 @@ static int hw_ip_info(struct hl_device *hdev, struct hl_info_args *args)
hw_ip.edma_enabled_mask = prop->edma_enabled_mask;
hw_ip.server_type = prop->server_type;
+ hw_ip.nic_ports_mask = hdev->cn.ports_mask;
+ hw_ip.nic_ports_external_mask = hdev->cn.eth_ports_mask;
hw_ip.security_enabled = prop->fw_security_enabled;
hw_ip.revision_id = hdev->pdev->revision;
hw_ip.rotator_enabled_mask = prop->rotator_enabled_mask;
diff --git a/drivers/accel/habanalabs/common/memory.c b/drivers/accel/habanalabs/common/memory.c
index 3348ad12c237..dd52b0ee0eef 100644
--- a/drivers/accel/habanalabs/common/memory.c
+++ b/drivers/accel/habanalabs/common/memory.c
@@ -1424,6 +1424,12 @@ static int map_block(struct hl_device *hdev, u64 address, u64 *handle, u32 *size
return 0;
}
+int hl_get_hw_block_handle(struct hl_device *hdev, u64 address,
+ u64 *handle, u32 *size)
+{
+ return map_block(hdev, address, handle, size);
+}
+
static void hw_block_vm_close(struct vm_area_struct *vma)
{
struct hl_vm_hw_block_list_node *lnode =
@@ -2940,3 +2946,120 @@ void hl_hw_block_mem_fini(struct hl_ctx *ctx)
mutex_destroy(&ctx->hw_block_list_lock);
}
+
+/**
+ * hl_map_vmalloc_range - Map vmalloc allocation to PMMU.
+ * @ctx: Associated context.
+ * @vmalloc_va: Start vmalloc virtual address.
+ * @device_va: Start device virtual address.
+ * @size: Size of allocation to map.
+ *
+ * Return: 0 on success, -ve on failure.
+ */
+int hl_map_vmalloc_range(struct hl_ctx *ctx, u64 vmalloc_va, u64 device_va, u64 size)
+{
+ struct hl_device *hdev = ctx->hdev;
+ struct hl_userptr *userptr = NULL;
+ struct hl_vm_phys_pg_pack *phys_pg_pack = NULL;
+ struct hl_vm_hash_node *hnode;
+ int rc;
+
+ /*
+ * Iterate through vmalloc pages and map them for DMA via sg-list.
+ * No need to pin the pages since we are mapping kernel memory which
+ * is never swapped out.
+ */
+ rc = dma_map_host_va(hdev, vmalloc_va, size, &userptr);
+ if (rc) {
+ dev_err(hdev->dev, "DMA mapping failed, vaddr 0x%llx\n", vmalloc_va);
+ return rc;
+ }
+
+ /*
+ * Create pack of host pages which we will later map to pmmu.
+ * Do not allow huge page optimization. We have pre allocated
+ * device VA with preset notion of alignment which is same as
+ * host page alignment.
+ */
+ rc = init_phys_pg_pack_from_userptr(ctx, userptr, &phys_pg_pack, true);
+ if (rc) {
+ dev_err(hdev->dev, "Unable to init page pack, vaddr 0x%llx\n", vmalloc_va);
+ goto err_dma_unmap;
+ }
+
+ /* Validate kernel host VA and device VA are aligned to pmmu page size. */
+ if (device_va & (phys_pg_pack->page_size - 1) ||
+ vmalloc_va & (phys_pg_pack->page_size - 1)) {
+ dev_err(hdev->dev,
+ "Unaligned mapping, host VA 0x%llx, device VA 0x%llx, page size 0x%x",
+ vmalloc_va, device_va, phys_pg_pack->page_size);
+ rc = -EINVAL;
+ goto err_free_page_pack;
+ }
+
+ mutex_lock(&hdev->mmu_lock);
+
+ /* Map page pack to pmmu */
+ rc = map_phys_pg_pack(ctx, device_va, phys_pg_pack);
+ if (rc) {
+ mutex_unlock(&hdev->mmu_lock);
+ dev_err(hdev->dev, "Mapping page pack failed, vaddr 0x%llx, device VA 0x%llx\n",
+ vmalloc_va, device_va);
+ goto err_free_page_pack;
+ }
+
+ rc = hl_mmu_invalidate_cache_range(hdev,
+ false, userptr->vm_type | MMU_OP_SKIP_LOW_CACHE_INV,
+ ctx->asid, device_va, phys_pg_pack->total_size);
+
+ mutex_unlock(&hdev->mmu_lock);
+
+ if (rc)
+ goto err_free_unmap_page_pack;
+
+ /*
+ * Keep track of mapping. Add mapped chunk to global hash list.
+ * Context release uses this list for force release if this mapping
+ * is not released gracefully.
+ */
+ hnode = kzalloc(sizeof(*hnode), GFP_KERNEL);
+ if (!hnode) {
+ rc = -ENOMEM;
+ goto err_free_unmap_page_pack;
+ }
+
+ hnode->ptr = (void *) userptr;
+ hnode->vaddr = device_va;
+
+ mutex_lock(&ctx->mem_hash_lock);
+ hash_add(ctx->mem_hash, &hnode->node, device_va);
+ mutex_unlock(&ctx->mem_hash_lock);
+
+ free_phys_pg_pack(hdev, phys_pg_pack);
+
+ return 0;
+
+err_free_unmap_page_pack:
+ unmap_phys_pg_pack(ctx, device_va, phys_pg_pack);
+err_free_page_pack:
+ free_phys_pg_pack(hdev, phys_pg_pack);
+err_dma_unmap:
+ dma_unmap_host_va(hdev, userptr);
+ return rc;
+}
+
+/**
+ * hl_unmap_vmalloc_range - Unmap vmalloc allocation from PMMU.
+ * @ctx: Associated context.
+ * @device_va: Start device virtual address.
+ *
+ * Return: 0 on success, -ve on failure.
+ */
+int hl_unmap_vmalloc_range(struct hl_ctx *ctx, u64 device_va)
+{
+ struct hl_mem_in args = {
+ .unmap.device_virt_addr = device_va,
+ };
+
+ return unmap_device_va(ctx, &args, false);
+}
diff --git a/drivers/accel/habanalabs/gaudi/gaudi.c b/drivers/accel/habanalabs/gaudi/gaudi.c
index f2b04ffb0ecb..e46bbe73fb82 100644
--- a/drivers/accel/habanalabs/gaudi/gaudi.c
+++ b/drivers/accel/habanalabs/gaudi/gaudi.c
@@ -1618,10 +1618,10 @@ static int gaudi_late_init(struct hl_device *hdev)
}
if ((hdev->card_type == cpucp_card_type_pci) &&
- (hdev->nic_ports_mask & 0x3)) {
+ (hdev->cn.ports_mask & 0x3)) {
dev_info(hdev->dev,
"PCI card detected, only 8 ports are enabled\n");
- hdev->nic_ports_mask &= ~0x3;
+ hdev->cn.ports_mask &= ~0x3;
/* Stop and disable unused NIC QMANs */
WREG32(mmNIC0_QM0_GLBL_CFG1, NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
@@ -3243,7 +3243,7 @@ static void gaudi_init_nic_qmans(struct hl_device *hdev)
mmNIC1_QM0_GLBL_CFG0 - mmNIC0_QM0_GLBL_CFG0;
int i, nic_id, internal_q_index;
- if (!hdev->nic_ports_mask)
+ if (!hdev->cn.ports_mask)
return;
if (gaudi->hw_cap_initialized & HW_CAP_NIC_MASK)
@@ -3252,7 +3252,7 @@ static void gaudi_init_nic_qmans(struct hl_device *hdev)
dev_dbg(hdev->dev, "Initializing NIC QMANs\n");
for (nic_id = 0 ; nic_id < NIC_NUMBER_OF_ENGINES ; nic_id++) {
- if (!(hdev->nic_ports_mask & (1 << nic_id))) {
+ if (!(hdev->cn.ports_mask & (1 << nic_id))) {
nic_offset += nic_delta_between_qmans;
if (nic_id & 1) {
nic_offset -= (nic_delta_between_qmans * 2);
@@ -9117,6 +9117,11 @@ static int gaudi_send_device_activity(struct hl_device *hdev, bool open)
return 0;
}
+static int gaudi_get_reg_pcie_addr(struct hl_device *hdev, u32 reg, u64 *pci_addr)
+{
+ return -EOPNOTSUPP;
+}
+
static const struct hl_asic_funcs gaudi_funcs = {
.early_init = gaudi_early_init,
.early_fini = gaudi_early_fini,
@@ -9172,6 +9177,7 @@ static const struct hl_asic_funcs gaudi_funcs = {
.init_iatu = gaudi_init_iatu,
.rreg = hl_rreg,
.wreg = hl_wreg,
+ .get_reg_pcie_addr = gaudi_get_reg_pcie_addr,
.halt_coresight = gaudi_halt_coresight,
.ctx_init = gaudi_ctx_init,
.ctx_fini = gaudi_ctx_fini,
diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2.c b/drivers/accel/habanalabs/gaudi2/gaudi2.c
index fa1c4feb9f89..a22d2a93394e 100644
--- a/drivers/accel/habanalabs/gaudi2/gaudi2.c
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2.c
@@ -3222,7 +3222,7 @@ static void gaudi2_init_arcs(struct hl_device *hdev)
continue;
if (gaudi2_is_arc_nic_owned(arc_id) &&
- !(hdev->nic_ports_mask & BIT_ULL(arc_id - CPU_ID_NIC_QMAN_ARC0)))
+ !(hdev->cn.ports_mask & BIT_ULL(arc_id - CPU_ID_NIC_QMAN_ARC0)))
continue;
if (gaudi2_is_arc_tpc_owned(arc_id) && !(gaudi2->tpc_hw_cap_initialized &
@@ -3996,7 +3996,7 @@ static void gaudi2_stop_nic_qmans(struct hl_device *hdev)
queue_id = GAUDI2_QUEUE_ID_NIC_0_0;
for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++, queue_id += NUM_OF_PQ_PER_QMAN) {
- if (!(hdev->nic_ports_mask & BIT(i)))
+ if (!(hdev->cn.ports_mask & BIT(i)))
continue;
reg_base = gaudi2_qm_blocks_bases[queue_id];
@@ -4192,7 +4192,7 @@ static void gaudi2_disable_nic_qmans(struct hl_device *hdev)
queue_id = GAUDI2_QUEUE_ID_NIC_0_0;
for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++, queue_id += NUM_OF_PQ_PER_QMAN) {
- if (!(hdev->nic_ports_mask & BIT(i)))
+ if (!(hdev->cn.ports_mask & BIT(i)))
continue;
reg_base = gaudi2_qm_blocks_bases[queue_id];
@@ -4661,7 +4661,7 @@ static void gaudi2_nic_qmans_manual_flush(struct hl_device *hdev)
queue_id = GAUDI2_QUEUE_ID_NIC_0_0;
for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++, queue_id += NUM_OF_PQ_PER_QMAN) {
- if (!(hdev->nic_ports_mask & BIT(i)))
+ if (!(hdev->cn.ports_mask & BIT(i)))
continue;
gaudi2_qman_manual_flush_common(hdev, queue_id);
@@ -7279,7 +7279,7 @@ static bool gaudi2_get_nic_idle_status(struct hl_device *hdev, u64 *mask_arr, u8
u64 offset = 0;
/* NIC, twelve macros in Full chip */
- if (e && hdev->nic_ports_mask)
+ if (e && hdev->cn.ports_mask)
hl_engine_data_sprintf(e,
"\nNIC is_idle QM_GLBL_STS0 QM_CGM_STS\n"
"--- ------- ------------ ----------\n");
@@ -7290,7 +7290,7 @@ static bool gaudi2_get_nic_idle_status(struct hl_device *hdev, u64 *mask_arr, u8
else
offset += NIC_QM_OFFSET;
- if (!(hdev->nic_ports_mask & BIT(i)))
+ if (!(hdev->cn.ports_mask & BIT(i)))
continue;
engine_idx = GAUDI2_ENGINE_ID_NIC0_0 + i;
@@ -8333,7 +8333,7 @@ static void gaudi2_check_if_razwi_happened(struct hl_device *hdev)
/* check all NICs */
for (mod_idx = 0 ; mod_idx < NIC_NUMBER_OF_PORTS ; mod_idx++)
- if (hdev->nic_ports_mask & BIT(mod_idx))
+ if (hdev->cn.ports_mask & BIT(mod_idx))
gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_NIC, mod_idx >> 1, 0,
NULL);
diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_security.c b/drivers/accel/habanalabs/gaudi2/gaudi2_security.c
index 34bf80c5a44b..bb837be47908 100644
--- a/drivers/accel/habanalabs/gaudi2/gaudi2_security.c
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2_security.c
@@ -3493,7 +3493,7 @@ static int gaudi2_init_protection_bits(struct hl_device *hdev)
rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
HL_PB_SINGLE_INSTANCE, HL_PB_NA,
gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0),
- NULL, HL_PB_NA, hdev->nic_ports_mask);
+ NULL, HL_PB_NA, hdev->cn.ports_mask);
/* NIC QM and QPC */
rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
@@ -3501,7 +3501,7 @@ static int gaudi2_init_protection_bits(struct hl_device *hdev)
gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),
gaudi2_pb_nic0_qm_qpc_unsecured_regs,
ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc_unsecured_regs),
- hdev->nic_ports_mask);
+ hdev->cn.ports_mask);
/* NIC QM ARC */
rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
@@ -3510,7 +3510,7 @@ static int gaudi2_init_protection_bits(struct hl_device *hdev)
ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0),
gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs,
ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs),
- hdev->nic_ports_mask);
+ hdev->cn.ports_mask);
/* NIC UMR */
rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
@@ -3519,7 +3519,7 @@ static int gaudi2_init_protection_bits(struct hl_device *hdev)
ARRAY_SIZE(gaudi2_pb_nic0_umr),
gaudi2_pb_nic0_umr_unsecured_regs,
ARRAY_SIZE(gaudi2_pb_nic0_umr_unsecured_regs),
- hdev->nic_ports_mask);
+ hdev->cn.ports_mask);
/* Rotators */
instance_offset = mmROT1_BASE - mmROT0_BASE;
@@ -3799,22 +3799,22 @@ void gaudi2_ack_protection_bits_errors(struct hl_device *hdev)
/* NIC */
hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
- gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), hdev->nic_ports_mask);
+ gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), hdev->cn.ports_mask);
/* NIC QM and QPC */
hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
NIC_QM_OFFSET, gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),
- hdev->nic_ports_mask);
+ hdev->cn.ports_mask);
/* NIC QM ARC */
hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
NIC_QM_OFFSET, gaudi2_pb_nic0_qm_arc_aux0,
- ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), hdev->nic_ports_mask);
+ ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), hdev->cn.ports_mask);
/* NIC UMR */
hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
NIC_QM_OFFSET, gaudi2_pb_nic0_umr, ARRAY_SIZE(gaudi2_pb_nic0_umr),
- hdev->nic_ports_mask);
+ hdev->cn.ports_mask);
/* Rotators */
instance_offset = mmROT1_BASE - mmROT0_BASE;
diff --git a/drivers/accel/habanalabs/goya/goya.c b/drivers/accel/habanalabs/goya/goya.c
index 5a359c3bdc78..e0a803bde463 100644
--- a/drivers/accel/habanalabs/goya/goya.c
+++ b/drivers/accel/habanalabs/goya/goya.c
@@ -5438,6 +5438,11 @@ static int goya_send_device_activity(struct hl_device *hdev, bool open)
return 0;
}
+static int goya_get_reg_pcie_addr(struct hl_device *hdev, u32 reg, u64 *pci_addr)
+{
+ return -EOPNOTSUPP;
+}
+
static const struct hl_asic_funcs goya_funcs = {
.early_init = goya_early_init,
.early_fini = goya_early_fini,
@@ -5493,6 +5498,7 @@ static const struct hl_asic_funcs goya_funcs = {
.init_iatu = goya_init_iatu,
.rreg = hl_rreg,
.wreg = hl_wreg,
+ .get_reg_pcie_addr = goya_get_reg_pcie_addr,
.halt_coresight = goya_halt_coresight,
.ctx_init = goya_ctx_init,
.ctx_fini = goya_ctx_fini,
diff --git a/drivers/accel/habanalabs/include/hw_ip/nic/nic_general.h b/drivers/accel/habanalabs/include/hw_ip/nic/nic_general.h
new file mode 100644
index 000000000000..5d300118d069
--- /dev/null
+++ b/drivers/accel/habanalabs/include/hw_ip/nic/nic_general.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef INCLUDE_NIC_GENERAL_H_
+#define INCLUDE_NIC_GENERAL_H_
+
+#define HABANALABS_MAC_OUI_1 0xB0FD0B
+#define HABANALABS_MAC_OUI_2 0x68932E
+
+#endif /* INCLUDE_NIC_GENERAL_H_ */
diff --git a/include/uapi/drm/habanalabs_accel.h b/include/uapi/drm/habanalabs_accel.h
index a512dc4cffd0..c2c987ba3998 100644
--- a/include/uapi/drm/habanalabs_accel.h
+++ b/include/uapi/drm/habanalabs_accel.h
@@ -935,14 +935,14 @@ struct hl_info_hw_ip_info {
__u8 reserved2;
__u64 reserved3;
__u64 device_mem_alloc_default_page_size;
- __u64 reserved4;
- __u64 reserved5;
- __u32 reserved6;
- __u8 reserved7;
+ __u64 nic_ports_mask;
+ __u64 nic_ports_external_mask;
+ __u32 reserved4;
+ __u8 reserved5;
__u8 revision_id;
__u16 tpc_interrupt_id;
__u32 rotator_enabled_mask;
- __u32 reserved9;
+ __u32 reserved6;
__u64 engine_core_interrupt_reg_addr;
__u64 reserved_dram_size;
};
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* [PATCH 14/15] accel/habanalabs/gaudi2: CN registers header files
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
` (12 preceding siblings ...)
2024-06-13 8:22 ` [PATCH 13/15] accel/habanalabs: network scaling support Omer Shpigelman
@ 2024-06-13 8:22 ` Omer Shpigelman
2024-06-13 8:22 ` [PATCH 15/15] accel/habanalabs/gaudi2: network scaling support Omer Shpigelman
` (2 subsequent siblings)
16 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:22 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
Add the relevant CN registers header files. These files are generated
automatically from a tool maintained by the VLSI engineers.
These are required for the upcoming GAUDI2 CN driver support.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
.../include/gaudi2/asic_reg/gaudi2_regs.h | 10 +-
.../include/gaudi2/asic_reg/nic0_phy_regs.h | 59 ++
.../nic0_qm0_axuser_nonsecured_regs.h | 61 ++
.../include/gaudi2/asic_reg/nic0_qpc1_regs.h | 905 ++++++++++++++++++
.../include/gaudi2/asic_reg/nic0_rxe0_regs.h | 725 ++++++++++++++
.../include/gaudi2/asic_reg/nic0_rxe1_regs.h | 725 ++++++++++++++
.../include/gaudi2/asic_reg/nic0_txe0_regs.h | 529 ++++++++++
.../include/gaudi2/asic_reg/nic0_txs0_regs.h | 289 ++++++
8 files changed, 3302 insertions(+), 1 deletion(-)
create mode 100644 drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_phy_regs.h
create mode 100644 drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_axuser_nonsecured_regs.h
create mode 100644 drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qpc1_regs.h
create mode 100644 drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_rxe0_regs.h
create mode 100644 drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_rxe1_regs.h
create mode 100644 drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_txe0_regs.h
create mode 100644 drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_txs0_regs.h
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h
index d21fcd3880b4..4aa0117dc62a 100644
--- a/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright 2020-2023 HabanaLabs, Ltd.
+ * Copyright 2020-2024 HabanaLabs, Ltd.
* All Rights Reserved.
*
*/
@@ -563,6 +563,14 @@
#include "nic0_qm0_cgm_regs.h"
#include "nic0_umr0_0_completion_queue_ci_1_regs.h"
#include "nic0_umr0_0_unsecure_doorbell0_regs.h"
+#include "nic0_qm0_axuser_nonsecured_regs.h"
+#include "nic0_txe0_regs.h"
+#include "nic0_rxe0_regs.h"
+#include "nic0_rxe1_regs.h"
+#include "nic0_txs0_regs.h"
+#include "nic0_phy_regs.h"
+#include "nic0_qpc1_regs.h"
+#include "nic0_rxe0_regs.h"
#define NIC_OFFSET (mmNIC1_MSTR_IF_RR_SHRD_HBW_BASE - mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE)
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_phy_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_phy_regs.h
new file mode 100644
index 000000000000..f7d21bf181fd
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_phy_regs.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_PHY_REGS_H_
+#define ASIC_REG_NIC0_PHY_REGS_H_
+
+/*
+ *****************************************
+ * NIC0_PHY
+ * (Prototype: PRT_PHY)
+ *****************************************
+ */
+
+#define mmNIC0_PHY_PHY_RX_STS_0 0x5460000
+
+#define mmNIC0_PHY_PHY_RX_STS_1 0x5460004
+
+#define mmNIC0_PHY_PHY_RX_STS_2 0x5460008
+
+#define mmNIC0_PHY_PHY_RX_STS_3 0x546000C
+
+#define mmNIC0_PHY_PHY_RX_CFG_0 0x5460010
+
+#define mmNIC0_PHY_PHY_RX_CFG_1 0x5460014
+
+#define mmNIC0_PHY_PHY_RX_CFG_2 0x5460018
+
+#define mmNIC0_PHY_PHY_RX_CFG_3 0x546001C
+
+#define mmNIC0_PHY_PHY_TX_STS_0 0x5460020
+
+#define mmNIC0_PHY_PHY_TX_STS_1 0x5460024
+
+#define mmNIC0_PHY_PHY_TX_STS_2 0x5460028
+
+#define mmNIC0_PHY_PHY_TX_STS_3 0x546002C
+
+#define mmNIC0_PHY_PHY_RST_CFG 0x5460030
+
+#define mmNIC0_PHY_PHY_CFG_ADDR 0x5460040
+
+#define mmNIC0_PHY_PHY_LINK_STS_INTR 0x5460050
+
+#define mmNIC0_PHY_PHY_IDDQ_0 0x5460060
+
+#define mmNIC0_PHY_PHY_IDDQ_1 0x5460064
+
+#define mmNIC0_PHY_PHY_ASYNC_LANE_SWAP 0x5460068
+
+#endif /* ASIC_REG_NIC0_PHY_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_axuser_nonsecured_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_axuser_nonsecured_regs.h
new file mode 100644
index 000000000000..adc0eec56f0c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_axuser_nonsecured_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QM0_AXUSER_NONSECURED_REGS_H_
+#define ASIC_REG_NIC0_QM0_AXUSER_NONSECURED_REGS_H_
+
+/*
+ *****************************************
+ * NIC0_QM0_AXUSER_NONSECURED
+ * (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_HB_ASID 0x541AB80
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_HB_MMU_BP 0x541AB84
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_HB_STRONG_ORDER 0x541AB88
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_HB_NO_SNOOP 0x541AB8C
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_HB_WR_REDUCTION 0x541AB90
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_HB_RD_ATOMIC 0x541AB94
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_HB_QOS 0x541AB98
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_HB_RSVD 0x541AB9C
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x541ABA0
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_HB_CORE 0x541ABA4
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_E2E_COORD 0x541ABA8
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x541ABB0
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x541ABB4
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x541ABB8
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x541ABBC
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_LB_COORD 0x541ABC0
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_LB_LOCK 0x541ABC4
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_LB_RSVD 0x541ABC8
+
+#define mmNIC0_QM0_AXUSER_NONSECURED_LB_OVRD 0x541ABCC
+
+#endif /* ASIC_REG_NIC0_QM0_AXUSER_NONSECURED_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qpc1_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qpc1_regs.h
new file mode 100644
index 000000000000..9d1443fffb2d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qpc1_regs.h
@@ -0,0 +1,905 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC1_REGS_H_
+#define ASIC_REG_NIC0_QPC1_REGS_H_
+
+/*
+ *****************************************
+ * NIC0_QPC1
+ * (Prototype: NIC_QPC)
+ *****************************************
+ */
+
+#define mmNIC0_QPC1_REQ_QPC_CACHE_INVALIDATE 0x543F000
+
+#define mmNIC0_QPC1_REQ_QPC_CACHE_INV_STATUS 0x543F004
+
+#define mmNIC0_QPC1_REQ_STATIC_CONFIG 0x543F008
+
+#define mmNIC0_QPC1_REQ_BASE_ADDRESS_63_32 0x543F00C
+
+#define mmNIC0_QPC1_REQ_BASE_ADDRESS_31_7 0x543F010
+
+#define mmNIC0_QPC1_REQ_CLEAN_LINK_LIST 0x543F014
+
+#define mmNIC0_QPC1_REQ_ERR_FIFO_PUSH_63_32 0x543F018
+
+#define mmNIC0_QPC1_REQ_ERR_FIFO_PUSH_31_0 0x543F01C
+
+#define mmNIC0_QPC1_REQ_ERR_QP_STATE_63_32 0x543F020
+
+#define mmNIC0_QPC1_REQ_ERR_QP_STATE_31_0 0x543F024
+
+#define mmNIC0_QPC1_RETRY_COUNT_MAX 0x543F028
+
+#define mmNIC0_QPC1_AXI_PROT 0x543F030
+
+#define mmNIC0_QPC1_RES_QPC_CACHE_INVALIDATE 0x543F034
+
+#define mmNIC0_QPC1_RES_QPC_CACHE_INV_STATUS 0x543F038
+
+#define mmNIC0_QPC1_RES_STATIC_CONFIG 0x543F03C
+
+#define mmNIC0_QPC1_RES_BASE_ADDRESS_63_32 0x543F040
+
+#define mmNIC0_QPC1_RES_BASE_ADDRESS_31_7 0x543F044
+
+#define mmNIC0_QPC1_RES_CLEAN_LINK_LIST 0x543F048
+
+#define mmNIC0_QPC1_ERR_FIFO_WRITE_INDEX 0x543F050
+
+#define mmNIC0_QPC1_ERR_FIFO_PRODUCER_INDEX 0x543F054
+
+#define mmNIC0_QPC1_ERR_FIFO_CONSUMER_INDEX 0x543F058
+
+#define mmNIC0_QPC1_ERR_FIFO_MASK 0x543F05C
+
+#define mmNIC0_QPC1_ERR_FIFO_CREDIT 0x543F060
+
+#define mmNIC0_QPC1_ERR_FIFO_CFG 0x543F064
+
+#define mmNIC0_QPC1_ERR_FIFO_INTR_MASK 0x543F068
+
+#define mmNIC0_QPC1_ERR_FIFO_BASE_ADDR_63_32 0x543F06C
+
+#define mmNIC0_QPC1_ERR_FIFO_BASE_ADDR_31_7 0x543F070
+
+#define mmNIC0_QPC1_GW_BUSY 0x543F080
+
+#define mmNIC0_QPC1_GW_CTRL 0x543F084
+
+#define mmNIC0_QPC1_GW_DATA_0 0x543F08C
+
+#define mmNIC0_QPC1_GW_DATA_1 0x543F090
+
+#define mmNIC0_QPC1_GW_DATA_2 0x543F094
+
+#define mmNIC0_QPC1_GW_DATA_3 0x543F098
+
+#define mmNIC0_QPC1_GW_DATA_4 0x543F09C
+
+#define mmNIC0_QPC1_GW_DATA_5 0x543F0A0
+
+#define mmNIC0_QPC1_GW_DATA_6 0x543F0A4
+
+#define mmNIC0_QPC1_GW_DATA_7 0x543F0A8
+
+#define mmNIC0_QPC1_GW_DATA_8 0x543F0AC
+
+#define mmNIC0_QPC1_GW_DATA_9 0x543F0B0
+
+#define mmNIC0_QPC1_GW_DATA_10 0x543F0B4
+
+#define mmNIC0_QPC1_GW_DATA_11 0x543F0B8
+
+#define mmNIC0_QPC1_GW_DATA_12 0x543F0BC
+
+#define mmNIC0_QPC1_GW_DATA_13 0x543F0C0
+
+#define mmNIC0_QPC1_GW_DATA_14 0x543F0C4
+
+#define mmNIC0_QPC1_GW_DATA_15 0x543F0C8
+
+#define mmNIC0_QPC1_GW_DATA_16 0x543F0CC
+
+#define mmNIC0_QPC1_GW_DATA_17 0x543F0D0
+
+#define mmNIC0_QPC1_GW_DATA_18 0x543F0D4
+
+#define mmNIC0_QPC1_GW_DATA_19 0x543F0D8
+
+#define mmNIC0_QPC1_GW_DATA_20 0x543F0DC
+
+#define mmNIC0_QPC1_GW_DATA_21 0x543F0E0
+
+#define mmNIC0_QPC1_GW_DATA_22 0x543F0E4
+
+#define mmNIC0_QPC1_GW_DATA_23 0x543F0E8
+
+#define mmNIC0_QPC1_GW_DATA_24 0x543F0EC
+
+#define mmNIC0_QPC1_GW_DATA_25 0x543F0F0
+
+#define mmNIC0_QPC1_GW_DATA_26 0x543F0F4
+
+#define mmNIC0_QPC1_GW_DATA_27 0x543F0F8
+
+#define mmNIC0_QPC1_GW_DATA_28 0x543F0FC
+
+#define mmNIC0_QPC1_GW_DATA_29 0x543F100
+
+#define mmNIC0_QPC1_GW_DATA_30 0x543F104
+
+#define mmNIC0_QPC1_GW_DATA_31 0x543F108
+
+#define mmNIC0_QPC1_GW_MASK_0 0x543F124
+
+#define mmNIC0_QPC1_GW_MASK_1 0x543F128
+
+#define mmNIC0_QPC1_GW_MASK_2 0x543F12C
+
+#define mmNIC0_QPC1_GW_MASK_3 0x543F130
+
+#define mmNIC0_QPC1_GW_MASK_4 0x543F134
+
+#define mmNIC0_QPC1_GW_MASK_5 0x543F138
+
+#define mmNIC0_QPC1_GW_MASK_6 0x543F13C
+
+#define mmNIC0_QPC1_GW_MASK_7 0x543F140
+
+#define mmNIC0_QPC1_GW_MASK_8 0x543F144
+
+#define mmNIC0_QPC1_GW_MASK_9 0x543F148
+
+#define mmNIC0_QPC1_GW_MASK_10 0x543F14C
+
+#define mmNIC0_QPC1_GW_MASK_11 0x543F150
+
+#define mmNIC0_QPC1_GW_MASK_12 0x543F154
+
+#define mmNIC0_QPC1_GW_MASK_13 0x543F158
+
+#define mmNIC0_QPC1_GW_MASK_14 0x543F15C
+
+#define mmNIC0_QPC1_GW_MASK_15 0x543F160
+
+#define mmNIC0_QPC1_GW_MASK_16 0x543F164
+
+#define mmNIC0_QPC1_GW_MASK_17 0x543F168
+
+#define mmNIC0_QPC1_GW_MASK_18 0x543F16C
+
+#define mmNIC0_QPC1_GW_MASK_19 0x543F170
+
+#define mmNIC0_QPC1_GW_MASK_20 0x543F174
+
+#define mmNIC0_QPC1_GW_MASK_21 0x543F178
+
+#define mmNIC0_QPC1_GW_MASK_22 0x543F17C
+
+#define mmNIC0_QPC1_GW_MASK_23 0x543F180
+
+#define mmNIC0_QPC1_GW_MASK_24 0x543F184
+
+#define mmNIC0_QPC1_GW_MASK_25 0x543F188
+
+#define mmNIC0_QPC1_GW_MASK_26 0x543F18C
+
+#define mmNIC0_QPC1_GW_MASK_27 0x543F190
+
+#define mmNIC0_QPC1_GW_MASK_28 0x543F194
+
+#define mmNIC0_QPC1_GW_MASK_29 0x543F198
+
+#define mmNIC0_QPC1_GW_MASK_30 0x543F19C
+
+#define mmNIC0_QPC1_GW_MASK_31 0x543F1A0
+
+#define mmNIC0_QPC1_CC_TIMEOUT 0x543F1B0
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_EN 0x543F1FC
+
+#define mmNIC0_QPC1_CC_TICK_WRAP 0x543F200
+
+#define mmNIC0_QPC1_CC_ROLLBACK 0x543F204
+
+#define mmNIC0_QPC1_CC_MAX_WINDOW_SIZE 0x543F208
+
+#define mmNIC0_QPC1_CC_MIN_WINDOW_SIZE 0x543F20C
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_0 0x543F210
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_1 0x543F214
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_2 0x543F218
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_3 0x543F21C
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_4 0x543F220
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_5 0x543F224
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_6 0x543F228
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_7 0x543F22C
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_8 0x543F230
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_9 0x543F234
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_10 0x543F238
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_11 0x543F23C
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_12 0x543F240
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_13 0x543F244
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_14 0x543F248
+
+#define mmNIC0_QPC1_CC_ALPHA_LINEAR_15 0x543F24C
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_0 0x543F250
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_1 0x543F254
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_2 0x543F258
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_3 0x543F25C
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_4 0x543F260
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_5 0x543F264
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_6 0x543F268
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_7 0x543F26C
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_8 0x543F270
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_9 0x543F274
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_10 0x543F278
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_11 0x543F27C
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_12 0x543F280
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_13 0x543F284
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_14 0x543F288
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_15 0x543F28C
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_0 0x543F290
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_1 0x543F294
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_2 0x543F298
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_3 0x543F29C
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_4 0x543F2A0
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_5 0x543F2A4
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_6 0x543F2A8
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_7 0x543F2AC
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_8 0x543F2B0
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_9 0x543F2B4
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_10 0x543F2B8
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_11 0x543F2BC
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_12 0x543F2C0
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_13 0x543F2C4
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_14 0x543F2C8
+
+#define mmNIC0_QPC1_CC_ALPHA_LOG_THRESHOLD_15 0x543F2CC
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_0 0x543F2D0
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_1 0x543F2D4
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_2 0x543F2D8
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_3 0x543F2DC
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_4 0x543F2E0
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_5 0x543F2E4
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_6 0x543F2E8
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_7 0x543F2EC
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_8 0x543F2F0
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_9 0x543F2F4
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_10 0x543F2F8
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_11 0x543F2FC
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_12 0x543F300
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_13 0x543F304
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_14 0x543F308
+
+#define mmNIC0_QPC1_CC_WINDOW_INC_15 0x543F30C
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_0 0x543F310
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_1 0x543F314
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_2 0x543F318
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_3 0x543F31C
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_4 0x543F320
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_5 0x543F324
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_6 0x543F328
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_7 0x543F32C
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_8 0x543F330
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_9 0x543F334
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_10 0x543F338
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_11 0x543F33C
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_12 0x543F340
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_13 0x543F344
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_14 0x543F348
+
+#define mmNIC0_QPC1_CC_WINDOW_IN_THRESHOLD_15 0x543F34C
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_0 0x543F360
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_1 0x543F364
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_2 0x543F368
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_3 0x543F36C
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_4 0x543F370
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_5 0x543F374
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_6 0x543F378
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_7 0x543F37C
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_8 0x543F380
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_9 0x543F384
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_10 0x543F388
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_11 0x543F38C
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_12 0x543F390
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_13 0x543F394
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_14 0x543F398
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_15 0x543F39C
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_16 0x543F3A0
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_17 0x543F3A4
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_18 0x543F3A8
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_19 0x543F3AC
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_20 0x543F3B0
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_21 0x543F3B4
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_22 0x543F3B8
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_23 0x543F3BC
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_24 0x543F3C0
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_25 0x543F3C4
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_26 0x543F3C8
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_27 0x543F3CC
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_28 0x543F3D0
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_29 0x543F3D4
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_30 0x543F3D8
+
+#define mmNIC0_QPC1_DB_FIFO_USER_OVRD_31 0x543F3DC
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_0 0x543F3E0
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_1 0x543F3E4
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_2 0x543F3E8
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_3 0x543F3EC
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_4 0x543F3F0
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_5 0x543F3F4
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_6 0x543F3F8
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_7 0x543F3FC
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_8 0x543F400
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_9 0x543F404
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_10 0x543F408
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_11 0x543F40C
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_12 0x543F410
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_13 0x543F414
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_14 0x543F418
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_15 0x543F41C
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_16 0x543F420
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_17 0x543F424
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_18 0x543F428
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_19 0x543F42C
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_20 0x543F430
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_21 0x543F434
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_22 0x543F438
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_23 0x543F43C
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_24 0x543F440
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_25 0x543F444
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_26 0x543F448
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_27 0x543F44C
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_28 0x543F450
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_29 0x543F454
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_30 0x543F458
+
+#define mmNIC0_QPC1_DB_FIFO_CFG_31 0x543F45C
+
+#define mmNIC0_QPC1_SECURED_DB_FIRST32 0x543F460
+
+#define mmNIC0_QPC1_SECURED_DB_SECOND32 0x543F464
+
+#define mmNIC0_QPC1_SECURED_DB_THIRD32 0x543F468
+
+#define mmNIC0_QPC1_SECURED_DB_FOURTH32 0x543F46C
+
+#define mmNIC0_QPC1_PRIVILEGE_DB_FIRST32 0x543F470
+
+#define mmNIC0_QPC1_PRIVILEGE_DB_SECOND32 0x543F474
+
+#define mmNIC0_QPC1_PRIVILEGE_DB_THIRD32 0x543F478
+
+#define mmNIC0_QPC1_PRIVILEGE_DB_FOURTH32 0x543F47C
+
+#define mmNIC0_QPC1_DBG_INDICATION 0x543F480
+
+#define mmNIC0_QPC1_WTD_WC_FSM 0x543F484
+
+#define mmNIC0_QPC1_WTD_SLICE_FSM 0x543F488
+
+#define mmNIC0_QPC1_REQ_TX_EMPTY_CNT 0x543F48C
+
+#define mmNIC0_QPC1_RES_TX_EMPTY_CNT 0x543F490
+
+#define mmNIC0_QPC1_NUM_ROLLBACKS 0x543F494
+
+#define mmNIC0_QPC1_LAST_QP_ROLLED_BACK 0x543F498
+
+#define mmNIC0_QPC1_NUM_TIMEOUTS 0x543F49C
+
+#define mmNIC0_QPC1_LAST_QP_TIMED_OUT 0x543F4A0
+
+#define mmNIC0_QPC1_WTD_SLICE_FSM_HI 0x543F4A4
+
+#define mmNIC0_QPC1_INTERRUPT_BASE_0 0x543F4B0
+
+#define mmNIC0_QPC1_INTERRUPT_BASE_1 0x543F4B4
+
+#define mmNIC0_QPC1_INTERRUPT_BASE_2 0x543F4B8
+
+#define mmNIC0_QPC1_INTERRUPT_BASE_3 0x543F4BC
+
+#define mmNIC0_QPC1_INTERRUPT_BASE_4 0x543F4C0
+
+#define mmNIC0_QPC1_INTERRUPT_BASE_5 0x543F4C4
+
+#define mmNIC0_QPC1_INTERRUPT_BASE_6 0x543F4C8
+
+#define mmNIC0_QPC1_INTERRUPT_BASE_7 0x543F4CC
+
+#define mmNIC0_QPC1_INTERRUPT_BASE_8 0x543F4D0
+
+#define mmNIC0_QPC1_INTERRUPT_BASE_9 0x543F4D4
+
+#define mmNIC0_QPC1_INTERRUPT_BASE_10 0x543F4D8
+
+#define mmNIC0_QPC1_INTERRUPT_DATA_0 0x543F4DC
+
+#define mmNIC0_QPC1_INTERRUPT_DATA_1 0x543F4E0
+
+#define mmNIC0_QPC1_INTERRUPT_DATA_2 0x543F4E4
+
+#define mmNIC0_QPC1_INTERRUPT_DATA_3 0x543F4E8
+
+#define mmNIC0_QPC1_INTERRUPT_DATA_4 0x543F4EC
+
+#define mmNIC0_QPC1_INTERRUPT_DATA_5 0x543F4F0
+
+#define mmNIC0_QPC1_INTERRUPT_DATA_6 0x543F4F4
+
+#define mmNIC0_QPC1_INTERRUPT_DATA_7 0x543F4F8
+
+#define mmNIC0_QPC1_INTERRUPT_DATA_8 0x543F4FC
+
+#define mmNIC0_QPC1_INTERRUPT_DATA_9 0x543F500
+
+#define mmNIC0_QPC1_INTERRUPT_DATA_10 0x543F504
+
+#define mmNIC0_QPC1_DBG_COUNT_SELECT_0 0x543F600
+
+#define mmNIC0_QPC1_DBG_COUNT_SELECT_1 0x543F604
+
+#define mmNIC0_QPC1_DBG_COUNT_SELECT_2 0x543F608
+
+#define mmNIC0_QPC1_DBG_COUNT_SELECT_3 0x543F60C
+
+#define mmNIC0_QPC1_DBG_COUNT_SELECT_4 0x543F610
+
+#define mmNIC0_QPC1_DBG_COUNT_SELECT_5 0x543F614
+
+#define mmNIC0_QPC1_DBG_COUNT_SELECT_6 0x543F618
+
+#define mmNIC0_QPC1_DBG_COUNT_SELECT_7 0x543F61C
+
+#define mmNIC0_QPC1_DBG_COUNT_SELECT_8 0x543F620
+
+#define mmNIC0_QPC1_DBG_COUNT_SELECT_9 0x543F624
+
+#define mmNIC0_QPC1_DBG_COUNT_SELECT_10 0x543F628
+
+#define mmNIC0_QPC1_DBG_COUNT_SELECT_11 0x543F62C
+
+#define mmNIC0_QPC1_DOORBELL_SECURITY 0x543F648
+
+#define mmNIC0_QPC1_DBG_CFG 0x543F64C
+
+#define mmNIC0_QPC1_RES_RING0_PI 0x543F650
+
+#define mmNIC0_QPC1_RES_RING0_CI 0x543F654
+
+#define mmNIC0_QPC1_RES_RING0_CFG 0x543F658
+
+#define mmNIC0_QPC1_RES_RING1_PI 0x543F65C
+
+#define mmNIC0_QPC1_RES_RING1_CI 0x543F660
+
+#define mmNIC0_QPC1_RES_RING1_CFG 0x543F664
+
+#define mmNIC0_QPC1_RES_RING2_PI 0x543F668
+
+#define mmNIC0_QPC1_RES_RING2_CI 0x543F66C
+
+#define mmNIC0_QPC1_RES_RING2_CFG 0x543F670
+
+#define mmNIC0_QPC1_RES_RING3_PI 0x543F674
+
+#define mmNIC0_QPC1_RES_RING3_CI 0x543F678
+
+#define mmNIC0_QPC1_RES_RING3_CFG 0x543F67C
+
+#define mmNIC0_QPC1_REQ_RING0_CI 0x543F680
+
+#define mmNIC0_QPC1_REQ_RING1_CI 0x543F684
+
+#define mmNIC0_QPC1_REQ_RING2_CI 0x543F688
+
+#define mmNIC0_QPC1_REQ_RING3_CI 0x543F68C
+
+#define mmNIC0_QPC1_INTERRUPT_CAUSE 0x543F690
+
+#define mmNIC0_QPC1_INTERRUPT_MASK 0x543F694
+
+#define mmNIC0_QPC1_INTERRUPT_CLR 0x543F698
+
+#define mmNIC0_QPC1_INTERRUPT_EN 0x543F69C
+
+#define mmNIC0_QPC1_INTERRUPT_CFG 0x543F6F0
+
+#define mmNIC0_QPC1_INTERRUPT_RESP_ERR_CAUSE 0x543F6F4
+
+#define mmNIC0_QPC1_INTERRUPT_RESP_ERR_MASK 0x543F6F8
+
+#define mmNIC0_QPC1_INTERRUPR_RESP_ERR_CLR 0x543F700
+
+#define mmNIC0_QPC1_TMR_GW_VALID 0x543F704
+
+#define mmNIC0_QPC1_TMR_GW_DATA0 0x543F708
+
+#define mmNIC0_QPC1_TMR_GW_DATA1 0x543F70C
+
+#define mmNIC0_QPC1_RNR_RETRY_COUNT_EN 0x543F710
+
+#define mmNIC0_QPC1_EVENT_QUE_BASE_ADDR_63_32 0x543F830
+
+#define mmNIC0_QPC1_EVENT_QUE_BASE_ADDR_31_7 0x543F834
+
+#define mmNIC0_QPC1_EVENT_QUE_LOG_SIZE 0x543F838
+
+#define mmNIC0_QPC1_EVENT_QUE_WRITE_INDEX 0x543F83C
+
+#define mmNIC0_QPC1_EVENT_QUE_PRODUCER_INDEX 0x543F840
+
+#define mmNIC0_QPC1_EVENT_QUE_PI_ADDR_63_32 0x543F844
+
+#define mmNIC0_QPC1_EVENT_QUE_PI_ADDR_31_7 0x543F848
+
+#define mmNIC0_QPC1_EVENT_QUE_CONSUMER_INDEX_CB 0x543F84C
+
+#define mmNIC0_QPC1_EVENT_QUE_CFG 0x543F850
+
+#define mmNIC0_QPC1_LBW_PROT 0x543F858
+
+#define mmNIC0_QPC1_MEM_WRITE_INIT 0x543F85C
+
+#define mmNIC0_QPC1_QMAN_DOORBELL 0x543F8E8
+
+#define mmNIC0_QPC1_QMAN_DOORBELL_QPN 0x543F8EC
+
+#define mmNIC0_QPC1_SECURED_CQ_NUMBER 0x543F8F0
+
+#define mmNIC0_QPC1_SECURED_CQ_CONSUMER_INDEX 0x543F8F4
+
+#define mmNIC0_QPC1_PRIVILEGE_CQ_NUMBER 0x543F8F8
+
+#define mmNIC0_QPC1_PRIVILEGE_CQ_CONSUMER_INDEX 0x543F8FC
+
+#define mmNIC0_QPC1_TX_WQ_BASE_ADDR_63_32_0 0x543F900
+
+#define mmNIC0_QPC1_TX_WQ_BASE_ADDR_63_32_1 0x543F904
+
+#define mmNIC0_QPC1_TX_WQ_BASE_ADDR_63_32_2 0x543F908
+
+#define mmNIC0_QPC1_TX_WQ_BASE_ADDR_63_32_3 0x543F90C
+
+#define mmNIC0_QPC1_TX_WQ_BASE_ADDR_31_0_0 0x543F910
+
+#define mmNIC0_QPC1_TX_WQ_BASE_ADDR_31_0_1 0x543F914
+
+#define mmNIC0_QPC1_TX_WQ_BASE_ADDR_31_0_2 0x543F918
+
+#define mmNIC0_QPC1_TX_WQ_BASE_ADDR_31_0_3 0x543F91C
+
+#define mmNIC0_QPC1_LOG_MAX_TX_WQ_SIZE_0 0x543F920
+
+#define mmNIC0_QPC1_LOG_MAX_TX_WQ_SIZE_1 0x543F924
+
+#define mmNIC0_QPC1_LOG_MAX_TX_WQ_SIZE_2 0x543F928
+
+#define mmNIC0_QPC1_LOG_MAX_TX_WQ_SIZE_3 0x543F92C
+
+#define mmNIC0_QPC1_MMU_BYPASS_TX_WQ_0 0x543F930
+
+#define mmNIC0_QPC1_MMU_BYPASS_TX_WQ_1 0x543F934
+
+#define mmNIC0_QPC1_MMU_BYPASS_TX_WQ_2 0x543F938
+
+#define mmNIC0_QPC1_MMU_BYPASS_TX_WQ_3 0x543F93C
+
+#define mmNIC0_QPC1_RX_WQ_BASE_ADDR_63_32_0 0x543F940
+
+#define mmNIC0_QPC1_RX_WQ_BASE_ADDR_63_32_1 0x543F944
+
+#define mmNIC0_QPC1_RX_WQ_BASE_ADDR_63_32_2 0x543F948
+
+#define mmNIC0_QPC1_RX_WQ_BASE_ADDR_63_32_3 0x543F94C
+
+#define mmNIC0_QPC1_RX_WQ_BASE_ADDR_31_0_0 0x543F950
+
+#define mmNIC0_QPC1_RX_WQ_BASE_ADDR_31_0_1 0x543F954
+
+#define mmNIC0_QPC1_RX_WQ_BASE_ADDR_31_0_2 0x543F958
+
+#define mmNIC0_QPC1_RX_WQ_BASE_ADDR_31_0_3 0x543F95C
+
+#define mmNIC0_QPC1_LOG_MAX_RX_WQ_SIZE_0 0x543F960
+
+#define mmNIC0_QPC1_LOG_MAX_RX_WQ_SIZE_1 0x543F964
+
+#define mmNIC0_QPC1_LOG_MAX_RX_WQ_SIZE_2 0x543F968
+
+#define mmNIC0_QPC1_LOG_MAX_RX_WQ_SIZE_3 0x543F96C
+
+#define mmNIC0_QPC1_MMU_BYPASS_RX_WQ_0 0x543F970
+
+#define mmNIC0_QPC1_MMU_BYPASS_RX_WQ_1 0x543F974
+
+#define mmNIC0_QPC1_MMU_BYPASS_RX_WQ_2 0x543F978
+
+#define mmNIC0_QPC1_MMU_BYPASS_RX_WQ_3 0x543F97C
+
+#define mmNIC0_QPC1_WQE_MEM_WRITE_AXI_PROT 0x543F980
+
+#define mmNIC0_QPC1_WQ_UPPER_THRESHOLD 0x543F984
+
+#define mmNIC0_QPC1_WQ_LOWER_THRESHOLD 0x543F988
+
+#define mmNIC0_QPC1_WQ_BP_2ARC_ADDR 0x543F98C
+
+#define mmNIC0_QPC1_WQ_BP_2QMAN_ADDR 0x543F990
+
+#define mmNIC0_QPC1_WTD_CONFIG 0x543F994
+
+#define mmNIC0_QPC1_REQTX_ERR_FIFO_PUSH_63_32 0x543F998
+
+#define mmNIC0_QPC1_REQTX_ERR_FIFO_PUSH_31_0 0x543F99C
+
+#define mmNIC0_QPC1_REQTX_ERR_QP_STATE_63_32 0x543F9A0
+
+#define mmNIC0_QPC1_REQTX_ERR_QP_STATE_31_0 0x543F9A4
+
+#define mmNIC0_QPC1_EVENT_QUE_CONSUMER_INDEX 0x543F9A8
+
+#define mmNIC0_QPC1_ARM_CQ_NUM 0x543F9AC
+
+#define mmNIC0_QPC1_ARM_CQ_INDEX 0x543F9B0
+
+#define mmNIC0_QPC1_QPC_CLOCK_GATE 0x543F9B4
+
+#define mmNIC0_QPC1_QPC_CLOCK_GATE_DIS 0x543F9B8
+
+#define mmNIC0_QPC1_CONG_QUE_BASE_ADDR_63_32 0x543F9BC
+
+#define mmNIC0_QPC1_CONG_QUE_BASE_ADDR_31_7 0x543F9C0
+
+#define mmNIC0_QPC1_CONG_QUE_LOG_SIZE 0x543F9C4
+
+#define mmNIC0_QPC1_CONG_QUE_WRITE_INDEX 0x543F9C8
+
+#define mmNIC0_QPC1_CONG_QUE_PRODUCER_INDEX 0x543F9CC
+
+#define mmNIC0_QPC1_CONG_QUE_PI_ADDR_63_32 0x543F9D0
+
+#define mmNIC0_QPC1_CONG_QUE_PI_ADDR_31_7 0x543F9D4
+
+#define mmNIC0_QPC1_CONG_QUE_CONSUMER_INDEX_CB 0x543F9D8
+
+#define mmNIC0_QPC1_CONG_QUE_CFG 0x543F9DC
+
+#define mmNIC0_QPC1_CONG_QUE_CONSUMER_INDEX 0x543F9E0
+
+#define mmNIC0_QPC1_LINEAR_WQE_STATIC_0 0x543FA00
+
+#define mmNIC0_QPC1_LINEAR_WQE_STATIC_1 0x543FA04
+
+#define mmNIC0_QPC1_LINEAR_WQE_STATIC_2 0x543FA08
+
+#define mmNIC0_QPC1_LINEAR_WQE_STATIC_3 0x543FA0C
+
+#define mmNIC0_QPC1_LINEAR_WQE_STATIC_4 0x543FA10
+
+#define mmNIC0_QPC1_LINEAR_WQE_STATIC_5 0x543FA14
+
+#define mmNIC0_QPC1_LINEAR_WQE_STATIC_6 0x543FA18
+
+#define mmNIC0_QPC1_LINEAR_WQE_STATIC_7 0x543FA1C
+
+#define mmNIC0_QPC1_LINEAR_WQE_STATIC_8 0x543FA20
+
+#define mmNIC0_QPC1_LINEAR_WQE_STATIC_9 0x543FA24
+
+#define mmNIC0_QPC1_LINEAR_WQE_DYNAMIC_0 0x543FA40
+
+#define mmNIC0_QPC1_LINEAR_WQE_DYNAMIC_1 0x543FA44
+
+#define mmNIC0_QPC1_LINEAR_WQE_DYNAMIC_2 0x543FA48
+
+#define mmNIC0_QPC1_LINEAR_WQE_DYNAMIC_3 0x543FA4C
+
+#define mmNIC0_QPC1_LINEAR_WQE_DYNAMIC_4 0x543FA50
+
+#define mmNIC0_QPC1_LINEAR_WQE_DYNAMIC_5 0x543FA54
+
+#define mmNIC0_QPC1_LINEAR_WQE_QPN 0x543FA58
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_0 0x543FA80
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_1 0x543FA84
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_2 0x543FA88
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_3 0x543FA8C
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_4 0x543FA90
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_5 0x543FA94
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_6 0x543FA98
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_7 0x543FA9C
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_8 0x543FAA0
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_9 0x543FAA4
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_10 0x543FAA8
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_11 0x543FAAC
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_12 0x543FAB0
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_13 0x543FAB4
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_14 0x543FAB8
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_15 0x543FABC
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_16 0x543FAC0
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_STATIC_17 0x543FAC4
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_DYNAMIC_0 0x543FAE0
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_DYNAMIC_1 0x543FAE4
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_DYNAMIC_2 0x543FAE8
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_DYNAMIC_3 0x543FAEC
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_DYNAMIC_4 0x543FAF0
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_DYNAMIC_5 0x543FAF4
+
+#define mmNIC0_QPC1_MULTI_STRIDE_WQE_QPN 0x543FAF8
+
+#endif /* ASIC_REG_NIC0_QPC1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_rxe0_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_rxe0_regs.h
new file mode 100644
index 000000000000..054414222ae1
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_rxe0_regs.h
@@ -0,0 +1,725 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_RXE0_REGS_H_
+#define ASIC_REG_NIC0_RXE0_REGS_H_
+
+/*
+ *****************************************
+ * NIC0_RXE0
+ * (Prototype: NIC_RXE)
+ *****************************************
+ */
+
+#define mmNIC0_RXE0_CONTROL 0x544A000
+
+#define mmNIC0_RXE0_SCATTER_CFG 0x544A004
+
+#define mmNIC0_RXE0_SCATTER_CQ_ADDR 0x544A008
+
+#define mmNIC0_RXE0_RAW_QPN_P0_0 0x544A010
+
+#define mmNIC0_RXE0_RAW_QPN_P0_1 0x544A014
+
+#define mmNIC0_RXE0_RAW_QPN_P1_0 0x544A018
+
+#define mmNIC0_RXE0_RAW_QPN_P1_1 0x544A01C
+
+#define mmNIC0_RXE0_RAW_QPN_P2_0 0x544A020
+
+#define mmNIC0_RXE0_RAW_QPN_P2_1 0x544A024
+
+#define mmNIC0_RXE0_RAW_QPN_P3_0 0x544A028
+
+#define mmNIC0_RXE0_RAW_QPN_P3_1 0x544A02C
+
+#define mmNIC0_RXE0_RXE_CHECKS 0x544A030
+
+#define mmNIC0_RXE0_PKT_DROP 0x544A034
+
+#define mmNIC0_RXE0_PKT_SIZE_CHECK_RC 0x544A038
+
+#define mmNIC0_RXE0_PKT_SIZE_CHECK_RAW 0x544A03C
+
+#define mmNIC0_RXE0_ARUSER_MMU_BP 0x544A064
+
+#define mmNIC0_RXE0_AWUSER_LBW 0x544A068
+
+#define mmNIC0_RXE0_ARPROT_HBW 0x544A070
+
+#define mmNIC0_RXE0_AWPROT_LBW 0x544A074
+
+#define mmNIC0_RXE0_WIN0_WQ_BASE_LO 0x544A080
+
+#define mmNIC0_RXE0_WIN0_WQ_BASE_HI 0x544A084
+
+#define mmNIC0_RXE0_WIN0_WQ_MISC 0x544A088
+
+#define mmNIC0_RXE0_WIN1_WQ_BASE_LO 0x544A090
+
+#define mmNIC0_RXE0_WIN1_WQ_BASE_HI 0x544A094
+
+#define mmNIC0_RXE0_WIN1_WQ_MISC 0x544A098
+
+#define mmNIC0_RXE0_WIN2_WQ_BASE_LO 0x544A0A0
+
+#define mmNIC0_RXE0_WIN2_WQ_BASE_HI 0x544A0A4
+
+#define mmNIC0_RXE0_WIN2_WQ_MISC 0x544A0A8
+
+#define mmNIC0_RXE0_WIN3_WQ_BASE_LO 0x544A0B0
+
+#define mmNIC0_RXE0_WIN3_WQ_BASE_HI 0x544A0B4
+
+#define mmNIC0_RXE0_WIN3_WQ_MISC 0x544A0B8
+
+#define mmNIC0_RXE0_CG 0x544A0D0
+
+#define mmNIC0_RXE0_CG_TIMER 0x544A0D4
+
+#define mmNIC0_RXE0_WQE_WQ_WR_OP_DISABLE 0x544A0D8
+
+#define mmNIC0_RXE0_WQE_WQ_RDV_OP_DISABLE 0x544A0DC
+
+#define mmNIC0_RXE0_WQE_WQ_RD_OP_DISABLE 0x544A0E0
+
+#define mmNIC0_RXE0_WQE_MAX_WRITE_SEND_SIZE 0x544A0E4
+
+#define mmNIC0_RXE0_WQE_MAX_MULTI_STRIDE_SIZE 0x544A0E8
+
+#define mmNIC0_RXE0_CACHE_CFG 0x544A0F0
+
+#define mmNIC0_RXE0_CACHE_INFO 0x544A0F4
+
+#define mmNIC0_RXE0_CACHE_ADDR_LO 0x544A0F8
+
+#define mmNIC0_RXE0_CACHE_ADDR_HI 0x544A0FC
+
+#define mmNIC0_RXE0_CQ_BASE_ADDR_31_7 0x544A100
+
+#define mmNIC0_RXE0_CQ_BASE_ADDR_63_32 0x544A104
+
+#define mmNIC0_RXE0_CQ_LOG_MAX_SIZE 0x544A108
+
+#define mmNIC0_RXE0_CQ_ARM_TIMEOUT_EN 0x544A110
+
+#define mmNIC0_RXE0_CQ_ARM_TIMEOUT 0x544A114
+
+#define mmNIC0_RXE0_CQ_CFG_0 0x544A180
+
+#define mmNIC0_RXE0_CQ_CFG_1 0x544A184
+
+#define mmNIC0_RXE0_CQ_CFG_2 0x544A188
+
+#define mmNIC0_RXE0_CQ_CFG_3 0x544A18C
+
+#define mmNIC0_RXE0_CQ_CFG_4 0x544A190
+
+#define mmNIC0_RXE0_CQ_CFG_5 0x544A194
+
+#define mmNIC0_RXE0_CQ_CFG_6 0x544A198
+
+#define mmNIC0_RXE0_CQ_CFG_7 0x544A19C
+
+#define mmNIC0_RXE0_CQ_CFG_8 0x544A1A0
+
+#define mmNIC0_RXE0_CQ_CFG_9 0x544A1A4
+
+#define mmNIC0_RXE0_CQ_CFG_10 0x544A1A8
+
+#define mmNIC0_RXE0_CQ_CFG_11 0x544A1AC
+
+#define mmNIC0_RXE0_CQ_CFG_12 0x544A1B0
+
+#define mmNIC0_RXE0_CQ_CFG_13 0x544A1B4
+
+#define mmNIC0_RXE0_CQ_CFG_14 0x544A1B8
+
+#define mmNIC0_RXE0_CQ_CFG_15 0x544A1BC
+
+#define mmNIC0_RXE0_CQ_CFG_16 0x544A1C0
+
+#define mmNIC0_RXE0_CQ_CFG_17 0x544A1C4
+
+#define mmNIC0_RXE0_CQ_CFG_18 0x544A1C8
+
+#define mmNIC0_RXE0_CQ_CFG_19 0x544A1CC
+
+#define mmNIC0_RXE0_CQ_CFG_20 0x544A1D0
+
+#define mmNIC0_RXE0_CQ_CFG_21 0x544A1D4
+
+#define mmNIC0_RXE0_CQ_CFG_22 0x544A1D8
+
+#define mmNIC0_RXE0_CQ_CFG_23 0x544A1DC
+
+#define mmNIC0_RXE0_CQ_CFG_24 0x544A1E0
+
+#define mmNIC0_RXE0_CQ_CFG_25 0x544A1E4
+
+#define mmNIC0_RXE0_CQ_CFG_26 0x544A1E8
+
+#define mmNIC0_RXE0_CQ_CFG_27 0x544A1EC
+
+#define mmNIC0_RXE0_CQ_CFG_28 0x544A1F0
+
+#define mmNIC0_RXE0_CQ_CFG_29 0x544A1F4
+
+#define mmNIC0_RXE0_CQ_CFG_30 0x544A1F8
+
+#define mmNIC0_RXE0_CQ_CFG_31 0x544A1FC
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_0 0x544A200
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_1 0x544A204
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_2 0x544A208
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_3 0x544A20C
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_4 0x544A210
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_5 0x544A214
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_6 0x544A218
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_7 0x544A21C
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_8 0x544A220
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_9 0x544A224
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_10 0x544A228
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_11 0x544A22C
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_12 0x544A230
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_13 0x544A234
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_14 0x544A238
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_15 0x544A23C
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_16 0x544A240
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_17 0x544A244
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_18 0x544A248
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_19 0x544A24C
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_20 0x544A250
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_21 0x544A254
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_22 0x544A258
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_23 0x544A25C
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_24 0x544A260
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_25 0x544A264
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_26 0x544A268
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_27 0x544A26C
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_28 0x544A270
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_29 0x544A274
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_30 0x544A278
+
+#define mmNIC0_RXE0_CQ_WRITE_INDEX_31 0x544A27C
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_0 0x544A280
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_1 0x544A284
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_2 0x544A288
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_3 0x544A28C
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_4 0x544A290
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_5 0x544A294
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_6 0x544A298
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_7 0x544A29C
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_8 0x544A2A0
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_9 0x544A2A4
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_10 0x544A2A8
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_11 0x544A2AC
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_12 0x544A2B0
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_13 0x544A2B4
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_14 0x544A2B8
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_15 0x544A2BC
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_16 0x544A2C0
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_17 0x544A2C4
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_18 0x544A2C8
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_19 0x544A2CC
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_20 0x544A2D0
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_21 0x544A2D4
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_22 0x544A2D8
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_23 0x544A2DC
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_24 0x544A2E0
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_25 0x544A2E4
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_26 0x544A2E8
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_27 0x544A2EC
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_28 0x544A2F0
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_29 0x544A2F4
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_30 0x544A2F8
+
+#define mmNIC0_RXE0_CQ_PRODUCER_INDEX_31 0x544A2FC
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_0 0x544A300
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_1 0x544A304
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_2 0x544A308
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_3 0x544A30C
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_4 0x544A310
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_5 0x544A314
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_6 0x544A318
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_7 0x544A31C
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_8 0x544A320
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_9 0x544A324
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_10 0x544A328
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_11 0x544A32C
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_12 0x544A330
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_13 0x544A334
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_14 0x544A338
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_15 0x544A33C
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_16 0x544A340
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_17 0x544A344
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_18 0x544A348
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_19 0x544A34C
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_20 0x544A350
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_21 0x544A354
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_22 0x544A358
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_23 0x544A35C
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_24 0x544A360
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_25 0x544A364
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_26 0x544A368
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_27 0x544A36C
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_28 0x544A370
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_29 0x544A374
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_30 0x544A378
+
+#define mmNIC0_RXE0_CQ_CONSUMER_INDEX_31 0x544A37C
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_0 0x544A380
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_1 0x544A384
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_2 0x544A388
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_3 0x544A38C
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_4 0x544A390
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_5 0x544A394
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_6 0x544A398
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_7 0x544A39C
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_8 0x544A3A0
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_9 0x544A3A4
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_10 0x544A3A8
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_11 0x544A3AC
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_12 0x544A3B0
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_13 0x544A3B4
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_14 0x544A3B8
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_15 0x544A3BC
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_16 0x544A3C0
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_17 0x544A3C4
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_18 0x544A3C8
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_19 0x544A3CC
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_20 0x544A3D0
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_21 0x544A3D4
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_22 0x544A3D8
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_23 0x544A3DC
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_24 0x544A3E0
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_25 0x544A3E4
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_26 0x544A3E8
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_27 0x544A3EC
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_28 0x544A3F0
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_29 0x544A3F4
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_30 0x544A3F8
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_LO_31 0x544A3FC
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_0 0x544A400
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_1 0x544A404
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_2 0x544A408
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_3 0x544A40C
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_4 0x544A410
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_5 0x544A414
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_6 0x544A418
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_7 0x544A41C
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_8 0x544A420
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_9 0x544A424
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_10 0x544A428
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_11 0x544A42C
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_12 0x544A430
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_13 0x544A434
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_14 0x544A438
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_15 0x544A43C
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_16 0x544A440
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_17 0x544A444
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_18 0x544A448
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_19 0x544A44C
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_20 0x544A450
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_21 0x544A454
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_22 0x544A458
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_23 0x544A45C
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_24 0x544A460
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_25 0x544A464
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_26 0x544A468
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_27 0x544A46C
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_28 0x544A470
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_29 0x544A474
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_30 0x544A478
+
+#define mmNIC0_RXE0_CQ_PI_ADDR_HI_31 0x544A47C
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_0 0x544A480
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_1 0x544A484
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_2 0x544A488
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_3 0x544A48C
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_4 0x544A490
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_5 0x544A494
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_6 0x544A498
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_7 0x544A49C
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_8 0x544A4A0
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_9 0x544A4A4
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_10 0x544A4A8
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_11 0x544A4AC
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_12 0x544A4B0
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_13 0x544A4B4
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_14 0x544A4B8
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_15 0x544A4BC
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_16 0x544A4C0
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_17 0x544A4C4
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_18 0x544A4C8
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_19 0x544A4CC
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_20 0x544A4D0
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_21 0x544A4D4
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_22 0x544A4D8
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_23 0x544A4DC
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_24 0x544A4E0
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_25 0x544A4E4
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_26 0x544A4E8
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_27 0x544A4EC
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_28 0x544A4F0
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_29 0x544A4F4
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_30 0x544A4F8
+
+#define mmNIC0_RXE0_CQ_AXI_PROT_31 0x544A4FC
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_0 0x544A500
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_1 0x544A504
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_2 0x544A508
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_3 0x544A50C
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_4 0x544A510
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_5 0x544A514
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_6 0x544A518
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_7 0x544A51C
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_8 0x544A520
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_9 0x544A524
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_10 0x544A528
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_11 0x544A52C
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_12 0x544A530
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_13 0x544A534
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_14 0x544A538
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_15 0x544A53C
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_16 0x544A540
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_17 0x544A544
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_18 0x544A548
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_19 0x544A54C
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_20 0x544A550
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_21 0x544A554
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_22 0x544A558
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_23 0x544A55C
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_24 0x544A560
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_25 0x544A564
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_26 0x544A568
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_27 0x544A56C
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_28 0x544A570
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_29 0x544A574
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_30 0x544A578
+
+#define mmNIC0_RXE0_CQ_LOG_SIZE_31 0x544A57C
+
+#define mmNIC0_RXE0_RDV_SEND_WQ_BASE_ADDR_LO 0x544A600
+
+#define mmNIC0_RXE0_RDV_SEND_WQ_BASE_ADDR_HI 0x544A604
+
+#define mmNIC0_RXE0_RDV_LOG_MAX_WQ_SIZE 0x544A608
+
+#define mmNIC0_RXE0_LBW_BASE_LO 0x544A700
+
+#define mmNIC0_RXE0_LBW_BASE_HI 0x544A704
+
+#define mmNIC0_RXE0_LBW_LOG_SIZE 0x544A708
+
+#define mmNIC0_RXE0_RAW_BASE_LO_P0_0 0x544A710
+
+#define mmNIC0_RXE0_RAW_BASE_LO_P0_1 0x544A714
+
+#define mmNIC0_RXE0_RAW_BASE_HI_P0_0 0x544A720
+
+#define mmNIC0_RXE0_RAW_BASE_HI_P0_1 0x544A724
+
+#define mmNIC0_RXE0_RAW_MISC_P0_0 0x544A730
+
+#define mmNIC0_RXE0_RAW_MISC_P0_1 0x544A734
+
+#define mmNIC0_RXE0_RAW_BASE_LO_P1_0 0x544A750
+
+#define mmNIC0_RXE0_RAW_BASE_LO_P1_1 0x544A754
+
+#define mmNIC0_RXE0_RAW_BASE_HI_P1_0 0x544A760
+
+#define mmNIC0_RXE0_RAW_BASE_HI_P1_1 0x544A764
+
+#define mmNIC0_RXE0_RAW_MISC_P1_0 0x544A770
+
+#define mmNIC0_RXE0_RAW_MISC_P1_1 0x544A774
+
+#define mmNIC0_RXE0_RAW_BASE_LO_P2_0 0x544A790
+
+#define mmNIC0_RXE0_RAW_BASE_LO_P2_1 0x544A794
+
+#define mmNIC0_RXE0_RAW_BASE_HI_P2_0 0x544A7A0
+
+#define mmNIC0_RXE0_RAW_BASE_HI_P2_1 0x544A7A4
+
+#define mmNIC0_RXE0_RAW_MISC_P2_0 0x544A7B0
+
+#define mmNIC0_RXE0_RAW_MISC_P2_1 0x544A7B4
+
+#define mmNIC0_RXE0_RAW_BASE_LO_P3_0 0x544A7D0
+
+#define mmNIC0_RXE0_RAW_BASE_LO_P3_1 0x544A7D4
+
+#define mmNIC0_RXE0_RAW_BASE_HI_P3_0 0x544A7E0
+
+#define mmNIC0_RXE0_RAW_BASE_HI_P3_1 0x544A7E4
+
+#define mmNIC0_RXE0_RAW_MISC_P3_0 0x544A7F0
+
+#define mmNIC0_RXE0_RAW_MISC_P3_1 0x544A7F4
+
+#define mmNIC0_RXE0_SEI_INTR_CAUSE 0x544A800
+
+#define mmNIC0_RXE0_SEI_INTR_MASK 0x544A804
+
+#define mmNIC0_RXE0_SEI_INTR_CLEAR 0x544A808
+
+#define mmNIC0_RXE0_SPI_INTR_CAUSE 0x544A810
+
+#define mmNIC0_RXE0_SPI_INTR_MASK 0x544A814
+
+#define mmNIC0_RXE0_SPI_INTR_CLEAR 0x544A818
+
+#define mmNIC0_RXE0_DBG_SPMU_SELECT 0x544AA00
+
+#define mmNIC0_RXE0_DBG_INV_OP_0 0x544AA04
+
+#define mmNIC0_RXE0_DBG_INV_OP_1 0x544AA08
+
+#define mmNIC0_RXE0_DBG_AXI_ERR 0x544AA0C
+
+#define mmNIC0_RXE0_DBG_AXI_CQE_ERR 0x544AA10
+
+#define mmNIC0_RXE0_DBG_AXI_LBW_ERR 0x544AA14
+
+#define mmNIC0_RXE0_DBG_EN 0x544AA18
+
+#define mmNIC0_RXE0_DBG_CQ_ARM_ON 0x544AA1C
+
+#define mmNIC0_RXE0_DBG_CQ_ARM_SEL 0x544AA20
+
+#define mmNIC0_RXE0_DBG_CQ_ARM_IDX 0x544AA24
+
+#define mmNIC0_RXE0_DBG_SLICE_MAIN 0x544AA28
+
+#define mmNIC0_RXE0_DBG_SLICE_SCT 0x544AA2C
+
+#endif /* ASIC_REG_NIC0_RXE0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_rxe1_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_rxe1_regs.h
new file mode 100644
index 000000000000..9cc3fbd5ec51
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_rxe1_regs.h
@@ -0,0 +1,725 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_RXE1_REGS_H_
+#define ASIC_REG_NIC0_RXE1_REGS_H_
+
+/*
+ *****************************************
+ * NIC0_RXE1
+ * (Prototype: NIC_RXE)
+ *****************************************
+ */
+
+#define mmNIC0_RXE1_CONTROL 0x544B000
+
+#define mmNIC0_RXE1_SCATTER_CFG 0x544B004
+
+#define mmNIC0_RXE1_SCATTER_CQ_ADDR 0x544B008
+
+#define mmNIC0_RXE1_RAW_QPN_P0_0 0x544B010
+
+#define mmNIC0_RXE1_RAW_QPN_P0_1 0x544B014
+
+#define mmNIC0_RXE1_RAW_QPN_P1_0 0x544B018
+
+#define mmNIC0_RXE1_RAW_QPN_P1_1 0x544B01C
+
+#define mmNIC0_RXE1_RAW_QPN_P2_0 0x544B020
+
+#define mmNIC0_RXE1_RAW_QPN_P2_1 0x544B024
+
+#define mmNIC0_RXE1_RAW_QPN_P3_0 0x544B028
+
+#define mmNIC0_RXE1_RAW_QPN_P3_1 0x544B02C
+
+#define mmNIC0_RXE1_RXE_CHECKS 0x544B030
+
+#define mmNIC0_RXE1_PKT_DROP 0x544B034
+
+#define mmNIC0_RXE1_PKT_SIZE_CHECK_RC 0x544B038
+
+#define mmNIC0_RXE1_PKT_SIZE_CHECK_RAW 0x544B03C
+
+#define mmNIC0_RXE1_ARUSER_MMU_BP 0x544B064
+
+#define mmNIC0_RXE1_AWUSER_LBW 0x544B068
+
+#define mmNIC0_RXE1_ARPROT_HBW 0x544B070
+
+#define mmNIC0_RXE1_AWPROT_LBW 0x544B074
+
+#define mmNIC0_RXE1_WIN0_WQ_BASE_LO 0x544B080
+
+#define mmNIC0_RXE1_WIN0_WQ_BASE_HI 0x544B084
+
+#define mmNIC0_RXE1_WIN0_WQ_MISC 0x544B088
+
+#define mmNIC0_RXE1_WIN1_WQ_BASE_LO 0x544B090
+
+#define mmNIC0_RXE1_WIN1_WQ_BASE_HI 0x544B094
+
+#define mmNIC0_RXE1_WIN1_WQ_MISC 0x544B098
+
+#define mmNIC0_RXE1_WIN2_WQ_BASE_LO 0x544B0A0
+
+#define mmNIC0_RXE1_WIN2_WQ_BASE_HI 0x544B0A4
+
+#define mmNIC0_RXE1_WIN2_WQ_MISC 0x544B0A8
+
+#define mmNIC0_RXE1_WIN3_WQ_BASE_LO 0x544B0B0
+
+#define mmNIC0_RXE1_WIN3_WQ_BASE_HI 0x544B0B4
+
+#define mmNIC0_RXE1_WIN3_WQ_MISC 0x544B0B8
+
+#define mmNIC0_RXE1_CG 0x544B0D0
+
+#define mmNIC0_RXE1_CG_TIMER 0x544B0D4
+
+#define mmNIC0_RXE1_WQE_WQ_WR_OP_DISABLE 0x544B0D8
+
+#define mmNIC0_RXE1_WQE_WQ_RDV_OP_DISABLE 0x544B0DC
+
+#define mmNIC0_RXE1_WQE_WQ_RD_OP_DISABLE 0x544B0E0
+
+#define mmNIC0_RXE1_WQE_MAX_WRITE_SEND_SIZE 0x544B0E4
+
+#define mmNIC0_RXE1_WQE_MAX_MULTI_STRIDE_SIZE 0x544B0E8
+
+#define mmNIC0_RXE1_CACHE_CFG 0x544B0F0
+
+#define mmNIC0_RXE1_CACHE_INFO 0x544B0F4
+
+#define mmNIC0_RXE1_CACHE_ADDR_LO 0x544B0F8
+
+#define mmNIC0_RXE1_CACHE_ADDR_HI 0x544B0FC
+
+#define mmNIC0_RXE1_CQ_BASE_ADDR_31_7 0x544B100
+
+#define mmNIC0_RXE1_CQ_BASE_ADDR_63_32 0x544B104
+
+#define mmNIC0_RXE1_CQ_LOG_MAX_SIZE 0x544B108
+
+#define mmNIC0_RXE1_CQ_ARM_TIMEOUT_EN 0x544B110
+
+#define mmNIC0_RXE1_CQ_ARM_TIMEOUT 0x544B114
+
+#define mmNIC0_RXE1_CQ_CFG_0 0x544B180
+
+#define mmNIC0_RXE1_CQ_CFG_1 0x544B184
+
+#define mmNIC0_RXE1_CQ_CFG_2 0x544B188
+
+#define mmNIC0_RXE1_CQ_CFG_3 0x544B18C
+
+#define mmNIC0_RXE1_CQ_CFG_4 0x544B190
+
+#define mmNIC0_RXE1_CQ_CFG_5 0x544B194
+
+#define mmNIC0_RXE1_CQ_CFG_6 0x544B198
+
+#define mmNIC0_RXE1_CQ_CFG_7 0x544B19C
+
+#define mmNIC0_RXE1_CQ_CFG_8 0x544B1A0
+
+#define mmNIC0_RXE1_CQ_CFG_9 0x544B1A4
+
+#define mmNIC0_RXE1_CQ_CFG_10 0x544B1A8
+
+#define mmNIC0_RXE1_CQ_CFG_11 0x544B1AC
+
+#define mmNIC0_RXE1_CQ_CFG_12 0x544B1B0
+
+#define mmNIC0_RXE1_CQ_CFG_13 0x544B1B4
+
+#define mmNIC0_RXE1_CQ_CFG_14 0x544B1B8
+
+#define mmNIC0_RXE1_CQ_CFG_15 0x544B1BC
+
+#define mmNIC0_RXE1_CQ_CFG_16 0x544B1C0
+
+#define mmNIC0_RXE1_CQ_CFG_17 0x544B1C4
+
+#define mmNIC0_RXE1_CQ_CFG_18 0x544B1C8
+
+#define mmNIC0_RXE1_CQ_CFG_19 0x544B1CC
+
+#define mmNIC0_RXE1_CQ_CFG_20 0x544B1D0
+
+#define mmNIC0_RXE1_CQ_CFG_21 0x544B1D4
+
+#define mmNIC0_RXE1_CQ_CFG_22 0x544B1D8
+
+#define mmNIC0_RXE1_CQ_CFG_23 0x544B1DC
+
+#define mmNIC0_RXE1_CQ_CFG_24 0x544B1E0
+
+#define mmNIC0_RXE1_CQ_CFG_25 0x544B1E4
+
+#define mmNIC0_RXE1_CQ_CFG_26 0x544B1E8
+
+#define mmNIC0_RXE1_CQ_CFG_27 0x544B1EC
+
+#define mmNIC0_RXE1_CQ_CFG_28 0x544B1F0
+
+#define mmNIC0_RXE1_CQ_CFG_29 0x544B1F4
+
+#define mmNIC0_RXE1_CQ_CFG_30 0x544B1F8
+
+#define mmNIC0_RXE1_CQ_CFG_31 0x544B1FC
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_0 0x544B200
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_1 0x544B204
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_2 0x544B208
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_3 0x544B20C
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_4 0x544B210
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_5 0x544B214
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_6 0x544B218
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_7 0x544B21C
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_8 0x544B220
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_9 0x544B224
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_10 0x544B228
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_11 0x544B22C
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_12 0x544B230
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_13 0x544B234
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_14 0x544B238
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_15 0x544B23C
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_16 0x544B240
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_17 0x544B244
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_18 0x544B248
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_19 0x544B24C
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_20 0x544B250
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_21 0x544B254
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_22 0x544B258
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_23 0x544B25C
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_24 0x544B260
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_25 0x544B264
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_26 0x544B268
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_27 0x544B26C
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_28 0x544B270
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_29 0x544B274
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_30 0x544B278
+
+#define mmNIC0_RXE1_CQ_WRITE_INDEX_31 0x544B27C
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_0 0x544B280
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_1 0x544B284
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_2 0x544B288
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_3 0x544B28C
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_4 0x544B290
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_5 0x544B294
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_6 0x544B298
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_7 0x544B29C
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_8 0x544B2A0
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_9 0x544B2A4
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_10 0x544B2A8
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_11 0x544B2AC
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_12 0x544B2B0
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_13 0x544B2B4
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_14 0x544B2B8
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_15 0x544B2BC
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_16 0x544B2C0
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_17 0x544B2C4
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_18 0x544B2C8
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_19 0x544B2CC
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_20 0x544B2D0
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_21 0x544B2D4
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_22 0x544B2D8
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_23 0x544B2DC
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_24 0x544B2E0
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_25 0x544B2E4
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_26 0x544B2E8
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_27 0x544B2EC
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_28 0x544B2F0
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_29 0x544B2F4
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_30 0x544B2F8
+
+#define mmNIC0_RXE1_CQ_PRODUCER_INDEX_31 0x544B2FC
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_0 0x544B300
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_1 0x544B304
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_2 0x544B308
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_3 0x544B30C
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_4 0x544B310
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_5 0x544B314
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_6 0x544B318
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_7 0x544B31C
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_8 0x544B320
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_9 0x544B324
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_10 0x544B328
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_11 0x544B32C
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_12 0x544B330
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_13 0x544B334
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_14 0x544B338
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_15 0x544B33C
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_16 0x544B340
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_17 0x544B344
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_18 0x544B348
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_19 0x544B34C
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_20 0x544B350
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_21 0x544B354
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_22 0x544B358
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_23 0x544B35C
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_24 0x544B360
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_25 0x544B364
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_26 0x544B368
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_27 0x544B36C
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_28 0x544B370
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_29 0x544B374
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_30 0x544B378
+
+#define mmNIC0_RXE1_CQ_CONSUMER_INDEX_31 0x544B37C
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_0 0x544B380
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_1 0x544B384
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_2 0x544B388
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_3 0x544B38C
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_4 0x544B390
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_5 0x544B394
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_6 0x544B398
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_7 0x544B39C
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_8 0x544B3A0
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_9 0x544B3A4
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_10 0x544B3A8
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_11 0x544B3AC
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_12 0x544B3B0
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_13 0x544B3B4
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_14 0x544B3B8
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_15 0x544B3BC
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_16 0x544B3C0
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_17 0x544B3C4
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_18 0x544B3C8
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_19 0x544B3CC
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_20 0x544B3D0
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_21 0x544B3D4
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_22 0x544B3D8
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_23 0x544B3DC
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_24 0x544B3E0
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_25 0x544B3E4
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_26 0x544B3E8
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_27 0x544B3EC
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_28 0x544B3F0
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_29 0x544B3F4
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_30 0x544B3F8
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_LO_31 0x544B3FC
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_0 0x544B400
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_1 0x544B404
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_2 0x544B408
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_3 0x544B40C
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_4 0x544B410
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_5 0x544B414
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_6 0x544B418
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_7 0x544B41C
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_8 0x544B420
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_9 0x544B424
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_10 0x544B428
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_11 0x544B42C
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_12 0x544B430
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_13 0x544B434
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_14 0x544B438
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_15 0x544B43C
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_16 0x544B440
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_17 0x544B444
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_18 0x544B448
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_19 0x544B44C
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_20 0x544B450
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_21 0x544B454
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_22 0x544B458
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_23 0x544B45C
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_24 0x544B460
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_25 0x544B464
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_26 0x544B468
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_27 0x544B46C
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_28 0x544B470
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_29 0x544B474
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_30 0x544B478
+
+#define mmNIC0_RXE1_CQ_PI_ADDR_HI_31 0x544B47C
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_0 0x544B480
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_1 0x544B484
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_2 0x544B488
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_3 0x544B48C
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_4 0x544B490
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_5 0x544B494
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_6 0x544B498
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_7 0x544B49C
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_8 0x544B4A0
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_9 0x544B4A4
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_10 0x544B4A8
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_11 0x544B4AC
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_12 0x544B4B0
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_13 0x544B4B4
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_14 0x544B4B8
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_15 0x544B4BC
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_16 0x544B4C0
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_17 0x544B4C4
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_18 0x544B4C8
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_19 0x544B4CC
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_20 0x544B4D0
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_21 0x544B4D4
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_22 0x544B4D8
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_23 0x544B4DC
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_24 0x544B4E0
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_25 0x544B4E4
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_26 0x544B4E8
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_27 0x544B4EC
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_28 0x544B4F0
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_29 0x544B4F4
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_30 0x544B4F8
+
+#define mmNIC0_RXE1_CQ_AXI_PROT_31 0x544B4FC
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_0 0x544B500
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_1 0x544B504
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_2 0x544B508
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_3 0x544B50C
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_4 0x544B510
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_5 0x544B514
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_6 0x544B518
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_7 0x544B51C
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_8 0x544B520
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_9 0x544B524
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_10 0x544B528
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_11 0x544B52C
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_12 0x544B530
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_13 0x544B534
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_14 0x544B538
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_15 0x544B53C
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_16 0x544B540
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_17 0x544B544
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_18 0x544B548
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_19 0x544B54C
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_20 0x544B550
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_21 0x544B554
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_22 0x544B558
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_23 0x544B55C
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_24 0x544B560
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_25 0x544B564
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_26 0x544B568
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_27 0x544B56C
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_28 0x544B570
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_29 0x544B574
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_30 0x544B578
+
+#define mmNIC0_RXE1_CQ_LOG_SIZE_31 0x544B57C
+
+#define mmNIC0_RXE1_RDV_SEND_WQ_BASE_ADDR_LO 0x544B600
+
+#define mmNIC0_RXE1_RDV_SEND_WQ_BASE_ADDR_HI 0x544B604
+
+#define mmNIC0_RXE1_RDV_LOG_MAX_WQ_SIZE 0x544B608
+
+#define mmNIC0_RXE1_LBW_BASE_LO 0x544B700
+
+#define mmNIC0_RXE1_LBW_BASE_HI 0x544B704
+
+#define mmNIC0_RXE1_LBW_LOG_SIZE 0x544B708
+
+#define mmNIC0_RXE1_RAW_BASE_LO_P0_0 0x544B710
+
+#define mmNIC0_RXE1_RAW_BASE_LO_P0_1 0x544B714
+
+#define mmNIC0_RXE1_RAW_BASE_HI_P0_0 0x544B720
+
+#define mmNIC0_RXE1_RAW_BASE_HI_P0_1 0x544B724
+
+#define mmNIC0_RXE1_RAW_MISC_P0_0 0x544B730
+
+#define mmNIC0_RXE1_RAW_MISC_P0_1 0x544B734
+
+#define mmNIC0_RXE1_RAW_BASE_LO_P1_0 0x544B750
+
+#define mmNIC0_RXE1_RAW_BASE_LO_P1_1 0x544B754
+
+#define mmNIC0_RXE1_RAW_BASE_HI_P1_0 0x544B760
+
+#define mmNIC0_RXE1_RAW_BASE_HI_P1_1 0x544B764
+
+#define mmNIC0_RXE1_RAW_MISC_P1_0 0x544B770
+
+#define mmNIC0_RXE1_RAW_MISC_P1_1 0x544B774
+
+#define mmNIC0_RXE1_RAW_BASE_LO_P2_0 0x544B790
+
+#define mmNIC0_RXE1_RAW_BASE_LO_P2_1 0x544B794
+
+#define mmNIC0_RXE1_RAW_BASE_HI_P2_0 0x544B7A0
+
+#define mmNIC0_RXE1_RAW_BASE_HI_P2_1 0x544B7A4
+
+#define mmNIC0_RXE1_RAW_MISC_P2_0 0x544B7B0
+
+#define mmNIC0_RXE1_RAW_MISC_P2_1 0x544B7B4
+
+#define mmNIC0_RXE1_RAW_BASE_LO_P3_0 0x544B7D0
+
+#define mmNIC0_RXE1_RAW_BASE_LO_P3_1 0x544B7D4
+
+#define mmNIC0_RXE1_RAW_BASE_HI_P3_0 0x544B7E0
+
+#define mmNIC0_RXE1_RAW_BASE_HI_P3_1 0x544B7E4
+
+#define mmNIC0_RXE1_RAW_MISC_P3_0 0x544B7F0
+
+#define mmNIC0_RXE1_RAW_MISC_P3_1 0x544B7F4
+
+#define mmNIC0_RXE1_SEI_INTR_CAUSE 0x544B800
+
+#define mmNIC0_RXE1_SEI_INTR_MASK 0x544B804
+
+#define mmNIC0_RXE1_SEI_INTR_CLEAR 0x544B808
+
+#define mmNIC0_RXE1_SPI_INTR_CAUSE 0x544B810
+
+#define mmNIC0_RXE1_SPI_INTR_MASK 0x544B814
+
+#define mmNIC0_RXE1_SPI_INTR_CLEAR 0x544B818
+
+#define mmNIC0_RXE1_DBG_SPMU_SELECT 0x544BA00
+
+#define mmNIC0_RXE1_DBG_INV_OP_0 0x544BA04
+
+#define mmNIC0_RXE1_DBG_INV_OP_1 0x544BA08
+
+#define mmNIC0_RXE1_DBG_AXI_ERR 0x544BA0C
+
+#define mmNIC0_RXE1_DBG_AXI_CQE_ERR 0x544BA10
+
+#define mmNIC0_RXE1_DBG_AXI_LBW_ERR 0x544BA14
+
+#define mmNIC0_RXE1_DBG_EN 0x544BA18
+
+#define mmNIC0_RXE1_DBG_CQ_ARM_ON 0x544BA1C
+
+#define mmNIC0_RXE1_DBG_CQ_ARM_SEL 0x544BA20
+
+#define mmNIC0_RXE1_DBG_CQ_ARM_IDX 0x544BA24
+
+#define mmNIC0_RXE1_DBG_SLICE_MAIN 0x544BA28
+
+#define mmNIC0_RXE1_DBG_SLICE_SCT 0x544BA2C
+
+#endif /* ASIC_REG_NIC0_RXE1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_txe0_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_txe0_regs.h
new file mode 100644
index 000000000000..0537d108ead9
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_txe0_regs.h
@@ -0,0 +1,529 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_TXE0_REGS_H_
+#define ASIC_REG_NIC0_TXE0_REGS_H_
+
+/*
+ *****************************************
+ * NIC0_TXE0
+ * (Prototype: NIC_TXE)
+ *****************************************
+ */
+
+#define mmNIC0_TXE0_WQE_FETCH_REQ_MASK_31_0 0x5452000
+
+#define mmNIC0_TXE0_WQE_FETCH_REQ_MASK_47_32 0x5452004
+
+#define mmNIC0_TXE0_LOCAL_WQ_BUFFER_SIZE 0x5452008
+
+#define mmNIC0_TXE0_LOCAL_WQ_LINE_SIZE 0x545200C
+
+#define mmNIC0_TXE0_LOG_MAX_WQ_SIZE_0 0x5452010
+
+#define mmNIC0_TXE0_LOG_MAX_WQ_SIZE_1 0x5452014
+
+#define mmNIC0_TXE0_LOG_MAX_WQ_SIZE_2 0x5452018
+
+#define mmNIC0_TXE0_LOG_MAX_WQ_SIZE_3 0x545201C
+
+#define mmNIC0_TXE0_SQ_BASE_ADDRESS_63_32_0 0x5452020
+
+#define mmNIC0_TXE0_SQ_BASE_ADDRESS_63_32_1 0x5452024
+
+#define mmNIC0_TXE0_SQ_BASE_ADDRESS_63_32_2 0x5452028
+
+#define mmNIC0_TXE0_SQ_BASE_ADDRESS_63_32_3 0x545202C
+
+#define mmNIC0_TXE0_SQ_BASE_ADDRESS_31_0_0 0x5452030
+
+#define mmNIC0_TXE0_SQ_BASE_ADDRESS_31_0_1 0x5452034
+
+#define mmNIC0_TXE0_SQ_BASE_ADDRESS_31_0_2 0x5452038
+
+#define mmNIC0_TXE0_SQ_BASE_ADDRESS_31_0_3 0x545203C
+
+#define mmNIC0_TXE0_WQE_USER_CFG 0x5452040
+
+#define mmNIC0_TXE0_ALLOC_CREDIT 0x5452044
+
+#define mmNIC0_TXE0_ALLOC_CREDIT_FORCE_FULL 0x5452048
+
+#define mmNIC0_TXE0_READ_CREDIT 0x545204C
+
+#define mmNIC0_TXE0_READ_CREDIT_FORCE_FULL 0x5452050
+
+#define mmNIC0_TXE0_BURST_ENABLE 0x5452054
+
+#define mmNIC0_TXE0_WR_INIT_BUSY 0x5452058
+
+#define mmNIC0_TXE0_READ_RES_WT_INIT_BUSY 0x545205C
+
+#define mmNIC0_TXE0_BTH_TVER 0x5452060
+
+#define mmNIC0_TXE0_IPV4_IDENTIFICATION 0x5452064
+
+#define mmNIC0_TXE0_IPV4_FLAGS 0x5452068
+
+#define mmNIC0_TXE0_PAD 0x545206C
+
+#define mmNIC0_TXE0_ADD_PAD_TO_IPV4_LEN 0x5452070
+
+#define mmNIC0_TXE0_ADD_PAD_TO_UDP_LEN 0x5452074
+
+#define mmNIC0_TXE0_ICRC_EN 0x5452078
+
+#define mmNIC0_TXE0_UDP_MASK_S_PORT 0x545207C
+
+#define mmNIC0_TXE0_UDP_CHECKSUM 0x5452080
+
+#define mmNIC0_TXE0_UDP_DEST_PORT 0x5452084
+
+#define mmNIC0_TXE0_PORT0_MAC_CFG_47_32 0x5452088
+
+#define mmNIC0_TXE0_PORT0_MAC_CFG_31_0 0x545208C
+
+#define mmNIC0_TXE0_PORT1_MAC_CFG_47_32 0x5452090
+
+#define mmNIC0_TXE0_PORT1_MAC_CFG_31_0 0x5452094
+
+#define mmNIC0_TXE0_PRIO_TO_DSCP_0 0x545209C
+
+#define mmNIC0_TXE0_PRIO_TO_DSCP_1 0x54520A0
+
+#define mmNIC0_TXE0_PRIO_TO_PCP 0x54520B0
+
+#define mmNIC0_TXE0_MAC_ETHER_TYPE 0x54520B4
+
+#define mmNIC0_TXE0_MAC_ETHER_TYPE_VLAN 0x54520B8
+
+#define mmNIC0_TXE0_ECN_0 0x54520BC
+
+#define mmNIC0_TXE0_ECN_1 0x54520C0
+
+#define mmNIC0_TXE0_IPV4_TIME_TO_LIVE_0 0x54520C4
+
+#define mmNIC0_TXE0_IPV4_TIME_TO_LIVE_1 0x54520C8
+
+#define mmNIC0_TXE0_PRIO_PORT_CREDIT_FORCE 0x54520CC
+
+#define mmNIC0_TXE0_PRIO_PORT_CRDIT_0 0x54520D0
+
+#define mmNIC0_TXE0_PRIO_PORT_CRDIT_1 0x54520D4
+
+#define mmNIC0_TXE0_PRIO_PORT_CRDIT_2 0x54520D8
+
+#define mmNIC0_TXE0_PRIO_PORT_CRDIT_3 0x54520DC
+
+#define mmNIC0_TXE0_PRIO_PORT_CRDIT_4 0x54520E0
+
+#define mmNIC0_TXE0_PRIO_PORT_CRDIT_5 0x54520E4
+
+#define mmNIC0_TXE0_PRIO_PORT_CRDIT_6 0x54520E8
+
+#define mmNIC0_TXE0_PRIO_PORT_CRDIT_7 0x54520EC
+
+#define mmNIC0_TXE0_WQE_FETCH_TOKEN_EN 0x54520F0
+
+#define mmNIC0_TXE0_NACK_SYNDROME 0x54520F4
+
+#define mmNIC0_TXE0_WQE_FETCH_AXI_PROT 0x54520FC
+
+#define mmNIC0_TXE0_DATA_FETCH_AXI_PROT 0x5452104
+
+#define mmNIC0_TXE0_FETCH_OUT_OF_TOKEN 0x5452108
+
+#define mmNIC0_TXE0_ECN_COUNT_EN 0x545210C
+
+#define mmNIC0_TXE0_INERRUPT_CAUSE 0x5452110
+
+#define mmNIC0_TXE0_INTERRUPT_MASK 0x5452114
+
+#define mmNIC0_TXE0_INTERRUPT_CLR 0x5452118
+
+#define mmNIC0_TXE0_VLAN_TAG_QPN_OFFSET 0x545211C
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_0 0x5452120
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_1 0x5452124
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_2 0x5452128
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_3 0x545212C
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_4 0x5452130
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_5 0x5452134
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_6 0x5452138
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_7 0x545213C
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_8 0x5452140
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_9 0x5452144
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_10 0x5452148
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_11 0x545214C
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_12 0x5452150
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_13 0x5452154
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_14 0x5452158
+
+#define mmNIC0_TXE0_VALN_TAG_CFG_15 0x545215C
+
+#define mmNIC0_TXE0_DBG_TRIG 0x5452160
+
+#define mmNIC0_TXE0_WQE_PREFETCH_CFG 0x5452164
+
+#define mmNIC0_TXE0_WQE_PREFETCH_INVALIDATE 0x5452168
+
+#define mmNIC0_TXE0_SWAP_MEMORY_ENDIANNESS 0x545216C
+
+#define mmNIC0_TXE0_WQE_FETCH_SLICE_47_32 0x5452170
+
+#define mmNIC0_TXE0_WQE_FETCH_SLICE_31_0 0x5452174
+
+#define mmNIC0_TXE0_WQE_EXE_SLICE_47_32 0x5452178
+
+#define mmNIC0_TXE0_WQE_EXE_SLICE_31_0 0x545217C
+
+#define mmNIC0_TXE0_DBG_COUNT_SELECT0 0x5452180
+
+#define mmNIC0_TXE0_DBG_COUNT_SELECT1 0x5452184
+
+#define mmNIC0_TXE0_DBG_COUNT_SELECT2 0x5452188
+
+#define mmNIC0_TXE0_DBG_COUNT_SELECT3 0x545218C
+
+#define mmNIC0_TXE0_DBG_COUNT_SELECT4 0x5452190
+
+#define mmNIC0_TXE0_DBG_COUNT_SELECT5 0x5452194
+
+#define mmNIC0_TXE0_DBG_COUNT_SELECT6 0x5452198
+
+#define mmNIC0_TXE0_DBG_COUNT_SELECT7 0x545219C
+
+#define mmNIC0_TXE0_DBG_COUNT_SELECT8 0x54521A0
+
+#define mmNIC0_TXE0_DBG_COUNT_SELECT9 0x54521A4
+
+#define mmNIC0_TXE0_DBG_COUNT_SELECT10 0x54521A8
+
+#define mmNIC0_TXE0_DBG_COUNT_SELECT11 0x54521AC
+
+#define mmNIC0_TXE0_BTH_MKEY 0x54521B0
+
+#define mmNIC0_TXE0_WQE_BUFF_FLUSH_SLICE_47_3 0x54521B4
+
+#define mmNIC0_TXE0_WQE_BUFF_FLUSH_SLICE_31_0 0x54521B8
+
+#define mmNIC0_TXE0_INTERRUPT_INDEX_MASK_RING_0 0x54521BC
+
+#define mmNIC0_TXE0_INTERRUPT_INDEX_MASK_RING_1 0x54521C0
+
+#define mmNIC0_TXE0_INTERRUPT_INDEX_MASK_RING_2 0x54521C4
+
+#define mmNIC0_TXE0_INTERRUPT_INDEX_MASK_RING_3 0x54521C8
+
+#define mmNIC0_TXE0_INTERRUPT_INDEX_MASK_RING_4 0x54521CC
+
+#define mmNIC0_TXE0_QPN_RING_0 0x54521D0
+
+#define mmNIC0_TXE0_QPN_RING_1 0x54521D4
+
+#define mmNIC0_TXE0_QPN_RING_2 0x54521D8
+
+#define mmNIC0_TXE0_QPN_RING_3 0x54521DC
+
+#define mmNIC0_TXE0_INTERRUPT_EACH_PACKET 0x54521F0
+
+#define mmNIC0_TXE0_EXECUTIN_INDEX_RING_0 0x54521F4
+
+#define mmNIC0_TXE0_EXECUTIN_INDEX_RING_1 0x54521F8
+
+#define mmNIC0_TXE0_EXECUTIN_INDEX_RING_2 0x54521FC
+
+#define mmNIC0_TXE0_EXECUTIN_INDEX_RING_3 0x5452200
+
+#define mmNIC0_TXE0_WQE_FETCH_AXI_USER_LO 0x5452208
+
+#define mmNIC0_TXE0_WQE_FETCH_AXI_USER_HI 0x545220C
+
+#define mmNIC0_TXE0_DATA_FETCH_AXI_USER_LO 0x5452210
+
+#define mmNIC0_TXE0_DATA_FETCH_AXI_USER_HI 0x5452214
+
+#define mmNIC0_TXE0_CHICKEN_BITS 0x5452218
+
+#define mmNIC0_TXE0_CHICKEN_BITS2 0x545221C
+
+#define mmNIC0_TXE0_WQE_CHECK_EN 0x5452220
+
+#define mmNIC0_TXE0_WQE_CHECK_EN2 0x5452224
+
+#define mmNIC0_TXE0_WQE_CHECK_CFG1 0x5452228
+
+#define mmNIC0_TXE0_WQE_CHECK_CFG2 0x545222C
+
+#define mmNIC0_TXE0_WQE_CHECK_CFG3 0x5452230
+
+#define mmNIC0_TXE0_WQE_CHECK_CONST1 0x5452234
+
+#define mmNIC0_TXE0_WQE_CHECK_CONST2 0x5452238
+
+#define mmNIC0_TXE0_WQE_CHECK_CONST3 0x545223C
+
+#define mmNIC0_TXE0_WQE_CHECK_CONST4 0x5452240
+
+#define mmNIC0_TXE0_WQE_CHECK_CONST5 0x5452244
+
+#define mmNIC0_TXE0_WQE_CHECK_CONST6 0x5452248
+
+#define mmNIC0_TXE0_WQE_CHECK_CONST7 0x545224C
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT0_0 0x5452250
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT0_1 0x5452254
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT0_2 0x5452258
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT0_3 0x545225C
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT0_4 0x5452260
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT0_5 0x5452264
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT0_6 0x5452268
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT0_7 0x545226C
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT1_0 0x5452270
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT1_1 0x5452274
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT1_2 0x5452278
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT1_3 0x545227C
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT1_4 0x5452280
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT1_5 0x5452284
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT1_6 0x5452288
+
+#define mmNIC0_TXE0_SOURCE_IP_PORT1_7 0x545228C
+
+#define mmNIC0_TXE0_BTH_RSVD 0x5452290
+
+#define mmNIC0_TXE0_MULTI_PKT_WQE 0x5452294
+
+#define mmNIC0_TXE0_TXWQC 0x54522A0
+
+#define mmNIC0_TXE0_TXWQC_STATUS 0x54522A4
+
+#define mmNIC0_TXE0_TXWQC_INVALIDATE 0x54522A8
+
+#define mmNIC0_TXE0_STATS_CFG0 0x54522B0
+
+#define mmNIC0_TXE0_STATS_CFG1 0x54522B4
+
+#define mmNIC0_TXE0_STATS_CFG2 0x54522B8
+
+#define mmNIC0_TXE0_STATS_TOT_BYTES_LSB 0x54522C0
+
+#define mmNIC0_TXE0_STATS_TOT_BYTES_MSB 0x54522C4
+
+#define mmNIC0_TXE0_STATS_TOT_PKTS_LSB 0x54522C8
+
+#define mmNIC0_TXE0_STATS_TOT_PKTS_MSB 0x54522CC
+
+#define mmNIC0_TXE0_STATS_MEAS_WIN_BYTES_LSB 0x54522D0
+
+#define mmNIC0_TXE0_STATS_MEAS_WIN_BYTES_MSB 0x54522D4
+
+#define mmNIC0_TXE0_STATS_MEAS_WIN_PKTS 0x54522D8
+
+#define mmNIC0_TXE0_STATS_MEAS_LATENCY 0x54522DC
+
+#define mmNIC0_TXE0_HW_EVENT_CFG 0x54522E0
+
+#define mmNIC0_TXE0_ENCAP_CFG_0 0x5452300
+
+#define mmNIC0_TXE0_ENCAP_CFG_1 0x5452304
+
+#define mmNIC0_TXE0_ENCAP_CFG_2 0x5452308
+
+#define mmNIC0_TXE0_ENCAP_CFG_3 0x545230C
+
+#define mmNIC0_TXE0_ENCAP_CFG_4 0x5452310
+
+#define mmNIC0_TXE0_ENCAP_CFG_5 0x5452314
+
+#define mmNIC0_TXE0_ENCAP_CFG_6 0x5452318
+
+#define mmNIC0_TXE0_ENCAP_CFG_7 0x545231C
+
+#define mmNIC0_TXE0_ENCAP_DATA_31_0_0 0x5452320
+
+#define mmNIC0_TXE0_ENCAP_DATA_31_0_1 0x5452324
+
+#define mmNIC0_TXE0_ENCAP_DATA_31_0_2 0x5452328
+
+#define mmNIC0_TXE0_ENCAP_DATA_31_0_3 0x545232C
+
+#define mmNIC0_TXE0_ENCAP_DATA_31_0_4 0x5452330
+
+#define mmNIC0_TXE0_ENCAP_DATA_31_0_5 0x5452334
+
+#define mmNIC0_TXE0_ENCAP_DATA_31_0_6 0x5452338
+
+#define mmNIC0_TXE0_ENCAP_DATA_31_0_7 0x545233C
+
+#define mmNIC0_TXE0_ENCAP_DATA_63_32_0 0x5452340
+
+#define mmNIC0_TXE0_ENCAP_DATA_63_32_1 0x5452344
+
+#define mmNIC0_TXE0_ENCAP_DATA_63_32_2 0x5452348
+
+#define mmNIC0_TXE0_ENCAP_DATA_63_32_3 0x545234C
+
+#define mmNIC0_TXE0_ENCAP_DATA_63_32_4 0x5452350
+
+#define mmNIC0_TXE0_ENCAP_DATA_63_32_5 0x5452354
+
+#define mmNIC0_TXE0_ENCAP_DATA_63_32_6 0x5452358
+
+#define mmNIC0_TXE0_ENCAP_DATA_63_32_7 0x545235C
+
+#define mmNIC0_TXE0_ENCAP_DATA_95_64_0 0x5452360
+
+#define mmNIC0_TXE0_ENCAP_DATA_95_64_1 0x5452364
+
+#define mmNIC0_TXE0_ENCAP_DATA_95_64_2 0x5452368
+
+#define mmNIC0_TXE0_ENCAP_DATA_95_64_3 0x545236C
+
+#define mmNIC0_TXE0_ENCAP_DATA_95_64_4 0x5452370
+
+#define mmNIC0_TXE0_ENCAP_DATA_95_64_5 0x5452374
+
+#define mmNIC0_TXE0_ENCAP_DATA_95_64_6 0x5452378
+
+#define mmNIC0_TXE0_ENCAP_DATA_95_64_7 0x545237C
+
+#define mmNIC0_TXE0_ENCAP_DATA_127_96_0 0x5452380
+
+#define mmNIC0_TXE0_ENCAP_DATA_127_96_1 0x5452384
+
+#define mmNIC0_TXE0_ENCAP_DATA_127_96_2 0x5452388
+
+#define mmNIC0_TXE0_ENCAP_DATA_127_96_3 0x545238C
+
+#define mmNIC0_TXE0_ENCAP_DATA_127_96_4 0x5452390
+
+#define mmNIC0_TXE0_ENCAP_DATA_127_96_5 0x5452394
+
+#define mmNIC0_TXE0_ENCAP_DATA_127_96_6 0x5452398
+
+#define mmNIC0_TXE0_ENCAP_DATA_127_96_7 0x545239C
+
+#define mmNIC0_TXE0_ENCAP_DATA_159_128_0 0x54523A0
+
+#define mmNIC0_TXE0_ENCAP_DATA_159_128_1 0x54523A4
+
+#define mmNIC0_TXE0_ENCAP_DATA_159_128_2 0x54523A8
+
+#define mmNIC0_TXE0_ENCAP_DATA_159_128_3 0x54523AC
+
+#define mmNIC0_TXE0_ENCAP_DATA_159_128_4 0x54523B0
+
+#define mmNIC0_TXE0_ENCAP_DATA_159_128_5 0x54523B4
+
+#define mmNIC0_TXE0_ENCAP_DATA_159_128_6 0x54523B8
+
+#define mmNIC0_TXE0_ENCAP_DATA_159_128_7 0x54523BC
+
+#define mmNIC0_TXE0_ENCAP_DATA_191_160_0 0x54523C0
+
+#define mmNIC0_TXE0_ENCAP_DATA_191_160_1 0x54523C4
+
+#define mmNIC0_TXE0_ENCAP_DATA_191_160_2 0x54523C8
+
+#define mmNIC0_TXE0_ENCAP_DATA_191_160_3 0x54523CC
+
+#define mmNIC0_TXE0_ENCAP_DATA_191_160_4 0x54523D0
+
+#define mmNIC0_TXE0_ENCAP_DATA_191_160_5 0x54523D4
+
+#define mmNIC0_TXE0_ENCAP_DATA_191_160_6 0x54523D8
+
+#define mmNIC0_TXE0_ENCAP_DATA_191_160_7 0x54523DC
+
+#define mmNIC0_TXE0_ENCAP_DATA_223_192_0 0x54523E0
+
+#define mmNIC0_TXE0_ENCAP_DATA_223_192_1 0x54523E4
+
+#define mmNIC0_TXE0_ENCAP_DATA_223_192_2 0x54523E8
+
+#define mmNIC0_TXE0_ENCAP_DATA_223_192_3 0x54523EC
+
+#define mmNIC0_TXE0_ENCAP_DATA_223_192_4 0x54523F0
+
+#define mmNIC0_TXE0_ENCAP_DATA_223_192_5 0x54523F4
+
+#define mmNIC0_TXE0_ENCAP_DATA_223_192_6 0x54523F8
+
+#define mmNIC0_TXE0_ENCAP_DATA_223_192_7 0x54523FC
+
+#define mmNIC0_TXE0_ENCAP_DATA_255_224_0 0x5452400
+
+#define mmNIC0_TXE0_ENCAP_DATA_255_224_1 0x5452404
+
+#define mmNIC0_TXE0_ENCAP_DATA_255_224_2 0x5452408
+
+#define mmNIC0_TXE0_ENCAP_DATA_255_224_3 0x545240C
+
+#define mmNIC0_TXE0_ENCAP_DATA_255_224_4 0x5452410
+
+#define mmNIC0_TXE0_ENCAP_DATA_255_224_5 0x5452414
+
+#define mmNIC0_TXE0_ENCAP_DATA_255_224_6 0x5452418
+
+#define mmNIC0_TXE0_ENCAP_DATA_255_224_7 0x545241C
+
+#define mmNIC0_TXE0_ENCAP_CFG2 0x5452420
+
+#define mmNIC0_TXE0_MTD_DUAL_STRIDE3 0x5452430
+
+#define mmNIC0_TXE0_MTD_DUAL_STRIDE4 0x5452434
+
+#define mmNIC0_TXE0_MTD_DUAL_NUM_OF_STRIDES 0x5452438
+
+#define mmNIC0_TXE0_CLK_GATE_CFG 0x5452440
+
+#define mmNIC0_TXE0_WQE_CHECK_NOTIFY_EN 0x5452450
+
+#define mmNIC0_TXE0_WQE_CHECK_NOTIFY_EN2 0x5452454
+
+#define mmNIC0_TXE0_WQE_CHECK_CFG4 0x5452458
+
+#define mmNIC0_TXE0_WQE_CHECK_CFG5 0x545245C
+
+#define mmNIC0_TXE0_WQE_CHECK_CFG6 0x5452460
+
+#define mmNIC0_TXE0_DATA_READ_RL_CFG 0x5452470
+
+#endif /* ASIC_REG_NIC0_TXE0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_txs0_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_txs0_regs.h
new file mode 100644
index 000000000000..94db189452b4
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_txs0_regs.h
@@ -0,0 +1,289 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_TXS0_REGS_H_
+#define ASIC_REG_NIC0_TXS0_REGS_H_
+
+/*
+ *****************************************
+ * NIC0_TXS0
+ * (Prototype: NIC_TXS)
+ *****************************************
+ */
+
+#define mmNIC0_TXS0_TMR_SCAN_EN 0x5450000
+
+#define mmNIC0_TXS0_TICK_WRAP 0x5450004
+
+#define mmNIC0_TXS0_SCAN_TIME_COMPARE_0 0x5450008
+
+#define mmNIC0_TXS0_SCAN_TIME_COMPARE_1 0x545000C
+
+#define mmNIC0_TXS0_SLICE_CREDIT 0x5450010
+
+#define mmNIC0_TXS0_SLICE_FORCE_FULL 0x5450014
+
+#define mmNIC0_TXS0_FIRST_SCHEDQ_ID 0x5450018
+
+#define mmNIC0_TXS0_LAST_SCHEDQ_ID 0x545001C
+
+#define mmNIC0_TXS0_PUSH_MASK 0x5450020
+
+#define mmNIC0_TXS0_POP_MASK 0x5450024
+
+#define mmNIC0_TXS0_PUSH_RELEASE_INVALIDATE 0x5450028
+
+#define mmNIC0_TXS0_POP_RELEASE_INVALIDATE 0x545002C
+
+#define mmNIC0_TXS0_LIST_MEM_READ_MASK 0x5450030
+
+#define mmNIC0_TXS0_FIFO_MEM_READ_MASK 0x5450034
+
+#define mmNIC0_TXS0_LIST_MEM_WRITE_MASK 0x5450038
+
+#define mmNIC0_TXS0_FIFO_MEM_WRITE_MASK 0x545003C
+
+#define mmNIC0_TXS0_BASE_ADDRESS_63_32 0x5450040
+
+#define mmNIC0_TXS0_BASE_ADDRESS_31_7 0x5450044
+
+#define mmNIC0_TXS0_AXI_PROT 0x545004C
+
+#define mmNIC0_TXS0_RATE_LIMIT 0x5450050
+
+#define mmNIC0_TXS0_CACHE_CFG 0x5450054
+
+#define mmNIC0_TXS0_SCHEDQ_MEM_INIT 0x5450058
+
+#define mmNIC0_TXS0_SCHEDQ_UPDATE_EN 0x545005C
+
+#define mmNIC0_TXS0_SCHEDQ_UPDATE_FIFO 0x5450060
+
+#define mmNIC0_TXS0_SCHEDQ_UPDATE_DESC_31_0 0x5450064
+
+#define mmNIC0_TXS0_SCHEDQ_UPDATE_DESC_63_32 0x5450068
+
+#define mmNIC0_TXS0_SCHEDQ_UPDATE_DESC_95_64 0x545006C
+
+#define mmNIC0_TXS0_SCHEDQ_UPDATE_DESC_127_96 0x5450070
+
+#define mmNIC0_TXS0_SCHEDQ_UPDATE_DESC_159_128 0x5450074
+
+#define mmNIC0_TXS0_SCHEDQ_UPDATE_DESC_191_160 0x5450078
+
+#define mmNIC0_TXS0_SCHEDQ_UPDATE_DESC_217_192 0x545007C
+
+#define mmNIC0_TXS0_FORCE_HIT_EN 0x5450080
+
+#define mmNIC0_TXS0_INVALIDATE_LIST 0x5450084
+
+#define mmNIC0_TXS0_INVALIDATE_LIST_STATUS 0x5450088
+
+#define mmNIC0_TXS0_INVALIDATE_FREE_LIST 0x545008C
+
+#define mmNIC0_TXS0_INVALIDATE_FREE_LIST_STAT 0x5450090
+
+#define mmNIC0_TXS0_PUSH_PREFETCH_EN 0x5450094
+
+#define mmNIC0_TXS0_PUSH_RELEASE_EN 0x5450098
+
+#define mmNIC0_TXS0_PUSH_LOCK_EN 0x545009C
+
+#define mmNIC0_TXS0_PUSH_PREFETCH_NEXT_EN 0x54500A0
+
+#define mmNIC0_TXS0_POP_PREFETCH_EN 0x54500A4
+
+#define mmNIC0_TXS0_POP_RELEASE_EN 0x54500A8
+
+#define mmNIC0_TXS0_POP_LOCK_EN 0x54500AC
+
+#define mmNIC0_TXS0_POP_PREFETCH_NEXT_EN 0x54500B0
+
+#define mmNIC0_TXS0_LIST_MASK 0x54500B4
+
+#define mmNIC0_TXS0_RELEASE_INCALIDATE 0x54500B8
+
+#define mmNIC0_TXS0_BASE_ADDRESS_FREE_LIST_63_32 0x54500BC
+
+#define mmNIC0_TXS0_BASE_ADDRESS_FREE_LIST_31_0 0x54500C0
+
+#define mmNIC0_TXS0_FREE_LIST_EN 0x54500C4
+
+#define mmNIC0_TXS0_PUSH_FORCE_HIT_EN 0x54500C8
+
+#define mmNIC0_TXS0_PRODUCER_UPDATE_EN 0x54500CC
+
+#define mmNIC0_TXS0_PRODUCER_UPDATE 0x54500D0
+
+#define mmNIC0_TXS0_PRIOQ_CREDIT_FORCE 0x54500D4
+
+#define mmNIC0_TXS0_PRIOQ_CREDIT_0 0x54500D8
+
+#define mmNIC0_TXS0_PRIOQ_CREDIT_1 0x54500DC
+
+#define mmNIC0_TXS0_PRIOQ_CREDIT_2 0x54500E0
+
+#define mmNIC0_TXS0_PRIOQ_CREDIT_3 0x54500E4
+
+#define mmNIC0_TXS0_PRIOQ_CREDIT_4 0x54500E8
+
+#define mmNIC0_TXS0_PRIOQ_CREDIT_5 0x54500EC
+
+#define mmNIC0_TXS0_PRIOQ_CREDIT_6 0x54500F0
+
+#define mmNIC0_TXS0_PRIOQ_CREDIT_7 0x54500F4
+
+#define mmNIC0_TXS0_DBG_COUNT_SELECT0 0x54500F8
+
+#define mmNIC0_TXS0_DBG_COUNT_SELECT1 0x54500FC
+
+#define mmNIC0_TXS0_DBG_COUNT_SELECT2 0x5450100
+
+#define mmNIC0_TXS0_DBG_COUNT_SELECT3 0x5450104
+
+#define mmNIC0_TXS0_DBG_COUNT_SELECT4 0x5450108
+
+#define mmNIC0_TXS0_DBG_COUNT_SELECT5 0x545010C
+
+#define mmNIC0_TXS0_DBG_COUNT_SELECT6 0x5450110
+
+#define mmNIC0_TXS0_DBG_COUNT_SELECT7 0x5450114
+
+#define mmNIC0_TXS0_DBG_COUNT_SELECT8 0x5450118
+
+#define mmNIC0_TXS0_DBG_COUNT_SELECT9 0x545011C
+
+#define mmNIC0_TXS0_DBG_COUNT_SELECT10 0x5450120
+
+#define mmNIC0_TXS0_DBG_COUNT_SELECT11 0x5450124
+
+#define mmNIC0_TXS0_IGNORE_BURST_EN 0x5450140
+
+#define mmNIC0_TXS0_IGNORE_BURST_THRESHOLD_0 0x5450144
+
+#define mmNIC0_TXS0_IGNORE_BURST_THRESHOLD_1 0x5450148
+
+#define mmNIC0_TXS0_IGNORE_BURST_THRESHOLD_2 0x545014C
+
+#define mmNIC0_TXS0_IGNORE_BURST_THRESHOLD_3 0x5450150
+
+#define mmNIC0_TXS0_IGNORE_BURST_THRESHOLD_4 0x5450154
+
+#define mmNIC0_TXS0_IGNORE_BURST_THRESHOLD_5 0x5450158
+
+#define mmNIC0_TXS0_IGNORE_BURST_THRESHOLD_6 0x545015C
+
+#define mmNIC0_TXS0_IGNORE_BURST_THRESHOLD_7 0x5450160
+
+#define mmNIC0_TXS0_RANDOM_PSUH_CFG 0x5450164
+
+#define mmNIC0_TXS0_DBG_HW_EVENT_TRIGER 0x5450168
+
+#define mmNIC0_TXS0_INTERRUPT_CAUSE 0x545016C
+
+#define mmNIC0_TXS0_INTERRUPT_MASK 0x5450170
+
+#define mmNIC0_TXS0_INTERRUPT_CLR 0x5450174
+
+#define mmNIC0_TXS0_LOAD_SLICE_HIT_EN 0x5450178
+
+#define mmNIC0_TXS0_SLICE_ACTIVE_47_32 0x545017C
+
+#define mmNIC0_TXS0_SLICE_ACTIVE_31_0 0x5450180
+
+#define mmNIC0_TXS0_AXI_CACHE 0x5450184
+
+#define mmNIC0_TXS0_SLICE_GW_ADDR 0x5450188
+
+#define mmNIC0_TXS0_SLICE_GW_DATA 0x545018C
+
+#define mmNIC0_TXS0_SCANNER_CREDIT_EN 0x5450190
+
+#define mmNIC0_TXS0_FREE_LIST_PUSH_MASK_EN 0x5450194
+
+#define mmNIC0_TXS0_FREE_AEMPTY_THRESHOLD 0x5450198
+
+#define mmNIC0_TXS0_AXI_USER_LO 0x5450200
+
+#define mmNIC0_TXS0_AXI_USER_HI 0x5450204
+
+#define mmNIC0_TXS0_NCH_SYNCED 0x5450210
+
+#define mmNIC0_TXS0_NCH_ASYNCED 0x5450214
+
+#define mmNIC0_TXS0_NCH_ASYNCED_RES 0x5450218
+
+#define mmNIC0_TXS0_STATS_CFG 0x5450220
+
+#define mmNIC0_TXS0_STATS_TOT_PUSH_REQ 0x5450230
+
+#define mmNIC0_TXS0_STATS_TOT_PUSH_RES 0x5450234
+
+#define mmNIC0_TXS0_STATS_TOT_SCHED_QP_REQ 0x5450238
+
+#define mmNIC0_TXS0_STATS_TOT_SCHED_QP_RES 0x545023C
+
+#define mmNIC0_TXS0_STATS_TOT_RETURN_SLICE 0x5450240
+
+#define mmNIC0_TXS0_STATS_WIN_PUSH_REQ 0x5450250
+
+#define mmNIC0_TXS0_STATS_WIN_PUSH_RES 0x5450254
+
+#define mmNIC0_TXS0_STATS_WIN_SCHED_QP_REQ 0x5450258
+
+#define mmNIC0_TXS0_STATS_WIN_SCHED_QP_RES 0x545025C
+
+#define mmNIC0_TXS0_STATS_WIN_RETURN_SLICE 0x5450260
+
+#define mmNIC0_TXS0_ASYNC_NICL_APB_ADDR_MASK 0x5450270
+
+#define mmNIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR0 0x5450274
+
+#define mmNIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR1 0x5450278
+
+#define mmNIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR2 0x545027C
+
+#define mmNIC0_TXS0_ASYNC_NICL_APB_SPLIT_ADDR3 0x5450280
+
+#define mmNIC0_TXS0_ASYNC_NICD_APB_ADDR_MASK 0x5450290
+
+#define mmNIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR0 0x5450294
+
+#define mmNIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR1 0x5450298
+
+#define mmNIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR2 0x545029C
+
+#define mmNIC0_TXS0_ASYNC_NICD_APB_SPLIT_ADDR3 0x54502A0
+
+#define mmNIC0_TXS0_TX_APB_ADDR_MASK 0x54502B0
+
+#define mmNIC0_TXS0_TX_APB_SPLIT_ADDR0 0x54502B4
+
+#define mmNIC0_TXS0_TX_APB_SPLIT_ADDR1 0x54502B8
+
+#define mmNIC0_TXS0_TX_APB_SPLIT_ADDR2 0x54502BC
+
+#define mmNIC0_TXS0_TX_APB_SPLIT_ADDR3 0x54502C0
+
+#define mmNIC0_TXS0_TX_APB_SPLIT_ADDR4 0x54502C4
+
+#define mmNIC0_TXS0_TX_APB_SPLIT_ADDR5 0x54502C8
+
+#define mmNIC0_TXS0_TX_APB_SPLIT_ADDR6 0x54502CC
+
+#define mmNIC0_TXS0_HW_EVENT_CFG 0x54502E0
+
+#define mmNIC0_TXS0_CHICKEN_BITS 0x54502E8
+
+#define mmNIC0_TXS0_CLK_GATE_CFG 0x54502F0
+
+#endif /* ASIC_REG_NIC0_TXS0_REGS_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* [PATCH 15/15] accel/habanalabs/gaudi2: network scaling support
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
` (13 preceding siblings ...)
2024-06-13 8:22 ` [PATCH 14/15] accel/habanalabs/gaudi2: CN registers header files Omer Shpigelman
@ 2024-06-13 8:22 ` Omer Shpigelman
2024-06-17 12:34 ` [PATCH 00/15] Introduce HabanaLabs network drivers Alexander Lobakin
2024-06-19 16:33 ` Jiri Pirko
16 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-13 8:22 UTC (permalink / raw)
To: linux-kernel, linux-rdma, netdev, dri-devel
Cc: ogabbay, oshpigelman, zyehudai
Add GAUDI2 ASIC specific support for AI scaling over the network.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Co-developed-by: Abhilash K V <kvabhilash@habana.ai>
Signed-off-by: Abhilash K V <kvabhilash@habana.ai>
Co-developed-by: Andrey Agranovich <aagranovich@habana.ai>
Signed-off-by: Andrey Agranovich <aagranovich@habana.ai>
Co-developed-by: Bharat Jauhari <bjauhari@habana.ai>
Signed-off-by: Bharat Jauhari <bjauhari@habana.ai>
Co-developed-by: David Meriin <dmeriin@habana.ai>
Signed-off-by: David Meriin <dmeriin@habana.ai>
Co-developed-by: Sagiv Ozeri <sozeri@habana.ai>
Signed-off-by: Sagiv Ozeri <sozeri@habana.ai>
Co-developed-by: Zvika Yehudai <zyehudai@habana.ai>
Signed-off-by: Zvika Yehudai <zyehudai@habana.ai>
---
drivers/accel/habanalabs/gaudi2/Makefile | 2 +-
drivers/accel/habanalabs/gaudi2/gaudi2.c | 426 +++++++++++++++++-
drivers/accel/habanalabs/gaudi2/gaudi2P.h | 41 +-
drivers/accel/habanalabs/gaudi2/gaudi2_cn.c | 424 +++++++++++++++++
drivers/accel/habanalabs/gaudi2/gaudi2_cn.h | 42 ++
.../habanalabs/gaudi2/gaudi2_coresight.c | 145 +++++-
6 files changed, 1050 insertions(+), 30 deletions(-)
create mode 100644 drivers/accel/habanalabs/gaudi2/gaudi2_cn.c
create mode 100644 drivers/accel/habanalabs/gaudi2/gaudi2_cn.h
diff --git a/drivers/accel/habanalabs/gaudi2/Makefile b/drivers/accel/habanalabs/gaudi2/Makefile
index 1e047883ba74..289e69a355b1 100644
--- a/drivers/accel/habanalabs/gaudi2/Makefile
+++ b/drivers/accel/habanalabs/gaudi2/Makefile
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
HL_GAUDI2_FILES := gaudi2/gaudi2.o gaudi2/gaudi2_security.o \
- gaudi2/gaudi2_coresight.o
+ gaudi2/gaudi2_coresight.o gaudi2/gaudi2_cn.o
diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2.c b/drivers/accel/habanalabs/gaudi2/gaudi2.c
index a22d2a93394e..6417c69d47af 100644
--- a/drivers/accel/habanalabs/gaudi2/gaudi2.c
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2.c
@@ -1,12 +1,14 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright 2020-2022 HabanaLabs, Ltd.
+ * Copyright 2020-2024 HabanaLabs, Ltd.
* All Rights Reserved.
*/
#include "gaudi2P.h"
+#include "gaudi2_cn.h"
#include "gaudi2_masks.h"
+#include "gaudi2_coresight_regs.h"
#include "../include/gaudi2/gaudi2_special_blocks.h"
#include "../include/hw_ip/mmu/mmu_general.h"
#include "../include/hw_ip/mmu/mmu_v2_0.h"
@@ -2216,6 +2218,9 @@ static bool gaudi2_get_edma_idle_status(struct hl_device *hdev, u64 *mask_arr, u
struct engines_data *e);
static u64 gaudi2_mmu_scramble_addr(struct hl_device *hdev, u64 raw_addr);
static u64 gaudi2_mmu_descramble_addr(struct hl_device *hdev, u64 scrambled_addr);
+static int gaudi2_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len, u32 timeout,
+ u64 *result);
+static void gaudi2_init_cn(struct hl_device *hdev);
static void gaudi2_init_scrambler_hbm(struct hl_device *hdev)
{
@@ -2382,15 +2387,17 @@ static int gaudi2_set_dram_properties(struct hl_device *hdev)
hbm_drv_base_offset = roundup(CPU_FW_IMAGE_SIZE, prop->num_functional_hbms * SZ_8M);
/*
- * The NIC driver section size and the HMMU page tables section in the HBM needs
- * to be the remaining size in the first dram page after taking into
- * account the F/W image size
+ * The NIC driver section size and the HMMU page tables section in the HBM needs to be the
+ * remaining size in the first dram page after taking into account the F/W image size.
*/
+ prop->nic_drv_size = (prop->dram_page_size - hbm_drv_base_offset) -
+ (HMMU_PAGE_TABLES_SIZE + EDMA_PQS_SIZE + EDMA_SCRATCHPAD_SIZE);
+ prop->nic_drv_addr = DRAM_PHYS_BASE + hbm_drv_base_offset;
+
+ prop->clk = GAUDI2_NIC_CLK_FREQ / USEC_PER_SEC;
/* Reserve region in HBM for HMMU page tables */
- prop->mmu_pgt_addr = DRAM_PHYS_BASE + hbm_drv_base_offset +
- ((prop->dram_page_size - hbm_drv_base_offset) -
- (HMMU_PAGE_TABLES_SIZE + EDMA_PQS_SIZE + EDMA_SCRATCHPAD_SIZE));
+ prop->mmu_pgt_addr = prop->nic_drv_addr + prop->nic_drv_size;
/* Set EDMA PQs HBM addresses */
edma_pq_base_addr = prop->mmu_pgt_addr + HMMU_PAGE_TABLES_SIZE;
@@ -2409,6 +2416,7 @@ static int gaudi2_set_dram_properties(struct hl_device *hdev)
static int gaudi2_set_fixed_properties(struct hl_device *hdev)
{
struct asic_fixed_properties *prop = &hdev->asic_prop;
+ struct hl_cn_properties *cn_prop = &prop->cn_props;
struct hw_queue_properties *q_props;
u32 num_sync_stream_queues = 0;
int i, rc;
@@ -2601,6 +2609,10 @@ static int gaudi2_set_fixed_properties(struct hl_device *hdev)
prop->hbw_flush_reg = mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0;
+ prop->macro_cfg_size = NIC_OFFSET;
+ cn_prop->status_packet_size = sizeof(struct cpucp_nic_status);
+ cn_prop->max_num_of_ports = NIC_NUMBER_OF_PORTS;
+
return 0;
free_qprops:
@@ -2996,8 +3008,16 @@ static int gaudi2_cpucp_info_get(struct hl_device *hdev)
u64 dram_size;
int rc;
- if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q))
+ if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q)) {
+ /* Skip for hard or device release reset flow. No need to repopulate. */
+ if (!hdev->reset_info.in_reset) {
+ rc = gaudi2_cn_set_info(hdev, false);
+ if (rc)
+ return rc;
+ }
+
return 0;
+ }
/* No point of asking this information again when not doing hard reset, as the device
* CPU hasn't been reset
@@ -3058,23 +3078,47 @@ static int gaudi2_cpucp_info_get(struct hl_device *hdev)
prop->max_power_default = (u64) max_power;
- return 0;
+ /* Repopulate post hard reset since device CPU has been reset */
+ return gaudi2_cn_set_info(hdev, true);
}
-static int gaudi2_fetch_psoc_frequency(struct hl_device *hdev)
+static int gaudi2_fetch_frequency(struct hl_device *hdev, u32 pll_index, u16 *pll_freq_arr)
{
struct gaudi2_device *gaudi2 = hdev->asic_specific;
- u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS];
- int rc;
if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q))
return 0;
- rc = hl_fw_cpucp_pll_info_get(hdev, HL_GAUDI2_CPU_PLL, pll_freq_arr);
+ return hl_fw_cpucp_pll_info_get(hdev, pll_index, pll_freq_arr);
+}
+
+static int gaudi2_fetch_psoc_frequency(struct hl_device *hdev)
+{
+ u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS] = {0};
+ int rc;
+
+ rc = gaudi2_fetch_frequency(hdev, HL_GAUDI2_CPU_PLL, pll_freq_arr);
+ if (rc)
+ return rc;
+
+ if (pll_freq_arr[3] != 0)
+ hdev->asic_prop.psoc_timestamp_frequency = pll_freq_arr[3];
+
+ return 0;
+}
+
+static int gaudi2_fetch_nic_frequency(struct hl_device *hdev)
+{
+ u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS] = {0};
+ int rc;
+
+ rc = gaudi2_fetch_frequency(hdev, HL_GAUDI2_NIC_PLL, pll_freq_arr);
if (rc)
return rc;
- hdev->asic_prop.psoc_timestamp_frequency = pll_freq_arr[3];
+ /* DIV1 - nic_clk */
+ if (pll_freq_arr[1] != 0)
+ hdev->asic_prop.clk = pll_freq_arr[1];
return 0;
}
@@ -3237,6 +3281,79 @@ static void gaudi2_init_arcs(struct hl_device *hdev)
CFG_BASE + le32_to_cpu(dyn_regs->eng_arc_irq_ctrl);
}
+static int gaudi2_cn_clear_mem(struct hl_device *hdev)
+{
+ u32 nic_drv_size, gran_per_packet, num_iter;
+ struct asic_fixed_properties *asic_prop;
+ struct cpucp_cn_clear_mem_packet pkt;
+ bool use_cpucp;
+ int i, rc = 0;
+ u64 val = 0;
+
+ if (!hdev->cn.ports_mask)
+ return rc;
+
+ asic_prop = &hdev->asic_prop;
+
+ use_cpucp = !!(hdev->asic_prop.fw_app_cpu_boot_dev_sts0 &
+ CPU_BOOT_DEV_STS0_NIC_MEM_CLEAR_EN);
+ if (use_cpucp) {
+ /* nic driver size is expected to be less than 4GB in gaudi2 */
+ if (asic_prop->nic_drv_size > BIT(32)) {
+ dev_err(hdev->dev,
+ "Failed to clear NIC memory, nic size is 0x%llx is bigger than 4GB\n",
+ asic_prop->nic_drv_size);
+ return -EINVAL;
+ }
+
+ /* subtract 1 to support size of 4GB as well */
+ nic_drv_size = (asic_prop->nic_drv_size - 1) & 0xFFFFFFFF;
+ /* max 250 MB per packet, in order to avoid CPUCP packet timeout */
+ gran_per_packet = 250 * 1024 * 1024;
+ num_iter = (nic_drv_size + gran_per_packet) / gran_per_packet;
+
+ for (i = 0; i < num_iter; i++) {
+ memset(&pkt, 0, sizeof(pkt));
+ pkt.cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_NIC_CLR_MEM <<
+ CPUCP_PKT_CTL_OPCODE_SHIFT);
+ pkt.mem_base_addr = cpu_to_le64(asic_prop->nic_drv_addr +
+ i * gran_per_packet);
+
+ if (i < num_iter - 1)
+ pkt.size = cpu_to_le32(gran_per_packet);
+ else
+ /* add 1 as it was subtracted in original size calculation */
+ pkt.size = cpu_to_le32(nic_drv_size - gran_per_packet * i + 1);
+
+ rc = gaudi2_send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, NULL);
+ if (rc) {
+ dev_err(hdev->dev,
+ "Failed to handle CPU-CP pkt %u, error %d\n",
+ CPUCP_PACKET_NIC_CLR_MEM, rc);
+ return rc;
+ }
+ }
+ } else {
+ for (i = 0; i < hdev->asic_prop.nic_drv_size; i += sizeof(val)) {
+ rc = hdev->asic_funcs->access_dev_mem(hdev, PCI_REGION_DRAM,
+ hdev->asic_prop.nic_drv_addr + i,
+ &val, DEBUGFS_WRITE64);
+
+ if (rc) {
+ dev_err(hdev->dev, "Failed to set nic memory. addr: 0x%llx",
+ hdev->asic_prop.nic_drv_addr + i);
+ return rc;
+ }
+
+ /* sleep every 32MB to avoid high CPU utilization */
+ if (i && !(i % SZ_32M))
+ usleep_range(50, 100);
+ }
+ }
+
+ return rc;
+}
+
static int gaudi2_scrub_arc_dccm(struct hl_device *hdev, u32 cpu_id)
{
u32 reg_base, reg_val;
@@ -3303,6 +3420,15 @@ static int gaudi2_scrub_arcs_dccm(struct hl_device *hdev)
return 0;
}
+static int gaudi2_nic_unmask_ecc_interrupts(struct hl_device *hdev)
+{
+ struct cpucp_packet pkt = {};
+
+ pkt.ctl = cpu_to_le32(CPUCP_PACKET_NIC_ECC_INTRS_UNMASK << CPUCP_PKT_CTL_OPCODE_SHIFT);
+
+ return gaudi2_send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, NULL);
+}
+
static int gaudi2_late_init(struct hl_device *hdev)
{
struct gaudi2_device *gaudi2 = hdev->asic_specific;
@@ -3329,6 +3455,24 @@ static int gaudi2_late_init(struct hl_device *hdev)
goto disable_pci_access;
}
+ rc = gaudi2_fetch_nic_frequency(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to fetch NIC frequency\n");
+ goto disable_pci_access;
+ }
+
+ rc = gaudi2_cn_clear_mem(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to clear CN memory\n");
+ goto disable_pci_access;
+ }
+
+ rc = gaudi2_nic_unmask_ecc_interrupts(hdev);
+ if (rc) {
+ dev_err(hdev->dev, "Failed to unmask NIC ECC interrupts\n");
+ goto disable_pci_access;
+ }
+
gaudi2_init_arcs(hdev);
rc = gaudi2_scrub_arcs_dccm(hdev);
@@ -4836,6 +4980,13 @@ static void gaudi2_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw
else
wait_timeout_ms = GAUDI2_RESET_WAIT_MSEC;
+ /*
+ * Mark the NIC as in reset to avoid any new NIC accesses to the H/W. This must be done
+ * before we stop the CPU as the NIC might use it e.g. get/set EEPROM data.
+ */
+ if (hard_reset)
+ hl_cn_hard_reset_prepare(hdev, fw_reset);
+
if (fw_reset)
goto skip_engines;
@@ -4872,11 +5023,14 @@ static void gaudi2_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw
skip_engines:
if (hard_reset) {
+ hl_cn_stop(hdev);
gaudi2_disable_msix(hdev);
return;
}
+ gaudi2_cn_compute_reset_prepare(hdev);
gaudi2_sync_irqs(hdev);
+ hl_cn_synchronize_irqs(hdev);
}
static void gaudi2_init_firmware_preload_params(struct hl_device *hdev)
@@ -5377,7 +5531,7 @@ static void gaudi2_arm_monitors_for_virt_msix_db(struct hl_device *hdev, u32 sob
static void gaudi2_prepare_sm_for_virt_msix_db(struct hl_device *hdev)
{
- u32 decoder_id, sob_id, first_mon_id, interrupt_id;
+ u32 decoder_id, port, sob_id, first_mon_id, interrupt_id;
struct asic_fixed_properties *prop = &hdev->asic_prop;
/* Decoder normal/abnormal interrupts */
@@ -5395,6 +5549,14 @@ static void gaudi2_prepare_sm_for_virt_msix_db(struct hl_device *hdev)
interrupt_id += 1;
gaudi2_arm_monitors_for_virt_msix_db(hdev, sob_id, first_mon_id, interrupt_id);
}
+
+ /* NIC EQ interrupts */
+ for (port = 0 ; port < NIC_NUMBER_OF_PORTS ; ++port) {
+ sob_id = GAUDI2_RESERVED_SOB_NIC_PORT_FIRST + port;
+ first_mon_id = GAUDI2_RESERVED_MON_NIC_PORT_FIRST + 3 * port;
+ interrupt_id = GAUDI2_IRQ_NUM_NIC_PORT_FIRST + port;
+ gaudi2_arm_monitors_for_virt_msix_db(hdev, sob_id, first_mon_id, interrupt_id);
+ }
}
static void gaudi2_init_sm(struct hl_device *hdev)
@@ -6161,6 +6323,8 @@ static int gaudi2_hw_init(struct hl_device *hdev)
return rc;
}
+ gaudi2_cn_quiescence(hdev);
+
gaudi2_init_scrambler_hbm(hdev);
gaudi2_init_kdma(hdev);
@@ -6187,6 +6351,7 @@ static int gaudi2_hw_init(struct hl_device *hdev)
gaudi2_init_mme(hdev);
gaudi2_init_rotator(hdev);
gaudi2_init_dec(hdev);
+ gaudi2_init_cn(hdev);
gaudi2_enable_timestamp(hdev);
rc = gaudi2_coresight_init(hdev);
@@ -6469,6 +6634,12 @@ static int gaudi2_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset
gaudi2_poll_btm_indication(hdev, poll_timeout_us);
}
+ /* On PLDM the NIC PHY link is always up, and because the NIC interrupts are enabled by
+ * default - need to disable the interrupts ASAP.
+ */
+ if (hard_reset && hdev->pldm)
+ gaudi2_cn_disable_interrupts(hdev);
+
if (!gaudi2)
return 0;
@@ -6488,7 +6659,7 @@ static int gaudi2_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset
HW_CAP_PMMU | HW_CAP_CPU | HW_CAP_CPU_Q |
HW_CAP_SRAM_SCRAMBLER | HW_CAP_DMMU_MASK |
HW_CAP_PDMA_MASK | HW_CAP_EDMA_MASK | HW_CAP_KDMA |
- HW_CAP_MME_MASK | HW_CAP_ROT_MASK);
+ HW_CAP_MME_MASK | HW_CAP_ROT_MASK | HW_CAP_NIC_DRV);
memset(gaudi2->events_stat, 0, sizeof(gaudi2->events_stat));
} else {
@@ -7173,6 +7344,8 @@ static int gaudi2_compute_reset_late_init(struct hl_device *hdev)
gaudi2_init_security(hdev);
+ gaudi2_cn_compute_reset_late_init(hdev);
+
/* Unmask all IRQs since some could have been received during the soft reset */
irq_arr_size = gaudi2->num_of_valid_hw_events * sizeof(gaudi2->hw_events[0]);
return hl_fw_unmask_irq_arr(hdev, gaudi2->hw_events, irq_arr_size);
@@ -7557,6 +7730,30 @@ static void gaudi2_hw_queues_unlock(struct hl_device *hdev)
spin_unlock(&gaudi2->hw_queues_lock);
}
+void gaudi2_init_cn(struct hl_device *hdev)
+{
+ struct gaudi2_device *gaudi2 = hdev->asic_specific;
+ u32 i, reg_base, queue_id;
+
+ if (!hdev->cn.ports_mask)
+ return;
+
+ if (gaudi2->nic_hw_cap_initialized & HW_CAP_NIC_MASK)
+ return;
+
+ queue_id = GAUDI2_QUEUE_ID_NIC_0_0;
+
+ for (i = 0; i < NIC_NUMBER_OF_ENGINES;
+ i++, queue_id += NUM_OF_PQ_PER_QMAN) {
+ if (!(hdev->cn.ports_mask & BIT(i)))
+ continue;
+
+ reg_base = gaudi2_qm_blocks_bases[queue_id];
+ gaudi2_init_qman(hdev, reg_base, queue_id);
+ gaudi2->nic_hw_cap_initialized |= BIT_ULL(i);
+ }
+}
+
static u32 gaudi2_get_pci_id(struct hl_device *hdev)
{
return hdev->pdev->device;
@@ -7779,7 +7976,7 @@ static int gaudi2_mmu_shared_prepare(struct hl_device *hdev, u32 asid)
{
struct asic_fixed_properties *prop = &hdev->asic_prop;
u32 rw_asid, offset;
- int rc, i;
+ int rc, i, q;
rw_asid = FIELD_PREP(ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_MASK, asid) |
FIELD_PREP(ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_MASK, asid);
@@ -7819,6 +8016,18 @@ static int gaudi2_mmu_shared_prepare(struct hl_device *hdev, u32 asid)
if (rc)
return rc;
+ /* NIC */
+ for (i = 0 ; i < NIC_NUMBER_OF_MACROS ; i++)
+ for (q = 0 ; q < NIC_NUMBER_OF_QM_PER_MACRO ; q++) {
+ if (!(hdev->cn.ports_mask & BIT(i * NIC_NUMBER_OF_QM_PER_MACRO + q)))
+ continue;
+
+ WREG32(mmNIC0_QM0_AXUSER_NONSECURED_HB_ASID +
+ i * NIC_OFFSET + q * NIC_QM_OFFSET, rw_asid);
+ WREG32(mmNIC0_QM0_AXUSER_NONSECURED_HB_MMU_BP +
+ i * NIC_OFFSET + q * NIC_QM_OFFSET, 0);
+ }
+
return 0;
}
@@ -7936,6 +8145,47 @@ static bool gaudi2_handle_ecc_event(struct hl_device *hdev, u16 event_type,
return !!ecc_data->is_critical;
}
+static void gaudi2_handle_bmon_spmu_event(struct hl_device *hdev, u8 macro_index)
+{
+ /* For this point a profiler is not configuring the BMON and SPMU block and
+ * therefore we can't deduce which port and entity triggered the interrupt.
+ * So for now we only clear all interrupt registers to prevent interrupt flood
+ */
+ u32 macro_offset = GAUDI2_SPMU_NIC1_DBG_0 - GAUDI2_SPMU_NIC0_DBG_0;
+
+ WREG32(debug_spmu_regs[GAUDI2_SPMU_NIC0_DBG_0 + macro_index * macro_offset]
+ + mmSPMU_PMINTENCLR_EL1_OFFSET, 0x1);
+ WREG32(debug_spmu_regs[GAUDI2_SPMU_NIC0_DBG_1 + macro_index * macro_offset]
+ + mmSPMU_PMINTENCLR_EL1_OFFSET, 0x1);
+
+ macro_offset = GAUDI2_BMON_NIC1_DBG_0_0 - GAUDI2_BMON_NIC0_DBG_0_0;
+ WREG32(debug_bmon_regs[GAUDI2_BMON_NIC0_DBG_0_0 + macro_index * macro_offset]
+ + mmBMON_INT_CLR_OFFSET, 0x1);
+ WREG32(debug_bmon_regs[GAUDI2_BMON_NIC0_DBG_1_0 + macro_index * macro_offset]
+ + mmBMON_INT_CLR_OFFSET, 0x1);
+ WREG32(debug_bmon_regs[GAUDI2_BMON_NIC0_DBG_2_0 + macro_index * macro_offset]
+ + mmBMON_INT_CLR_OFFSET, 0x1);
+ WREG32(debug_bmon_regs[GAUDI2_BMON_NIC0_DBG_0_1 + macro_index * macro_offset]
+ + mmBMON_INT_CLR_OFFSET, 0x1);
+ WREG32(debug_bmon_regs[GAUDI2_BMON_NIC0_DBG_1_1 + macro_index * macro_offset]
+ + mmBMON_INT_CLR_OFFSET, 0x1);
+ WREG32(debug_bmon_regs[GAUDI2_BMON_NIC0_DBG_2_1 + macro_index * macro_offset]
+ + mmBMON_INT_CLR_OFFSET, 0x1);
+}
+
+static int gaudi2_handle_nic_sw_error_event(struct hl_device *hdev, u16 event_type, u8 macro_index,
+ struct hl_eq_nic_intr_cause *nic_intr_cause)
+{
+ u32 error_count;
+
+ error_count = gaudi2_cn_handle_sw_error_event(hdev, event_type, macro_index,
+ nic_intr_cause);
+
+ hl_check_for_glbl_errors(hdev);
+
+ return error_count;
+}
+
static void handle_lower_qman_data_on_err(struct hl_device *hdev, u64 qman_base, u32 engine_id)
{
struct undefined_opcode_info *undef_opcode = &hdev->captured_err_info.undef_opcode;
@@ -8347,6 +8597,22 @@ static void gaudi2_check_if_razwi_happened(struct hl_device *hdev)
gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_ROT, mod_idx, 0, NULL);
}
+static int gaudi2_handle_nic_axi_error_response_event(struct hl_device *hdev, u16 event_type,
+ u8 macro_index, struct hl_eq_nic_intr_cause *nic_intr_cause,
+ u64 *event_mask)
+{
+ u32 error_count = 0;
+
+ error_count = gaudi2_cn_handle_axi_error_response_event(hdev, event_type, macro_index,
+ nic_intr_cause);
+
+ /* check if RAZWI happened */
+ gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_NIC, macro_index, 0, event_mask);
+ hl_check_for_glbl_errors(hdev);
+
+ return error_count;
+}
+
static int gaudi2_psoc_razwi_get_engines(struct gaudi2_razwi_info *razwi_info, u32 array_size,
u32 axuser_xy, u32 *base, u16 *eng_id,
char *eng_name)
@@ -8560,6 +8826,11 @@ static int gaudi2_handle_qm_sei_err(struct hl_device *hdev, u16 event_type,
qman_base = mmROT0_QM_BASE + index * ROT_OFFSET;
module = RAZWI_ROT;
break;
+ case GAUDI2_EVENT_NIC0_AXI_ERROR_RESPONSE ... GAUDI2_EVENT_NIC11_AXI_ERROR_RESPONSE:
+ index = event_type - GAUDI2_EVENT_NIC0_AXI_ERROR_RESPONSE;
+ qman_base = mmNIC0_QM0_BASE + index * NIC_OFFSET;
+ module = RAZWI_NIC;
+ break;
default:
return 0;
}
@@ -8684,6 +8955,13 @@ static int gaudi2_handle_qman_err(struct hl_device *hdev, u16 event_type, u64 *e
qid_base = GAUDI2_QUEUE_ID_ROT_1_0;
qman_base = mmROT1_QM_BASE;
break;
+ case GAUDI2_EVENT_NIC0_QM0 ... GAUDI2_EVENT_NIC11_QM1:
+ index = event_type - GAUDI2_EVENT_NIC0_QM0;
+ qid_base = GAUDI2_QUEUE_ID_NIC_0_0 + index * QMAN_STREAMS;
+ qman_base = mmNIC0_QM0_BASE +
+ (index / NIC_NUMBER_OF_QM_PER_MACRO) * NIC_OFFSET +
+ (index % NIC_NUMBER_OF_QM_PER_MACRO) * NIC_QM_OFFSET;
+ break;
default:
return 0;
}
@@ -10176,6 +10454,25 @@ static void gaudi2_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_ent
event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
break;
+ case GAUDI2_EVENT_NIC0_BMON_SPMU:
+ case GAUDI2_EVENT_NIC1_BMON_SPMU:
+ case GAUDI2_EVENT_NIC2_BMON_SPMU:
+ case GAUDI2_EVENT_NIC3_BMON_SPMU:
+ case GAUDI2_EVENT_NIC4_BMON_SPMU:
+ case GAUDI2_EVENT_NIC5_BMON_SPMU:
+ case GAUDI2_EVENT_NIC6_BMON_SPMU:
+ case GAUDI2_EVENT_NIC7_BMON_SPMU:
+ case GAUDI2_EVENT_NIC8_BMON_SPMU:
+ case GAUDI2_EVENT_NIC9_BMON_SPMU:
+ case GAUDI2_EVENT_NIC10_BMON_SPMU:
+ case GAUDI2_EVENT_NIC11_BMON_SPMU:
+ index = (event_type - GAUDI2_EVENT_NIC0_BMON_SPMU) /
+ (GAUDI2_EVENT_NIC1_BMON_SPMU - GAUDI2_EVENT_NIC0_BMON_SPMU);
+ gaudi2_handle_bmon_spmu_event(hdev, index);
+ error_count = GAUDI2_NA_EVENT_CAUSE;
+ event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+ break;
+
case GAUDI2_EVENT_CPU_FIX_POWER_ENV_S:
case GAUDI2_EVENT_CPU_FIX_POWER_ENV_E:
case GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_S:
@@ -10213,6 +10510,33 @@ static void gaudi2_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_ent
event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
break;
+ case GAUDI2_EVENT_NIC0_AXI_ERROR_RESPONSE ... GAUDI2_EVENT_NIC11_AXI_ERROR_RESPONSE:
+ index = (event_type - GAUDI2_EVENT_NIC0_AXI_ERROR_RESPONSE);
+ error_count = gaudi2_handle_nic_axi_error_response_event(hdev, event_type, index,
+ &eq_entry->nic_intr_cause, &event_mask);
+ error_count += gaudi2_handle_qm_sei_err(hdev, event_type, false, &event_mask);
+ event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+ break;
+
+ case GAUDI2_EVENT_NIC0_SW_ERROR:
+ case GAUDI2_EVENT_NIC1_SW_ERROR:
+ case GAUDI2_EVENT_NIC2_SW_ERROR:
+ case GAUDI2_EVENT_NIC3_SW_ERROR:
+ case GAUDI2_EVENT_NIC4_SW_ERROR:
+ case GAUDI2_EVENT_NIC5_SW_ERROR:
+ case GAUDI2_EVENT_NIC6_SW_ERROR:
+ case GAUDI2_EVENT_NIC7_SW_ERROR:
+ case GAUDI2_EVENT_NIC8_SW_ERROR:
+ case GAUDI2_EVENT_NIC9_SW_ERROR:
+ case GAUDI2_EVENT_NIC10_SW_ERROR:
+ case GAUDI2_EVENT_NIC11_SW_ERROR:
+ index = (event_type - GAUDI2_EVENT_NIC0_SW_ERROR) /
+ (GAUDI2_EVENT_NIC1_SW_ERROR - GAUDI2_EVENT_NIC0_SW_ERROR);
+ error_count = gaudi2_handle_nic_sw_error_event(hdev, event_type, index,
+ &eq_entry->nic_intr_cause);
+ event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+ break;
+
case GAUDI2_EVENT_CPU_CPLD_SHUTDOWN_CAUSE:
dev_info(hdev->dev, "CPLD shutdown cause, reset reason: 0x%llx\n",
le64_to_cpu(eq_entry->data[0]));
@@ -10233,6 +10557,11 @@ static void gaudi2_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_ent
event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
break;
+ case GAUDI2_EVENT_CPU0_STATUS_NIC0_ENG0 ... GAUDI2_EVENT_CPU11_STATUS_NIC11_ENG1:
+ hl_cn_send_status(hdev, event_type - GAUDI2_EVENT_CPU0_STATUS_NIC0_ENG0, 0, 0);
+ error_count = GAUDI2_NA_EVENT_CAUSE;
+ break;
+
case GAUDI2_EVENT_ARC_DCCM_FULL:
error_count = hl_arc_event_handle(hdev, event_type, &eq_entry->arc_data);
event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
@@ -11510,6 +11839,54 @@ static u32 *gaudi2_get_stream_master_qid_arr(void)
return NULL;
}
+static void gaudi2_update_nic_qmans_state(struct hl_device *hdev)
+{
+ struct gaudi2_device *gaudi2 = hdev->asic_specific;
+ u32 nic_mask, queue_id;
+ int nic_id;
+
+ queue_id = GAUDI2_QUEUE_ID_NIC_0_0;
+
+ for (nic_id = 0 ; nic_id < NIC_NUMBER_OF_ENGINES;
+ nic_id++, queue_id += NUM_OF_PQ_PER_QMAN) {
+
+ nic_mask = BIT(HW_CAP_NIC_SHIFT + nic_id);
+
+ /* We need to stop and disable the QMAN in case we already
+ * initialized it AND the firmware reported that the matching
+ * NIC is disabled
+ */
+ if ((gaudi2->nic_hw_cap_initialized & nic_mask) &&
+ (!(hdev->cn.ports_mask & BIT(nic_id)))) {
+
+ gaudi2_stop_qman_common(hdev, gaudi2_qm_blocks_bases[queue_id]);
+ gaudi2_disable_qman_common(hdev, gaudi2_qm_blocks_bases[queue_id]);
+
+ /* Remove that capability bit so no one would be able
+ * to submit to that NIC's QMAN
+ */
+ gaudi2->nic_hw_cap_initialized &= ~nic_mask;
+ }
+ }
+}
+
+static int gaudi2_cn_init(struct hl_device *hdev)
+{
+ int rc;
+
+ rc = hl_cn_init(hdev);
+ if (rc)
+ return rc;
+
+ /* After ports initialization (for the first time), we need to check
+ * whether the f/w reported on ports that are disabled. For those
+ * ports, we need to disable their QMANs and update the HW_CAP bits
+ */
+ gaudi2_update_nic_qmans_state(hdev);
+
+ return 0;
+}
+
static void gaudi2_add_device_attr(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp,
struct attribute_group *dev_vrm_attr_grp)
{
@@ -11590,6 +11967,17 @@ static void gaudi2_write_pte(struct hl_device *hdev, u64 addr, u64 val)
writeq(val, hdev->pcie_bar[DRAM_BAR_ID] + (addr - gaudi2->dram_bar_cur_addr));
}
+static int gaudi2_get_reg_pcie_addr(struct hl_device *hdev, u32 reg, u64 *pci_addr)
+{
+ u64 offset = CFG_BASE - STM_FLASH_BASE_ADDR + reg;
+
+ if (pci_resource_len(hdev->pdev, SRAM_CFG_BAR_ID) < offset)
+ return -EINVAL;
+
+ *pci_addr = offset;
+ return 0;
+}
+
static const struct hl_asic_funcs gaudi2_funcs = {
.early_init = gaudi2_early_init,
.early_fini = gaudi2_early_fini,
@@ -11641,10 +12029,13 @@ static const struct hl_asic_funcs gaudi2_funcs = {
.get_eeprom_data = gaudi2_get_eeprom_data,
.get_monitor_dump = gaudi2_get_monitor_dump,
.send_cpu_message = gaudi2_send_cpu_message,
+ .cn_init = gaudi2_cn_init,
+ .cn_fini = hl_cn_fini,
.pci_bars_map = gaudi2_pci_bars_map,
.init_iatu = gaudi2_init_iatu,
.rreg = hl_rreg,
.wreg = hl_wreg,
+ .get_reg_pcie_addr = gaudi2_get_reg_pcie_addr,
.halt_coresight = gaudi2_halt_coresight,
.ctx_init = gaudi2_ctx_init,
.ctx_fini = gaudi2_ctx_fini,
@@ -11679,6 +12070,7 @@ static const struct hl_asic_funcs gaudi2_funcs = {
.get_sob_addr = &gaudi2_get_sob_addr,
.set_pci_memory_regions = gaudi2_set_pci_memory_regions,
.get_stream_master_qid_arr = gaudi2_get_stream_master_qid_arr,
+ .cn_funcs = &gaudi2_cn_funcs,
.check_if_razwi_happened = gaudi2_check_if_razwi_happened,
.mmu_get_real_page_size = gaudi2_mmu_get_real_page_size,
.access_dev_mem = hl_access_dev_mem,
diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2P.h b/drivers/accel/habanalabs/gaudi2/gaudi2P.h
index eee41387b269..429e89703e36 100644
--- a/drivers/accel/habanalabs/gaudi2/gaudi2P.h
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2P.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright 2020-2022 HabanaLabs, Ltd.
+ * Copyright 2020-2024 HabanaLabs, Ltd.
* All Rights Reserved.
*
*/
@@ -8,12 +8,15 @@
#ifndef GAUDI2P_H_
#define GAUDI2P_H_
+#include <linux/net/intel/cn_aux.h>
+#include <linux/net/intel/gaudi2_aux.h>
#include <uapi/drm/habanalabs_accel.h>
#include "../common/habanalabs.h"
#include <linux/habanalabs/hl_boot_if.h>
#include "../include/gaudi2/gaudi2.h"
#include "../include/gaudi2/gaudi2_packets.h"
#include "../include/gaudi2/gaudi2_fw_if.h"
+#include "../include/gaudi2/gaudi2_coresight.h"
#include "../include/gaudi2/gaudi2_async_events.h"
#define GAUDI2_LINUX_FW_FILE "habanalabs/gaudi2/gaudi2-fit.itb"
@@ -86,7 +89,7 @@
#define GAUDI2_BOOT_FIT_REQ_TIMEOUT_USEC 10000000 /* 10s */
-#define GAUDI2_NIC_CLK_FREQ 450000000ull /* 450 MHz */
+#define GAUDI2_NIC_CLK_FREQ 488000000ull /* 488 MHz */
#define DC_POWER_DEFAULT 60000 /* 60W */
@@ -198,6 +201,7 @@
HW_CAP_HBM_SCRAMBLER_SW_RESET)
#define HW_CAP_HBM_SCRAMBLER_SHIFT 41
#define HW_CAP_RESERVED BIT(43)
+#define HW_CAP_NIC_DRV BIT(44)
#define HW_CAP_MMU_MASK (HW_CAP_PMMU | HW_CAP_DMMU_MASK)
/* Range Registers */
@@ -239,6 +243,8 @@
#define GAUDI2_NUM_TESTED_QS (GAUDI2_QUEUE_ID_CPU_PQ - GAUDI2_QUEUE_ID_PDMA_0_0)
+extern u64 debug_bmon_regs[GAUDI2_BMON_LAST + 1];
+extern u64 debug_spmu_regs[GAUDI2_SPMU_LAST + 1];
enum gaudi2_reserved_sob_id {
GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST,
@@ -251,6 +257,9 @@ enum gaudi2_reserved_sob_id {
GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST,
GAUDI2_RESERVED_SOB_DEC_ABNRM_LAST =
GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + NUMBER_OF_DEC - 1,
+ GAUDI2_RESERVED_SOB_NIC_PORT_FIRST,
+ GAUDI2_RESERVED_SOB_NIC_PORT_LAST =
+ GAUDI2_RESERVED_SOB_NIC_PORT_FIRST + NIC_NUMBER_OF_PORTS - 1,
GAUDI2_RESERVED_SOB_NUMBER
};
@@ -265,6 +274,9 @@ enum gaudi2_reserved_mon_id {
GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST,
GAUDI2_RESERVED_MON_DEC_ABNRM_LAST =
GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST + 3 * NUMBER_OF_DEC - 1,
+ GAUDI2_RESERVED_MON_NIC_PORT_FIRST,
+ GAUDI2_RESERVED_MON_NIC_PORT_LAST =
+ GAUDI2_RESERVED_MON_NIC_PORT_FIRST + 3 * NIC_NUMBER_OF_PORTS - 1,
GAUDI2_RESERVED_MON_NUMBER
};
@@ -513,13 +525,8 @@ struct gaudi2_queues_test_info {
* @events_stat: array that holds histogram of all received events.
* @events_stat_aggregate: same as events_stat but doesn't get cleared on reset.
* @num_of_valid_hw_events: used to hold the number of valid H/W events.
- * @nic_ports: array that holds all NIC ports manage structures.
- * @nic_macros: array that holds all NIC macro manage structures.
- * @core_info: core info to be used by the Ethernet driver.
- * @aux_ops: functions for core <-> aux drivers communication.
- * @flush_db_fifo: flag to force flush DB FIFO after a write.
- * @hbm_cfg: HBM subsystem settings
- * @hw_queues_lock_mutex: used by simulator instead of hw_queues_lock.
+ * @cn_aux_ops: functions for core <-> accel drivers communication.
+ * @cn_aux_data: data to be used by the core driver.
* @queues_test_info: information used by the driver when testing the HW queues.
*/
struct gaudi2_device {
@@ -549,6 +556,10 @@ struct gaudi2_device {
u32 events_stat_aggregate[GAUDI2_EVENT_SIZE];
u32 num_of_valid_hw_events;
+ /* NIC fields */
+ struct gaudi2_cn_aux_ops cn_aux_ops;
+ struct gaudi2_cn_aux_data cn_aux_data;
+
/* Queue testing */
struct gaudi2_queues_test_info queues_test_info[GAUDI2_NUM_TESTED_QS];
};
@@ -588,6 +599,7 @@ enum gaudi2_block_types {
GAUDI2_BLOCK_TYPE_MAX
};
+extern struct hl_cn_funcs gaudi2_cn_funcs;
extern const u32 gaudi2_dma_core_blocks_bases[DMA_CORE_ID_SIZE];
extern const u32 gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_SIZE];
extern const u32 gaudi2_mme_acc_blocks_bases[MME_ID_SIZE];
@@ -609,4 +621,15 @@ int gaudi2_init_security(struct hl_device *hdev);
void gaudi2_ack_protection_bits_errors(struct hl_device *hdev);
int gaudi2_send_device_activity(struct hl_device *hdev, bool open);
+/* Functions exported for NIC */
+void gaudi2_cn_spmu_get_stats_info(struct hl_device *hdev, u32 port, struct hbl_cn_stat **stats,
+ u32 *n_stats);
+int gaudi2_cn_spmu_config(struct hl_device *hdev, u32 port, u32 num_event_types, u32 event_types[],
+ bool enable);
+int gaudi2_cn_spmu_sample(struct hl_device *hdev, u32 port, u32 num_out_data, u64 out_data[]);
+void gaudi2_cn_disable_interrupts(struct hl_device *hdev);
+void gaudi2_cn_quiescence(struct hl_device *hdev);
+void gaudi2_cn_compute_reset_prepare(struct hl_device *hdev);
+void gaudi2_cn_compute_reset_late_init(struct hl_device *hdev);
+
#endif /* GAUDI2P_H_ */
diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_cn.c b/drivers/accel/habanalabs/gaudi2/gaudi2_cn.c
new file mode 100644
index 000000000000..9beb11b579e4
--- /dev/null
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2_cn.c
@@ -0,0 +1,424 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2020-2022 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ */
+
+#include "gaudi2_cn.h"
+#include "../include/gaudi2/asic_reg/gaudi2_regs.h"
+#include "../include/gaudi2/gaudi2_async_ids_map_extended.h"
+#include "../include/hw_ip/nic/nic_general.h"
+
+static bool gaudi2_cn_get_hw_cap(struct hl_device *hdev);
+
+int gaudi2_cn_handle_sw_error_event(struct hl_device *hdev, u16 event_type, u8 macro_index,
+ struct hl_eq_nic_intr_cause *nic_intr_cause)
+{
+ struct hbl_aux_dev *aux_dev = &hdev->cn.cn_aux_dev;
+ struct gaudi2_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_cn_aux_ops *aux_ops = &gaudi2->cn_aux_ops;
+ u32 error_count = 0;
+
+ if (aux_ops->sw_err_event_handler)
+ error_count = aux_ops->sw_err_event_handler(aux_dev, event_type, macro_index,
+ nic_intr_cause);
+
+ return error_count;
+}
+
+int gaudi2_cn_handle_axi_error_response_event(struct hl_device *hdev, u16 event_type,
+ u8 macro_index,
+ struct hl_eq_nic_intr_cause *nic_intr_cause)
+{
+ struct hbl_aux_dev *aux_dev = &hdev->cn.cn_aux_dev;
+ struct gaudi2_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_cn_aux_ops *aux_ops = &gaudi2->cn_aux_ops;
+ u32 error_count = 0;
+
+ if (aux_ops->axi_error_response_event_handler)
+ error_count = aux_ops->axi_error_response_event_handler(aux_dev, event_type,
+ macro_index,
+ nic_intr_cause);
+
+ return error_count;
+}
+
+/**
+ * gaudi2_cn_disable_interrupts() - Disable interrupts of all ports.
+ * Gaudi2 CN interrupts are enabled by default, need to disable them ASAP
+ * before ports init and after hard reset.
+ *
+ * @hdev: habanalabs device structure.
+ */
+void gaudi2_cn_disable_interrupts(struct hl_device *hdev)
+{
+ u32 port;
+
+ if (!hdev->cn.ports_mask)
+ return;
+
+ /* we only need the port number for NIC_WREG32 */
+ for (port = 0 ; port < NIC_NUMBER_OF_PORTS ; port++) {
+ NIC_WREG32(mmNIC0_QPC0_EVENT_QUE_CFG, 0);
+ NIC_WREG32(mmNIC0_QPC0_INTERRUPT_EN, 0);
+ NIC_WREG32(mmNIC0_QPC0_INTERRUPT_MASK, 0xFFFFFFFF);
+
+ /* This registers needs to be configured only in case of PLDM */
+ if (hdev->pldm) {
+ NIC_WREG32(mmNIC0_QPC0_INTERRUPT_RESP_ERR_MASK, 0xFFFFFFFF);
+ NIC_WREG32(mmNIC0_TXE0_INTERRUPT_MASK, 0xFFFFFFFF);
+ NIC_WREG32(mmNIC0_RXE0_SPI_INTR_MASK, 0xFFFFFFFF);
+ NIC_WREG32(mmNIC0_RXE0_SEI_INTR_MASK, 0xFFFFFFFF);
+ NIC_WREG32(mmNIC0_TXS0_INTERRUPT_MASK, 0xFFFFFFFF);
+ }
+
+ /* WA for H/W bug H6-3339 - mask the link UP interrupt */
+ NIC_MACRO_WREG32(mmNIC0_PHY_PHY_LINK_STS_INTR, 0x1);
+ }
+
+ /* flush */
+ port = 0;
+ NIC_RREG32(mmNIC0_QPC0_EVENT_QUE_CFG);
+}
+
+/**
+ * gaudi2_cn_quiescence() - make sure that NIC does not generate events nor
+ * receives traffic.
+ * Gaudi2 default values at power-up and after hard-reset are interrupts enabled
+ * and Rx enabled, we need to disable them until driver configuration is
+ * complete.
+ *
+ * @hdev: habanalabs device structure.
+ */
+void gaudi2_cn_quiescence(struct hl_device *hdev)
+{
+ /*
+ * Do not quiescence the ports during device release
+ * reset aka soft reset flow.
+ */
+ if (gaudi2_cn_get_hw_cap(hdev))
+ return;
+
+ dev_dbg(hdev->dev, "Quiescence the NICs\n");
+
+ gaudi2_cn_disable_interrupts(hdev);
+}
+
+static bool gaudi2_cn_get_hw_cap(struct hl_device *hdev)
+{
+ struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+ return (gaudi2->hw_cap_initialized & HW_CAP_NIC_DRV);
+}
+
+static void gaudi2_cn_set_hw_cap(struct hl_device *hdev, bool enable)
+{
+ struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+ if (enable)
+ gaudi2->hw_cap_initialized |= HW_CAP_NIC_DRV;
+ else
+ gaudi2->hw_cap_initialized &= ~HW_CAP_NIC_DRV;
+}
+
+/**
+ * gaudi2_cn_override_ports_ext_mask() - Set the external ports mask.
+ * @hdev: Hl device whose external ports mask to return.
+ * @ports_ext_mask: Out, the external ports mask.
+ */
+static void gaudi2_cn_override_ports_ext_mask(struct hl_device *hdev, uint64_t *ports_ext_mask)
+{
+ /* For asic type GAUDI2B, the external ports mask shouldn't be changed */
+ if (hdev->asic_type == ASIC_GAUDI2B) {
+ *ports_ext_mask = hdev->cn.ports_ext_mask;
+ return;
+ }
+
+ /* If we are running on a PCI card, all the ports should be set as external */
+ if (hdev->card_type == cpucp_card_type_pci) {
+ *ports_ext_mask = hdev->cn.ports_mask;
+ return;
+ }
+
+ /* For HLS2 setup type, the external ports mask shouldn't be changed */
+ *ports_ext_mask = hdev->cn.ports_ext_mask;
+}
+
+static int gaudi2_cn_check_oui_prefix_validity(u8 *mac_addr)
+{
+ u8 mac[ETH_ALEN];
+ int i;
+
+ for (i = 0 ; i < 3 ; i++)
+ mac[i] = HABANALABS_MAC_OUI_1 >> (8 * (2 - i));
+
+ if (!strncmp(mac, mac_addr, 3))
+ return 1;
+
+ for (i = 0 ; i < 3 ; i++)
+ mac[i] = HABANALABS_MAC_OUI_2 >> (8 * (2 - i));
+
+ if (!strncmp(mac, mac_addr, 3))
+ return 1;
+
+ return 0;
+}
+
+int gaudi2_cn_set_info(struct hl_device *hdev, bool get_from_fw)
+{
+ struct hbl_cn_cpucp_info *cn_cpucp_info = &hdev->asic_prop.cn_props.cpucp_info;
+ struct cpucp_info *cpucp_info = &hdev->asic_prop.cpucp_info;
+ struct hbl_cn_cpucp_mac_addr *mac_arr = cn_cpucp_info->mac_addrs;
+ struct hl_cn *cn = &hdev->cn;
+ u32 serdes_type = MAX_NUM_SERDES_TYPE;
+ u8 mac[ETH_ALEN], *mac_addr;
+ int rc, i;
+
+ /* copy the MAC OUI in reverse */
+ for (i = 0 ; i < 3 ; i++)
+ mac[i] = HABANALABS_MAC_OUI_1 >> (8 * (2 - i));
+
+ if (get_from_fw) {
+ rc = hl_cn_cpucp_info_get(hdev);
+ if (rc)
+ return rc;
+
+ cn->ports_mask &= cn_cpucp_info->link_mask[0];
+ cn->ports_ext_mask &= cn_cpucp_info->link_ext_mask[0];
+ cn->auto_neg_mask &= cn_cpucp_info->auto_neg_mask[0];
+
+ serdes_type = cn_cpucp_info->serdes_type;
+
+ /* check for invalid MAC addresses from F/W (bad OUI) */
+ for (i = 0 ; i < NIC_NUMBER_OF_PORTS ; i++) {
+ if (!(cn->ports_mask & BIT(i)))
+ continue;
+
+ mac_addr = mac_arr[i].mac_addr;
+ if (!gaudi2_cn_check_oui_prefix_validity(mac_addr))
+ dev_warn(hdev->dev, "unrecognized MAC OUI %pM, port %d\n",
+ mac_addr, i);
+ }
+
+ cn->card_location = le32_to_cpu(cpucp_info->card_location);
+ cn->use_fw_serdes_info = true;
+ } else {
+ /* No F/W, hence need to set the MACs manually (randomize) */
+ get_random_bytes(&mac[3], 2);
+
+ for (i = 0 ; i < NIC_NUMBER_OF_PORTS ; i++) {
+ if (!(cn->ports_mask & BIT(i)))
+ continue;
+
+ mac[ETH_ALEN - 1] = i;
+ memcpy(mac_arr[i].mac_addr, mac, ETH_ALEN);
+ }
+
+ dev_warn(hdev->dev, "can't read card location as FW security is enabled\n");
+ }
+
+ switch (serdes_type) {
+ case HLS2_SERDES_TYPE:
+ hdev->asic_prop.server_type = HL_SERVER_GAUDI2_HLS2;
+ break;
+ case HLS2_TYPE_1_SERDES_TYPE:
+ hdev->asic_prop.server_type = HL_SERVER_GAUDI2_TYPE1;
+ break;
+ default:
+ hdev->asic_prop.server_type = HL_SERVER_TYPE_UNKNOWN;
+
+ if (get_from_fw) {
+ dev_err(hdev->dev, "bad SerDes type %d\n", serdes_type);
+ return -EFAULT;
+ }
+ break;
+ }
+
+ /* If we are running on non HLS2 setup or a PCI card, all the ports should be set as
+ * external (the only exception is when the asic type is GADUI2B).
+ */
+ if (hdev->card_type == cpucp_card_type_pci) {
+ if (hdev->asic_type != ASIC_GAUDI2B)
+ cn->ports_ext_mask = cn->ports_mask;
+
+ cn->auto_neg_mask &= ~cn->ports_ext_mask;
+ }
+
+ gaudi2_cn_override_ports_ext_mask(hdev, &cn->ports_ext_mask);
+
+ if (hdev->card_type == cpucp_card_type_pci)
+ cn->auto_neg_mask &= ~cn->ports_ext_mask;
+
+ /* Disable ANLT on NIC 0 ports (due to lane swapping) */
+ cn->auto_neg_mask &= ~0x3;
+
+ cn->lanes_per_port = 2;
+ cn->load_fw = false;
+ cn->eth_on_internal = false;
+
+ return 0;
+}
+
+static int gaudi2_cn_pre_core_init(struct hl_device *hdev)
+{
+ return 0;
+}
+
+static char *gaudi2_cn_get_event_name(struct hbl_aux_dev *aux_dev, u16 event_type)
+{
+ return gaudi2_irq_map_table[event_type].valid ? gaudi2_irq_map_table[event_type].name :
+ "N/A Event";
+}
+
+static int gaudi2_cn_poll_mem(struct hbl_aux_dev *aux_dev, u32 *addr, u32 *val,
+ hbl_cn_poll_cond_func func)
+{
+ return hl_poll_timeout_memory(hdev, addr, *val, func(*val, NULL), 10,
+ HL_DEVICE_TIMEOUT_USEC, true);
+}
+
+static void *gaudi2_cn_dma_alloc_coherent(struct hbl_aux_dev *aux_dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t flag)
+{
+ return hl_cn_dma_alloc_coherent(aux_dev, size, dma_handle, flag);
+}
+
+static void gaudi2_cn_dma_free_coherent(struct hbl_aux_dev *aux_dev, size_t size, void *cpu_addr,
+ dma_addr_t dma_handle)
+{
+ hl_cn_dma_free_coherent(aux_dev, size, cpu_addr, dma_handle);
+}
+
+static void *gaudi2_cn_dma_pool_zalloc(struct hbl_aux_dev *aux_dev, size_t size, gfp_t mem_flags,
+ dma_addr_t *dma_handle)
+{
+ return hl_cn_dma_pool_zalloc(aux_dev, size, mem_flags, dma_handle);
+}
+
+static void gaudi2_cn_dma_pool_free(struct hbl_aux_dev *aux_dev, void *vaddr, dma_addr_t dma_addr)
+{
+ hl_cn_dma_pool_free(aux_dev, vaddr, dma_addr);
+}
+
+static void gaudi2_cn_set_cn_data(struct hl_device *hdev)
+{
+ struct gaudi2_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_cn_aux_data *gaudi2_aux_data;
+ struct gaudi2_cn_aux_ops *gaudi2_aux_ops;
+ struct hbl_cn_aux_data *aux_data;
+ struct hbl_cn_aux_ops *aux_ops;
+ struct hl_cn *cn = &hdev->cn;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = &cn->cn_aux_dev;
+ aux_data = aux_dev->aux_data;
+ gaudi2_aux_data = &gaudi2->cn_aux_data;
+ aux_data->asic_specific = gaudi2_aux_data;
+ aux_ops = aux_dev->aux_ops;
+ gaudi2_aux_ops = &gaudi2->cn_aux_ops;
+ aux_ops->asic_ops = gaudi2_aux_ops;
+
+ gaudi2_aux_data->cfg_base = CFG_BASE;
+ gaudi2_aux_data->fw_security_enabled = hdev->asic_prop.fw_security_enabled;
+ gaudi2_aux_data->msix_enabled = !!(gaudi2->hw_cap_initialized & HW_CAP_MSIX);
+ gaudi2_aux_data->irq_num_port_base = GAUDI2_IRQ_NUM_NIC_PORT_FIRST;
+ gaudi2_aux_data->sob_id_base = GAUDI2_RESERVED_SOB_NIC_PORT_FIRST;
+ gaudi2_aux_data->sob_inc_cfg_val = GAUDI2_SOB_INCREMENT_BY_ONE;
+ gaudi2_aux_data->setup_type = GAUDI2_SETUP_TYPE_HLS2;
+
+ /* cn2accel */
+ gaudi2_aux_ops->get_event_name = gaudi2_cn_get_event_name;
+ gaudi2_aux_ops->poll_mem = gaudi2_cn_poll_mem;
+ gaudi2_aux_ops->dma_alloc_coherent = gaudi2_cn_dma_alloc_coherent;
+ gaudi2_aux_ops->dma_free_coherent = gaudi2_cn_dma_free_coherent;
+ gaudi2_aux_ops->dma_pool_zalloc = gaudi2_cn_dma_pool_zalloc;
+ gaudi2_aux_ops->dma_pool_free = gaudi2_cn_dma_pool_free;
+ gaudi2_aux_ops->spmu_get_stats_info = hl_cn_spmu_get_stats_info;
+ gaudi2_aux_ops->spmu_config = hl_cn_spmu_config;
+ gaudi2_aux_ops->spmu_sample = hl_cn_spmu_sample;
+ gaudi2_aux_ops->poll_reg = hl_cn_poll_reg;
+ gaudi2_aux_ops->send_cpu_message = hl_cn_send_cpu_message;
+ gaudi2_aux_ops->post_send_status = hl_cn_post_send_status;
+}
+
+void gaudi2_cn_compute_reset_prepare(struct hl_device *hdev)
+{
+ struct gaudi2_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_cn_aux_ops *gaudi2_aux_ops;
+ struct hl_cn *cn = &hdev->cn;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = &cn->cn_aux_dev;
+ gaudi2_aux_ops = &gaudi2->cn_aux_ops;
+
+ if (gaudi2_aux_ops->reset_prepare)
+ gaudi2_aux_ops->reset_prepare(aux_dev);
+}
+
+void gaudi2_cn_compute_reset_late_init(struct hl_device *hdev)
+{
+ struct gaudi2_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_cn_aux_ops *gaudi2_aux_ops;
+ struct hl_cn *cn = &hdev->cn;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = &cn->cn_aux_dev;
+ gaudi2_aux_ops = &gaudi2->cn_aux_ops;
+
+ if (gaudi2_aux_ops->reset_late_init)
+ gaudi2_aux_ops->reset_late_init(aux_dev);
+}
+
+static void gaudi2_cn_post_send_status(struct hl_device *hdev, u32 port)
+{
+ hl_fw_unmask_irq(hdev, GAUDI2_EVENT_CPU0_STATUS_NIC0_ENG0 + port);
+}
+
+static void gaudi2_cn_ports_stop_prepare(struct hl_device *hdev, bool fw_reset, bool in_teardown)
+{
+ struct gaudi2_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_cn_aux_ops *gaudi2_aux_ops;
+ struct hl_cn *cn = &hdev->cn;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = &cn->cn_aux_dev;
+ gaudi2_aux_ops = &gaudi2->cn_aux_ops;
+
+ if (gaudi2_aux_ops->ports_stop_prepare)
+ gaudi2_aux_ops->ports_stop_prepare(aux_dev, fw_reset, in_teardown);
+}
+
+static int gaudi2_cn_send_port_cpucp_status(struct hl_device *hdev, u32 port, u8 cmd, u8 period)
+{
+ struct gaudi2_device *gaudi2 = hdev->asic_specific;
+ struct gaudi2_cn_aux_ops *gaudi2_aux_ops;
+ struct hl_cn *cn = &hdev->cn;
+ struct hbl_aux_dev *aux_dev;
+
+ aux_dev = &cn->cn_aux_dev;
+ gaudi2_aux_ops = &gaudi2->cn_aux_ops;
+
+ if (gaudi2_aux_ops->send_port_cpucp_status)
+ return gaudi2_aux_ops->send_port_cpucp_status(aux_dev, port, cmd, period);
+
+ return -ENODEV;
+}
+
+static struct hl_cn_port_funcs gaudi2_cn_port_funcs = {
+ .spmu_get_stats_info = gaudi2_cn_spmu_get_stats_info,
+ .spmu_config = gaudi2_cn_spmu_config,
+ .spmu_sample = gaudi2_cn_spmu_sample,
+ .post_send_status = gaudi2_cn_post_send_status,
+ .ports_stop_prepare = gaudi2_cn_ports_stop_prepare,
+ .send_port_cpucp_status = gaudi2_cn_send_port_cpucp_status,
+};
+
+struct hl_cn_funcs gaudi2_cn_funcs = {
+ .get_hw_cap = gaudi2_cn_get_hw_cap,
+ .set_hw_cap = gaudi2_cn_set_hw_cap,
+ .pre_core_init = gaudi2_cn_pre_core_init,
+ .set_cn_data = gaudi2_cn_set_cn_data,
+ .port_funcs = &gaudi2_cn_port_funcs,
+};
diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_cn.h b/drivers/accel/habanalabs/gaudi2/gaudi2_cn.h
new file mode 100644
index 000000000000..dbc8ede23779
--- /dev/null
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2_cn.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2024 HabanaLabs, Ltd.
+ * Copyright (C) 2023-2024, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI2_CN_H_
+#define GAUDI2_CN_H_
+
+#include "gaudi2P.h"
+#include "../include/gaudi2/asic_reg/gaudi2_regs.h"
+
+#define NIC_MAX_RC_MTU SZ_8K
+/* This is the max frame length the H/W supports (Tx/Rx) */
+#define NIC_MAX_RDMA_HDRS 128
+#define NIC_MAX_FRM_LEN (NIC_MAX_RC_MTU + NIC_MAX_RDMA_HDRS)
+
+#define NIC_CFG_LO_SIZE (mmNIC0_QPC1_REQ_STATIC_CONFIG - \
+ mmNIC0_QPC0_REQ_STATIC_CONFIG)
+
+#define NIC_CFG_HI_SIZE (mmNIC0_RXE1_CONTROL - mmNIC0_RXE0_CONTROL)
+
+#define NIC_CFG_BASE(port, reg) \
+ ((u64) (NIC_MACRO_CFG_BASE(port) + \
+ ((reg < mmNIC0_RXE0_CONTROL) ? \
+ (NIC_CFG_LO_SIZE * (u64) ((port) & 1)) : \
+ (NIC_CFG_HI_SIZE * (u64) ((port) & 1)))))
+
+#define NIC_RREG32(reg) RREG32(NIC_CFG_BASE(port, (reg)) + (reg))
+#define NIC_WREG32(reg, val) WREG32(NIC_CFG_BASE(port, (reg)) + (reg), (val))
+#define NIC_RMWREG32(reg, val, mask) \
+ RMWREG32(NIC_CFG_BASE(port, reg) + (reg), (val), (mask))
+
+int gaudi2_cn_set_info(struct hl_device *hdev, bool get_from_fw);
+int gaudi2_cn_handle_sw_error_event(struct hl_device *hdev, u16 event_type, u8 macro_index,
+ struct hl_eq_nic_intr_cause *nic_intr_cause);
+int gaudi2_cn_handle_axi_error_response_event(struct hl_device *hdev, u16 event_type,
+ u8 macro_index, struct hl_eq_nic_intr_cause *nic_intr_cause);
+
+#endif /* GAUDI2_CN_H_ */
diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
index 2423620ff358..f7b3692f6bff 100644
--- a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright 2019-2022 HabanaLabs, Ltd.
+ * Copyright 2019-2024 HabanaLabs, Ltd.
* All Rights Reserved.
*/
#include "gaudi2_coresight_regs.h"
@@ -9,6 +9,8 @@
#define GAUDI2_PLDM_CORESIGHT_TIMEOUT_USEC (CORESIGHT_TIMEOUT_USEC * 2000)
#define SPMU_MAX_COUNTERS 6
+/* SPMU should also include overflow_idx and cycle_cnt_idx */
+#define SPMU_DATA_LEN (SPMU_MAX_COUNTERS + 2)
#define COMPONENT_ID_INVALID ((u32)(-1))
#define MAX_BMONS_PER_UNIT 8
@@ -59,6 +61,23 @@ struct component_config_offsets {
u32 bmon_ids[MAX_BMONS_PER_UNIT];
};
+static struct hbl_cn_stat gaudi2_nic0_spmu_stats[] = {
+ {"spmu_req_out_of_range_psn", 17},
+ {"spmu_req_unset_psn", 18},
+ {"spmu_res_duplicate_psn", 20},
+ {"spmu_res_out_of_sequence_psn", 21}
+};
+
+static struct hbl_cn_stat gaudi2_nic1_spmu_stats[] = {
+ {"spmu_req_out_of_range_psn", 5},
+ {"spmu_req_unset_psn", 6},
+ {"spmu_res_duplicate_psn", 8},
+ {"spmu_res_out_of_sequence_psn", 9}
+};
+
+static size_t gaudi2_nic0_spmu_stats_len = ARRAY_SIZE(gaudi2_nic0_spmu_stats);
+static size_t gaudi2_nic1_spmu_stats_len = ARRAY_SIZE(gaudi2_nic1_spmu_stats);
+
static u64 debug_stm_regs[GAUDI2_STM_LAST + 1] = {
[GAUDI2_STM_DCORE0_TPC0_EML] = mmDCORE0_TPC0_EML_STM_BASE,
[GAUDI2_STM_DCORE0_TPC1_EML] = mmDCORE0_TPC1_EML_STM_BASE,
@@ -489,7 +508,7 @@ static u64 debug_funnel_regs[GAUDI2_FUNNEL_LAST + 1] = {
[GAUDI2_FUNNEL_NIC11_DBG_NCH] = mmNIC11_DBG_FUNNEL_NCH_BASE
};
-static u64 debug_bmon_regs[GAUDI2_BMON_LAST + 1] = {
+u64 debug_bmon_regs[GAUDI2_BMON_LAST + 1] = {
[GAUDI2_BMON_DCORE0_TPC0_EML_0] = mmDCORE0_TPC0_EML_BUSMON_0_BASE,
[GAUDI2_BMON_DCORE0_TPC0_EML_1] = mmDCORE0_TPC0_EML_BUSMON_1_BASE,
[GAUDI2_BMON_DCORE0_TPC0_EML_2] = mmDCORE0_TPC0_EML_BUSMON_2_BASE,
@@ -877,7 +896,7 @@ static u64 debug_bmon_regs[GAUDI2_BMON_LAST + 1] = {
[GAUDI2_BMON_NIC11_DBG_2_1] = mmNIC11_DBG_BMON2_1_BASE
};
-static u64 debug_spmu_regs[GAUDI2_SPMU_LAST + 1] = {
+u64 debug_spmu_regs[GAUDI2_SPMU_LAST + 1] = {
[GAUDI2_SPMU_DCORE0_TPC0_EML] = mmDCORE0_TPC0_EML_SPMU_BASE,
[GAUDI2_SPMU_DCORE0_TPC1_EML] = mmDCORE0_TPC1_EML_SPMU_BASE,
[GAUDI2_SPMU_DCORE0_TPC2_EML] = mmDCORE0_TPC2_EML_SPMU_BASE,
@@ -2432,6 +2451,11 @@ static int gaudi2_config_bmon(struct hl_device *hdev, struct hl_debug_params *pa
return 0;
}
+static bool gaudi2_reg_is_nic_spmu(enum gaudi2_debug_spmu_regs_index reg_idx)
+{
+ return reg_idx >= GAUDI2_SPMU_NIC0_DBG_0 && reg_idx <= GAUDI2_SPMU_NIC11_DBG_1;
+}
+
static int gaudi2_config_spmu(struct hl_device *hdev, struct hl_debug_params *params)
{
struct hl_debug_params_spmu *input = params->input;
@@ -2542,6 +2566,121 @@ static int gaudi2_config_spmu(struct hl_device *hdev, struct hl_debug_params *pa
return 0;
}
+static int gaudi2_sample_spmu(struct hl_device *hdev, struct hl_debug_params *params)
+{
+ u32 output_arr_len;
+ u32 events_num;
+ u64 base_reg;
+ u64 *output;
+ int i;
+
+ if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) {
+ dev_err(hdev->dev, "Invalid register index in SPMU\n");
+ return -EINVAL;
+ }
+
+ base_reg = debug_spmu_regs[params->reg_idx];
+
+ /* in case base reg is 0x0 we ignore this configuration */
+ if (!base_reg)
+ return 0;
+
+ output = params->output;
+ output_arr_len = params->output_size / sizeof(u64);
+ events_num = output_arr_len;
+
+ if (output_arr_len < 1) {
+ dev_err(hdev->dev, "not enough values for SPMU sample\n");
+ return -EINVAL;
+ }
+
+ if (events_num > SPMU_MAX_COUNTERS) {
+ dev_err(hdev->dev, "too many events values for SPMU sample\n");
+ return -EINVAL;
+ }
+
+ /* capture */
+ WREG32(base_reg + mmSPMU_PMSCR_OFFSET, 1);
+
+ /* read the shadow registers */
+ for (i = 0 ; i < events_num ; i++)
+ output[i] = RREG32(base_reg + mmSPMU_PMEVCNTSR0_OFFSET + i * 4);
+
+ return 0;
+}
+
+void gaudi2_cn_spmu_get_stats_info(struct hl_device *hdev, u32 port, struct hbl_cn_stat **stats,
+ u32 *n_stats)
+{
+ if (!hdev->supports_coresight) {
+ *n_stats = 0;
+ return;
+ }
+
+ if (port & 1) {
+ *n_stats = gaudi2_nic1_spmu_stats_len;
+ *stats = gaudi2_nic1_spmu_stats;
+ } else {
+ *n_stats = gaudi2_nic0_spmu_stats_len;
+ *stats = gaudi2_nic0_spmu_stats;
+ }
+}
+
+int gaudi2_cn_spmu_config(struct hl_device *hdev, u32 port, u32 num_event_types, u32 event_types[],
+ bool enable)
+{
+ struct hl_debug_params_spmu spmu;
+ struct hl_debug_params params;
+ u64 event_counters[SPMU_DATA_LEN];
+ int i;
+
+ if (!hdev->supports_coresight)
+ return 0;
+
+ /* validate nic port */
+ if (!gaudi2_reg_is_nic_spmu(GAUDI2_SPMU_NIC0_DBG_0 + port)) {
+ dev_err(hdev->dev, "Invalid nic port %u\n", port);
+ return -EINVAL;
+ }
+
+ memset(¶ms, 0, sizeof(struct hl_debug_params));
+ params.op = HL_DEBUG_OP_SPMU;
+ params.input = &spmu;
+ params.enable = enable;
+ params.output_size = sizeof(event_counters);
+ params.output = event_counters;
+ params.reg_idx = GAUDI2_SPMU_NIC0_DBG_0 + port;
+
+ memset(&spmu, 0, sizeof(struct hl_debug_params_spmu));
+ spmu.event_types_num = num_event_types;
+
+ for (i = 0 ; i < spmu.event_types_num ; i++)
+ spmu.event_types[i] = event_types[i];
+
+ return gaudi2_config_spmu(hdev, ¶ms);
+}
+
+int gaudi2_cn_spmu_sample(struct hl_device *hdev, u32 port, u32 num_out_data, u64 out_data[])
+{
+ struct hl_debug_params params;
+
+ if (!hdev->supports_coresight)
+ return 0;
+
+ /* validate nic port */
+ if (!gaudi2_reg_is_nic_spmu(GAUDI2_SPMU_NIC0_DBG_0 + port)) {
+ dev_err(hdev->dev, "Invalid nic port %u\n", port);
+ return -EINVAL;
+ }
+
+ memset(¶ms, 0, sizeof(struct hl_debug_params));
+ params.output = out_data;
+ params.output_size = num_out_data * sizeof(u64);
+ params.reg_idx = GAUDI2_SPMU_NIC0_DBG_0 + port;
+
+ return gaudi2_sample_spmu(hdev, ¶ms);
+}
+
int gaudi2_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data)
{
struct hl_debug_params *params = data;
--
2.34.1
^ permalink raw reply related [flat|nested] 108+ messages in thread* Re: [PATCH 00/15] Introduce HabanaLabs network drivers
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
` (14 preceding siblings ...)
2024-06-13 8:22 ` [PATCH 15/15] accel/habanalabs/gaudi2: network scaling support Omer Shpigelman
@ 2024-06-17 12:34 ` Alexander Lobakin
2024-06-19 11:40 ` Omer Shpigelman
2024-06-19 16:33 ` Jiri Pirko
16 siblings, 1 reply; 108+ messages in thread
From: Alexander Lobakin @ 2024-06-17 12:34 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel, linux-rdma, netdev, dri-devel, ogabbay, zyehudai
From: Omer Shpigelman <oshpigelman@habana.ai>
Date: Thu, 13 Jun 2024 11:21:53 +0300
> This patch set implements the HabanaLabs network drivers for Gaudi2 ASIC
> which is designed for scaling of AI neural networks training.
> The patch set includes the common code which is shared by all Gaudi ASICs
> and the Gaudi2 ASIC specific code. Newer ASICs code will be followed.
> All of these network drivers are modeled as an auxiliary devices to the
> parent driver.
>
> The newly added drivers are Core Network (CN), Ethernet and InfiniBand.
> All of these drivers are based on the existing habanalabs driver which
> serves as the compute driver and the entire platform.
> The habanalabs driver probes the network drivers which configure the
> relevant NIC HW of the device. In addition, it continuously communicates
> with the CN driver for providing some services which are not NIC specific
> e.g. PCI, MMU, FW communication etc.
>
> See the drivers scheme at:
> Documentation/networking/device_drivers/ethernet/intel/hbl.rst
>
> The CN driver is both a parent and a son driver. It serves as the common
> layer of many shared operations that are required by both EN and IB
> drivers.
>
> The Gaudi2 NIC HW is composed of 48 physical lanes, 56Gbps each. Each pair
> of lanes represent a 100Gbps logical port.
>
> The NIC HW was designed specifically for scaling AI training.
> Hence it basically functions as a regular NIC device but it is tuned for
> its dedicated purpose. As a result, the NIC HW supports Ethernet traffic
> and RDMA over modified ROCEv2 protocol.
> For example, with respect to the IB driver, the HW supports a single
> context and a single PD. The reason for this is that the operational use
> case of AI training for Gaudi2 consists of a single user
> application/process.
> Another example related to the IB driver is the lack of MR since a single
> application/process can share the entire MMU with the compute device.
> Moreover, the memory allocation of user data buffers which are used for
> RDMA communication is done via the habanalabs compute driver uAPI.
> With respect to the Ethernet driver, since the Ethernet flow is used
> mainly for control, the HW is not performance tuned e.g. it assumes a
> contiguous memory for the Rx buffers. Thus the EN driver needs to copy the
> Rx packets from the Rx buffer into the skb memory.
>
> The first 8 patches implement the CN driver.
> The next 2 patches implement the EN driver.
> The next 2 patches implement the IB driver.
> The last 3 patches modify the compute driver to support the CN driver.
>
> The patches are rebased on v6.10-rc3 tag:
> https://github.com/torvalds/linux/releases/tag/v6.10-rc3
>
> The patches are also available at:
> https://github.com/HabanaAI/drivers.gpu.linux-nic.kernel/tree/hbl_next
>
> The user-mode of the driver is being reviewed at:
> https://github.com/linux-rdma/rdma-core/pull/1472
>
> Any feedback, comment or question is welcome.
>
> Thanks,
> Omer
>
> Omer Shpigelman (15):
> net: hbl_cn: add habanalabs Core Network driver
> net: hbl_cn: memory manager component
> net: hbl_cn: physical layer support
> net: hbl_cn: QP state machine
> net: hbl_cn: memory trace events
> net: hbl_cn: debugfs support
> net: hbl_cn: gaudi2: ASIC register header files
> net: hbl_cn: gaudi2: ASIC specific support
> net: hbl_en: add habanalabs Ethernet driver
> net: hbl_en: gaudi2: ASIC specific support
> RDMA/hbl: add habanalabs RDMA driver
> RDMA/hbl: direct verbs support
> accel/habanalabs: network scaling support
> accel/habanalabs/gaudi2: CN registers header files
> accel/habanalabs/gaudi2: network scaling support
>
> .../ABI/testing/debugfs-driver-habanalabs_cn | 195 +
> .../device_drivers/ethernet/index.rst | 1 +
> .../device_drivers/ethernet/intel/hbl.rst | 82 +
> MAINTAINERS | 33 +
> drivers/accel/habanalabs/Kconfig | 1 +
> drivers/accel/habanalabs/Makefile | 3 +
> drivers/accel/habanalabs/cn/Makefile | 2 +
> drivers/accel/habanalabs/cn/cn.c | 815 +
> drivers/accel/habanalabs/cn/cn.h | 133 +
> .../habanalabs/common/command_submission.c | 2 +-
> drivers/accel/habanalabs/common/device.c | 23 +
> drivers/accel/habanalabs/common/firmware_if.c | 20 +
> drivers/accel/habanalabs/common/habanalabs.h | 43 +-
> .../accel/habanalabs/common/habanalabs_drv.c | 37 +-
> .../habanalabs/common/habanalabs_ioctl.c | 2 +
> drivers/accel/habanalabs/common/memory.c | 123 +
> drivers/accel/habanalabs/gaudi/gaudi.c | 14 +-
> drivers/accel/habanalabs/gaudi2/Makefile | 2 +-
> drivers/accel/habanalabs/gaudi2/gaudi2.c | 440 +-
> drivers/accel/habanalabs/gaudi2/gaudi2P.h | 41 +-
> drivers/accel/habanalabs/gaudi2/gaudi2_cn.c | 424 +
> drivers/accel/habanalabs/gaudi2/gaudi2_cn.h | 42 +
> .../habanalabs/gaudi2/gaudi2_coresight.c | 145 +-
> .../accel/habanalabs/gaudi2/gaudi2_security.c | 16 +-
> drivers/accel/habanalabs/goya/goya.c | 6 +
> .../include/gaudi2/asic_reg/gaudi2_regs.h | 10 +-
> .../include/gaudi2/asic_reg/nic0_phy_regs.h | 59 +
> .../nic0_qm0_axuser_nonsecured_regs.h | 61 +
> .../include/gaudi2/asic_reg/nic0_qpc1_regs.h | 905 +
> .../include/gaudi2/asic_reg/nic0_rxe0_regs.h | 725 +
> .../include/gaudi2/asic_reg/nic0_rxe1_regs.h | 725 +
> .../include/gaudi2/asic_reg/nic0_txe0_regs.h | 529 +
> .../include/gaudi2/asic_reg/nic0_txs0_regs.h | 289 +
> .../include/hw_ip/nic/nic_general.h | 15 +
> drivers/infiniband/Kconfig | 1 +
> drivers/infiniband/hw/Makefile | 1 +
> drivers/infiniband/hw/hbl/Kconfig | 18 +
> drivers/infiniband/hw/hbl/Makefile | 12 +
> drivers/infiniband/hw/hbl/hbl.h | 326 +
> drivers/infiniband/hw/hbl/hbl_encap.c | 216 +
> drivers/infiniband/hw/hbl/hbl_main.c | 493 +
> drivers/infiniband/hw/hbl/hbl_query_port.c | 96 +
> drivers/infiniband/hw/hbl/hbl_set_port_ex.c | 96 +
> drivers/infiniband/hw/hbl/hbl_usr_fifo.c | 252 +
> drivers/infiniband/hw/hbl/hbl_verbs.c | 2686 +
> drivers/net/ethernet/intel/Kconfig | 38 +
> drivers/net/ethernet/intel/Makefile | 2 +
> drivers/net/ethernet/intel/hbl_cn/Makefile | 14 +
> .../net/ethernet/intel/hbl_cn/common/Makefile | 3 +
> .../net/ethernet/intel/hbl_cn/common/hbl_cn.c | 5984 ++
> .../net/ethernet/intel/hbl_cn/common/hbl_cn.h | 1666 +
> .../intel/hbl_cn/common/hbl_cn_debugfs.c | 1457 +
> .../ethernet/intel/hbl_cn/common/hbl_cn_drv.c | 240 +
> .../intel/hbl_cn/common/hbl_cn_memory.c | 368 +
> .../ethernet/intel/hbl_cn/common/hbl_cn_phy.c | 234 +
> .../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 491 +
> .../net/ethernet/intel/hbl_cn/gaudi2/Makefile | 3 +
> .../asic_reg/arc_farm_kdma_ctx_axuser_masks.h | 135 +
> .../asic_reg/dcore0_sync_mngr_objs_regs.h | 43543 +++++++++++++++
> .../asic_reg/gaudi2_blocks_linux_driver.h | 45068 ++++++++++++++++
I don't think adding generated register defs etc. is a good idea.
You just bloat the kernel code while most of the values are not used.
When I work with HW and need to use some register defs, I add them
manually one-by-one only when needed. I know it takes more time than to
just add a whole generated reg file, but we don't need tens of thousand
unused locs in the kernel.
Please add only the actually used definitions. This applies to every
file from the series.
> .../hbl_cn/gaudi2/asic_reg/gaudi2_regs.h | 77 +
> .../asic_reg/nic0_mac_ch0_mac_128_masks.h | 339 +
> .../asic_reg/nic0_mac_ch0_mac_128_regs.h | 101 +
> .../asic_reg/nic0_mac_ch0_mac_pcs_masks.h | 713 +
> .../asic_reg/nic0_mac_ch0_mac_pcs_regs.h | 271 +
> .../asic_reg/nic0_mac_ch1_mac_pcs_regs.h | 271 +
> .../asic_reg/nic0_mac_ch2_mac_pcs_regs.h | 271 +
> .../asic_reg/nic0_mac_ch3_mac_pcs_regs.h | 271 +
> .../nic0_mac_glob_stat_control_reg_masks.h | 67 +
> .../nic0_mac_glob_stat_control_reg_regs.h | 37 +
> .../asic_reg/nic0_mac_glob_stat_rx0_regs.h | 93 +
> .../asic_reg/nic0_mac_glob_stat_rx2_regs.h | 93 +
> .../asic_reg/nic0_mac_glob_stat_tx0_regs.h | 75 +
> .../asic_reg/nic0_mac_glob_stat_tx2_regs.h | 75 +
> .../gaudi2/asic_reg/nic0_mac_rs_fec_regs.h | 157 +
> .../hbl_cn/gaudi2/asic_reg/nic0_phy_masks.h | 77 +
> .../hbl_cn/gaudi2/asic_reg/nic0_phy_regs.h | 59 +
> .../nic0_qm0_axuser_nonsecured_regs.h | 61 +
> .../asic_reg/nic0_qpc0_axuser_cong_que_regs.h | 61 +
> .../asic_reg/nic0_qpc0_axuser_db_fifo_regs.h | 61 +
> .../asic_reg/nic0_qpc0_axuser_err_fifo_regs.h | 61 +
> .../nic0_qpc0_axuser_ev_que_lbw_intr_regs.h | 61 +
> .../asic_reg/nic0_qpc0_axuser_qpc_req_regs.h | 61 +
> .../asic_reg/nic0_qpc0_axuser_qpc_resp_regs.h | 61 +
> .../asic_reg/nic0_qpc0_axuser_rxwqe_regs.h | 61 +
> .../nic0_qpc0_axuser_txwqe_lbw_qman_bp_regs.h | 61 +
> .../nic0_qpc0_dbfifo0_ci_upd_addr_regs.h | 27 +
> .../nic0_qpc0_dbfifosecur_ci_upd_addr_regs.h | 27 +
> .../hbl_cn/gaudi2/asic_reg/nic0_qpc0_masks.h | 963 +
> .../hbl_cn/gaudi2/asic_reg/nic0_qpc0_regs.h | 905 +
> .../hbl_cn/gaudi2/asic_reg/nic0_qpc1_regs.h | 905 +
> .../gaudi2/asic_reg/nic0_rxb_core_masks.h | 459 +
> .../gaudi2/asic_reg/nic0_rxb_core_regs.h | 665 +
> .../nic0_rxe0_axuser_axuser_cq0_regs.h | 61 +
> .../nic0_rxe0_axuser_axuser_cq1_regs.h | 61 +
> .../hbl_cn/gaudi2/asic_reg/nic0_rxe0_masks.h | 705 +
> .../hbl_cn/gaudi2/asic_reg/nic0_rxe0_regs.h | 725 +
> .../asic_reg/nic0_rxe0_wqe_aruser_regs.h | 61 +
> .../hbl_cn/gaudi2/asic_reg/nic0_rxe1_regs.h | 725 +
> .../gaudi2/asic_reg/nic0_serdes0_masks.h | 7163 +++
> .../gaudi2/asic_reg/nic0_serdes0_regs.h | 1679 +
> .../gaudi2/asic_reg/nic0_serdes1_regs.h | 1679 +
> .../asic_reg/nic0_tmr_axuser_tmr_fifo_regs.h | 61 +
> .../nic0_tmr_axuser_tmr_free_list_regs.h | 61 +
> .../asic_reg/nic0_tmr_axuser_tmr_fsm_regs.h | 61 +
> .../hbl_cn/gaudi2/asic_reg/nic0_tmr_masks.h | 361 +
> .../hbl_cn/gaudi2/asic_reg/nic0_tmr_regs.h | 183 +
> .../hbl_cn/gaudi2/asic_reg/nic0_txb_regs.h | 167 +
> .../hbl_cn/gaudi2/asic_reg/nic0_txe0_masks.h | 759 +
> .../hbl_cn/gaudi2/asic_reg/nic0_txe0_regs.h | 529 +
> .../hbl_cn/gaudi2/asic_reg/nic0_txs0_masks.h | 555 +
> .../hbl_cn/gaudi2/asic_reg/nic0_txs0_regs.h | 289 +
> .../nic0_umr0_0_completion_queue_ci_1_regs.h | 27 +
> .../nic0_umr0_0_unsecure_doorbell0_regs.h | 31 +
> .../nic0_umr0_0_unsecure_doorbell1_regs.h | 31 +
> .../gaudi2/asic_reg/prt0_mac_core_masks.h | 137 +
> .../gaudi2/asic_reg/prt0_mac_core_regs.h | 67 +
> .../ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.c | 5689 ++
> .../ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.h | 427 +
> .../intel/hbl_cn/gaudi2/gaudi2_cn_debugfs.c | 319 +
> .../intel/hbl_cn/gaudi2/gaudi2_cn_eq.c | 732 +
> .../intel/hbl_cn/gaudi2/gaudi2_cn_phy.c | 2743 +
> drivers/net/ethernet/intel/hbl_en/Makefile | 12 +
> .../net/ethernet/intel/hbl_en/common/Makefile | 3 +
> .../net/ethernet/intel/hbl_en/common/hbl_en.c | 1170 +
> .../net/ethernet/intel/hbl_en/common/hbl_en.h | 208 +
> .../intel/hbl_en/common/hbl_en_dcbnl.c | 101 +
> .../ethernet/intel/hbl_en/common/hbl_en_drv.c | 211 +
> .../intel/hbl_en/common/hbl_en_ethtool.c | 452 +
> .../net/ethernet/intel/hbl_en/gaudi2/Makefile | 2 +
> .../ethernet/intel/hbl_en/gaudi2/gaudi2_en.c | 728 +
> .../ethernet/intel/hbl_en/gaudi2/gaudi2_en.h | 53 +
> .../intel/hbl_en/gaudi2/gaudi2_en_dcbnl.c | 32 +
> include/linux/habanalabs/cpucp_if.h | 125 +-
> include/linux/habanalabs/hl_boot_if.h | 9 +-
> include/linux/net/intel/cn.h | 474 +
> include/linux/net/intel/cn_aux.h | 298 +
> include/linux/net/intel/cni.h | 636 +
> include/linux/net/intel/gaudi2.h | 432 +
> include/linux/net/intel/gaudi2_aux.h | 94 +
> include/trace/events/habanalabs_cn.h | 116 +
> include/uapi/drm/habanalabs_accel.h | 10 +-
> include/uapi/rdma/hbl-abi.h | 204 +
> include/uapi/rdma/hbl_user_ioctl_cmds.h | 66 +
> include/uapi/rdma/hbl_user_ioctl_verbs.h | 106 +
> include/uapi/rdma/ib_user_ioctl_verbs.h | 1 +
> 146 files changed, 148514 insertions(+), 70 deletions(-)
So most of these new lines are generated register definitions. The
series can be several times smaller if you follow my advice.
Thanks,
Olek
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 00/15] Introduce HabanaLabs network drivers
2024-06-17 12:34 ` [PATCH 00/15] Introduce HabanaLabs network drivers Alexander Lobakin
@ 2024-06-19 11:40 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-19 11:40 UTC (permalink / raw)
To: Alexander Lobakin
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/17/24 15:34, Alexander Lobakin wrote:
> [Some people who received this message don't often get email from aleksander.lobakin@intel.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> From: Omer Shpigelman <oshpigelman@habana.ai>
> Date: Thu, 13 Jun 2024 11:21:53 +0300
>
>> This patch set implements the HabanaLabs network drivers for Gaudi2 ASIC
>> which is designed for scaling of AI neural networks training.
>> The patch set includes the common code which is shared by all Gaudi ASICs
>> and the Gaudi2 ASIC specific code. Newer ASICs code will be followed.
>> All of these network drivers are modeled as an auxiliary devices to the
>> parent driver.
>>
>> The newly added drivers are Core Network (CN), Ethernet and InfiniBand.
>> All of these drivers are based on the existing habanalabs driver which
>> serves as the compute driver and the entire platform.
>> The habanalabs driver probes the network drivers which configure the
>> relevant NIC HW of the device. In addition, it continuously communicates
>> with the CN driver for providing some services which are not NIC specific
>> e.g. PCI, MMU, FW communication etc.
>>
>> See the drivers scheme at:
>> Documentation/networking/device_drivers/ethernet/intel/hbl.rst
>>
>> The CN driver is both a parent and a son driver. It serves as the common
>> layer of many shared operations that are required by both EN and IB
>> drivers.
>>
>> The Gaudi2 NIC HW is composed of 48 physical lanes, 56Gbps each. Each pair
>> of lanes represent a 100Gbps logical port.
>>
>> The NIC HW was designed specifically for scaling AI training.
>> Hence it basically functions as a regular NIC device but it is tuned for
>> its dedicated purpose. As a result, the NIC HW supports Ethernet traffic
>> and RDMA over modified ROCEv2 protocol.
>> For example, with respect to the IB driver, the HW supports a single
>> context and a single PD. The reason for this is that the operational use
>> case of AI training for Gaudi2 consists of a single user
>> application/process.
>> Another example related to the IB driver is the lack of MR since a single
>> application/process can share the entire MMU with the compute device.
>> Moreover, the memory allocation of user data buffers which are used for
>> RDMA communication is done via the habanalabs compute driver uAPI.
>> With respect to the Ethernet driver, since the Ethernet flow is used
>> mainly for control, the HW is not performance tuned e.g. it assumes a
>> contiguous memory for the Rx buffers. Thus the EN driver needs to copy the
>> Rx packets from the Rx buffer into the skb memory.
>>
>> The first 8 patches implement the CN driver.
>> The next 2 patches implement the EN driver.
>> The next 2 patches implement the IB driver.
>> The last 3 patches modify the compute driver to support the CN driver.
>>
>> The patches are rebased on v6.10-rc3 tag:
>> https://github.com/torvalds/linux/releases/tag/v6.10-rc3
>>
>> The patches are also available at:
>> https://github.com/HabanaAI/drivers.gpu.linux-nic.kernel/tree/hbl_next
>>
>> The user-mode of the driver is being reviewed at:
>> https://github.com/linux-rdma/rdma-core/pull/1472
>>
>> Any feedback, comment or question is welcome.
>>
>> Thanks,
>> Omer
>>
>> Omer Shpigelman (15):
>> net: hbl_cn: add habanalabs Core Network driver
>> net: hbl_cn: memory manager component
>> net: hbl_cn: physical layer support
>> net: hbl_cn: QP state machine
>> net: hbl_cn: memory trace events
>> net: hbl_cn: debugfs support
>> net: hbl_cn: gaudi2: ASIC register header files
>> net: hbl_cn: gaudi2: ASIC specific support
>> net: hbl_en: add habanalabs Ethernet driver
>> net: hbl_en: gaudi2: ASIC specific support
>> RDMA/hbl: add habanalabs RDMA driver
>> RDMA/hbl: direct verbs support
>> accel/habanalabs: network scaling support
>> accel/habanalabs/gaudi2: CN registers header files
>> accel/habanalabs/gaudi2: network scaling support
>>
>> .../ABI/testing/debugfs-driver-habanalabs_cn | 195 +
>> .../device_drivers/ethernet/index.rst | 1 +
>> .../device_drivers/ethernet/intel/hbl.rst | 82 +
>> MAINTAINERS | 33 +
>> drivers/accel/habanalabs/Kconfig | 1 +
>> drivers/accel/habanalabs/Makefile | 3 +
>> drivers/accel/habanalabs/cn/Makefile | 2 +
>> drivers/accel/habanalabs/cn/cn.c | 815 +
>> drivers/accel/habanalabs/cn/cn.h | 133 +
>> .../habanalabs/common/command_submission.c | 2 +-
>> drivers/accel/habanalabs/common/device.c | 23 +
>> drivers/accel/habanalabs/common/firmware_if.c | 20 +
>> drivers/accel/habanalabs/common/habanalabs.h | 43 +-
>> .../accel/habanalabs/common/habanalabs_drv.c | 37 +-
>> .../habanalabs/common/habanalabs_ioctl.c | 2 +
>> drivers/accel/habanalabs/common/memory.c | 123 +
>> drivers/accel/habanalabs/gaudi/gaudi.c | 14 +-
>> drivers/accel/habanalabs/gaudi2/Makefile | 2 +-
>> drivers/accel/habanalabs/gaudi2/gaudi2.c | 440 +-
>> drivers/accel/habanalabs/gaudi2/gaudi2P.h | 41 +-
>> drivers/accel/habanalabs/gaudi2/gaudi2_cn.c | 424 +
>> drivers/accel/habanalabs/gaudi2/gaudi2_cn.h | 42 +
>> .../habanalabs/gaudi2/gaudi2_coresight.c | 145 +-
>> .../accel/habanalabs/gaudi2/gaudi2_security.c | 16 +-
>> drivers/accel/habanalabs/goya/goya.c | 6 +
>> .../include/gaudi2/asic_reg/gaudi2_regs.h | 10 +-
>> .../include/gaudi2/asic_reg/nic0_phy_regs.h | 59 +
>> .../nic0_qm0_axuser_nonsecured_regs.h | 61 +
>> .../include/gaudi2/asic_reg/nic0_qpc1_regs.h | 905 +
>> .../include/gaudi2/asic_reg/nic0_rxe0_regs.h | 725 +
>> .../include/gaudi2/asic_reg/nic0_rxe1_regs.h | 725 +
>> .../include/gaudi2/asic_reg/nic0_txe0_regs.h | 529 +
>> .../include/gaudi2/asic_reg/nic0_txs0_regs.h | 289 +
>> .../include/hw_ip/nic/nic_general.h | 15 +
>> drivers/infiniband/Kconfig | 1 +
>> drivers/infiniband/hw/Makefile | 1 +
>> drivers/infiniband/hw/hbl/Kconfig | 18 +
>> drivers/infiniband/hw/hbl/Makefile | 12 +
>> drivers/infiniband/hw/hbl/hbl.h | 326 +
>> drivers/infiniband/hw/hbl/hbl_encap.c | 216 +
>> drivers/infiniband/hw/hbl/hbl_main.c | 493 +
>> drivers/infiniband/hw/hbl/hbl_query_port.c | 96 +
>> drivers/infiniband/hw/hbl/hbl_set_port_ex.c | 96 +
>> drivers/infiniband/hw/hbl/hbl_usr_fifo.c | 252 +
>> drivers/infiniband/hw/hbl/hbl_verbs.c | 2686 +
>> drivers/net/ethernet/intel/Kconfig | 38 +
>> drivers/net/ethernet/intel/Makefile | 2 +
>> drivers/net/ethernet/intel/hbl_cn/Makefile | 14 +
>> .../net/ethernet/intel/hbl_cn/common/Makefile | 3 +
>> .../net/ethernet/intel/hbl_cn/common/hbl_cn.c | 5984 ++
>> .../net/ethernet/intel/hbl_cn/common/hbl_cn.h | 1666 +
>> .../intel/hbl_cn/common/hbl_cn_debugfs.c | 1457 +
>> .../ethernet/intel/hbl_cn/common/hbl_cn_drv.c | 240 +
>> .../intel/hbl_cn/common/hbl_cn_memory.c | 368 +
>> .../ethernet/intel/hbl_cn/common/hbl_cn_phy.c | 234 +
>> .../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 491 +
>> .../net/ethernet/intel/hbl_cn/gaudi2/Makefile | 3 +
>> .../asic_reg/arc_farm_kdma_ctx_axuser_masks.h | 135 +
>> .../asic_reg/dcore0_sync_mngr_objs_regs.h | 43543 +++++++++++++++
>> .../asic_reg/gaudi2_blocks_linux_driver.h | 45068 ++++++++++++++++
>
> I don't think adding generated register defs etc. is a good idea.
> You just bloat the kernel code while most of the values are not used.
>
> When I work with HW and need to use some register defs, I add them
> manually one-by-one only when needed. I know it takes more time than to
> just add a whole generated reg file, but we don't need tens of thousand
> unused locs in the kernel.
> Please add only the actually used definitions. This applies to every
> file from the series.
>
Ok, I'll check which register definitions are actually needed.
>> .../hbl_cn/gaudi2/asic_reg/gaudi2_regs.h | 77 +
>> .../asic_reg/nic0_mac_ch0_mac_128_masks.h | 339 +
>> .../asic_reg/nic0_mac_ch0_mac_128_regs.h | 101 +
>> .../asic_reg/nic0_mac_ch0_mac_pcs_masks.h | 713 +
>> .../asic_reg/nic0_mac_ch0_mac_pcs_regs.h | 271 +
>> .../asic_reg/nic0_mac_ch1_mac_pcs_regs.h | 271 +
>> .../asic_reg/nic0_mac_ch2_mac_pcs_regs.h | 271 +
>> .../asic_reg/nic0_mac_ch3_mac_pcs_regs.h | 271 +
>> .../nic0_mac_glob_stat_control_reg_masks.h | 67 +
>> .../nic0_mac_glob_stat_control_reg_regs.h | 37 +
>> .../asic_reg/nic0_mac_glob_stat_rx0_regs.h | 93 +
>> .../asic_reg/nic0_mac_glob_stat_rx2_regs.h | 93 +
>> .../asic_reg/nic0_mac_glob_stat_tx0_regs.h | 75 +
>> .../asic_reg/nic0_mac_glob_stat_tx2_regs.h | 75 +
>> .../gaudi2/asic_reg/nic0_mac_rs_fec_regs.h | 157 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_phy_masks.h | 77 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_phy_regs.h | 59 +
>> .../nic0_qm0_axuser_nonsecured_regs.h | 61 +
>> .../asic_reg/nic0_qpc0_axuser_cong_que_regs.h | 61 +
>> .../asic_reg/nic0_qpc0_axuser_db_fifo_regs.h | 61 +
>> .../asic_reg/nic0_qpc0_axuser_err_fifo_regs.h | 61 +
>> .../nic0_qpc0_axuser_ev_que_lbw_intr_regs.h | 61 +
>> .../asic_reg/nic0_qpc0_axuser_qpc_req_regs.h | 61 +
>> .../asic_reg/nic0_qpc0_axuser_qpc_resp_regs.h | 61 +
>> .../asic_reg/nic0_qpc0_axuser_rxwqe_regs.h | 61 +
>> .../nic0_qpc0_axuser_txwqe_lbw_qman_bp_regs.h | 61 +
>> .../nic0_qpc0_dbfifo0_ci_upd_addr_regs.h | 27 +
>> .../nic0_qpc0_dbfifosecur_ci_upd_addr_regs.h | 27 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_qpc0_masks.h | 963 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_qpc0_regs.h | 905 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_qpc1_regs.h | 905 +
>> .../gaudi2/asic_reg/nic0_rxb_core_masks.h | 459 +
>> .../gaudi2/asic_reg/nic0_rxb_core_regs.h | 665 +
>> .../nic0_rxe0_axuser_axuser_cq0_regs.h | 61 +
>> .../nic0_rxe0_axuser_axuser_cq1_regs.h | 61 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_rxe0_masks.h | 705 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_rxe0_regs.h | 725 +
>> .../asic_reg/nic0_rxe0_wqe_aruser_regs.h | 61 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_rxe1_regs.h | 725 +
>> .../gaudi2/asic_reg/nic0_serdes0_masks.h | 7163 +++
>> .../gaudi2/asic_reg/nic0_serdes0_regs.h | 1679 +
>> .../gaudi2/asic_reg/nic0_serdes1_regs.h | 1679 +
>> .../asic_reg/nic0_tmr_axuser_tmr_fifo_regs.h | 61 +
>> .../nic0_tmr_axuser_tmr_free_list_regs.h | 61 +
>> .../asic_reg/nic0_tmr_axuser_tmr_fsm_regs.h | 61 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_tmr_masks.h | 361 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_tmr_regs.h | 183 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_txb_regs.h | 167 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_txe0_masks.h | 759 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_txe0_regs.h | 529 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_txs0_masks.h | 555 +
>> .../hbl_cn/gaudi2/asic_reg/nic0_txs0_regs.h | 289 +
>> .../nic0_umr0_0_completion_queue_ci_1_regs.h | 27 +
>> .../nic0_umr0_0_unsecure_doorbell0_regs.h | 31 +
>> .../nic0_umr0_0_unsecure_doorbell1_regs.h | 31 +
>> .../gaudi2/asic_reg/prt0_mac_core_masks.h | 137 +
>> .../gaudi2/asic_reg/prt0_mac_core_regs.h | 67 +
>> .../ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.c | 5689 ++
>> .../ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.h | 427 +
>> .../intel/hbl_cn/gaudi2/gaudi2_cn_debugfs.c | 319 +
>> .../intel/hbl_cn/gaudi2/gaudi2_cn_eq.c | 732 +
>> .../intel/hbl_cn/gaudi2/gaudi2_cn_phy.c | 2743 +
>> drivers/net/ethernet/intel/hbl_en/Makefile | 12 +
>> .../net/ethernet/intel/hbl_en/common/Makefile | 3 +
>> .../net/ethernet/intel/hbl_en/common/hbl_en.c | 1170 +
>> .../net/ethernet/intel/hbl_en/common/hbl_en.h | 208 +
>> .../intel/hbl_en/common/hbl_en_dcbnl.c | 101 +
>> .../ethernet/intel/hbl_en/common/hbl_en_drv.c | 211 +
>> .../intel/hbl_en/common/hbl_en_ethtool.c | 452 +
>> .../net/ethernet/intel/hbl_en/gaudi2/Makefile | 2 +
>> .../ethernet/intel/hbl_en/gaudi2/gaudi2_en.c | 728 +
>> .../ethernet/intel/hbl_en/gaudi2/gaudi2_en.h | 53 +
>> .../intel/hbl_en/gaudi2/gaudi2_en_dcbnl.c | 32 +
>> include/linux/habanalabs/cpucp_if.h | 125 +-
>> include/linux/habanalabs/hl_boot_if.h | 9 +-
>> include/linux/net/intel/cn.h | 474 +
>> include/linux/net/intel/cn_aux.h | 298 +
>> include/linux/net/intel/cni.h | 636 +
>> include/linux/net/intel/gaudi2.h | 432 +
>> include/linux/net/intel/gaudi2_aux.h | 94 +
>> include/trace/events/habanalabs_cn.h | 116 +
>> include/uapi/drm/habanalabs_accel.h | 10 +-
>> include/uapi/rdma/hbl-abi.h | 204 +
>> include/uapi/rdma/hbl_user_ioctl_cmds.h | 66 +
>> include/uapi/rdma/hbl_user_ioctl_verbs.h | 106 +
>> include/uapi/rdma/ib_user_ioctl_verbs.h | 1 +
>> 146 files changed, 148514 insertions(+), 70 deletions(-)
>
> So most of these new lines are generated register definitions. The
> series can be several times smaller if you follow my advice.
>
> Thanks,
> Olek
^ permalink raw reply [flat|nested] 108+ messages in thread
* Re: [PATCH 00/15] Introduce HabanaLabs network drivers
2024-06-13 8:21 [PATCH 00/15] Introduce HabanaLabs network drivers Omer Shpigelman
` (15 preceding siblings ...)
2024-06-17 12:34 ` [PATCH 00/15] Introduce HabanaLabs network drivers Alexander Lobakin
@ 2024-06-19 16:33 ` Jiri Pirko
2024-06-20 5:37 ` Omer Shpigelman
16 siblings, 1 reply; 108+ messages in thread
From: Jiri Pirko @ 2024-06-19 16:33 UTC (permalink / raw)
To: Omer Shpigelman
Cc: linux-kernel, linux-rdma, netdev, dri-devel, ogabbay, zyehudai
Thu, Jun 13, 2024 at 10:21:53AM CEST, oshpigelman@habana.ai wrote:
>This patch set implements the HabanaLabs network drivers for Gaudi2 ASIC
>which is designed for scaling of AI neural networks training.
>The patch set includes the common code which is shared by all Gaudi ASICs
>and the Gaudi2 ASIC specific code. Newer ASICs code will be followed.
>All of these network drivers are modeled as an auxiliary devices to the
>parent driver.
>
>The newly added drivers are Core Network (CN), Ethernet and InfiniBand.
>All of these drivers are based on the existing habanalabs driver which
>serves as the compute driver and the entire platform.
>The habanalabs driver probes the network drivers which configure the
>relevant NIC HW of the device. In addition, it continuously communicates
>with the CN driver for providing some services which are not NIC specific
>e.g. PCI, MMU, FW communication etc.
>
>See the drivers scheme at:
>Documentation/networking/device_drivers/ethernet/intel/hbl.rst
>
>The CN driver is both a parent and a son driver. It serves as the common
>layer of many shared operations that are required by both EN and IB
>drivers.
>
>The Gaudi2 NIC HW is composed of 48 physical lanes, 56Gbps each. Each pair
>of lanes represent a 100Gbps logical port.
What do you mean by "logical port"? Is it a separate netdevice. So you
have 24 netdevices visible on the system? How the physical port/ports
look like? How do you model that in devlink? Do you support port
splitting?
>
>The NIC HW was designed specifically for scaling AI training.
>Hence it basically functions as a regular NIC device but it is tuned for
>its dedicated purpose. As a result, the NIC HW supports Ethernet traffic
>and RDMA over modified ROCEv2 protocol.
>For example, with respect to the IB driver, the HW supports a single
>context and a single PD. The reason for this is that the operational use
>case of AI training for Gaudi2 consists of a single user
>application/process.
>Another example related to the IB driver is the lack of MR since a single
>application/process can share the entire MMU with the compute device.
>Moreover, the memory allocation of user data buffers which are used for
>RDMA communication is done via the habanalabs compute driver uAPI.
>With respect to the Ethernet driver, since the Ethernet flow is used
>mainly for control, the HW is not performance tuned e.g. it assumes a
>contiguous memory for the Rx buffers. Thus the EN driver needs to copy the
>Rx packets from the Rx buffer into the skb memory.
>
>The first 8 patches implement the CN driver.
>The next 2 patches implement the EN driver.
>The next 2 patches implement the IB driver.
>The last 3 patches modify the compute driver to support the CN driver.
>
>The patches are rebased on v6.10-rc3 tag:
>https://github.com/torvalds/linux/releases/tag/v6.10-rc3
>
>The patches are also available at:
>https://github.com/HabanaAI/drivers.gpu.linux-nic.kernel/tree/hbl_next
>
>The user-mode of the driver is being reviewed at:
>https://github.com/linux-rdma/rdma-core/pull/1472
>
>Any feedback, comment or question is welcome.
>
>Thanks,
>Omer
>
>Omer Shpigelman (15):
> net: hbl_cn: add habanalabs Core Network driver
> net: hbl_cn: memory manager component
> net: hbl_cn: physical layer support
> net: hbl_cn: QP state machine
> net: hbl_cn: memory trace events
> net: hbl_cn: debugfs support
> net: hbl_cn: gaudi2: ASIC register header files
> net: hbl_cn: gaudi2: ASIC specific support
> net: hbl_en: add habanalabs Ethernet driver
> net: hbl_en: gaudi2: ASIC specific support
> RDMA/hbl: add habanalabs RDMA driver
> RDMA/hbl: direct verbs support
> accel/habanalabs: network scaling support
> accel/habanalabs/gaudi2: CN registers header files
> accel/habanalabs/gaudi2: network scaling support
>
> .../ABI/testing/debugfs-driver-habanalabs_cn | 195 +
> .../device_drivers/ethernet/index.rst | 1 +
> .../device_drivers/ethernet/intel/hbl.rst | 82 +
> MAINTAINERS | 33 +
> drivers/accel/habanalabs/Kconfig | 1 +
> drivers/accel/habanalabs/Makefile | 3 +
> drivers/accel/habanalabs/cn/Makefile | 2 +
> drivers/accel/habanalabs/cn/cn.c | 815 +
> drivers/accel/habanalabs/cn/cn.h | 133 +
> .../habanalabs/common/command_submission.c | 2 +-
> drivers/accel/habanalabs/common/device.c | 23 +
> drivers/accel/habanalabs/common/firmware_if.c | 20 +
> drivers/accel/habanalabs/common/habanalabs.h | 43 +-
> .../accel/habanalabs/common/habanalabs_drv.c | 37 +-
> .../habanalabs/common/habanalabs_ioctl.c | 2 +
> drivers/accel/habanalabs/common/memory.c | 123 +
> drivers/accel/habanalabs/gaudi/gaudi.c | 14 +-
> drivers/accel/habanalabs/gaudi2/Makefile | 2 +-
> drivers/accel/habanalabs/gaudi2/gaudi2.c | 440 +-
> drivers/accel/habanalabs/gaudi2/gaudi2P.h | 41 +-
> drivers/accel/habanalabs/gaudi2/gaudi2_cn.c | 424 +
> drivers/accel/habanalabs/gaudi2/gaudi2_cn.h | 42 +
> .../habanalabs/gaudi2/gaudi2_coresight.c | 145 +-
> .../accel/habanalabs/gaudi2/gaudi2_security.c | 16 +-
> drivers/accel/habanalabs/goya/goya.c | 6 +
> .../include/gaudi2/asic_reg/gaudi2_regs.h | 10 +-
> .../include/gaudi2/asic_reg/nic0_phy_regs.h | 59 +
> .../nic0_qm0_axuser_nonsecured_regs.h | 61 +
> .../include/gaudi2/asic_reg/nic0_qpc1_regs.h | 905 +
> .../include/gaudi2/asic_reg/nic0_rxe0_regs.h | 725 +
> .../include/gaudi2/asic_reg/nic0_rxe1_regs.h | 725 +
> .../include/gaudi2/asic_reg/nic0_txe0_regs.h | 529 +
> .../include/gaudi2/asic_reg/nic0_txs0_regs.h | 289 +
> .../include/hw_ip/nic/nic_general.h | 15 +
> drivers/infiniband/Kconfig | 1 +
> drivers/infiniband/hw/Makefile | 1 +
> drivers/infiniband/hw/hbl/Kconfig | 18 +
> drivers/infiniband/hw/hbl/Makefile | 12 +
> drivers/infiniband/hw/hbl/hbl.h | 326 +
> drivers/infiniband/hw/hbl/hbl_encap.c | 216 +
> drivers/infiniband/hw/hbl/hbl_main.c | 493 +
> drivers/infiniband/hw/hbl/hbl_query_port.c | 96 +
> drivers/infiniband/hw/hbl/hbl_set_port_ex.c | 96 +
> drivers/infiniband/hw/hbl/hbl_usr_fifo.c | 252 +
> drivers/infiniband/hw/hbl/hbl_verbs.c | 2686 +
> drivers/net/ethernet/intel/Kconfig | 38 +
> drivers/net/ethernet/intel/Makefile | 2 +
> drivers/net/ethernet/intel/hbl_cn/Makefile | 14 +
> .../net/ethernet/intel/hbl_cn/common/Makefile | 3 +
> .../net/ethernet/intel/hbl_cn/common/hbl_cn.c | 5984 ++
> .../net/ethernet/intel/hbl_cn/common/hbl_cn.h | 1666 +
> .../intel/hbl_cn/common/hbl_cn_debugfs.c | 1457 +
> .../ethernet/intel/hbl_cn/common/hbl_cn_drv.c | 240 +
> .../intel/hbl_cn/common/hbl_cn_memory.c | 368 +
> .../ethernet/intel/hbl_cn/common/hbl_cn_phy.c | 234 +
> .../ethernet/intel/hbl_cn/common/hbl_cn_qp.c | 491 +
> .../net/ethernet/intel/hbl_cn/gaudi2/Makefile | 3 +
> .../asic_reg/arc_farm_kdma_ctx_axuser_masks.h | 135 +
> .../asic_reg/dcore0_sync_mngr_objs_regs.h | 43543 +++++++++++++++
> .../asic_reg/gaudi2_blocks_linux_driver.h | 45068 ++++++++++++++++
> .../hbl_cn/gaudi2/asic_reg/gaudi2_regs.h | 77 +
> .../asic_reg/nic0_mac_ch0_mac_128_masks.h | 339 +
> .../asic_reg/nic0_mac_ch0_mac_128_regs.h | 101 +
> .../asic_reg/nic0_mac_ch0_mac_pcs_masks.h | 713 +
> .../asic_reg/nic0_mac_ch0_mac_pcs_regs.h | 271 +
> .../asic_reg/nic0_mac_ch1_mac_pcs_regs.h | 271 +
> .../asic_reg/nic0_mac_ch2_mac_pcs_regs.h | 271 +
> .../asic_reg/nic0_mac_ch3_mac_pcs_regs.h | 271 +
> .../nic0_mac_glob_stat_control_reg_masks.h | 67 +
> .../nic0_mac_glob_stat_control_reg_regs.h | 37 +
> .../asic_reg/nic0_mac_glob_stat_rx0_regs.h | 93 +
> .../asic_reg/nic0_mac_glob_stat_rx2_regs.h | 93 +
> .../asic_reg/nic0_mac_glob_stat_tx0_regs.h | 75 +
> .../asic_reg/nic0_mac_glob_stat_tx2_regs.h | 75 +
> .../gaudi2/asic_reg/nic0_mac_rs_fec_regs.h | 157 +
> .../hbl_cn/gaudi2/asic_reg/nic0_phy_masks.h | 77 +
> .../hbl_cn/gaudi2/asic_reg/nic0_phy_regs.h | 59 +
> .../nic0_qm0_axuser_nonsecured_regs.h | 61 +
> .../asic_reg/nic0_qpc0_axuser_cong_que_regs.h | 61 +
> .../asic_reg/nic0_qpc0_axuser_db_fifo_regs.h | 61 +
> .../asic_reg/nic0_qpc0_axuser_err_fifo_regs.h | 61 +
> .../nic0_qpc0_axuser_ev_que_lbw_intr_regs.h | 61 +
> .../asic_reg/nic0_qpc0_axuser_qpc_req_regs.h | 61 +
> .../asic_reg/nic0_qpc0_axuser_qpc_resp_regs.h | 61 +
> .../asic_reg/nic0_qpc0_axuser_rxwqe_regs.h | 61 +
> .../nic0_qpc0_axuser_txwqe_lbw_qman_bp_regs.h | 61 +
> .../nic0_qpc0_dbfifo0_ci_upd_addr_regs.h | 27 +
> .../nic0_qpc0_dbfifosecur_ci_upd_addr_regs.h | 27 +
> .../hbl_cn/gaudi2/asic_reg/nic0_qpc0_masks.h | 963 +
> .../hbl_cn/gaudi2/asic_reg/nic0_qpc0_regs.h | 905 +
> .../hbl_cn/gaudi2/asic_reg/nic0_qpc1_regs.h | 905 +
> .../gaudi2/asic_reg/nic0_rxb_core_masks.h | 459 +
> .../gaudi2/asic_reg/nic0_rxb_core_regs.h | 665 +
> .../nic0_rxe0_axuser_axuser_cq0_regs.h | 61 +
> .../nic0_rxe0_axuser_axuser_cq1_regs.h | 61 +
> .../hbl_cn/gaudi2/asic_reg/nic0_rxe0_masks.h | 705 +
> .../hbl_cn/gaudi2/asic_reg/nic0_rxe0_regs.h | 725 +
> .../asic_reg/nic0_rxe0_wqe_aruser_regs.h | 61 +
> .../hbl_cn/gaudi2/asic_reg/nic0_rxe1_regs.h | 725 +
> .../gaudi2/asic_reg/nic0_serdes0_masks.h | 7163 +++
> .../gaudi2/asic_reg/nic0_serdes0_regs.h | 1679 +
> .../gaudi2/asic_reg/nic0_serdes1_regs.h | 1679 +
> .../asic_reg/nic0_tmr_axuser_tmr_fifo_regs.h | 61 +
> .../nic0_tmr_axuser_tmr_free_list_regs.h | 61 +
> .../asic_reg/nic0_tmr_axuser_tmr_fsm_regs.h | 61 +
> .../hbl_cn/gaudi2/asic_reg/nic0_tmr_masks.h | 361 +
> .../hbl_cn/gaudi2/asic_reg/nic0_tmr_regs.h | 183 +
> .../hbl_cn/gaudi2/asic_reg/nic0_txb_regs.h | 167 +
> .../hbl_cn/gaudi2/asic_reg/nic0_txe0_masks.h | 759 +
> .../hbl_cn/gaudi2/asic_reg/nic0_txe0_regs.h | 529 +
> .../hbl_cn/gaudi2/asic_reg/nic0_txs0_masks.h | 555 +
> .../hbl_cn/gaudi2/asic_reg/nic0_txs0_regs.h | 289 +
> .../nic0_umr0_0_completion_queue_ci_1_regs.h | 27 +
> .../nic0_umr0_0_unsecure_doorbell0_regs.h | 31 +
> .../nic0_umr0_0_unsecure_doorbell1_regs.h | 31 +
> .../gaudi2/asic_reg/prt0_mac_core_masks.h | 137 +
> .../gaudi2/asic_reg/prt0_mac_core_regs.h | 67 +
> .../ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.c | 5689 ++
> .../ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.h | 427 +
> .../intel/hbl_cn/gaudi2/gaudi2_cn_debugfs.c | 319 +
> .../intel/hbl_cn/gaudi2/gaudi2_cn_eq.c | 732 +
> .../intel/hbl_cn/gaudi2/gaudi2_cn_phy.c | 2743 +
> drivers/net/ethernet/intel/hbl_en/Makefile | 12 +
> .../net/ethernet/intel/hbl_en/common/Makefile | 3 +
> .../net/ethernet/intel/hbl_en/common/hbl_en.c | 1170 +
> .../net/ethernet/intel/hbl_en/common/hbl_en.h | 208 +
> .../intel/hbl_en/common/hbl_en_dcbnl.c | 101 +
> .../ethernet/intel/hbl_en/common/hbl_en_drv.c | 211 +
> .../intel/hbl_en/common/hbl_en_ethtool.c | 452 +
> .../net/ethernet/intel/hbl_en/gaudi2/Makefile | 2 +
> .../ethernet/intel/hbl_en/gaudi2/gaudi2_en.c | 728 +
> .../ethernet/intel/hbl_en/gaudi2/gaudi2_en.h | 53 +
> .../intel/hbl_en/gaudi2/gaudi2_en_dcbnl.c | 32 +
> include/linux/habanalabs/cpucp_if.h | 125 +-
> include/linux/habanalabs/hl_boot_if.h | 9 +-
> include/linux/net/intel/cn.h | 474 +
> include/linux/net/intel/cn_aux.h | 298 +
> include/linux/net/intel/cni.h | 636 +
> include/linux/net/intel/gaudi2.h | 432 +
> include/linux/net/intel/gaudi2_aux.h | 94 +
> include/trace/events/habanalabs_cn.h | 116 +
> include/uapi/drm/habanalabs_accel.h | 10 +-
> include/uapi/rdma/hbl-abi.h | 204 +
> include/uapi/rdma/hbl_user_ioctl_cmds.h | 66 +
> include/uapi/rdma/hbl_user_ioctl_verbs.h | 106 +
> include/uapi/rdma/ib_user_ioctl_verbs.h | 1 +
> 146 files changed, 148514 insertions(+), 70 deletions(-)
> create mode 100644 Documentation/ABI/testing/debugfs-driver-habanalabs_cn
> create mode 100644 Documentation/networking/device_drivers/ethernet/intel/hbl.rst
> create mode 100644 drivers/accel/habanalabs/cn/Makefile
> create mode 100644 drivers/accel/habanalabs/cn/cn.c
> create mode 100644 drivers/accel/habanalabs/cn/cn.h
> create mode 100644 drivers/accel/habanalabs/gaudi2/gaudi2_cn.c
> create mode 100644 drivers/accel/habanalabs/gaudi2/gaudi2_cn.h
> create mode 100644 drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_phy_regs.h
> create mode 100644 drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_axuser_nonsecured_regs.h
> create mode 100644 drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qpc1_regs.h
> create mode 100644 drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_rxe0_regs.h
> create mode 100644 drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_rxe1_regs.h
> create mode 100644 drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_txe0_regs.h
> create mode 100644 drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_txs0_regs.h
> create mode 100644 drivers/accel/habanalabs/include/hw_ip/nic/nic_general.h
> create mode 100644 drivers/infiniband/hw/hbl/Kconfig
> create mode 100644 drivers/infiniband/hw/hbl/Makefile
> create mode 100644 drivers/infiniband/hw/hbl/hbl.h
> create mode 100644 drivers/infiniband/hw/hbl/hbl_encap.c
> create mode 100644 drivers/infiniband/hw/hbl/hbl_main.c
> create mode 100644 drivers/infiniband/hw/hbl/hbl_query_port.c
> create mode 100644 drivers/infiniband/hw/hbl/hbl_set_port_ex.c
> create mode 100644 drivers/infiniband/hw/hbl/hbl_usr_fifo.c
> create mode 100644 drivers/infiniband/hw/hbl/hbl_verbs.c
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/Makefile
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/Makefile
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.c
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/hbl_cn.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_debugfs.c
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_drv.c
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_memory.c
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_phy.c
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/common/hbl_cn_qp.c
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/Makefile
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/gaudi2_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_128_masks.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_128_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_pcs_masks.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch0_mac_pcs_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch1_mac_pcs_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch2_mac_pcs_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_ch3_mac_pcs_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_control_reg_masks.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_control_reg_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_rx0_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_rx2_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_tx0_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_glob_stat_tx2_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_mac_rs_fec_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_phy_masks.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_phy_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qm0_axuser_nonsecured_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_cong_que_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_db_fifo_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_err_fifo_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_ev_que_lbw_intr_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_qpc_req_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_qpc_resp_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_rxwqe_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_axuser_txwqe_lbw_qman_bp_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_dbfifo0_ci_upd_addr_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_dbfifosecur_ci_upd_addr_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_masks.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc0_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_qpc1_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxb_core_masks.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxb_core_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_axuser_axuser_cq0_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_axuser_axuser_cq1_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_masks.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe0_wqe_aruser_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_rxe1_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes0_masks.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes0_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_serdes1_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_fifo_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_free_list_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_axuser_tmr_fsm_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_masks.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_tmr_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txb_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txe0_masks.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txe0_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txs0_masks.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_txs0_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell1_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/prt0_mac_core_masks.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/asic_reg/prt0_mac_core_regs.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.c
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn.h
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_debugfs.c
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_eq.c
> create mode 100644 drivers/net/ethernet/intel/hbl_cn/gaudi2/gaudi2_cn_phy.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/Makefile
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/Makefile
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en.h
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_dcbnl.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_drv.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/common/hbl_en_ethtool.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/gaudi2/Makefile
> create mode 100644 drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en.c
> create mode 100644 drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en.h
> create mode 100644 drivers/net/ethernet/intel/hbl_en/gaudi2/gaudi2_en_dcbnl.c
> create mode 100644 include/linux/net/intel/cn.h
> create mode 100644 include/linux/net/intel/cn_aux.h
> create mode 100644 include/linux/net/intel/cni.h
> create mode 100644 include/linux/net/intel/gaudi2.h
> create mode 100644 include/linux/net/intel/gaudi2_aux.h
> create mode 100644 include/trace/events/habanalabs_cn.h
> create mode 100644 include/uapi/rdma/hbl-abi.h
> create mode 100644 include/uapi/rdma/hbl_user_ioctl_cmds.h
> create mode 100644 include/uapi/rdma/hbl_user_ioctl_verbs.h
>
>--
>2.34.1
>
>
^ permalink raw reply [flat|nested] 108+ messages in thread* Re: [PATCH 00/15] Introduce HabanaLabs network drivers
2024-06-19 16:33 ` Jiri Pirko
@ 2024-06-20 5:37 ` Omer Shpigelman
0 siblings, 0 replies; 108+ messages in thread
From: Omer Shpigelman @ 2024-06-20 5:37 UTC (permalink / raw)
To: Jiri Pirko
Cc: linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, dri-devel@lists.freedesktop.org,
ogabbay@kernel.org, Zvika Yehudai
On 6/19/24 19:33, Jiri Pirko wrote:
> [You don't often get email from jiri@resnulli.us. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> Thu, Jun 13, 2024 at 10:21:53AM CEST, oshpigelman@habana.ai wrote:
>> This patch set implements the HabanaLabs network drivers for Gaudi2 ASIC
>> which is designed for scaling of AI neural networks training.
>> The patch set includes the common code which is shared by all Gaudi ASICs
>> and the Gaudi2 ASIC specific code. Newer ASICs code will be followed.
>> All of these network drivers are modeled as an auxiliary devices to the
>> parent driver.
>>
>> The newly added drivers are Core Network (CN), Ethernet and InfiniBand.
>> All of these drivers are based on the existing habanalabs driver which
>> serves as the compute driver and the entire platform.
>> The habanalabs driver probes the network drivers which configure the
>> relevant NIC HW of the device. In addition, it continuously communicates
>> with the CN driver for providing some services which are not NIC specific
>> e.g. PCI, MMU, FW communication etc.
>>
>> See the drivers scheme at:
>> Documentation/networking/device_drivers/ethernet/intel/hbl.rst
>>
>> The CN driver is both a parent and a son driver. It serves as the common
>> layer of many shared operations that are required by both EN and IB
>> drivers.
>>
>> The Gaudi2 NIC HW is composed of 48 physical lanes, 56Gbps each. Each pair
>> of lanes represent a 100Gbps logical port.
>
> What do you mean by "logical port"? Is it a separate netdevice. So you
> have 24 netdevices visible on the system? How the physical port/ports
> look like? How do you model that in devlink? Do you support port
> splitting?
>
I first described our HW. It is composed of 48 physical lanes. But each
netdevice (meaning a "logical port") is mapped to a pair of these, so we
end up with 24 netdevices visible on the system.
Technically we could work in a mode where we have 48 netdevices visible on
the system and each netdevice is mapped to a single physical lane, but we
have no use case for that.
We are not interagted to devlink, we didn't find a need for that in our
use cases.
^ permalink raw reply [flat|nested] 108+ messages in thread