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Miller" , Andrew Lunn , Eric Dumazet , Florian Fainelli , Jakub Kicinski , Paolo Abeni , Woojung Huh , Arun Ramadoss , Lucas Stach , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, UNGLinuxDriver@microchip.com Subject: Re: [PATCH net-next v1 2/3] net: dsa: microchip: lan937x: force RGMII interface into PHY mode Message-ID: <20240627222543.rcx3i5o43toopwcm@skbuf> References: <20240627123911.227480-1-o.rempel@pengutronix.de> <20240627123911.227480-3-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240627123911.227480-3-o.rempel@pengutronix.de> On Thu, Jun 27, 2024 at 02:39:10PM +0200, Oleksij Rempel wrote: > From: Lucas Stach > > The register manual and datasheet documentation for the LAN937x series > disagree about the polarity of the MII mode strap. As a consequence > there are hardware designs that have the RGMII interface strapped into > MAC mode, which is a invalid configuration and will prevent the internal > clock from being fed into the port TX interface. > > Force the MII mode to PHY for RGMII interfaces where this is the only > valid mode, to override the inproper strapping. > > Signed-off-by: Lucas Stach > Signed-off-by: Oleksij Rempel > --- What's the difference between MAC mode and PHY mode with RGMII for this switch?