From: Simon Horman <horms@kernel.org>
To: Roger Quadros <rogerq@kernel.org>
Cc: "David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Siddharth Vadapalli <s-vadapalli@ti.com>,
Julien Panis <jpanis@baylibre.com>, Andrew Lunn <andrew@lunn.ch>,
srk@ti.com, vigneshr@ti.com, danishanwar@ti.com,
pekka Varis <p-varis@ti.com>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-omap@vger.kernel.org
Subject: Re: [PATCH net-next v3 5/6] net: ethernet: ti: cpsw_ale: add policer/classifier helpers and setup defaults
Date: Thu, 4 Jul 2024 09:54:25 +0100 [thread overview]
Message-ID: <20240704085425.GY598357@kernel.org> (raw)
In-Reply-To: <20240703-am65-cpsw-multi-rx-v3-5-f11cd860fd72@kernel.org>
On Wed, Jul 03, 2024 at 04:51:36PM +0300, Roger Quadros wrote:
> The Policer registers in the ALE register space are just shadow registers
> and use an index field in the policer table control register to read/write
> to the actual Polier registers.
> Add helper functions to Read and Write to Policer registers.
>
> Also add a helper function to set the thread value to classifier/policer
> mapping. Any packet that first matches the classifier will be sent to the
> thread (flow) that is set in the classifier to thread mapping table.
> If not set then it goes to the default flow.
>
> Default behaviour is to have 8 classifiers to map 8 DSCP/PCP
> priorities to N receive threads (flows). N depends on number of
> RX channels enabled for the port.
> As per the standard [1] User prioritie 1 (Background) and 2 (Spare) have
> lower priority than the user priority 0 (default). User priority 1 being
> of the lowest priority.
>
> [1] IEEE802.1D-2004, IEEE Standard for Local and metropolitan area networks
> Table G-2 - Traffic type acronyms
> Table G-3 - Defining traffic types
>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
> Changelog:
> v3:
> - squashed 2 patches into 1
> - added comment explaining the default thread to priority mapping table
> - typo fix "classifer"->"classifier"
Thanks for the updates,
Reviewed-by: Simon Horman <horms@kernel.org>
next prev parent reply other threads:[~2024-07-04 8:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-03 13:51 [PATCH net-next v3 0/6] net: ethernet: ti: am65-cpsw: Add multi queue RX support Roger Quadros
2024-07-03 13:51 ` [PATCH net-next v3 1/6] net: ethernet: ti: am65-cpsw: Introduce multi queue Rx Roger Quadros
2024-07-06 1:15 ` Jakub Kicinski
2024-07-08 19:42 ` Roger Quadros
2024-07-23 17:11 ` Joe Damato
2024-07-27 6:29 ` Roger Quadros
2024-09-09 14:17 ` Roger Quadros
2024-07-23 21:10 ` Brett Creeley
2024-07-27 6:27 ` Roger Quadros
2024-07-03 13:51 ` [PATCH net-next v3 2/6] net: ethernet: ti: cpsw_ale: use regfields for ALE registers Roger Quadros
2024-07-03 13:51 ` [PATCH net-next v3 3/6] net: ethernet: ti: cpsw_ale: use regfields for number of Entries and Policers Roger Quadros
2024-07-03 13:51 ` [PATCH net-next v3 4/6] net: ethernet: ti: cpsw_ale: add Policer and Thread control register fields Roger Quadros
2024-07-03 13:51 ` [PATCH net-next v3 5/6] net: ethernet: ti: cpsw_ale: add policer/classifier helpers and setup defaults Roger Quadros
2024-07-04 8:54 ` Simon Horman [this message]
2024-07-03 13:51 ` [PATCH net-next v3 6/6] net: ethernet: ti: am65-cpsw: setup priority to flow mapping Roger Quadros
2024-07-04 9:59 ` [PATCH net-next v3 0/6] net: ethernet: ti: am65-cpsw: Add multi queue RX support MD Danish Anwar
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