From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4213A1DFE8; Sun, 4 Aug 2024 17:15:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722791735; cv=none; b=dfSw4pDhFRgT7R/tgpdhxAivxAtU5e4G6SR+MQvluOoZqkn7qSvyXiSJlA54TFV2ZvJwW3xpRlAcyg1n7qB+TjJPQTPqYzHRnP6SFZA5x8x0Y15VNSW4KIP+NYFaIexcJhj7o9VETnG/I9DHfwKku0ZlLvedDnd430sKT43C0Co= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722791735; c=relaxed/simple; bh=3kKKRkg3NLAuEiyxJ+xtIkx9o2Y5luF9WRvVWfmvXXk=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MaeS2uLpvsl1AN68UZjbOOoPMnAix1Q22B7ZFrjz4Ad40FRRkjdeW6Dw+Jh6lBE1ielJ5kzjHmon4w4GUeAudMBWZUZSOy7xjwSJ97KmVL3Hc/9JpJB+9mhPLjnTRCk/8HHQnnpWds/TN01oYxh+fA5KfMVmqzhCm6bYLAaYlww= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=Huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=Huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4WcR360FcHz6K92Y; Mon, 5 Aug 2024 01:12:50 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (unknown [7.191.163.240]) by mail.maildlp.com (Postfix) with ESMTPS id A01321400C9; Mon, 5 Aug 2024 01:15:30 +0800 (CST) Received: from localhost (10.195.244.131) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Sun, 4 Aug 2024 18:15:30 +0100 Date: Sun, 4 Aug 2024 18:15:29 +0100 From: Jonathan Cameron To: CC: , , , , , , , , , , Alejandro Lucero Subject: Re: [PATCH v2 02/15] cxl: add function for type2 cxl regs setup Message-ID: <20240804181529.00004aa9@Huawei.com> In-Reply-To: <20240715172835.24757-3-alejandro.lucero-palau@amd.com> References: <20240715172835.24757-1-alejandro.lucero-palau@amd.com> <20240715172835.24757-3-alejandro.lucero-palau@amd.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To lhrpeml500005.china.huawei.com (7.191.163.240) On Mon, 15 Jul 2024 18:28:22 +0100 alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero > > Create a new function for a type2 device initialising the opaque > cxl_dev_state struct regarding cxl regs setup and mapping. > > Signed-off-by: Alejandro Lucero > --- > drivers/cxl/pci.c | 28 ++++++++++++++++++++++++++++ > drivers/net/ethernet/sfc/efx_cxl.c | 3 +++ > include/linux/cxl_accel_mem.h | 1 + > 3 files changed, 32 insertions(+) > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index e53646e9f2fb..b34d6259faf4 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > #include "cxlmem.h" > #include "cxlpci.h" > #include "cxl.h" > @@ -521,6 +522,33 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > return cxl_setup_regs(map); > } > > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) > +{ > + struct cxl_register_map map; > + int rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); > + if (rc) > + return rc; > + > + rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); > + if (rc) > + return rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > + &cxlds->reg_map); > + if (rc) > + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); Not fatal? If we think it will happen on real devices, then dev_warn is too strong. > + > + rc = cxl_map_component_regs(&cxlds->reg_map, &cxlds->regs.component, > + BIT(CXL_CM_CAP_CAP_ID_RAS)); > + if (rc) > + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); pci_err() or similar would make sense here as we have asked for something that isn't happening. Specification says this is mandatory so definitely smells like a fatal error to me. > + > + return rc; > +} > +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, CXL); > + > static int cxl_pci_ras_unmask(struct pci_dev *pdev) > { > struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); > diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c > index 4554dd7cca76..10c4fb915278 100644 > --- a/drivers/net/ethernet/sfc/efx_cxl.c > +++ b/drivers/net/ethernet/sfc/efx_cxl.c > @@ -47,6 +47,9 @@ void efx_cxl_init(struct efx_nic *efx) > > res = DEFINE_RES_MEM_NAMED(0, EFX_CTPIO_BUFFER_SIZE, "ram"); > cxl_accel_set_resource(cxl->cxlds, res, CXL_ACCEL_RES_RAM); > + > + if (cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds)) > + pci_info(pci_dev, "CXL accel setup regs failed"); Handle errors fully. That is report them up to the caller. > } > > > diff --git a/include/linux/cxl_accel_mem.h b/include/linux/cxl_accel_mem.h > index daf46d41f59c..ca7af4a9cefc 100644 > --- a/include/linux/cxl_accel_mem.h > +++ b/include/linux/cxl_accel_mem.h > @@ -19,4 +19,5 @@ void cxl_accel_set_dvsec(cxl_accel_state *cxlds, u16 dvsec); > void cxl_accel_set_serial(cxl_accel_state *cxlds, u64 serial); > void cxl_accel_set_resource(struct cxl_dev_state *cxlds, struct resource res, > enum accel_resource); > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds); > #endif