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Fri, 9 Aug 2024 02:10:36 -0700 Date: Fri, 9 Aug 2024 12:10:36 +0300 From: Zhi Wang To: CC: , , , , , , , , , , Alejandro Lucero , Subject: Re: [PATCH v2 04/15] cxl: add capabilities field to cxl_dev_state Message-ID: <20240809121036.000057f0.zhiw@nvidia.com> In-Reply-To: <20240715172835.24757-5-alejandro.lucero-palau@amd.com> References: <20240715172835.24757-1-alejandro.lucero-palau@amd.com> <20240715172835.24757-5-alejandro.lucero-palau@amd.com> Organization: NVIDIA X-Mailer: Claws Mail 4.2.0 (GTK 3.24.38; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7B:EE_|CY8PR12MB7706:EE_ X-MS-Office365-Filtering-Correlation-Id: f8a37edc-ac02-4a99-20b9-08dcb8532a26 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|7416014|1800799024; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Aug 2024 09:10:50.7143 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f8a37edc-ac02-4a99-20b9-08dcb8532a26 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7706 On Mon, 15 Jul 2024 18:28:24 +0100 wrote: > From: Alejandro Lucero > > Type2 devices have some Type3 functionalities as optional like an mbox > or an hdm decoder, and CXL core needs a way to know what a CXL > accelerator implements. > > Add a new field for keeping device capabilities to be initialised by > Type2 drivers. Advertise all those capabilities for Type3. > > Signed-off-by: Alejandro Lucero > --- > drivers/cxl/core/mbox.c | 1 + > drivers/cxl/core/memdev.c | 4 +++- > drivers/cxl/core/port.c | 2 +- > drivers/cxl/core/regs.c | 11 ++++++----- > drivers/cxl/cxl.h | 2 +- > drivers/cxl/cxlmem.h | 4 ++++ > drivers/cxl/pci.c | 15 +++++++++------ > drivers/net/ethernet/sfc/efx_cxl.c | 3 ++- > include/linux/cxl_accel_mem.h | 5 ++++- > 9 files changed, 31 insertions(+), 16 deletions(-) > > diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c > index 2626f3fff201..2ba7d36e3f38 100644 > --- a/drivers/cxl/core/mbox.c > +++ b/drivers/cxl/core/mbox.c > @@ -1424,6 +1424,7 @@ struct cxl_memdev_state > *cxl_memdev_state_create(struct device *dev) mds->cxlds.reg_map.host > = dev; mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE; > mds->cxlds.type = CXL_DEVTYPE_CLASSMEM; > + mds->cxlds.capabilities = CXL_DRIVER_CAP_HDM | > CXL_DRIVER_CAP_MBOX; mds->ram_perf.qos_class = CXL_QOS_CLASS_INVALID; > mds->pmem_perf.qos_class = CXL_QOS_CLASS_INVALID; > > diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c > index 04c3a0f8bc2e..b4205ecca365 100644 > --- a/drivers/cxl/core/memdev.c > +++ b/drivers/cxl/core/memdev.c > @@ -616,7 +616,7 @@ static void detach_memdev(struct work_struct > *work) > static struct lock_class_key cxl_memdev_key; > > -struct cxl_dev_state *cxl_accel_state_create(struct device *dev) > +struct cxl_dev_state *cxl_accel_state_create(struct device *dev, > uint8_t caps) { > struct cxl_dev_state *cxlds; > > @@ -631,6 +631,8 @@ struct cxl_dev_state > *cxl_accel_state_create(struct device *dev) cxlds->ram_res = > DEFINE_RES_MEM_NAMED(0, 0, "ram"); cxlds->pmem_res = > DEFINE_RES_MEM_NAMED(0, 0, "pmem"); > + cxlds->capabilities = caps; > + > return cxlds; > } > EXPORT_SYMBOL_NS_GPL(cxl_accel_state_create, CXL); > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index 887ed6e358fb..d66c6349ed2d 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -763,7 +763,7 @@ static int cxl_setup_comp_regs(struct device > *host, struct cxl_register_map *map map->reg_type = > CXL_REGLOC_RBI_COMPONENT; map->max_size = > CXL_COMPONENT_REG_BLOCK_SIZE; > - return cxl_setup_regs(map); > + return cxl_setup_regs(map, 0); > } > > static int cxl_port_setup_regs(struct cxl_port *port, > diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c > index e1082e749c69..9d218ebe180d 100644 > --- a/drivers/cxl/core/regs.c > +++ b/drivers/cxl/core/regs.c > @@ -421,7 +421,7 @@ static void cxl_unmap_regblock(struct > cxl_register_map *map) map->base = NULL; > } > > -static int cxl_probe_regs(struct cxl_register_map *map) > +static int cxl_probe_regs(struct cxl_register_map *map, uint8_t caps) > { Can we not use uintxx_t? Just like any other one in the cxl-core. Generally, u{8,16...} are mostly used for kernel programming, and your previous patches use them nicely. Let's use u8 for caps. > struct cxl_component_reg_map *comp_map; > struct cxl_device_reg_map *dev_map; > @@ -437,11 +437,12 @@ static int cxl_probe_regs(struct > cxl_register_map *map) case CXL_REGLOC_RBI_MEMDEV: > dev_map = &map->device_map; > cxl_probe_device_regs(host, base, dev_map); > - if (!dev_map->status.valid || !dev_map->mbox.valid || > + if (!dev_map->status.valid || > + ((caps & CXL_DRIVER_CAP_MBOX) && > !dev_map->mbox.valid) || !dev_map->memdev.valid) { > dev_err(host, "registers not found: > %s%s%s\n", !dev_map->status.valid ? "status " : "", > - !dev_map->mbox.valid ? "mbox " : "", > + ((caps & CXL_DRIVER_CAP_MBOX) && > !dev_map->mbox.valid) ? "mbox " : "", !dev_map->memdev.valid ? > "memdev " : ""); return -ENXIO; > } > @@ -455,7 +456,7 @@ static int cxl_probe_regs(struct cxl_register_map > *map) return 0; > } > > -int cxl_setup_regs(struct cxl_register_map *map) > +int cxl_setup_regs(struct cxl_register_map *map, uint8_t caps) > { > int rc; > > @@ -463,7 +464,7 @@ int cxl_setup_regs(struct cxl_register_map *map) > if (rc) > return rc; > > - rc = cxl_probe_regs(map); > + rc = cxl_probe_regs(map, caps); > cxl_unmap_regblock(map); > > return rc; > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index a6613a6f8923..9973430d975f 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -300,7 +300,7 @@ int cxl_find_regblock_instance(struct pci_dev > *pdev, enum cxl_regloc_type type, struct cxl_register_map *map, int > index); int cxl_find_regblock(struct pci_dev *pdev, enum > cxl_regloc_type type, struct cxl_register_map *map); > -int cxl_setup_regs(struct cxl_register_map *map); > +int cxl_setup_regs(struct cxl_register_map *map, uint8_t caps); > struct cxl_dport; > resource_size_t cxl_rcd_component_reg_phys(struct device *dev, > struct cxl_dport *dport); > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h > index af8169ccdbc0..8f2a820bd92d 100644 > --- a/drivers/cxl/cxlmem.h > +++ b/drivers/cxl/cxlmem.h > @@ -405,6 +405,9 @@ struct cxl_dpa_perf { > int qos_class; > }; > > +#define CXL_DRIVER_CAP_HDM 0x1 > +#define CXL_DRIVER_CAP_MBOX 0x2 > + > /** > * struct cxl_dev_state - The driver device state > * > @@ -438,6 +441,7 @@ struct cxl_dev_state { > struct resource ram_res; > u64 serial; > enum cxl_devtype type; > + uint8_t capabilities; > }; > > /** > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index b34d6259faf4..e2a978312281 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -502,7 +502,8 @@ static int cxl_rcrb_get_comp_regs(struct pci_dev > *pdev, } > > static int cxl_pci_setup_regs(struct pci_dev *pdev, enum > cxl_regloc_type type, > - struct cxl_register_map *map) > + struct cxl_register_map *map, > + uint8_t cxl_dev_caps) > { > int rc; > > @@ -519,7 +520,7 @@ static int cxl_pci_setup_regs(struct pci_dev > *pdev, enum cxl_regloc_type type, if (rc) > return rc; > > - return cxl_setup_regs(map); > + return cxl_setup_regs(map, cxl_dev_caps); > } > > int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct > cxl_dev_state *cxlds) @@ -527,7 +528,8 @@ int > cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state > *cxlds) struct cxl_register_map map; int rc; > > - rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, > + cxlds->capabilities); > if (rc) > return rc; > > @@ -536,7 +538,7 @@ int cxl_pci_accel_setup_regs(struct pci_dev > *pdev, struct cxl_dev_state *cxlds) return rc; > > rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > - &cxlds->reg_map); > + &cxlds->reg_map, > cxlds->capabilities); if (rc) > dev_warn(&pdev->dev, "No component registers > (%d)\n", rc); > @@ -850,7 +852,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, > const struct pci_device_id *id) dev_warn(&pdev->dev, > "Device DVSEC not present, skip CXL.mem > init\n"); > - rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, > + cxlds->capabilities); > if (rc) > return rc; > > @@ -863,7 +866,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, > const struct pci_device_id *id) > * still be useful for management functions so don't return > an error. */ > rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > - &cxlds->reg_map); > + &cxlds->reg_map, > cxlds->capabilities); if (rc) > dev_warn(&pdev->dev, "No component registers > (%d)\n", rc); else if (!cxlds->reg_map.component_map.ras.valid) > diff --git a/drivers/net/ethernet/sfc/efx_cxl.c > b/drivers/net/ethernet/sfc/efx_cxl.c index 9cefcaf3caca..37d8bfdef517 > 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c > +++ b/drivers/net/ethernet/sfc/efx_cxl.c > @@ -33,7 +33,8 @@ void efx_cxl_init(struct efx_nic *efx) > > pci_info(pci_dev, "CXL CXL_DVSEC_PCIE_DEVICE capability > found"); > - cxl->cxlds = cxl_accel_state_create(&pci_dev->dev); > + cxl->cxlds = cxl_accel_state_create(&pci_dev->dev, > + > CXL_ACCEL_DRIVER_CAP_HDM); if (IS_ERR(cxl->cxlds)) { > pci_info(pci_dev, "CXL accel device state failed"); > return; > diff --git a/include/linux/cxl_accel_mem.h > b/include/linux/cxl_accel_mem.h index c7b254edc096..0ba2195b919b > 100644 --- a/include/linux/cxl_accel_mem.h > +++ b/include/linux/cxl_accel_mem.h > @@ -12,8 +12,11 @@ enum accel_resource{ > CXL_ACCEL_RES_PMEM, > }; > > +#define CXL_ACCEL_DRIVER_CAP_HDM 0x1 > +#define CXL_ACCEL_DRIVER_CAP_MBOX 0x2 > + > typedef struct cxl_dev_state cxl_accel_state; > -cxl_accel_state *cxl_accel_state_create(struct device *dev); > +cxl_accel_state *cxl_accel_state_create(struct device *dev, uint8_t > caps); > void cxl_accel_set_dvsec(cxl_accel_state *cxlds, u16 dvsec); > void cxl_accel_set_serial(cxl_accel_state *cxlds, u64 serial);