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Fri, 9 Aug 2024 07:40:43 -0700 Date: Fri, 9 Aug 2024 17:40:43 +0300 From: Zhi Wang To: CC: , , , , , , , , , , Alejandro Lucero , Subject: Re: [PATCH v2 08/15] cxl: indicate probe deferral Message-ID: <20240809174043.0000011a.zhiw@nvidia.com> In-Reply-To: <20240715172835.24757-9-alejandro.lucero-palau@amd.com> References: <20240715172835.24757-1-alejandro.lucero-palau@amd.com> <20240715172835.24757-9-alejandro.lucero-palau@amd.com> Organization: NVIDIA X-Mailer: Claws Mail 4.2.0 (GTK 3.24.38; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000144:EE_|PH7PR12MB8779:EE_ X-MS-Office365-Filtering-Correlation-Id: db972046-062c-4194-127c-08dcb8814a3c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700013; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Aug 2024 14:41:01.3791 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db972046-062c-4194-127c-08dcb8814a3c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000144.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8779 On Mon, 15 Jul 2024 18:28:28 +0100 wrote: Another spell check is spotted besides others review threads. Will circle back with more comments once checking the users of the APIs. > From: Alejandro Lucero > > The first stop for a CXL accelerator driver that wants to establish > new CXL.mem regions is to register a 'struct cxl_memdev. That kicks > off cxl_mem_probe() to enumerate all 'struct cxl_port' instances in > the topology up to the root. > > If the root driver has not attached yet the expectation is that the > driver waits until that link is established. The common cxl_pci_driver > has reason to keep the 'struct cxl_memdev' device attached to the bus > until the root driver attaches. An accelerator may want to instead > defer probing until CXL resources can be acquired. > > Use the @endpoint attribute of a 'struct cxl_memdev' to convey when > accelerator driver probing should be defferred vs failed. Provide that ^deferred > indication via a new cxl_acquire_endpoint() API that can retrieve the > probe status of the memdev. > > The first consumer of this API is a test driver that excercises the > CXL Type-2 flow. > > Based on > https://lore.kernel.org/linux-cxl/168592149709.1948938.8663425987110396027.stgit@dwillia2-xfh.jf.intel.com/T/#m18497367d2ae38f88e94c06369eaa83fa23e92b2 > > Signed-off-by: Alejandro Lucero > Co-developed-by: Dan Williams > --- > drivers/cxl/core/memdev.c | 41 > ++++++++++++++++++++++++++++++ drivers/cxl/core/port.c | > 2 +- drivers/cxl/mem.c | 7 +++-- > drivers/net/ethernet/sfc/efx_cxl.c | 10 +++++++- > include/linux/cxl_accel_mem.h | 3 +++ > 5 files changed, 59 insertions(+), 4 deletions(-) > > diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c > index b902948b121f..d51c8bfb32e3 100644 > --- a/drivers/cxl/core/memdev.c > +++ b/drivers/cxl/core/memdev.c > @@ -1137,6 +1137,47 @@ struct cxl_memdev *devm_cxl_add_memdev(struct > device *host, } > EXPORT_SYMBOL_NS_GPL(devm_cxl_add_memdev, CXL); > > +/* > + * Try to get a locked reference on a memdev's CXL port topology > + * connection. Be careful to observe when cxl_mem_probe() has > deposited > + * a probe deferral awaiting the arrival of the CXL root driver > +*/ > +struct cxl_port *cxl_acquire_endpoint(struct cxl_memdev *cxlmd) > +{ > + struct cxl_port *endpoint; > + int rc = -ENXIO; > + > + device_lock(&cxlmd->dev); > + endpoint = cxlmd->endpoint; > + if (!endpoint) > + goto err; > + > + if (IS_ERR(endpoint)) { > + rc = PTR_ERR(endpoint); > + goto err; > + } > + > + device_lock(&endpoint->dev); > + if (!endpoint->dev.driver) > + goto err_endpoint; > + > + return endpoint; > + > +err_endpoint: > + device_unlock(&endpoint->dev); > +err: > + device_unlock(&cxlmd->dev); > + return ERR_PTR(rc); > +} > +EXPORT_SYMBOL_NS(cxl_acquire_endpoint, CXL); > + > +void cxl_release_endpoint(struct cxl_memdev *cxlmd, struct cxl_port > *endpoint) +{ > + device_unlock(&endpoint->dev); > + device_unlock(&cxlmd->dev); > +} > +EXPORT_SYMBOL_NS(cxl_release_endpoint, CXL); > + > static void sanitize_teardown_notifier(void *data) > { > struct cxl_memdev_state *mds = data; > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index d66c6349ed2d..3c6b896c5f65 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -1553,7 +1553,7 @@ static int add_port_attach_ep(struct cxl_memdev > *cxlmd, */ > dev_dbg(&cxlmd->dev, "%s is a root dport\n", > dev_name(dport_dev)); > - return -ENXIO; > + return -EPROBE_DEFER; > } > > parent_port = find_cxl_port(dparent, &parent_dport); > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index f76af75a87b7..383a6f4829d3 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c > @@ -145,13 +145,16 @@ static int cxl_mem_probe(struct device *dev) > return rc; > > rc = devm_cxl_enumerate_ports(cxlmd); > - if (rc) > + if (rc) { > + cxlmd->endpoint = ERR_PTR(rc); > return rc; > + } > > parent_port = cxl_mem_find_port(cxlmd, &dport); > if (!parent_port) { > dev_err(dev, "CXL port topology not found\n"); > - return -ENXIO; > + cxlmd->endpoint = ERR_PTR(-EPROBE_DEFER); > + return -EPROBE_DEFER; > } > > if (resource_size(&cxlds->pmem_res) && > IS_ENABLED(CONFIG_CXL_PMEM)) { diff --git > a/drivers/net/ethernet/sfc/efx_cxl.c > b/drivers/net/ethernet/sfc/efx_cxl.c index 0abe66490ef5..2cf4837ddfc1 > 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c +++ > b/drivers/net/ethernet/sfc/efx_cxl.c @@ -65,8 +65,16 @@ void > efx_cxl_init(struct efx_nic *efx) } > > cxl->cxlmd = devm_cxl_add_memdev(&pci_dev->dev, cxl->cxlds); > - if (IS_ERR(cxl->cxlmd)) > + if (IS_ERR(cxl->cxlmd)) { > pci_info(pci_dev, "CXL accel memdev creation > failed"); > + return; > + } > + > + cxl->endpoint = cxl_acquire_endpoint(cxl->cxlmd); > + if (IS_ERR(cxl->endpoint)) > + pci_info(pci_dev, "CXL accel acquire endpoint > failed"); + > + cxl_release_endpoint(cxl->cxlmd, cxl->endpoint); > } > > > diff --git a/include/linux/cxl_accel_mem.h > b/include/linux/cxl_accel_mem.h index 442ed9862292..701910021df8 > 100644 --- a/include/linux/cxl_accel_mem.h > +++ b/include/linux/cxl_accel_mem.h > @@ -29,4 +29,7 @@ int cxl_await_media_ready(struct cxl_dev_state > *cxlds); > struct cxl_memdev *devm_cxl_add_memdev(struct device *host, > struct cxl_dev_state *cxlds); > + > +struct cxl_port *cxl_acquire_endpoint(struct cxl_memdev *cxlmd); > +void cxl_release_endpoint(struct cxl_memdev *cxlmd, struct cxl_port > *endpoint); #endif