[net PATCH v2] octeontx2-af: Fix CPT AF register offset calculation

[net PATCH v2] octeontx2-af: Fix CPT AF register offset calculation

[Bharat Bhushan]

Some CPT AF registers are per LF and others are global.
Translation of PF/VF local LF slot number to actual LF slot
number is required only for accessing perf LF registers.
CPT AF global registers access do not require any LF
slot number.

Also there is no reason CPT PF/VF to know actual lf's register
offset.

Fixes: bc35e28af789 ("octeontx2-af: replace cpt slot with lf id on reg write")
Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
---
 .../ethernet/marvell/octeontx2/af/rvu_cpt.c   | 23 +++++++++----------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
index 3e09d2285814..daf4b951e905 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
@@ -632,7 +632,9 @@ int rvu_mbox_handler_cpt_inline_ipsec_cfg(struct rvu *rvu,
 	return ret;
 }
 
-static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req)
+static bool validate_and_update_reg_offset(struct rvu *rvu,
+					   struct cpt_rd_wr_reg_msg *req,
+					   u64 *reg_offset)
 {
 	u64 offset = req->reg_offset;
 	int blkaddr, num_lfs, lf;
@@ -663,6 +665,11 @@ static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req)
 		if (lf < 0)
 			return false;
 
+		/* Translate local LF's offset to global CPT LF's offset to
+		 * access LFX register.
+		 */
+		*reg_offset = (req->reg_offset & 0xFF000) + (lf << 3);
+
 		return true;
 	} else if (!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK)) {
 		/* Registers that can be accessed from PF */
@@ -697,7 +704,7 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu,
 					struct cpt_rd_wr_reg_msg *rsp)
 {
 	u64 offset = req->reg_offset;
-	int blkaddr, lf;
+	int blkaddr;
 
 	blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
 	if (blkaddr < 0)
@@ -708,18 +715,10 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu,
 	    !is_cpt_vf(rvu, req->hdr.pcifunc))
 		return CPT_AF_ERR_ACCESS_DENIED;
 
-	if (!is_valid_offset(rvu, req))
+	if (!validate_and_update_reg_offset(rvu, req, &offset))
 		return CPT_AF_ERR_ACCESS_DENIED;
 
-	/* Translate local LF used by VFs to global CPT LF */
-	lf = rvu_get_lf(rvu, &rvu->hw->block[blkaddr], req->hdr.pcifunc,
-			(offset & 0xFFF) >> 3);
-
-	/* Translate local LF's offset to global CPT LF's offset */
-	offset &= 0xFF000;
-	offset += lf << 3;
-
-	rsp->reg_offset = offset;
+	rsp->reg_offset = req->reg_offset;
 	rsp->ret_val = req->ret_val;
 	rsp->is_write = req->is_write;
 
-- 
2.34.1

Re: [net PATCH v2] octeontx2-af: Fix CPT AF register offset calculation

[Simon Horman]

On Mon, Aug 19, 2024 at 06:02:37PM +0530, Bharat Bhushan wrote:
> Some CPT AF registers are per LF and others are global.
> Translation of PF/VF local LF slot number to actual LF slot
> number is required only for accessing perf LF registers.
> CPT AF global registers access do not require any LF
> slot number.
> 
> Also there is no reason CPT PF/VF to know actual lf's register
> offset.
> 
> Fixes: bc35e28af789 ("octeontx2-af: replace cpt slot with lf id on reg write")
> Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
> ---

Hi Bharat,

It would be very nice to have links (to lore) to earlier version and
descriptions of what has changed between versions here.

Using b4 to manage patch submissions will help with this.

Re: [net PATCH v2] octeontx2-af: Fix CPT AF register offset calculation

[Jakub Kicinski]

On Mon, 19 Aug 2024 18:02:37 +0530 Bharat Bhushan wrote:
> Some CPT AF registers are per LF and others are global.
> Translation of PF/VF local LF slot number to actual LF slot
> number is required only for accessing perf LF registers.
> CPT AF global registers access do not require any LF
> slot number.

You need to add examples of features which are broken without this fix
into the commit message.
-- 
pw-bot: cr

Re: [net PATCH v2] octeontx2-af: Fix CPT AF register offset calculation

[Bharat Bhushan]

On Tue, Aug 20, 2024 at 5:58 AM Jakub Kicinski <kuba@kernel.org> wrote:
>
> On Mon, 19 Aug 2024 18:02:37 +0530 Bharat Bhushan wrote:
> > Some CPT AF registers are per LF and others are global.
> > Translation of PF/VF local LF slot number to actual LF slot
> > number is required only for accessing perf LF registers.
> > CPT AF global registers access do not require any LF
> > slot number.
>
> You need to add examples of features which are broken without this fix
> into the commit message.

okay, will update below to commit message

"    Without this fix microcode loading will fail, VFs cannot be created
    and hardware is not usable.
"

Thanks
-Bharat

> --
> pw-bot: cr
>

Re: [net PATCH v2] octeontx2-af: Fix CPT AF register offset calculation

[Bharat Bhushan]

On Mon, Aug 19, 2024 at 8:57 PM Simon Horman <horms@kernel.org> wrote:
>
> On Mon, Aug 19, 2024 at 06:02:37PM +0530, Bharat Bhushan wrote:
> > Some CPT AF registers are per LF and others are global.
> > Translation of PF/VF local LF slot number to actual LF slot
> > number is required only for accessing perf LF registers.
> > CPT AF global registers access do not require any LF
> > slot number.
> >
> > Also there is no reason CPT PF/VF to know actual lf's register
> > offset.
> >
> > Fixes: bc35e28af789 ("octeontx2-af: replace cpt slot with lf id on reg write")
> > Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
> > ---
>
> Hi Bharat,
>
> It would be very nice to have links (to lore) to earlier version and
> descriptions of what has changed between versions here.

Hi Simon,

Will add below in next version of this patch

v3:
  - Updated patch description about what's broken without this fix
  - Added patch history

v2: https://lore.kernel.org/netdev/20240819152744.GA543198@kernel.org/T/
  - Spelling fixes in patch description

v1: https://lore.kernel.org/lkml/CAAeCc_nJtR2ryzoaXop8-bbw_0RGciZsniiUqS+NVMg7dHahiQ@mail.gmail.com/T/
  - Added "net" in patch subject prefix, missed in previous patch:
    https://lore.kernel.org/lkml/20240806070239.1541623-1-bbhushan2@marvell.com/


Thanks
-Bharat

>
> Using b4 to manage patch submissions will help with this.
>

Re: [net PATCH v2] octeontx2-af: Fix CPT AF register offset calculation

[Simon Horman]

On Tue, Aug 20, 2024 at 04:37:02PM +0530, Bharat Bhushan wrote:
> On Mon, Aug 19, 2024 at 8:57 PM Simon Horman <horms@kernel.org> wrote:
> >
> > On Mon, Aug 19, 2024 at 06:02:37PM +0530, Bharat Bhushan wrote:
> > > Some CPT AF registers are per LF and others are global.
> > > Translation of PF/VF local LF slot number to actual LF slot
> > > number is required only for accessing perf LF registers.
> > > CPT AF global registers access do not require any LF
> > > slot number.
> > >
> > > Also there is no reason CPT PF/VF to know actual lf's register
> > > offset.
> > >
> > > Fixes: bc35e28af789 ("octeontx2-af: replace cpt slot with lf id on reg write")
> > > Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
> > > ---
> >
> > Hi Bharat,
> >
> > It would be very nice to have links (to lore) to earlier version and
> > descriptions of what has changed between versions here.
> 
> Hi Simon,
> 
> Will add below in next version of this patch

Thanks, much appreciated.

> v3:
>   - Updated patch description about what's broken without this fix
>   - Added patch history
> 
> v2: https://lore.kernel.org/netdev/20240819152744.GA543198@kernel.org/T/
>   - Spelling fixes in patch description
> 
> v1: https://lore.kernel.org/lkml/CAAeCc_nJtR2ryzoaXop8-bbw_0RGciZsniiUqS+NVMg7dHahiQ@mail.gmail.com/T/
>   - Added "net" in patch subject prefix, missed in previous patch:
>     https://lore.kernel.org/lkml/20240806070239.1541623-1-bbhushan2@marvell.com/
> 
> 
> Thanks
> -Bharat
> 
> >
> > Using b4 to manage patch submissions will help with this.
> >
>