* [PATCHv2 net-next] net: ag71xx: update FIFO bits and descriptions
@ 2024-08-28 22:38 Rosen Penev
2024-08-29 16:52 ` Simon Horman
0 siblings, 1 reply; 7+ messages in thread
From: Rosen Penev @ 2024-08-28 22:38 UTC (permalink / raw)
To: netdev
Cc: davem, edumazet, kuba, pabeni, linux, linux-kernel, o.rempel,
p.zabel
Taken from QCA SDK. No functional difference as same bits get applied.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
v2: forgot to send to netdev
drivers/net/ethernet/atheros/ag71xx.c | 48 +++++++++++++--------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/net/ethernet/atheros/ag71xx.c b/drivers/net/ethernet/atheros/ag71xx.c
index db2a8ade6205..692dbded8211 100644
--- a/drivers/net/ethernet/atheros/ag71xx.c
+++ b/drivers/net/ethernet/atheros/ag71xx.c
@@ -149,11 +149,11 @@
#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
#define FIFO_CFG4_DR BIT(10) /* Dribble */
-#define FIFO_CFG4_LE BIT(11) /* Long Event */
-#define FIFO_CFG4_CF BIT(12) /* Control Frame */
-#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
-#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
-#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
+#define FIFO_CFG4_CF BIT(11) /* Control Frame */
+#define FIFO_CFG4_PF BIT(12) /* Pause Frame */
+#define FIFO_CFG4_UO BIT(13) /* Unsupported Opcode */
+#define FIFO_CFG4_VT BIT(14) /* VLAN tag detected */
+#define FIFO_CFG4_LE BIT(15) /* Long Event */
#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
@@ -168,28 +168,28 @@
#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
#define FIFO_CFG5_FC BIT(2) /* False Carrier */
#define FIFO_CFG5_CE BIT(3) /* Code Error */
-#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
-#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
-#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
-#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
-#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
-#define FIFO_CFG5_DR BIT(9) /* Dribble */
-#define FIFO_CFG5_CF BIT(10) /* Control Frame */
-#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
-#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
-#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
-#define FIFO_CFG5_LE BIT(14) /* Long Event */
-#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
-#define FIFO_CFG5_16 BIT(16) /* unknown */
-#define FIFO_CFG5_17 BIT(17) /* unknown */
+#define FIFO_CFG5_CR BIT(4) /* CRC error */
+#define FIFO_CFG5_LM BIT(5) /* Length Mismatch */
+#define FIFO_CFG5_LO BIT(6) /* Length Out of Range */
+#define FIFO_CFG5_OK BIT(7) /* Packet is OK */
+#define FIFO_CFG5_MC BIT(8) /* Multicast Packet */
+#define FIFO_CFG5_BC BIT(9) /* Broadcast Packet */
+#define FIFO_CFG5_DR BIT(10) /* Dribble */
+#define FIFO_CFG5_CF BIT(11) /* Control Frame */
+#define FIFO_CFG5_PF BIT(12) /* Pause Frame */
+#define FIFO_CFG5_UO BIT(13) /* Unsupported Opcode */
+#define FIFO_CFG5_VT BIT(14) /* VLAN tag detected */
+#define FIFO_CFG5_LE BIT(15) /* Long Event */
+#define FIFO_CFG5_FT BIT(16) /* Frame Truncated */
+#define FIFO_CFG5_UC BIT(17) /* Unicast Packet */
#define FIFO_CFG5_SF BIT(18) /* Short Frame */
#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
- FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
- FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
- FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
- FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
- FIFO_CFG5_17 | FIFO_CFG5_SF)
+ FIFO_CFG5_CE | FIFO_CFG5_LM | FIFO_CFG5_L0 | \
+ FIFO_CFG5_OK | FIFO_CFG5_MC | FIFO_CFG5_BC | \
+ FIFO_CFG5_DR | FIFO_CFG5_CF | FIFO_CFG5_UO | \
+ FIFO_CFG5_VT | FIFO_CFG5_LE | FIFO_CFG5_FT | \
+ FIFO_CFG5_UC | FIFO_CFG5_SF)
#define AG71XX_REG_TX_CTRL 0x0180
#define TX_CTRL_TXE BIT(0) /* Tx Enable */
--
2.46.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCHv2 net-next] net: ag71xx: update FIFO bits and descriptions
2024-08-28 22:38 [PATCHv2 net-next] net: ag71xx: update FIFO bits and descriptions Rosen Penev
@ 2024-08-29 16:52 ` Simon Horman
2024-08-29 17:47 ` Rosen Penev
0 siblings, 1 reply; 7+ messages in thread
From: Simon Horman @ 2024-08-29 16:52 UTC (permalink / raw)
To: Rosen Penev
Cc: netdev, davem, edumazet, kuba, pabeni, linux, linux-kernel,
o.rempel, p.zabel
On Wed, Aug 28, 2024 at 03:38:47PM -0700, Rosen Penev wrote:
> Taken from QCA SDK. No functional difference as same bits get applied.
>
> Signed-off-by: Rosen Penev <rosenp@gmail.com>
> ---
> v2: forgot to send to netdev
> drivers/net/ethernet/atheros/ag71xx.c | 48 +++++++++++++--------------
> 1 file changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/net/ethernet/atheros/ag71xx.c b/drivers/net/ethernet/atheros/ag71xx.c
> index db2a8ade6205..692dbded8211 100644
> --- a/drivers/net/ethernet/atheros/ag71xx.c
> +++ b/drivers/net/ethernet/atheros/ag71xx.c
> @@ -149,11 +149,11 @@
> #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
> #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
> #define FIFO_CFG4_DR BIT(10) /* Dribble */
> -#define FIFO_CFG4_LE BIT(11) /* Long Event */
> -#define FIFO_CFG4_CF BIT(12) /* Control Frame */
> -#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
> -#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
> -#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
> +#define FIFO_CFG4_CF BIT(11) /* Control Frame */
> +#define FIFO_CFG4_PF BIT(12) /* Pause Frame */
> +#define FIFO_CFG4_UO BIT(13) /* Unsupported Opcode */
> +#define FIFO_CFG4_VT BIT(14) /* VLAN tag detected */
> +#define FIFO_CFG4_LE BIT(15) /* Long Event */
> #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
> #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
> #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
> @@ -168,28 +168,28 @@
> #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
> #define FIFO_CFG5_FC BIT(2) /* False Carrier */
> #define FIFO_CFG5_CE BIT(3) /* Code Error */
> -#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
> -#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
> -#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
> -#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
> -#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
> -#define FIFO_CFG5_DR BIT(9) /* Dribble */
> -#define FIFO_CFG5_CF BIT(10) /* Control Frame */
> -#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
> -#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
> -#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
> -#define FIFO_CFG5_LE BIT(14) /* Long Event */
> -#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
> -#define FIFO_CFG5_16 BIT(16) /* unknown */
> -#define FIFO_CFG5_17 BIT(17) /* unknown */
> +#define FIFO_CFG5_CR BIT(4) /* CRC error */
> +#define FIFO_CFG5_LM BIT(5) /* Length Mismatch */
> +#define FIFO_CFG5_LO BIT(6) /* Length Out of Range */
> +#define FIFO_CFG5_OK BIT(7) /* Packet is OK */
> +#define FIFO_CFG5_MC BIT(8) /* Multicast Packet */
> +#define FIFO_CFG5_BC BIT(9) /* Broadcast Packet */
> +#define FIFO_CFG5_DR BIT(10) /* Dribble */
> +#define FIFO_CFG5_CF BIT(11) /* Control Frame */
> +#define FIFO_CFG5_PF BIT(12) /* Pause Frame */
> +#define FIFO_CFG5_UO BIT(13) /* Unsupported Opcode */
> +#define FIFO_CFG5_VT BIT(14) /* VLAN tag detected */
> +#define FIFO_CFG5_LE BIT(15) /* Long Event */
> +#define FIFO_CFG5_FT BIT(16) /* Frame Truncated */
> +#define FIFO_CFG5_UC BIT(17) /* Unicast Packet */
> #define FIFO_CFG5_SF BIT(18) /* Short Frame */
> #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
> #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
> - FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
> - FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
> - FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
> - FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
> - FIFO_CFG5_17 | FIFO_CFG5_SF)
> + FIFO_CFG5_CE | FIFO_CFG5_LM | FIFO_CFG5_L0 | \
FIFO_CFG5_LO
> + FIFO_CFG5_OK | FIFO_CFG5_MC | FIFO_CFG5_BC | \
> + FIFO_CFG5_DR | FIFO_CFG5_CF | FIFO_CFG5_UO | \
> + FIFO_CFG5_VT | FIFO_CFG5_LE | FIFO_CFG5_FT | \
> + FIFO_CFG5_UC | FIFO_CFG5_SF)
>
> #define AG71XX_REG_TX_CTRL 0x0180
> #define TX_CTRL_TXE BIT(0) /* Tx Enable */
Please consider a patch to allow compilation of this driver with
COMPILE_TEST in order to increase build coverage.
--
pw-bot: cr
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCHv2 net-next] net: ag71xx: update FIFO bits and descriptions
2024-08-29 16:52 ` Simon Horman
@ 2024-08-29 17:47 ` Rosen Penev
2024-08-29 19:47 ` Jakub Kicinski
2024-08-29 20:19 ` Simon Horman
0 siblings, 2 replies; 7+ messages in thread
From: Rosen Penev @ 2024-08-29 17:47 UTC (permalink / raw)
To: Simon Horman
Cc: netdev, davem, edumazet, kuba, pabeni, linux, linux-kernel,
o.rempel, p.zabel
On Thu, Aug 29, 2024 at 9:52 AM Simon Horman <horms@kernel.org> wrote:
>
> On Wed, Aug 28, 2024 at 03:38:47PM -0700, Rosen Penev wrote:
> > Taken from QCA SDK. No functional difference as same bits get applied.
> >
> > Signed-off-by: Rosen Penev <rosenp@gmail.com>
> > ---
> > v2: forgot to send to netdev
> > drivers/net/ethernet/atheros/ag71xx.c | 48 +++++++++++++--------------
> > 1 file changed, 24 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/atheros/ag71xx.c b/drivers/net/ethernet/atheros/ag71xx.c
> > index db2a8ade6205..692dbded8211 100644
> > --- a/drivers/net/ethernet/atheros/ag71xx.c
> > +++ b/drivers/net/ethernet/atheros/ag71xx.c
> > @@ -149,11 +149,11 @@
> > #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
> > #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
> > #define FIFO_CFG4_DR BIT(10) /* Dribble */
> > -#define FIFO_CFG4_LE BIT(11) /* Long Event */
> > -#define FIFO_CFG4_CF BIT(12) /* Control Frame */
> > -#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
> > -#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
> > -#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
> > +#define FIFO_CFG4_CF BIT(11) /* Control Frame */
> > +#define FIFO_CFG4_PF BIT(12) /* Pause Frame */
> > +#define FIFO_CFG4_UO BIT(13) /* Unsupported Opcode */
> > +#define FIFO_CFG4_VT BIT(14) /* VLAN tag detected */
> > +#define FIFO_CFG4_LE BIT(15) /* Long Event */
> > #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
> > #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
> > #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
> > @@ -168,28 +168,28 @@
> > #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
> > #define FIFO_CFG5_FC BIT(2) /* False Carrier */
> > #define FIFO_CFG5_CE BIT(3) /* Code Error */
> > -#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
> > -#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
> > -#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
> > -#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
> > -#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
> > -#define FIFO_CFG5_DR BIT(9) /* Dribble */
> > -#define FIFO_CFG5_CF BIT(10) /* Control Frame */
> > -#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
> > -#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
> > -#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
> > -#define FIFO_CFG5_LE BIT(14) /* Long Event */
> > -#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
> > -#define FIFO_CFG5_16 BIT(16) /* unknown */
> > -#define FIFO_CFG5_17 BIT(17) /* unknown */
> > +#define FIFO_CFG5_CR BIT(4) /* CRC error */
> > +#define FIFO_CFG5_LM BIT(5) /* Length Mismatch */
> > +#define FIFO_CFG5_LO BIT(6) /* Length Out of Range */
> > +#define FIFO_CFG5_OK BIT(7) /* Packet is OK */
> > +#define FIFO_CFG5_MC BIT(8) /* Multicast Packet */
> > +#define FIFO_CFG5_BC BIT(9) /* Broadcast Packet */
> > +#define FIFO_CFG5_DR BIT(10) /* Dribble */
> > +#define FIFO_CFG5_CF BIT(11) /* Control Frame */
> > +#define FIFO_CFG5_PF BIT(12) /* Pause Frame */
> > +#define FIFO_CFG5_UO BIT(13) /* Unsupported Opcode */
> > +#define FIFO_CFG5_VT BIT(14) /* VLAN tag detected */
> > +#define FIFO_CFG5_LE BIT(15) /* Long Event */
> > +#define FIFO_CFG5_FT BIT(16) /* Frame Truncated */
> > +#define FIFO_CFG5_UC BIT(17) /* Unicast Packet */
> > #define FIFO_CFG5_SF BIT(18) /* Short Frame */
> > #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
> > #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
> > - FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
> > - FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
> > - FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
> > - FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
> > - FIFO_CFG5_17 | FIFO_CFG5_SF)
> > + FIFO_CFG5_CE | FIFO_CFG5_LM | FIFO_CFG5_L0 | \
>
> FIFO_CFG5_LO
>
> > + FIFO_CFG5_OK | FIFO_CFG5_MC | FIFO_CFG5_BC | \
> > + FIFO_CFG5_DR | FIFO_CFG5_CF | FIFO_CFG5_UO | \
> > + FIFO_CFG5_VT | FIFO_CFG5_LE | FIFO_CFG5_FT | \
> > + FIFO_CFG5_UC | FIFO_CFG5_SF)
> >
> > #define AG71XX_REG_TX_CTRL 0x0180
> > #define TX_CTRL_TXE BIT(0) /* Tx Enable */
>
> Please consider a patch to allow compilation of this driver with
> COMPILE_TEST in order to increase build coverage.
Is that just
--- a/drivers/net/ethernet/atheros/Kconfig
+++ b/drivers/net/ethernet/atheros/Kconfig
@@ -6,7 +6,7 @@
config NET_VENDOR_ATHEROS
bool "Atheros devices"
default y
- depends on (PCI || ATH79)
+ depends on (PCI || ATH79 || COMPILE_TEST)
help
If you have a network (Ethernet) card belonging to this class, say Y.
@@ -19,7 +19,7 @@ if NET_VENDOR_ATHEROS
config AG71XX
tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support"
- depends on ATH79
+ depends on ATH79 || COMPILE_TEST
select PHYLINK
imply NET_SELFTESTS
help
>
> --
> pw-bot: cr
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCHv2 net-next] net: ag71xx: update FIFO bits and descriptions
2024-08-29 17:47 ` Rosen Penev
@ 2024-08-29 19:47 ` Jakub Kicinski
2024-08-29 20:21 ` Rosen Penev
2024-08-29 20:19 ` Simon Horman
1 sibling, 1 reply; 7+ messages in thread
From: Jakub Kicinski @ 2024-08-29 19:47 UTC (permalink / raw)
To: Rosen Penev
Cc: Simon Horman, netdev, davem, edumazet, pabeni, linux,
linux-kernel, o.rempel, p.zabel
On Thu, 29 Aug 2024 10:47:01 -0700 Rosen Penev wrote:
> > Please consider a patch to allow compilation of this driver with
> > COMPILE_TEST in order to increase build coverage.
> Is that just
Aha, do that and run an allmodconfig build on x86 to make sure nothing
breaks. If it's all fine please submit
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCHv2 net-next] net: ag71xx: update FIFO bits and descriptions
2024-08-29 19:47 ` Jakub Kicinski
@ 2024-08-29 20:21 ` Rosen Penev
2024-08-29 20:55 ` Simon Horman
0 siblings, 1 reply; 7+ messages in thread
From: Rosen Penev @ 2024-08-29 20:21 UTC (permalink / raw)
To: Jakub Kicinski
Cc: Simon Horman, netdev, davem, edumazet, pabeni, linux,
linux-kernel, o.rempel, p.zabel
On Thu, Aug 29, 2024 at 12:47 PM Jakub Kicinski <kuba@kernel.org> wrote:
>
> On Thu, 29 Aug 2024 10:47:01 -0700 Rosen Penev wrote:
> > > Please consider a patch to allow compilation of this driver with
> > > COMPILE_TEST in order to increase build coverage.
> > Is that just
>
> Aha, do that and run an allmodconfig build on x86 to make sure nothing
> breaks. If it's all fine please submit
Funny enough it did break due to a mistake (L0 vs LO). I guess I'll
send a series just to keep these patches together.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCHv2 net-next] net: ag71xx: update FIFO bits and descriptions
2024-08-29 20:21 ` Rosen Penev
@ 2024-08-29 20:55 ` Simon Horman
0 siblings, 0 replies; 7+ messages in thread
From: Simon Horman @ 2024-08-29 20:55 UTC (permalink / raw)
To: Rosen Penev
Cc: Jakub Kicinski, netdev, davem, edumazet, pabeni, linux,
linux-kernel, o.rempel, p.zabel
On Thu, Aug 29, 2024 at 01:21:02PM -0700, Rosen Penev wrote:
> On Thu, Aug 29, 2024 at 12:47 PM Jakub Kicinski <kuba@kernel.org> wrote:
> >
> > On Thu, 29 Aug 2024 10:47:01 -0700 Rosen Penev wrote:
> > > > Please consider a patch to allow compilation of this driver with
> > > > COMPILE_TEST in order to increase build coverage.
> > > Is that just
> >
> > Aha, do that and run an allmodconfig build on x86 to make sure nothing
> > breaks. If it's all fine please submit
> Funny enough it did break due to a mistake (L0 vs LO).
Then I'd say this exercise is a success :)
> I guess I'll
> send a series just to keep these patches together.
In general, if you have multiple patches for the same driver,
for a single tree (net or net-next) I would either:
1) Send them as a series
2) Wait for one to be accepted before sending the next one
Option 1 seems appropriate here.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCHv2 net-next] net: ag71xx: update FIFO bits and descriptions
2024-08-29 17:47 ` Rosen Penev
2024-08-29 19:47 ` Jakub Kicinski
@ 2024-08-29 20:19 ` Simon Horman
1 sibling, 0 replies; 7+ messages in thread
From: Simon Horman @ 2024-08-29 20:19 UTC (permalink / raw)
To: Rosen Penev
Cc: netdev, davem, edumazet, kuba, pabeni, linux, linux-kernel,
o.rempel, p.zabel
On Thu, Aug 29, 2024 at 10:47:01AM -0700, Rosen Penev wrote:
> On Thu, Aug 29, 2024 at 9:52 AM Simon Horman <horms@kernel.org> wrote:
> >
> > On Wed, Aug 28, 2024 at 03:38:47PM -0700, Rosen Penev wrote:
> > > Taken from QCA SDK. No functional difference as same bits get applied.
> > >
> > > Signed-off-by: Rosen Penev <rosenp@gmail.com>
...
> > Please consider a patch to allow compilation of this driver with
> > COMPILE_TEST in order to increase build coverage.
> Is that just
Of course we should test that it works, but yes, I think so.
>
> --- a/drivers/net/ethernet/atheros/Kconfig
> +++ b/drivers/net/ethernet/atheros/Kconfig
> @@ -6,7 +6,7 @@
> config NET_VENDOR_ATHEROS
> bool "Atheros devices"
> default y
> - depends on (PCI || ATH79)
> + depends on (PCI || ATH79 || COMPILE_TEST)
FWIIW, I would drop the () while we are here.
> help
> If you have a network (Ethernet) card belonging to this class, say Y.
>
> @@ -19,7 +19,7 @@ if NET_VENDOR_ATHEROS
>
> config AG71XX
> tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support"
> - depends on ATH79
> + depends on ATH79 || COMPILE_TEST
> select PHYLINK
> imply NET_SELFTESTS
> help
>
> >
> > --
> > pw-bot: cr
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-08-29 20:55 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2024-08-28 22:38 [PATCHv2 net-next] net: ag71xx: update FIFO bits and descriptions Rosen Penev
2024-08-29 16:52 ` Simon Horman
2024-08-29 17:47 ` Rosen Penev
2024-08-29 19:47 ` Jakub Kicinski
2024-08-29 20:21 ` Rosen Penev
2024-08-29 20:55 ` Simon Horman
2024-08-29 20:19 ` Simon Horman
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