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Thu, 12 Sep 2024 02:19:11 -0700 Date: Thu, 12 Sep 2024 12:19:08 +0300 From: Zhi Wang To: CC: , , , , , , , , , Alejandro Lucero Subject: Re: [PATCH v3 10/20] cxl: indicate probe deferral Message-ID: <20240912121908.000054dc.zhiw@nvidia.com> In-Reply-To: <20240907081836.5801-11-alejandro.lucero-palau@amd.com> References: <20240907081836.5801-1-alejandro.lucero-palau@amd.com> <20240907081836.5801-11-alejandro.lucero-palau@amd.com> Organization: NVIDIA X-Mailer: Claws Mail 4.2.0 (GTK 3.24.38; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017095:EE_|CY8PR12MB7756:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e76884a-2bd7-4a57-0a10-08dcd30c00d8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|36860700013|1800799024; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 09:19:28.5744 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e76884a-2bd7-4a57-0a10-08dcd30c00d8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017095.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7756 On Sat, 7 Sep 2024 09:18:26 +0100 wrote: > From: Alejandro Lucero > Hi Alejandro: When working with V2, I noticed that if CONFIG_CXL_MEM=m and cxl_mem.ko is not loaded, loading the type-2 driver would fail on cxl_acquire_endpoint(). Not sure if you met the same problem. Now we are waiting for it to be loaded, it seems not ideal with the problem. Thanks, Zhi. > The first stop for a CXL accelerator driver that wants to establish > new CXL.mem regions is to register a 'struct cxl_memdev. That kicks > off cxl_mem_probe() to enumerate all 'struct cxl_port' instances in > the topology up to the root. > > If the root driver has not attached yet the expectation is that the > driver waits until that link is established. The common cxl_pci_driver > has reason to keep the 'struct cxl_memdev' device attached to the bus > until the root driver attaches. An accelerator may want to instead > defer probing until CXL resources can be acquired. > > Use the @endpoint attribute of a 'struct cxl_memdev' to convey when > accelerator driver probing should be deferred vs failed. Provide that > indication via a new cxl_acquire_endpoint() API that can retrieve the > probe status of the memdev. > > Based on > https://lore.kernel.org/linux-cxl/168592155270.1948938.11536845108449547920.stgit@dwillia2-xfh.jf.intel.com/ > > Signed-off-by: Alejandro Lucero > Co-developed-by: Dan Williams > --- > drivers/cxl/core/memdev.c | 67 > +++++++++++++++++++++++++++++++++++++++ drivers/cxl/core/port.c | > 2 +- drivers/cxl/mem.c | 4 ++- > include/linux/cxl/cxl.h | 2 ++ > 4 files changed, 73 insertions(+), 2 deletions(-) > > diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c > index 5f8418620b70..d4406cf3ed32 100644 > --- a/drivers/cxl/core/memdev.c > +++ b/drivers/cxl/core/memdev.c > @@ -5,6 +5,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -23,6 +24,8 @@ static DECLARE_RWSEM(cxl_memdev_rwsem); > static int cxl_mem_major; > static DEFINE_IDA(cxl_memdev_ida); > > +static unsigned short endpoint_ready_timeout = HZ; > + > static void cxl_memdev_release(struct device *dev) > { > struct cxl_memdev *cxlmd = to_cxl_memdev(dev); > @@ -1163,6 +1166,70 @@ struct cxl_memdev *devm_cxl_add_memdev(struct > device *host, } > EXPORT_SYMBOL_NS_GPL(devm_cxl_add_memdev, CXL); > > +/* > + * Try to get a locked reference on a memdev's CXL port topology > + * connection. Be careful to observe when cxl_mem_probe() has > deposited > + * a probe deferral awaiting the arrival of the CXL root driver. > + */ > +struct cxl_port *cxl_acquire_endpoint(struct cxl_memdev *cxlmd) > +{ > + struct cxl_port *endpoint; > + unsigned long timeout; > + int rc = -ENXIO; > + > + /* > + * A memdev creation triggers ports creation through the > kernel > + * device object model. An endpoint port could not be > created yet > + * but coming. Wait here for a gentle space of time for > ensuring > + * and endpoint port not there is due to some error and not > because > + * the race described. > + * > + * Note this is a similar case this function is implemented > for, but > + * instead of the race with the root port, this is against > its own > + * endpoint port. > + */ > + timeout = jiffies + endpoint_ready_timeout; > + do { > + device_lock(&cxlmd->dev); > + endpoint = cxlmd->endpoint; > + if (endpoint) > + break; > + device_unlock(&cxlmd->dev); > + if (msleep_interruptible(100)) { > + device_lock(&cxlmd->dev); > + break; > + } > + } while (!time_after(jiffies, timeout)); > + > + if (!endpoint) > + goto err; > + > + if (IS_ERR(endpoint)) { > + rc = PTR_ERR(endpoint); > + goto err; > + } > + > + device_lock(&endpoint->dev); > + if (!endpoint->dev.driver) > + goto err_endpoint; > + > + return endpoint; > + > +err_endpoint: > + device_unlock(&endpoint->dev); > +err: > + device_unlock(&cxlmd->dev); > + return ERR_PTR(rc); > +} > +EXPORT_SYMBOL_NS(cxl_acquire_endpoint, CXL); > + > +void cxl_release_endpoint(struct cxl_memdev *cxlmd, struct cxl_port > *endpoint) +{ > + device_unlock(&endpoint->dev); > + device_unlock(&cxlmd->dev); > +} > +EXPORT_SYMBOL_NS(cxl_release_endpoint, CXL); > + > static void sanitize_teardown_notifier(void *data) > { > struct cxl_memdev_state *mds = data; > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index 39b20ddd0296..ca2c993faa9c 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -1554,7 +1554,7 @@ static int add_port_attach_ep(struct cxl_memdev > *cxlmd, */ > dev_dbg(&cxlmd->dev, "%s is a root dport\n", > dev_name(dport_dev)); > - return -ENXIO; > + return -EPROBE_DEFER; > } > > parent_port = find_cxl_port(dparent, &parent_dport); > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index 5c7ad230bccb..56fd7a100c2f 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c > @@ -145,8 +145,10 @@ static int cxl_mem_probe(struct device *dev) > return rc; > > rc = devm_cxl_enumerate_ports(cxlmd); > - if (rc) > + if (rc) { > + cxlmd->endpoint = ERR_PTR(rc); > return rc; > + } > > parent_port = cxl_mem_find_port(cxlmd, &dport); > if (!parent_port) { > diff --git a/include/linux/cxl/cxl.h b/include/linux/cxl/cxl.h > index fc0859f841dc..7e4580fb8659 100644 > --- a/include/linux/cxl/cxl.h > +++ b/include/linux/cxl/cxl.h > @@ -57,4 +57,6 @@ int cxl_release_resource(struct cxl_dev_state > *cxlds, enum cxl_resource type); void cxl_set_media_ready(struct > cxl_dev_state *cxlds); struct cxl_memdev *devm_cxl_add_memdev(struct > device *host, struct cxl_dev_state *cxlds); > +struct cxl_port *cxl_acquire_endpoint(struct cxl_memdev *cxlmd); > +void cxl_release_endpoint(struct cxl_memdev *cxlmd, struct cxl_port > *endpoint); #endif