From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D2B68F6A; Fri, 13 Sep 2024 17:43:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726249406; cv=none; b=ll3NljSHJhlK3TVe4NBPIyPJDRRd/xp0iSw8x6nWMP1w1hCzssdamnAsu00/cNh1Stz3TXuSJwNUv1L2zIiLzdQ4OboFF/UKcUeWQEnKGvdC6EqFRbDTKSsPeR7jWXf/TXhYqKBGKotFlIWZOlFyfjBvyBVvh7IMAv1Em5GGcN0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726249406; c=relaxed/simple; bh=RiIldHorGs5Nzrp/08/WYCMvH26mcu7vdB6VGWwQRKQ=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MJKQxLeKwCjItYI3biNK/rjegCv3qM+Huba3ll4QPNV0RnfEfaN6pzlm2n0q89xJq88a0uFkOGnFqLGmS0/5RXnvntX4BGAyiBUjyxlAFfJID3aaZwmDLyydsNH8EBK/okJYYFEp64QP7VoaBzsUlCLGIygmWn1KDWdtI9Mp6zU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=Huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=Huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4X51ld3mgcz6L6pJ; Sat, 14 Sep 2024 01:39:41 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id D9A05140A77; Sat, 14 Sep 2024 01:43:21 +0800 (CST) Received: from localhost (10.48.150.243) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 13 Sep 2024 19:43:20 +0200 Date: Fri, 13 Sep 2024 18:43:19 +0100 From: Jonathan Cameron To: CC: , , , , , , , , , Alejandro Lucero Subject: Re: [PATCH v3 10/20] cxl: indicate probe deferral Message-ID: <20240913184319.00000440@Huawei.com> In-Reply-To: <20240907081836.5801-11-alejandro.lucero-palau@amd.com> References: <20240907081836.5801-1-alejandro.lucero-palau@amd.com> <20240907081836.5801-11-alejandro.lucero-palau@amd.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml100006.china.huawei.com (7.191.160.224) To frapeml500008.china.huawei.com (7.182.85.71) On Sat, 7 Sep 2024 09:18:26 +0100 alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero > > The first stop for a CXL accelerator driver that wants to establish new > CXL.mem regions is to register a 'struct cxl_memdev. That kicks off > cxl_mem_probe() to enumerate all 'struct cxl_port' instances in the > topology up to the root. > > If the root driver has not attached yet the expectation is that the > driver waits until that link is established. The common cxl_pci_driver > has reason to keep the 'struct cxl_memdev' device attached to the bus > until the root driver attaches. An accelerator may want to instead defer > probing until CXL resources can be acquired. > > Use the @endpoint attribute of a 'struct cxl_memdev' to convey when > accelerator driver probing should be deferred vs failed. Provide that > indication via a new cxl_acquire_endpoint() API that can retrieve the > probe status of the memdev. > > Based on https://lore.kernel.org/linux-cxl/168592155270.1948938.11536845108449547920.stgit@dwillia2-xfh.jf.intel.com/ > > Signed-off-by: Alejandro Lucero > Co-developed-by: Dan Williams > --- > drivers/cxl/core/memdev.c | 67 +++++++++++++++++++++++++++++++++++++++ > drivers/cxl/core/port.c | 2 +- > drivers/cxl/mem.c | 4 ++- > include/linux/cxl/cxl.h | 2 ++ > 4 files changed, 73 insertions(+), 2 deletions(-) > > diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c > index 5f8418620b70..d4406cf3ed32 100644 > --- a/drivers/cxl/core/memdev.c > +++ b/drivers/cxl/core/memdev.c > @@ -5,6 +5,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -23,6 +24,8 @@ static DECLARE_RWSEM(cxl_memdev_rwsem); > static int cxl_mem_major; > static DEFINE_IDA(cxl_memdev_ida); > > +static unsigned short endpoint_ready_timeout = HZ; > + > static void cxl_memdev_release(struct device *dev) > { > struct cxl_memdev *cxlmd = to_cxl_memdev(dev); > @@ -1163,6 +1166,70 @@ struct cxl_memdev *devm_cxl_add_memdev(struct device *host, > } > EXPORT_SYMBOL_NS_GPL(devm_cxl_add_memdev, CXL); > > +/* > + * Try to get a locked reference on a memdev's CXL port topology > + * connection. Be careful to observe when cxl_mem_probe() has deposited > + * a probe deferral awaiting the arrival of the CXL root driver. > + */ > +struct cxl_port *cxl_acquire_endpoint(struct cxl_memdev *cxlmd) > +{ > + struct cxl_port *endpoint; > + unsigned long timeout; > + int rc = -ENXIO; > + > + /* > + * A memdev creation triggers ports creation through the kernel > + * device object model. An endpoint port could not be created yet > + * but coming. Wait here for a gentle space of time for ensuring > + * and endpoint port not there is due to some error and not because > + * the race described. > + * > + * Note this is a similar case this function is implemented for, but > + * instead of the race with the root port, this is against its own > + * endpoint port. This dance is nasty and there is no real guarantee it will even help. We need a better solution. I'm not quite sure on what it is though. Is there any precedence for similar 'wait a bit and hope' in the kernel? > + */ > + timeout = jiffies + endpoint_ready_timeout; > + do { > + device_lock(&cxlmd->dev); > + endpoint = cxlmd->endpoint; > + if (endpoint) > + break; > + device_unlock(&cxlmd->dev); > + if (msleep_interruptible(100)) { > + device_lock(&cxlmd->dev); > + break; > + } > + } while (!time_after(jiffies, timeout)); > + > + if (!endpoint) > + goto err; > + > + if (IS_ERR(endpoint)) { > + rc = PTR_ERR(endpoint); > + goto err; > + } > + > + device_lock(&endpoint->dev); > + if (!endpoint->dev.driver) > + goto err_endpoint; > + > + return endpoint; > + > +err_endpoint: > + device_unlock(&endpoint->dev); > +err: > + device_unlock(&cxlmd->dev); > + return ERR_PTR(rc); > +} > +EXPORT_SYMBOL_NS(cxl_acquire_endpoint, CXL); > + > +void cxl_release_endpoint(struct cxl_memdev *cxlmd, struct cxl_port *endpoint) > +{ > + device_unlock(&endpoint->dev); > + device_unlock(&cxlmd->dev); > +} > +EXPORT_SYMBOL_NS(cxl_release_endpoint, CXL); > + > static void sanitize_teardown_notifier(void *data) > { > struct cxl_memdev_state *mds = data; > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index 39b20ddd0296..ca2c993faa9c 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -1554,7 +1554,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd, > */ > dev_dbg(&cxlmd->dev, "%s is a root dport\n", > dev_name(dport_dev)); > - return -ENXIO; > + return -EPROBE_DEFER; > } > > parent_port = find_cxl_port(dparent, &parent_dport); > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index 5c7ad230bccb..56fd7a100c2f 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c > @@ -145,8 +145,10 @@ static int cxl_mem_probe(struct device *dev) > return rc; > > rc = devm_cxl_enumerate_ports(cxlmd); > - if (rc) > + if (rc) { > + cxlmd->endpoint = ERR_PTR(rc); > return rc; > + } > > parent_port = cxl_mem_find_port(cxlmd, &dport); > if (!parent_port) { > diff --git a/include/linux/cxl/cxl.h b/include/linux/cxl/cxl.h > index fc0859f841dc..7e4580fb8659 100644 > --- a/include/linux/cxl/cxl.h > +++ b/include/linux/cxl/cxl.h > @@ -57,4 +57,6 @@ int cxl_release_resource(struct cxl_dev_state *cxlds, enum cxl_resource type); > void cxl_set_media_ready(struct cxl_dev_state *cxlds); > struct cxl_memdev *devm_cxl_add_memdev(struct device *host, > struct cxl_dev_state *cxlds); > +struct cxl_port *cxl_acquire_endpoint(struct cxl_memdev *cxlmd); > +void cxl_release_endpoint(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); > #endif