From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: <alejandro.lucero-palau@amd.com>
Cc: <linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>,
<dan.j.williams@intel.com>, <martin.habets@xilinx.com>,
<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
<pabeni@redhat.com>, <edumazet@google.com>,
Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v3 13/20] cxl: define a driver interface for DPA allocation
Date: Fri, 13 Sep 2024 18:59:06 +0100 [thread overview]
Message-ID: <20240913185906.000008a2@Huawei.com> (raw)
In-Reply-To: <20240907081836.5801-14-alejandro.lucero-palau@amd.com>
On Sat, 7 Sep 2024 09:18:29 +0100
alejandro.lucero-palau@amd.com wrote:
> From: Alejandro Lucero <alucerop@amd.com>
>
> Region creation involves finding available DPA (device-physical-address)
> capacity to map into HPA (host-physical-address) space. Given the HPA
> capacity constraint, define an API, cxl_request_dpa(), that has the
> flexibility to map the minimum amount of memory the driver needs to
> operate vs the total possible that can be mapped given HPA availability.
>
> Factor out the core of cxl_dpa_alloc, that does free space scanning,
> into a cxl_dpa_freespace() helper, and use that to balance the capacity
> available to map vs the @min and @max arguments to cxl_request_dpa.
>
> Based on https://lore.kernel.org/linux-cxl/168592158743.1948938.7622563891193802610.stgit@dwillia2-xfh.jf.intel.com/
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Co-developed-by: Dan Williams <dan.j.williams@intel.com>
Trivial comment below.
> +
> +/**
> + * cxl_request_dpa - search and reserve DPA given input constraints
> + * @endpoint: an endpoint port with available decoders
> + * @is_ram: DPA operation mode (ram vs pmem)
> + * @min: the minimum amount of capacity the call needs
> + * @max: extra capacity to allocate after min is satisfied
> + *
> + * Given that a region needs to allocate from limited HPA capacity it
> + * may be the case that a device has more mappable DPA capacity than
> + * available HPA. So, the expectation is that @min is a driver known
> + * value for how much capacity is needed, and @max is based the limit of
> + * how much HPA space is available for a new region.
> + *
> + * Returns a pinned cxl_decoder with at least @min bytes of capacity
> + * reserved, or an error pointer. The caller is also expected to own the
> + * lifetime of the memdev registration associated with the endpoint to
> + * pin the decoder registered as well.
> + */
> +struct cxl_endpoint_decoder *cxl_request_dpa(struct cxl_port *endpoint,
> + bool is_ram,
> + resource_size_t min,
> + resource_size_t max)
> +{
> + struct cxl_endpoint_decoder *cxled;
> + enum cxl_decoder_mode mode;
> + struct device *cxled_dev;
> + resource_size_t alloc;
> + int rc;
> +
> + if (!IS_ALIGNED(min | max, SZ_256M))
> + return ERR_PTR(-EINVAL);
> +
> + down_read(&cxl_dpa_rwsem);
> +
> + cxled_dev = device_find_child(&endpoint->dev, NULL, find_free_decoder);
> + if (!cxled_dev)
> + cxled = ERR_PTR(-ENXIO);
> + else
> + cxled = to_cxl_endpoint_decoder(cxled_dev);
Does this need to be under the rwsem? If not cleaner to just
check cxled_dev outside the lock and return the error directly.
Also, in theory this could return NULL - in practice not but
checking it for IS_ERR() is perhaps going to lead to a bug
in the distant future.
> +
> + up_read(&cxl_dpa_rwsem);
> +
> + if (IS_ERR(cxled))
> + return cxled;
> +
> + if (is_ram)
> + mode = CXL_DECODER_RAM;
> + else
> + mode = CXL_DECODER_PMEM;
> +
> + rc = cxl_dpa_set_mode(cxled, mode);
> + if (rc)
> + goto err;
> +
> + down_read(&cxl_dpa_rwsem);
> + alloc = cxl_dpa_freespace(cxled, NULL, NULL);
> + up_read(&cxl_dpa_rwsem);
> +
> + if (max)
> + alloc = min(max, alloc);
> + if (alloc < min) {
> + rc = -ENOMEM;
> + goto err;
> + }
> +
> + rc = cxl_dpa_alloc(cxled, alloc);
> + if (rc)
> + goto err;
> +
> + return cxled;
> +err:
> + put_device(cxled_dev);
> + return ERR_PTR(rc);
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_request_dpa, CXL);
next prev parent reply other threads:[~2024-09-13 17:59 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-07 8:18 [PATCH v3 00/20] cxl: add Type2 device support alejandro.lucero-palau
2024-09-07 8:18 ` [PATCH v3 01/20] cxl: add type2 device basic support alejandro.lucero-palau
2024-09-07 20:26 ` kernel test robot
2024-09-10 6:12 ` Li, Ming4
2024-09-10 7:25 ` Alejandro Lucero Palau
2024-09-12 8:57 ` Zhi Wang
2024-09-16 9:52 ` Alejandro Lucero Palau
2024-09-12 9:35 ` Zhi Wang
2024-09-16 10:03 ` Alejandro Lucero Palau
2024-09-13 16:41 ` Jonathan Cameron
2024-09-16 12:03 ` Alejandro Lucero Palau
2024-09-16 12:24 ` Jonathan Cameron
2024-09-07 8:18 ` [PATCH v3 02/20] cxl: add capabilities field to cxl_dev_state and cxl_port alejandro.lucero-palau
2024-09-07 18:08 ` kernel test robot
2024-09-11 22:17 ` Dave Jiang
2024-09-16 8:36 ` Alejandro Lucero Palau
2024-09-16 16:07 ` Dave Jiang
2024-09-13 17:25 ` Jonathan Cameron
2024-09-16 12:13 ` Alejandro Lucero Palau
2024-09-07 8:18 ` [PATCH v3 03/20] cxl/pci: add check for validating capabilities alejandro.lucero-palau
2024-09-10 3:26 ` Li, Ming4
2024-09-10 6:24 ` Li, Ming4
2024-09-10 7:31 ` Alejandro Lucero Palau
2024-09-11 23:06 ` Dave Jiang
2024-09-16 8:56 ` Alejandro Lucero Palau
2024-09-16 16:11 ` Dave Jiang
2024-09-13 17:28 ` Jonathan Cameron
2024-09-16 12:17 ` Alejandro Lucero Palau
2024-09-07 8:18 ` [PATCH v3 04/20] cxl: move pci generic code alejandro.lucero-palau
2024-09-11 23:55 ` Dave Jiang
2024-09-16 9:46 ` Alejandro Lucero Palau
2024-09-07 8:18 ` [PATCH v3 05/20] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2024-09-10 6:00 ` Li, Ming4
2024-09-10 7:24 ` Alejandro Lucero Palau
2024-09-12 9:08 ` Zhi Wang
2024-09-13 17:32 ` Jonathan Cameron
2024-09-16 12:23 ` Alejandro Lucero Palau
2024-09-07 8:18 ` [PATCH v3 06/20] cxl: add functions for resource request/release by a driver alejandro.lucero-palau
2024-09-10 6:15 ` Li, Ming4
2024-09-16 8:15 ` Alejandro Lucero Palau
2024-09-13 17:35 ` Jonathan Cameron
2024-09-16 12:33 ` Alejandro Lucero Palau
2024-09-16 13:21 ` Jonathan Cameron
2024-09-07 8:18 ` [PATCH v3 07/20] cxl: harden resource_contains checks to handle zero size resources alejandro.lucero-palau
2024-09-13 17:36 ` Jonathan Cameron
2024-09-16 12:36 ` Alejandro Lucero Palau
2024-09-07 8:18 ` [PATCH v3 08/20] cxl: add function for setting media ready by a driver alejandro.lucero-palau
2024-09-07 8:18 ` [PATCH v3 09/20] cxl: support type2 memdev creation alejandro.lucero-palau
2024-09-12 18:19 ` Dave Jiang
2024-09-16 12:38 ` Alejandro Lucero Palau
2024-09-07 8:18 ` [PATCH v3 10/20] cxl: indicate probe deferral alejandro.lucero-palau
2024-09-10 6:37 ` Li, Ming4
2024-09-16 8:24 ` Alejandro Lucero Palau
2024-09-17 3:31 ` Li, Ming4
2024-09-17 9:16 ` Alejandro Lucero Palau
2024-09-12 9:19 ` Zhi Wang
2024-09-16 10:08 ` Alejandro Lucero Palau
2024-09-13 17:43 ` Jonathan Cameron
2024-09-16 13:24 ` Alejandro Lucero Palau
2024-09-07 8:18 ` [PATCH v3 11/20] cxl: define a driver interface for HPA free space enumaration alejandro.lucero-palau
2024-09-13 17:52 ` Jonathan Cameron
2024-09-16 14:09 ` Alejandro Lucero Palau
2024-09-07 8:18 ` [PATCH v3 12/20] efx: use acquire_endpoint when looking for free HPA alejandro.lucero-palau
2024-09-07 19:33 ` kernel test robot
2024-09-12 23:09 ` Dave Jiang
2024-09-16 10:29 ` Alejandro Lucero Palau
2024-09-07 8:18 ` [PATCH v3 13/20] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2024-09-13 17:59 ` Jonathan Cameron [this message]
2024-09-16 14:26 ` Alejandro Lucero Palau
2024-09-07 8:18 ` [PATCH v3 14/20] cxl: make region type based on endpoint type alejandro.lucero-palau
2024-09-07 8:18 ` [PATCH v3 15/20] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2024-09-07 8:18 ` [PATCH v3 16/20] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2024-09-07 8:18 ` [PATCH v3 17/20] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2024-09-13 18:08 ` Jonathan Cameron
2024-09-16 16:31 ` Alejandro Lucero Palau
2024-09-07 8:18 ` [PATCH v3 18/20] cxl: preclude device memory to be used for dax alejandro.lucero-palau
2024-09-13 17:26 ` Dave Jiang
2024-09-16 14:32 ` Alejandro Lucero Palau
2024-09-07 8:18 ` [PATCH v3 19/20] cxl: add function for obtaining params from a region alejandro.lucero-palau
2024-09-13 17:48 ` Dave Jiang
2024-09-16 16:22 ` Alejandro Lucero Palau
2024-09-07 8:18 ` [PATCH v3 20/20] efx: support pio mapping based on cxl alejandro.lucero-palau
2024-09-13 17:45 ` Edward Cree
2024-09-16 16:12 ` Alejandro Lucero Palau
2024-09-13 17:52 ` Dave Jiang
2024-09-16 16:23 ` Alejandro Lucero Palau
2024-09-13 18:10 ` Jonathan Cameron
2024-09-16 16:23 ` Alejandro Lucero Palau
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