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AJvYcCU35rlx6ZsK5Ltp4w1y3c7WCrclhwnVkH0vfe7/ttu4EkPSlYKXooA72b6Jn0Gnt9BdJpfWCTnuQMLxYZQ=@vger.kernel.org, AJvYcCXLNgxVrP59PxKaW3dnG+SitgQbaArOZB23b02FrHLVV+x4o3/EzKNFOcPvokXvAxK16h8dCfzi@vger.kernel.org X-Gm-Message-State: AOJu0YzEW2HHazzNGJuMQEghJhRl2TP+OrtnIlz6X9QAxdac0pir9hFq VuX5wyTDVB014KRso/vh5SqBvrRUQD1p2X799jxyj1ajChGYnEcb X-Google-Smtp-Source: AGHT+IFduHHYOeGnIjHKPhqSRTid9Q8opnKcs7z5l4h7HwBhUORtSS/HEc6X+MCCWiyS/K7HSNxigA== X-Received: by 2002:a17:903:244c:b0:20c:f39e:4c04 with SMTP id d9443c01a7336-20d471ec6ddmr224478475ad.2.1729487164568; Sun, 20 Oct 2024 22:06:04 -0700 (PDT) Received: from localhost ([129.146.253.192]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7f0e1ba7sm17686565ad.238.2024.10.20.22.06.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 22:06:04 -0700 (PDT) Date: Mon, 21 Oct 2024 13:05:54 +0800 From: Furong Xu <0x1207@gmail.com> To: 2694439648@qq.com Cc: alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, hailong.fan@siengine.com Subject: Re: [PATCH v1] net: stmmac: enable MAC after MTL configuring Message-ID: <20241021130554.00005cf5@gmail.com> In-Reply-To: References: X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Mon, 21 Oct 2024 09:03:05 +0800, 2694439648@qq.com wrote: > From: "hailong.fan" > > DMA maybe block while ETH is opening, > Adjust the enable sequence, put the MAC enable last > > For example, ETH is directly connected to the switch, > which never power down and sends broadcast packets at regular intervals. > During the process of opening ETH, data may flow into the MTL FIFO, > once MAC RX is enabled. and then, MTL will be set, such as FIFO size. > Once enable DMA, There is a certain probability that DMA will read > incorrect data from MTL FIFO, causing DMA to hang up. > By read DMA_Debug_Status, you can be observed that the RPS remains at > a certain value forever. The correct process should be to configure > MAC/MTL/DMA before enabling DMA/MAC > > Signed-off-by: hailong.fan > A Fixes: tag should be added. > static void dwxgmac2_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c > index e21404822..c19ca62a4 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c > @@ -3437,9 +3437,6 @@ static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) > priv->hw->rx_csum = 0; > } > > - /* Enable the MAC Rx/Tx */ > - stmmac_mac_set(priv, priv->ioaddr, true); > - > /* Set the HW DMA mode and the COE */ > stmmac_dma_operation_mode(priv); > > @@ -3523,6 +3520,9 @@ static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) > /* Start the ball rolling... */ > stmmac_start_all_dma(priv); > > + /* Enable the MAC Rx/Tx */ > + stmmac_mac_set(priv, priv->ioaddr, true); > + This sequence fix should be applied to stmmac_xdp_open() too. > stmmac_set_hw_vlan_mode(priv, priv->hw); > > return 0; It is better to split this patch into individual patches, since you are trying to fix an issue related to several previous commits: dwmac4, dwxgmac2, stmmac_hw_setup() and stmmac_xdp_open()