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From: Zhi Wang <zhiw@nvidia.com>
To: <alejandro.lucero-palau@amd.com>
Cc: <linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>,
	<dan.j.williams@intel.com>, <martin.habets@xilinx.com>,
	<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
	<pabeni@redhat.com>, <edumazet@google.com>,
	Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v5 22/27] cxl: allow region creation by type2 drivers
Date: Tue, 19 Nov 2024 22:37:05 +0200	[thread overview]
Message-ID: <20241119223705.00001c1d@nvidia.com> (raw)
In-Reply-To: <20241118164434.7551-23-alejandro.lucero-palau@amd.com>

On Mon, 18 Nov 2024 16:44:29 +0000
<alejandro.lucero-palau@amd.com> wrote:

> From: Alejandro Lucero <alucerop@amd.com>
> 
> Creating a CXL region requires userspace intervention through the cxl
> sysfs files. Type2 support should allow accelerator drivers to create
> such cxl region from kernel code.
> 
> Adding that functionality and integrating it with current support for
> memory expanders.
> 
> Based on https://lore.kernel.org/linux-cxl/168592159835.1948938.1647215579839222774.stgit@dwillia2-xfh.jf.intel.com/
> 
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> ---
>  drivers/cxl/core/region.c | 147 ++++++++++++++++++++++++++++++++++----
>  drivers/cxl/cxlmem.h      |   2 +
>  drivers/cxl/port.c        |   5 +-
>  include/cxl/cxl.h         |   4 ++
>  4 files changed, 142 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 6652887ea396..70549d42c2e3 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -2256,6 +2256,18 @@ static int cxl_region_detach(struct cxl_endpoint_decoder *cxled)
>  	return rc;
>  }
>  
> +int cxl_accel_region_detach(struct cxl_endpoint_decoder *cxled)
> +{
> +	int rc;
> +
> +	down_write(&cxl_region_rwsem);
> +	cxled->mode = CXL_DECODER_DEAD;
> +	rc = cxl_region_detach(cxled);
> +	up_write(&cxl_region_rwsem);
> +	return rc;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_accel_region_detach, CXL);
> +
>  void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled)
>  {
>  	down_write(&cxl_region_rwsem);
> @@ -2770,6 +2782,14 @@ cxl_find_region_by_name(struct cxl_root_decoder *cxlrd, const char *name)
>  	return to_cxl_region(region_dev);
>  }
>  
> +static void drop_region(struct cxl_region *cxlr)
> +{
> +	struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
> +	struct cxl_port *port = cxlrd_to_port(cxlrd);
> +
> +	devm_release_action(port->uport_dev, unregister_region, cxlr);
> +}
> +
>  static ssize_t delete_region_store(struct device *dev,
>  				   struct device_attribute *attr,
>  				   const char *buf, size_t len)
> @@ -3376,17 +3396,18 @@ static int match_region_by_range(struct device *dev, void *data)
>  	return rc;
>  }
>  
> -/* Establish an empty region covering the given HPA range */
> -static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
> -					   struct cxl_endpoint_decoder *cxled)
> +static void construct_region_end(void)
> +{
> +	up_write(&cxl_region_rwsem);
> +}
> +
> +static struct cxl_region *construct_region_begin(struct cxl_root_decoder *cxlrd,
> +						 struct cxl_endpoint_decoder *cxled)
>  {
>  	struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> -	struct cxl_port *port = cxlrd_to_port(cxlrd);
> -	struct range *hpa = &cxled->cxld.hpa_range;
>  	struct cxl_region_params *p;
>  	struct cxl_region *cxlr;
> -	struct resource *res;
> -	int rc;
> +	int err;

maybe let's keep the original name "rc".
>  
>  	do {
>  		cxlr = __create_region(cxlrd, cxled->mode,
> @@ -3395,8 +3416,7 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
>  	} while (IS_ERR(cxlr) && PTR_ERR(cxlr) == -EBUSY);
>  
>  	if (IS_ERR(cxlr)) {
> -		dev_err(cxlmd->dev.parent,
> -			"%s:%s: %s failed assign region: %ld\n",
> +		dev_err(cxlmd->dev.parent, "%s:%s: %s failed assign region: %ld\n",
>  			dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev),
>  			__func__, PTR_ERR(cxlr));
>  		return cxlr;
> @@ -3406,13 +3426,33 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
>  	p = &cxlr->params;
>  	if (p->state >= CXL_CONFIG_INTERLEAVE_ACTIVE) {
>  		dev_err(cxlmd->dev.parent,
> -			"%s:%s: %s autodiscovery interrupted\n",
> +			"%s:%s: %s region setup interrupted\n",
>  			dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev),
>  			__func__);
> -		rc = -EBUSY;
> -		goto err;
> +		err = -EBUSY;
> +		construct_region_end();
> +		drop_region(cxlr);
> +		return ERR_PTR(err);
>  	}
>  
> +	return cxlr;
> +}
> +
> +/* Establish an empty region covering the given HPA range */
> +static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
> +					   struct cxl_endpoint_decoder *cxled)
> +{
> +	struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> +	struct range *hpa = &cxled->cxld.hpa_range;
> +	struct cxl_region_params *p;
> +	struct cxl_region *cxlr;
> +	struct resource *res;
> +	int rc;
> +
> +	cxlr = construct_region_begin(cxlrd, cxled);
> +	if (IS_ERR(cxlr))
> +		return cxlr;
> +
>  	set_bit(CXL_REGION_F_AUTO, &cxlr->flags);
>  
>  	res = kmalloc(sizeof(*res), GFP_KERNEL);
> @@ -3435,6 +3475,7 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
>  			 __func__, dev_name(&cxlr->dev));
>  	}
>  
> +	p = &cxlr->params;
>  	p->res = res;
>  	p->interleave_ways = cxled->cxld.interleave_ways;
>  	p->interleave_granularity = cxled->cxld.interleave_granularity;
> @@ -3452,15 +3493,91 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
>  	/* ...to match put_device() in cxl_add_to_region() */
>  	get_device(&cxlr->dev);
>  	up_write(&cxl_region_rwsem);
> -
> +	construct_region_end();

cxl_region_rwsem seems got up_write() two times. Guess you should remove
it like below since it is now done in construct_region_end().

>  	return cxlr;
>  
>  err:
> -	up_write(&cxl_region_rwsem);
> -	devm_release_action(port->uport_dev, unregister_region, cxlr);
> +	construct_region_end();
> +	drop_region(cxlr);
> +	return ERR_PTR(rc);
> +}
> +
> +static struct cxl_region *
> +__construct_new_region(struct cxl_root_decoder *cxlrd,
> +		       struct cxl_endpoint_decoder *cxled)
> +{
> +	struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
> +	struct cxl_region_params *p;
> +	struct cxl_region *cxlr;
> +	int rc;
> +
> +	cxlr = construct_region_begin(cxlrd, cxled);
> +	if (IS_ERR(cxlr))
> +		return cxlr;
> +
> +	rc = set_interleave_ways(cxlr, 1);
> +	if (rc)
> +		goto err;
> +
> +	rc = set_interleave_granularity(cxlr, cxld->interleave_granularity);
> +	if (rc)
> +		goto err;
> +
> +	rc = alloc_hpa(cxlr, resource_size(cxled->dpa_res));
> +	if (rc)
> +		goto err;
> +
> +	down_read(&cxl_dpa_rwsem);
> +	rc = cxl_region_attach(cxlr, cxled, 0);
> +	up_read(&cxl_dpa_rwsem);
> +
> +	if (rc)
> +		goto err;
> +
> +	rc = cxl_region_decode_commit(cxlr);
> +	if (rc)
> +		goto err;
> +
> +	p = &cxlr->params;
> +	p->state = CXL_CONFIG_COMMIT;
> +
> +	construct_region_end();
> +	return cxlr;
> +err:
> +	construct_region_end();
> +	drop_region(cxlr);
>  	return ERR_PTR(rc);
>  }
>  
> +/**
> + * cxl_create_region - Establish a region given an endpoint decoder
> + * @cxlrd: root decoder to allocate HPA
> + * @cxled: endpoint decoder with reserved DPA capacity
> + *
> + * Returns a fully formed region in the commit state and attached to the
> + * cxl_region driver.
> + */
> +struct cxl_region *cxl_create_region(struct cxl_root_decoder *cxlrd,
> +				     struct cxl_endpoint_decoder *cxled)
> +{
> +	struct cxl_region *cxlr;
> +
> +	mutex_lock(&cxlrd->range_lock);
> +	cxlr = __construct_new_region(cxlrd, cxled);
> +	mutex_unlock(&cxlrd->range_lock);
> +
> +	if (IS_ERR(cxlr))
> +		return cxlr;
> +
> +	if (device_attach(&cxlr->dev) <= 0) {
> +		dev_err(&cxlr->dev, "failed to create region\n");
> +		drop_region(cxlr);
> +		return ERR_PTR(-ENODEV);
> +	}
> +	return cxlr;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_create_region, CXL);
> +
>  int cxl_add_to_region(struct cxl_port *root, struct cxl_endpoint_decoder *cxled)
>  {
>  	struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 4c1c53c29544..9d874f1cb3bf 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -874,4 +874,6 @@ struct cxl_hdm {
>  struct seq_file;
>  struct dentry *cxl_debugfs_create_dir(const char *dir);
>  void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds);
> +struct cxl_region *cxl_create_region(struct cxl_root_decoder *cxlrd,
> +				     struct cxl_endpoint_decoder *cxled);
>  #endif /* __CXL_MEM_H__ */
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index acf2ac70f343..ec1f0cfb11a5 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -33,6 +33,7 @@ static void schedule_detach(void *cxlmd)
>  static int discover_region(struct device *dev, void *root)
>  {
>  	struct cxl_endpoint_decoder *cxled;
> +	struct cxl_memdev *cxlmd;
>  	int rc;
>  
>  	if (!is_endpoint_decoder(dev))
> @@ -42,7 +43,9 @@ static int discover_region(struct device *dev, void *root)
>  	if ((cxled->cxld.flags & CXL_DECODER_F_ENABLE) == 0)
>  		return 0;
>  
> -	if (cxled->state != CXL_DECODER_STATE_AUTO)
> +	cxlmd = cxled_to_memdev(cxled);
> +	if (cxled->state != CXL_DECODER_STATE_AUTO ||
> +	    cxlmd->cxlds->type == CXL_DEVTYPE_DEVMEM)
>  		return 0;
>  
>  	/*
> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> index 9b5b5472a86b..d295af4f5f9e 100644
> --- a/include/cxl/cxl.h
> +++ b/include/cxl/cxl.h
> @@ -72,4 +72,8 @@ struct cxl_endpoint_decoder *cxl_request_dpa(struct cxl_memdev *cxlmd,
>  					     resource_size_t min,
>  					     resource_size_t max);
>  int cxl_dpa_free(struct cxl_endpoint_decoder *cxled);
> +struct cxl_region *cxl_create_region(struct cxl_root_decoder *cxlrd,
> +				     struct cxl_endpoint_decoder *cxled);
> +
> +int cxl_accel_region_detach(struct cxl_endpoint_decoder *cxled);
>  #endif


  reply	other threads:[~2024-11-19 20:37 UTC|newest]

Thread overview: 99+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-18 16:44 [PATCH v5 00/27] cxl: add type2 device basic support alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 01/27] " alejandro.lucero-palau
2024-11-18 21:55   ` Dave Jiang
2024-11-20 13:40     ` Alejandro Lucero Palau
2024-11-20 23:07   ` Fan Ni
2024-11-22  4:35   ` Alison Schofield
2024-11-22  9:27     ` Alejandro Lucero Palau
2024-11-26  5:59       ` Alison Schofield
2024-11-26 16:38         ` Alejandro Lucero Palau
2024-11-22 20:43   ` Ben Cheatham
2024-11-27  9:00     ` Alejandro Lucero Palau
2024-11-27  9:07       ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 02/27] sfc: add cxl support using new CXL API alejandro.lucero-palau
2024-11-22 20:43   ` Ben Cheatham
2024-11-27  9:15     ` Alejandro Lucero Palau
2024-11-26 18:08   ` Fan Ni
2024-11-27  9:17     ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 03/27] cxl: add capabilities field to cxl_dev_state and cxl_port alejandro.lucero-palau
2024-11-18 22:52   ` Dave Jiang
2024-11-19 12:28     ` Alejandro Lucero Palau
2024-11-19 15:53       ` Dave Jiang
2024-11-20 13:41         ` Alejandro Lucero Palau
2024-11-22 20:44   ` Ben Cheatham
2024-11-18 16:44 ` [PATCH v5 04/27] cxl/pci: add check for validating capabilities alejandro.lucero-palau
2024-11-22 20:44   ` Ben Cheatham
2024-11-27 11:34     ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 05/27] cxl: move pci generic code alejandro.lucero-palau
2024-11-18 22:57   ` Dave Jiang
2024-11-22 20:44   ` Ben Cheatham
2024-11-18 16:44 ` [PATCH v5 06/27] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2024-11-18 23:32   ` Dave Jiang
2024-11-21 22:34   ` Alison Schofield
2024-11-27 11:46     ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 07/27] sfc: use cxl api for regs setup and checking alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 08/27] cxl: add functions for resource request/release by a driver alejandro.lucero-palau
2024-11-22 20:45   ` Ben Cheatham
2024-11-18 16:44 ` [PATCH v5 09/27] sfc: request cxl ram resource alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 10/27] cxl: harden resource_contains checks to handle zero size resources alejandro.lucero-palau
2024-11-19 18:00   ` Dave Jiang
2024-11-20 13:44     ` Alejandro Lucero Palau
2024-11-19 19:50   ` Zhi Wang
2024-11-20 13:45     ` Alejandro Lucero Palau
2024-11-21  7:13       ` Zhi Wang
2024-11-21  2:46   ` Alison Schofield
2024-11-21  9:22     ` Alejandro Lucero Palau
2024-11-21 21:00       ` Alison Schofield
2024-11-27 14:56         ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 11/27] cxl: add function for setting media ready by a driver alejandro.lucero-palau
2024-11-19 18:12   ` Dave Jiang
2024-11-22 20:45   ` Ben Cheatham
2024-11-27 15:07     ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 12/27] sfc: set cxl media ready alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 13/27] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2024-11-19 18:24   ` Dave Jiang
2024-11-19 20:06     ` Zhi Wang
2024-11-19 21:27       ` Dave Jiang
2024-11-20 13:57         ` Alejandro Lucero Palau
2024-11-20 17:15           ` Dave Jiang
2024-11-21  7:43             ` Zhi Wang
2024-11-22 20:45   ` Ben Cheatham
2024-11-27 16:09     ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 14/27] sfc: create type2 cxl memdev alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 15/27] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2024-11-22 20:45   ` Ben Cheatham
2024-11-27 16:32     ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 16/27] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 17/27] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 18/27] sfc: get endpoint decoder alejandro.lucero-palau
2024-11-22 20:45   ` Ben Cheatham
2024-11-27 16:47     ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 19/27] cxl: make region type based on endpoint type alejandro.lucero-palau
2024-11-19 20:16   ` Zhi Wang
2024-11-21 16:16   ` Dave Jiang
2024-11-18 16:44 ` [PATCH v5 20/27] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2024-11-19 20:20   ` Zhi Wang
2024-11-21 16:23   ` Dave Jiang
2024-11-18 16:44 ` [PATCH v5 21/27] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2024-11-19 20:23   ` Zhi Wang
2024-11-21 16:24   ` Dave Jiang
2024-11-18 16:44 ` [PATCH v5 22/27] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2024-11-19 20:37   ` Zhi Wang [this message]
2024-11-20 13:51     ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 23/27] sfc: create cxl region alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 24/27] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2024-11-19 20:39   ` Zhi Wang
2024-11-20 13:55     ` Alejandro Lucero Palau
2024-11-22 20:46   ` Ben Cheatham
2024-11-27 16:59     ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 25/27] sfc: specify avoid dax when cxl region is created alejandro.lucero-palau
2024-11-18 16:44 ` [PATCH v5 26/27] cxl: add function for obtaining params from a region alejandro.lucero-palau
2024-11-19 20:40   ` Zhi Wang
2024-11-21  2:56   ` Alison Schofield
2024-11-27 17:18     ` Alejandro Lucero Palau
2024-11-21 16:31   ` Dave Jiang
2024-11-27 17:12     ` Alejandro Lucero Palau
2024-11-18 16:44 ` [PATCH v5 27/27] sfc: support pio mapping based on cxl alejandro.lucero-palau
2024-11-21  3:33 ` [PATCH v5 00/27] cxl: add type2 device basic support Alison Schofield
2024-11-21  9:27   ` Alejandro Lucero Palau
2024-11-22  4:14     ` Alison Schofield

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