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Wed, 20 Nov 2024 23:43:57 -0800 Date: Thu, 21 Nov 2024 09:43:58 +0200 From: Zhi Wang To: Dave Jiang CC: Alejandro Lucero Palau , , , , , , , , , , Subject: Re: [PATCH v5 13/27] cxl: prepare memdev creation for type2 Message-ID: <20241121094358.00002bb7@nvidia.com> In-Reply-To: <1a788b8b-48b8-4853-906f-97af5952ce21@intel.com> References: <20241118164434.7551-1-alejandro.lucero-palau@amd.com> <20241118164434.7551-14-alejandro.lucero-palau@amd.com> <75e8c64e-5d0c-4ebf-843e-e5e4dd0aa5ec@intel.com> <20241119220605.00005808@nvidia.com> <4fc8fd99-f349-47f9-8f5e-d4c393370ada@intel.com> <1a788b8b-48b8-4853-906f-97af5952ce21@intel.com> X-Mailer: Claws Mail 4.2.0 (GTK 3.24.38; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F9:EE_|LV2PR12MB5799:EE_ X-MS-Office365-Filtering-Correlation-Id: b663da28-849b-4300-ae68-08dd0a004bc8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026|7053199007; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2024 07:44:14.3261 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b663da28-849b-4300-ae68-08dd0a004bc8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F9.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5799 On Wed, 20 Nov 2024 10:15:59 -0700 Dave Jiang wrote: >=20 >=20 > On 11/20/24 6:57 AM, Alejandro Lucero Palau wrote: > >=20 > > On 11/19/24 21:27, Dave Jiang wrote: > >> > >> On 11/19/24 1:06 PM, Zhi Wang wrote: > >>> On Tue, 19 Nov 2024 11:24:44 -0700 > >>> Dave Jiang wrote: > >>> > >>>> > >>>> On 11/18/24 9:44 AM, alejandro.lucero-palau@amd.com wrote: > >>>>> From: Alejandro Lucero > >>>>> > >>>>> Current cxl core is relying on a CXL_DEVTYPE_CLASSMEM type device > >>>>> when creating a memdev leading to problems when obtaining > >>>>> cxl_memdev_state references from a CXL_DEVTYPE_DEVMEM type. This > >>>>> last device type is managed by a specific vendor driver and does > >>>>> not need same sysfs files since not userspace intervention is > >>>>> expected. > >>>>> > >>>>> Create a new cxl_mem device type with no attributes for Type2. > >>>>> > >>>>> Avoid debugfs files relying on existence of clx_memdev_state. > >>>>> > >>>>> Make devm_cxl_add_memdev accesible from a accel driver. > >>>>> > >>>>> Signed-off-by: Alejandro Lucero > >>>>> --- > >>>>> =C2=A0 drivers/cxl/core/cdat.c=C2=A0=C2=A0 |=C2=A0 3 +++ > >>>>> =C2=A0 drivers/cxl/core/memdev.c | 15 +++++++++++++-- > >>>>> =C2=A0 drivers/cxl/core/region.c |=C2=A0 3 ++- > >>>>> =C2=A0 drivers/cxl/mem.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 | 25 +++++++++++++++++++------ > >>>>> =C2=A0 include/cxl/cxl.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 |=C2=A0 2 ++ > >>>>> =C2=A0 5 files changed, 39 insertions(+), 9 deletions(-) > >>>>> > >>>>> diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c > >>>>> index e9cd7939c407..192cff18ea25 100644 > >>>>> --- a/drivers/cxl/core/cdat.c > >>>>> +++ b/drivers/cxl/core/cdat.c > >>>>> @@ -577,6 +577,9 @@ static struct cxl_dpa_perf > >>>>> *cxled_get_dpa_perf(struct cxl_endpoint_decoder *cxle struct > >>>>> cxl_memdev_state *mds =3D to_cxl_memdev_state(cxlmd->cxlds); struct > >>>>> cxl_dpa_perf *perf; > >>>>> +=C2=A0=C2=A0=C2=A0 if (!mds) > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return ERR_PTR(-EINVAL); > >>>>> + > >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 switch (mode) { > >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case CXL_DECODER_RAM: > >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 perf =3D &md= s->ram_perf; > >>>>> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c > >>>>> index d746c8a1021c..df31eea0c06b 100644 > >>>>> --- a/drivers/cxl/core/memdev.c > >>>>> +++ b/drivers/cxl/core/memdev.c > >>>>> @@ -547,9 +547,17 @@ static const struct device_type > >>>>> cxl_memdev_type =3D { .groups =3D cxl_memdev_attribute_groups, > >>>>> =C2=A0 }; > >>>>> =C2=A0 +static const struct device_type cxl_accel_memdev_type =3D { > >>>>> +=C2=A0=C2=A0=C2=A0 .name =3D "cxl_memdev", > >>>>> +=C2=A0=C2=A0=C2=A0 .release =3D cxl_memdev_release, > >>>>> +=C2=A0=C2=A0=C2=A0 .devnode =3D cxl_memdev_devnode, > >>>>> +}; > >>>>> + > >>>>> =C2=A0 bool is_cxl_memdev(const struct device *dev) > >>>>> =C2=A0 { > >>>>> -=C2=A0=C2=A0=C2=A0 return dev->type =3D=3D &cxl_memdev_type; > >>>>> +=C2=A0=C2=A0=C2=A0 return (dev->type =3D=3D &cxl_memdev_type || > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dev->type =3D=3D &cxl_a= ccel_memdev_type); > >>>>> + > >>>>> =C2=A0 } > >>>>> =C2=A0 EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, CXL); > >>>> Does type2 device also exports a CDAT? > >>>> > >>> Yes. Type2 can also export a CDAT. > >> Thanks! Probably should have the split out helpers regardless. > >=20 > >=20 > > Maybe, but should not we wait until that is required? I did not see the= need for adding them with this patchset. >=20 > Sure. I think my concern is with paths that apply only to one type but no= t the other. If you have not encountered any then we can wait. >=20 Agree. I was thinking that for long-term, maybe CDAT routines shouldn't be tied to device type, for me, it is like a cap that can be probed-and-used. E.g. when talking with DOE, the core knows if CDAT is available or not, similar case when the core tries to reach it via mailbox. Z. > DJ >=20 > >=20 > >=20 > >>>> I'm also wondering if we should have distinctive helpers: > >>>> is_cxl_type3_memdev() > >>>> is_cxl_type2_memdev() > >>>> > >>>> and is_cxl_memdev() is just calling those two helpers above. > >>>> > >>>> And if no CDAT is exported, we should change the is_cxl_memdev() to > >>>> is_cxl_type3_memdev() in read_cdat_data(). > >>>> > >>>> DJ > >>>> > >>>>> =C2=A0 @@ -660,7 +668,10 @@ static struct cxl_memdev > >>>>> *cxl_memdev_alloc(struct cxl_dev_state *cxlds, dev->parent =3D > >>>>> cxlds->dev; dev->bus =3D &cxl_bus_type; > >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dev->devt =3D MKDEV(cxl_mem_major, c= xlmd->id); > >>>>> -=C2=A0=C2=A0=C2=A0 dev->type =3D &cxl_memdev_type; > >>>>> +=C2=A0=C2=A0=C2=A0 if (cxlds->type =3D=3D CXL_DEVTYPE_DEVMEM) > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dev->type =3D &cxl_acce= l_memdev_type; > >>>>> +=C2=A0=C2=A0=C2=A0 else > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dev->type =3D &cxl_memd= ev_type; > >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 device_set_pm_not_required(dev); > >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 INIT_WORK(&cxlmd->detach_work, detac= h_memdev); > >>>>> =C2=A0 diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/re= gion.c > >>>>> index dff618c708dc..622e3bb2e04b 100644 > >>>>> --- a/drivers/cxl/core/region.c > >>>>> +++ b/drivers/cxl/core/region.c > >>>>> @@ -1948,7 +1948,8 @@ static int cxl_region_attach(struct > >>>>> cxl_region *cxlr, return -EINVAL; > >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } > >>>>> =C2=A0 -=C2=A0=C2=A0=C2=A0 cxl_region_perf_data_calculate(cxlr, cxl= ed); > >>>>> +=C2=A0=C2=A0=C2=A0 if (cxlr->type =3D=3D CXL_DECODER_HOSTONLYMEM) > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cxl_region_perf_data_ca= lculate(cxlr, cxled); > >>>>> =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (test_bit(CXL_REGION_F_AUT= O, &cxlr->flags)) { > >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int i; > >>>>> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > >>>>> index a9fd5cd5a0d2..cb771bf196cd 100644 > >>>>> --- a/drivers/cxl/mem.c > >>>>> +++ b/drivers/cxl/mem.c > >>>>> @@ -130,12 +130,18 @@ static int cxl_mem_probe(struct device *dev) > >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dentry =3D cxl_debugfs_create_dir(de= v_name(dev)); > >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 debugfs_create_devm_seqfile(dev, "dp= amem", dentry, > >>>>> cxl_mem_dpa_show); > >>>>> -=C2=A0=C2=A0=C2=A0 if (test_bit(CXL_POISON_ENABLED_INJECT, > >>>>> mds->poison.enabled_cmds)) > >>>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 debugfs_create_file("in= ject_poison", 0200, dentry, > >>>>> cxlmd, > >>>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 &cxl_poison_inject_fops); > >>>>> -=C2=A0=C2=A0=C2=A0 if (test_bit(CXL_POISON_ENABLED_CLEAR, > >>>>> mds->poison.enabled_cmds)) > >>>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 debugfs_create_file("cl= ear_poison", 0200, dentry, > >>>>> cxlmd, > >>>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 &cxl_poison_clear_fops); > >>>>> +=C2=A0=C2=A0=C2=A0 /* > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 * Avoid poison debugfs files for Type2 de= vices as they > >>>>> rely on > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 * cxl_memdev_state. > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 */ > >>>>> +=C2=A0=C2=A0=C2=A0 if (mds) { > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (test_bit(CXL_POISON= _ENABLED_INJECT, > >>>>> mds->poison.enabled_cmds)) > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= debugfs_create_file("inject_poison", 0200, > >>>>> dentry, cxlmd, > >>>>> + > >>>>> &cxl_poison_inject_fops); > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (test_bit(CXL_POISON= _ENABLED_CLEAR, > >>>>> mds->poison.enabled_cmds)) > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= debugfs_create_file("clear_poison", 0200, > >>>>> dentry, cxlmd, > >>>>> + > >>>>> &cxl_poison_clear_fops); > >>>>> +=C2=A0=C2=A0=C2=A0 } > >>>>> =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rc =3D devm_add_action_or_res= et(dev, remove_debugfs, dentry); > >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (rc) > >>>>> @@ -219,6 +225,13 @@ static umode_t cxl_mem_visible(struct kobject > >>>>> *kobj, struct attribute *a, int n) struct cxl_memdev *cxlmd =3D > >>>>> to_cxl_memdev(dev); struct cxl_memdev_state *mds =3D > >>>>> to_cxl_memdev_state(cxlmd->cxlds); > >>>>> +=C2=A0=C2=A0=C2=A0 /* > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 * Avoid poison sysfs files for Type2 devi= ces as they rely > >>>>> on > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 * cxl_memdev_state. > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 */ > >>>>> +=C2=A0=C2=A0=C2=A0 if (!mds) > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return 0; > >>>>> + > >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (a =3D=3D &dev_attr_trigger_poiso= n_list.attr) > >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (!test_bi= t(CXL_POISON_ENABLED_LIST, > >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 mds->poison.enabled_cmds)) > >>>>> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h > >>>>> index 6033ce84b3d3..5608ed0f5f15 100644 > >>>>> --- a/include/cxl/cxl.h > >>>>> +++ b/include/cxl/cxl.h > >>>>> @@ -57,4 +57,6 @@ int cxl_pci_accel_setup_regs(struct pci_dev > >>>>> *pdev, struct cxl_dev_state *cxlds); int > >>>>> cxl_request_resource(struct cxl_dev_state *cxlds, enum cxl_resource > >>>>> type); int cxl_release_resource(struct cxl_dev_state *cxlds, enum > >>>>> cxl_resource type); void cxl_set_media_ready(struct cxl_dev_state > >>>>> *cxlds); +struct cxl_memdev *devm_cxl_add_memdev(struct device > >>>>> *host, > >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct c= xl_dev_state > >>>>> *cxlds); #endif > >>>> >=20 >=20