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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Davis , Andrew Lunn , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next v2 2/2] net: phy: dp83822: Add support for GPIO2 clock output Message-ID: <20241211105242.GB4424@debian> References: <20241211-dp83822-gpio2-clk-out-v2-0-614a54f6acab@liebherr.com> <20241211-dp83822-gpio2-clk-out-v2-2-614a54f6acab@liebherr.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Am Wed, Dec 11, 2024 at 10:45:53AM +0100 schrieb Krzysztof Kozlowski: > On Wed, Dec 11, 2024 at 09:04:40AM +0100, Dimitri Fedrau wrote: > > The GPIO2 pin on the DP83822 can be configured as clock output. Add support > > for configuration via DT. > > > > Signed-off-by: Dimitri Fedrau > > --- > > drivers/net/phy/dp83822.c | 40 ++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 40 insertions(+) > > > > diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c > > index 25ee09c48027c86b7d8f4acb5cbe2e157c56a85a..dc5595eae6cc74e5c77914d53772c5fad64c3e70 100644 > > --- a/drivers/net/phy/dp83822.c > > +++ b/drivers/net/phy/dp83822.c > > @@ -14,6 +14,8 @@ > > #include > > #include > > > > +#include > > + > > #define DP83822_PHY_ID 0x2000a240 > > #define DP83825S_PHY_ID 0x2000a140 > > #define DP83825I_PHY_ID 0x2000a150 > > @@ -30,6 +32,7 @@ > > #define MII_DP83822_FCSCR 0x14 > > #define MII_DP83822_RCSR 0x17 > > #define MII_DP83822_RESET_CTRL 0x1f > > +#define MII_DP83822_IOCTRL2 0x463 > > #define MII_DP83822_GENCFG 0x465 > > #define MII_DP83822_SOR1 0x467 > > > > @@ -104,6 +107,11 @@ > > #define DP83822_RX_CLK_SHIFT BIT(12) > > #define DP83822_TX_CLK_SHIFT BIT(11) > > > > +/* IOCTRL2 bits */ > > +#define DP83822_IOCTRL2_GPIO2_CLK_SRC GENMASK(6, 4) > > +#define DP83822_IOCTRL2_GPIO2_CTRL GENMASK(2, 0) > > +#define DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF GENMASK(1, 0) > > + > > /* SOR1 mode */ > > #define DP83822_STRAP_MODE1 0 > > #define DP83822_STRAP_MODE2 BIT(0) > > @@ -139,6 +147,8 @@ struct dp83822_private { > > u8 cfg_dac_minus; > > u8 cfg_dac_plus; > > struct ethtool_wolinfo wol; > > + bool set_gpio2_clk_out; > > + u32 gpio2_clk_out; > > }; > > > > static int dp83822_config_wol(struct phy_device *phydev, > > @@ -413,6 +423,15 @@ static int dp83822_config_init(struct phy_device *phydev) > > int err = 0; > > int bmcr; > > > > + if (dp83822->set_gpio2_clk_out) > > + phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2, > > + DP83822_IOCTRL2_GPIO2_CTRL | > > + DP83822_IOCTRL2_GPIO2_CLK_SRC, > > + FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL, > > + DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF) | > > + FIELD_PREP(DP83822_IOCTRL2_GPIO2_CLK_SRC, > > + dp83822->gpio2_clk_out)); > > You include the header but you do not use the defines, so it's a proof > these are register values. Register values are not bindings, they do not > bind anything. Bindings are imaginary numbers starting from 0 or 1 which > are used between drivers and DTS, serving as abstraction layer (or > abstraction values) between these two. > > You do not have here abstraction. Drop the bindings header entirely. > Ok, thanks for the explanation. Best regards, Dimitri Fedrau