[PATCH 0/3] dsa: mv88e6xxx: Add RMU enable/disable ops

[PATCH 0/3] dsa: mv88e6xxx: Add RMU enable/disable ops

[Andrew Lunn]

Add internal APIs for enabling the Remote Management Unit, and
extending the existing implementation to other families. Actually
making use of the RMU is not included here, that will be part of a
later big patch set, which without this preliminary patchset would be
too big.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
Andrew Lunn (2):
      net: dsa: mv88e6xxx: Enable RMU on 6165 family
      net: dsa: mv88e6xxx: Enable RMU on 6351 family

Mattias Forsblad (1):
      net: dsa: mv88e6xxx: Add RMU enable for switches that support disable.

 drivers/net/dsa/mv88e6xxx/chip.c    | 29 ++++++++++++
 drivers/net/dsa/mv88e6xxx/chip.h    |  1 +
 drivers/net/dsa/mv88e6xxx/global1.c | 89 +++++++++++++++++++++++++++++++++++++
 drivers/net/dsa/mv88e6xxx/global1.h | 10 +++++
 4 files changed, 129 insertions(+)
---
base-commit: 2c2b61d2138f472e50b5531ec0cb4a1485837e21
change-id: 20241207-v6-13-rc1-net-next-mv88e6xxx-rmu-ops-4d0a84f5f7d1

Best regards,
-- 
Andrew Lunn <andrew@lunn.ch>

[PATCH 1/3] net: dsa: mv88e6xxx: Add RMU enable for switches that support disable.

[Andrew Lunn]

From: Mattias Forsblad <mattias.forsblad@gmail.com>

Add RMU enable functionality for Marvell SOHO switches which already
support disabling the RMU.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Mattias Forsblad <mattias.forsblad@gmail.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
 drivers/net/dsa/mv88e6xxx/chip.c    | 15 +++++++++
 drivers/net/dsa/mv88e6xxx/chip.h    |  1 +
 drivers/net/dsa/mv88e6xxx/global1.c | 64 +++++++++++++++++++++++++++++++++++++
 drivers/net/dsa/mv88e6xxx/global1.h |  3 ++
 4 files changed, 83 insertions(+)

diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 570c8642d3871c5cdd20fc61814a3747e32063fe..46f81b925208024b9029d6d674ebb5816a615e68 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -4197,6 +4197,7 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {
 	.ppu_disable = mv88e6185_g1_ppu_disable,
 	.reset = mv88e6185_g1_reset,
 	.rmu_disable = mv88e6085_g1_rmu_disable,
+	.rmu_enable = mv88e6085_g1_rmu_enable,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
 	.stu_getnext = mv88e6352_g1_stu_getnext,
@@ -4275,6 +4276,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {
 	.pot_clear = mv88e6xxx_g2_pot_clear,
 	.reset = mv88e6352_g1_reset,
 	.rmu_disable = mv88e6085_g1_rmu_disable,
+	.rmu_enable = mv88e6085_g1_rmu_enable,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
 	.phylink_get_caps = mv88e6095_phylink_get_caps,
@@ -4410,6 +4412,7 @@ static const struct mv88e6xxx_ops mv88e6141_ops = {
 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
 	.reset = mv88e6352_g1_reset,
 	.rmu_disable = mv88e6390_g1_rmu_disable,
+	.rmu_enable = mv88e6390_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
@@ -4603,6 +4606,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
 	.reset = mv88e6352_g1_reset,
 	.rmu_disable = mv88e6352_g1_rmu_disable,
+	.rmu_enable = mv88e6352_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
@@ -4706,6 +4710,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
 	.reset = mv88e6352_g1_reset,
 	.rmu_disable = mv88e6352_g1_rmu_disable,
+	.rmu_enable = mv88e6352_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
@@ -4802,6 +4807,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
 	.reset = mv88e6352_g1_reset,
 	.rmu_disable = mv88e6390_g1_rmu_disable,
+	.rmu_enable = mv88e6390_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
@@ -4862,6 +4868,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
 	.reset = mv88e6352_g1_reset,
 	.rmu_disable = mv88e6390_g1_rmu_disable,
+	.rmu_enable = mv88e6390_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
@@ -4920,6 +4927,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
 	.reset = mv88e6352_g1_reset,
 	.rmu_disable = mv88e6390_g1_rmu_disable,
+	.rmu_enable = mv88e6390_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
@@ -4982,6 +4990,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
 	.reset = mv88e6352_g1_reset,
 	.rmu_disable = mv88e6352_g1_rmu_disable,
+	.rmu_enable = mv88e6352_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
@@ -5086,6 +5095,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
 	.reset = mv88e6352_g1_reset,
 	.rmu_disable = mv88e6390_g1_rmu_disable,
+	.rmu_enable = mv88e6390_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
@@ -5247,6 +5257,7 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {
 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
 	.reset = mv88e6352_g1_reset,
 	.rmu_disable = mv88e6390_g1_rmu_disable,
+	.rmu_enable = mv88e6390_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
@@ -5405,6 +5416,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
 	.reset = mv88e6352_g1_reset,
 	.rmu_disable = mv88e6352_g1_rmu_disable,
+	.rmu_enable = mv88e6352_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
@@ -5469,6 +5481,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
 	.reset = mv88e6352_g1_reset,
 	.rmu_disable = mv88e6390_g1_rmu_disable,
+	.rmu_enable = mv88e6390_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
@@ -5533,6 +5546,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
 	.reset = mv88e6352_g1_reset,
 	.rmu_disable = mv88e6390_g1_rmu_disable,
+	.rmu_enable = mv88e6390_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
@@ -5600,6 +5614,7 @@ static const struct mv88e6xxx_ops mv88e6393x_ops = {
 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
 	.reset = mv88e6352_g1_reset,
 	.rmu_disable = mv88e6390_g1_rmu_disable,
+	.rmu_enable = mv88e6390_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
index 86bf113c9bfa1e9ca15d0d651ea96a56a4c14605..11f8cb6f827313e49b63d1c871e501ce96f57d2a 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -672,6 +672,7 @@ struct mv88e6xxx_ops {
 
 	/* Remote Management Unit operations */
 	int (*rmu_disable)(struct mv88e6xxx_chip *chip);
+	int (*rmu_enable)(struct mv88e6xxx_chip *chip, int port);
 
 	/* Precision Time Protocol operations */
 	const struct mv88e6xxx_ptp_ops *ptp_ops;
diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c
index 9820cd596757431be332369449526fcef8ce6dce..ae0b6e5628184042404c208273ece55650cbc433 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.c
+++ b/drivers/net/dsa/mv88e6xxx/global1.c
@@ -536,18 +536,82 @@ int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
 				      MV88E6085_G1_CTL2_RM_ENABLE, 0);
 }
 
+int mv88e6085_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port)
+{
+	int val = MV88E6352_G1_CTL2_RMU_MODE_DISABLED;
+
+	switch (port) {
+	case 9:
+		val = MV88E6085_G1_CTL2_RM_ENABLE;
+		break;
+	case 10:
+		val = MV88E6085_G1_CTL2_RM_ENABLE | MV88E6085_G1_CTL2_P10RM;
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
+				      MV88E6085_G1_CTL2_RM_ENABLE, val);
+}
+
 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
 {
 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
 				      MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
 }
 
+int mv88e6352_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port)
+{
+	int val = MV88E6352_G1_CTL2_RMU_MODE_DISABLED;
+
+	switch (port) {
+	case 4:
+		val = MV88E6352_G1_CTL2_RMU_MODE_PORT_4;
+		break;
+	case 5:
+		val = MV88E6352_G1_CTL2_RMU_MODE_PORT_5;
+		break;
+	case 6:
+		val = MV88E6352_G1_CTL2_RMU_MODE_PORT_6;
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, val);
+}
+
 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
 {
 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
 				      MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
 }
 
+int mv88e6390_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port)
+{
+	int val = MV88E6390_G1_CTL2_RMU_MODE_DISABLED;
+
+	switch (port) {
+	case 0:
+		val = MV88E6390_G1_CTL2_RMU_MODE_PORT_0;
+		break;
+	case 1:
+		val = MV88E6390_G1_CTL2_RMU_MODE_PORT_1;
+		break;
+	case 9:
+		val = MV88E6390_G1_CTL2_RMU_MODE_PORT_9;
+		break;
+	case 10:
+		val = MV88E6390_G1_CTL2_RMU_MODE_PORT_10;
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, val);
+}
+
 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
 {
 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK,
diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h
index 3dbb7a1b8fe1188f2a0f2fdfaa35798b0b3dfcb0..4624d1bdfc2430d51be747662a25e7b5325e8c79 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.h
+++ b/drivers/net/dsa/mv88e6xxx/global1.h
@@ -316,8 +316,11 @@ int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
 
 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);
+int mv88e6085_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port);
 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);
+int mv88e6352_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port);
 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);
+int mv88e6390_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port);
 
 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);
 

-- 
2.45.2

[PATCH 2/3] net: dsa: mv88e6xxx: Enable RMU on 6165 family

[Andrew Lunn]

The 6165 family allows the use of the RMU on ports 5 and 6.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
 drivers/net/dsa/mv88e6xxx/chip.c    |  6 ++++++
 drivers/net/dsa/mv88e6xxx/global1.c | 25 +++++++++++++++++++++++++
 drivers/net/dsa/mv88e6xxx/global1.h |  7 +++++++
 3 files changed, 38 insertions(+)

diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 46f81b925208024b9029d6d674ebb5816a615e68..fe471ff4cd8ea8bb6654c61d0b95bb66c2e12157 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -4317,6 +4317,8 @@ static const struct mv88e6xxx_ops mv88e6123_ops = {
 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
 	.pot_clear = mv88e6xxx_g2_pot_clear,
 	.reset = mv88e6352_g1_reset,
+	.rmu_disable = mv88e6165_g1_rmu_disable,
+	.rmu_enable = mv88e6165_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
@@ -4467,6 +4469,8 @@ static const struct mv88e6xxx_ops mv88e6161_ops = {
 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
 	.pot_clear = mv88e6xxx_g2_pot_clear,
 	.reset = mv88e6352_g1_reset,
+	.rmu_disable = mv88e6165_g1_rmu_disable,
+	.rmu_enable = mv88e6165_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
@@ -4505,6 +4509,8 @@ static const struct mv88e6xxx_ops mv88e6165_ops = {
 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
 	.pot_clear = mv88e6xxx_g2_pot_clear,
 	.reset = mv88e6352_g1_reset,
+	.rmu_disable = mv88e6165_g1_rmu_disable,
+	.rmu_enable = mv88e6165_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c
index ae0b6e5628184042404c208273ece55650cbc433..fcddba505ca3b8ddc0bc1a1e0576a5e08a51ef0e 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.c
+++ b/drivers/net/dsa/mv88e6xxx/global1.c
@@ -555,6 +555,31 @@ int mv88e6085_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port)
 				      MV88E6085_G1_CTL2_RM_ENABLE, val);
 }
 
+int mv88e6165_g1_rmu_disable(struct mv88e6xxx_chip *chip)
+{
+	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6165_G1_CTL2_RMU_MODE_MASK,
+				      MV88E6165_G1_CTL2_RMU_DISABLED);
+}
+
+int mv88e6165_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port)
+{
+	int val;
+
+	switch (port) {
+	case 4:
+		val = MV88E6165_G1_CTL2_RMU_MODE_PORT_4;
+		break;
+	case 5:
+		val = MV88E6165_G1_CTL2_RMU_MODE_PORT_5;
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6165_G1_CTL2_RMU_MODE_MASK,
+				      val);
+}
+
 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
 {
 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h
index 4624d1bdfc2430d51be747662a25e7b5325e8c79..b8a28afcdcd695c519679976d1361fb7235411a6 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.h
+++ b/drivers/net/dsa/mv88e6xxx/global1.h
@@ -235,6 +235,11 @@
 #define MV88E6085_G1_CTL2_DA_CHECK		0x4000
 #define MV88E6085_G1_CTL2_P10RM			0x2000
 #define MV88E6085_G1_CTL2_RM_ENABLE		0x1000
+#define MV88E6165_G1_CTL2_RMU_MODE_MASK		0x0300
+#define MV88E6165_G1_CTL2_RMU_DISABLED	        0x0000
+#define MV88E6165_G1_CTL2_RMU_MODE_PORT_4	0x0100
+#define MV88E6165_G1_CTL2_RMU_MODE_PORT_5	0x0200
+#define MV88E6165_G1_CTL2_RMU_MODE_PORT_RECVD	0x0300
 #define MV88E6352_G1_CTL2_DA_CHECK		0x0800
 #define MV88E6390_G1_CTL2_RMU_MODE_MASK		0x0700
 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_0	0x0000
@@ -317,6 +322,8 @@ int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
 
 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);
 int mv88e6085_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port);
+int mv88e6165_g1_rmu_disable(struct mv88e6xxx_chip *chip);
+int mv88e6165_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port);
 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);
 int mv88e6352_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port);
 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);

-- 
2.45.2

[PATCH 3/3] net: dsa: mv88e6xxx: Enable RMU on 6351 family

[Andrew Lunn]

The 6351 family of switches has the same RMU configuration as the 6352
family.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
 drivers/net/dsa/mv88e6xxx/chip.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index fe471ff4cd8ea8bb6654c61d0b95bb66c2e12157..300a2acfdd941f30d5ae7cb16062ee269e04178a 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -4559,6 +4559,8 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {
 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
 	.pot_clear = mv88e6xxx_g2_pot_clear,
 	.reset = mv88e6352_g1_reset,
+	.rmu_disable = mv88e6352_g1_rmu_disable,
+	.rmu_enable = mv88e6352_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
@@ -4663,6 +4665,8 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {
 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
 	.pot_clear = mv88e6xxx_g2_pot_clear,
 	.reset = mv88e6352_g1_reset,
+	.rmu_disable = mv88e6352_g1_rmu_disable,
+	.rmu_enable = mv88e6352_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
@@ -5321,6 +5325,8 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {
 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
 	.pot_clear = mv88e6xxx_g2_pot_clear,
 	.reset = mv88e6352_g1_reset,
+	.rmu_disable = mv88e6352_g1_rmu_disable,
+	.rmu_enable = mv88e6352_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
@@ -5367,6 +5373,8 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
 	.pot_clear = mv88e6xxx_g2_pot_clear,
 	.reset = mv88e6352_g1_reset,
+	.rmu_disable = mv88e6352_g1_rmu_disable,
+	.rmu_enable = mv88e6352_g1_rmu_enable,
 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
 	.vtu_getnext = mv88e6352_g1_vtu_getnext,

-- 
2.45.2

Re: [PATCH 0/3] dsa: mv88e6xxx: Add RMU enable/disable ops

[Andrew Lunn]

On Sun, Dec 15, 2024 at 05:30:02PM +0000, Andrew Lunn wrote:
> Add internal APIs for enabling the Remote Management Unit, and
> extending the existing implementation to other families. Actually
> making use of the RMU is not included here, that will be part of a
> later big patch set, which without this preliminary patchset would be
> too big.

Gerr, forget to use b4 --set-prefixes net-next

	Andrew

Re: [PATCH 0/3] dsa: mv88e6xxx: Add RMU enable/disable ops

[Vladimir Oltean]

Hi Andrew,

On Sun, Dec 15, 2024 at 05:30:02PM +0000, Andrew Lunn wrote:
> Add internal APIs for enabling the Remote Management Unit, and
> extending the existing implementation to other families. Actually
> making use of the RMU is not included here, that will be part of a
> later big patch set, which without this preliminary patchset would be
> too big.
> 
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---

How big is the later patch set? Too big to accept even one more patch?

There is a risk that the RMU effort gets abandoned before it becomes
functional. And in that case, we will have a newly introduced rmu_enable()
operation which does nothing.

Could you splice the first patch of this set, providing rmu_enable() for
some switches but not all, with the set that integrates the RMU with DSA?
If the big set is accepted, a trivial follow-up will be necessary to
complete the support. If it is not accepted, we don't end up with merged
code that we don't need.

Re: [PATCH 0/3] dsa: mv88e6xxx: Add RMU enable/disable ops

[Andrew Lunn]

On Mon, Dec 16, 2024 at 12:59:10AM +0200, Vladimir Oltean wrote:
> Hi Andrew,
> 
> On Sun, Dec 15, 2024 at 05:30:02PM +0000, Andrew Lunn wrote:
> > Add internal APIs for enabling the Remote Management Unit, and
> > extending the existing implementation to other families. Actually
> > making use of the RMU is not included here, that will be part of a
> > later big patch set, which without this preliminary patchset would be
> > too big.
> > 
> > Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> > ---
> 
> How big is the later patch set? Too big to accept even one more patch?

The patchset is 21 patches, if i only support one switch family.

I can remove a couple of patches, getting statistics via RMU, and
timing the RMU vs MDIO and disabling RMU if it is slower.

The other way i can slice it is split it into two patchsets:

1) incremental modifications to qca8k to centralise code
2) implement the mv88e6xxx changes to add RMU to it.

I did not really want to slice it like this, because the central API
is designed around what both QCA8K and Marvell needs, and hopefully is
generic enough for other devices. But there might be questions asked
when you can only see the qca8k refactor without the Marvell parts.

I can maybe squash some of the QCA patches together. Previously i was
doing lots of simple changes because i did not have hardware to test
on. I do have a QCA8K test system now.

> There is a risk that the RMU effort gets abandoned before it becomes
> functional. And in that case, we will have a newly introduced rmu_enable()
> operation which does nothing.

True, but i'm more motivated this time, i'm getting paid for the work :-)

And there is one other interested party as well that i know of.

This patch series is fully self contained, so it easy to revert, if
this ends up going nowhere.

	Andrew

Re: [PATCH 0/3] dsa: mv88e6xxx: Add RMU enable/disable ops

[Vladimir Oltean]

On Mon, Dec 16, 2024 at 10:50:47AM +0100, Andrew Lunn wrote:
> > How big is the later patch set? Too big to accept even one more patch?
> 
> The patchset is 21 patches, if i only support one switch family.
> 
> I can remove a couple of patches, getting statistics via RMU, and
> timing the RMU vs MDIO and disabling RMU if it is slower.
> 
> The other way i can slice it is split it into two patchsets:
> 
> 1) incremental modifications to qca8k to centralise code
> 2) implement the mv88e6xxx changes to add RMU to it.
> 
> I did not really want to slice it like this, because the central API
> is designed around what both QCA8K and Marvell needs, and hopefully is
> generic enough for other devices. But there might be questions asked
> when you can only see the qca8k refactor without the Marvell parts.
> 
> I can maybe squash some of the QCA patches together. Previously i was
> doing lots of simple changes because i did not have hardware to test
> on. I do have a QCA8K test system now.
> 
> > There is a risk that the RMU effort gets abandoned before it becomes
> > functional. And in that case, we will have a newly introduced rmu_enable()
> > operation which does nothing.
> 
> True, but i'm more motivated this time, i'm getting paid for the work :-)
> 
> And there is one other interested party as well that i know of.
> 
> This patch series is fully self contained, so it easy to revert, if
> this ends up going nowhere.

So what's a no-go is introducing code with no user.

Splitting into 2 sets like this should be fine. You could post a link to
Github with the complete picture when you post the qca8k refactoring, so
that we know what to expect next and where things are going. Hopefully
it makes sense on its own and does not leave loose ends hanging.

I don't think that squashing multiple logical changes to fit the 15
patch limit is a good idea.

Re: [PATCH 0/3] dsa: mv88e6xxx: Add RMU enable/disable ops

[Jakub Kicinski]

On Mon, 16 Dec 2024 16:59:40 +0200 Vladimir Oltean wrote:
> > > There is a risk that the RMU effort gets abandoned before it becomes
> > > functional. And in that case, we will have a newly introduced rmu_enable()
> > > operation which does nothing.  
> > 
> > True, but i'm more motivated this time, i'm getting paid for the work :-)
> > 
> > And there is one other interested party as well that i know of.
> > 
> > This patch series is fully self contained, so it easy to revert, if
> > this ends up going nowhere.  
> 
> So what's a no-go is introducing code with no user.
> 
> Splitting into 2 sets like this should be fine. You could post a link to
> Github with the complete picture when you post the qca8k refactoring, so
> that we know what to expect next and where things are going. Hopefully
> it makes sense on its own and does not leave loose ends hanging.
> 
> I don't think that squashing multiple logical changes to fit the 15
> patch limit is a good idea.

Yes, we're not religious about the 15 patch rule. If you give it 
an honest try and it doesn't make sense just say so in the cover
letter.