From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 343D03EA76; Tue, 24 Dec 2024 17:04:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735059867; cv=none; b=m4y8OzF7AXqbnqAxKiUflhVxRM7GLpnwIOoQQJv3McW67UTQtj1Ym1e3AMvrYa5lvW+OEPFH4V9NnrMmOhGyzATfG0BPl3M5ENqoXJt9EhjMvGZ3OJResK37awkOlqbojTIOHlQsHXbSQzvokHWEj88q736wE4FNGaZwgdOlbdo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735059867; c=relaxed/simple; bh=M7eAf831o2qzlQUMnckK5y5sVhnCPT8tUCh9dq50mXA=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EWVDq8ReMbJreNds0Jn4MPL+4L0pImhYXu97kdu1yIggSj5WJxY9ELTs0KCYT72FoTEWhD8h+JiKvuczVyX9vHsolooI0v3uQ/2nOarfLLp1oPFIzs/EajfyOGjjMq1GdyV0lpNgpaYFrgm8Pn2vsvhIFOXPkslT59lDZS3uVhY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YHh3H0gL1z6K5qN; Wed, 25 Dec 2024 01:00:27 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 77A69140133; Wed, 25 Dec 2024 01:04:20 +0800 (CST) Received: from localhost (10.48.156.150) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 24 Dec 2024 18:04:19 +0100 Date: Tue, 24 Dec 2024 17:04:16 +0000 From: Jonathan Cameron To: CC: , , , , , , , , , , Alejandro Lucero Subject: Re: [PATCH v8 02/27] sfc: add cxl support using new CXL API Message-ID: <20241224170416.00000541@huawei.com> In-Reply-To: <20241216161042.42108-3-alejandro.lucero-palau@amd.com> References: <20241216161042.42108-1-alejandro.lucero-palau@amd.com> <20241216161042.42108-3-alejandro.lucero-palau@amd.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml100011.china.huawei.com (7.191.174.247) To frapeml500008.china.huawei.com (7.182.85.71) On Mon, 16 Dec 2024 16:10:17 +0000 wrote: > From: Alejandro Lucero > > Add CXL initialization based on new CXL API for accel drivers and make > it dependent on kernel CXL configuration. > > Signed-off-by: Alejandro Lucero > Reviewed-by: Martin Habets > Acked-by: Edward Cree Hi Alejandro A few minor comments inline. Assuming those are tidied up. Reviewed-by: Jonathan Cameron > diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c > new file mode 100644 > index 000000000000..356d7a977e1c > --- /dev/null > +++ b/drivers/net/ethernet/sfc/efx_cxl.c > @@ -0,0 +1,87 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/**************************************************************************** > + * > + * Driver for AMD network controllers and boards > + * Copyright (C) 2024, Advanced Micro Devices, Inc. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation, incorporated herein by reference. > + */ > + > +#include > +#include > +#include > + > +#include "net_driver.h" > +#include "efx_cxl.h" > + > +#define EFX_CTPIO_BUFFER_SIZE SZ_256M > + > +int efx_cxl_init(struct efx_probe_data *probe_data) > +{ > + struct efx_nic *efx = &probe_data->efx; > + struct pci_dev *pci_dev; > + struct efx_cxl *cxl; > + struct resource res; > + u16 dvsec; > + int rc; > + > + pci_dev = efx->pci_dev; Trivial, but maybe put that one inline at the declaration above. > + probe_data->cxl_pio_initialised = false; > + > + dvsec = pci_find_dvsec_capability(pci_dev, PCI_VENDOR_ID_CXL, > + CXL_DVSEC_PCIE_DEVICE); > + if (!dvsec) > + return 0; > + > + pci_dbg(pci_dev, "CXL_DVSEC_PCIE_DEVICE capability found\n"); > + > + cxl = kzalloc(sizeof(*cxl), GFP_KERNEL); > + if (!cxl) > + return -ENOMEM; > + > + cxl->cxlds = cxl_accel_state_create(&pci_dev->dev); > + if (IS_ERR(cxl->cxlds)) { > + pci_err(pci_dev, "CXL accel device state failed"); > + rc = -ENOMEM; > + goto err_state; > + } > + > + cxl_set_dvsec(cxl->cxlds, dvsec); > + cxl_set_serial(cxl->cxlds, pci_dev->dev.id); > + > + res = DEFINE_RES_MEM(0, EFX_CTPIO_BUFFER_SIZE); > + if (cxl_set_resource(cxl->cxlds, res, CXL_RES_DPA)) { > + pci_err(pci_dev, "cxl_set_resource DPA failed\n"); > + rc = -EINVAL; > + goto err_resource_set; > + } > + > + res = DEFINE_RES_MEM_NAMED(0, EFX_CTPIO_BUFFER_SIZE, "ram"); > + if (cxl_set_resource(cxl->cxlds, res, CXL_RES_RAM)) { > + pci_err(pci_dev, "cxl_set_resource RAM failed\n"); > + rc = -EINVAL; > + goto err_resource_set; > + } > + > + probe_data->cxl = cxl; > + > + return 0; > + > +err_resource_set: > + kfree(cxl->cxlds); > +err_state: > + kfree(cxl); > + return rc; > +} > + > +void efx_cxl_exit(struct efx_probe_data *probe_data) > +{ > + if (probe_data->cxl) { > + kfree(probe_data->cxl->cxlds); > + kfree(probe_data->cxl); > + } > +} > + > +MODULE_IMPORT_NS("CXL"); > diff --git a/drivers/net/ethernet/sfc/efx_cxl.h b/drivers/net/ethernet/sfc/efx_cxl.h > new file mode 100644 > index 000000000000..90fa46bc94db > --- /dev/null > +++ b/drivers/net/ethernet/sfc/efx_cxl.h > @@ -0,0 +1,28 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/**************************************************************************** > + * Driver for AMD network controllers and boards > + * Copyright (C) 2024, Advanced Micro Devices, Inc. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation, incorporated herein by reference. > + */ > + > +#ifndef EFX_CXL_H > +#define EFX_CXL_H > + > +struct efx_nic; Not sure why you need this one, but... struct efx_probe_data; struct cxl_dev_state; struct cxl_memdev; etc. are probably a good idea to avoid potential issues with include reorderings in the future. > + > +struct efx_cxl { > + struct cxl_dev_state *cxlds; > + struct cxl_memdev *cxlmd; > + struct cxl_root_decoder *cxlrd; > + struct cxl_port *endpoint; > + struct cxl_endpoint_decoder *cxled; > + struct cxl_region *efx_region; > + void __iomem *ctpio_cxl; > +}; > + > +int efx_cxl_init(struct efx_probe_data *probe_data); > +void efx_cxl_exit(struct efx_probe_data *probe_data); > +#endif