From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEA1C190059; Thu, 2 Jan 2025 14:53:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735829643; cv=none; b=CXhyDhFxfbg/R6AWlaPK2KistJviXcDErDGZf0aqbSchGIGTGX5cz3cbEpm3qxS4DCsTiLE7ZkWJvyLPMAPOhuaQ5tklE8ful3A2JbJzr/M395RVWyJf6w6zo+e8tNldBfyq/30SVzY3zQzewtZmcOaqGg00rGVo1H1P0ettQMs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735829643; c=relaxed/simple; bh=FReYFJD+0p0in0BerEUh3dCvq9xqaXboVVI88xlp9Cs=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hxnvkspvefsSf6wqHSH3PgMkCxlQ+t46O+c1jkb/1bb5yvJAwhVP+tuFYlICvOiUa9m/FotCo2uke0izyKD1IW6zZ27mdZeluowwbRcoFDnxvHh5vHaikQuFzJc2iAv+kfRXb+yqK2jX+/zUT5+mSAL88P4DCR5auRPCXxn5La8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YP8pC5G9Wz6K5xS; Thu, 2 Jan 2025 22:53:07 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id B14C6140A9C; Thu, 2 Jan 2025 22:53:56 +0800 (CST) Received: from localhost (10.203.177.66) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Thu, 2 Jan 2025 15:53:56 +0100 Date: Thu, 2 Jan 2025 14:53:54 +0000 From: Jonathan Cameron To: CC: , , , , , , , , , Alejandro Lucero Subject: Re: [PATCH v9 06/27] cxl: add function for type2 cxl regs setup Message-ID: <20250102145354.00007ae3@huawei.com> In-Reply-To: <20241230214445.27602-7-alejandro.lucero-palau@amd.com> References: <20241230214445.27602-1-alejandro.lucero-palau@amd.com> <20241230214445.27602-7-alejandro.lucero-palau@amd.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml100010.china.huawei.com (7.191.174.197) To frapeml500008.china.huawei.com (7.182.85.71) On Mon, 30 Dec 2024 21:44:24 +0000 wrote: > From: Alejandro Lucero > > Create a new function for a type2 device initialising > cxl_dev_state struct regarding cxl regs setup and mapping. > > Signed-off-by: Alejandro Lucero > Reviewed-by: Dave Jiang > Reviewed-by: Fan Ni Hi Alejandro I think there was one additional change you were going to make based on v8 feedback. See inline. With that add Reviewed-by: Jonathan Cameron > --- > drivers/cxl/core/pci.c | 51 ++++++++++++++++++++++++++++++++++++++++++ > include/cxl/cxl.h | 2 ++ > 2 files changed, 53 insertions(+) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 5821d582c520..493ab33fe771 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -1107,6 +1107,57 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > } > EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); > > +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, > + struct cxl_dev_state *cxlds) > +{ > + struct cxl_register_map map; > + int rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, > + cxlds->capabilities); > + /* > + * This call can return -ENODEV if regs not found. This is not an error > + * for Type2 since these regs are not mandatory. If they do exist then > + * mapping them should not fail. If they should exist, it is with driver > + * calling cxl_pci_check_caps where the problem should be found. > + */ > + if (rc == -ENODEV) > + return 0; > + > + if (rc) > + return rc; > + > + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); > +} > + > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) > +{ > + int rc; > + > + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); > + if (rc) > + return rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > + &cxlds->reg_map, cxlds->capabilities); > + if (rc) { > + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); > + return rc; > + } > + > + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) > + return rc; return 0; will make it clear what intent is here. > + > + rc = cxl_map_component_regs(&cxlds->reg_map, > + &cxlds->regs.component, > + BIT(CXL_CM_CAP_CAP_ID_RAS)); > + if (rc) > + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); > + > + return rc; > +} > +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, "CXL");