From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Alejandro Lucero Palau <alucerop@amd.com>
Cc: <alejandro.lucero-palau@amd.com>, <linux-cxl@vger.kernel.org>,
<netdev@vger.kernel.org>, <dan.j.williams@intel.com>,
<martin.habets@xilinx.com>, <edward.cree@amd.com>,
<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
<edumazet@google.com>, <dave.jiang@intel.com>
Subject: Re: [PATCH v8 03/27] cxl: add capabilities field to cxl_dev_state and cxl_port
Date: Fri, 3 Jan 2025 10:47:17 +0000 [thread overview]
Message-ID: <20250103104717.00002554@huawei.com> (raw)
In-Reply-To: <04a40923-d3ca-1b4a-7c05-2eedea707818@amd.com>
On Fri, 3 Jan 2025 07:16:51 +0000
Alejandro Lucero Palau <alucerop@amd.com> wrote:
> On 1/2/25 12:49, Jonathan Cameron wrote:
> >>>> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> >>>> index 19e5d883557a..f656fcd4945f 100644
> >>>> --- a/include/cxl/cxl.h
> >>>> +++ b/include/cxl/cxl.h
> >>>> @@ -12,6 +12,25 @@ enum cxl_resource {
> >>>> CXL_RES_PMEM,
> >>>> };
> >>>>
> >>>> +/* Capabilities as defined for:
> >>>> + *
> >>>> + * Component Registers (Table 8-22 CXL 3.1 specification)
> >>>> + * Device Registers (8.2.8.2.1 CXL 3.1 specification)
> >>>> + *
> >>>> + * and currently being used for kernel CXL support.
> >>>> + */
> >>>> +
> >>>> +enum cxl_dev_cap {
> >>>> + /* capabilities from Component Registers */
> >>>> + CXL_DEV_CAP_RAS,
> >>>> + CXL_DEV_CAP_HDM,
> >>>> + /* capabilities from Device Registers */
> >>>> + CXL_DEV_CAP_DEV_STATUS,
> >>>> + CXL_DEV_CAP_MAILBOX_PRIMARY,
> >>>> + CXL_DEV_CAP_MEMDEV,
> >>>> + CXL_MAX_CAPS = 64
> >>> Why set it to 64? All the bitmaps etc will autosize so
> >>> you just need to ensure you use correct set_bit() and test_bit()
> >>> that are happy dealing with bitmaps of multiple longs.
> >>>
> >> Initially it was set to 32, but DECLARE_BITMAP uses unsigned long, so
> >> for initializing/zeroing the locally allocated bitmap in some functions,
> >> bitmap_clear had to use sizeof for the size, and I was suggested to
> >> define CXL_MAX_CAPS to 64 and use it instead, what seems cleaner.
> > It should never have been using sizeof() once it was a bitmap.
> > Just clear what is actually used and make sure no code assumes
> > any particular length of bitmap. Then you will never have
> > to deal with changing it.
>
>
> The problem I had was to zeroing a locally allocated bitmap for avoiding
> random bits set by the previous use of that memory.
>
> The macros/functions like bitmap_clear or bitmap_zero require a start
> and a number of bits, and I did not find any other way than using sizeof.
CXL_MAX_CAPS is fine, but set it to 5 (automatically by making it last
element in enum), not 64 which is made up value and gains you nothing that
I can see. As you can see in the bitmap_zero implementation:
static __always_inline void bitmap_zero(unsigned long *dst, unsigned int nbits)
{
unsigned int len = bitmap_size(nbits);
if (small_const_nbits(nbits))
*dst = 0;
else
memset(dst, 0, len);
}
If it fits in an unsigned long it will just do *dst = 0
which is what we want, but if the bitmap grows in future it will just
do the right thing.
No need for a magic 64 or anything else.
Jonathan
>
> I was not happy with it, although it was fine for current needs of a
> bitmap not bigger than unsigned long size. But I was told to use the
> CXL_MAX_CAPS as currently implemented for using that for the zeroing.
>
>
> >
> > Then CXL_MAX_CAP just becomes last entry in this enum.
> >
> > The only time this is becomes tricky with bitmaps is if you need
> > to set a bits in a constant bitmap as then you can't use the
> > set/get functions and have to assume something about the length.
> >
> > Don't think that applies here.
> >
> > Jonathan
> >
> >
> >>
> >>>> +};
> >>>> +
> >>>> struct cxl_dev_state *cxl_accel_state_create(struct device *dev);
> >>>>
> >>>> void cxl_set_dvsec(struct cxl_dev_state *cxlds, u16 dvsec);
next prev parent reply other threads:[~2025-01-03 10:47 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-16 16:10 [PATCH v8 00/27] cxl: add type2 device basic support alejandro.lucero-palau
2024-12-16 16:10 ` [PATCH v8 01/27] " alejandro.lucero-palau
2024-12-24 16:35 ` Jonathan Cameron
2024-12-27 6:56 ` Alejandro Lucero Palau
2025-01-07 16:35 ` Alison Schofield
2025-01-07 23:42 ` Dan Williams
2025-01-08 1:33 ` Dan Williams
2025-01-08 14:32 ` Alejandro Lucero Palau
2025-01-14 14:35 ` Alejandro Lucero Palau
2025-01-14 16:40 ` Alejandro Lucero Palau
2025-01-14 22:52 ` Dan Williams
2025-01-15 16:01 ` Alejandro Lucero Palau
2025-01-16 6:16 ` Dan Williams
2025-01-16 10:02 ` Alejandro Lucero Palau
2025-02-05 20:05 ` Dan Williams
2025-02-06 17:37 ` Alejandro Lucero Palau
2025-02-07 1:57 ` Dan Williams
2025-01-24 13:38 ` Alejandro Lucero Palau
2025-01-08 14:11 ` Alejandro Lucero Palau
2025-01-14 23:48 ` Dan Williams
2024-12-16 16:10 ` [PATCH v8 02/27] sfc: add cxl support using new CXL API alejandro.lucero-palau
2024-12-24 17:04 ` Jonathan Cameron
2024-12-27 7:00 ` Alejandro Lucero Palau
2025-01-08 1:56 ` Dan Williams
2025-01-08 14:53 ` Alejandro Lucero Palau
2025-01-14 23:59 ` Dan Williams
2024-12-16 16:10 ` [PATCH v8 03/27] cxl: add capabilities field to cxl_dev_state and cxl_port alejandro.lucero-palau
2024-12-24 17:08 ` Jonathan Cameron
2024-12-27 7:07 ` Alejandro Lucero Palau
2025-01-02 12:49 ` Jonathan Cameron
2025-01-03 7:16 ` Alejandro Lucero Palau
2025-01-03 10:47 ` Jonathan Cameron [this message]
2024-12-16 16:10 ` [PATCH v8 04/27] cxl/pci: add check for validating capabilities alejandro.lucero-palau
2024-12-24 17:15 ` Jonathan Cameron
2024-12-27 7:47 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 05/27] cxl: move pci generic code alejandro.lucero-palau
2024-12-24 17:19 ` Jonathan Cameron
2024-12-27 7:53 ` Alejandro Lucero Palau
2025-01-08 5:19 ` Dan Williams
2025-01-08 14:39 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 06/27] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2024-12-24 17:22 ` Jonathan Cameron
2024-12-27 8:04 ` Alejandro Lucero Palau
2024-12-30 9:01 ` Alejandro Lucero Palau
2025-01-06 10:41 ` Dan Carpenter
2025-01-06 15:19 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 07/27] sfc: use cxl api for regs setup and checking alejandro.lucero-palau
2024-12-24 17:23 ` Jonathan Cameron
2024-12-27 8:05 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 08/27] cxl: add functions for resource request/release by a driver alejandro.lucero-palau
2024-12-24 17:25 ` Jonathan Cameron
2024-12-27 8:06 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 09/27] sfc: request cxl ram resource alejandro.lucero-palau
2024-12-24 17:27 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 10/27] resource: harden resource_contains alejandro.lucero-palau
2024-12-24 17:27 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 11/27] cxl: add function for setting media ready by a driver alejandro.lucero-palau
2024-12-24 17:29 ` Jonathan Cameron
2024-12-27 8:08 ` Alejandro Lucero Palau
2025-01-02 12:45 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 12/27] sfc: set cxl media ready alejandro.lucero-palau
2024-12-16 16:10 ` [PATCH v8 13/27] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2024-12-24 17:32 ` Jonathan Cameron
2024-12-27 8:28 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 14/27] sfc: create type2 cxl memdev alejandro.lucero-palau
2024-12-24 17:33 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 15/27] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2024-12-24 17:42 ` Jonathan Cameron
2024-12-27 10:05 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 16/27] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2024-12-18 11:17 ` Edward Cree
2024-12-24 17:43 ` Jonathan Cameron
2024-12-25 20:21 ` kernel test robot
2024-12-16 16:10 ` [PATCH v8 17/27] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2024-12-24 17:53 ` Jonathan Cameron
2024-12-27 10:23 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 18/27] sfc: get endpoint decoder alejandro.lucero-palau
2024-12-17 10:42 ` Simon Horman
2024-12-18 8:22 ` Alejandro Lucero Palau
2025-01-07 11:34 ` Simon Horman
2024-12-16 16:10 ` [PATCH v8 19/27] cxl: make region type based on endpoint type alejandro.lucero-palau
2024-12-24 17:54 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 20/27] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2024-12-24 17:56 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 21/27] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2024-12-24 17:56 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 22/27] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2024-12-24 18:01 ` Jonathan Cameron
2024-12-27 10:27 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 23/27] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2024-12-24 18:04 ` Jonathan Cameron
2024-12-27 8:46 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 24/27] sfc: create cxl region alejandro.lucero-palau
2024-12-24 18:05 ` Jonathan Cameron
2024-12-25 23:58 ` kernel test robot
2024-12-16 16:10 ` [PATCH v8 25/27] cxl: add function for obtaining region range alejandro.lucero-palau
2024-12-24 18:07 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 26/27] sfc: update MCDI protocol headers alejandro.lucero-palau
2024-12-16 16:10 ` [PATCH v8 27/27] sfc: support pio mapping based on cxl alejandro.lucero-palau
2024-12-17 10:47 ` Simon Horman
2024-12-18 8:32 ` Alejandro Lucero Palau
2024-12-30 12:16 ` Alejandro Lucero Palau
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