From: Maxime Chevallier <maxime.chevallier@bootlin.com>
To: Vladimir Oltean <vladimir.oltean@nxp.com>
Cc: netdev@vger.kernel.org, Jose Abreu <Jose.Abreu@synopsys.com>,
Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
"Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>,
Voon Weifeng <weifeng.voon@intel.com>,
Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH net 1/2] net: pcs: xpcs: fix DW_VR_MII_DIG_CTRL1_2G5_EN bit being set for 1G SGMII w/o inband
Date: Wed, 15 Jan 2025 15:37:50 +0100 [thread overview]
Message-ID: <20250115153750.1aac00b7@fedora.home> (raw)
In-Reply-To: <20250114164721.2879380-1-vladimir.oltean@nxp.com>
Hello Vlad,
On Tue, 14 Jan 2025 18:47:20 +0200
Vladimir Oltean <vladimir.oltean@nxp.com> wrote:
> On a port with SGMII fixed-link at SPEED_1000, DW_VR_MII_DIG_CTRL1 gets
> set to 0x2404. This is incorrect, because bit 2 (DW_VR_MII_DIG_CTRL1_2G5_EN)
> is set.
>
> It comes from the previous write to DW_VR_MII_AN_CTRL, because the "val"
> variable is reused and is dirty. Actually, its value is 0x4, aka
> FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, DW_VR_MII_PCS_MODE_C37_SGMII).
>
> Resolve the issue by clearing "val" to 0 when writing to a new register.
> After the fix, the register value is 0x2400.
>
> Prior to the blamed commit, when the read-modify-write was open-coded,
> the code saved the content of the DW_VR_MII_DIG_CTRL1 register in the
> "ret" variable.
>
> Fixes: ce8d6081fcf4 ("net: pcs: xpcs: add _modify() accessors")
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Thanks,
Maxime
next prev parent reply other threads:[~2025-01-15 14:38 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-14 16:47 [PATCH net 1/2] net: pcs: xpcs: fix DW_VR_MII_DIG_CTRL1_2G5_EN bit being set for 1G SGMII w/o inband Vladimir Oltean
2025-01-14 16:47 ` [PATCH net 2/2] net: pcs: xpcs: actively unset DW_VR_MII_DIG_CTRL1_2G5_EN for 1G SGMII Vladimir Oltean
2025-01-15 14:39 ` Maxime Chevallier
2025-01-15 14:44 ` Russell King (Oracle)
2025-01-15 14:51 ` Vladimir Oltean
2025-01-15 15:41 ` Russell King (Oracle)
2025-01-15 14:37 ` Maxime Chevallier [this message]
2025-01-15 14:43 ` [PATCH net 1/2] net: pcs: xpcs: fix DW_VR_MII_DIG_CTRL1_2G5_EN bit being set for 1G SGMII w/o inband Russell King (Oracle)
2025-01-15 21:30 ` patchwork-bot+netdevbpf
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