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From: Furong Xu <0x1207@gmail.com>
To: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>,
	Jose Abreu <joabreu@synopsys.com>,
	Andrew Lunn <andrew+netdev@lunn.ch>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH net 1/2] net: stmmac: Limit FIFO size by hardware feature value
Date: Thu, 16 Jan 2025 11:04:36 +0800	[thread overview]
Message-ID: <20250116105011.00003206@gmail.com> (raw)
In-Reply-To: <20250116020853.2835521-1-hayashi.kunihiko@socionext.com>

On Thu, 16 Jan 2025 11:08:52 +0900, Kunihiko Hayashi <hayashi.kunihiko@socionext.com> wrote:

> Tx/Rx FIFO size is specified by the parameter "{tx,rx}-fifo-depth" from
> the platform layer.
> 
> However, these values are constrained by upper limits determined by the
> capabilities of each hardware feature. There is a risk that the upper
> bits will be truncated due to the calculation, so it's appropriate to
> limit them to the upper limit values.
> 

Patch is fine, but the Fixes: tag is required here.

And if you like to group this patch and the another patch into one series,
it is better to add a cover letter.

> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
>  drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 7bf275f127c9..2d69c3c4b329 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -2375,9 +2375,9 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
>  	u32 chan = 0;
>  	u8 qmode = 0;
>  
> -	if (rxfifosz == 0)
> +	if (!rxfifosz || rxfifosz > priv->dma_cap.rx_fifo_size)
>  		rxfifosz = priv->dma_cap.rx_fifo_size;
> -	if (txfifosz == 0)
> +	if (!txfifosz || txfifosz > priv->dma_cap.tx_fifo_size)
>  		txfifosz = priv->dma_cap.tx_fifo_size;
>  
>  	/* Split up the shared Tx/Rx FIFO memory on DW QoS Eth and DW XGMAC */
> @@ -2851,9 +2851,9 @@ static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
>  	int rxfifosz = priv->plat->rx_fifo_size;
>  	int txfifosz = priv->plat->tx_fifo_size;
>  
> -	if (rxfifosz == 0)
> +	if (!rxfifosz || rxfifosz > priv->dma_cap.rx_fifo_size)
>  		rxfifosz = priv->dma_cap.rx_fifo_size;
> -	if (txfifosz == 0)
> +	if (!txfifosz || txfifosz > priv->dma_cap.tx_fifo_size)
>  		txfifosz = priv->dma_cap.tx_fifo_size;
>  
>  	/* Adjust for real per queue fifo size */

  parent reply	other threads:[~2025-01-16  3:06 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-16  2:08 [PATCH net 1/2] net: stmmac: Limit FIFO size by hardware feature value Kunihiko Hayashi
2025-01-16  2:08 ` [PATCH net 2/2] net: stmmac: Limit the number of MTL queues to maximum value Kunihiko Hayashi
2025-01-16  3:28   ` Furong Xu
2025-01-16 10:02     ` Kunihiko Hayashi
2025-01-16  3:04 ` Furong Xu [this message]
2025-01-16 10:02   ` [PATCH net 1/2] net: stmmac: Limit FIFO size by hardware feature value Kunihiko Hayashi
2025-01-16 20:16 ` Andrew Lunn
2025-01-20  5:20   ` Kunihiko Hayashi
2025-01-20 16:29     ` Andrew Lunn
2025-01-21  0:17       ` Kunihiko Hayashi

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