From: <alucerop@amd.com>
To: <linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>,
<dan.j.williams@intel.com>, <edward.cree@amd.com>,
<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
<edumazet@google.com>, <dave.jiang@intel.com>
Cc: Alejandro Lucero <alucerop@amd.com>
Subject: [PATCH v10 10/26] cxl: modify dpa setup process for supporting type2
Date: Wed, 5 Feb 2025 15:19:34 +0000 [thread overview]
Message-ID: <20250205151950.25268-11-alucerop@amd.com> (raw)
In-Reply-To: <20250205151950.25268-1-alucerop@amd.com>
From: Alejandro Lucero <alucerop@amd.com>
Accel drivers allocate a memdev state struct but only able to use it
through the accel driver API for initialization and setup.
Modify current dpa setup by drivers for realying on memdev state instead
of dev state.
Allow accel drivers to use dpa structs and functions.
Signed-off-by: Alejandro Lucero <alucerop@amd.com>
---
drivers/cxl/core/hdm.c | 4 +++-
drivers/cxl/cxl.h | 6 +-----
drivers/cxl/cxlmem.h | 14 --------------
drivers/cxl/pci.c | 2 +-
include/cxl/cxl.h | 19 +++++++++++++++++++
5 files changed, 24 insertions(+), 21 deletions(-)
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index d705dec1471e..af025da81fa2 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -467,8 +467,10 @@ static const char *cxl_mode_name(enum cxl_partition_mode mode)
}
/* if this fails the caller must destroy @cxlds, there is no recovery */
-int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
+int cxl_dpa_setup(struct cxl_memdev_state *cxlmds,
+ const struct cxl_dpa_info *info)
{
+ struct cxl_dev_state *cxlds = &cxlmds->cxlds;
struct device *dev = cxlds->dev;
guard(rwsem_write)(&cxl_dpa_rwsem);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 27d1dc48611c..3faba6c9dbfb 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -11,6 +11,7 @@
#include <linux/log2.h>
#include <linux/node.h>
#include <linux/io.h>
+#include <cxl/cxl.h>
extern const struct nvdimm_security_ops *cxl_security_ops;
@@ -478,11 +479,6 @@ struct cxl_region_params {
int nr_targets;
};
-enum cxl_partition_mode {
- CXL_PARTMODE_RAM,
- CXL_PARTMODE_PMEM,
-};
-
/*
* Indicate whether this region has been assembled by autodetection or
* userspace assembly. Prevent endpoint decoders outside of automatic
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index ab8c23009b9d..a5994061780c 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -98,19 +98,6 @@ int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled,
resource_size_t base, resource_size_t len,
resource_size_t skipped);
-#define CXL_NR_PARTITIONS_MAX 2
-
-struct cxl_dpa_info {
- u64 size;
- struct cxl_dpa_part_info {
- struct range range;
- enum cxl_partition_mode mode;
- } part[CXL_NR_PARTITIONS_MAX];
- int nr_partitions;
-};
-
-int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info);
-
static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
struct cxl_memdev *cxlmd)
{
@@ -841,7 +828,6 @@ int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox,
struct cxl_mbox_cmd *cmd);
int cxl_dev_state_identify(struct cxl_memdev_state *mds);
int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
-int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
u16 dvsec, enum cxl_devtype type);
void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 5fe5f7ff4fb1..bcfa3d86c37b 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -955,7 +955,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (rc)
return rc;
- rc = cxl_dpa_setup(cxlds, &range_info);
+ rc = cxl_dpa_setup(mds, &range_info);
if (rc)
return rc;
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index 1b2224ee1d5b..ec56a82966c0 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -49,6 +49,23 @@ struct mds_info {
u64 persistent_only_bytes;
};
+enum cxl_partition_mode {
+ CXL_PARTMODE_NONE,
+ CXL_PARTMODE_RAM,
+ CXL_PARTMODE_PMEM,
+};
+
+#define CXL_NR_PARTITIONS_MAX 2
+
+struct cxl_dpa_info {
+ u64 size;
+ struct cxl_dpa_part_info {
+ struct range range;
+ enum cxl_partition_mode mode;
+ } part[CXL_NR_PARTITIONS_MAX];
+ int nr_partitions;
+};
+
struct device;
struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
u16 dvsec, enum cxl_devtype type);
@@ -59,4 +76,6 @@ int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_memdev_state *cxlm
int cxl_await_media_ready(struct cxl_memdev_state *mds);
void cxl_set_media_ready(struct cxl_memdev_state *mds);
void cxl_dev_state_setup(struct cxl_memdev_state *mds, struct mds_info *info);
+int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
+int cxl_dpa_setup(struct cxl_memdev_state *cxlmds, const struct cxl_dpa_info *info);
#endif
--
2.17.1
next prev parent reply other threads:[~2025-02-05 15:20 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-05 15:19 [PATCH v10 00/26] cxl: add type2 device basic support alucerop
2025-02-05 15:19 ` [PATCH v10 01/26] cxl: make memdev creation type agnostic alucerop
2025-02-06 19:37 ` Dan Williams
2025-02-17 12:32 ` Alejandro Lucero Palau
2025-02-19 2:29 ` Dan Williams
2025-02-20 18:17 ` Alejandro Lucero Palau
2025-02-17 13:05 ` Alejandro Lucero Palau
2025-02-13 3:57 ` Alison Schofield
2025-02-17 12:49 ` Alejandro Lucero Palau
2025-02-17 13:06 ` Alejandro Lucero Palau
2025-02-14 17:02 ` Jonathan Cameron
2025-02-17 13:08 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 02/26] sfc: add basic cxl initialization alucerop
2025-02-06 1:37 ` Edward Cree
2025-02-07 12:48 ` Simon Horman
2025-02-17 13:10 ` Alejandro Lucero Palau
2025-02-07 13:03 ` Simon Horman
2025-02-17 13:11 ` Alejandro Lucero Palau
2025-02-18 13:32 ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 03/26] cxl: move pci generic code alucerop
2025-02-05 21:33 ` Ira Weiny
2025-02-06 17:49 ` Alejandro Lucero Palau
2025-02-14 17:11 ` Jonathan Cameron
2025-02-17 13:13 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 04/26] cxl: move register/capability check to driver alucerop
2025-02-07 12:52 ` Simon Horman
2025-02-17 13:17 ` Alejandro Lucero Palau
2025-02-14 17:21 ` Jonathan Cameron
2025-02-17 13:18 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 05/26] cxl: add function for type2 cxl regs setup alucerop
2025-02-05 21:35 ` Ira Weiny
2025-02-06 17:50 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 06/26] sfc: use cxl api for regs setup and checking alucerop
2025-02-05 21:31 ` Ira Weiny
2025-02-06 17:47 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 07/26] cxl: add support for setting media ready by an accel driver alucerop
2025-02-05 21:42 ` Ira Weiny
2025-02-06 17:58 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 08/26] sfc: set cxl media ready alucerop
2025-02-05 15:19 ` [PATCH v10 09/26] cxl: support device identification without mailbox alucerop
2025-02-05 21:45 ` Ira Weiny
2025-02-06 18:10 ` Alejandro Lucero Palau
2025-02-06 19:23 ` Ira Weiny
2025-02-17 13:41 ` Alejandro Lucero Palau
2025-02-05 15:19 ` alucerop [this message]
2025-02-05 15:19 ` [PATCH v10 11/26] sfc: initialize dpa resources alucerop
2025-02-05 15:19 ` [PATCH v10 12/26] cxl: prepare memdev creation for type2 alucerop
2025-02-05 15:19 ` [PATCH v10 13/26] sfc: create type2 cxl memdev alucerop
2025-02-05 15:19 ` [PATCH v10 14/26] cxl: define a driver interface for HPA free space enumeration alucerop
2025-02-07 12:55 ` Simon Horman
2025-02-17 13:44 ` Alejandro Lucero Palau
2025-02-13 4:08 ` Alison Schofield
2025-02-17 13:49 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 15/26] sfc: obtain root decoder with enough HPA free space alucerop
2025-02-05 22:47 ` Ira Weiny
2025-02-17 13:54 ` Alejandro Lucero Palau
2025-02-18 0:03 ` Ira Weiny
2025-02-05 15:19 ` [PATCH v10 16/26] cxl: define a driver interface for DPA allocation alucerop
2025-02-06 19:11 ` kernel test robot
2025-02-07 13:46 ` Simon Horman
2025-02-17 14:08 ` Alejandro Lucero Palau
2025-02-18 13:34 ` Simon Horman
2025-02-18 14:09 ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 17/26] sfc: get endpoint decoder alucerop
2025-02-05 15:19 ` [PATCH v10 18/26] cxl: make region type based on endpoint type alucerop
2025-02-05 15:19 ` [PATCH v10 19/26] cxl/region: factor out interleave ways setup alucerop
2025-02-05 15:19 ` [PATCH v10 20/26] cxl/region: factor out interleave granularity setup alucerop
2025-02-05 15:19 ` [PATCH v10 21/26] cxl: allow region creation by type2 drivers alucerop
2025-02-06 20:06 ` kernel test robot
2025-02-07 13:23 ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 22/26] cxl: add region flag for precluding a device memory to be used for dax alucerop
2025-02-05 15:19 ` [PATCH v10 23/26] sfc: create cxl region alucerop
2025-02-05 15:19 ` [PATCH v10 24/26] cxl: add function for obtaining region range alucerop
2025-02-05 15:19 ` [PATCH v10 25/26] sfc: update MCDI protocol headers alucerop
2025-02-05 15:19 ` [PATCH v10 26/26] sfc: support pio mapping based on cxl alucerop
2025-02-13 1:51 ` [PATCH v10 00/26] cxl: add type2 device basic support Alison Schofield
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