From: <alucerop@amd.com>
To: <linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>,
<dan.j.williams@intel.com>, <edward.cree@amd.com>,
<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
<edumazet@google.com>, <dave.jiang@intel.com>
Cc: Alejandro Lucero <alucerop@amd.com>
Subject: [PATCH v10 12/26] cxl: prepare memdev creation for type2
Date: Wed, 5 Feb 2025 15:19:36 +0000 [thread overview]
Message-ID: <20250205151950.25268-13-alucerop@amd.com> (raw)
In-Reply-To: <20250205151950.25268-1-alucerop@amd.com>
From: Alejandro Lucero <alucerop@amd.com>
Current cxl core is relying on a CXL_DEVTYPE_CLASSMEM type device when
creating a memdev leading to problems when obtaining cxl_memdev_state
references from a CXL_DEVTYPE_DEVMEM type.
Modify check for obtaining cxl_memdev_state adding CXL_DEVTYPE_DEVMEM
support.
Make devm_cxl_add_memdev accesible from a accel driver.
Signed-off-by: Alejandro Lucero <alucerop@amd.com>
---
drivers/cxl/core/memdev.c | 17 ++++++++++++++---
drivers/cxl/cxlmem.h | 5 ++---
drivers/cxl/pci.c | 2 +-
include/cxl/cxl.h | 2 ++
4 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
index 7113a51b3a93..9a414980b550 100644
--- a/drivers/cxl/core/memdev.c
+++ b/drivers/cxl/core/memdev.c
@@ -562,9 +562,16 @@ static const struct device_type cxl_memdev_type = {
.groups = cxl_memdev_attribute_groups,
};
+static const struct device_type cxl_accel_memdev_type = {
+ .name = "cxl_accel_memdev",
+ .release = cxl_memdev_release,
+ .devnode = cxl_memdev_devnode,
+};
+
bool is_cxl_memdev(const struct device *dev)
{
- return dev->type == &cxl_memdev_type;
+ return (dev->type == &cxl_memdev_type ||
+ dev->type == &cxl_accel_memdev_type);
}
EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, "CXL");
@@ -691,7 +698,10 @@ static struct cxl_memdev *cxl_memdev_alloc(struct cxl_dev_state *cxlds,
dev->parent = cxlds->dev;
dev->bus = &cxl_bus_type;
dev->devt = MKDEV(cxl_mem_major, cxlmd->id);
- dev->type = &cxl_memdev_type;
+ if (cxlds->type == CXL_DEVTYPE_DEVMEM)
+ dev->type = &cxl_accel_memdev_type;
+ else
+ dev->type = &cxl_memdev_type;
device_set_pm_not_required(dev);
INIT_WORK(&cxlmd->detach_work, detach_memdev);
@@ -1069,8 +1079,9 @@ static const struct file_operations cxl_memdev_fops = {
};
struct cxl_memdev *devm_cxl_add_memdev(struct device *host,
- struct cxl_dev_state *cxlds)
+ struct cxl_memdev_state *cxlmds)
{
+ struct cxl_dev_state *cxlds = &cxlmds->cxlds;
struct cxl_memdev *cxlmd;
struct device *dev;
struct cdev *cdev;
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index a5994061780c..760f7e16a6a4 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -88,8 +88,6 @@ static inline bool is_cxl_endpoint(struct cxl_port *port)
return is_cxl_memdev(port->uport_dev);
}
-struct cxl_memdev *devm_cxl_add_memdev(struct device *host,
- struct cxl_dev_state *cxlds);
int devm_cxl_sanitize_setup_notifier(struct device *host,
struct cxl_memdev *cxlmd);
struct cxl_memdev_state;
@@ -514,7 +512,8 @@ struct cxl_memdev_state {
static inline struct cxl_memdev_state *
to_cxl_memdev_state(struct cxl_dev_state *cxlds)
{
- if (cxlds->type != CXL_DEVTYPE_CLASSMEM)
+ if (cxlds->type != CXL_DEVTYPE_CLASSMEM &&
+ cxlds->type != CXL_DEVTYPE_DEVMEM)
return NULL;
return container_of(cxlds, struct cxl_memdev_state, cxlds);
}
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index bcfa3d86c37b..485e60f60288 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -959,7 +959,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (rc)
return rc;
- cxlmd = devm_cxl_add_memdev(&pdev->dev, cxlds);
+ cxlmd = devm_cxl_add_memdev(&pdev->dev, mds);
if (IS_ERR(cxlmd))
return PTR_ERR(cxlmd);
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index ec56a82966c0..592aa5e75bc2 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -78,4 +78,6 @@ void cxl_set_media_ready(struct cxl_memdev_state *mds);
void cxl_dev_state_setup(struct cxl_memdev_state *mds, struct mds_info *info);
int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
int cxl_dpa_setup(struct cxl_memdev_state *cxlmds, const struct cxl_dpa_info *info);
+struct cxl_memdev *devm_cxl_add_memdev(struct device *host,
+ struct cxl_memdev_state *cxlmds);
#endif
--
2.17.1
next prev parent reply other threads:[~2025-02-05 15:20 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-05 15:19 [PATCH v10 00/26] cxl: add type2 device basic support alucerop
2025-02-05 15:19 ` [PATCH v10 01/26] cxl: make memdev creation type agnostic alucerop
2025-02-06 19:37 ` Dan Williams
2025-02-17 12:32 ` Alejandro Lucero Palau
2025-02-19 2:29 ` Dan Williams
2025-02-20 18:17 ` Alejandro Lucero Palau
2025-02-17 13:05 ` Alejandro Lucero Palau
2025-02-13 3:57 ` Alison Schofield
2025-02-17 12:49 ` Alejandro Lucero Palau
2025-02-17 13:06 ` Alejandro Lucero Palau
2025-02-14 17:02 ` Jonathan Cameron
2025-02-17 13:08 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 02/26] sfc: add basic cxl initialization alucerop
2025-02-06 1:37 ` Edward Cree
2025-02-07 12:48 ` Simon Horman
2025-02-17 13:10 ` Alejandro Lucero Palau
2025-02-07 13:03 ` Simon Horman
2025-02-17 13:11 ` Alejandro Lucero Palau
2025-02-18 13:32 ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 03/26] cxl: move pci generic code alucerop
2025-02-05 21:33 ` Ira Weiny
2025-02-06 17:49 ` Alejandro Lucero Palau
2025-02-14 17:11 ` Jonathan Cameron
2025-02-17 13:13 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 04/26] cxl: move register/capability check to driver alucerop
2025-02-07 12:52 ` Simon Horman
2025-02-17 13:17 ` Alejandro Lucero Palau
2025-02-14 17:21 ` Jonathan Cameron
2025-02-17 13:18 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 05/26] cxl: add function for type2 cxl regs setup alucerop
2025-02-05 21:35 ` Ira Weiny
2025-02-06 17:50 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 06/26] sfc: use cxl api for regs setup and checking alucerop
2025-02-05 21:31 ` Ira Weiny
2025-02-06 17:47 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 07/26] cxl: add support for setting media ready by an accel driver alucerop
2025-02-05 21:42 ` Ira Weiny
2025-02-06 17:58 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 08/26] sfc: set cxl media ready alucerop
2025-02-05 15:19 ` [PATCH v10 09/26] cxl: support device identification without mailbox alucerop
2025-02-05 21:45 ` Ira Weiny
2025-02-06 18:10 ` Alejandro Lucero Palau
2025-02-06 19:23 ` Ira Weiny
2025-02-17 13:41 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 10/26] cxl: modify dpa setup process for supporting type2 alucerop
2025-02-05 15:19 ` [PATCH v10 11/26] sfc: initialize dpa resources alucerop
2025-02-05 15:19 ` alucerop [this message]
2025-02-05 15:19 ` [PATCH v10 13/26] sfc: create type2 cxl memdev alucerop
2025-02-05 15:19 ` [PATCH v10 14/26] cxl: define a driver interface for HPA free space enumeration alucerop
2025-02-07 12:55 ` Simon Horman
2025-02-17 13:44 ` Alejandro Lucero Palau
2025-02-13 4:08 ` Alison Schofield
2025-02-17 13:49 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 15/26] sfc: obtain root decoder with enough HPA free space alucerop
2025-02-05 22:47 ` Ira Weiny
2025-02-17 13:54 ` Alejandro Lucero Palau
2025-02-18 0:03 ` Ira Weiny
2025-02-05 15:19 ` [PATCH v10 16/26] cxl: define a driver interface for DPA allocation alucerop
2025-02-06 19:11 ` kernel test robot
2025-02-07 13:46 ` Simon Horman
2025-02-17 14:08 ` Alejandro Lucero Palau
2025-02-18 13:34 ` Simon Horman
2025-02-18 14:09 ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 17/26] sfc: get endpoint decoder alucerop
2025-02-05 15:19 ` [PATCH v10 18/26] cxl: make region type based on endpoint type alucerop
2025-02-05 15:19 ` [PATCH v10 19/26] cxl/region: factor out interleave ways setup alucerop
2025-02-05 15:19 ` [PATCH v10 20/26] cxl/region: factor out interleave granularity setup alucerop
2025-02-05 15:19 ` [PATCH v10 21/26] cxl: allow region creation by type2 drivers alucerop
2025-02-06 20:06 ` kernel test robot
2025-02-07 13:23 ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 22/26] cxl: add region flag for precluding a device memory to be used for dax alucerop
2025-02-05 15:19 ` [PATCH v10 23/26] sfc: create cxl region alucerop
2025-02-05 15:19 ` [PATCH v10 24/26] cxl: add function for obtaining region range alucerop
2025-02-05 15:19 ` [PATCH v10 25/26] sfc: update MCDI protocol headers alucerop
2025-02-05 15:19 ` [PATCH v10 26/26] sfc: support pio mapping based on cxl alucerop
2025-02-13 1:51 ` [PATCH v10 00/26] cxl: add type2 device basic support Alison Schofield
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