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From: <alucerop@amd.com>
To: <linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>,
	<dan.j.williams@intel.com>, <edward.cree@amd.com>,
	<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
	<edumazet@google.com>, <dave.jiang@intel.com>
Cc: Alejandro Lucero <alucerop@amd.com>
Subject: [PATCH v10 07/26] cxl: add support for setting media ready by an accel driver
Date: Wed, 5 Feb 2025 15:19:31 +0000	[thread overview]
Message-ID: <20250205151950.25268-8-alucerop@amd.com> (raw)
In-Reply-To: <20250205151950.25268-1-alucerop@amd.com>

From: Alejandro Lucero <alucerop@amd.com>

A Type-2 driver needs to set or initialize the device media
availability.

Modify cxl_await_media_ready for the argument being cxl_memdev_state
available from accel drivers, allowing the media device initialization
as currently supported for Type3.

A Type-2 driver may be required to set the memory availability explicitly,
for example because there is not a mailbox for doing so through a specific
command.

Add a function to the exported CXL API for accelerator drivers having this
possibility.

Signed-off-by: Alejandro Lucero <alucerop@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/cxl/core/pci.c | 11 ++++++++++-
 drivers/cxl/cxlmem.h   |  1 -
 drivers/cxl/pci.c      |  3 ++-
 include/cxl/cxl.h      |  2 ++
 4 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 08705c39721d..4461cababf6a 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -177,8 +177,9 @@ static int cxl_dvsec_mem_range_active(struct cxl_dev_state *cxlds, int id)
  * Wait up to @media_ready_timeout for the device to report memory
  * active.
  */
-int cxl_await_media_ready(struct cxl_dev_state *cxlds)
+int cxl_await_media_ready(struct cxl_memdev_state *cxlmds)
 {
+	struct cxl_dev_state *cxlds = &cxlmds->cxlds;
 	struct pci_dev *pdev = to_pci_dev(cxlds->dev);
 	int d = cxlds->cxl_dvsec;
 	int rc, i, hdm_count;
@@ -211,6 +212,14 @@ int cxl_await_media_ready(struct cxl_dev_state *cxlds)
 }
 EXPORT_SYMBOL_NS_GPL(cxl_await_media_ready, "CXL");
 
+void cxl_set_media_ready(struct cxl_memdev_state *cxlmds)
+{
+	struct cxl_dev_state *cxlds = &cxlmds->cxlds;
+
+	cxlds->media_ready = true;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_set_media_ready, "CXL");
+
 static int cxl_set_mem_enable(struct cxl_dev_state *cxlds, u16 val)
 {
 	struct pci_dev *pdev = to_pci_dev(cxlds->dev);
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 62a459078ec3..ab8c23009b9d 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -840,7 +840,6 @@ enum {
 int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox,
 			  struct cxl_mbox_cmd *cmd);
 int cxl_dev_state_identify(struct cxl_memdev_state *mds);
-int cxl_await_media_ready(struct cxl_dev_state *cxlds);
 int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
 int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index cf0991c423d1..5fe5f7ff4fb1 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -12,6 +12,7 @@
 #include <linux/aer.h>
 #include <linux/io.h>
 #include <cxl/mailbox.h>
+#include <cxl/cxl.h>
 #include "cxlmem.h"
 #include "cxlpci.h"
 #include "cxl.h"
@@ -922,7 +923,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	if (rc)
 		return rc;
 
-	rc = cxl_await_media_ready(cxlds);
+	rc = cxl_await_media_ready(mds);
 	if (rc == 0)
 		cxlds->media_ready = true;
 	else
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index 17bf86993a41..955e58103df6 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -46,4 +46,6 @@ struct pci_dev;
 struct cxl_dev_state;
 int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_memdev_state *cxlmds,
 			     unsigned long *caps);
+int cxl_await_media_ready(struct cxl_memdev_state *mds);
+void cxl_set_media_ready(struct cxl_memdev_state *mds);
 #endif
-- 
2.17.1


  parent reply	other threads:[~2025-02-05 15:20 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-05 15:19 [PATCH v10 00/26] cxl: add type2 device basic support alucerop
2025-02-05 15:19 ` [PATCH v10 01/26] cxl: make memdev creation type agnostic alucerop
2025-02-06 19:37   ` Dan Williams
2025-02-17 12:32     ` Alejandro Lucero Palau
2025-02-19  2:29       ` Dan Williams
2025-02-20 18:17         ` Alejandro Lucero Palau
2025-02-17 13:05     ` Alejandro Lucero Palau
2025-02-13  3:57   ` Alison Schofield
2025-02-17 12:49     ` Alejandro Lucero Palau
2025-02-17 13:06     ` Alejandro Lucero Palau
2025-02-14 17:02   ` Jonathan Cameron
2025-02-17 13:08     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 02/26] sfc: add basic cxl initialization alucerop
2025-02-06  1:37   ` Edward Cree
2025-02-07 12:48   ` Simon Horman
2025-02-17 13:10     ` Alejandro Lucero Palau
2025-02-07 13:03   ` Simon Horman
2025-02-17 13:11     ` Alejandro Lucero Palau
2025-02-18 13:32       ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 03/26] cxl: move pci generic code alucerop
2025-02-05 21:33   ` Ira Weiny
2025-02-06 17:49     ` Alejandro Lucero Palau
2025-02-14 17:11       ` Jonathan Cameron
2025-02-17 13:13         ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 04/26] cxl: move register/capability check to driver alucerop
2025-02-07 12:52   ` Simon Horman
2025-02-17 13:17     ` Alejandro Lucero Palau
2025-02-14 17:21   ` Jonathan Cameron
2025-02-17 13:18     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 05/26] cxl: add function for type2 cxl regs setup alucerop
2025-02-05 21:35   ` Ira Weiny
2025-02-06 17:50     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 06/26] sfc: use cxl api for regs setup and checking alucerop
2025-02-05 21:31   ` Ira Weiny
2025-02-06 17:47     ` Alejandro Lucero Palau
2025-02-05 15:19 ` alucerop [this message]
2025-02-05 21:42   ` [PATCH v10 07/26] cxl: add support for setting media ready by an accel driver Ira Weiny
2025-02-06 17:58     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 08/26] sfc: set cxl media ready alucerop
2025-02-05 15:19 ` [PATCH v10 09/26] cxl: support device identification without mailbox alucerop
2025-02-05 21:45   ` Ira Weiny
2025-02-06 18:10     ` Alejandro Lucero Palau
2025-02-06 19:23       ` Ira Weiny
2025-02-17 13:41         ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 10/26] cxl: modify dpa setup process for supporting type2 alucerop
2025-02-05 15:19 ` [PATCH v10 11/26] sfc: initialize dpa resources alucerop
2025-02-05 15:19 ` [PATCH v10 12/26] cxl: prepare memdev creation for type2 alucerop
2025-02-05 15:19 ` [PATCH v10 13/26] sfc: create type2 cxl memdev alucerop
2025-02-05 15:19 ` [PATCH v10 14/26] cxl: define a driver interface for HPA free space enumeration alucerop
2025-02-07 12:55   ` Simon Horman
2025-02-17 13:44     ` Alejandro Lucero Palau
2025-02-13  4:08   ` Alison Schofield
2025-02-17 13:49     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 15/26] sfc: obtain root decoder with enough HPA free space alucerop
2025-02-05 22:47   ` Ira Weiny
2025-02-17 13:54     ` Alejandro Lucero Palau
2025-02-18  0:03       ` Ira Weiny
2025-02-05 15:19 ` [PATCH v10 16/26] cxl: define a driver interface for DPA allocation alucerop
2025-02-06 19:11   ` kernel test robot
2025-02-07 13:46   ` Simon Horman
2025-02-17 14:08     ` Alejandro Lucero Palau
2025-02-18 13:34       ` Simon Horman
2025-02-18 14:09         ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 17/26] sfc: get endpoint decoder alucerop
2025-02-05 15:19 ` [PATCH v10 18/26] cxl: make region type based on endpoint type alucerop
2025-02-05 15:19 ` [PATCH v10 19/26] cxl/region: factor out interleave ways setup alucerop
2025-02-05 15:19 ` [PATCH v10 20/26] cxl/region: factor out interleave granularity setup alucerop
2025-02-05 15:19 ` [PATCH v10 21/26] cxl: allow region creation by type2 drivers alucerop
2025-02-06 20:06   ` kernel test robot
2025-02-07 13:23   ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 22/26] cxl: add region flag for precluding a device memory to be used for dax alucerop
2025-02-05 15:19 ` [PATCH v10 23/26] sfc: create cxl region alucerop
2025-02-05 15:19 ` [PATCH v10 24/26] cxl: add function for obtaining region range alucerop
2025-02-05 15:19 ` [PATCH v10 25/26] sfc: update MCDI protocol headers alucerop
2025-02-05 15:19 ` [PATCH v10 26/26] sfc: support pio mapping based on cxl alucerop
2025-02-13  1:51 ` [PATCH v10 00/26] cxl: add type2 device basic support Alison Schofield

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