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From: kernel test robot <lkp@intel.com>
To: alucerop@amd.com, linux-cxl@vger.kernel.org,
	netdev@vger.kernel.org, dan.j.williams@intel.com,
	edward.cree@amd.com, davem@davemloft.net, kuba@kernel.org,
	pabeni@redhat.com, edumazet@google.com, dave.jiang@intel.com
Cc: oe-kbuild-all@lists.linux.dev, Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v10 16/26] cxl: define a driver interface for DPA allocation
Date: Fri, 7 Feb 2025 03:11:58 +0800	[thread overview]
Message-ID: <202502070213.8GNIAg8A-lkp@intel.com> (raw)
In-Reply-To: <20250205151950.25268-17-alucerop@amd.com>

Hi,

kernel test robot noticed the following build warnings:

[auto build test WARNING on 6cd498f39cf5e1475b567eb67a6fcf1ca3d67d46]

url:    https://github.com/intel-lab-lkp/linux/commits/alucerop-amd-com/cxl-make-memdev-creation-type-agnostic/20250205-233651
base:   6cd498f39cf5e1475b567eb67a6fcf1ca3d67d46
patch link:    https://lore.kernel.org/r/20250205151950.25268-17-alucerop%40amd.com
patch subject: [PATCH v10 16/26] cxl: define a driver interface for DPA allocation
config: i386-buildonly-randconfig-006-20250206 (https://download.01.org/0day-ci/archive/20250207/202502070213.8GNIAg8A-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250207/202502070213.8GNIAg8A-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202502070213.8GNIAg8A-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/cxl/core/hdm.c:743: warning: Function parameter or struct member 'alloc' not described in 'cxl_request_dpa'
>> drivers/cxl/core/hdm.c:743: warning: Excess function parameter 'min' description in 'cxl_request_dpa'


vim +743 drivers/cxl/core/hdm.c

   722	
   723	/**
   724	 * cxl_request_dpa - search and reserve DPA given input constraints
   725	 * @cxlmd: memdev with an endpoint port with available decoders
   726	 * @is_ram: DPA operation mode (ram vs pmem)
   727	 * @min: the minimum amount of capacity the call needs
   728	 *
   729	 * Given that a region needs to allocate from limited HPA capacity it
   730	 * may be the case that a device has more mappable DPA capacity than
   731	 * available HPA. So, the expectation is that @min is a driver known
   732	 * value for how much capacity is needed, and @max is the limit of
   733	 * how much HPA space is available for a new region.
   734	 *
   735	 * Returns a pinned cxl_decoder with at least @min bytes of capacity
   736	 * reserved, or an error pointer. The caller is also expected to own the
   737	 * lifetime of the memdev registration associated with the endpoint to
   738	 * pin the decoder registered as well.
   739	 */
   740	struct cxl_endpoint_decoder *cxl_request_dpa(struct cxl_memdev *cxlmd,
   741						     bool is_ram,
   742						     resource_size_t alloc)
 > 743	{
   744		struct cxl_port *endpoint = cxlmd->endpoint;
   745		struct cxl_endpoint_decoder *cxled;
   746		enum cxl_partition_mode mode;
   747		struct device *cxled_dev;
   748		int rc;
   749	
   750		if (!IS_ALIGNED(alloc, SZ_256M))
   751			return ERR_PTR(-EINVAL);
   752	
   753		down_read(&cxl_dpa_rwsem);
   754		cxled_dev = device_find_child(&endpoint->dev, NULL, find_free_decoder);
   755		up_read(&cxl_dpa_rwsem);
   756	
   757		if (!cxled_dev)
   758			return ERR_PTR(-ENXIO);
   759	
   760		cxled = to_cxl_endpoint_decoder(cxled_dev);
   761	
   762		if (!cxled) {
   763			rc = -ENODEV;
   764			goto err;
   765		}
   766	
   767		if (is_ram)
   768			mode = CXL_PARTMODE_RAM;
   769		else
   770			mode = CXL_PARTMODE_PMEM;
   771	
   772		rc = cxl_dpa_set_part(cxled, mode);
   773		if (rc)
   774			goto err;
   775	
   776		rc = cxl_dpa_alloc(cxled, alloc);
   777		if (rc)
   778			goto err;
   779	
   780		return cxled;
   781	err:
   782		put_device(cxled_dev);
   783		return ERR_PTR(rc);
   784	}
   785	EXPORT_SYMBOL_NS_GPL(cxl_request_dpa, "CXL");
   786	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

  reply	other threads:[~2025-02-06 19:13 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-05 15:19 [PATCH v10 00/26] cxl: add type2 device basic support alucerop
2025-02-05 15:19 ` [PATCH v10 01/26] cxl: make memdev creation type agnostic alucerop
2025-02-06 19:37   ` Dan Williams
2025-02-17 12:32     ` Alejandro Lucero Palau
2025-02-19  2:29       ` Dan Williams
2025-02-20 18:17         ` Alejandro Lucero Palau
2025-02-17 13:05     ` Alejandro Lucero Palau
2025-02-13  3:57   ` Alison Schofield
2025-02-17 12:49     ` Alejandro Lucero Palau
2025-02-17 13:06     ` Alejandro Lucero Palau
2025-02-14 17:02   ` Jonathan Cameron
2025-02-17 13:08     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 02/26] sfc: add basic cxl initialization alucerop
2025-02-06  1:37   ` Edward Cree
2025-02-07 12:48   ` Simon Horman
2025-02-17 13:10     ` Alejandro Lucero Palau
2025-02-07 13:03   ` Simon Horman
2025-02-17 13:11     ` Alejandro Lucero Palau
2025-02-18 13:32       ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 03/26] cxl: move pci generic code alucerop
2025-02-05 21:33   ` Ira Weiny
2025-02-06 17:49     ` Alejandro Lucero Palau
2025-02-14 17:11       ` Jonathan Cameron
2025-02-17 13:13         ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 04/26] cxl: move register/capability check to driver alucerop
2025-02-07 12:52   ` Simon Horman
2025-02-17 13:17     ` Alejandro Lucero Palau
2025-02-14 17:21   ` Jonathan Cameron
2025-02-17 13:18     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 05/26] cxl: add function for type2 cxl regs setup alucerop
2025-02-05 21:35   ` Ira Weiny
2025-02-06 17:50     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 06/26] sfc: use cxl api for regs setup and checking alucerop
2025-02-05 21:31   ` Ira Weiny
2025-02-06 17:47     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 07/26] cxl: add support for setting media ready by an accel driver alucerop
2025-02-05 21:42   ` Ira Weiny
2025-02-06 17:58     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 08/26] sfc: set cxl media ready alucerop
2025-02-05 15:19 ` [PATCH v10 09/26] cxl: support device identification without mailbox alucerop
2025-02-05 21:45   ` Ira Weiny
2025-02-06 18:10     ` Alejandro Lucero Palau
2025-02-06 19:23       ` Ira Weiny
2025-02-17 13:41         ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 10/26] cxl: modify dpa setup process for supporting type2 alucerop
2025-02-05 15:19 ` [PATCH v10 11/26] sfc: initialize dpa resources alucerop
2025-02-05 15:19 ` [PATCH v10 12/26] cxl: prepare memdev creation for type2 alucerop
2025-02-05 15:19 ` [PATCH v10 13/26] sfc: create type2 cxl memdev alucerop
2025-02-05 15:19 ` [PATCH v10 14/26] cxl: define a driver interface for HPA free space enumeration alucerop
2025-02-07 12:55   ` Simon Horman
2025-02-17 13:44     ` Alejandro Lucero Palau
2025-02-13  4:08   ` Alison Schofield
2025-02-17 13:49     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 15/26] sfc: obtain root decoder with enough HPA free space alucerop
2025-02-05 22:47   ` Ira Weiny
2025-02-17 13:54     ` Alejandro Lucero Palau
2025-02-18  0:03       ` Ira Weiny
2025-02-05 15:19 ` [PATCH v10 16/26] cxl: define a driver interface for DPA allocation alucerop
2025-02-06 19:11   ` kernel test robot [this message]
2025-02-07 13:46   ` Simon Horman
2025-02-17 14:08     ` Alejandro Lucero Palau
2025-02-18 13:34       ` Simon Horman
2025-02-18 14:09         ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 17/26] sfc: get endpoint decoder alucerop
2025-02-05 15:19 ` [PATCH v10 18/26] cxl: make region type based on endpoint type alucerop
2025-02-05 15:19 ` [PATCH v10 19/26] cxl/region: factor out interleave ways setup alucerop
2025-02-05 15:19 ` [PATCH v10 20/26] cxl/region: factor out interleave granularity setup alucerop
2025-02-05 15:19 ` [PATCH v10 21/26] cxl: allow region creation by type2 drivers alucerop
2025-02-06 20:06   ` kernel test robot
2025-02-07 13:23   ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 22/26] cxl: add region flag for precluding a device memory to be used for dax alucerop
2025-02-05 15:19 ` [PATCH v10 23/26] sfc: create cxl region alucerop
2025-02-05 15:19 ` [PATCH v10 24/26] cxl: add function for obtaining region range alucerop
2025-02-05 15:19 ` [PATCH v10 25/26] sfc: update MCDI protocol headers alucerop
2025-02-05 15:19 ` [PATCH v10 26/26] sfc: support pio mapping based on cxl alucerop
2025-02-13  1:51 ` [PATCH v10 00/26] cxl: add type2 device basic support Alison Schofield

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