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From: Simon Horman <horms@kernel.org>
To: alucerop@amd.com
Cc: linux-cxl@vger.kernel.org, netdev@vger.kernel.org,
	dan.j.williams@intel.com, edward.cree@amd.com,
	davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com,
	edumazet@google.com, dave.jiang@intel.com
Subject: Re: [PATCH v10 02/26] sfc: add basic cxl initialization
Date: Fri, 7 Feb 2025 12:48:46 +0000	[thread overview]
Message-ID: <20250207124846.GP554665@kernel.org> (raw)
In-Reply-To: <20250205151950.25268-3-alucerop@amd.com>

On Wed, Feb 05, 2025 at 03:19:26PM +0000, alucerop@amd.com wrote:
> From: Alejandro Lucero <alucerop@amd.com>
> 
> Create a cxl_memdev_state with CXL_DEVTYPE_DEVMEM, aka CXL Type2 memory
> device.
> 
> Make sfc CXL initialization dependent on kernel CXL configuration.
> 
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>

...

> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
> new file mode 100644
> index 000000000000..69feffd4aec3
> --- /dev/null
> +++ b/drivers/net/ethernet/sfc/efx_cxl.c
> @@ -0,0 +1,60 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/****************************************************************************
> + *
> + * Driver for AMD network controllers and boards
> + * Copyright (C) 2024, Advanced Micro Devices, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation, incorporated herein by reference.
> + */
> +
> +#include <cxl/pci.h>
> +#include <cxl/cxl.h>
> +#include <linux/pci.h>
> +
> +#include "net_driver.h"
> +#include "efx_cxl.h"
> +
> +#define EFX_CTPIO_BUFFER_SIZE	SZ_256M
> +
> +int efx_cxl_init(struct efx_probe_data *probe_data)
> +{
> +	struct efx_nic *efx = &probe_data->efx;
> +	struct pci_dev *pci_dev = efx->pci_dev;
> +	struct efx_cxl *cxl;
> +	u16 dvsec;
> +
> +	probe_data->cxl_pio_initialised = false;
> +
> +	dvsec = pci_find_dvsec_capability(pci_dev, PCI_VENDOR_ID_CXL,
> +					  CXL_DVSEC_PCIE_DEVICE);
> +	if (!dvsec)
> +		return 0;
> +
> +	pci_dbg(pci_dev, "CXL_DVSEC_PCIE_DEVICE capability found\n");
> +
> +	cxl = kzalloc(sizeof(*cxl), GFP_KERNEL);
> +	if (!cxl)
> +		return -ENOMEM;
> +
> +	cxl->cxlmds = cxl_memdev_state_create(&pci_dev->dev, pci_dev->dev.id,
> +					      dvsec, CXL_DEVTYPE_DEVMEM);
> +
> +	if (IS_ERR(cxl->cxlmds)) {
> +		kfree(cxl);

Hi Alejandro,

cxl is freed on the line above but dereferenced on the line below.

> +		return PTR_ERR(cxl->cxlmds);
> +	}
> +
> +	probe_data->cxl = cxl;
> +
> +	return 0;
> +}

...

  parent reply	other threads:[~2025-02-07 12:48 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-05 15:19 [PATCH v10 00/26] cxl: add type2 device basic support alucerop
2025-02-05 15:19 ` [PATCH v10 01/26] cxl: make memdev creation type agnostic alucerop
2025-02-06 19:37   ` Dan Williams
2025-02-17 12:32     ` Alejandro Lucero Palau
2025-02-19  2:29       ` Dan Williams
2025-02-20 18:17         ` Alejandro Lucero Palau
2025-02-17 13:05     ` Alejandro Lucero Palau
2025-02-13  3:57   ` Alison Schofield
2025-02-17 12:49     ` Alejandro Lucero Palau
2025-02-17 13:06     ` Alejandro Lucero Palau
2025-02-14 17:02   ` Jonathan Cameron
2025-02-17 13:08     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 02/26] sfc: add basic cxl initialization alucerop
2025-02-06  1:37   ` Edward Cree
2025-02-07 12:48   ` Simon Horman [this message]
2025-02-17 13:10     ` Alejandro Lucero Palau
2025-02-07 13:03   ` Simon Horman
2025-02-17 13:11     ` Alejandro Lucero Palau
2025-02-18 13:32       ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 03/26] cxl: move pci generic code alucerop
2025-02-05 21:33   ` Ira Weiny
2025-02-06 17:49     ` Alejandro Lucero Palau
2025-02-14 17:11       ` Jonathan Cameron
2025-02-17 13:13         ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 04/26] cxl: move register/capability check to driver alucerop
2025-02-07 12:52   ` Simon Horman
2025-02-17 13:17     ` Alejandro Lucero Palau
2025-02-14 17:21   ` Jonathan Cameron
2025-02-17 13:18     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 05/26] cxl: add function for type2 cxl regs setup alucerop
2025-02-05 21:35   ` Ira Weiny
2025-02-06 17:50     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 06/26] sfc: use cxl api for regs setup and checking alucerop
2025-02-05 21:31   ` Ira Weiny
2025-02-06 17:47     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 07/26] cxl: add support for setting media ready by an accel driver alucerop
2025-02-05 21:42   ` Ira Weiny
2025-02-06 17:58     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 08/26] sfc: set cxl media ready alucerop
2025-02-05 15:19 ` [PATCH v10 09/26] cxl: support device identification without mailbox alucerop
2025-02-05 21:45   ` Ira Weiny
2025-02-06 18:10     ` Alejandro Lucero Palau
2025-02-06 19:23       ` Ira Weiny
2025-02-17 13:41         ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 10/26] cxl: modify dpa setup process for supporting type2 alucerop
2025-02-05 15:19 ` [PATCH v10 11/26] sfc: initialize dpa resources alucerop
2025-02-05 15:19 ` [PATCH v10 12/26] cxl: prepare memdev creation for type2 alucerop
2025-02-05 15:19 ` [PATCH v10 13/26] sfc: create type2 cxl memdev alucerop
2025-02-05 15:19 ` [PATCH v10 14/26] cxl: define a driver interface for HPA free space enumeration alucerop
2025-02-07 12:55   ` Simon Horman
2025-02-17 13:44     ` Alejandro Lucero Palau
2025-02-13  4:08   ` Alison Schofield
2025-02-17 13:49     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 15/26] sfc: obtain root decoder with enough HPA free space alucerop
2025-02-05 22:47   ` Ira Weiny
2025-02-17 13:54     ` Alejandro Lucero Palau
2025-02-18  0:03       ` Ira Weiny
2025-02-05 15:19 ` [PATCH v10 16/26] cxl: define a driver interface for DPA allocation alucerop
2025-02-06 19:11   ` kernel test robot
2025-02-07 13:46   ` Simon Horman
2025-02-17 14:08     ` Alejandro Lucero Palau
2025-02-18 13:34       ` Simon Horman
2025-02-18 14:09         ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 17/26] sfc: get endpoint decoder alucerop
2025-02-05 15:19 ` [PATCH v10 18/26] cxl: make region type based on endpoint type alucerop
2025-02-05 15:19 ` [PATCH v10 19/26] cxl/region: factor out interleave ways setup alucerop
2025-02-05 15:19 ` [PATCH v10 20/26] cxl/region: factor out interleave granularity setup alucerop
2025-02-05 15:19 ` [PATCH v10 21/26] cxl: allow region creation by type2 drivers alucerop
2025-02-06 20:06   ` kernel test robot
2025-02-07 13:23   ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 22/26] cxl: add region flag for precluding a device memory to be used for dax alucerop
2025-02-05 15:19 ` [PATCH v10 23/26] sfc: create cxl region alucerop
2025-02-05 15:19 ` [PATCH v10 24/26] cxl: add function for obtaining region range alucerop
2025-02-05 15:19 ` [PATCH v10 25/26] sfc: update MCDI protocol headers alucerop
2025-02-05 15:19 ` [PATCH v10 26/26] sfc: support pio mapping based on cxl alucerop
2025-02-13  1:51 ` [PATCH v10 00/26] cxl: add type2 device basic support Alison Schofield

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