From: Simon Horman <horms@kernel.org>
To: Alejandro Lucero Palau <alucerop@amd.com>
Cc: linux-cxl@vger.kernel.org, netdev@vger.kernel.org,
dan.j.williams@intel.com, edward.cree@amd.com,
davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com,
edumazet@google.com, dave.jiang@intel.com
Subject: Re: [PATCH v10 16/26] cxl: define a driver interface for DPA allocation
Date: Tue, 18 Feb 2025 14:09:44 +0000 [thread overview]
Message-ID: <20250218140944.GZ1615191@kernel.org> (raw)
In-Reply-To: <20250218133459.GX1615191@kernel.org>
On Tue, Feb 18, 2025 at 01:34:59PM +0000, Simon Horman wrote:
> On Mon, Feb 17, 2025 at 02:08:28PM +0000, Alejandro Lucero Palau wrote:
> >
> > On 2/7/25 13:46, Simon Horman wrote:
> > > On Wed, Feb 05, 2025 at 03:19:40PM +0000, alucerop@amd.com wrote:
> > > > From: Alejandro Lucero <alucerop@amd.com>
> > > >
> > > > Region creation involves finding available DPA (device-physical-address)
> > > > capacity to map into HPA (host-physical-address) space. Define an API,
> > > > cxl_request_dpa(), that tries to allocate the DPA memory the driver
> > > > requires to operate. The memory requested should not be bigger than the
> > > > max available HPA obtained previously with cxl_get_hpa_freespace.
> > > >
> > > > Based on https://lore.kernel.org/linux-cxl/168592158743.1948938.7622563891193802610.stgit@dwillia2-xfh.jf.intel.com/
> > > >
> > > > Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> > > > ---
> > > > drivers/cxl/core/hdm.c | 83 ++++++++++++++++++++++++++++++++++++++++++
> > > > include/cxl/cxl.h | 4 ++
> > > > 2 files changed, 87 insertions(+)
> > > >
> > > > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> > > > index af025da81fa2..cec2c7dcaf3a 100644
> > > > --- a/drivers/cxl/core/hdm.c
> > > > +++ b/drivers/cxl/core/hdm.c
> > > > @@ -3,6 +3,7 @@
> > > > #include <linux/seq_file.h>
> > > > #include <linux/device.h>
> > > > #include <linux/delay.h>
> > > > +#include <cxl/cxl.h>
> > > Hi Alejandro,
> >
> >
> > Hi Simon,
> >
> >
> > > I think that linux/range.h should be included in cxl.h, or if not here.
> > > This is because on allmodconfigs for both arm and arm64 I see:
> > >
> > > In file included from drivers/cxl/core/hdm.c:6:
> > > ./include/cxl/cxl.h:67:16: error: field has incomplete type 'struct range'
> > > 67 | struct range range;
> > > | ^
> > > ./include/linux/memory_hotplug.h:247:8: note: forward declaration of 'struct range'
> > > 247 | struct range arch_get_mappable_range(void);
> > > | ^
> > > 1 error generated.
> > >
> > > ...
> >
> >
> > I do not understand then why the robot does not trigger an issue when
> > building this code for those archs.
> >
> > And where does that second struct range reference in memory_hotplug.h come
> > from? Is that related to cxl.h?
>
> Thanks, let me try to reproduce this again.
Hi Alejandro,
I tried testing this with an allmodconfig build for arm64 [*].
And this time I see this manifesting slightly differently. I can follow-up
on why it is different (probably I messed something up when first reporting
the issue). But I am certainly seeing an issue there today.
...
CC [M] drivers/cxl/core/hdm.o
In file included from drivers/cxl/core/hdm.c:6:
./include/cxl/cxl.h:67:30: error: field 'range' has incomplete type
67 | struct range range;
| ^~~~~
...
[*] This is with patches 1 - 16 of this series applied on top of next-20250205.
I am using the GCC 14.2.0 toolchain from [1] to cross compile on x86_64.
Like this:
PATH=/tmp/gcc-14.2.0-nolibc/aarch64-linux/bin:$PATH
ARCH=arm64 CROSS_COMPILE=aarch64-linux- make allmodconfig
ARCH=arm64 CROSS_COMPILE=aarch64-linux- make
[1] https://mirrors.edge.kernel.org/pub/tools/crosstool/
next prev parent reply other threads:[~2025-02-18 14:09 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-05 15:19 [PATCH v10 00/26] cxl: add type2 device basic support alucerop
2025-02-05 15:19 ` [PATCH v10 01/26] cxl: make memdev creation type agnostic alucerop
2025-02-06 19:37 ` Dan Williams
2025-02-17 12:32 ` Alejandro Lucero Palau
2025-02-19 2:29 ` Dan Williams
2025-02-20 18:17 ` Alejandro Lucero Palau
2025-02-17 13:05 ` Alejandro Lucero Palau
2025-02-13 3:57 ` Alison Schofield
2025-02-17 12:49 ` Alejandro Lucero Palau
2025-02-17 13:06 ` Alejandro Lucero Palau
2025-02-14 17:02 ` Jonathan Cameron
2025-02-17 13:08 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 02/26] sfc: add basic cxl initialization alucerop
2025-02-06 1:37 ` Edward Cree
2025-02-07 12:48 ` Simon Horman
2025-02-17 13:10 ` Alejandro Lucero Palau
2025-02-07 13:03 ` Simon Horman
2025-02-17 13:11 ` Alejandro Lucero Palau
2025-02-18 13:32 ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 03/26] cxl: move pci generic code alucerop
2025-02-05 21:33 ` Ira Weiny
2025-02-06 17:49 ` Alejandro Lucero Palau
2025-02-14 17:11 ` Jonathan Cameron
2025-02-17 13:13 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 04/26] cxl: move register/capability check to driver alucerop
2025-02-07 12:52 ` Simon Horman
2025-02-17 13:17 ` Alejandro Lucero Palau
2025-02-14 17:21 ` Jonathan Cameron
2025-02-17 13:18 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 05/26] cxl: add function for type2 cxl regs setup alucerop
2025-02-05 21:35 ` Ira Weiny
2025-02-06 17:50 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 06/26] sfc: use cxl api for regs setup and checking alucerop
2025-02-05 21:31 ` Ira Weiny
2025-02-06 17:47 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 07/26] cxl: add support for setting media ready by an accel driver alucerop
2025-02-05 21:42 ` Ira Weiny
2025-02-06 17:58 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 08/26] sfc: set cxl media ready alucerop
2025-02-05 15:19 ` [PATCH v10 09/26] cxl: support device identification without mailbox alucerop
2025-02-05 21:45 ` Ira Weiny
2025-02-06 18:10 ` Alejandro Lucero Palau
2025-02-06 19:23 ` Ira Weiny
2025-02-17 13:41 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 10/26] cxl: modify dpa setup process for supporting type2 alucerop
2025-02-05 15:19 ` [PATCH v10 11/26] sfc: initialize dpa resources alucerop
2025-02-05 15:19 ` [PATCH v10 12/26] cxl: prepare memdev creation for type2 alucerop
2025-02-05 15:19 ` [PATCH v10 13/26] sfc: create type2 cxl memdev alucerop
2025-02-05 15:19 ` [PATCH v10 14/26] cxl: define a driver interface for HPA free space enumeration alucerop
2025-02-07 12:55 ` Simon Horman
2025-02-17 13:44 ` Alejandro Lucero Palau
2025-02-13 4:08 ` Alison Schofield
2025-02-17 13:49 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 15/26] sfc: obtain root decoder with enough HPA free space alucerop
2025-02-05 22:47 ` Ira Weiny
2025-02-17 13:54 ` Alejandro Lucero Palau
2025-02-18 0:03 ` Ira Weiny
2025-02-05 15:19 ` [PATCH v10 16/26] cxl: define a driver interface for DPA allocation alucerop
2025-02-06 19:11 ` kernel test robot
2025-02-07 13:46 ` Simon Horman
2025-02-17 14:08 ` Alejandro Lucero Palau
2025-02-18 13:34 ` Simon Horman
2025-02-18 14:09 ` Simon Horman [this message]
2025-02-05 15:19 ` [PATCH v10 17/26] sfc: get endpoint decoder alucerop
2025-02-05 15:19 ` [PATCH v10 18/26] cxl: make region type based on endpoint type alucerop
2025-02-05 15:19 ` [PATCH v10 19/26] cxl/region: factor out interleave ways setup alucerop
2025-02-05 15:19 ` [PATCH v10 20/26] cxl/region: factor out interleave granularity setup alucerop
2025-02-05 15:19 ` [PATCH v10 21/26] cxl: allow region creation by type2 drivers alucerop
2025-02-06 20:06 ` kernel test robot
2025-02-07 13:23 ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 22/26] cxl: add region flag for precluding a device memory to be used for dax alucerop
2025-02-05 15:19 ` [PATCH v10 23/26] sfc: create cxl region alucerop
2025-02-05 15:19 ` [PATCH v10 24/26] cxl: add function for obtaining region range alucerop
2025-02-05 15:19 ` [PATCH v10 25/26] sfc: update MCDI protocol headers alucerop
2025-02-05 15:19 ` [PATCH v10 26/26] sfc: support pio mapping based on cxl alucerop
2025-02-13 1:51 ` [PATCH v10 00/26] cxl: add type2 device basic support Alison Schofield
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