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bh=MhOkwnRfRJLwfP6dSvZKfc6g/BsuQm8/Rk8DKbOHg8M=; b=VjNc9Dfb9+6zQTeqEjlxmGrL9jtvs1GMekMDZcHlkmepiktDUl9DLttcDBG8W7k/wy+VoP iTXe2xSU4pmiHEzuK0WMUImToUzDbMS3l9ewHy/eewy7aBqVJTO9G18WfKx8MsQvQJVNe3 nrU9qA+fJgx8jL3eTizDcp1qo/e5siQ63yJoahQLlznC9xXE5uyHVAaW6Ci5JcxX0yWDUw d7FzToisVmq5sSxEauTDZuVC3knMe/7KLwpZ8XEtvNE6J8XP9i2ewlrIanUr9ltkw+I3CJ szufUiMw0lF2boE7iWSvKbJSnfNepyI3gxw95DsfmA5gIs4rTZS0h3X7uTOTJQ== Date: Mon, 24 Feb 2025 11:03:15 +0100 From: Maxime Chevallier To: Andrew Lunn Cc: davem@davemloft.net, Jakub Kicinski , Eric Dumazet , Paolo Abeni , Russell King , Heiner Kallweit , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com, Florian Fainelli , =?UTF-8?B?S8O2cnk=?= Maincent , Simon Horman , Romain Gantois , Antoine Tenart , Marek =?UTF-8?B?QmVow7pu?= Subject: Re: [PATCH net-next 2/2] net: mdio: mdio-i2c: Add support for single-byte SMBus operations Message-ID: <20250224110315.62fb8c80@fedora> In-Reply-To: <4ff4113d-f97d-4d40-bd7e-cdba6f30b6ee@lunn.ch> References: <20250223172848.1098621-1-maxime.chevallier@bootlin.com> <20250223172848.1098621-3-maxime.chevallier@bootlin.com> <4ff4113d-f97d-4d40-bd7e-cdba6f30b6ee@lunn.ch> Organization: Bootlin X-Mailer: Claws Mail 4.3.0 (GTK 3.24.43; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeefvddrtddtgdejkeegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhepfffhvfevuffkjghfohfogggtgfesthejredtredtvdenucfhrhhomhepofgrgihimhgvucevhhgvvhgrlhhlihgvrhcuoehmrgigihhmvgdrtghhvghvrghllhhivghrsegsohhothhlihhnrdgtohhmqeenucggtffrrghtthgvrhhnpeegveeltddvveeuhefhvefhlefhkeevfedtgfeiudefffeiledttdfgfeeuhfeukeenucfkphepledtrdekledrudeifedruddvjeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpeeltddrkeelrdduieefrdduvdejpdhhvghlohepfhgvughorhgrpdhmrghilhhfrhhomhepmhgrgihimhgvrdgthhgvvhgrlhhlihgvrhessghoohhtlhhinhdrtghomhdpnhgspghrtghpthhtohepudeipdhrtghpthhtoheprghnughrvgifsehluhhnnhdrtghhpdhrtghpthhtohepuggrvhgvmhesuggrvhgvmhhlohhfthdrnhgvthdprhgtphhtthhopehkuhgsrgeskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepvgguuhhmrgiivghtsehgohhoghhlvgdrtghomhdprhgtphhtthhopehprggsvghnihesrhgvughhrghtrdgtohhmpdhrtghpthhtoheplhhinhhugiesrghrm hhlihhnuhigrdhorhhgrdhukhdprhgtphhtthhopehhkhgrlhhlfigvihhtudesghhmrghilhdrtghomhdprhgtphhtthhopehnvghtuggvvhesvhhgvghrrdhkvghrnhgvlhdrohhrgh X-GND-Sasl: maxime.chevallier@bootlin.com On Mon, 24 Feb 2025 04:36:49 +0100 Andrew Lunn wrote: > > This was only tested on Copper SFP modules that embed a Marvell 88e1111 > > PHY. > > Does the Marvell PHY datasheet say what happens when you perform 8 bit > accesses to 16 bit registers, such at the BMSR? It doesn't specifically say what happens to BMSR, however the section about "how to perform a random read" gives an example of a random register read that is made of 2 single-byte reads, including the STOP bit being set in-between reading the upper byte and the lower byte. While this doesn't exactly specify the BMSR's latching behaviour, it looks to me that this is a coherent way of reading a register state, and BMSR's link status register *should* latch until the lower byte is read. I'll try it out with one of my modules to make sure though. Maxime