[PATCH net v2 0/2] net: phy: nxp-c45-tja11xx: add errata for TJA112XA/B

[PATCH net v2 0/2] net: phy: nxp-c45-tja11xx: add errata for TJA112XA/B

[Andrei Botila]

This patch series implements two errata for TJA1120 and TJA1121.

The first errata applicable to both RGMII and SGMII version
of TJA1120 and TJA1121 deals with achieving full silicon performance.
The workaround in this case is putting the PHY in managed mode and
applying a series of PHY writes before the link gest established.

The second errata applicable only to SGMII version of TJA1120 and
TJA1121 deals with achieving a stable operation of SGMII after a
startup event.
The workaround puts the SGMII PCS into power down mode and back up
after restart or wakeup from sleep.

Changes in v2:
- use phy_id_compare() in case phydev->drv->phy_id is not set

Andrei Botila (2):
  net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata
  net: phy: nxp-c45-tja11xx: add TJA112XB SGMII PCS restart errata

 drivers/net/phy/nxp-c45-tja11xx.c | 68 +++++++++++++++++++++++++++++++
 1 file changed, 68 insertions(+)

-- 
2.48.1

[PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata

[Andrei Botila]

The most recent sillicon versions of TJA1120 and TJA1121 can achieve
full silicon performance by putting the PHY in managed mode.

It is necessary to apply these PHY writes before link gets established.
Application of this fix is required after restart of device and wakeup
from sleep.

Cc: stable@vger.kernel.org
Fixes: f1fe5dff2b8a ("net: phy: nxp-c45-tja11xx: add TJA1120 support")
Signed-off-by: Andrei Botila <andrei.botila@oss.nxp.com>
---
 drivers/net/phy/nxp-c45-tja11xx.c | 52 +++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c
index 34231b5b9175..709d6c9f7cba 100644
--- a/drivers/net/phy/nxp-c45-tja11xx.c
+++ b/drivers/net/phy/nxp-c45-tja11xx.c
@@ -22,6 +22,11 @@
 #define PHY_ID_TJA_1103			0x001BB010
 #define PHY_ID_TJA_1120			0x001BB031
 
+#define VEND1_DEVICE_ID3		0x0004
+#define TJA1120_DEV_ID3_SILICON_VERSION	GENMASK(15, 12)
+#define TJA1120_DEV_ID3_SAMPLE_TYPE	GENMASK(11, 8)
+#define DEVICE_ID3_SAMPLE_TYPE_R	0x9
+
 #define VEND1_DEVICE_CONTROL		0x0040
 #define DEVICE_CONTROL_RESET		BIT(15)
 #define DEVICE_CONTROL_CONFIG_GLOBAL_EN	BIT(14)
@@ -1593,6 +1598,50 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev)
 	return 0;
 }
 
+/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 */
+static void nxp_c45_tja1120_errata(struct phy_device *phydev)
+{
+	int silicon_version, sample_type;
+	bool macsec_ability;
+	int phy_abilities;
+	int ret = 0;
+
+	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3);
+	if (ret < 0)
+		return;
+
+	sample_type = FIELD_GET(TJA1120_DEV_ID3_SAMPLE_TYPE, ret);
+	if (sample_type != DEVICE_ID3_SAMPLE_TYPE_R)
+		return;
+
+	silicon_version = FIELD_GET(TJA1120_DEV_ID3_SILICON_VERSION, ret);
+
+	phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
+				     VEND1_PORT_ABILITIES);
+	macsec_ability = !!(phy_abilities & MACSEC_ABILITY);
+	if ((!macsec_ability && silicon_version == 2) ||
+	    (macsec_ability && silicon_version == 1)) {
+		/* TJA1120/TJA1121 PHY configuration errata workaround.
+		 * Apply PHY writes sequence before link up.
+		 */
+		if (!macsec_ability) {
+			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95);
+			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd);
+		} else {
+			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7);
+			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893);
+		}
+
+		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0);
+
+		phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a);
+		phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1);
+
+		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0);
+		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0);
+	}
+}
+
 static int nxp_c45_config_init(struct phy_device *phydev)
 {
 	int ret;
@@ -1609,6 +1658,9 @@ static int nxp_c45_config_init(struct phy_device *phydev)
 	phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1);
 	phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2);
 
+	if (phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, GENMASK(31, 4)))
+		nxp_c45_tja1120_errata(phydev);
+
 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG,
 			 PHY_CONFIG_AUTO);
 
-- 
2.48.1

[PATCH net v2 2/2] net: phy: nxp-c45-tja11xx: add TJA112XB SGMII PCS restart errata

[Andrei Botila]

TJA1120B/TJA1121B can achieve a stable operation of SGMII after
a startup event by putting the SGMII PCS into power down mode and
restart afterwards.

It is necessary to put the SGMII PCS into power down mode and back up.

Cc: stable@vger.kernel.org
Fixes: f1fe5dff2b8a ("net: phy: nxp-c45-tja11xx: add TJA1120 support")
Signed-off-by: Andrei Botila <andrei.botila@oss.nxp.com>
---
 drivers/net/phy/nxp-c45-tja11xx.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c
index 709d6c9f7cba..e9fc54517449 100644
--- a/drivers/net/phy/nxp-c45-tja11xx.c
+++ b/drivers/net/phy/nxp-c45-tja11xx.c
@@ -114,6 +114,9 @@
 #define MII_BASIC_CONFIG_RMII		0x5
 #define MII_BASIC_CONFIG_MII		0x4
 
+#define VEND1_SGMII_BASIC_CONTROL	0xB000
+#define SGMII_LPM			BIT(11)
+
 #define VEND1_SYMBOL_ERROR_CNT_XTD	0x8351
 #define EXTENDED_CNT_EN			BIT(15)
 #define VEND1_MONITOR_STATUS		0xAC80
@@ -1598,11 +1601,11 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev)
 	return 0;
 }
 
-/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 */
+/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 & 3.2 */
 static void nxp_c45_tja1120_errata(struct phy_device *phydev)
 {
+	bool macsec_ability, sgmii_ability;
 	int silicon_version, sample_type;
-	bool macsec_ability;
 	int phy_abilities;
 	int ret = 0;
 
@@ -1619,6 +1622,7 @@ static void nxp_c45_tja1120_errata(struct phy_device *phydev)
 	phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
 				     VEND1_PORT_ABILITIES);
 	macsec_ability = !!(phy_abilities & MACSEC_ABILITY);
+	sgmii_ability = !!(phy_abilities & SGMII_ABILITY);
 	if ((!macsec_ability && silicon_version == 2) ||
 	    (macsec_ability && silicon_version == 1)) {
 		/* TJA1120/TJA1121 PHY configuration errata workaround.
@@ -1639,6 +1643,18 @@ static void nxp_c45_tja1120_errata(struct phy_device *phydev)
 
 		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0);
 		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0);
+
+		if (sgmii_ability) {
+			/* TJA1120B/TJA1121B SGMII PCS restart errata workaround.
+			 * Put SGMII PCS into power down mode and back up.
+			 */
+			phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+					 VEND1_SGMII_BASIC_CONTROL,
+					 SGMII_LPM);
+			phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
+					   VEND1_SGMII_BASIC_CONTROL,
+					   SGMII_LPM);
+		}
 	}
 }
 
-- 
2.48.1

Re: [PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata

[Paolo Abeni]

On 3/4/25 5:06 PM, Andrei Botila wrote:
> diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c
> index 34231b5b9175..709d6c9f7cba 100644
> --- a/drivers/net/phy/nxp-c45-tja11xx.c
> +++ b/drivers/net/phy/nxp-c45-tja11xx.c
> @@ -22,6 +22,11 @@
>  #define PHY_ID_TJA_1103			0x001BB010
>  #define PHY_ID_TJA_1120			0x001BB031
>  
> +#define VEND1_DEVICE_ID3		0x0004
> +#define TJA1120_DEV_ID3_SILICON_VERSION	GENMASK(15, 12)
> +#define TJA1120_DEV_ID3_SAMPLE_TYPE	GENMASK(11, 8)
> +#define DEVICE_ID3_SAMPLE_TYPE_R	0x9
> +
>  #define VEND1_DEVICE_CONTROL		0x0040
>  #define DEVICE_CONTROL_RESET		BIT(15)
>  #define DEVICE_CONTROL_CONFIG_GLOBAL_EN	BIT(14)
> @@ -1593,6 +1598,50 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev)
>  	return 0;
>  }
>  
> +/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 */
> +static void nxp_c45_tja1120_errata(struct phy_device *phydev)
> +{
> +	int silicon_version, sample_type;
> +	bool macsec_ability;
> +	int phy_abilities;
> +	int ret = 0;
> +
> +	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3);
> +	if (ret < 0)
> +		return;
> +
> +	sample_type = FIELD_GET(TJA1120_DEV_ID3_SAMPLE_TYPE, ret);
> +	if (sample_type != DEVICE_ID3_SAMPLE_TYPE_R)
> +		return;
> +
> +	silicon_version = FIELD_GET(TJA1120_DEV_ID3_SILICON_VERSION, ret);
> +
> +	phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
> +				     VEND1_PORT_ABILITIES);
> +	macsec_ability = !!(phy_abilities & MACSEC_ABILITY);
> +	if ((!macsec_ability && silicon_version == 2) ||
> +	    (macsec_ability && silicon_version == 1)) {
> +		/* TJA1120/TJA1121 PHY configuration errata workaround.
> +		 * Apply PHY writes sequence before link up.
> +		 */
> +		if (!macsec_ability) {
> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95);
> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd);
> +		} else {
> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7);
> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893);
> +		}
> +
> +		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0);
> +
> +		phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a);
> +		phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1);
> +
> +		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0);
> +		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0);

Please add macro with meaningful names for all the magic numbers used
above, thanks!

Paolo

Re: [PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata

[Andrei Botila]

On 3/6/2025 11:43 AM, Paolo Abeni wrote:
> On 3/4/25 5:06 PM, Andrei Botila wrote:
>> diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c
>> index 34231b5b9175..709d6c9f7cba 100644
>> --- a/drivers/net/phy/nxp-c45-tja11xx.c
>> +++ b/drivers/net/phy/nxp-c45-tja11xx.c
>> @@ -22,6 +22,11 @@
>>  #define PHY_ID_TJA_1103			0x001BB010
>>  #define PHY_ID_TJA_1120			0x001BB031
>>  
>> +#define VEND1_DEVICE_ID3		0x0004
>> +#define TJA1120_DEV_ID3_SILICON_VERSION	GENMASK(15, 12)
>> +#define TJA1120_DEV_ID3_SAMPLE_TYPE	GENMASK(11, 8)
>> +#define DEVICE_ID3_SAMPLE_TYPE_R	0x9
>> +
>>  #define VEND1_DEVICE_CONTROL		0x0040
>>  #define DEVICE_CONTROL_RESET		BIT(15)
>>  #define DEVICE_CONTROL_CONFIG_GLOBAL_EN	BIT(14)
>> @@ -1593,6 +1598,50 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev)
>>  	return 0;
>>  }
>>  
>> +/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 */
>> +static void nxp_c45_tja1120_errata(struct phy_device *phydev)
>> +{
>> +	int silicon_version, sample_type;
>> +	bool macsec_ability;
>> +	int phy_abilities;
>> +	int ret = 0;
>> +
>> +	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3);
>> +	if (ret < 0)
>> +		return;
>> +
>> +	sample_type = FIELD_GET(TJA1120_DEV_ID3_SAMPLE_TYPE, ret);
>> +	if (sample_type != DEVICE_ID3_SAMPLE_TYPE_R)
>> +		return;
>> +
>> +	silicon_version = FIELD_GET(TJA1120_DEV_ID3_SILICON_VERSION, ret);
>> +
>> +	phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
>> +				     VEND1_PORT_ABILITIES);
>> +	macsec_ability = !!(phy_abilities & MACSEC_ABILITY);
>> +	if ((!macsec_ability && silicon_version == 2) ||
>> +	    (macsec_ability && silicon_version == 1)) {
>> +		/* TJA1120/TJA1121 PHY configuration errata workaround.
>> +		 * Apply PHY writes sequence before link up.
>> +		 */
>> +		if (!macsec_ability) {
>> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95);
>> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd);
>> +		} else {
>> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7);
>> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893);
>> +		}
>> +
>> +		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0);
>> +
>> +		phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a);
>> +		phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1);
>> +
>> +		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0);
>> +		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0);
> 
> Please add macro with meaningful names for all the magic numbers used
> above, thanks!
> 
> Paolo
> 

Hello, these registers are not documented in the datasheet or errata sheet.
The access sequence comes 1-to-1 from the errata so I couldn't use macros.

Regards, Andrei B.

Re: [PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata

[Andrew Lunn]

> >> +/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 */
> >> +static void nxp_c45_tja1120_errata(struct phy_device *phydev)
> >> +{
> >> +	int silicon_version, sample_type;
> >> +	bool macsec_ability;
> >> +	int phy_abilities;
> >> +	int ret = 0;
> >> +
> >> +	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3);
> >> +	if (ret < 0)
> >> +		return;
> >> +
> >> +	sample_type = FIELD_GET(TJA1120_DEV_ID3_SAMPLE_TYPE, ret);
> >> +	if (sample_type != DEVICE_ID3_SAMPLE_TYPE_R)
> >> +		return;
> >> +
> >> +	silicon_version = FIELD_GET(TJA1120_DEV_ID3_SILICON_VERSION, ret);
> >> +
> >> +	phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
> >> +				     VEND1_PORT_ABILITIES);
> >> +	macsec_ability = !!(phy_abilities & MACSEC_ABILITY);
> >> +	if ((!macsec_ability && silicon_version == 2) ||
> >> +	    (macsec_ability && silicon_version == 1)) {
> >> +		/* TJA1120/TJA1121 PHY configuration errata workaround.
> >> +		 * Apply PHY writes sequence before link up.
> >> +		 */
> >> +		if (!macsec_ability) {
> >> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95);
> >> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd);
> >> +		} else {
> >> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7);
> >> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893);
> >> +		}
> >> +
> >> +		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0);
> >> +
> >> +		phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a);
> >> +		phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1);
> >> +
> >> +		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0);
> >> +		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0);
> > 
> > Please add macro with meaningful names for all the magic numbers used
> > above, thanks!
> > 
> > Paolo
> > 
> 
> Hello, these registers are not documented in the datasheet or errata sheet.
> The access sequence comes 1-to-1 from the errata so I couldn't use macros.

Yes, we sometimes just have to accept the drivers are doing magic we
have no idea about because the vendor does not want to tell is. All
the registers in MDIO_MMD_VEND1 are clearly vendor specific. The
MDIO_MMD_PMAPMD registers are also in the range reserved for
vendors. So i think we just have to accept it.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata

[Simon Horman]

On Thu, Mar 06, 2025 at 04:35:12PM +0100, Andrew Lunn wrote:
> > >> +/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 */
> > >> +static void nxp_c45_tja1120_errata(struct phy_device *phydev)
> > >> +{
> > >> +	int silicon_version, sample_type;
> > >> +	bool macsec_ability;
> > >> +	int phy_abilities;
> > >> +	int ret = 0;
> > >> +
> > >> +	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3);
> > >> +	if (ret < 0)
> > >> +		return;
> > >> +
> > >> +	sample_type = FIELD_GET(TJA1120_DEV_ID3_SAMPLE_TYPE, ret);
> > >> +	if (sample_type != DEVICE_ID3_SAMPLE_TYPE_R)
> > >> +		return;
> > >> +
> > >> +	silicon_version = FIELD_GET(TJA1120_DEV_ID3_SILICON_VERSION, ret);
> > >> +
> > >> +	phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
> > >> +				     VEND1_PORT_ABILITIES);
> > >> +	macsec_ability = !!(phy_abilities & MACSEC_ABILITY);
> > >> +	if ((!macsec_ability && silicon_version == 2) ||
> > >> +	    (macsec_ability && silicon_version == 1)) {
> > >> +		/* TJA1120/TJA1121 PHY configuration errata workaround.
> > >> +		 * Apply PHY writes sequence before link up.
> > >> +		 */
> > >> +		if (!macsec_ability) {
> > >> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95);
> > >> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd);
> > >> +		} else {
> > >> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7);
> > >> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893);
> > >> +		}
> > >> +
> > >> +		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0);
> > >> +
> > >> +		phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a);
> > >> +		phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1);
> > >> +
> > >> +		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0);
> > >> +		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0);
> > > 
> > > Please add macro with meaningful names for all the magic numbers used
> > > above, thanks!
> > > 
> > > Paolo
> > > 
> > 
> > Hello, these registers are not documented in the datasheet or errata sheet.
> > The access sequence comes 1-to-1 from the errata so I couldn't use macros.
> 
> Yes, we sometimes just have to accept the drivers are doing magic we
> have no idea about because the vendor does not want to tell is. All
> the registers in MDIO_MMD_VEND1 are clearly vendor specific. The
> MDIO_MMD_PMAPMD registers are also in the range reserved for
> vendors. So i think we just have to accept it.

+1

It can happen that vendors regard such information as IP that they do
not wish to disclose. Not saying that is the case here. Just saying
it is one reason that we sometimes have to accept such things.
So I think what you say above is completely reasonable.

> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
> 
>     Andrew
> 

Re: [PATCH net v2 0/2] net: phy: nxp-c45-tja11xx: add errata for TJA112XA/B

[patchwork-bot+netdevbpf]

Hello:

This series was applied to netdev/net.git (main)
by Jakub Kicinski <kuba@kernel.org>:

On Tue,  4 Mar 2025 18:06:12 +0200 you wrote:
> This patch series implements two errata for TJA1120 and TJA1121.
> 
> The first errata applicable to both RGMII and SGMII version
> of TJA1120 and TJA1121 deals with achieving full silicon performance.
> The workaround in this case is putting the PHY in managed mode and
> applying a series of PHY writes before the link gest established.
> 
> [...]

Here is the summary with links:
  - [net,v2,1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata
    https://git.kernel.org/netdev/net/c/a07364b39469
  - [net,v2,2/2] net: phy: nxp-c45-tja11xx: add TJA112XB SGMII PCS restart errata
    https://git.kernel.org/netdev/net/c/48939523843e

You are awesome, thank you!
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