Re: [PATCH net-next v3 0/2] net: phy: sfp: Add single-byte SMBus SFP access

[Maxime Chevallier <maxime.chevallier@bootlin.com>]

Hello Andrew,

On Mon, 17 Mar 2025 22:34:09 +0100
Andrew Lunn <andrew@lunn.ch> wrote:

> On Fri, Mar 14, 2025 at 05:23:16PM +0100, Maxime Chevallier wrote:
> > Hello everyone,
> > 
> > This is V3 for the single-byte SMBus support for SFP cages as well as
> > embedded PHYs accessed over mdio-i2c.  
> 
> Just curious, what hardware is this? And does it support bit-banging
> the I2C pins? If it does, you get a choice, slow but correct vs fast
> but broken and limited?

The HW is a VSC8552 PHY that includes a so-called "i2c mux", which in
reality is that smbus interface.

             +---------+
 +-----+     |         |     +-----+
 | MAC | --- | VSC8552 | --- | SFP |
 +-----+     |         |     +-----+
    |        |         |        |
    +-mdio---|         |-smbus--+
             +---------+

it has 4 SCL and 1 SDA lines, that you can connect to 4 different SFP
cages.

You perform transfers by using 2 dedicated MDIO registers , one
register contains xfer info such as the address to access over smbus,
the direction of the xfer, and the other one contains data :
 - lower byte is write data
 - upper byte is read-back data

and that's all you have :( so the HW can only really do one single byte
transfer at a time, then you re-configure the 2 registers above, rinse
and repeat.

Looks like the datasheet is publicly available :

https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/60001809A.pdf

The whole xfer protocol is described in page 35.

On the board itself, the i2c for the SFP cage is connected to that PHY
smbus.

Now it looks like there's some pinmux within the PHY and we can use the
PHY as a gpio controller, so we could consider using a bitbang approach
indeed (provided that SFP is on PHY smbus bus 0 or 1).

I didn't consider that, it's probably worth giving a try, even if as
you say it's probably be very slow, each bit being set amounting to a
mdio xfer towards the PHY.

But if it allows better HW support, and the SFP reacts well on slow
busses, it may be work :)

Do we still want the current series ? Looks like some other people were
interested in that.

On my side that's the second time I deal with a product that uses a PHY
from this family and uses that smbus feature (but if that bitbang thing
works it's probably better)

Thanks,

Maxime