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bh=wH9krpUaOUfNxPqmjVtIC4eOg6NnJP0I0NYX9C6ILs0=; b=mdaolHjcBM5J+3USTKkvgACDoOJRIL/AZRaMIkYGvGR0P1OhmDOqyM1wf4jSgl+dfFQpwj Qi4OGN8uFpLM95YpnzxFfvihz3DyzKsjGMBysp9lTdvEwc6SGODz04nahDPWVp84YrW9HT C7JIcWrkX6x/yVN7f1UtqnNrk2kyQAV7lg1dj08exOhf9oC0zmJuiOQ4zZPo34aYDLDtwM WiW9uDXFaAiUHGtdx0SsoLEU9egfuii5yoHI6LpDwEGqjeS0hctP1lnbyRE82jMkedXgGS B8NemPce+4fzsFw+oIIsdPTlmkZ/ZB1TnZ6Dmg8yKIwt6Fj/9DbOkB+Qt8dt/Q== Date: Tue, 18 Mar 2025 09:25:51 +0100 From: Maxime Chevallier To: Andrew Lunn Cc: davem@davemloft.net, Jakub Kicinski , Eric Dumazet , Paolo Abeni , Russell King , Heiner Kallweit , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com, Florian Fainelli , =?UTF-8?B?S8O2cnk=?= Maincent , Simon Horman , Romain Gantois , Antoine Tenart , Marek =?UTF-8?B?QmVow7pu?= , Sean Anderson , =?UTF-8?B?QmrDuHJu?= Mork Subject: Re: [PATCH net-next v3 0/2] net: phy: sfp: Add single-byte SMBus SFP access Message-ID: <20250318092551.3beed50d@fedora.home> In-Reply-To: <1653ddbd-af37-4ed1-8419-06d17424b894@lunn.ch> References: <20250314162319.516163-1-maxime.chevallier@bootlin.com> <1653ddbd-af37-4ed1-8419-06d17424b894@lunn.ch> Organization: Bootlin X-Mailer: Claws Mail 4.3.0 (GTK 3.24.43; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeefvddrtddtgddugeduleehucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuifetpfffkfdpucggtfgfnhhsuhgsshgtrhhisggvnecuuegrihhlohhuthemuceftddunecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpeffhffvvefukfgjfhhoofggtgfgsehtjeertdertddvnecuhfhrohhmpeforgigihhmvgcuvehhvghvrghllhhivghruceomhgrgihimhgvrdgthhgvvhgrlhhlihgvrhessghoohhtlhhinhdrtghomheqnecuggftrfgrthhtvghrnhepjeetjefgheegfeejtdetfefggfekveeggeehudeuteeuleeviedvheevtdeugfetnecuffhomhgrihhnpehmihgtrhhotghhihhprdgtohhmnecukfhppedvrgdtudemtggsudelmeekugegheemgeeltddtmeeiheeikeemvdelsgdumeelvghfheemvgektgejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepvdgrtddumegtsgduleemkegugeehmeegledttdemieehieekmedvlegsudemlegvfhehmegvkegtjedphhgvlhhopehfvgguohhrrgdrhhhomhgvpdhmrghilhhfrhhomhepmhgrgihimhgvrdgthhgvvhgrlhhlihgvrhessghoohhtlhhinhdrtghomhdpnhgspghrtghpthhtohepudekpdhrtghpthhtoheprghnughrvgifsehluhhnnhdrtghhpdhrtghpthhtohepuggrvhgvmhesuggrvhgvmhhlohhfthdrnhgvthdprhgtphhtthhopehkuhgsr geskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepvgguuhhmrgiivghtsehgohhoghhlvgdrtghomhdprhgtphhtthhopehprggsvghnihesrhgvughhrghtrdgtohhmpdhrtghpthhtoheplhhinhhugiesrghrmhhlihhnuhigrdhorhhgrdhukhdprhgtphhtthhopehhkhgrlhhlfigvihhtudesghhmrghilhdrtghomhdprhgtphhtthhopehnvghtuggvvhesvhhgvghrrdhkvghrnhgvlhdrohhrgh X-GND-Sasl: maxime.chevallier@bootlin.com Hello Andrew, On Mon, 17 Mar 2025 22:34:09 +0100 Andrew Lunn wrote: > On Fri, Mar 14, 2025 at 05:23:16PM +0100, Maxime Chevallier wrote: > > Hello everyone, > > > > This is V3 for the single-byte SMBus support for SFP cages as well as > > embedded PHYs accessed over mdio-i2c. > > Just curious, what hardware is this? And does it support bit-banging > the I2C pins? If it does, you get a choice, slow but correct vs fast > but broken and limited? The HW is a VSC8552 PHY that includes a so-called "i2c mux", which in reality is that smbus interface. +---------+ +-----+ | | +-----+ | MAC | --- | VSC8552 | --- | SFP | +-----+ | | +-----+ | | | | +-mdio---| |-smbus--+ +---------+ it has 4 SCL and 1 SDA lines, that you can connect to 4 different SFP cages. You perform transfers by using 2 dedicated MDIO registers , one register contains xfer info such as the address to access over smbus, the direction of the xfer, and the other one contains data : - lower byte is write data - upper byte is read-back data and that's all you have :( so the HW can only really do one single byte transfer at a time, then you re-configure the 2 registers above, rinse and repeat. Looks like the datasheet is publicly available : https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/60001809A.pdf The whole xfer protocol is described in page 35. On the board itself, the i2c for the SFP cage is connected to that PHY smbus. Now it looks like there's some pinmux within the PHY and we can use the PHY as a gpio controller, so we could consider using a bitbang approach indeed (provided that SFP is on PHY smbus bus 0 or 1). I didn't consider that, it's probably worth giving a try, even if as you say it's probably be very slow, each bit being set amounting to a mdio xfer towards the PHY. But if it allows better HW support, and the SFP reacts well on slow busses, it may be work :) Do we still want the current series ? Looks like some other people were interested in that. On my side that's the second time I deal with a product that uses a PHY from this family and uses that smbus feature (but if that bitbang thing works it's probably better) Thanks, Maxime