From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: <alejandro.lucero-palau@amd.com>
Cc: <linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>,
<dan.j.williams@intel.com>, <edward.cree@amd.com>,
<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
<edumazet@google.com>, <dave.jiang@intel.com>,
Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v12 11/23] cxl: define a driver interface for HPA free space enumeration
Date: Fri, 4 Apr 2025 17:37:16 +0100 [thread overview]
Message-ID: <20250404173716.00004438@huawei.com> (raw)
In-Reply-To: <20250331144555.1947819-12-alejandro.lucero-palau@amd.com>
On Mon, 31 Mar 2025 15:45:43 +0100
alejandro.lucero-palau@amd.com wrote:
> From: Alejandro Lucero <alucerop@amd.com>
>
> CXL region creation involves allocating capacity from device DPA
> (device-physical-address space) and assigning it to decode a given HPA
> (host-physical-address space). Before determining how much DPA to
> allocate the amount of available HPA must be determined. Also, not all
> HPA is created equal, some specifically targets RAM, some target PMEM,
> some is prepared for device-memory flows like HDM-D and HDM-DB, and some
> is host-only (HDM-H).
>
> Wrap all of those concerns into an API that retrieves a root decoder
> (platform CXL window) that fits the specified constraints and the
> capacity available for a new region.
>
> Add a complementary function for releasing the reference to such root
> decoder.
>
> Based on https://lore.kernel.org/linux-cxl/168592159290.1948938.13522227102445462976.stgit@dwillia2-xfh.jf.intel.com/
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> ---
> drivers/cxl/core/region.c | 160 ++++++++++++++++++++++++++++++++++++++
> drivers/cxl/cxl.h | 3 +
> include/cxl/cxl.h | 11 ++-
> 3 files changed, 173 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index c3f4dc244df7..59fb51ff8922 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -695,6 +695,166 @@ static int free_hpa(struct cxl_region *cxlr)
> return 0;
> }
> +static int find_max_hpa(struct device *dev, void *data)
> +{
> + struct cxlrd_max_context *ctx = data;
> + struct cxl_switch_decoder *cxlsd;
> + struct cxl_root_decoder *cxlrd;
> + struct resource *res, *prev;
> + struct cxl_decoder *cxld;
> + resource_size_t max;
> + int found = 0;
> +
> + if (!is_root_decoder(dev))
> + return 0;
> +
> + cxlrd = to_cxl_root_decoder(dev);
> + cxlsd = &cxlrd->cxlsd;
> + cxld = &cxlsd->cxld;
> + if ((cxld->flags & ctx->flags) != ctx->flags) {
Hmm. Is this a subset test?
if (!(cxld->flags & ~ctx->flags)) or something like that?
Or just use bitmap_subset() on it if they are both unsigned longs.
> + dev_dbg(dev, "flags not matching: %08lx vs %08lx\n",
> + cxld->flags, ctx->flags);
> + return 0;
> + }
> +
> + for (int i = 0; i < ctx->interleave_ways; i++) {
> + for (int j = 0; j < ctx->interleave_ways; j++) {
> + if (ctx->host_bridges[i] == cxlsd->target[j]->dport_dev) {
> + found++;
> + break;
> + }
> + }
> + }
> +
> + if (found != ctx->interleave_ways) {
> + dev_dbg(dev, "Not enough host bridges found(%d) for interleave ways requested (%d)\n",
> + found, ctx->interleave_ways);
> + return 0;
> + }
> +
> + /*
> + * Walk the root decoder resource range relying on cxl_region_rwsem to
> + * preclude sibling arrival/departure and find the largest free space
> + * gap.
> + */
> + lockdep_assert_held_read(&cxl_region_rwsem);
> + max = 0;
> + res = cxlrd->res->child;
> +
> + /* With no resource child the whole parent resource is available */
> + if (!res)
> + max = resource_size(cxlrd->res);
> + else
> + max = 0;
max is already 0 in this path.
> +
> + for (prev = NULL; res; prev = res, res = res->sibling) {
> + struct resource *next = res->sibling;
> + resource_size_t free = 0;
> +
> + /*
> + * Sanity check for preventing arithmetic problems below as a
> + * resource with size 0 could imply using the end field below
> + * when set to unsigned zero - 1 or all f in hex.
> + */
> + if (prev && !resource_size(prev))
> + continue;
> +
> + if (!prev && res->start > cxlrd->res->start) {
> + free = res->start - cxlrd->res->start;
> + max = max(free, max);
> + }
> + if (prev && res->start > prev->end + 1) {
> + free = res->start - prev->end + 1;
> + max = max(free, max);
> + }
> + if (next && res->end + 1 < next->start) {
> + free = next->start - res->end + 1;
> + max = max(free, max);
> + }
> + if (!next && res->end + 1 < cxlrd->res->end + 1) {
> + free = cxlrd->res->end + 1 - res->end + 1;
> + max = max(free, max);
> + }
> + }
> +
> + dev_dbg(CXLRD_DEV(cxlrd), "found %pa bytes of free space\n", &max);
> + if (max > ctx->max_hpa) {
> + if (ctx->cxlrd)
> + put_device(CXLRD_DEV(ctx->cxlrd));
> + get_device(CXLRD_DEV(cxlrd));
> + ctx->cxlrd = cxlrd;
> + ctx->max_hpa = max;
> + }
> + return 0;
> +}
next prev parent reply other threads:[~2025-04-04 16:37 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-31 14:45 [PATCH v12 00/23] cxl: add type2 device basic support alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 01/23] " alejandro.lucero-palau
2025-04-01 17:36 ` Alejandro Lucero Palau
2025-04-04 15:24 ` Jonathan Cameron
2025-04-07 9:50 ` Alejandro Lucero Palau
2025-04-10 8:12 ` Alejandro Lucero Palau
2025-04-07 16:55 ` Dave Jiang
2025-03-31 14:45 ` [PATCH v12 02/23] sfc: add cxl support alejandro.lucero-palau
2025-03-31 18:31 ` Simon Horman
2025-04-07 13:59 ` Alejandro Lucero Palau
2025-04-04 15:29 ` Jonathan Cameron
2025-03-31 14:45 ` [PATCH v12 03/23] cxl: move pci generic code alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 04/23] cxl: move register/capability check to driver alejandro.lucero-palau
2025-04-04 15:47 ` Jonathan Cameron
2025-04-07 13:40 ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 05/23] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2025-03-31 18:33 ` Simon Horman
2025-04-07 14:00 ` Alejandro Lucero Palau
2025-04-04 16:03 ` Jonathan Cameron
2025-04-07 10:04 ` Alejandro Lucero Palau
2025-04-15 16:34 ` Jonathan Cameron
2025-03-31 14:45 ` [PATCH v12 06/23] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 07/23] cxl: support dpa initialization without a mailbox alejandro.lucero-palau
2025-04-04 16:05 ` Jonathan Cameron
2025-04-07 10:53 ` Alejandro Lucero Palau
2025-04-10 11:37 ` Alejandro Lucero Palau
2025-04-04 16:11 ` Jonathan Cameron
2025-04-07 10:56 ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 08/23] sfc: initialize dpa alejandro.lucero-palau
2025-04-04 16:12 ` Jonathan Cameron
2025-04-07 11:01 ` Alejandro Lucero Palau
2025-04-10 11:48 ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 09/23] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2025-03-31 18:34 ` Simon Horman
2025-04-07 14:01 ` Alejandro Lucero Palau
2025-04-04 16:25 ` Jonathan Cameron
2025-04-11 21:07 ` Dave Jiang
2025-03-31 14:45 ` [PATCH v12 10/23] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 11/23] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-04-04 16:37 ` Jonathan Cameron [this message]
2025-04-07 13:25 ` Alejandro Lucero Palau
2025-04-11 21:30 ` Dave Jiang
2025-04-14 13:14 ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 12/23] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-04-04 16:38 ` Jonathan Cameron
2025-04-07 11:02 ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 13/23] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2025-04-04 16:41 ` Jonathan Cameron
2025-04-11 22:41 ` Dave Jiang
2025-04-14 13:28 ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 14/23] sfc: get endpoint decoder alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 15/23] cxl: make region type based on endpoint type alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 16/23] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 17/23] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 18/23] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2025-04-04 16:45 ` Jonathan Cameron
2025-04-07 11:03 ` Alejandro Lucero Palau
2025-04-11 23:18 ` Dave Jiang
2025-04-14 13:52 ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 19/23] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-04-11 23:25 ` Dave Jiang
2025-03-31 14:45 ` [PATCH v12 20/23] sfc: create cxl region alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 21/23] cxl: add function for obtaining region range alejandro.lucero-palau
2025-04-11 23:32 ` Dave Jiang
2025-03-31 14:45 ` [PATCH v12 22/23] sfc: update MCDI protocol headers alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 23/23] sfc: support pio mapping based on cxl alejandro.lucero-palau
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