From: Andre Przywara <andre.przywara@arm.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Yixun Lan <dlan@gentoo.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Maxime Ripard <mripard@kernel.org>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
netdev@vger.kernel.org
Subject: Re: [PATCH 4/5] arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E board
Date: Thu, 24 Apr 2025 15:00:37 +0100 [thread overview]
Message-ID: <20250424150037.0f09a867@donnerap.manchester.arm.com> (raw)
In-Reply-To: <4ba3e7b8-e680-40fa-b159-5146a16a9415@lunn.ch>
On Thu, 24 Apr 2025 14:57:27 +0200
Andrew Lunn <andrew@lunn.ch> wrote:
Hi Andrew,
> > > Just to be clear, you tried it with "rgmii-id" and the same <300> and
> > > <400> values?
> >
> > Yes, sorry, I wasn't clear: I used rgmii-id, then experimented with those
> > values.
>
> O.K, great.
>
> I do suspect the delays are not actually in pico seconds. But without
> a data sheet, it is hard to know.
>
> if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
> if (val % 100) {
> dev_err(dev, "rx-delay must be a multiple of 100\n");
> return -EINVAL;
> }
> val /= 100;
> dev_dbg(dev, "set rx-delay to %x\n", val);
> if (val <= gmac->variant->rx_delay_max) {
> reg &= ~(gmac->variant->rx_delay_max <<
> SYSCON_ERXDC_SHIFT);
> reg |= (val << SYSCON_ERXDC_SHIFT);
>
> So the code divides by 100 and writes it to a register. But:
>
> static const struct emac_variant emac_variant_h3 = {
> .rx_delay_max = 31,
>
>
> static const struct emac_variant emac_variant_r40 = {
> .rx_delay_max = 7,
> };
>
> With the change from 7 to 31, did the range get extended by a factor
> of 4, or did the step go down by a factor of 4, and the / 100 should
> be / 25? I suppose the git history might have the answer in the commit
> message, but i'm too lazy to go look.
IIRC this picosecond mapping was somewhat made up, to match common DT
properties. The manual just says:
====================
12:10 R/W default: 0x0 ETXDC: Configure EMAC Transmit Clock Delay Chain.
====================
So the unit is really unknown, but is probably some kind of internal cycle count.
The change from 7 to 31 is purely because the bitfield grew from 3 to 5
bits. We don't know if the underlying unit changed on the way.
Those values are just copied from whatever the board vendor came up with,
we then multiply them by 100 and put them in the mainline DT. Welcome to
the world of Allwinner ;-)
And git history doesn't help, it's all already in the first commit for this
driver. I remember some discussions on the mailing list, almost 10 years
ago, but this requires even more digging ...
Cheers,
Andre
>
> I briefly tried "rgmii", and I couldn't get a lease, so I quite
> > confident it's rgmii-id, as you said. The vendor DTs just use "rgmii", but
> > they might hack the delay up another way (and I cannot be asked to look at
> > that awful code).
> >
> > Cheers,
> > Andre
next prev parent reply other threads:[~2025-04-24 14:00 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-23 14:03 [PATCH 0/5] allwinner: Add EMAC0 support to A523 variant SoC Yixun Lan
2025-04-23 14:03 ` [PATCH 1/5] dt-bindings: sram: sunxi-sram: Add A523 compatible Yixun Lan
2025-04-24 0:46 ` Andre Przywara
2025-04-23 14:03 ` [PATCH 2/5] dt-bindings: arm: sunxi: Add A523 EMAC0 compatible Yixun Lan
2025-04-24 0:48 ` Andre Przywara
2025-04-23 14:03 ` [PATCH 3/5] arm64: dts: allwinner: a523: Add EMAC0 ethernet MAC Yixun Lan
2025-04-24 0:43 ` Andre Przywara
2025-04-24 3:28 ` Yixun Lan
2025-04-24 10:28 ` Chen-Yu Tsai
2025-04-23 14:03 ` [PATCH 4/5] arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E board Yixun Lan
2025-04-23 16:58 ` Andrew Lunn
2025-04-24 0:42 ` Andre Przywara
2025-04-24 10:05 ` Yixun Lan
2025-04-24 12:05 ` Andre Przywara
2025-04-24 12:19 ` Andrew Lunn
2025-04-24 13:20 ` Andre Przywara
2025-04-24 13:32 ` Andrew Lunn
2025-04-24 12:16 ` Andrew Lunn
2025-04-24 12:41 ` Andre Przywara
2025-04-24 12:57 ` Andrew Lunn
2025-04-24 14:00 ` Andre Przywara [this message]
2025-04-24 18:38 ` Jernej Škrabec
2025-04-24 19:02 ` Andrew Lunn
2025-04-24 19:05 ` Chen-Yu Tsai
2025-04-24 19:21 ` Jernej Škrabec
2025-04-24 22:56 ` Andre Przywara
2025-04-25 2:01 ` Andrew Lunn
2025-04-25 13:22 ` Andre Przywara
2025-04-24 0:43 ` Andre Przywara
2025-04-24 3:24 ` Yixun Lan
2025-04-25 3:30 ` Chukun Pan
2025-04-25 7:46 ` Yixun Lan
2025-04-25 10:00 ` Chukun Pan
2025-04-23 14:03 ` [PATCH 5/5] arm64: dts: allwinner: t527: add EMAC0 to Avaoto-A1 board Yixun Lan
2025-04-23 16:59 ` Andrew Lunn
2025-04-24 1:17 ` Andre Przywara
2025-04-24 3:25 ` Yixun Lan
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